| T273 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/0.rom_e2e_jtag_debug_rma.3520052680 |
|
|
Aug 24 10:26:15 AM UTC 24 |
Aug 24 10:48:56 AM UTC 24 |
10900512227 ps |
| T907 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/0.rom_e2e_sigverify_always_a_nothing_b_bad_dev.765243812 |
|
|
Aug 24 10:00:51 AM UTC 24 |
Aug 24 10:49:40 AM UTC 24 |
14382295449 ps |
| T908 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/0.rom_e2e_boot_policy_valid_a_bad_b_good_rma.333992446 |
|
|
Aug 24 09:20:54 AM UTC 24 |
Aug 24 10:49:57 AM UTC 24 |
23031619010 ps |
| T909 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_clkmgr_smoketest.3205415012 |
|
|
Aug 24 10:47:33 AM UTC 24 |
Aug 24 10:50:04 AM UTC 24 |
2475359890 ps |
| T910 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_aes_smoketest.3184695913 |
|
|
Aug 24 10:46:38 AM UTC 24 |
Aug 24 10:50:26 AM UTC 24 |
3759604620 ps |
| T911 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/0.rom_e2e_sigverify_always_a_nothing_b_bad_prod_end.2383702178 |
|
|
Aug 24 10:01:43 AM UTC 24 |
Aug 24 10:50:28 AM UTC 24 |
14723975008 ps |
| T912 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_csrng_smoketest.3243112816 |
|
|
Aug 24 10:48:24 AM UTC 24 |
Aug 24 10:50:43 AM UTC 24 |
2846686880 ps |
| T913 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_aon_timer_smoketest.1843655145 |
|
|
Aug 24 10:47:03 AM UTC 24 |
Aug 24 10:51:12 AM UTC 24 |
3718274978 ps |
| T45 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_gpio_smoketest.1154167872 |
|
|
Aug 24 10:49:21 AM UTC 24 |
Aug 24 10:52:13 AM UTC 24 |
3390260971 ps |
| T914 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_bad_prod.3345453279 |
|
|
Aug 24 09:26:07 AM UTC 24 |
Aug 24 10:52:24 AM UTC 24 |
23157885796 ps |
| T915 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/0.rom_keymgr_functest.3295926644 |
|
|
Aug 24 10:46:21 AM UTC 24 |
Aug 24 10:52:52 AM UTC 24 |
4105385940 ps |
| T916 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_bad_dev.838174065 |
|
|
Aug 24 09:25:53 AM UTC 24 |
Aug 24 10:53:29 AM UTC 24 |
23347126805 ps |
| T917 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_kmac_smoketest.2755515050 |
|
|
Aug 24 10:50:05 AM UTC 24 |
Aug 24 10:53:35 AM UTC 24 |
3507072058 ps |
| T270 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_rv_timer_smoketest.3163723604 |
|
|
Aug 24 10:51:35 AM UTC 24 |
Aug 24 10:53:55 AM UTC 24 |
2592021832 ps |
| T918 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_otp_ctrl_smoketest.3153208548 |
|
|
Aug 24 10:50:29 AM UTC 24 |
Aug 24 10:54:04 AM UTC 24 |
2582033620 ps |
| T376 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_rv_plic_smoketest.2635209044 |
|
|
Aug 24 10:51:07 AM UTC 24 |
Aug 24 10:54:05 AM UTC 24 |
2964520060 ps |
| T919 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_hmac_smoketest.2516175016 |
|
|
Aug 24 10:49:22 AM UTC 24 |
Aug 24 10:54:06 AM UTC 24 |
3435153464 ps |
| T920 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_rstmgr_smoketest.1354491353 |
|
|
Aug 24 10:52:37 AM UTC 24 |
Aug 24 10:55:18 AM UTC 24 |
2707708820 ps |
| T244 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_inject_scramble_seed.2504414109 |
|
|
Aug 24 07:40:39 AM UTC 24 |
Aug 24 10:55:25 AM UTC 24 |
66864617916 ps |
| T921 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_entropy_src_smoketest.4122654479 |
|
|
Aug 24 10:48:34 AM UTC 24 |
Aug 24 10:55:26 AM UTC 24 |
4369369604 ps |
| T922 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_sram_ctrl_smoketest.2242126139 |
|
|
Aug 24 10:52:48 AM UTC 24 |
Aug 24 10:55:27 AM UTC 24 |
3147072062 ps |
| T923 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_example_rom.4292908690 |
|
|
Aug 24 10:53:55 AM UTC 24 |
Aug 24 10:55:39 AM UTC 24 |
3034687040 ps |
| T924 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/0.rom_e2e_asm_init_rma.1244203699 |
|
|
Aug 24 10:06:50 AM UTC 24 |
Aug 24 10:56:22 AM UTC 24 |
14671794252 ps |
| T925 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_uart_smoketest.2505641421 |
|
|
Aug 24 10:53:15 AM UTC 24 |
Aug 24 10:56:24 AM UTC 24 |
2642912216 ps |
| T926 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/0.rom_e2e_asm_init_prod.492700354 |
|
|
Aug 24 10:05:59 AM UTC 24 |
Aug 24 10:56:33 AM UTC 24 |
15906376410 ps |
| T427 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_pwrmgr_usbdev_smoketest.3729549465 |
|
|
Aug 24 10:50:58 AM UTC 24 |
Aug 24 10:56:36 AM UTC 24 |
5039253264 ps |
| T927 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_pwrmgr_smoketest.4157832351 |
|
|
Aug 24 10:50:57 AM UTC 24 |
Aug 24 10:57:10 AM UTC 24 |
5597150890 ps |
| T928 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_example_concurrency.3493507714 |
|
|
Aug 24 10:54:44 AM UTC 24 |
Aug 24 10:57:17 AM UTC 24 |
2552675720 ps |
| T929 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_example_flash.610206834 |
|
|
Aug 24 10:53:57 AM UTC 24 |
Aug 24 10:57:22 AM UTC 24 |
2718217800 ps |
| T930 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/0.rom_e2e_asm_init_dev.1234861454 |
|
|
Aug 24 10:05:03 AM UTC 24 |
Aug 24 10:57:38 AM UTC 24 |
15913624086 ps |
| T931 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_example_manufacturer.4132651229 |
|
|
Aug 24 10:54:18 AM UTC 24 |
Aug 24 10:57:42 AM UTC 24 |
3585424520 ps |
| T385 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sival_flash_info_access.3910114738 |
|
|
Aug 24 10:54:45 AM UTC 24 |
Aug 24 10:58:37 AM UTC 24 |
3516587366 ps |
| T28 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_sleep_pin_mio_dio_val.976314261 |
|
|
Aug 24 10:56:13 AM UTC 24 |
Aug 24 10:59:49 AM UTC 24 |
3434631095 ps |
| T29 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_sleep_pin_wake.74417946 |
|
|
Aug 24 10:56:15 AM UTC 24 |
Aug 24 11:00:00 AM UTC 24 |
4032566014 ps |
| T135 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_pattgen_ios.4154621706 |
|
|
Aug 24 10:57:12 AM UTC 24 |
Aug 24 11:00:05 AM UTC 24 |
3679125796 ps |
| T71 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_sleep_pin_retention.2466101096 |
|
|
Aug 24 10:56:17 AM UTC 24 |
Aug 24 11:00:11 AM UTC 24 |
3441017476 ps |
| T675 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_all_escalation_resets.987476531 |
|
|
Aug 24 10:54:46 AM UTC 24 |
Aug 24 11:00:30 AM UTC 24 |
5209126440 ps |
| T932 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/0.rom_e2e_asm_init_prod_end.4098992432 |
|
|
Aug 24 10:06:01 AM UTC 24 |
Aug 24 11:00:33 AM UTC 24 |
15876119576 ps |
| T933 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_bad_prod_end.3795907483 |
|
|
Aug 24 09:29:18 AM UTC 24 |
Aug 24 11:01:22 AM UTC 24 |
23293400961 ps |
| T442 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/0.rom_e2e_jtag_inject_test_unlocked0.775615472 |
|
|
Aug 24 10:26:38 AM UTC 24 |
Aug 24 11:02:41 AM UTC 24 |
32214643316 ps |
| T377 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_rstmgr_rst_cnsty_escalation.2049538188 |
|
|
Aug 24 10:56:14 AM UTC 24 |
Aug 24 11:02:48 AM UTC 24 |
5772762924 ps |
| T934 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_otbn_smoketest.1777955615 |
|
|
Aug 24 10:50:29 AM UTC 24 |
Aug 24 11:03:01 AM UTC 24 |
6324100484 ps |
| T132 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_uart_tx_rx_idx1.2782485713 |
|
|
Aug 24 10:57:11 AM UTC 24 |
Aug 24 11:04:08 AM UTC 24 |
3630113406 ps |
| T372 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_uart_tx_rx.382299711 |
|
|
Aug 24 10:57:10 AM UTC 24 |
Aug 24 11:04:15 AM UTC 24 |
3903020736 ps |
| T282 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_data_integrity_escalation.1201015906 |
|
|
Aug 24 10:56:18 AM UTC 24 |
Aug 24 11:04:59 AM UTC 24 |
5059089720 ps |
| T935 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_uart_tx_rx_idx2.2730789988 |
|
|
Aug 24 10:57:52 AM UTC 24 |
Aug 24 11:05:20 AM UTC 24 |
4406788756 ps |
| T80 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_uart_tx_rx_idx3.100748039 |
|
|
Aug 24 10:58:00 AM UTC 24 |
Aug 24 11:05:24 AM UTC 24 |
4146521826 ps |
| T55 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_spi_device_tpm.1950494928 |
|
|
Aug 24 11:01:46 AM UTC 24 |
Aug 24 11:06:01 AM UTC 24 |
3158354533 ps |
| T66 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_spi_device_pinmux_sleep_retention.4014287901 |
|
|
Aug 24 11:03:14 AM UTC 24 |
Aug 24 11:06:07 AM UTC 24 |
3702720882 ps |
| T936 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_uart_tx_rx_alt_clk_freq.3527774140 |
|
|
Aug 24 11:00:14 AM UTC 24 |
Aug 24 11:06:21 AM UTC 24 |
3405076027 ps |
| T51 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_spi_host_tx_rx.3126427578 |
|
|
Aug 24 11:03:12 AM UTC 24 |
Aug 24 11:06:30 AM UTC 24 |
3095317050 ps |
| T77 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_i2c_device_tx_rx.1144668479 |
|
|
Aug 24 11:01:03 AM UTC 24 |
Aug 24 11:08:40 AM UTC 24 |
4688319072 ps |
| T138 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_i2c_host_tx_rx_idx1.4161372282 |
|
|
Aug 24 11:00:41 AM UTC 24 |
Aug 24 11:09:08 AM UTC 24 |
4712236116 ps |
| T139 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_i2c_host_tx_rx_idx2.4044318792 |
|
|
Aug 24 11:01:03 AM UTC 24 |
Aug 24 11:09:33 AM UTC 24 |
5167076168 ps |
| T46 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_gpio.2594886000 |
|
|
Aug 24 11:04:41 AM UTC 24 |
Aug 24 11:09:47 AM UTC 24 |
3871504832 ps |
| T325 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_flash_ctrl_lc_rw_en.1161282192 |
|
|
Aug 24 11:05:52 AM UTC 24 |
Aug 24 11:10:23 AM UTC 24 |
5204750120 ps |
| T238 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_spi_device_pass_through.754227085 |
|
|
Aug 24 11:03:25 AM UTC 24 |
Aug 24 11:10:26 AM UTC 24 |
5826156370 ps |
| T383 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_flash_ctrl_idle_low_power.2951065876 |
|
|
Aug 24 11:06:49 AM UTC 24 |
Aug 24 11:11:17 AM UTC 24 |
3646500460 ps |
| T239 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_spi_device_pass_through_collision.2739826219 |
|
|
Aug 24 11:04:39 AM UTC 24 |
Aug 24 11:11:39 AM UTC 24 |
4387541905 ps |
| T937 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_sleep_pwm_pulses.1484209894 |
|
|
Aug 24 10:57:11 AM UTC 24 |
Aug 24 11:11:42 AM UTC 24 |
8901178890 ps |
| T74 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_i2c_host_tx_rx.1455976699 |
|
|
Aug 24 11:00:42 AM UTC 24 |
Aug 24 11:11:54 AM UTC 24 |
5870688120 ps |
| T373 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_uart_tx_rx_alt_clk_freq_low_speed.2899634991 |
|
|
Aug 24 11:00:41 AM UTC 24 |
Aug 24 11:12:05 AM UTC 24 |
9103906865 ps |
| T938 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_flash_ctrl_ops.1083148951 |
|
|
Aug 24 11:05:23 AM UTC 24 |
Aug 24 11:12:07 AM UTC 24 |
4057613960 ps |
| T939 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_kmac_entropy.2544343439 |
|
|
Aug 24 11:09:56 AM UTC 24 |
Aug 24 11:12:42 AM UTC 24 |
2039672322 ps |
| T370 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_flash_ctrl_ops_jitter_en.2927429677 |
|
|
Aug 24 11:05:52 AM UTC 24 |
Aug 24 11:12:50 AM UTC 24 |
4717498394 ps |
| T940 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_lc_ctrl_otp_hw_cfg0.3170845641 |
|
|
Aug 24 11:10:11 AM UTC 24 |
Aug 24 11:13:12 AM UTC 24 |
3128746600 ps |
| T941 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_bad_rma.2673040497 |
|
|
Aug 24 09:49:13 AM UTC 24 |
Aug 24 11:14:21 AM UTC 24 |
23343334754 ps |
| T631 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_lc_ctrl_rand_to_scrap.1084339486 |
|
|
Aug 24 11:12:37 AM UTC 24 |
Aug 24 11:14:28 AM UTC 24 |
3462553866 ps |
| T200 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_otp_ctrl_vendor_test_csr_access.3111091955 |
|
|
Aug 24 11:12:18 AM UTC 24 |
Aug 24 11:14:58 AM UTC 24 |
2893417694 ps |
| T250 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_uart_tx_rx_bootstrap.873824041 |
|
|
Aug 24 07:39:09 AM UTC 24 |
Aug 24 11:15:15 AM UTC 24 |
80309071784 ps |
| T942 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_otp_ctrl_ecc_error_vendor_test.2501316194 |
|
|
Aug 24 11:12:20 AM UTC 24 |
Aug 24 11:15:26 AM UTC 24 |
2847509610 ps |
| T632 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz.2369265206 |
|
|
Aug 24 11:14:54 AM UTC 24 |
Aug 24 11:16:19 AM UTC 24 |
2306632209 ps |
| T633 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_lc_ctrl_volatile_raw_unlock.3193354884 |
|
|
Aug 24 11:14:51 AM UTC 24 |
Aug 24 11:16:23 AM UTC 24 |
1875124398 ps |
| T659 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/0.rom_e2e_jtag_inject_dev.1737555623 |
|
|
Aug 24 10:32:40 AM UTC 24 |
Aug 24 11:16:37 AM UTC 24 |
31023571643 ps |
| T943 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_flash_ctrl_access.2292674388 |
|
|
Aug 24 11:06:33 AM UTC 24 |
Aug 24 11:17:33 AM UTC 24 |
5478015732 ps |
| T944 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_uart_rand_baudrate.116995054 |
|
|
Aug 24 10:59:01 AM UTC 24 |
Aug 24 11:18:23 AM UTC 24 |
8894134916 ps |
| T945 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_flash_ctrl_access_jitter_en.1953373195 |
|
|
Aug 24 11:06:33 AM UTC 24 |
Aug 24 11:18:32 AM UTC 24 |
5915535307 ps |
| T946 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_otp_ctrl_lc_signals_test_unlocked0.2313176038 |
|
|
Aug 24 11:10:55 AM UTC 24 |
Aug 24 11:18:38 AM UTC 24 |
4527699088 ps |
| T947 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_rstmgr_sw_rst.3184874502 |
|
|
Aug 24 11:16:51 AM UTC 24 |
Aug 24 11:19:48 AM UTC 24 |
2644757192 ps |
| T948 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_rstmgr_sw_req.3853471274 |
|
|
Aug 24 11:15:49 AM UTC 24 |
Aug 24 11:20:40 AM UTC 24 |
4369967368 ps |
| T108 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_alert_handler_reverse_ping_in_deep_sleep.1836453348 |
|
|
Aug 24 08:16:48 AM UTC 24 |
Aug 24 11:20:45 AM UTC 24 |
256081612496 ps |
| T949 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_flash_ctrl_clock_freqs.663467015 |
|
|
Aug 24 11:09:32 AM UTC 24 |
Aug 24 11:21:33 AM UTC 24 |
5544454778 ps |
| T950 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_pwrmgr_main_power_glitch_reset.231396320 |
|
|
Aug 24 11:18:47 AM UTC 24 |
Aug 24 11:23:23 AM UTC 24 |
4246918625 ps |
| T182 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_pwrmgr_full_aon_reset.936060616 |
|
|
Aug 24 11:17:57 AM UTC 24 |
Aug 24 11:23:55 AM UTC 24 |
8349065192 ps |
| T951 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_otp_ctrl_lc_signals_dev.2001662419 |
|
|
Aug 24 11:10:55 AM UTC 24 |
Aug 24 11:24:20 AM UTC 24 |
8459379260 ps |
| T952 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_lc_ctrl_transition.2953358883 |
|
|
Aug 24 11:12:36 AM UTC 24 |
Aug 24 11:24:22 AM UTC 24 |
12874653734 ps |
| T953 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_lc_walkthrough_prodend.526951646 |
|
|
Aug 24 11:13:36 AM UTC 24 |
Aug 24 11:24:56 AM UTC 24 |
11289574592 ps |
| T443 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/0.rom_e2e_jtag_inject_rma.3768989989 |
|
|
Aug 24 10:34:26 AM UTC 24 |
Aug 24 11:24:56 AM UTC 24 |
40168307275 ps |
| T254 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_rstmgr_cpu_info.2553795499 |
|
|
Aug 24 11:17:01 AM UTC 24 |
Aug 24 11:25:49 AM UTC 24 |
7051005250 ps |
| T954 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_otp_ctrl_lc_signals_rma.3216897910 |
|
|
Aug 24 11:12:17 AM UTC 24 |
Aug 24 11:27:05 AM UTC 24 |
8505018672 ps |
| T955 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_otp_ctrl_lc_signals_prod.1391933841 |
|
|
Aug 24 11:11:41 AM UTC 24 |
Aug 24 11:28:00 AM UTC 24 |
7340327200 ps |
| T956 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_pwrmgr_deep_sleep_por_reset.204358264 |
|
|
Aug 24 11:21:57 AM UTC 24 |
Aug 24 11:28:14 AM UTC 24 |
8422179870 ps |
| T957 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_rv_timer_irq.2374137142 |
|
|
Aug 24 11:26:12 AM UTC 24 |
Aug 24 11:29:02 AM UTC 24 |
2382598936 ps |
| T646 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_pwrmgr_sleep_disabled.2356837496 |
|
|
Aug 24 11:25:27 AM UTC 24 |
Aug 24 11:29:13 AM UTC 24 |
3181971188 ps |
| T958 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_pwrmgr_normal_sleep_por_reset.2428196798 |
|
|
Aug 24 11:23:47 AM UTC 24 |
Aug 24 11:29:20 AM UTC 24 |
6480662022 ps |
| T959 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_pwrmgr_usb_clk_disabled_when_active.3480259792 |
|
|
Aug 24 11:25:27 AM UTC 24 |
Aug 24 11:30:37 AM UTC 24 |
5664292160 ps |
| T960 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_pwrmgr_deep_sleep_power_glitch_reset.403233180 |
|
|
Aug 24 11:24:53 AM UTC 24 |
Aug 24 11:30:43 AM UTC 24 |
5545997992 ps |
| T245 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_sysrst_ctrl_inputs.169924321 |
|
|
Aug 24 11:28:04 AM UTC 24 |
Aug 24 11:31:46 AM UTC 24 |
3288054202 ps |
| T961 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/0.rom_e2e_keymgr_init_rom_ext_meas.4124465508 |
|
|
Aug 24 10:39:57 AM UTC 24 |
Aug 24 11:31:56 AM UTC 24 |
15498321896 ps |
| T962 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_pwrmgr_sysrst_ctrl_reset.1506097624 |
|
|
Aug 24 11:19:04 AM UTC 24 |
Aug 24 11:32:23 AM UTC 24 |
8789809630 ps |
| T322 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_flash_init.2058555120 |
|
|
Aug 24 11:06:50 AM UTC 24 |
Aug 24 11:32:49 AM UTC 24 |
24792233786 ps |
| T963 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/0.rom_e2e_keymgr_init_rom_ext_invalid_meas.1936591381 |
|
|
Aug 24 10:42:47 AM UTC 24 |
Aug 24 11:32:55 AM UTC 24 |
15105732896 ps |
| T964 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/0.rom_e2e_static_critical.913855108 |
|
|
Aug 24 10:37:26 AM UTC 24 |
Aug 24 11:33:35 AM UTC 24 |
17248456728 ps |
| T53 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_sysrst_ctrl_ulp_z3_wakeup.908900536 |
|
|
Aug 24 11:28:38 AM UTC 24 |
Aug 24 11:34:03 AM UTC 24 |
5892316260 ps |
| T246 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_sysrst_ctrl_outputs.316466774 |
|
|
Aug 24 11:29:46 AM UTC 24 |
Aug 24 11:34:06 AM UTC 24 |
3811587416 ps |
| T965 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_pwrmgr_all_reset_reqs.2882020998 |
|
|
Aug 24 11:19:05 AM UTC 24 |
Aug 24 11:34:14 AM UTC 24 |
11654686307 ps |
| T247 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_sysrst_ctrl_in_irq.3708329815 |
|
|
Aug 24 11:28:25 AM UTC 24 |
Aug 24 11:35:07 AM UTC 24 |
4493220182 ps |
| T384 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_aon_timer_irq.335564149 |
|
|
Aug 24 11:31:09 AM UTC 24 |
Aug 24 11:35:13 AM UTC 24 |
3292427184 ps |
| T966 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/0.rom_e2e_keymgr_init_rom_ext_no_meas.135677769 |
|
|
Aug 24 10:42:45 AM UTC 24 |
Aug 24 11:36:27 AM UTC 24 |
14784671336 ps |
| T345 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_rstmgr_alert_info.3780124073 |
|
|
Aug 24 11:16:51 AM UTC 24 |
Aug 24 11:36:32 AM UTC 24 |
12230313114 ps |
| T967 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_pwrmgr_wdog_reset.1447052091 |
|
|
Aug 24 11:32:20 AM UTC 24 |
Aug 24 11:37:21 AM UTC 24 |
4310373400 ps |
| T968 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_aon_timer_sleep_wdog_sleep_pause.662327087 |
|
|
Aug 24 11:31:09 AM UTC 24 |
Aug 24 11:37:32 AM UTC 24 |
8255505872 ps |
| T969 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_pwrmgr_deep_sleep_all_reset_reqs.518076052 |
|
|
Aug 24 11:21:13 AM UTC 24 |
Aug 24 11:38:36 AM UTC 24 |
18016320135 ps |
| T970 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_pwrmgr_normal_sleep_all_reset_reqs.1442634212 |
|
|
Aug 24 11:21:13 AM UTC 24 |
Aug 24 11:38:50 AM UTC 24 |
11661182897 ps |
| T971 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_aes_enc.4195527538 |
|
|
Aug 24 11:35:39 AM UTC 24 |
Aug 24 11:39:21 AM UTC 24 |
2887216620 ps |
| T972 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_aon_timer_wdog_lc_escalate.1333816226 |
|
|
Aug 24 11:32:47 AM UTC 24 |
Aug 24 11:39:31 AM UTC 24 |
6165096694 ps |
| T382 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_adc_ctrl_sleep_debug_cable_wakeup.2298350535 |
|
|
Aug 24 11:33:21 AM UTC 24 |
Aug 24 11:39:33 AM UTC 24 |
19594032392 ps |
| T973 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_lc_walkthrough_testunlocks.869344688 |
|
|
Aug 24 11:15:39 AM UTC 24 |
Aug 24 11:39:47 AM UTC 24 |
33880500318 ps |
| T974 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_aes_enc_jitter_en.823704712 |
|
|
Aug 24 11:36:59 AM UTC 24 |
Aug 24 11:40:17 AM UTC 24 |
3232060594 ps |
| T975 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_aes_idle.726955 |
|
|
Aug 24 11:36:59 AM UTC 24 |
Aug 24 11:40:24 AM UTC 24 |
2653466368 ps |
| T283 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_otbn_mem_scramble.232435212 |
|
|
Aug 24 11:34:43 AM UTC 24 |
Aug 24 11:40:39 AM UTC 24 |
3669331066 ps |
| T88 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_alert_test.2811185708 |
|
|
Aug 24 11:37:56 AM UTC 24 |
Aug 24 11:41:00 AM UTC 24 |
3536391104 ps |
| T976 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_aes_masking_off.546583668 |
|
|
Aug 24 11:37:44 AM UTC 24 |
Aug 24 11:42:04 AM UTC 24 |
3215445831 ps |
| T977 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_otbn_randomness.3096566248 |
|
|
Aug 24 11:33:21 AM UTC 24 |
Aug 24 11:42:44 AM UTC 24 |
5594113488 ps |
| T978 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_aon_timer_wdog_bite_reset.3301035544 |
|
|
Aug 24 11:32:10 AM UTC 24 |
Aug 24 11:43:20 AM UTC 24 |
7289094640 ps |
| T979 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_entropy_src_kat_test.2256728515 |
|
|
Aug 24 11:41:23 AM UTC 24 |
Aug 24 11:43:45 AM UTC 24 |
2001307256 ps |
| T980 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_aes_entropy.3597284254 |
|
|
Aug 24 11:41:10 AM UTC 24 |
Aug 24 11:44:05 AM UTC 24 |
2324647408 ps |
| T981 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_alert_handler_escalation.4172987822 |
|
|
Aug 24 11:39:01 AM UTC 24 |
Aug 24 11:44:18 AM UTC 24 |
5372643762 ps |
| T773 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_alert_handler_lpg_sleep_mode_alerts.3251906284 |
|
|
Aug 24 11:40:12 AM UTC 24 |
Aug 24 11:44:41 AM UTC 24 |
3678408052 ps |
| T196 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_alert_handler_entropy.305152411 |
|
|
Aug 24 11:41:09 AM UTC 24 |
Aug 24 11:44:53 AM UTC 24 |
3194223593 ps |
| T454 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_rv_core_ibex_nmi_irq.166659015 |
|
|
Aug 24 11:35:39 AM UTC 24 |
Aug 24 11:45:17 AM UTC 24 |
4278632352 ps |
| T982 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_alert_handler_ping_timeout.1809766314 |
|
|
Aug 24 11:39:14 AM UTC 24 |
Aug 24 11:45:22 AM UTC 24 |
5271370820 ps |
| T983 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_pwrmgr_random_sleep_all_reset_reqs.4030731148 |
|
|
Aug 24 11:20:12 AM UTC 24 |
Aug 24 11:46:04 AM UTC 24 |
24336656147 ps |
| T984 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_rv_core_ibex_rnd.3130079506 |
|
|
Aug 24 11:34:43 AM UTC 24 |
Aug 24 11:46:38 AM UTC 24 |
6049757448 ps |
| T985 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_entropy_src_ast_rng_req.775278674 |
|
|
Aug 24 11:45:49 AM UTC 24 |
Aug 24 11:48:11 AM UTC 24 |
3145551952 ps |
| T986 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_csrng_kat_test.3250366919 |
|
|
Aug 24 11:45:04 AM UTC 24 |
Aug 24 11:49:00 AM UTC 24 |
3527012304 ps |
| T451 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_edn_boot_mode.308790294 |
|
|
Aug 24 11:43:08 AM UTC 24 |
Aug 24 11:49:47 AM UTC 24 |
3348725090 ps |
| T248 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_sysrst_ctrl_reset.410045564 |
|
|
Aug 24 11:29:26 AM UTC 24 |
Aug 24 11:50:42 AM UTC 24 |
23014938156 ps |
| T987 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_edn_kat.758230230 |
|
|
Aug 24 11:43:44 AM UTC 24 |
Aug 24 11:51:05 AM UTC 24 |
3291522206 ps |
| T988 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_csrng_lc_hw_debug_en_test.3225219493 |
|
|
Aug 24 11:44:30 AM UTC 24 |
Aug 24 11:51:30 AM UTC 24 |
6347025576 ps |
| T989 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_csrng_fuse_en_sw_app_read_test.1888008810 |
|
|
Aug 24 11:45:18 AM UTC 24 |
Aug 24 11:52:03 AM UTC 24 |
5375595300 ps |
| T990 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_hmac_enc_jitter_en.2616918908 |
|
|
Aug 24 11:49:24 AM UTC 24 |
Aug 24 11:52:21 AM UTC 24 |
2329764728 ps |
| T991 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_hmac_enc.2070507535 |
|
|
Aug 24 11:48:35 AM UTC 24 |
Aug 24 11:52:59 AM UTC 24 |
3656219514 ps |
| T992 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_hmac_enc_idle.1709908520 |
|
|
Aug 24 11:50:11 AM UTC 24 |
Aug 24 11:53:02 AM UTC 24 |
3243201400 ps |
| T197 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_alert_handler_lpg_sleep_mode_pings.1234323285 |
|
|
Aug 24 11:40:14 AM UTC 24 |
Aug 24 11:55:02 AM UTC 24 |
11181412624 ps |
| T993 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_alert_handler_ping_ok.740334028 |
|
|
Aug 24 11:39:45 AM UTC 24 |
Aug 24 11:55:06 AM UTC 24 |
7054284840 ps |
| T994 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_hmac_oneshot.2759989589 |
|
|
Aug 24 11:51:06 AM UTC 24 |
Aug 24 11:55:11 AM UTC 24 |
3678693072 ps |
| T995 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_edn_entropy_reqs.1142928526 |
|
|
Aug 24 11:46:29 AM UTC 24 |
Aug 24 11:56:37 AM UTC 24 |
6773573440 ps |
| T996 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_alert_handler_lpg_clkoff.949820374 |
|
|
Aug 24 11:40:50 AM UTC 24 |
Aug 24 11:57:43 AM UTC 24 |
7557465144 ps |
| T453 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_edn_auto_mode.379911865 |
|
|
Aug 24 11:42:28 AM UTC 24 |
Aug 24 11:58:40 AM UTC 24 |
5647025310 ps |
| T997 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_kmac_mode_cshake.606039197 |
|
|
Aug 24 11:55:43 AM UTC 24 |
Aug 24 11:59:12 AM UTC 24 |
3028898828 ps |
| T998 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_kmac_mode_kmac.1731235011 |
|
|
Aug 24 11:55:43 AM UTC 24 |
Aug 24 11:59:22 AM UTC 24 |
2866906656 ps |
| T999 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_edn_entropy_reqs_jitter.3374126954 |
|
|
Aug 24 11:47:02 AM UTC 24 |
Aug 24 12:00:17 PM UTC 24 |
7305727188 ps |
| T1000 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_kmac_mode_kmac_jitter_en.4202509294 |
|
|
Aug 24 11:57:00 AM UTC 24 |
Aug 24 12:00:48 PM UTC 24 |
3108617718 ps |
| T430 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_kmac_app_rom.3186595270 |
|
|
Aug 24 11:58:07 AM UTC 24 |
Aug 24 12:00:52 PM UTC 24 |
3220726520 ps |
| T1001 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_alert_handler_lpg_reset_toggle.868095858 |
|
|
Aug 24 11:40:51 AM UTC 24 |
Aug 24 12:00:55 PM UTC 24 |
7893970948 ps |
| T1002 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_kmac_idle.1361531139 |
|
|
Aug 24 11:59:04 AM UTC 24 |
Aug 24 12:01:49 PM UTC 24 |
2486920540 ps |
| T1003 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_keymgr_key_derivation.960686755 |
|
|
Aug 24 11:51:55 AM UTC 24 |
Aug 24 12:02:32 PM UTC 24 |
5667358548 ps |
| T1004 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_keymgr_key_derivation_prod.3312225163 |
|
|
Aug 24 11:52:27 AM UTC 24 |
Aug 24 12:04:29 PM UTC 24 |
6034948786 ps |
| T142 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_csrng_edn_concurrency_reduced_freq.1056470704 |
|
|
Aug 24 09:05:53 AM UTC 24 |
Aug 24 12:04:48 PM UTC 24 |
81048910567 ps |
| T347 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_entropy_src_csrng.3428391475 |
|
|
Aug 24 11:45:50 AM UTC 24 |
Aug 24 12:05:51 PM UTC 24 |
7439290660 ps |
| T346 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_sensor_ctrl_status.3756532713 |
|
|
Aug 24 12:02:56 PM UTC 24 |
Aug 24 12:06:28 PM UTC 24 |
3132579731 ps |
| T431 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_rom_ctrl_integrity_check.58894484 |
|
|
Aug 24 11:59:36 AM UTC 24 |
Aug 24 12:06:44 PM UTC 24 |
7846801641 ps |
| T1005 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_keymgr_key_derivation_jitter_en.1244192934 |
|
|
Aug 24 11:52:46 AM UTC 24 |
Aug 24 12:07:35 PM UTC 24 |
8949067650 ps |
| T284 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_sram_ctrl_scrambled_access.3567522001 |
|
|
Aug 24 11:59:46 AM UTC 24 |
Aug 24 12:08:15 PM UTC 24 |
5070146040 ps |
| T285 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_sram_ctrl_scrambled_access_jitter_en.2108488509 |
|
|
Aug 24 12:00:41 PM UTC 24 |
Aug 24 12:08:18 PM UTC 24 |
4811786826 ps |
| T1006 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_sleep_sram_ret_contents_no_scramble.977636812 |
|
|
Aug 24 12:01:30 PM UTC 24 |
Aug 24 12:08:28 PM UTC 24 |
7249295896 ps |
| T168 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_sensor_ctrl_alert.14863500 |
|
|
Aug 24 12:02:13 PM UTC 24 |
Aug 24 12:08:55 PM UTC 24 |
4580389440 ps |
| T286 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_sleep_sram_ret_contents_scramble.120762311 |
|
|
Aug 24 12:01:30 PM UTC 24 |
Aug 24 12:09:24 PM UTC 24 |
8533659472 ps |
| T1007 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_hmac_multistream.3375738606 |
|
|
Aug 24 11:51:29 AM UTC 24 |
Aug 24 12:10:00 PM UTC 24 |
7969905204 ps |
| T1008 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_edn_sw_mode.1630830944 |
|
|
Aug 24 11:44:09 AM UTC 24 |
Aug 24 12:10:05 PM UTC 24 |
10604347920 ps |
| T1009 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_keymgr_sideload_kmac.2568094670 |
|
|
Aug 24 11:53:31 AM UTC 24 |
Aug 24 12:10:19 PM UTC 24 |
8851683868 ps |
| T170 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup.3673491178 |
|
|
Aug 24 12:04:53 PM UTC 24 |
Aug 24 12:10:22 PM UTC 24 |
4713997692 ps |
| T269 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_plic_sw_irq.75513455 |
|
|
Aug 24 12:07:58 PM UTC 24 |
Aug 24 12:10:36 PM UTC 24 |
2199593260 ps |
| T305 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_sram_ctrl_execution_main.1062919102 |
|
|
Aug 24 12:01:29 PM UTC 24 |
Aug 24 12:11:03 PM UTC 24 |
7123221259 ps |
| T317 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_keymgr_sideload_aes.2561218224 |
|
|
Aug 24 11:53:31 AM UTC 24 |
Aug 24 12:11:25 PM UTC 24 |
8239985990 ps |
| T1010 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_sysrst_ctrl_ec_rst_l.4003202060 |
|
|
Aug 24 11:29:46 AM UTC 24 |
Aug 24 12:12:02 PM UTC 24 |
20409037022 ps |
| T193 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_plic_all_irqs_10.1606812821 |
|
|
Aug 24 12:06:53 PM UTC 24 |
Aug 24 12:12:43 PM UTC 24 |
4180831080 ps |
| T1011 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_clkmgr_off_otbn_trans.4007299724 |
|
|
Aug 24 12:09:47 PM UTC 24 |
Aug 24 12:14:45 PM UTC 24 |
3779486100 ps |
| T1012 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_clkmgr_off_aes_trans.3227682820 |
|
|
Aug 24 12:08:55 PM UTC 24 |
Aug 24 12:15:09 PM UTC 24 |
5015934028 ps |
| T1013 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_clkmgr_off_hmac_trans.145402811 |
|
|
Aug 24 12:08:56 PM UTC 24 |
Aug 24 12:15:11 PM UTC 24 |
5907420600 ps |
| T1014 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/0.rom_e2e_self_hash.3421771704 |
|
|
Aug 24 10:46:23 AM UTC 24 |
Aug 24 12:15:25 PM UTC 24 |
26766039128 ps |
| T338 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_plic_all_irqs_20.2055953308 |
|
|
Aug 24 12:07:08 PM UTC 24 |
Aug 24 12:16:01 PM UTC 24 |
5026798680 ps |
| T1015 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_clkmgr_off_kmac_trans.3143763502 |
|
|
Aug 24 12:09:18 PM UTC 24 |
Aug 24 12:16:03 PM UTC 24 |
5471863960 ps |
| T1016 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_clkmgr_reset_frequency.3232413672 |
|
|
Aug 24 12:12:26 PM UTC 24 |
Aug 24 12:17:11 PM UTC 24 |
3056705894 ps |
| T1017 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0.898983582 |
|
|
Aug 24 12:10:31 PM UTC 24 |
Aug 24 12:17:34 PM UTC 24 |
4181299998 ps |
| T1018 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0.1874658803 |
|
|
Aug 24 12:10:50 PM UTC 24 |
Aug 24 12:17:41 PM UTC 24 |
4318867818 ps |
| T1019 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_clkmgr_external_clk_src_for_sw_slow_dev.2922649726 |
|
|
Aug 24 12:11:00 PM UTC 24 |
Aug 24 12:17:50 PM UTC 24 |
4545878720 ps |
| T1020 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_clkmgr_jitter_frequency.503477735 |
|
|
Aug 24 12:13:06 PM UTC 24 |
Aug 24 12:18:11 PM UTC 24 |
2921166544 ps |
| T224 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_flash_rma_unlocked.730824058 |
|
|
Aug 24 11:09:00 AM UTC 24 |
Aug 24 12:18:20 PM UTC 24 |
42983297130 ps |
| T1021 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_clkmgr_jitter.1588584161 |
|
|
Aug 24 12:15:09 PM UTC 24 |
Aug 24 12:18:21 PM UTC 24 |
2857972485 ps |
| T341 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_plic_all_irqs_0.2837576051 |
|
|
Aug 24 12:06:16 PM UTC 24 |
Aug 24 12:18:37 PM UTC 24 |
5874168182 ps |
| T1022 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_clkmgr_external_clk_src_for_sw_fast_dev.1756270586 |
|
|
Aug 24 12:10:50 PM UTC 24 |
Aug 24 12:18:53 PM UTC 24 |
4959345818 ps |
| T1023 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_clkmgr_external_clk_src_for_sw_fast_rma.3638042408 |
|
|
Aug 24 12:11:27 PM UTC 24 |
Aug 24 12:18:55 PM UTC 24 |
3712514698 ps |
| T1024 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_clkmgr_external_clk_src_for_sw_slow_rma.4199195264 |
|
|
Aug 24 12:11:49 PM UTC 24 |
Aug 24 12:19:23 PM UTC 24 |
4763342184 ps |
| T1025 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_clkmgr_off_peri.3594369442 |
|
|
Aug 24 12:08:55 PM UTC 24 |
Aug 24 12:20:36 PM UTC 24 |
8282988134 ps |
| T210 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_lc_ctrl_program_error.2444310562 |
|
|
Aug 24 12:16:33 PM UTC 24 |
Aug 24 12:21:33 PM UTC 24 |
5392933568 ps |
| T1026 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_clkmgr_external_clk_src_for_lc.647815209 |
|
|
Aug 24 12:10:31 PM UTC 24 |
Aug 24 12:22:08 PM UTC 24 |
9494208238 ps |
| T1027 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_clkmgr_sleep_frequency.3914011925 |
|
|
Aug 24 12:15:33 PM UTC 24 |
Aug 24 12:22:53 PM UTC 24 |
4972149172 ps |
| T1028 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_tap_straps_dev.1056973882 |
|
|
Aug 24 12:19:43 PM UTC 24 |
Aug 24 12:23:03 PM UTC 24 |
3883762651 ps |
| T125 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_pwrmgr_normal_sleep_all_wake_ups.4173889840 |
|
|
Aug 24 12:17:36 PM UTC 24 |
Aug 24 12:23:34 PM UTC 24 |
7785448576 ps |
| T388 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up.69864503 |
|
|
Aug 24 12:18:53 PM UTC 24 |
Aug 24 12:23:40 PM UTC 24 |
5461276144 ps |
| T368 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_pwrmgr_lowpower_cancel.3733703734 |
|
|
Aug 24 12:18:14 PM UTC 24 |
Aug 24 12:23:53 PM UTC 24 |
4478331200 ps |
| T410 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_rv_dm_ndm_reset_req.1089545732 |
|
|
Aug 24 12:18:53 PM UTC 24 |
Aug 24 12:24:16 PM UTC 24 |
4412350688 ps |
| T326 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_lc_walkthrough_rma.513841729 |
|
|
Aug 24 11:15:22 AM UTC 24 |
Aug 24 12:24:45 PM UTC 24 |
46186469027 ps |
| T330 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_lc_walkthrough_prod.4152402351 |
|
|
Aug 24 11:13:14 AM UTC 24 |
Aug 24 12:24:51 PM UTC 24 |
48789157596 ps |
| T1029 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_pwrmgr_sleep_wake_5_bug.731212395 |
|
|
Aug 24 12:18:50 PM UTC 24 |
Aug 24 12:25:15 PM UTC 24 |
5827382060 ps |
| T360 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_rv_dm_ndm_reset_req_when_cpu_halted.3780576421 |
|
|
Aug 24 12:19:02 PM UTC 24 |
Aug 24 12:25:24 PM UTC 24 |
4968853256 ps |
| T1030 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_otbn_ecdsa_op_irq_jitter_en.2088452657 |
|
|
Aug 24 11:34:42 AM UTC 24 |
Aug 24 12:25:30 PM UTC 24 |
18656084274 ps |
| T1031 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_rv_dm_access_after_wakeup.1056009922 |
|
|
Aug 24 12:19:24 PM UTC 24 |
Aug 24 12:25:32 PM UTC 24 |
5707234840 ps |
| T91 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_tap_straps_rma.1494933170 |
|
|
Aug 24 12:21:53 PM UTC 24 |
Aug 24 12:25:39 PM UTC 24 |
4550958554 ps |
| T418 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_rv_core_ibex_lockstep_glitch.2850154934 |
|
|
Aug 24 12:23:27 PM UTC 24 |
Aug 24 12:25:44 PM UTC 24 |
2888151200 ps |
| T628 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_rv_dm_access_after_escalation_reset.3162099930 |
|
|
Aug 24 12:19:25 PM UTC 24 |
Aug 24 12:26:20 PM UTC 24 |
4328818229 ps |
| T222 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_rv_core_ibex_icache_invalidate.540618322 |
|
|
Aug 24 12:24:07 PM UTC 24 |
Aug 24 12:26:50 PM UTC 24 |
2866014241 ps |
| T1032 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_ast_clk_outputs.4013999656 |
|
|
Aug 24 12:16:33 PM UTC 24 |
Aug 24 12:26:58 PM UTC 24 |
8667432750 ps |
| T92 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_tap_straps_testunlock0.1313299830 |
|
|
Aug 24 12:20:56 PM UTC 24 |
Aug 24 12:27:04 PM UTC 24 |
6312330743 ps |
| T256 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_rv_core_ibex_address_translation.1290917379 |
|
|
Aug 24 12:23:16 PM UTC 24 |
Aug 24 12:27:05 PM UTC 24 |
2374751808 ps |
| T1033 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_clkmgr_jitter_reduced_freq.3547534109 |
|
|
Aug 24 12:24:40 PM UTC 24 |
Aug 24 12:27:12 PM UTC 24 |
2873321224 ps |
| T1034 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_flash_ctrl_write_clear.963856324 |
|
|
Aug 24 12:24:17 PM UTC 24 |
Aug 24 12:28:03 PM UTC 24 |
3199393864 ps |
| T1035 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_otbn_ecdsa_op_irq.703529299 |
|
|
Aug 24 11:33:59 AM UTC 24 |
Aug 24 12:28:12 PM UTC 24 |
16745125486 ps |
| T1036 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_hmac_enc_jitter_en_reduced_freq.1321867003 |
|
|
Aug 24 12:26:20 PM UTC 24 |
Aug 24 12:29:11 PM UTC 24 |
2923101874 ps |
| T1037 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_aes_enc_jitter_en_reduced_freq.3695512744 |
|
|
Aug 24 12:26:14 PM UTC 24 |
Aug 24 12:29:46 PM UTC 24 |
3670311867 ps |
| T327 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_lc_walkthrough_dev.1734886826 |
|
|
Aug 24 11:13:12 AM UTC 24 |
Aug 24 12:29:47 PM UTC 24 |
47531946913 ps |
| T1038 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_kmac_mode_kmac_jitter_en_reduced_freq.1645368570 |
|
|
Aug 24 12:26:21 PM UTC 24 |
Aug 24 12:29:52 PM UTC 24 |
2902493451 ps |
| T660 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_flash_crash_alert.46126350 |
|
|
Aug 24 12:24:07 PM UTC 24 |
Aug 24 12:30:18 PM UTC 24 |
4333565160 ps |
| T65 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_jtag_csr_rw.1123499782 |
|
|
Aug 24 12:15:25 PM UTC 24 |
Aug 24 12:30:22 PM UTC 24 |
12980342408 ps |
| T242 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_jtag_mem_access.3879706742 |
|
|
Aug 24 12:15:40 PM UTC 24 |
Aug 24 12:30:50 PM UTC 24 |
13894783444 ps |
| T1039 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_flash_scrambling_smoketest.3073760215 |
|
|
Aug 24 12:28:41 PM UTC 24 |
Aug 24 12:31:28 PM UTC 24 |
2552976712 ps |
| T651 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_power_sleep_load.1387717476 |
|
|
Aug 24 12:27:53 PM UTC 24 |
Aug 24 12:31:36 PM UTC 24 |
4485379404 ps |
| T455 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq.36338402 |
|
|
Aug 24 12:26:21 PM UTC 24 |
Aug 24 12:32:58 PM UTC 24 |
5152676848 ps |
| T1040 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_flash_ctrl_ops_jitter_en_reduced_freq.3044668608 |
|
|
Aug 24 12:25:17 PM UTC 24 |
Aug 24 12:33:03 PM UTC 24 |
4690919498 ps |
| T436 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_pwrmgr_random_sleep_all_wake_ups.3897073150 |
|
|
Aug 24 12:18:16 PM UTC 24 |
Aug 24 12:34:56 PM UTC 24 |
24309001952 ps |
| T1041 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_power_idle_load.2070398284 |
|
|
Aug 24 12:27:52 PM UTC 24 |
Aug 24 12:35:39 PM UTC 24 |
5172033896 ps |
| T319 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_keymgr_sideload_otbn.2959990950 |
|
|
Aug 24 11:55:42 AM UTC 24 |
Aug 24 12:35:43 PM UTC 24 |
12232602562 ps |
| T437 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_pwrmgr_deep_sleep_all_wake_ups.683122145 |
|
|
Aug 24 12:18:13 PM UTC 24 |
Aug 24 12:37:29 PM UTC 24 |
23343809926 ps |
| T1042 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_pwrmgr_b2b_sleep_reset_req.4021897082 |
|
|
Aug 24 12:05:12 PM UTC 24 |
Aug 24 12:37:31 PM UTC 24 |
28355928612 ps |
| T1043 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_flash_ctrl_access_jitter_en_reduced_freq.3962254913 |
|
|
Aug 24 12:25:18 PM UTC 24 |
Aug 24 12:37:34 PM UTC 24 |
7748211751 ps |
| T1044 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/1.rom_volatile_raw_unlock.864460594 |
|
|
Aug 24 12:36:11 PM UTC 24 |
Aug 24 12:37:46 PM UTC 24 |
2492550722 ps |
| T1045 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_tap_straps_prod.2679565263 |
|
|
Aug 24 12:22:27 PM UTC 24 |
Aug 24 12:37:54 PM UTC 24 |
13546665574 ps |
| T190 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/1.rom_raw_unlock.2844362313 |
|
|
Aug 24 12:36:12 PM UTC 24 |
Aug 24 12:39:04 PM UTC 24 |
5051595771 ps |
| T1046 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_aes_smoketest.127217297 |
|
|
Aug 24 12:38:29 PM UTC 24 |
Aug 24 12:41:07 PM UTC 24 |
2635246568 ps |
| T1047 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_flash_ctrl_mem_protection.3416270692 |
|
|
Aug 24 12:28:40 PM UTC 24 |
Aug 24 12:41:42 PM UTC 24 |
5982393822 ps |
| T1048 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_clkmgr_smoketest.667281754 |
|
|
Aug 24 12:38:28 PM UTC 24 |
Aug 24 12:41:48 PM UTC 24 |
2887464940 ps |
| T1049 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_csrng_smoketest.2109424067 |
|
|
Aug 24 12:39:28 PM UTC 24 |
Aug 24 12:41:55 PM UTC 24 |
2943396860 ps |
| T1050 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_aon_timer_smoketest.2809223165 |
|
|
Aug 24 12:38:29 PM UTC 24 |
Aug 24 12:41:55 PM UTC 24 |
2958492600 ps |
| T1051 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_coremark.2089345432 |
|
|
Aug 24 08:38:39 AM UTC 24 |
Aug 24 12:41:59 PM UTC 24 |
71604258350 ps |
| T1052 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/1.rom_keymgr_functest.1647466157 |
|
|
Aug 24 12:38:30 PM UTC 24 |
Aug 24 12:43:39 PM UTC 24 |
5061359008 ps |
| T1053 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_csrng_edn_concurrency.921661037 |
|
|
Aug 24 11:44:42 AM UTC 24 |
Aug 24 12:45:13 PM UTC 24 |
18172256068 ps |
| T85 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_power_virus.1496247399 |
|
|
Aug 24 12:28:00 PM UTC 24 |
Aug 24 12:45:15 PM UTC 24 |
5287441172 ps |
| T1054 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_gpio_smoketest.3457212690 |
|
|
Aug 24 12:42:34 PM UTC 24 |
Aug 24 12:45:39 PM UTC 24 |
3083290918 ps |