| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | GROUP |
| 96.27 | 95.58 | 94.38 | 95.46 | 95.27 | 97.35 | 99.58 |
| T2762 | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/91.xbar_random_zero_delays.1243567191 | Aug 24 07:19:38 AM UTC 24 | Aug 24 07:20:07 AM UTC 24 | 440572356 ps | ||
| T2763 | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/86.xbar_stress_all_with_reset_error.3110323328 | Aug 24 07:13:01 AM UTC 24 | Aug 24 07:20:11 AM UTC 24 | 13792561540 ps | ||
| T2764 | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/90.xbar_stress_all_with_error.714903691 | Aug 24 07:19:17 AM UTC 24 | Aug 24 07:20:12 AM UTC 24 | 992728160 ps | ||
| T2765 | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/91.xbar_smoke_large_delays.2598342927 | Aug 24 07:19:31 AM UTC 24 | Aug 24 07:20:15 AM UTC 24 | 5242238800 ps | ||
| T2766 | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/91.xbar_same_source.1463086558 | Aug 24 07:20:02 AM UTC 24 | Aug 24 07:20:16 AM UTC 24 | 542454827 ps | ||
| T2767 | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/91.xbar_error_random.3517342617 | Aug 24 07:20:13 AM UTC 24 | Aug 24 07:20:26 AM UTC 24 | 198088738 ps | ||
| T2768 | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/90.xbar_stress_all_with_rand_reset.3861714981 | Aug 24 07:19:16 AM UTC 24 | Aug 24 07:20:30 AM UTC 24 | 287647980 ps | ||
| T2769 | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/91.xbar_error_and_unmapped_addr.2356846661 | Aug 24 07:20:26 AM UTC 24 | Aug 24 07:20:33 AM UTC 24 | 127317816 ps | ||
| T2770 | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/91.xbar_unmapped_addr.3197456679 | Aug 24 07:20:21 AM UTC 24 | Aug 24 07:20:34 AM UTC 24 | 130233103 ps | ||
| T2771 | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/91.xbar_random.699713210 | Aug 24 07:19:38 AM UTC 24 | Aug 24 07:20:36 AM UTC 24 | 2360078502 ps | ||
| T2772 | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/91.xbar_smoke_slow_rsp.3128711297 | Aug 24 07:19:34 AM UTC 24 | Aug 24 07:20:43 AM UTC 24 | 5754927953 ps | ||
| T2773 | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/90.xbar_stress_all_with_reset_error.1460775899 | Aug 24 07:19:18 AM UTC 24 | Aug 24 07:20:50 AM UTC 24 | 885642465 ps | ||
| T2774 | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/92.xbar_smoke.2258660817 | Aug 24 07:20:45 AM UTC 24 | Aug 24 07:20:51 AM UTC 24 | 53270710 ps | ||
| T2775 | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/92.xbar_smoke_zero_delays.3701240394 | Aug 24 07:20:47 AM UTC 24 | Aug 24 07:20:53 AM UTC 24 | 41252093 ps | ||
| T2776 | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/83.xbar_access_same_device_slow_rsp.1477955555 | Aug 24 07:07:15 AM UTC 24 | Aug 24 07:21:00 AM UTC 24 | 71177546267 ps | ||
| T2777 | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/91.xbar_stress_all_with_reset_error.3984731810 | Aug 24 07:20:40 AM UTC 24 | Aug 24 07:21:04 AM UTC 24 | 58668024 ps | ||
| T2778 | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/89.xbar_stress_all.1171741485 | Aug 24 07:17:45 AM UTC 24 | Aug 24 07:21:34 AM UTC 24 | 8483064914 ps | ||
| T2779 | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/92.xbar_access_same_device.2208102919 | Aug 24 07:21:14 AM UTC 24 | Aug 24 07:21:36 AM UTC 24 | 388969285 ps | ||
| T2780 | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/85.xbar_random_slow_rsp.3908114851 | Aug 24 07:10:10 AM UTC 24 | Aug 24 07:21:42 AM UTC 24 | 57789611813 ps | ||
| T2781 | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/92.xbar_smoke_slow_rsp.2310413384 | Aug 24 07:20:50 AM UTC 24 | Aug 24 07:21:42 AM UTC 24 | 4314877829 ps | ||
| T2782 | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/92.xbar_random_zero_delays.2140404899 | Aug 24 07:21:04 AM UTC 24 | Aug 24 07:21:42 AM UTC 24 | 576392840 ps | ||
| T2783 | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/89.xbar_stress_all_with_error.1774253138 | Aug 24 07:17:52 AM UTC 24 | Aug 24 07:21:43 AM UTC 24 | 4203997453 ps | ||
| T2784 | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/77.xbar_access_same_device_slow_rsp.4072508452 | Aug 24 06:57:05 AM UTC 24 | Aug 24 07:21:45 AM UTC 24 | 129647032831 ps | ||
| T2785 | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/92.xbar_smoke_large_delays.2401135308 | Aug 24 07:20:48 AM UTC 24 | Aug 24 07:21:57 AM UTC 24 | 8399787366 ps | ||
| T2786 | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/92.xbar_random.2075086688 | Aug 24 07:20:57 AM UTC 24 | Aug 24 07:22:01 AM UTC 24 | 2574928647 ps | ||
| T2787 | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/92.xbar_error_and_unmapped_addr.215007593 | Aug 24 07:21:57 AM UTC 24 | Aug 24 07:22:10 AM UTC 24 | 134121780 ps | ||
| T2788 | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/92.xbar_unmapped_addr.3079191617 | Aug 24 07:21:57 AM UTC 24 | Aug 24 07:22:11 AM UTC 24 | 128345481 ps | ||
| T2789 | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/92.xbar_same_source.373174611 | Aug 24 07:21:47 AM UTC 24 | Aug 24 07:22:15 AM UTC 24 | 1274767211 ps | ||
| T2790 | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/92.xbar_error_random.96011257 | Aug 24 07:21:51 AM UTC 24 | Aug 24 07:22:17 AM UTC 24 | 445506748 ps | ||
| T2791 | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/93.xbar_smoke.3454245483 | Aug 24 07:22:15 AM UTC 24 | Aug 24 07:22:22 AM UTC 24 | 199795620 ps | ||
| T2792 | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/92.xbar_random_slow_rsp.1266498136 | Aug 24 07:21:07 AM UTC 24 | Aug 24 07:22:26 AM UTC 24 | 6651726596 ps | ||
| T2793 | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/92.xbar_stress_all_with_error.839759549 | Aug 24 07:22:00 AM UTC 24 | Aug 24 07:22:29 AM UTC 24 | 481079708 ps | ||
| T2794 | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/93.xbar_smoke_zero_delays.355841385 | Aug 24 07:22:24 AM UTC 24 | Aug 24 07:22:30 AM UTC 24 | 48054575 ps | ||
| T2795 | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/93.xbar_random_zero_delays.1886220364 | Aug 24 07:22:36 AM UTC 24 | Aug 24 07:22:44 AM UTC 24 | 62077237 ps | ||
| T2796 | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/93.xbar_random.3233423288 | Aug 24 07:22:31 AM UTC 24 | Aug 24 07:22:49 AM UTC 24 | 252226231 ps | ||
| T2797 | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/92.xbar_stress_all.1740933422 | Aug 24 07:21:57 AM UTC 24 | Aug 24 07:22:51 AM UTC 24 | 771475120 ps | ||
| T2798 | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/93.xbar_access_same_device.3810458583 | Aug 24 07:22:44 AM UTC 24 | Aug 24 07:22:52 AM UTC 24 | 28183804 ps | ||
| T2799 | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/80.xbar_access_same_device_slow_rsp.2131347368 | Aug 24 07:02:12 AM UTC 24 | Aug 24 07:23:05 AM UTC 24 | 109832594334 ps | ||
| T2800 | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/90.xbar_access_same_device_slow_rsp.3072182178 | Aug 24 07:18:47 AM UTC 24 | Aug 24 07:23:14 AM UTC 24 | 23422584027 ps | ||
| T2801 | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/93.xbar_error_random.3268554737 | Aug 24 07:23:05 AM UTC 24 | Aug 24 07:23:15 AM UTC 24 | 108920867 ps | ||
| T2802 | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/89.xbar_random_slow_rsp.2851898445 | Aug 24 07:16:38 AM UTC 24 | Aug 24 07:23:17 AM UTC 24 | 34854943514 ps | ||
| T2803 | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/91.xbar_stress_all.3410488994 | Aug 24 07:20:27 AM UTC 24 | Aug 24 07:23:19 AM UTC 24 | 6078032160 ps | ||
| T2804 | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/93.xbar_smoke_slow_rsp.562701854 | Aug 24 07:22:29 AM UTC 24 | Aug 24 07:23:21 AM UTC 24 | 4025507867 ps | ||
| T2805 | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/90.xbar_stress_all.310662887 | Aug 24 07:19:10 AM UTC 24 | Aug 24 07:23:24 AM UTC 24 | 9486904065 ps | ||
| T2806 | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/93.xbar_same_source.569998711 | Aug 24 07:23:03 AM UTC 24 | Aug 24 07:23:25 AM UTC 24 | 939058049 ps | ||
| T2807 | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/93.xbar_smoke_large_delays.2894430621 | Aug 24 07:22:25 AM UTC 24 | Aug 24 07:23:26 AM UTC 24 | 7427621790 ps | ||
| T2808 | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/93.xbar_unmapped_addr.4271852379 | Aug 24 07:23:06 AM UTC 24 | Aug 24 07:23:37 AM UTC 24 | 1069510432 ps | ||
| T2809 | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/94.xbar_smoke.690060050 | Aug 24 07:23:35 AM UTC 24 | Aug 24 07:23:43 AM UTC 24 | 250130644 ps | ||
| T2810 | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/93.xbar_stress_all_with_reset_error.2216302935 | Aug 24 07:23:33 AM UTC 24 | Aug 24 07:23:43 AM UTC 24 | 78941586 ps | ||
| T2811 | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/94.xbar_smoke_zero_delays.54184290 | Aug 24 07:23:39 AM UTC 24 | Aug 24 07:23:45 AM UTC 24 | 47899529 ps | ||
| T2812 | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/93.xbar_error_and_unmapped_addr.2708909037 | Aug 24 07:23:20 AM UTC 24 | Aug 24 07:23:48 AM UTC 24 | 1001996809 ps | ||
| T2813 | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/91.xbar_stress_all_with_rand_reset.2114787405 | Aug 24 07:20:29 AM UTC 24 | Aug 24 07:23:49 AM UTC 24 | 3942601541 ps | ||
| T2814 | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/94.xbar_random.1585031378 | Aug 24 07:23:51 AM UTC 24 | Aug 24 07:24:15 AM UTC 24 | 913385560 ps | ||
| T2815 | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/93.xbar_random_large_delays.3286317499 | Aug 24 07:22:40 AM UTC 24 | Aug 24 07:24:20 AM UTC 24 | 11840236007 ps | ||
| T2816 | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/94.xbar_random_zero_delays.1934745414 | Aug 24 07:23:57 AM UTC 24 | Aug 24 07:24:22 AM UTC 24 | 373023601 ps | ||
| T2817 | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/88.xbar_random_slow_rsp.2804670344 | Aug 24 07:15:14 AM UTC 24 | Aug 24 07:24:25 AM UTC 24 | 46913902387 ps | ||
| T2818 | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/89.xbar_stress_all_with_rand_reset.1098352843 | Aug 24 07:17:51 AM UTC 24 | Aug 24 07:24:35 AM UTC 24 | 7355323687 ps | ||
| T2819 | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/94.xbar_error_random.1600950622 | Aug 24 07:24:33 AM UTC 24 | Aug 24 07:24:39 AM UTC 24 | 32856064 ps | ||
| T2820 | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/94.xbar_error_and_unmapped_addr.413022044 | Aug 24 07:24:38 AM UTC 24 | Aug 24 07:24:51 AM UTC 24 | 123989970 ps | ||
| T2821 | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/94.xbar_unmapped_addr.3334987281 | Aug 24 07:24:37 AM UTC 24 | Aug 24 07:24:51 AM UTC 24 | 376755649 ps | ||
| T2822 | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/94.xbar_access_same_device.2857398199 | Aug 24 07:24:02 AM UTC 24 | Aug 24 07:24:51 AM UTC 24 | 1982373870 ps | ||
| T2823 | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/94.xbar_same_source.618993762 | Aug 24 07:24:29 AM UTC 24 | Aug 24 07:24:53 AM UTC 24 | 435463591 ps | ||
| T2824 | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/94.xbar_smoke_slow_rsp.1256501120 | Aug 24 07:23:40 AM UTC 24 | Aug 24 07:24:54 AM UTC 24 | 5989293217 ps | ||
| T2825 | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/94.xbar_smoke_large_delays.1996671734 | Aug 24 07:23:39 AM UTC 24 | Aug 24 07:24:58 AM UTC 24 | 9274912507 ps | ||
| T2826 | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/91.xbar_stress_all_with_error.4001219914 | Aug 24 07:20:30 AM UTC 24 | Aug 24 07:25:00 AM UTC 24 | 12201761136 ps | ||
| T2827 | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/95.xbar_smoke_zero_delays.207493094 | Aug 24 07:25:07 AM UTC 24 | Aug 24 07:25:13 AM UTC 24 | 42166161 ps | ||
| T2828 | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/95.xbar_smoke.1363848600 | Aug 24 07:25:06 AM UTC 24 | Aug 24 07:25:15 AM UTC 24 | 237924027 ps | ||
| T2829 | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/89.xbar_random_large_delays.3904006372 | Aug 24 07:16:37 AM UTC 24 | Aug 24 07:25:24 AM UTC 24 | 62377984091 ps | ||
| T2830 | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/95.xbar_random.2007667116 | Aug 24 07:25:14 AM UTC 24 | Aug 24 07:25:27 AM UTC 24 | 367561422 ps | ||
| T2831 | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/92.xbar_stress_all_with_reset_error.3728380199 | Aug 24 07:22:11 AM UTC 24 | Aug 24 07:25:36 AM UTC 24 | 582211867 ps | ||
| T2832 | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/94.xbar_stress_all.170204441 | Aug 24 07:24:49 AM UTC 24 | Aug 24 07:25:37 AM UTC 24 | 1785373446 ps | ||
| T2833 | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/92.xbar_random_large_delays.2711780494 | Aug 24 07:21:05 AM UTC 24 | Aug 24 07:25:41 AM UTC 24 | 33999035315 ps | ||
| T2834 | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/95.xbar_random_zero_delays.3087872701 | Aug 24 07:25:28 AM UTC 24 | Aug 24 07:25:57 AM UTC 24 | 459659867 ps | ||
| T2835 | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/95.xbar_smoke_slow_rsp.3583736365 | Aug 24 07:25:13 AM UTC 24 | Aug 24 07:26:09 AM UTC 24 | 4629638345 ps | ||
| T2836 | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/95.xbar_same_source.158155375 | Aug 24 07:25:50 AM UTC 24 | Aug 24 07:26:09 AM UTC 24 | 815501642 ps | ||
| T2837 | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/94.xbar_random_large_delays.627199910 | Aug 24 07:23:58 AM UTC 24 | Aug 24 07:26:14 AM UTC 24 | 16742624591 ps | ||
| T2838 | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/93.xbar_random_slow_rsp.4264390614 | Aug 24 07:22:43 AM UTC 24 | Aug 24 07:26:16 AM UTC 24 | 18085934768 ps | ||
| T2839 | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/95.xbar_error_and_unmapped_addr.549197861 | Aug 24 07:26:11 AM UTC 24 | Aug 24 07:26:16 AM UTC 24 | 24370078 ps | ||
| T2840 | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/95.xbar_smoke_large_delays.3168486493 | Aug 24 07:25:08 AM UTC 24 | Aug 24 07:26:18 AM UTC 24 | 7918854333 ps | ||
| T2841 | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/95.xbar_unmapped_addr.1068011121 | Aug 24 07:25:56 AM UTC 24 | Aug 24 07:26:24 AM UTC 24 | 321041004 ps | ||
| T2842 | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/92.xbar_stress_all_with_rand_reset.3183738601 | Aug 24 07:21:58 AM UTC 24 | Aug 24 07:26:32 AM UTC 24 | 797702376 ps | ||
| T2843 | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/96.xbar_smoke.1560999945 | Aug 24 07:26:30 AM UTC 24 | Aug 24 07:26:35 AM UTC 24 | 40165611 ps | ||
| T2844 | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/95.xbar_access_same_device.1691173856 | Aug 24 07:25:40 AM UTC 24 | Aug 24 07:26:38 AM UTC 24 | 1156420438 ps | ||
| T2845 | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/96.xbar_smoke_zero_delays.2031110639 | Aug 24 07:26:32 AM UTC 24 | Aug 24 07:26:38 AM UTC 24 | 54119180 ps | ||
| T2846 | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/95.xbar_error_random.720261823 | Aug 24 07:25:50 AM UTC 24 | Aug 24 07:26:44 AM UTC 24 | 2304815586 ps | ||
| T2847 | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/96.xbar_random.3407301971 | Aug 24 07:26:49 AM UTC 24 | Aug 24 07:26:55 AM UTC 24 | 39677326 ps | ||
| T2848 | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/95.xbar_stress_all_with_error.1221261833 | Aug 24 07:26:29 AM UTC 24 | Aug 24 07:27:07 AM UTC 24 | 731513593 ps | ||
| T2849 | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/95.xbar_stress_all.1424824883 | Aug 24 07:26:23 AM UTC 24 | Aug 24 07:27:15 AM UTC 24 | 833025765 ps | ||
| T2850 | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/95.xbar_stress_all_with_rand_reset.4116023691 | Aug 24 07:26:24 AM UTC 24 | Aug 24 07:27:18 AM UTC 24 | 91202204 ps | ||
| T2851 | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/96.xbar_random_zero_delays.1767659279 | Aug 24 07:26:52 AM UTC 24 | Aug 24 07:27:25 AM UTC 24 | 506684537 ps | ||
| T2852 | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/96.xbar_smoke_large_delays.502657236 | Aug 24 07:26:38 AM UTC 24 | Aug 24 07:27:25 AM UTC 24 | 5573676618 ps | ||
| T2853 | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/96.xbar_access_same_device.366256326 | Aug 24 07:27:10 AM UTC 24 | Aug 24 07:27:28 AM UTC 24 | 296041119 ps | ||
| T2854 | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/84.xbar_access_same_device_slow_rsp.168811048 | Aug 24 07:08:53 AM UTC 24 | Aug 24 07:27:39 AM UTC 24 | 99119234848 ps | ||
| T2855 | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/96.xbar_smoke_slow_rsp.2779551609 | Aug 24 07:26:46 AM UTC 24 | Aug 24 07:27:40 AM UTC 24 | 4362851594 ps | ||
| T2856 | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/94.xbar_stress_all_with_reset_error.3594461599 | Aug 24 07:25:06 AM UTC 24 | Aug 24 07:27:44 AM UTC 24 | 499947739 ps | ||
| T2857 | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/96.xbar_error_and_unmapped_addr.1502714160 | Aug 24 07:27:40 AM UTC 24 | Aug 24 07:27:46 AM UTC 24 | 44932583 ps | ||
| T2858 | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/79.xbar_access_same_device_slow_rsp.3521166877 | Aug 24 07:00:21 AM UTC 24 | Aug 24 07:27:51 AM UTC 24 | 142154043698 ps | ||
| T2859 | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/96.xbar_same_source.3470988989 | Aug 24 07:27:28 AM UTC 24 | Aug 24 07:27:55 AM UTC 24 | 1127198532 ps | ||
| T2860 | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/97.xbar_smoke.1785938647 | Aug 24 07:28:00 AM UTC 24 | Aug 24 07:28:08 AM UTC 24 | 184999784 ps | ||
| T2861 | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/97.xbar_smoke_zero_delays.4090876843 | Aug 24 07:28:05 AM UTC 24 | Aug 24 07:28:11 AM UTC 24 | 42212037 ps | ||
| T2862 | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/96.xbar_unmapped_addr.1070070449 | Aug 24 07:27:40 AM UTC 24 | Aug 24 07:28:17 AM UTC 24 | 1151830691 ps | ||
| T607 | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/93.xbar_stress_all_with_error.4015046637 | Aug 24 07:23:31 AM UTC 24 | Aug 24 07:28:20 AM UTC 24 | 11799914037 ps | ||
| T2863 | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/89.xbar_access_same_device_slow_rsp.1255290973 | Aug 24 07:17:07 AM UTC 24 | Aug 24 07:28:21 AM UTC 24 | 55434671015 ps | ||
| T2864 | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/96.xbar_error_random.4270051252 | Aug 24 07:27:32 AM UTC 24 | Aug 24 07:28:29 AM UTC 24 | 2303221794 ps | ||
| T2865 | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/90.xbar_random_large_delays.3348136017 | Aug 24 07:18:26 AM UTC 24 | Aug 24 07:28:30 AM UTC 24 | 71877017566 ps | ||
| T2866 | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/94.xbar_stress_all_with_error.154782316 | Aug 24 07:25:05 AM UTC 24 | Aug 24 07:28:41 AM UTC 24 | 9249113152 ps | ||
| T2867 | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/97.xbar_random.7211592 | Aug 24 07:28:25 AM UTC 24 | Aug 24 07:28:42 AM UTC 24 | 216138587 ps | ||
| T2868 | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/95.xbar_stress_all_with_reset_error.2838480910 | Aug 24 07:26:30 AM UTC 24 | Aug 24 07:28:43 AM UTC 24 | 1920664911 ps | ||
| T2869 | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/95.xbar_access_same_device_slow_rsp.583910298 | Aug 24 07:25:43 AM UTC 24 | Aug 24 07:28:48 AM UTC 24 | 15984915319 ps | ||
| T2870 | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/91.xbar_random_slow_rsp.3334701592 | Aug 24 07:19:46 AM UTC 24 | Aug 24 07:28:51 AM UTC 24 | 45854629744 ps | ||
| T2871 | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/97.xbar_random_zero_delays.3020751030 | Aug 24 07:28:31 AM UTC 24 | Aug 24 07:28:56 AM UTC 24 | 365250279 ps | ||
| T2872 | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/88.xbar_random_large_delays.1352630680 | Aug 24 07:15:12 AM UTC 24 | Aug 24 07:29:06 AM UTC 24 | 103739245361 ps | ||
| T2873 | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/97.xbar_same_source.134407019 | Aug 24 07:28:55 AM UTC 24 | Aug 24 07:29:08 AM UTC 24 | 175413122 ps | ||
| T2874 | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/91.xbar_access_same_device_slow_rsp.1786482288 | Aug 24 07:19:55 AM UTC 24 | Aug 24 07:29:11 AM UTC 24 | 49266549913 ps | ||
| T2875 | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/97.xbar_unmapped_addr.100196430 | Aug 24 07:28:57 AM UTC 24 | Aug 24 07:29:12 AM UTC 24 | 413748605 ps | ||
| T2876 | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/97.xbar_smoke_large_delays.992217636 | Aug 24 07:28:09 AM UTC 24 | Aug 24 07:29:20 AM UTC 24 | 8147685098 ps | ||
| T2877 | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/98.xbar_smoke_zero_delays.2234290292 | Aug 24 07:29:26 AM UTC 24 | Aug 24 07:29:32 AM UTC 24 | 45918562 ps | ||
| T2878 | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/97.xbar_access_same_device.1603775724 | Aug 24 07:28:42 AM UTC 24 | Aug 24 07:29:34 AM UTC 24 | 970342576 ps | ||
| T2879 | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/98.xbar_smoke.37938922 | Aug 24 07:29:25 AM UTC 24 | Aug 24 07:29:34 AM UTC 24 | 206003197 ps | ||
| T2880 | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/97.xbar_error_random.280406490 | Aug 24 07:28:57 AM UTC 24 | Aug 24 07:29:37 AM UTC 24 | 1682546559 ps | ||
| T2881 | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/97.xbar_error_and_unmapped_addr.231257596 | Aug 24 07:29:03 AM UTC 24 | Aug 24 07:29:38 AM UTC 24 | 1346247214 ps | ||
| T2882 | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/97.xbar_smoke_slow_rsp.247122838 | Aug 24 07:28:22 AM UTC 24 | Aug 24 07:29:38 AM UTC 24 | 6369691094 ps | ||
| T2883 | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/98.xbar_random_zero_delays.1966000817 | Aug 24 07:29:48 AM UTC 24 | Aug 24 07:30:00 AM UTC 24 | 150885775 ps | ||
| T2884 | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/94.xbar_stress_all_with_rand_reset.3921228069 | Aug 24 07:24:53 AM UTC 24 | Aug 24 07:30:07 AM UTC 24 | 3296269402 ps | ||
| T2885 | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/97.xbar_stress_all.3708115277 | Aug 24 07:29:05 AM UTC 24 | Aug 24 07:30:13 AM UTC 24 | 2073853631 ps | ||
| T2886 | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/95.xbar_random_slow_rsp.1693879562 | Aug 24 07:25:39 AM UTC 24 | Aug 24 07:30:27 AM UTC 24 | 23365482679 ps | ||
| T2887 | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/98.xbar_error_random.2159130740 | Aug 24 07:30:27 AM UTC 24 | Aug 24 07:30:38 AM UTC 24 | 126241945 ps | ||
| T2888 | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/98.xbar_random.370115219 | Aug 24 07:29:48 AM UTC 24 | Aug 24 07:30:40 AM UTC 24 | 2118429677 ps | ||
| T2889 | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/98.xbar_smoke_large_delays.2042323220 | Aug 24 07:29:34 AM UTC 24 | Aug 24 07:30:49 AM UTC 24 | 9499397040 ps | ||
| T2890 | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/98.xbar_access_same_device.1491448536 | Aug 24 07:29:52 AM UTC 24 | Aug 24 07:30:52 AM UTC 24 | 2133186434 ps | ||
| T2891 | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/98.xbar_unmapped_addr.3233734801 | Aug 24 07:30:42 AM UTC 24 | Aug 24 07:30:59 AM UTC 24 | 493735147 ps | ||
| T2892 | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/98.xbar_smoke_slow_rsp.3448752876 | Aug 24 07:29:46 AM UTC 24 | Aug 24 07:31:01 AM UTC 24 | 6381038418 ps | ||
| T2893 | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/96.xbar_stress_all_with_error.4079858077 | Aug 24 07:27:54 AM UTC 24 | Aug 24 07:31:09 AM UTC 24 | 8524107303 ps | ||
| T2894 | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/98.xbar_error_and_unmapped_addr.3266617526 | Aug 24 07:30:53 AM UTC 24 | Aug 24 07:31:11 AM UTC 24 | 625554740 ps | ||
| T2895 | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/97.xbar_stress_all_with_rand_reset.1031307844 | Aug 24 07:29:11 AM UTC 24 | Aug 24 07:31:12 AM UTC 24 | 251739059 ps | ||
| T2896 | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/97.xbar_stress_all_with_reset_error.2275936171 | Aug 24 07:29:23 AM UTC 24 | Aug 24 07:31:12 AM UTC 24 | 403605414 ps | ||
| T2897 | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/98.xbar_same_source.1019631687 | Aug 24 07:30:21 AM UTC 24 | Aug 24 07:31:19 AM UTC 24 | 2592745009 ps | ||
| T2898 | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/99.xbar_smoke.389428392 | Aug 24 07:31:16 AM UTC 24 | Aug 24 07:31:22 AM UTC 24 | 48010343 ps | ||
| T2899 | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/99.xbar_smoke_zero_delays.2945256888 | Aug 24 07:31:23 AM UTC 24 | Aug 24 07:31:28 AM UTC 24 | 37709120 ps | ||
| T2900 | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/97.xbar_access_same_device_slow_rsp.1158701229 | Aug 24 07:28:43 AM UTC 24 | Aug 24 07:31:33 AM UTC 24 | 14782441467 ps | ||
| T2901 | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/99.xbar_random.2036297010 | Aug 24 07:31:26 AM UTC 24 | Aug 24 07:31:46 AM UTC 24 | 642221904 ps | ||
| T2902 | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/99.xbar_random_zero_delays.1596007302 | Aug 24 07:31:33 AM UTC 24 | Aug 24 07:31:55 AM UTC 24 | 330593865 ps | ||
| T2903 | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/99.xbar_access_same_device.2527069604 | Aug 24 07:31:47 AM UTC 24 | Aug 24 07:32:11 AM UTC 24 | 450614585 ps | ||
| T2904 | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/93.xbar_stress_all_with_rand_reset.1605467906 | Aug 24 07:23:29 AM UTC 24 | Aug 24 07:32:12 AM UTC 24 | 4826265711 ps | ||
| T2905 | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/99.xbar_smoke_slow_rsp.3434503781 | Aug 24 07:31:26 AM UTC 24 | Aug 24 07:32:32 AM UTC 24 | 5563368211 ps | ||
| T2906 | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/99.xbar_same_source.2310052888 | Aug 24 07:32:09 AM UTC 24 | Aug 24 07:32:41 AM UTC 24 | 1339736272 ps | ||
| T2907 | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/99.xbar_smoke_large_delays.2547933868 | Aug 24 07:31:25 AM UTC 24 | Aug 24 07:32:43 AM UTC 24 | 9248329799 ps | ||
| T2908 | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/94.xbar_random_slow_rsp.551819666 | Aug 24 07:23:59 AM UTC 24 | Aug 24 07:32:50 AM UTC 24 | 45850686387 ps | ||
| T2909 | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/99.xbar_error_random.1576475118 | Aug 24 07:32:25 AM UTC 24 | Aug 24 07:32:53 AM UTC 24 | 524645918 ps | ||
| T2910 | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/96.xbar_access_same_device_slow_rsp.2737019809 | Aug 24 07:27:22 AM UTC 24 | Aug 24 07:32:58 AM UTC 24 | 27372628422 ps | ||
| T2911 | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/96.xbar_stress_all_with_reset_error.3269296812 | Aug 24 07:27:59 AM UTC 24 | Aug 24 07:32:59 AM UTC 24 | 8819900435 ps | ||
| T2912 | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/99.xbar_error_and_unmapped_addr.1909807241 | Aug 24 07:32:46 AM UTC 24 | Aug 24 07:33:11 AM UTC 24 | 279065314 ps | ||
| T2913 | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/99.xbar_unmapped_addr.1719007761 | Aug 24 07:32:26 AM UTC 24 | Aug 24 07:33:12 AM UTC 24 | 1416187157 ps | ||
| T2914 | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/91.xbar_random_large_delays.608373029 | Aug 24 07:19:46 AM UTC 24 | Aug 24 07:33:15 AM UTC 24 | 96476500261 ps | ||
| T2915 | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/97.xbar_stress_all_with_error.3241379317 | Aug 24 07:29:20 AM UTC 24 | Aug 24 07:33:17 AM UTC 24 | 10440995720 ps | ||
| T2916 | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/99.xbar_stress_all_with_error.2156134804 | Aug 24 07:33:04 AM UTC 24 | Aug 24 07:33:58 AM UTC 24 | 2606765939 ps | ||
| T2917 | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/88.xbar_access_same_device_slow_rsp.1773456031 | Aug 24 07:15:21 AM UTC 24 | Aug 24 07:34:00 AM UTC 24 | 98409919744 ps | ||
| T2918 | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/96.xbar_stress_all_with_rand_reset.3817585009 | Aug 24 07:27:54 AM UTC 24 | Aug 24 07:34:01 AM UTC 24 | 2554077813 ps | ||
| T2919 | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/98.xbar_stress_all_with_error.665121790 | Aug 24 07:31:06 AM UTC 24 | Aug 24 07:34:20 AM UTC 24 | 7239917138 ps | ||
| T2920 | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/98.xbar_stress_all.3659188077 | Aug 24 07:30:55 AM UTC 24 | Aug 24 07:34:30 AM UTC 24 | 7133480489 ps | ||
| T2921 | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/96.xbar_random_slow_rsp.2885068723 | Aug 24 07:26:57 AM UTC 24 | Aug 24 07:34:32 AM UTC 24 | 38945950340 ps | ||
| T2922 | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/99.xbar_stress_all_with_reset_error.3488845891 | Aug 24 07:33:07 AM UTC 24 | Aug 24 07:34:55 AM UTC 24 | 1450228176 ps | ||
| T2923 | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/96.xbar_stress_all.2961499098 | Aug 24 07:27:42 AM UTC 24 | Aug 24 07:35:48 AM UTC 24 | 18325304949 ps | ||
| T2924 | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/99.xbar_stress_all.2133715609 | Aug 24 07:32:55 AM UTC 24 | Aug 24 07:36:41 AM UTC 24 | 7941870992 ps | ||
| T2925 | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/98.xbar_stress_all_with_rand_reset.561742029 | Aug 24 07:31:04 AM UTC 24 | Aug 24 07:37:16 AM UTC 24 | 9716687388 ps | ||
| T2926 | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/98.xbar_random_large_delays.1982057831 | Aug 24 07:29:51 AM UTC 24 | Aug 24 07:37:16 AM UTC 24 | 53081759975 ps | ||
| T2927 | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/98.xbar_stress_all_with_reset_error.1639035069 | Aug 24 07:31:15 AM UTC 24 | Aug 24 07:37:21 AM UTC 24 | 4437655879 ps | ||
| T2928 | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/99.xbar_random_large_delays.2892674501 | Aug 24 07:31:36 AM UTC 24 | Aug 24 07:37:48 AM UTC 24 | 44764411062 ps | ||
| T2929 | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/97.xbar_random_slow_rsp.3363694939 | Aug 24 07:28:35 AM UTC 24 | Aug 24 07:38:30 AM UTC 24 | 47980742582 ps | ||
| T2930 | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/95.xbar_random_large_delays.3166042458 | Aug 24 07:25:30 AM UTC 24 | Aug 24 07:39:51 AM UTC 24 | 100073598343 ps | ||
| T2931 | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/99.xbar_stress_all_with_rand_reset.3815215042 | Aug 24 07:32:58 AM UTC 24 | Aug 24 07:39:56 AM UTC 24 | 7783925327 ps | ||
| T2932 | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/87.xbar_access_same_device_slow_rsp.2687885330 | Aug 24 07:13:57 AM UTC 24 | Aug 24 07:39:57 AM UTC 24 | 129826529633 ps | ||
| T2933 | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/99.xbar_access_same_device_slow_rsp.2579005951 | Aug 24 07:32:01 AM UTC 24 | Aug 24 07:40:05 AM UTC 24 | 40602527189 ps | ||
| T2934 | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/96.xbar_random_large_delays.949210329 | Aug 24 07:26:52 AM UTC 24 | Aug 24 07:41:09 AM UTC 24 | 99410829304 ps | ||
| T2935 | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/97.xbar_random_large_delays.1517171676 | Aug 24 07:28:34 AM UTC 24 | Aug 24 07:41:56 AM UTC 24 | 100016469936 ps | ||
| T2936 | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/98.xbar_random_slow_rsp.372018175 | Aug 24 07:29:52 AM UTC 24 | Aug 24 07:42:22 AM UTC 24 | 60724301301 ps | ||
| T2937 | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/93.xbar_access_same_device_slow_rsp.109226107 | Aug 24 07:22:58 AM UTC 24 | Aug 24 07:42:37 AM UTC 24 | 97447853916 ps | ||
| T2938 | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/99.xbar_random_slow_rsp.1711308583 | Aug 24 07:31:42 AM UTC 24 | Aug 24 07:43:10 AM UTC 24 | 55775143029 ps | ||
| T2939 | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/94.xbar_access_same_device_slow_rsp.611710888 | Aug 24 07:24:03 AM UTC 24 | Aug 24 07:45:41 AM UTC 24 | 105790366380 ps | ||
| T2940 | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/92.xbar_access_same_device_slow_rsp.2090010971 | Aug 24 07:21:19 AM UTC 24 | Aug 24 07:46:29 AM UTC 24 | 128717555310 ps | ||
| T2941 | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/98.xbar_access_same_device_slow_rsp.3669960974 | Aug 24 07:30:14 AM UTC 24 | Aug 24 07:56:14 AM UTC 24 | 132271283142 ps | ||
| T24 | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/pad_ctrl_test_mode/0.chip_padctrl_attributes.364763044 | Aug 24 07:33:12 AM UTC 24 | Aug 24 07:36:17 AM UTC 24 | 4483555178 ps | ||
| T25 | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/pad_ctrl_test_mode/5.chip_padctrl_attributes.1093319605 | Aug 24 07:33:30 AM UTC 24 | Aug 24 07:36:18 AM UTC 24 | 5587269352 ps | ||
| T26 | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/pad_ctrl_test_mode/1.chip_padctrl_attributes.2952282386 | Aug 24 07:33:13 AM UTC 24 | Aug 24 07:36:20 AM UTC 24 | 4542958086 ps | ||
| T230 | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/pad_ctrl_test_mode/4.chip_padctrl_attributes.3498004107 | Aug 24 07:33:28 AM UTC 24 | Aug 24 07:36:21 AM UTC 24 | 5168816928 ps | ||
| T231 | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/pad_ctrl_test_mode/6.chip_padctrl_attributes.3418485337 | Aug 24 07:34:12 AM UTC 24 | Aug 24 07:36:34 AM UTC 24 | 4821886620 ps | ||
| T237 | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/pad_ctrl_test_mode/2.chip_padctrl_attributes.288283935 | Aug 24 07:33:25 AM UTC 24 | Aug 24 07:36:38 AM UTC 24 | 4741959592 ps | ||
| T232 | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/pad_ctrl_test_mode/8.chip_padctrl_attributes.1581388133 | Aug 24 07:34:16 AM UTC 24 | Aug 24 07:36:53 AM UTC 24 | 4957753289 ps | ||
| T233 | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/pad_ctrl_test_mode/7.chip_padctrl_attributes.542264375 | Aug 24 07:34:15 AM UTC 24 | Aug 24 07:37:16 AM UTC 24 | 5576816220 ps | ||
| T234 | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/pad_ctrl_test_mode/3.chip_padctrl_attributes.3607440041 | Aug 24 07:33:26 AM UTC 24 | Aug 24 07:37:51 AM UTC 24 | 6109230384 ps | ||
| T235 | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/pad_ctrl_test_mode/9.chip_padctrl_attributes.1651310400 | Aug 24 07:34:35 AM UTC 24 | Aug 24 07:38:03 AM UTC 24 | 4475184248 ps |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_sleep_pin_mio_dio_val.2010941863 |
| Short name | T8 |
| Test name | |
| Test status | |
| Simulation time | 3211109561 ps |
| CPU time | 190.19 seconds |
| Started | Aug 24 07:37:34 AM UTC 24 |
| Finished | Aug 24 07:40:47 AM UTC 24 |
| Peak memory | 624648 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/default/simv +use_otp_image=OtpTypeLcStProd +sw_build_device=sim_dv +sw_i mages=sleep_pin_mio_dio_val_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2010941863 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sleep_pin_ mio_dio_val_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vc s/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_sleep_pin_mio_dio_val.2010941863 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/0.chip_sw_sleep_pin_mio_dio_val/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_jtag_csr_rw.2371593039 |
| Short name | T64 |
| Test name | |
| Test status | |
| Simulation time | 20559306638 ps |
| CPU time | 1458 seconds |
| Started | Aug 24 08:53:50 AM UTC 24 |
| Finished | Aug 24 09:18:24 AM UTC 24 |
| Peak memory | 627276 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/default/simv +en_scb=0 +csr_rw +create_jtag_riscv_map=1 +stub_cpu=1 +cdc_ instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=237159 3039 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_jtag_csr_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_jtag_csr_rw.2371593039 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/0.chip_jtag_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_plic_all_irqs_0.1969554727 |
| Short name | T340 |
| Test name | |
| Test status | |
| Simulation time | 6042637210 ps |
| CPU time | 829.92 seconds |
| Started | Aug 24 08:41:26 AM UTC 24 |
| Finished | Aug 24 08:55:25 AM UTC 24 |
| Peak memory | 624576 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=plic_all_irqs_test_0:1:ne w_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1969554727 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.ch ip_plic_all_irqs_0.1969554727 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/0.chip_plic_all_irqs_0/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/0.xbar_access_same_device_slow_rsp.27533580 |
| Short name | T468 |
| Test name | |
| Test status | |
| Simulation time | 130208095991 ps |
| CPU time | 1564.3 seconds |
| Started | Aug 24 03:47:02 AM UTC 24 |
| Finished | Aug 24 04:13:22 AM UTC 24 |
| Peak memory | 597820 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=27533580 -assert nopostproc +UVM_TES TNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_ regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.xbar_access_same_device_slow_rsp.27533580 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/0.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/0.xbar_random.2419486570 |
| Short name | T104 |
| Test name | |
| Test status | |
| Simulation time | 470545680 ps |
| CPU time | 14.57 seconds |
| Started | Aug 24 03:45:56 AM UTC 24 |
| Finished | Aug 24 03:46:12 AM UTC 24 |
| Peak memory | 597688 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2419486570 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.xbar_random.2419486570 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/0.xbar_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_all_escalation_resets.2221822962 |
| Short name | T48 |
| Test name | |
| Test status | |
| Simulation time | 4655796680 ps |
| CPU time | 434.16 seconds |
| Started | Aug 24 07:37:49 AM UTC 24 |
| Finished | Aug 24 07:45:09 AM UTC 24 |
| Peak memory | 675324 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv + sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2221822962 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_es calation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_all_escalation_resets.2221822962 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/0.chip_sw_all_escalation_resets/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/pad_ctrl_test_mode/0.chip_padctrl_attributes.364763044 |
| Short name | T24 |
| Test name | |
| Test status | |
| Simulation time | 4483555178 ps |
| CPU time | 182.4 seconds |
| Started | Aug 24 07:33:12 AM UTC 24 |
| Finished | Aug 24 07:36:17 AM UTC 24 |
| Peak memory | 669940 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/pad_ctrl_test_mode/simv +use_otp_image=OtpTypeLcStProd +stub_cpu=1 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3647630 44 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_padctrl_attributes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/pad_ctrl_test_mode.vdb -cm_log /dev/null -cm_name 0.chip_p adctrl_attributes.364763044 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/0.chip_padctrl_attributes/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/11.xbar_access_same_device_slow_rsp.3800875793 |
| Short name | T807 |
| Test name | |
| Test status | |
| Simulation time | 116778780142 ps |
| CPU time | 1355.7 seconds |
| Started | Aug 24 04:33:58 AM UTC 24 |
| Finished | Aug 24 04:56:47 AM UTC 24 |
| Peak memory | 597896 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3800875793 -assert nopostproc +UVM_T ESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.xbar_access_same_device_slow_rsp.3800875793 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/11.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/0.chip_csr_hw_reset.766074429 |
| Short name | T176 |
| Test name | |
| Test status | |
| Simulation time | 4527769922 ps |
| CPU time | 181.68 seconds |
| Started | Aug 24 03:48:06 AM UTC 24 |
| Finished | Aug 24 03:51:11 AM UTC 24 |
| Peak memory | 682484 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +stub_cpu=1 +cdc_instrumentati on_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=766074429 -assert n opostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.chip_csr_hw_reset.766074429 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/0.chip_csr_hw_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_keymgr_sideload_aes.3529009600 |
| Short name | T312 |
| Test name | |
| Test status | |
| Simulation time | 7041120548 ps |
| CPU time | 737.42 seconds |
| Started | Aug 24 08:30:24 AM UTC 24 |
| Finished | Aug 24 08:42:51 AM UTC 24 |
| Peak memory | 627256 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=20_000_000 +sw_build_device=sim_dv +sw_i mages=keymgr_sideload_aes_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3529009600 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_keymgr_sidel oad_aes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_keymgr_sideload_aes.3529009600 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/0.chip_sw_keymgr_sideload_aes/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/1.xbar_stress_all.780769328 |
| Short name | T542 |
| Test name | |
| Test status | |
| Simulation time | 11008298801 ps |
| CPU time | 320.45 seconds |
| Started | Aug 24 03:53:34 AM UTC 24 |
| Finished | Aug 24 03:58:59 AM UTC 24 |
| Peak memory | 597820 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=780769328 -assert nopostproc +UVM_TESTNAME =xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.xbar_stress_all.780769328 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/1.xbar_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_alert_test.3736550748 |
| Short name | T87 |
| Test name | |
| Test status | |
| Simulation time | 3824934094 ps |
| CPU time | 270.31 seconds |
| Started | Aug 24 08:14:24 AM UTC 24 |
| Finished | Aug 24 08:18:58 AM UTC 24 |
| Peak memory | 624572 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=alert_test:1:new_rules,te st_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_rand om_seed=3736550748 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert - cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_aler t_test.3736550748 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/0.chip_sw_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/3.xbar_access_same_device_slow_rsp.410850659 |
| Short name | T803 |
| Test name | |
| Test status | |
| Simulation time | 101864865139 ps |
| CPU time | 1191.26 seconds |
| Started | Aug 24 04:01:52 AM UTC 24 |
| Finished | Aug 24 04:21:56 AM UTC 24 |
| Peak memory | 598136 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=410850659 -assert nopostproc +UVM_TE STNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os _regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.xbar_access_same_device_slow_rsp.410850659 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/3.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_lc_walkthrough_prodend.2840566215 |
| Short name | T205 |
| Test name | |
| Test status | |
| Simulation time | 9190073053 ps |
| CPU time | 614.64 seconds |
| Started | Aug 24 07:53:48 AM UTC 24 |
| Finished | Aug 24 08:04:10 AM UTC 24 |
| Peak memory | 641164 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/default/simv +flash_program_latency=5 +use_otp_image=OtpTypeLcStRaw +dest _dec_state=DecLcStProdEnd +sw_build_device=sim_dv +sw_images=lc_walkthrough_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2840566215 -assert nopostproc +UVM_TESTNAME =chip_base_test +UVM_TEST_SEQ=chip_sw_lc_walkthrough_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_lc_walkthrough_prodend.2840566215 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/0.chip_sw_lc_walkthrough_prodend/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_plic_all_irqs_20.2571536318 |
| Short name | T333 |
| Test name | |
| Test status | |
| Simulation time | 5478890712 ps |
| CPU time | 536.97 seconds |
| Started | Aug 24 08:43:17 AM UTC 24 |
| Finished | Aug 24 08:52:20 AM UTC 24 |
| Peak memory | 624884 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=plic_all_irqs_test_20:1:n ew_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc l +ntb_random_seed=2571536318 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.c hip_plic_all_irqs_20.2571536318 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/0.chip_plic_all_irqs_20/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/0.xbar_stress_all_with_error.1838043288 |
| Short name | T456 |
| Test name | |
| Test status | |
| Simulation time | 2102938518 ps |
| CPU time | 114.7 seconds |
| Started | Aug 24 03:48:00 AM UTC 24 |
| Finished | Aug 24 03:49:57 AM UTC 24 |
| Peak memory | 597872 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1838043288 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.xbar_stress_all_with_error.1838043288 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/0.xbar_stress_all_with_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/15.xbar_access_same_device_slow_rsp.59893241 |
| Short name | T792 |
| Test name | |
| Test status | |
| Simulation time | 160840015194 ps |
| CPU time | 1830.19 seconds |
| Started | Aug 24 04:50:18 AM UTC 24 |
| Finished | Aug 24 05:21:05 AM UTC 24 |
| Peak memory | 598992 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=59893241 -assert nopostproc +UVM_TES TNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_ regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.xbar_access_same_device_slow_rsp.59893241 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/15.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_power_virus.3966031085 |
| Short name | T15 |
| Test name | |
| Test status | |
| Simulation time | 5627649208 ps |
| CPU time | 1086.01 seconds |
| Started | Aug 24 09:06:41 AM UTC 24 |
| Finished | Aug 24 09:25:00 AM UTC 24 |
| Peak memory | 641636 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/default/simv +rng_srate_value_min=15 +rng_srate_value_max=20 +sw_test_tim eout_ns=400_000_000 +use_otp_image=OtpTypeCustom +accelerate_cold_power_up_time=3 +accelerate_regulators_power_up_time=2 +sw_build_device=sim_dv + sw_images=power_virus_systemtest:1:new_rules,power_virus_systemtest_otp_img_rma:4,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3966031085 -assert nopostproc +UVM_TESTNAME=chip_base_ test +UVM_TEST_SEQ=chip_sw_power_virus_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_2 2/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_power_virus.3966031085 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/0.chip_sw_power_virus/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_sleep_pin_retention.4050725107 |
| Short name | T7 |
| Test name | |
| Test status | |
| Simulation time | 4464802620 ps |
| CPU time | 275.79 seconds |
| Started | Aug 24 07:39:17 AM UTC 24 |
| Finished | Aug 24 07:43:56 AM UTC 24 |
| Peak memory | 625128 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=sleep_pin_retention_test: 1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim .tcl +ntb_random_seed=4050725107 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sleep_pin_retention_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev /null -cm_name 0.chip_sw_sleep_pin_retention.4050725107 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/0.chip_sw_sleep_pin_retention/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_rv_core_ibex_address_translation.3530762746 |
| Short name | T221 |
| Test name | |
| Test status | |
| Simulation time | 3214830234 ps |
| CPU time | 192.08 seconds |
| Started | Aug 24 09:02:10 AM UTC 24 |
| Finished | Aug 24 09:05:25 AM UTC 24 |
| Peak memory | 624816 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=7_000_000 +sw_build_device=sim_dv +sw_im ages=rv_core_ibex_address_translation_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3530762746 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_ base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover age/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_rv_core_ibex_address_translation.3530762746 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/0.chip_sw_rv_core_ibex_address_translation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/7.xbar_access_same_device.264253669 |
| Short name | T466 |
| Test name | |
| Test status | |
| Simulation time | 3255568204 ps |
| CPU time | 102.66 seconds |
| Started | Aug 24 04:19:43 AM UTC 24 |
| Finished | Aug 24 04:21:27 AM UTC 24 |
| Peak memory | 597832 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=264253669 -assert nopostproc +UVM_TESTNAME =xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.xbar_access_same_device.264253669 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/7.xbar_access_same_device/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_edn_auto_mode.2627141188 |
| Short name | T158 |
| Test name | |
| Test status | |
| Simulation time | 4326599580 ps |
| CPU time | 647.84 seconds |
| Started | Aug 24 08:18:48 AM UTC 24 |
| Finished | Aug 24 08:29:43 AM UTC 24 |
| Peak memory | 626744 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=18_000_000 +rng_srate_value=5 +accelerat e_cold_power_up_time=3 +accelerate_regulators_power_up_time=2 +sw_build_device=sim_dv +sw_images=edn_auto_mode:1:new_rules,test_rom:0 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2627141188 -a ssert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re po/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_edn_auto_mode.2627141188 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/0.chip_sw_edn_auto_mode/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup.401036783 |
| Short name | T165 |
| Test name | |
| Test status | |
| Simulation time | 5437531532 ps |
| CPU time | 301.21 seconds |
| Started | Aug 24 08:38:21 AM UTC 24 |
| Finished | Aug 24 08:43:26 AM UTC 24 |
| Peak memory | 624636 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=8_000_000 +sw_build_device=sim_dv +sw_im ages=sensor_ctrl_wakeup_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo rkspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=401036783 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup.401036783 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/0.chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/6.xbar_access_same_device_slow_rsp.1244399208 |
| Short name | T816 |
| Test name | |
| Test status | |
| Simulation time | 34684199221 ps |
| CPU time | 430.61 seconds |
| Started | Aug 24 04:15:06 AM UTC 24 |
| Finished | Aug 24 04:22:22 AM UTC 24 |
| Peak memory | 597820 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1244399208 -assert nopostproc +UVM_T ESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.xbar_access_same_device_slow_rsp.1244399208 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/6.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/17.xbar_access_same_device_slow_rsp.48213435 |
| Short name | T511 |
| Test name | |
| Test status | |
| Simulation time | 103807552623 ps |
| CPU time | 1214.62 seconds |
| Started | Aug 24 04:58:44 AM UTC 24 |
| Finished | Aug 24 05:19:11 AM UTC 24 |
| Peak memory | 597888 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=48213435 -assert nopostproc +UVM_TES TNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_ regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.xbar_access_same_device_slow_rsp.48213435 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/17.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/1.chip_tl_errors.3738959388 |
| Short name | T547 |
| Test name | |
| Test status | |
| Simulation time | 3933094224 ps |
| CPU time | 166.77 seconds |
| Started | Aug 24 03:50:13 AM UTC 24 |
| Finished | Aug 24 03:53:02 AM UTC 24 |
| Peak memory | 619292 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enable d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3738959388 -assert nopostpro c +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.chip_tl_errors.3738959388 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/1.chip_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_gpio.2787697940 |
| Short name | T33 |
| Test name | |
| Test status | |
| Simulation time | 3838058404 ps |
| CPU time | 330.26 seconds |
| Started | Aug 24 07:44:23 AM UTC 24 |
| Finished | Aug 24 07:49:58 AM UTC 24 |
| Peak memory | 626860 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=gpio_test:1:new_rules,tes t_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_rando m_seed=2787697940 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_gpio_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_gpio.2787697940 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/0.chip_sw_gpio/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_plic_all_irqs_10.581956280 |
| Short name | T128 |
| Test name | |
| Test status | |
| Simulation time | 4361065502 ps |
| CPU time | 391.18 seconds |
| Started | Aug 24 08:42:36 AM UTC 24 |
| Finished | Aug 24 08:49:12 AM UTC 24 |
| Peak memory | 626872 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=plic_all_irqs_test_10:1:n ew_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc l +ntb_random_seed=581956280 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.ch ip_plic_all_irqs_10.581956280 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/0.chip_plic_all_irqs_10/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/6.xbar_access_same_device.1315661054 |
| Short name | T786 |
| Test name | |
| Test status | |
| Simulation time | 2007683060 ps |
| CPU time | 72.44 seconds |
| Started | Aug 24 04:14:35 AM UTC 24 |
| Finished | Aug 24 04:15:49 AM UTC 24 |
| Peak memory | 597708 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1315661054 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.xbar_access_same_device.1315661054 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/6.xbar_access_same_device/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_flash_ctrl_lc_rw_en.3646034829 |
| Short name | T42 |
| Test name | |
| Test status | |
| Simulation time | 5021023382 ps |
| CPU time | 401.56 seconds |
| Started | Aug 24 07:46:27 AM UTC 24 |
| Finished | Aug 24 07:53:14 AM UTC 24 |
| Peak memory | 626684 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv + sw_images=flash_ctrl_lc_rw_en_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli - do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3646034829 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_flash_ct rl_lc_rw_en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vc s/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_flash_ctrl_lc_rw_en.3646034829 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/0.chip_sw_flash_ctrl_lc_rw_en/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/2.chip_csr_rw.1776974933 |
| Short name | T424 |
| Test name | |
| Test status | |
| Simulation time | 6057712634 ps |
| CPU time | 406.79 seconds |
| Started | Aug 24 03:59:31 AM UTC 24 |
| Finished | Aug 24 04:06:23 AM UTC 24 |
| Peak memory | 619368 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +stub_cpu=1 +cdc_instrumentation_ena bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1776974933 -assert nopost proc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os _regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.chip_csr_rw.1776974933 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/2.chip_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_flash_rma_unlocked.381981647 |
| Short name | T213 |
| Test name | |
| Test status | |
| Simulation time | 43314574748 ps |
| CPU time | 4049.06 seconds |
| Started | Aug 24 07:47:00 AM UTC 24 |
| Finished | Aug 24 08:55:11 AM UTC 24 |
| Peak memory | 640104 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/default/simv +flash_program_latency=5 +sw_test_timeout_ns=150_000_000 +sw _build_device=sim_dv +sw_images=flash_rma_unlocked_test:0:test_in_rom:new_rules +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=381981647 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST _SEQ=chip_sw_flash_rma_unlocked_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/chip_ earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_flash_rma_unlocked.381981647 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/0.chip_sw_flash_rma_unlocked/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/6.xbar_stress_all.462957702 |
| Short name | T470 |
| Test name | |
| Test status | |
| Simulation time | 4924893250 ps |
| CPU time | 345.98 seconds |
| Started | Aug 24 04:16:13 AM UTC 24 |
| Finished | Aug 24 04:22:03 AM UTC 24 |
| Peak memory | 598080 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=462957702 -assert nopostproc +UVM_TESTNAME =xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.xbar_stress_all.462957702 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/6.xbar_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/0.xbar_random_large_delays.915912013 |
| Short name | T569 |
| Test name | |
| Test status | |
| Simulation time | 96472418092 ps |
| CPU time | 745.69 seconds |
| Started | Aug 24 03:46:46 AM UTC 24 |
| Finished | Aug 24 03:59:21 AM UTC 24 |
| Peak memory | 598072 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max _device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=915912013 -assert nopostproc +UV M_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.xbar_random_large_delays.915912013 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/0.xbar_random_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/0.rom_e2e_shutdown_output.3331260713 |
| Short name | T58 |
| Test name | |
| Test status | |
| Simulation time | 29938882931 ps |
| CPU time | 2816.76 seconds |
| Started | Aug 24 09:09:10 AM UTC 24 |
| Finished | Aug 24 09:56:37 AM UTC 24 |
| Peak memory | 630028 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=20000000 +use_otp_image=OtpTypeCustom +s w_build_device=sim_dv +sw_images=empty_test_slot_a_unsigned:1:ot_flash_binary,otp_img_shutdown_output_test_unlocked0:4,mask_rom:0 +cdc_instrumenta tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3331260713 -asser t nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rom_e2e_shutdown_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_shutdown_output.3331260713 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/0.rom_e2e_shutdown_output/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_sysrst_ctrl_in_irq.1313917976 |
| Short name | T82 |
| Test name | |
| Test status | |
| Simulation time | 4601496552 ps |
| CPU time | 377.43 seconds |
| Started | Aug 24 08:04:02 AM UTC 24 |
| Finished | Aug 24 08:10:26 AM UTC 24 |
| Peak memory | 629228 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=sysrst_ctrl_in_irq_test:1 :new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim. tcl +ntb_random_seed=1313917976 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sysrst_ctrl_in_irq_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/n ull -cm_name 0.chip_sw_sysrst_ctrl_in_irq.1313917976 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/0.chip_sw_sysrst_ctrl_in_irq/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_alert_handler_lpg_sleep_mode_pings.147324631 |
| Short name | T107 |
| Test name | |
| Test status | |
| Simulation time | 10703313960 ps |
| CPU time | 874.42 seconds |
| Started | Aug 24 08:17:54 AM UTC 24 |
| Finished | Aug 24 08:32:38 AM UTC 24 |
| Peak memory | 626684 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_rea dy_to_end_check=1 +sw_build_device=sim_dv +sw_images=alert_handler_lpg_sleep_mode_pings_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=147324631 -assert nopostproc +U VM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_alert_handler_shorten_ping_wait_cycle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_alert_handl er_lpg_sleep_mode_pings.147324631 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/0.chip_sw_alert_handler_lpg_sleep_mode_pings/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/8.chip_tl_errors.1820584305 |
| Short name | T557 |
| Test name | |
| Test status | |
| Simulation time | 4671058916 ps |
| CPU time | 262.35 seconds |
| Started | Aug 24 04:22:11 AM UTC 24 |
| Finished | Aug 24 04:26:36 AM UTC 24 |
| Peak memory | 623472 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enable d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1820584305 -assert nopostpro c +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.chip_tl_errors.1820584305 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/8.chip_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_usbdev_aon_pullup.3003319520 |
| Short name | T10 |
| Test name | |
| Test status | |
| Simulation time | 3644710570 ps |
| CPU time | 273.69 seconds |
| Started | Aug 24 07:39:14 AM UTC 24 |
| Finished | Aug 24 07:43:52 AM UTC 24 |
| Peak memory | 624648 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/default/simv +uart_idx=0 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw _images=usbdev_aon_pullup_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3003319520 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_usbdev_dpi_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/de fault.vdb -cm_log /dev/null -cm_name 0.chip_sw_usbdev_aon_pullup.3003319520 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/0.chip_sw_usbdev_aon_pullup/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_otp_ctrl_escalation.2460945554 |
| Short name | T195 |
| Test name | |
| Test status | |
| Simulation time | 4876508910 ps |
| CPU time | 428.17 seconds |
| Started | Aug 24 07:50:30 AM UTC 24 |
| Finished | Aug 24 07:57:43 AM UTC 24 |
| Peak memory | 626628 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv + sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2460945554 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_otp_ct rl_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_otp_ctrl_escalation.2460945554 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/0.chip_sw_otp_ctrl_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_jtag_csr_rw.1123499782 |
| Short name | T65 |
| Test name | |
| Test status | |
| Simulation time | 12980342408 ps |
| CPU time | 886.56 seconds |
| Started | Aug 24 12:15:25 PM UTC 24 |
| Finished | Aug 24 12:30:22 PM UTC 24 |
| Peak memory | 627276 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/default/simv +en_scb=0 +csr_rw +create_jtag_riscv_map=1 +stub_cpu=1 +cdc_ instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=112349 9782 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_jtag_csr_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_jtag_csr_rw.1123499782 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/1.chip_jtag_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/30.xbar_access_same_device_slow_rsp.4105883163 |
| Short name | T799 |
| Test name | |
| Test status | |
| Simulation time | 118348682582 ps |
| CPU time | 1366.13 seconds |
| Started | Aug 24 05:34:23 AM UTC 24 |
| Finished | Aug 24 05:57:23 AM UTC 24 |
| Peak memory | 598788 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4105883163 -assert nopostproc +UVM_T ESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.xbar_access_same_device_slow_rsp.4105883163 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/30.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_sleep_pin_mio_dio_val.976314261 |
| Short name | T28 |
| Test name | |
| Test status | |
| Simulation time | 3434631095 ps |
| CPU time | 212.33 seconds |
| Started | Aug 24 10:56:13 AM UTC 24 |
| Finished | Aug 24 10:59:49 AM UTC 24 |
| Peak memory | 624816 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/default/simv +use_otp_image=OtpTypeLcStProd +sw_build_device=sim_dv +sw_i mages=sleep_pin_mio_dio_val_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=976314261 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sleep_pin_m io_dio_val_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_sleep_pin_mio_dio_val.976314261 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/1.chip_sw_sleep_pin_mio_dio_val/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/1.xbar_stress_all_with_reset_error.3858398648 |
| Short name | T589 |
| Test name | |
| Test status | |
| Simulation time | 6194775583 ps |
| CPU time | 311.69 seconds |
| Started | Aug 24 03:54:01 AM UTC 24 |
| Finished | Aug 24 03:59:17 AM UTC 24 |
| Peak memory | 597824 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3858398648 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.xbar_stress_all_with_reset_error.3858398648 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/1.xbar_stress_all_with_reset_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_jtag_csr_rw.1618617623 |
| Short name | T81 |
| Test name | |
| Test status | |
| Simulation time | 18612019124 ps |
| CPU time | 1300.76 seconds |
| Started | Aug 24 02:28:10 PM UTC 24 |
| Finished | Aug 24 02:50:05 PM UTC 24 |
| Peak memory | 627284 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/default/simv +en_scb=0 +csr_rw +create_jtag_riscv_map=1 +stub_cpu=1 +cdc_ instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=161861 7623 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_jtag_csr_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_jtag_csr_rw.1618617623 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/2.chip_jtag_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_data_integrity_escalation.977016896 |
| Short name | T50 |
| Test name | |
| Test status | |
| Simulation time | 5397523750 ps |
| CPU time | 406.87 seconds |
| Started | Aug 24 07:39:15 AM UTC 24 |
| Finished | Aug 24 07:46:07 AM UTC 24 |
| Peak memory | 626776 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv + sw_images=data_integrity_escalation_reset_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=977016896 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_ sw_data_integrity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_data_integrity_escalation.977016896 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/0.chip_sw_data_integrity_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_csrng_lc_hw_debug_en_test.1930890397 |
| Short name | T226 |
| Test name | |
| Test status | |
| Simulation time | 7877292364 ps |
| CPU time | 562.86 seconds |
| Started | Aug 24 08:21:03 AM UTC 24 |
| Finished | Aug 24 08:30:33 AM UTC 24 |
| Peak memory | 626752 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=15_000_000 +rng_srate_value_min=15 +use_ otp_image=OtpTypeLcStTestUnlocked0 +sw_build_device=sim_dv +sw_images=csrng_lc_hw_debug_en_test:1:new_rules,test_rom:0 +cdc_instrumentation_enable d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1930890397 -assert nopostpro c +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_csrng_lc_hw_debug_en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r epo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_csrng_lc_hw_debug_en_test.1930890397 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/0.chip_sw_csrng_lc_hw_debug_en_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/1.xbar_random_slow_rsp.2353556408 |
| Short name | T573 |
| Test name | |
| Test status | |
| Simulation time | 18231149257 ps |
| CPU time | 224.86 seconds |
| Started | Aug 24 03:52:20 AM UTC 24 |
| Finished | Aug 24 03:56:08 AM UTC 24 |
| Peak memory | 598080 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2353556408 -assert nopostproc +UVM_T ESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.xbar_random_slow_rsp.2353556408 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/1.xbar_random_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/17.chip_tl_errors.2865073311 |
| Short name | T558 |
| Test name | |
| Test status | |
| Simulation time | 4206154112 ps |
| CPU time | 255.96 seconds |
| Started | Aug 24 04:56:57 AM UTC 24 |
| Finished | Aug 24 05:01:16 AM UTC 24 |
| Peak memory | 623472 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enable d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2865073311 -assert nopostpro c +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.chip_tl_errors.2865073311 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/17.chip_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_rstmgr_cpu_info.3486419458 |
| Short name | T253 |
| Test name | |
| Test status | |
| Simulation time | 6403888256 ps |
| CPU time | 297.88 seconds |
| Started | Aug 24 07:56:03 AM UTC 24 |
| Finished | Aug 24 08:01:05 AM UTC 24 |
| Peak memory | 624584 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=rstmgr_cpu_info_test:1:ne w_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3486419458 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.ch ip_sw_rstmgr_cpu_info.3486419458 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/0.chip_sw_rstmgr_cpu_info/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_sleep_pin_mio_dio_val.1793002838 |
| Short name | T23 |
| Test name | |
| Test status | |
| Simulation time | 2779280838 ps |
| CPU time | 218.57 seconds |
| Started | Aug 24 12:50:24 PM UTC 24 |
| Finished | Aug 24 12:54:06 PM UTC 24 |
| Peak memory | 624652 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/default/simv +use_otp_image=OtpTypeLcStProd +sw_build_device=sim_dv +sw_i mages=sleep_pin_mio_dio_val_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1793002838 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sleep_pin_ mio_dio_val_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vc s/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_sleep_pin_mio_dio_val.1793002838 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/2.chip_sw_sleep_pin_mio_dio_val/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_lc_ctrl_rma_to_scrap.1694590176 |
| Short name | T62 |
| Test name | |
| Test status | |
| Simulation time | 3438093114 ps |
| CPU time | 214.65 seconds |
| Started | Aug 24 07:52:16 AM UTC 24 |
| Finished | Aug 24 07:55:53 AM UTC 24 |
| Peak memory | 636928 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/default/simv +bypass_alert_ready_to_end_check=1 +src_dec_state=DecLcStRma +sw_build_device=sim_dv +sw_images=lc_ctrl_scrap_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1694590176 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_ SEQ=chip_sw_lc_ctrl_scrap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgr ey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_lc_ctrl_rma_to_scrap.1694590176 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/0.chip_sw_lc_ctrl_rma_to_scrap/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/3.xbar_stress_all.2348179175 |
| Short name | T461 |
| Test name | |
| Test status | |
| Simulation time | 8762135345 ps |
| CPU time | 233.45 seconds |
| Started | Aug 24 04:02:39 AM UTC 24 |
| Finished | Aug 24 04:06:35 AM UTC 24 |
| Peak memory | 597964 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2348179175 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.xbar_stress_all.2348179175 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/3.xbar_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_pwrmgr_deep_sleep_all_wake_ups.3078784464 |
| Short name | T70 |
| Test name | |
| Test status | |
| Simulation time | 24406430776 ps |
| CPU time | 1056.96 seconds |
| Started | Aug 24 08:56:30 AM UTC 24 |
| Finished | Aug 24 09:14:19 AM UTC 24 |
| Peak memory | 629676 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_i mages=pwrmgr_deep_sleep_all_wake_ups:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3078784464 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_pwrmgr _deep_sleep_all_wake_ups_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgre y_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_pwrmgr_deep_sleep_all_wake_ups.3078784464 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/0.chip_sw_pwrmgr_deep_sleep_all_wake_ups/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/0.xbar_smoke.820882211 |
| Short name | T102 |
| Test name | |
| Test status | |
| Simulation time | 190967146 ps |
| CPU time | 6.86 seconds |
| Started | Aug 24 03:45:05 AM UTC 24 |
| Finished | Aug 24 03:45:13 AM UTC 24 |
| Peak memory | 595820 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=820882211 -assert nopostproc +UVM_TESTNAME =xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08 _22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.xbar_smoke.820882211 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/0.xbar_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_pwrmgr_deep_sleep_all_reset_reqs.3551952933 |
| Short name | T586 |
| Test name | |
| Test status | |
| Simulation time | 16369016527 ps |
| CPU time | 966.46 seconds |
| Started | Aug 24 07:58:44 AM UTC 24 |
| Finished | Aug 24 08:15:01 AM UTC 24 |
| Peak memory | 626760 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=50_000_000 +sw_build_device=sim_dv +sw_i mages=pwrmgr_deep_sleep_all_reset_reqs_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu e -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3551952933 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw _deep_sleep_all_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_a sic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_pwrmgr_deep_sleep_all_reset_reqs.3551952933 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/0.chip_sw_pwrmgr_deep_sleep_all_reset_reqs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/88.chip_sw_all_escalation_resets.3627686406 |
| Short name | T392 |
| Test name | |
| Test status | |
| Simulation time | 5735363880 ps |
| CPU time | 407.37 seconds |
| Started | Aug 24 04:37:05 PM UTC 24 |
| Finished | Aug 24 04:43:57 PM UTC 24 |
| Peak memory | 675192 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv + sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3627686406 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_es calation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 88.chip_sw_all_escalation_resets.3627686406 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/88.chip_sw_all_escalation_resets/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/34.chip_sw_all_escalation_resets.4044032290 |
| Short name | T111 |
| Test name | |
| Test status | |
| Simulation time | 6215988710 ps |
| CPU time | 407.01 seconds |
| Started | Aug 24 04:05:23 PM UTC 24 |
| Finished | Aug 24 04:12:15 PM UTC 24 |
| Peak memory | 675360 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv + sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4044032290 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_es calation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.chip_sw_all_escalation_resets.4044032290 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/34.chip_sw_all_escalation_resets/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/61.chip_sw_all_escalation_resets.3711193697 |
| Short name | T348 |
| Test name | |
| Test status | |
| Simulation time | 4306058074 ps |
| CPU time | 427.2 seconds |
| Started | Aug 24 04:22:56 PM UTC 24 |
| Finished | Aug 24 04:30:08 PM UTC 24 |
| Peak memory | 675440 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv + sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3711193697 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_es calation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 61.chip_sw_all_escalation_resets.3711193697 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/61.chip_sw_all_escalation_resets/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/27.chip_sw_all_escalation_resets.2050183503 |
| Short name | T264 |
| Test name | |
| Test status | |
| Simulation time | 5798826756 ps |
| CPU time | 505.49 seconds |
| Started | Aug 24 03:59:44 PM UTC 24 |
| Finished | Aug 24 04:08:16 PM UTC 24 |
| Peak memory | 675188 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv + sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2050183503 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_es calation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.chip_sw_all_escalation_resets.2050183503 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/27.chip_sw_all_escalation_resets/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/3.chip_csr_hw_reset.3471911497 |
| Short name | T175 |
| Test name | |
| Test status | |
| Simulation time | 7382791446 ps |
| CPU time | 315.77 seconds |
| Started | Aug 24 04:03:01 AM UTC 24 |
| Finished | Aug 24 04:08:21 AM UTC 24 |
| Peak memory | 683024 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +stub_cpu=1 +cdc_instrumentati on_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3471911497 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra tch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.chip_csr_hw_reset.3471911497 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/3.chip_csr_hw_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_uart_tx_rx_alt_clk_freq_low_speed.4047985044 |
| Short name | T36 |
| Test name | |
| Test status | |
| Simulation time | 4511512185 ps |
| CPU time | 343.6 seconds |
| Started | Aug 24 07:41:42 AM UTC 24 |
| Finished | Aug 24 07:47:30 AM UTC 24 |
| Peak memory | 637124 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=80_000_000 +calibrate_usb_clk=1 +chip_cl ock_source=ChipClockSourceExternal48Mhz +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4047985044 -assert nopostproc +UV M_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_baudrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr atch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_uart_tx_rx_alt_clk_freq_low_speed.4047985044 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/0.chip_sw_uart_tx_rx_alt_clk_freq_low_speed/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_tap_straps_rma.3724995784 |
| Short name | T97 |
| Test name | |
| Test status | |
| Simulation time | 3757461821 ps |
| CPU time | 192.64 seconds |
| Started | Aug 24 09:01:23 AM UTC 24 |
| Finished | Aug 24 09:04:39 AM UTC 24 |
| Peak memory | 639608 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/default/simv +create_jtag_riscv_map=1 +sw_build_device=sim_dv +sw_images= example_test_from_rom:0:test_in_rom:new_rules +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac es/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3724995784 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_tap_straps_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default.vdb - cm_log /dev/null -cm_name 0.chip_tap_straps_rma.3724995784 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/0.chip_tap_straps_rma/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/3.xbar_stress_all_with_reset_error.967417000 |
| Short name | T663 |
| Test name | |
| Test status | |
| Simulation time | 2118650984 ps |
| CPU time | 247.76 seconds |
| Started | Aug 24 04:02:59 AM UTC 24 |
| Finished | Aug 24 04:07:10 AM UTC 24 |
| Peak memory | 597692 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=967417000 -assert nopostproc +UVM_TESTNAME =xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.xbar_stress_all_with_reset_error.967417000 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/3.xbar_stress_all_with_reset_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_lc_walkthrough_dev.1157408545 |
| Short name | T215 |
| Test name | |
| Test status | |
| Simulation time | 49471450004 ps |
| CPU time | 3899.63 seconds |
| Started | Aug 24 07:53:47 AM UTC 24 |
| Finished | Aug 24 08:59:27 AM UTC 24 |
| Peak memory | 644456 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/default/simv +flash_program_latency=5 +use_otp_image=OtpTypeLcStRaw +dest _dec_state=DecLcStDev +sw_test_timeout_ns=200_000_000 +sw_build_device=sim_dv +sw_images=lc_walkthrough_test:1:new_rules,test_rom:0 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1157408545 -ass ert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_walkthrough_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works paces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_lc_walkthrough_dev.1157408545 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/0.chip_sw_lc_walkthrough_dev/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_plic_all_irqs_20.2055953308 |
| Short name | T338 |
| Test name | |
| Test status | |
| Simulation time | 5026798680 ps |
| CPU time | 525.89 seconds |
| Started | Aug 24 12:07:08 PM UTC 24 |
| Finished | Aug 24 12:16:01 PM UTC 24 |
| Peak memory | 624804 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=plic_all_irqs_test_20:1:n ew_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc l +ntb_random_seed=2055953308 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.c hip_plic_all_irqs_20.2055953308 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/1.chip_plic_all_irqs_20/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/2.xbar_stress_all_with_rand_reset.262489615 |
| Short name | T474 |
| Test name | |
| Test status | |
| Simulation time | 8167815578 ps |
| CPU time | 648.02 seconds |
| Started | Aug 24 03:58:34 AM UTC 24 |
| Finished | Aug 24 04:09:30 AM UTC 24 |
| Peak memory | 597828 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=262489615 -assert nopostproc +UVM_TESTNAME =xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.xbar_stress_all_with_rand_reset.262489615 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/2.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_plic_all_irqs_0.2837576051 |
| Short name | T341 |
| Test name | |
| Test status | |
| Simulation time | 5874168182 ps |
| CPU time | 732.4 seconds |
| Started | Aug 24 12:06:16 PM UTC 24 |
| Finished | Aug 24 12:18:37 PM UTC 24 |
| Peak memory | 624744 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=plic_all_irqs_test_0:1:ne w_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2837576051 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.ch ip_plic_all_irqs_0.2837576051 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/1.chip_plic_all_irqs_0/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_sleep_pin_wake.74417946 |
| Short name | T29 |
| Test name | |
| Test status | |
| Simulation time | 4032566014 ps |
| CPU time | 222.18 seconds |
| Started | Aug 24 10:56:15 AM UTC 24 |
| Finished | Aug 24 11:00:00 AM UTC 24 |
| Peak memory | 624624 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/default/simv +use_otp_image=OtpTypeLcStProd +sw_build_device=sim_dv +sw_i mages=sleep_pin_wake_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works paces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=74417946 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sleep_pin_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 1.chip_sw_sleep_pin_wake.74417946 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/1.chip_sw_sleep_pin_wake/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_spi_device_pinmux_sleep_retention.1536426456 |
| Short name | T16 |
| Test name | |
| Test status | |
| Simulation time | 3843231444 ps |
| CPU time | 170.88 seconds |
| Started | Aug 24 07:43:18 AM UTC 24 |
| Finished | Aug 24 07:46:12 AM UTC 24 |
| Peak memory | 637184 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=spi_device_sleep_test:1:n ew_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc l +ntb_random_seed=1536426456 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_spi_device_pinmux_sleep_retention_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default.vdb - cm_log /dev/null -cm_name 0.chip_sw_spi_device_pinmux_sleep_retention.1536426456 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/0.chip_sw_spi_device_pinmux_sleep_retention/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/2.chip_same_csr_outstanding.2841402199 |
| Short name | T405 |
| Test name | |
| Test status | |
| Simulation time | 17144172866 ps |
| CPU time | 1427.24 seconds |
| Started | Aug 24 03:54:24 AM UTC 24 |
| Finished | Aug 24 04:18:26 AM UTC 24 |
| Peak memory | 613148 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +test_timeout_ns=120_000_000 +run_same_csr_outstanding +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim .tcl +ntb_random_seed=2841402199 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_ name 2.chip_same_csr_outstanding.2841402199 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/2.chip_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/15.chip_tl_errors.3517079733 |
| Short name | T559 |
| Test name | |
| Test status | |
| Simulation time | 5432110326 ps |
| CPU time | 370.71 seconds |
| Started | Aug 24 04:48:47 AM UTC 24 |
| Finished | Aug 24 04:55:02 AM UTC 24 |
| Peak memory | 623328 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enable d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3517079733 -assert nopostpro c +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.chip_tl_errors.3517079733 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/15.chip_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/20.xbar_stress_all_with_rand_reset.1828819915 |
| Short name | T860 |
| Test name | |
| Test status | |
| Simulation time | 870951738 ps |
| CPU time | 209.07 seconds |
| Started | Aug 24 05:10:47 AM UTC 24 |
| Finished | Aug 24 05:14:19 AM UTC 24 |
| Peak memory | 597976 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1828819915 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.xbar_stress_all_with_rand_reset.1828819915 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/20.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_sensor_ctrl_alert.3158473084 |
| Short name | T167 |
| Test name | |
| Test status | |
| Simulation time | 5169206692 ps |
| CPU time | 395.56 seconds |
| Started | Aug 24 08:38:11 AM UTC 24 |
| Finished | Aug 24 08:44:52 AM UTC 24 |
| Peak memory | 627016 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=40_000_000 +sw_build_device=sim_dv +sw_i mages=sensor_ctrl_alert_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo rkspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3158473084 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default.vd b -cm_log /dev/null -cm_name 0.chip_sw_sensor_ctrl_alert.3158473084 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/0.chip_sw_sensor_ctrl_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_sram_ctrl_scrambled_access_jitter_en.1216445769 |
| Short name | T150 |
| Test name | |
| Test status | |
| Simulation time | 4463275100 ps |
| CPU time | 379.86 seconds |
| Started | Aug 24 08:38:05 AM UTC 24 |
| Finished | Aug 24 08:44:30 AM UTC 24 |
| Peak memory | 626868 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=12_000_000 +bypass_alert_ready_to_end_ch eck=1 +en_jitter=1 +en_scb_tl_err_chk=0 +sw_build_device=sim_dv +sw_images=sram_ctrl_scrambled_access_test:1:new_rules,test_rom:0 +cdc_instrumenta tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1216445769 -asser t nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sram_ctrl_scrambled_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_sram_ct rl_scrambled_access_jitter_en.1216445769 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/0.chip_sw_sram_ctrl_scrambled_access_jitter_en/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_sensor_ctrl_alert.4223843829 |
| Short name | T172 |
| Test name | |
| Test status | |
| Simulation time | 5807434080 ps |
| CPU time | 466.96 seconds |
| Started | Aug 24 02:14:29 PM UTC 24 |
| Finished | Aug 24 02:22:22 PM UTC 24 |
| Peak memory | 626748 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=40_000_000 +sw_build_device=sim_dv +sw_i mages=sensor_ctrl_alert_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo rkspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4223843829 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default.vd b -cm_log /dev/null -cm_name 2.chip_sw_sensor_ctrl_alert.4223843829 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/2.chip_sw_sensor_ctrl_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_spi_device_pass_through_collision.3543439004 |
| Short name | T13 |
| Test name | |
| Test status | |
| Simulation time | 4055371107 ps |
| CPU time | 366.71 seconds |
| Started | Aug 24 07:44:23 AM UTC 24 |
| Finished | Aug 24 07:50:35 AM UTC 24 |
| Peak memory | 641416 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=spi_passthrough_test:1:ne w_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3543439004 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_spi_passthrough_collision_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /d ev/null -cm_name 0.chip_sw_spi_device_pass_through_collision.3543439004 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/0.chip_sw_spi_device_pass_through_collision/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/27.xbar_stress_all_with_rand_reset.2996650848 |
| Short name | T857 |
| Test name | |
| Test status | |
| Simulation time | 24692802634 ps |
| CPU time | 772.02 seconds |
| Started | Aug 24 05:29:19 AM UTC 24 |
| Finished | Aug 24 05:42:19 AM UTC 24 |
| Peak memory | 598852 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2996650848 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.xbar_stress_all_with_rand_reset.2996650848 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/27.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_sleep_pin_wake.3507313963 |
| Short name | T27 |
| Test name | |
| Test status | |
| Simulation time | 5321372976 ps |
| CPU time | 262.8 seconds |
| Started | Aug 24 07:38:00 AM UTC 24 |
| Finished | Aug 24 07:42:27 AM UTC 24 |
| Peak memory | 626820 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/default/simv +use_otp_image=OtpTypeLcStProd +sw_build_device=sim_dv +sw_i mages=sleep_pin_wake_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works paces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3507313963 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sleep_pin_wake_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/def ault.vdb -cm_log /dev/null -cm_name 0.chip_sw_sleep_pin_wake.3507313963 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/0.chip_sw_sleep_pin_wake/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_flash_rma_unlocked.730824058 |
| Short name | T224 |
| Test name | |
| Test status | |
| Simulation time | 42983297130 ps |
| CPU time | 4116.95 seconds |
| Started | Aug 24 11:09:00 AM UTC 24 |
| Finished | Aug 24 12:18:20 PM UTC 24 |
| Peak memory | 639972 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/default/simv +flash_program_latency=5 +sw_test_timeout_ns=150_000_000 +sw _build_device=sim_dv +sw_images=flash_rma_unlocked_test:0:test_in_rom:new_rules +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=730824058 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST _SEQ=chip_sw_flash_rma_unlocked_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/chip_ earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_flash_rma_unlocked.730824058 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/1.chip_sw_flash_rma_unlocked/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/20.xbar_stress_all.3775486240 |
| Short name | T481 |
| Test name | |
| Test status | |
| Simulation time | 8750278064 ps |
| CPU time | 243.26 seconds |
| Started | Aug 24 05:10:41 AM UTC 24 |
| Finished | Aug 24 05:14:47 AM UTC 24 |
| Peak memory | 597960 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3775486240 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.xbar_stress_all.3775486240 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/20.xbar_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_plic_all_irqs_0.2412421818 |
| Short name | T342 |
| Test name | |
| Test status | |
| Simulation time | 6108643806 ps |
| CPU time | 788.69 seconds |
| Started | Aug 24 02:17:26 PM UTC 24 |
| Finished | Aug 24 02:30:44 PM UTC 24 |
| Peak memory | 624568 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=plic_all_irqs_test_0:1:ne w_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2412421818 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.ch ip_plic_all_irqs_0.2412421818 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/2.chip_plic_all_irqs_0/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/0.xbar_random_slow_rsp.4094559806 |
| Short name | T459 |
| Test name | |
| Test status | |
| Simulation time | 17448357858 ps |
| CPU time | 204.78 seconds |
| Started | Aug 24 03:46:56 AM UTC 24 |
| Finished | Aug 24 03:50:24 AM UTC 24 |
| Peak memory | 597824 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4094559806 -assert nopostproc +UVM_T ESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.xbar_random_slow_rsp.4094559806 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/0.xbar_random_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/22.xbar_stress_all_with_reset_error.324713962 |
| Short name | T797 |
| Test name | |
| Test status | |
| Simulation time | 9765094841 ps |
| CPU time | 411.93 seconds |
| Started | Aug 24 05:17:02 AM UTC 24 |
| Finished | Aug 24 05:24:00 AM UTC 24 |
| Peak memory | 597820 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=324713962 -assert nopostproc +UVM_TESTNAME =xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.xbar_stress_all_with_reset_error.324713962 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/22.xbar_stress_all_with_reset_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/7.chip_tl_errors.619049630 |
| Short name | T556 |
| Test name | |
| Test status | |
| Simulation time | 3865891922 ps |
| CPU time | 189.6 seconds |
| Started | Aug 24 04:17:44 AM UTC 24 |
| Finished | Aug 24 04:20:57 AM UTC 24 |
| Peak memory | 623324 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enable d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=619049630 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.chip_tl_errors.619049630 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/7.chip_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_flash_init.2316195656 |
| Short name | T329 |
| Test name | |
| Test status | |
| Simulation time | 21190009512 ps |
| CPU time | 1241.15 seconds |
| Started | Aug 24 01:16:10 PM UTC 24 |
| Finished | Aug 24 01:37:05 PM UTC 24 |
| Peak memory | 628980 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=25_000_000 +sw_build_device=sim_dv +sw_i mages=flash_init_test:0:test_in_rom:new_rules +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac es/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2316195656 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_flash_init_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default.vd b -cm_log /dev/null -cm_name 2.chip_sw_flash_init.2316195656 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/2.chip_sw_flash_init/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/1.chip_csr_hw_reset.689190658 |
| Short name | T174 |
| Test name | |
| Test status | |
| Simulation time | 5228760390 ps |
| CPU time | 166.88 seconds |
| Started | Aug 24 03:54:03 AM UTC 24 |
| Finished | Aug 24 03:56:53 AM UTC 24 |
| Peak memory | 683028 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +stub_cpu=1 +cdc_instrumentati on_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=689190658 -assert n opostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.chip_csr_hw_reset.689190658 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/1.chip_csr_hw_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_otp_ctrl_vendor_test_csr_access.228365675 |
| Short name | T40 |
| Test name | |
| Test status | |
| Simulation time | 3154163346 ps |
| CPU time | 151.12 seconds |
| Started | Aug 24 07:50:30 AM UTC 24 |
| Finished | Aug 24 07:53:03 AM UTC 24 |
| Peak memory | 641352 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=otp_ctrl_vendor_test_csr_ access_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/ dv/tools/sim.tcl +ntb_random_seed=228365675 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_otp_ctrl_vendor_test_csr_access_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 0.chip_sw_otp_ctrl_vendor_test_csr_access.228365675 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/0.chip_sw_otp_ctrl_vendor_test_csr_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_rv_dm_ndm_reset_req_when_cpu_halted.1546866029 |
| Short name | T94 |
| Test name | |
| Test status | |
| Simulation time | 3597900982 ps |
| CPU time | 321.39 seconds |
| Started | Aug 24 08:57:56 AM UTC 24 |
| Finished | Aug 24 09:03:21 AM UTC 24 |
| Peak memory | 636840 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/default/simv +use_jtag_dmi=1 +sw_build_device=sim_dv +sw_images=rv_dm_ndm _reset_req_when_cpu_halted_rma:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1546866029 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rv_dm_ndm_re set_when_cpu_halted_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asi c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_rv_dm_ndm_reset_req_when_cpu_halted.1546866029 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/0.chip_sw_rv_dm_ndm_reset_req_when_cpu_halted/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_gpio.2594886000 |
| Short name | T46 |
| Test name | |
| Test status | |
| Simulation time | 3871504832 ps |
| CPU time | 302.34 seconds |
| Started | Aug 24 11:04:41 AM UTC 24 |
| Finished | Aug 24 11:09:47 AM UTC 24 |
| Peak memory | 626864 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=gpio_test:1:new_rules,tes t_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_rando m_seed=2594886000 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_gpio_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_gpio.2594886000 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/1.chip_sw_gpio/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/50.xbar_stress_all_with_reset_error.887538532 |
| Short name | T2070 |
| Test name | |
| Test status | |
| Simulation time | 3291592187 ps |
| CPU time | 193.49 seconds |
| Started | Aug 24 06:12:21 AM UTC 24 |
| Finished | Aug 24 06:15:37 AM UTC 24 |
| Peak memory | 598000 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=887538532 -assert nopostproc +UVM_TESTNAME =xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 50.xbar_stress_all_with_reset_error.887538532 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/50.xbar_stress_all_with_reset_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_uart_tx_rx_idx2.3552580688 |
| Short name | T32 |
| Test name | |
| Test status | |
| Simulation time | 4753110540 ps |
| CPU time | 404.16 seconds |
| Started | Aug 24 07:39:15 AM UTC 24 |
| Finished | Aug 24 07:46:05 AM UTC 24 |
| Peak memory | 637088 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/default/simv +uart_idx=2 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw _images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3552580688 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_tx_rx_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 0.chip_sw_uart_tx_rx_idx2.3552580688 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/0.chip_sw_uart_tx_rx_idx2/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_ast_clk_rst_inputs.1679127926 |
| Short name | T141 |
| Test name | |
| Test status | |
| Simulation time | 23714348201 ps |
| CPU time | 2854.45 seconds |
| Started | Aug 24 09:06:39 AM UTC 24 |
| Finished | Aug 24 09:54:44 AM UTC 24 |
| Peak memory | 629984 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=200_000_000 +sw_build_device=sim_dv +sw_ images=ast_clk_rst_inputs:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works paces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1679127926 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_ast_clk_rst_input s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage /default.vdb -cm_log /dev/null -cm_name 0.chip_sw_ast_clk_rst_inputs.1679127926 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/0.chip_sw_ast_clk_rst_inputs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/20.chip_tl_errors.477315044 |
| Short name | T582 |
| Test name | |
| Test status | |
| Simulation time | 4354506876 ps |
| CPU time | 251.88 seconds |
| Started | Aug 24 05:07:59 AM UTC 24 |
| Finished | Aug 24 05:12:14 AM UTC 24 |
| Peak memory | 623324 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enable d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=477315044 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.chip_tl_errors.477315044 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/20.chip_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_plic_all_irqs_10.1606812821 |
| Short name | T193 |
| Test name | |
| Test status | |
| Simulation time | 4180831080 ps |
| CPU time | 345.22 seconds |
| Started | Aug 24 12:06:53 PM UTC 24 |
| Finished | Aug 24 12:12:43 PM UTC 24 |
| Peak memory | 624568 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=plic_all_irqs_test_10:1:n ew_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc l +ntb_random_seed=1606812821 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.c hip_plic_all_irqs_10.1606812821 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/1.chip_plic_all_irqs_10/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_flash_ctrl_ops.2548183988 |
| Short name | T386 |
| Test name | |
| Test status | |
| Simulation time | 4457478244 ps |
| CPU time | 460.27 seconds |
| Started | Aug 24 01:10:41 PM UTC 24 |
| Finished | Aug 24 01:18:27 PM UTC 24 |
| Peak memory | 624820 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=50_000_000 +sw_build_device=sim_dv +sw_i mages=flash_ctrl_ops_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works paces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2548183988 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default.vdb - cm_log /dev/null -cm_name 2.chip_sw_flash_ctrl_ops.2548183988 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/2.chip_sw_flash_ctrl_ops/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/42.xbar_stress_all_with_rand_reset.646327027 |
| Short name | T1975 |
| Test name | |
| Test status | |
| Simulation time | 11157333967 ps |
| CPU time | 396.14 seconds |
| Started | Aug 24 05:58:51 AM UTC 24 |
| Finished | Aug 24 06:05:32 AM UTC 24 |
| Peak memory | 597824 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=646327027 -assert nopostproc +UVM_TESTNAME =xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.xbar_stress_all_with_rand_reset.646327027 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/42.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/pad_ctrl_test_mode/1.chip_padctrl_attributes.2952282386 |
| Short name | T26 |
| Test name | |
| Test status | |
| Simulation time | 4542958086 ps |
| CPU time | 183.31 seconds |
| Started | Aug 24 07:33:13 AM UTC 24 |
| Finished | Aug 24 07:36:20 AM UTC 24 |
| Peak memory | 667708 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/pad_ctrl_test_mode/simv +use_otp_image=OtpTypeLcStProd +stub_cpu=1 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2952282 386 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_padctrl_attributes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/pad_ctrl_test_mode.vdb -cm_log /dev/null -cm_name 1.chip_ padctrl_attributes.2952282386 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/1.chip_padctrl_attributes/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_uart_tx_rx_idx3.1904136887 |
| Short name | T31 |
| Test name | |
| Test status | |
| Simulation time | 4679979428 ps |
| CPU time | 387.05 seconds |
| Started | Aug 24 07:39:16 AM UTC 24 |
| Finished | Aug 24 07:45:48 AM UTC 24 |
| Peak memory | 636860 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/default/simv +uart_idx=3 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw _images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1904136887 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_tx_rx_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 0.chip_sw_uart_tx_rx_idx3.1904136887 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/0.chip_sw_uart_tx_rx_idx3/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_sw_fast_dev.1469225573 |
| Short name | T154 |
| Test name | |
| Test status | |
| Simulation time | 3682016112 ps |
| CPU time | 463.33 seconds |
| Started | Aug 24 08:48:07 AM UTC 24 |
| Finished | Aug 24 08:55:56 AM UTC 24 |
| Peak memory | 628604 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/default/simv +chip_clock_source=ChipClockSourceExternal96Mhz +calibrate_u sb_clk=1 +src_dec_state=DecLcStDev +sw_build_device=sim_dv +sw_images=clkmgr_external_clk_src_for_sw_fast_test:1:new_rules,test_rom:0 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1469225573 -a ssert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces /repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_clkmgr_external_clk_sr c_for_sw_fast_dev.1469225573 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/0.chip_sw_clkmgr_external_clk_src_for_sw_fast_dev/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_flash_rma_unlocked.4288649324 |
| Short name | T227 |
| Test name | |
| Test status | |
| Simulation time | 44753586454 ps |
| CPU time | 4251.93 seconds |
| Started | Aug 24 01:16:46 PM UTC 24 |
| Finished | Aug 24 02:28:21 PM UTC 24 |
| Peak memory | 640104 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/default/simv +flash_program_latency=5 +sw_test_timeout_ns=150_000_000 +sw _build_device=sim_dv +sw_images=flash_rma_unlocked_test:0:test_in_rom:new_rules +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4288649324 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TES T_SEQ=chip_sw_flash_rma_unlocked_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/chip _earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_flash_rma_unlocked.4288649324 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/2.chip_sw_flash_rma_unlocked/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_sysrst_ctrl_ulp_z3_wakeup.737282210 |
| Short name | T20 |
| Test name | |
| Test status | |
| Simulation time | 5233317300 ps |
| CPU time | 258.68 seconds |
| Started | Aug 24 08:04:41 AM UTC 24 |
| Finished | Aug 24 08:09:03 AM UTC 24 |
| Peak memory | 627260 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=sysrst_ctrl_ulp_z3_wakeup _test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/too ls/sim.tcl +ntb_random_seed=737282210 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sysrst_ctrl_ulp_z3_wakeup_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default.vdb - cm_log /dev/null -cm_name 0.chip_sw_sysrst_ctrl_ulp_z3_wakeup.737282210 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/0.chip_sw_sysrst_ctrl_ulp_z3_wakeup/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/0.xbar_access_same_device.2016445960 |
| Short name | T548 |
| Test name | |
| Test status | |
| Simulation time | 779499176 ps |
| CPU time | 43.57 seconds |
| Started | Aug 24 03:46:57 AM UTC 24 |
| Finished | Aug 24 03:47:42 AM UTC 24 |
| Peak memory | 597840 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2016445960 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.xbar_access_same_device.2016445960 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/0.xbar_access_same_device/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/62.xbar_stress_all_with_rand_reset.3665158443 |
| Short name | T2389 |
| Test name | |
| Test status | |
| Simulation time | 21953261954 ps |
| CPU time | 684.17 seconds |
| Started | Aug 24 06:32:42 AM UTC 24 |
| Finished | Aug 24 06:44:13 AM UTC 24 |
| Peak memory | 597884 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3665158443 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 62.xbar_stress_all_with_rand_reset.3665158443 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/62.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/12.xbar_stress_all_with_rand_reset.1247300163 |
| Short name | T530 |
| Test name | |
| Test status | |
| Simulation time | 6660158617 ps |
| CPU time | 626.13 seconds |
| Started | Aug 24 04:40:21 AM UTC 24 |
| Finished | Aug 24 04:50:55 AM UTC 24 |
| Peak memory | 598040 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1247300163 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.xbar_stress_all_with_rand_reset.1247300163 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/12.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/6.chip_sw_all_escalation_resets.429046675 |
| Short name | T379 |
| Test name | |
| Test status | |
| Simulation time | 6039520208 ps |
| CPU time | 400.42 seconds |
| Started | Aug 24 03:30:03 PM UTC 24 |
| Finished | Aug 24 03:36:49 PM UTC 24 |
| Peak memory | 675196 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv + sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=429046675 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_esc alation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.chip_sw_all_escalation_resets.429046675 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/6.chip_sw_all_escalation_resets/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_lc_ctrl_transition.1705352294 |
| Short name | T228 |
| Test name | |
| Test status | |
| Simulation time | 13945585671 ps |
| CPU time | 822.56 seconds |
| Started | Aug 24 07:52:13 AM UTC 24 |
| Finished | Aug 24 08:06:05 AM UTC 24 |
| Peak memory | 639572 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=lc_ctrl_transition_test:1 :new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim. tcl +ntb_random_seed=1705352294 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_ctrl_transition_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/n ull -cm_name 0.chip_sw_lc_ctrl_transition.1705352294 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/0.chip_sw_lc_ctrl_transition/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/55.xbar_stress_all_with_rand_reset.3150226928 |
| Short name | T852 |
| Test name | |
| Test status | |
| Simulation time | 2122592825 ps |
| CPU time | 182.11 seconds |
| Started | Aug 24 06:22:14 AM UTC 24 |
| Finished | Aug 24 06:25:19 AM UTC 24 |
| Peak memory | 597764 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3150226928 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 55.xbar_stress_all_with_rand_reset.3150226928 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/55.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/67.xbar_stress_all_with_reset_error.1157330188 |
| Short name | T848 |
| Test name | |
| Test status | |
| Simulation time | 306067058 ps |
| CPU time | 48.15 seconds |
| Started | Aug 24 06:40:47 AM UTC 24 |
| Finished | Aug 24 06:41:37 AM UTC 24 |
| Peak memory | 597924 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1157330188 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 67.xbar_stress_all_with_reset_error.1157330188 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/67.xbar_stress_all_with_reset_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/21.xbar_stress_all.3128841474 |
| Short name | T496 |
| Test name | |
| Test status | |
| Simulation time | 9898251541 ps |
| CPU time | 272.54 seconds |
| Started | Aug 24 05:14:02 AM UTC 24 |
| Finished | Aug 24 05:18:38 AM UTC 24 |
| Peak memory | 598028 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3128841474 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.xbar_stress_all.3128841474 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/21.xbar_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/4.chip_csr_rw.3099576585 |
| Short name | T458 |
| Test name | |
| Test status | |
| Simulation time | 5492874999 ps |
| CPU time | 362.51 seconds |
| Started | Aug 24 04:08:14 AM UTC 24 |
| Finished | Aug 24 04:14:21 AM UTC 24 |
| Peak memory | 619364 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +stub_cpu=1 +cdc_instrumentation_ena bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3099576585 -assert nopost proc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os _regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.chip_csr_rw.3099576585 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/4.chip_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_plic_all_irqs_20.3886849096 |
| Short name | T339 |
| Test name | |
| Test status | |
| Simulation time | 4887715232 ps |
| CPU time | 539.06 seconds |
| Started | Aug 24 02:19:06 PM UTC 24 |
| Finished | Aug 24 02:28:12 PM UTC 24 |
| Peak memory | 624772 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=plic_all_irqs_test_20:1:n ew_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc l +ntb_random_seed=3886849096 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.c hip_plic_all_irqs_20.3886849096 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/2.chip_plic_all_irqs_20/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_otp_ctrl_vendor_test_csr_access.3111091955 |
| Short name | T200 |
| Test name | |
| Test status | |
| Simulation time | 2893417694 ps |
| CPU time | 157.66 seconds |
| Started | Aug 24 11:12:18 AM UTC 24 |
| Finished | Aug 24 11:14:58 AM UTC 24 |
| Peak memory | 641268 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=otp_ctrl_vendor_test_csr_ access_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/ dv/tools/sim.tcl +ntb_random_seed=3111091955 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_otp_ctrl_vendor_test_csr_access _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/ default.vdb -cm_log /dev/null -cm_name 1.chip_sw_otp_ctrl_vendor_test_csr_access.3111091955 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/1.chip_sw_otp_ctrl_vendor_test_csr_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_pwrmgr_full_aon_reset.629245590 |
| Short name | T164 |
| Test name | |
| Test status | |
| Simulation time | 9603712123 ps |
| CPU time | 394.93 seconds |
| Started | Aug 24 07:56:18 AM UTC 24 |
| Finished | Aug 24 08:02:57 AM UTC 24 |
| Peak memory | 626936 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=rstmgr_smoketest:1:new_ru les,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +nt b_random_seed=629245590 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_full_aon_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_pwrmgr_full_aon_reset.629245590 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/0.chip_sw_pwrmgr_full_aon_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_plic_all_irqs_10.635556492 |
| Short name | T194 |
| Test name | |
| Test status | |
| Simulation time | 3677568552 ps |
| CPU time | 476.74 seconds |
| Started | Aug 24 02:18:11 PM UTC 24 |
| Finished | Aug 24 02:26:14 PM UTC 24 |
| Peak memory | 624780 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=plic_all_irqs_test_10:1:n ew_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc l +ntb_random_seed=635556492 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.ch ip_plic_all_irqs_10.635556492 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/2.chip_plic_all_irqs_10/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_uart_tx_rx_idx1.2255073082 |
| Short name | T131 |
| Test name | |
| Test status | |
| Simulation time | 4491324660 ps |
| CPU time | 458.54 seconds |
| Started | Aug 24 07:39:11 AM UTC 24 |
| Finished | Aug 24 07:46:55 AM UTC 24 |
| Peak memory | 641204 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/default/simv +uart_idx=1 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw _images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2255073082 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_tx_rx_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 0.chip_sw_uart_tx_rx_idx1.2255073082 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/0.chip_sw_uart_tx_rx_idx1/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq.1822102128 |
| Short name | T186 |
| Test name | |
| Test status | |
| Simulation time | 24763073199 ps |
| CPU time | 3324.48 seconds |
| Started | Aug 24 09:04:23 AM UTC 24 |
| Finished | Aug 24 10:00:24 AM UTC 24 |
| Peak memory | 629792 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=33_000_000 +rng_srate_value=30 +en_jitte r=1 +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +sw_images=otbn_ecdsa_op_irq_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1822102128 -assert nopostproc +UVM_TESTNA ME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_08_22/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq.1822102128 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/0.chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_usbdev_config_host.4074941196 |
| Short name | T21 |
| Test name | |
| Test status | |
| Simulation time | 8279636966 ps |
| CPU time | 1130.78 seconds |
| Started | Aug 24 07:39:41 AM UTC 24 |
| Finished | Aug 24 07:58:44 AM UTC 24 |
| Peak memory | 624780 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/default/simv +uart_idx=0 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw _images=usbdev_config_host_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4074941196 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_usbdev_dpi_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 0.chip_sw_usbdev_config_host.4074941196 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/0.chip_sw_usbdev_config_host/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_rv_dm_access_after_escalation_reset.4084442555 |
| Short name | T96 |
| Test name | |
| Test status | |
| Simulation time | 5164709502 ps |
| CPU time | 309.55 seconds |
| Started | Aug 24 08:59:24 AM UTC 24 |
| Finished | Aug 24 09:04:38 AM UTC 24 |
| Peak memory | 638828 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/default/simv +use_jtag_dmi=1 +sw_build_device=sim_dv +sw_images=alert_han dler_escalation_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces /repo/hw/dv/tools/sim.tcl +ntb_random_seed=4084442555 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rv_dm_access_after_esc alation_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_rv_dm_access_after_escalation_reset.4084442555 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/0.chip_sw_rv_dm_access_after_escalation_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_flash_ctrl_ops.2907677090 |
| Short name | T334 |
| Test name | |
| Test status | |
| Simulation time | 3959279796 ps |
| CPU time | 436.64 seconds |
| Started | Aug 24 07:45:34 AM UTC 24 |
| Finished | Aug 24 07:52:56 AM UTC 24 |
| Peak memory | 624784 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=50_000_000 +sw_build_device=sim_dv +sw_i mages=flash_ctrl_ops_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works paces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2907677090 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default.vdb - cm_log /dev/null -cm_name 0.chip_sw_flash_ctrl_ops.2907677090 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/0.chip_sw_flash_ctrl_ops/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_rstmgr_alert_info.1684739327 |
| Short name | T198 |
| Test name | |
| Test status | |
| Simulation time | 13087752024 ps |
| CPU time | 1038.04 seconds |
| Started | Aug 24 07:56:03 AM UTC 24 |
| Finished | Aug 24 08:13:32 AM UTC 24 |
| Peak memory | 626684 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=30_000_000 +en_scb_tl_err_chk=0 +sw_buil d_device=sim_dv +sw_images=rstmgr_alert_info_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1684739327 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=c hip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vc s/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_rstmgr_alert_info.1684739327 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/0.chip_sw_rstmgr_alert_info/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/18.xbar_stress_all_with_rand_reset.3096893441 |
| Short name | T867 |
| Test name | |
| Test status | |
| Simulation time | 305909007 ps |
| CPU time | 80.41 seconds |
| Started | Aug 24 05:04:02 AM UTC 24 |
| Finished | Aug 24 05:05:24 AM UTC 24 |
| Peak memory | 597692 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3096893441 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.xbar_stress_all_with_rand_reset.3096893441 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/18.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_alert_handler_lpg_sleep_mode_alerts.3251906284 |
| Short name | T773 |
| Test name | |
| Test status | |
| Simulation time | 3678408052 ps |
| CPU time | 264.87 seconds |
| Started | Aug 24 11:40:12 AM UTC 24 |
| Finished | Aug 24 11:44:41 AM UTC 24 |
| Peak memory | 673528 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_rea dy_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv _core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_handler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3251906284 -assert nopos tproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_alert_handler_lpg_s leep_mode_alerts.3251906284 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/1.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_all_escalation_resets.987476531 |
| Short name | T675 |
| Test name | |
| Test status | |
| Simulation time | 5209126440 ps |
| CPU time | 339.91 seconds |
| Started | Aug 24 10:54:46 AM UTC 24 |
| Finished | Aug 24 11:00:30 AM UTC 24 |
| Peak memory | 675280 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv + sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=987476531 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_esc alation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_all_escalation_resets.987476531 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/1.chip_sw_all_escalation_resets/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/10.chip_sw_alert_handler_lpg_sleep_mode_alerts.1832799366 |
| Short name | T766 |
| Test name | |
| Test status | |
| Simulation time | 3774814150 ps |
| CPU time | 260.49 seconds |
| Started | Aug 24 03:40:04 PM UTC 24 |
| Finished | Aug 24 03:44:28 PM UTC 24 |
| Peak memory | 673272 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_rea dy_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv _core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_handler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1832799366 -assert nopos tproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.chip_sw_alert_handler_lpg_ sleep_mode_alerts.1832799366 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/10.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/10.chip_sw_all_escalation_resets.2526818020 |
| Short name | T711 |
| Test name | |
| Test status | |
| Simulation time | 6352260932 ps |
| CPU time | 456.98 seconds |
| Started | Aug 24 03:38:11 PM UTC 24 |
| Finished | Aug 24 03:45:54 PM UTC 24 |
| Peak memory | 675192 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv + sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2526818020 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_es calation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.chip_sw_all_escalation_resets.2526818020 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/10.chip_sw_all_escalation_resets/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/11.chip_sw_alert_handler_lpg_sleep_mode_alerts.1990323089 |
| Short name | T109 |
| Test name | |
| Test status | |
| Simulation time | 3714134288 ps |
| CPU time | 320.5 seconds |
| Started | Aug 24 03:41:00 PM UTC 24 |
| Finished | Aug 24 03:46:24 PM UTC 24 |
| Peak memory | 673292 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_rea dy_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv _core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_handler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1990323089 -assert nopos tproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.chip_sw_alert_handler_lpg_ sleep_mode_alerts.1990323089 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/11.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/11.chip_sw_all_escalation_resets.1148703892 |
| Short name | T119 |
| Test name | |
| Test status | |
| Simulation time | 5579561700 ps |
| CPU time | 478.36 seconds |
| Started | Aug 24 03:40:16 PM UTC 24 |
| Finished | Aug 24 03:48:20 PM UTC 24 |
| Peak memory | 675196 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv + sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1148703892 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_es calation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.chip_sw_all_escalation_resets.1148703892 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/11.chip_sw_all_escalation_resets/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/12.chip_sw_alert_handler_lpg_sleep_mode_alerts.1115893414 |
| Short name | T120 |
| Test name | |
| Test status | |
| Simulation time | 3915823370 ps |
| CPU time | 297.1 seconds |
| Started | Aug 24 03:43:50 PM UTC 24 |
| Finished | Aug 24 03:48:51 PM UTC 24 |
| Peak memory | 673276 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_rea dy_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv _core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_handler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1115893414 -assert nopos tproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.chip_sw_alert_handler_lpg_ sleep_mode_alerts.1115893414 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/12.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/12.chip_sw_all_escalation_resets.3151326193 |
| Short name | T118 |
| Test name | |
| Test status | |
| Simulation time | 4129988170 ps |
| CPU time | 379.24 seconds |
| Started | Aug 24 03:41:43 PM UTC 24 |
| Finished | Aug 24 03:48:07 PM UTC 24 |
| Peak memory | 675196 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv + sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3151326193 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_es calation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.chip_sw_all_escalation_resets.3151326193 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/12.chip_sw_all_escalation_resets/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/13.chip_sw_alert_handler_lpg_sleep_mode_alerts.584111278 |
| Short name | T124 |
| Test name | |
| Test status | |
| Simulation time | 4055322716 ps |
| CPU time | 327.68 seconds |
| Started | Aug 24 03:45:00 PM UTC 24 |
| Finished | Aug 24 03:50:33 PM UTC 24 |
| Peak memory | 673212 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_rea dy_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv _core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_handler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=584111278 -assert nopost proc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac es/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.chip_sw_alert_handler_lpg_s leep_mode_alerts.584111278 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/13.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/13.chip_sw_all_escalation_resets.2661478892 |
| Short name | T759 |
| Test name | |
| Test status | |
| Simulation time | 5218271320 ps |
| CPU time | 467.87 seconds |
| Started | Aug 24 03:44:23 PM UTC 24 |
| Finished | Aug 24 03:52:17 PM UTC 24 |
| Peak memory | 673144 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv + sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2661478892 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_es calation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.chip_sw_all_escalation_resets.2661478892 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/13.chip_sw_all_escalation_resets/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/14.chip_sw_alert_handler_lpg_sleep_mode_alerts.778216331 |
| Short name | T673 |
| Test name | |
| Test status | |
| Simulation time | 3869363354 ps |
| CPU time | 296.14 seconds |
| Started | Aug 24 03:46:57 PM UTC 24 |
| Finished | Aug 24 03:51:58 PM UTC 24 |
| Peak memory | 673464 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_rea dy_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv _core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_handler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=778216331 -assert nopost proc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac es/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.chip_sw_alert_handler_lpg_s leep_mode_alerts.778216331 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/14.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/14.chip_sw_all_escalation_resets.1640888514 |
| Short name | T687 |
| Test name | |
| Test status | |
| Simulation time | 5370751570 ps |
| CPU time | 491.08 seconds |
| Started | Aug 24 03:45:13 PM UTC 24 |
| Finished | Aug 24 03:53:30 PM UTC 24 |
| Peak memory | 675276 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv + sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1640888514 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_es calation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.chip_sw_all_escalation_resets.1640888514 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/14.chip_sw_all_escalation_resets/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/15.chip_sw_alert_handler_lpg_sleep_mode_alerts.1515883749 |
| Short name | T733 |
| Test name | |
| Test status | |
| Simulation time | 3350129344 ps |
| CPU time | 280.35 seconds |
| Started | Aug 24 03:48:31 PM UTC 24 |
| Finished | Aug 24 03:53:16 PM UTC 24 |
| Peak memory | 673464 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_rea dy_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv _core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_handler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1515883749 -assert nopos tproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.chip_sw_alert_handler_lpg_ sleep_mode_alerts.1515883749 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/15.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/15.chip_sw_all_escalation_resets.2343976130 |
| Short name | T682 |
| Test name | |
| Test status | |
| Simulation time | 5960558336 ps |
| CPU time | 519.11 seconds |
| Started | Aug 24 03:46:57 PM UTC 24 |
| Finished | Aug 24 03:55:43 PM UTC 24 |
| Peak memory | 675512 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv + sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2343976130 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_es calation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.chip_sw_all_escalation_resets.2343976130 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/15.chip_sw_all_escalation_resets/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/16.chip_sw_alert_handler_lpg_sleep_mode_alerts.1267273550 |
| Short name | T779 |
| Test name | |
| Test status | |
| Simulation time | 3296597568 ps |
| CPU time | 282.24 seconds |
| Started | Aug 24 03:50:21 PM UTC 24 |
| Finished | Aug 24 03:55:07 PM UTC 24 |
| Peak memory | 673460 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_rea dy_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv _core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_handler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1267273550 -assert nopos tproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.chip_sw_alert_handler_lpg_ sleep_mode_alerts.1267273550 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/16.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/17.chip_sw_alert_handler_lpg_sleep_mode_alerts.3249149433 |
| Short name | T758 |
| Test name | |
| Test status | |
| Simulation time | 3359685496 ps |
| CPU time | 273.67 seconds |
| Started | Aug 24 03:51:06 PM UTC 24 |
| Finished | Aug 24 03:55:43 PM UTC 24 |
| Peak memory | 673208 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_rea dy_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv _core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_handler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3249149433 -assert nopos tproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.chip_sw_alert_handler_lpg_ sleep_mode_alerts.3249149433 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/17.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/18.chip_sw_alert_handler_lpg_sleep_mode_alerts.4038179267 |
| Short name | T721 |
| Test name | |
| Test status | |
| Simulation time | 3555643770 ps |
| CPU time | 250.57 seconds |
| Started | Aug 24 03:52:11 PM UTC 24 |
| Finished | Aug 24 03:56:25 PM UTC 24 |
| Peak memory | 673456 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_rea dy_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv _core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_handler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4038179267 -assert nopos tproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.chip_sw_alert_handler_lpg_ sleep_mode_alerts.4038179267 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/18.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/19.chip_sw_alert_handler_lpg_sleep_mode_alerts.2547997285 |
| Short name | T700 |
| Test name | |
| Test status | |
| Simulation time | 3887192554 ps |
| CPU time | 278.49 seconds |
| Started | Aug 24 03:53:40 PM UTC 24 |
| Finished | Aug 24 03:58:23 PM UTC 24 |
| Peak memory | 673460 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_rea dy_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv _core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_handler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2547997285 -assert nopos tproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.chip_sw_alert_handler_lpg_ sleep_mode_alerts.2547997285 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/19.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/19.chip_sw_all_escalation_resets.1885449069 |
| Short name | T689 |
| Test name | |
| Test status | |
| Simulation time | 4846543368 ps |
| CPU time | 441.41 seconds |
| Started | Aug 24 03:52:23 PM UTC 24 |
| Finished | Aug 24 03:59:50 PM UTC 24 |
| Peak memory | 675512 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv + sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1885449069 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_es calation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.chip_sw_all_escalation_resets.1885449069 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/19.chip_sw_all_escalation_resets/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_alert_handler_lpg_sleep_mode_alerts.3855713159 |
| Short name | T696 |
| Test name | |
| Test status | |
| Simulation time | 3314002190 ps |
| CPU time | 270.26 seconds |
| Started | Aug 24 01:47:49 PM UTC 24 |
| Finished | Aug 24 01:52:23 PM UTC 24 |
| Peak memory | 673216 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_rea dy_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv _core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_handler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3855713159 -assert nopos tproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_alert_handler_lpg_s leep_mode_alerts.3855713159 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/2.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_all_escalation_resets.1238525354 |
| Short name | T661 |
| Test name | |
| Test status | |
| Simulation time | 4533928792 ps |
| CPU time | 374.97 seconds |
| Started | Aug 24 12:49:39 PM UTC 24 |
| Finished | Aug 24 12:55:58 PM UTC 24 |
| Peak memory | 675200 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv + sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1238525354 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_es calation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_all_escalation_resets.1238525354 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/2.chip_sw_all_escalation_resets/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/21.chip_sw_alert_handler_lpg_sleep_mode_alerts.3463480088 |
| Short name | T731 |
| Test name | |
| Test status | |
| Simulation time | 4254971752 ps |
| CPU time | 325.98 seconds |
| Started | Aug 24 03:56:25 PM UTC 24 |
| Finished | Aug 24 04:01:55 PM UTC 24 |
| Peak memory | 673460 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_rea dy_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv _core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_handler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3463480088 -assert nopos tproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.chip_sw_alert_handler_lpg_ sleep_mode_alerts.3463480088 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/21.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/22.chip_sw_all_escalation_resets.3883848882 |
| Short name | T680 |
| Test name | |
| Test status | |
| Simulation time | 5881295656 ps |
| CPU time | 529.69 seconds |
| Started | Aug 24 03:56:24 PM UTC 24 |
| Finished | Aug 24 04:05:20 PM UTC 24 |
| Peak memory | 675344 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv + sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3883848882 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_es calation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.chip_sw_all_escalation_resets.3883848882 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/22.chip_sw_all_escalation_resets/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/24.chip_sw_alert_handler_lpg_sleep_mode_alerts.1805683873 |
| Short name | T768 |
| Test name | |
| Test status | |
| Simulation time | 4312729016 ps |
| CPU time | 297.43 seconds |
| Started | Aug 24 03:58:03 PM UTC 24 |
| Finished | Aug 24 04:03:05 PM UTC 24 |
| Peak memory | 673216 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_rea dy_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv _core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_handler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1805683873 -assert nopos tproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.chip_sw_alert_handler_lpg_ sleep_mode_alerts.1805683873 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/24.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/24.chip_sw_all_escalation_resets.1308636880 |
| Short name | T705 |
| Test name | |
| Test status | |
| Simulation time | 4879998504 ps |
| CPU time | 357.11 seconds |
| Started | Aug 24 03:57:49 PM UTC 24 |
| Finished | Aug 24 04:03:51 PM UTC 24 |
| Peak memory | 675380 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv + sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1308636880 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_es calation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.chip_sw_all_escalation_resets.1308636880 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/24.chip_sw_all_escalation_resets/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/26.chip_sw_alert_handler_lpg_sleep_mode_alerts.4105029732 |
| Short name | T665 |
| Test name | |
| Test status | |
| Simulation time | 4007495912 ps |
| CPU time | 257.26 seconds |
| Started | Aug 24 03:59:13 PM UTC 24 |
| Finished | Aug 24 04:03:34 PM UTC 24 |
| Peak memory | 673464 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_rea dy_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv _core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_handler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4105029732 -assert nopos tproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.chip_sw_alert_handler_lpg_ sleep_mode_alerts.4105029732 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/26.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/27.chip_sw_alert_handler_lpg_sleep_mode_alerts.3263945183 |
| Short name | T738 |
| Test name | |
| Test status | |
| Simulation time | 3199744680 ps |
| CPU time | 221.72 seconds |
| Started | Aug 24 04:00:14 PM UTC 24 |
| Finished | Aug 24 04:04:00 PM UTC 24 |
| Peak memory | 673216 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_rea dy_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv _core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_handler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3263945183 -assert nopos tproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.chip_sw_alert_handler_lpg_ sleep_mode_alerts.3263945183 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/27.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/28.chip_sw_all_escalation_resets.2614879375 |
| Short name | T290 |
| Test name | |
| Test status | |
| Simulation time | 4968087380 ps |
| CPU time | 417.94 seconds |
| Started | Aug 24 04:00:53 PM UTC 24 |
| Finished | Aug 24 04:07:57 PM UTC 24 |
| Peak memory | 675508 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv + sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2614879375 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_es calation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.chip_sw_all_escalation_resets.2614879375 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/28.chip_sw_all_escalation_resets/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/29.chip_sw_alert_handler_lpg_sleep_mode_alerts.2426581878 |
| Short name | T263 |
| Test name | |
| Test status | |
| Simulation time | 4295662288 ps |
| CPU time | 277.21 seconds |
| Started | Aug 24 04:02:20 PM UTC 24 |
| Finished | Aug 24 04:07:01 PM UTC 24 |
| Peak memory | 673356 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_rea dy_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv _core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_handler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2426581878 -assert nopos tproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.chip_sw_alert_handler_lpg_ sleep_mode_alerts.2426581878 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/29.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/30.chip_sw_all_escalation_resets.1916372907 |
| Short name | T294 |
| Test name | |
| Test status | |
| Simulation time | 4236621008 ps |
| CPU time | 357.66 seconds |
| Started | Aug 24 04:02:42 PM UTC 24 |
| Finished | Aug 24 04:08:44 PM UTC 24 |
| Peak memory | 675192 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv + sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1916372907 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_es calation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.chip_sw_all_escalation_resets.1916372907 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/30.chip_sw_all_escalation_resets/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/32.chip_sw_alert_handler_lpg_sleep_mode_alerts.3303378146 |
| Short name | T292 |
| Test name | |
| Test status | |
| Simulation time | 3869502512 ps |
| CPU time | 229.64 seconds |
| Started | Aug 24 04:04:23 PM UTC 24 |
| Finished | Aug 24 04:08:16 PM UTC 24 |
| Peak memory | 673276 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_rea dy_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv _core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_handler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3303378146 -assert nopos tproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.chip_sw_alert_handler_lpg_ sleep_mode_alerts.3303378146 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/32.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/32.chip_sw_all_escalation_resets.3283721906 |
| Short name | T394 |
| Test name | |
| Test status | |
| Simulation time | 5001941380 ps |
| CPU time | 455.6 seconds |
| Started | Aug 24 04:04:15 PM UTC 24 |
| Finished | Aug 24 04:11:57 PM UTC 24 |
| Peak memory | 675188 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv + sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3283721906 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_es calation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.chip_sw_all_escalation_resets.3283721906 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/32.chip_sw_all_escalation_resets/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/33.chip_sw_alert_handler_lpg_sleep_mode_alerts.2596330606 |
| Short name | T295 |
| Test name | |
| Test status | |
| Simulation time | 3770092370 ps |
| CPU time | 294.85 seconds |
| Started | Aug 24 04:04:27 PM UTC 24 |
| Finished | Aug 24 04:09:26 PM UTC 24 |
| Peak memory | 673332 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_rea dy_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv _core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_handler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2596330606 -assert nopos tproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.chip_sw_alert_handler_lpg_ sleep_mode_alerts.2596330606 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/33.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/33.chip_sw_all_escalation_resets.2774427857 |
| Short name | T395 |
| Test name | |
| Test status | |
| Simulation time | 4506049560 ps |
| CPU time | 455.12 seconds |
| Started | Aug 24 04:04:27 PM UTC 24 |
| Finished | Aug 24 04:12:08 PM UTC 24 |
| Peak memory | 675204 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv + sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2774427857 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_es calation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.chip_sw_all_escalation_resets.2774427857 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/33.chip_sw_all_escalation_resets/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/35.chip_sw_alert_handler_lpg_sleep_mode_alerts.3407847820 |
| Short name | T393 |
| Test name | |
| Test status | |
| Simulation time | 3509405110 ps |
| CPU time | 312.05 seconds |
| Started | Aug 24 04:06:19 PM UTC 24 |
| Finished | Aug 24 04:11:35 PM UTC 24 |
| Peak memory | 673528 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_rea dy_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv _core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_handler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3407847820 -assert nopos tproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.chip_sw_alert_handler_lpg_ sleep_mode_alerts.3407847820 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/35.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/35.chip_sw_all_escalation_resets.1616881063 |
| Short name | T397 |
| Test name | |
| Test status | |
| Simulation time | 5254028032 ps |
| CPU time | 446.92 seconds |
| Started | Aug 24 04:05:58 PM UTC 24 |
| Finished | Aug 24 04:13:30 PM UTC 24 |
| Peak memory | 675192 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv + sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1616881063 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_es calation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.chip_sw_all_escalation_resets.1616881063 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/35.chip_sw_all_escalation_resets/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/37.chip_sw_all_escalation_resets.3427026818 |
| Short name | T777 |
| Test name | |
| Test status | |
| Simulation time | 5160474832 ps |
| CPU time | 468.76 seconds |
| Started | Aug 24 04:07:26 PM UTC 24 |
| Finished | Aug 24 04:15:21 PM UTC 24 |
| Peak memory | 675272 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv + sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3427026818 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_es calation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.chip_sw_all_escalation_resets.3427026818 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/37.chip_sw_all_escalation_resets/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/39.chip_sw_alert_handler_lpg_sleep_mode_alerts.3343620601 |
| Short name | T399 |
| Test name | |
| Test status | |
| Simulation time | 4257810840 ps |
| CPU time | 298.07 seconds |
| Started | Aug 24 04:08:58 PM UTC 24 |
| Finished | Aug 24 04:14:00 PM UTC 24 |
| Peak memory | 673540 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_rea dy_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv _core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_handler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3343620601 -assert nopos tproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.chip_sw_alert_handler_lpg_ sleep_mode_alerts.3343620601 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/39.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/4.chip_sw_alert_handler_lpg_sleep_mode_alerts.3510999369 |
| Short name | T746 |
| Test name | |
| Test status | |
| Simulation time | 4355739584 ps |
| CPU time | 342.13 seconds |
| Started | Aug 24 03:23:31 PM UTC 24 |
| Finished | Aug 24 03:29:18 PM UTC 24 |
| Peak memory | 673228 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_rea dy_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv _core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_handler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3510999369 -assert nopos tproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.chip_sw_alert_handler_lpg_s leep_mode_alerts.3510999369 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/4.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/4.chip_sw_all_escalation_resets.3989073627 |
| Short name | T770 |
| Test name | |
| Test status | |
| Simulation time | 5313266312 ps |
| CPU time | 471.76 seconds |
| Started | Aug 24 03:14:26 PM UTC 24 |
| Finished | Aug 24 03:22:23 PM UTC 24 |
| Peak memory | 675196 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv + sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3989073627 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_es calation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.chip_sw_all_escalation_resets.3989073627 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/4.chip_sw_all_escalation_resets/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/41.chip_sw_all_escalation_resets.2583133257 |
| Short name | T763 |
| Test name | |
| Test status | |
| Simulation time | 5411707928 ps |
| CPU time | 371.18 seconds |
| Started | Aug 24 04:09:09 PM UTC 24 |
| Finished | Aug 24 04:15:25 PM UTC 24 |
| Peak memory | 675196 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv + sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2583133257 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_es calation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.chip_sw_all_escalation_resets.2583133257 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/41.chip_sw_all_escalation_resets/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/43.chip_sw_alert_handler_lpg_sleep_mode_alerts.748070643 |
| Short name | T692 |
| Test name | |
| Test status | |
| Simulation time | 4199885010 ps |
| CPU time | 291.32 seconds |
| Started | Aug 24 04:12:03 PM UTC 24 |
| Finished | Aug 24 04:16:58 PM UTC 24 |
| Peak memory | 673464 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_rea dy_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv _core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_handler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=748070643 -assert nopost proc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac es/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.chip_sw_alert_handler_lpg_s leep_mode_alerts.748070643 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/43.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/43.chip_sw_all_escalation_resets.965446880 |
| Short name | T681 |
| Test name | |
| Test status | |
| Simulation time | 4882087404 ps |
| CPU time | 458.59 seconds |
| Started | Aug 24 04:12:03 PM UTC 24 |
| Finished | Aug 24 04:19:47 PM UTC 24 |
| Peak memory | 678352 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv + sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=965446880 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_esc alation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.chip_sw_all_escalation_resets.965446880 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/43.chip_sw_all_escalation_resets/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/44.chip_sw_all_escalation_resets.1498988219 |
| Short name | T275 |
| Test name | |
| Test status | |
| Simulation time | 4744309960 ps |
| CPU time | 363.15 seconds |
| Started | Aug 24 04:12:47 PM UTC 24 |
| Finished | Aug 24 04:18:55 PM UTC 24 |
| Peak memory | 675268 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv + sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1498988219 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_es calation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.chip_sw_all_escalation_resets.1498988219 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/44.chip_sw_all_escalation_resets/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/45.chip_sw_alert_handler_lpg_sleep_mode_alerts.3511579083 |
| Short name | T749 |
| Test name | |
| Test status | |
| Simulation time | 3576109972 ps |
| CPU time | 249.12 seconds |
| Started | Aug 24 04:12:50 PM UTC 24 |
| Finished | Aug 24 04:17:02 PM UTC 24 |
| Peak memory | 673340 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_rea dy_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv _core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_handler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3511579083 -assert nopos tproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.chip_sw_alert_handler_lpg_ sleep_mode_alerts.3511579083 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/45.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/45.chip_sw_all_escalation_resets.2317497076 |
| Short name | T719 |
| Test name | |
| Test status | |
| Simulation time | 5131103384 ps |
| CPU time | 401.82 seconds |
| Started | Aug 24 04:12:49 PM UTC 24 |
| Finished | Aug 24 04:19:36 PM UTC 24 |
| Peak memory | 675512 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv + sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2317497076 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_es calation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.chip_sw_all_escalation_resets.2317497076 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/45.chip_sw_all_escalation_resets/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/46.chip_sw_alert_handler_lpg_sleep_mode_alerts.879847666 |
| Short name | T735 |
| Test name | |
| Test status | |
| Simulation time | 3403161876 ps |
| CPU time | 283.33 seconds |
| Started | Aug 24 04:13:55 PM UTC 24 |
| Finished | Aug 24 04:18:42 PM UTC 24 |
| Peak memory | 673464 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_rea dy_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv _core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_handler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=879847666 -assert nopost proc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac es/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.chip_sw_alert_handler_lpg_s leep_mode_alerts.879847666 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/46.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/48.chip_sw_alert_handler_lpg_sleep_mode_alerts.1519376 |
| Short name | T743 |
| Test name | |
| Test status | |
| Simulation time | 4188197580 ps |
| CPU time | 338.5 seconds |
| Started | Aug 24 04:15:11 PM UTC 24 |
| Finished | Aug 24 04:20:54 PM UTC 24 |
| Peak memory | 673216 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_rea dy_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv _core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_handler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1519376 -assert nopostpr oc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces /repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.chip_sw_alert_handler_lpg_sle ep_mode_alerts.1519376 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/48.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/48.chip_sw_all_escalation_resets.2157648356 |
| Short name | T722 |
| Test name | |
| Test status | |
| Simulation time | 4591847100 ps |
| CPU time | 375.98 seconds |
| Started | Aug 24 04:14:57 PM UTC 24 |
| Finished | Aug 24 04:21:18 PM UTC 24 |
| Peak memory | 675444 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv + sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2157648356 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_es calation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.chip_sw_all_escalation_resets.2157648356 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/48.chip_sw_all_escalation_resets/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/5.chip_sw_alert_handler_lpg_sleep_mode_alerts.156383728 |
| Short name | T710 |
| Test name | |
| Test status | |
| Simulation time | 4008662962 ps |
| CPU time | 311.05 seconds |
| Started | Aug 24 03:29:05 PM UTC 24 |
| Finished | Aug 24 03:34:20 PM UTC 24 |
| Peak memory | 673292 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_rea dy_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv _core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_handler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=156383728 -assert nopost proc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac es/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.chip_sw_alert_handler_lpg_sl eep_mode_alerts.156383728 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/5.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/50.chip_sw_alert_handler_lpg_sleep_mode_alerts.3867431253 |
| Short name | T697 |
| Test name | |
| Test status | |
| Simulation time | 3466171280 ps |
| CPU time | 305.53 seconds |
| Started | Aug 24 04:16:14 PM UTC 24 |
| Finished | Aug 24 04:21:24 PM UTC 24 |
| Peak memory | 673460 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_rea dy_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv _core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_handler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3867431253 -assert nopos tproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 50.chip_sw_alert_handler_lpg_ sleep_mode_alerts.3867431253 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/50.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/50.chip_sw_all_escalation_resets.3792614152 |
| Short name | T762 |
| Test name | |
| Test status | |
| Simulation time | 5852784072 ps |
| CPU time | 471.48 seconds |
| Started | Aug 24 04:16:10 PM UTC 24 |
| Finished | Aug 24 04:24:08 PM UTC 24 |
| Peak memory | 676060 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv + sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3792614152 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_es calation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 50.chip_sw_all_escalation_resets.3792614152 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/50.chip_sw_all_escalation_resets/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/53.chip_sw_all_escalation_resets.3653429020 |
| Short name | T739 |
| Test name | |
| Test status | |
| Simulation time | 5016946392 ps |
| CPU time | 408.9 seconds |
| Started | Aug 24 04:17:32 PM UTC 24 |
| Finished | Aug 24 04:24:26 PM UTC 24 |
| Peak memory | 675412 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv + sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3653429020 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_es calation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 53.chip_sw_all_escalation_resets.3653429020 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/53.chip_sw_all_escalation_resets/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/56.chip_sw_all_escalation_resets.2673528612 |
| Short name | T670 |
| Test name | |
| Test status | |
| Simulation time | 5640697326 ps |
| CPU time | 416.33 seconds |
| Started | Aug 24 04:20:21 PM UTC 24 |
| Finished | Aug 24 04:27:22 PM UTC 24 |
| Peak memory | 675956 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv + sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2673528612 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_es calation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 56.chip_sw_all_escalation_resets.2673528612 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/56.chip_sw_all_escalation_resets/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/57.chip_sw_all_escalation_resets.3146334477 |
| Short name | T736 |
| Test name | |
| Test status | |
| Simulation time | 5445201602 ps |
| CPU time | 454.97 seconds |
| Started | Aug 24 04:21:03 PM UTC 24 |
| Finished | Aug 24 04:28:44 PM UTC 24 |
| Peak memory | 675836 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv + sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3146334477 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_es calation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 57.chip_sw_all_escalation_resets.3146334477 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/57.chip_sw_all_escalation_resets/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/58.chip_sw_all_escalation_resets.3348281141 |
| Short name | T354 |
| Test name | |
| Test status | |
| Simulation time | 5151265106 ps |
| CPU time | 472.85 seconds |
| Started | Aug 24 04:22:40 PM UTC 24 |
| Finished | Aug 24 04:30:38 PM UTC 24 |
| Peak memory | 676036 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv + sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3348281141 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_es calation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 58.chip_sw_all_escalation_resets.3348281141 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/58.chip_sw_all_escalation_resets/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/61.chip_sw_alert_handler_lpg_sleep_mode_alerts.480426606 |
| Short name | T713 |
| Test name | |
| Test status | |
| Simulation time | 3965130284 ps |
| CPU time | 278.61 seconds |
| Started | Aug 24 04:22:58 PM UTC 24 |
| Finished | Aug 24 04:27:41 PM UTC 24 |
| Peak memory | 673528 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_rea dy_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv _core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_handler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=480426606 -assert nopost proc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac es/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 61.chip_sw_alert_handler_lpg_s leep_mode_alerts.480426606 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/61.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/69.chip_sw_alert_handler_lpg_sleep_mode_alerts.3599346621 |
| Short name | T752 |
| Test name | |
| Test status | |
| Simulation time | 3491231732 ps |
| CPU time | 298.69 seconds |
| Started | Aug 24 04:28:11 PM UTC 24 |
| Finished | Aug 24 04:33:14 PM UTC 24 |
| Peak memory | 673460 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_rea dy_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv _core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_handler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3599346621 -assert nopos tproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 69.chip_sw_alert_handler_lpg_ sleep_mode_alerts.3599346621 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/69.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/72.chip_sw_alert_handler_lpg_sleep_mode_alerts.1563118306 |
| Short name | T725 |
| Test name | |
| Test status | |
| Simulation time | 3693116298 ps |
| CPU time | 281.36 seconds |
| Started | Aug 24 04:29:19 PM UTC 24 |
| Finished | Aug 24 04:34:04 PM UTC 24 |
| Peak memory | 673212 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_rea dy_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv _core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_handler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1563118306 -assert nopos tproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 72.chip_sw_alert_handler_lpg_ sleep_mode_alerts.1563118306 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/72.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/74.chip_sw_alert_handler_lpg_sleep_mode_alerts.1323081987 |
| Short name | T754 |
| Test name | |
| Test status | |
| Simulation time | 3622856664 ps |
| CPU time | 245.06 seconds |
| Started | Aug 24 04:31:38 PM UTC 24 |
| Finished | Aug 24 04:35:47 PM UTC 24 |
| Peak memory | 673208 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_rea dy_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv _core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_handler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1323081987 -assert nopos tproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 74.chip_sw_alert_handler_lpg_ sleep_mode_alerts.1323081987 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/74.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/75.chip_sw_alert_handler_lpg_sleep_mode_alerts.1672639718 |
| Short name | T695 |
| Test name | |
| Test status | |
| Simulation time | 3242590112 ps |
| CPU time | 268.62 seconds |
| Started | Aug 24 04:31:33 PM UTC 24 |
| Finished | Aug 24 04:36:06 PM UTC 24 |
| Peak memory | 673456 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_rea dy_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv _core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_handler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1672639718 -assert nopos tproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 75.chip_sw_alert_handler_lpg_ sleep_mode_alerts.1672639718 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/75.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/75.chip_sw_all_escalation_resets.976706224 |
| Short name | T730 |
| Test name | |
| Test status | |
| Simulation time | 5269390928 ps |
| CPU time | 473.81 seconds |
| Started | Aug 24 04:31:38 PM UTC 24 |
| Finished | Aug 24 04:39:37 PM UTC 24 |
| Peak memory | 675900 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv + sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=976706224 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_esc alation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 75.chip_sw_all_escalation_resets.976706224 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/75.chip_sw_all_escalation_resets/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/8.chip_sw_alert_handler_lpg_sleep_mode_alerts.2801983277 |
| Short name | T669 |
| Test name | |
| Test status | |
| Simulation time | 3873183460 ps |
| CPU time | 292.61 seconds |
| Started | Aug 24 03:36:21 PM UTC 24 |
| Finished | Aug 24 03:41:18 PM UTC 24 |
| Peak memory | 673288 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_rea dy_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv _core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_handler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2801983277 -assert nopos tproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.chip_sw_alert_handler_lpg_s leep_mode_alerts.2801983277 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/8.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/83.chip_sw_all_escalation_resets.4113805896 |
| Short name | T729 |
| Test name | |
| Test status | |
| Simulation time | 4692146644 ps |
| CPU time | 408.36 seconds |
| Started | Aug 24 04:34:58 PM UTC 24 |
| Finished | Aug 24 04:41:52 PM UTC 24 |
| Peak memory | 675508 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv + sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4113805896 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_es calation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 83.chip_sw_all_escalation_resets.4113805896 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/83.chip_sw_all_escalation_resets/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/85.chip_sw_alert_handler_lpg_sleep_mode_alerts.3214357835 |
| Short name | T349 |
| Test name | |
| Test status | |
| Simulation time | 4092603694 ps |
| CPU time | 265.93 seconds |
| Started | Aug 24 04:36:52 PM UTC 24 |
| Finished | Aug 24 04:41:22 PM UTC 24 |
| Peak memory | 673476 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_rea dy_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv _core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_handler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3214357835 -assert nopos tproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 85.chip_sw_alert_handler_lpg_ sleep_mode_alerts.3214357835 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/85.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/86.chip_sw_alert_handler_lpg_sleep_mode_alerts.2583764149 |
| Short name | T769 |
| Test name | |
| Test status | |
| Simulation time | 4039979214 ps |
| CPU time | 303.03 seconds |
| Started | Aug 24 04:37:02 PM UTC 24 |
| Finished | Aug 24 04:42:09 PM UTC 24 |
| Peak memory | 673508 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_rea dy_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv _core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_handler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2583764149 -assert nopos tproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 86.chip_sw_alert_handler_lpg_ sleep_mode_alerts.2583764149 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/86.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/90.chip_sw_all_escalation_resets.129769987 |
| Short name | T277 |
| Test name | |
| Test status | |
| Simulation time | 4640553856 ps |
| CPU time | 408.16 seconds |
| Started | Aug 24 04:37:32 PM UTC 24 |
| Finished | Aug 24 04:44:25 PM UTC 24 |
| Peak memory | 675660 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv + sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=129769987 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_esc alation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 90.chip_sw_all_escalation_resets.129769987 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/90.chip_sw_all_escalation_resets/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_sleep_pin_wake.2595752544 |
| Short name | T30 |
| Test name | |
| Test status | |
| Simulation time | 5124031224 ps |
| CPU time | 228.5 seconds |
| Started | Aug 24 12:50:54 PM UTC 24 |
| Finished | Aug 24 12:54:46 PM UTC 24 |
| Peak memory | 627192 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/default/simv +use_otp_image=OtpTypeLcStProd +sw_build_device=sim_dv +sw_i mages=sleep_pin_wake_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works paces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2595752544 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sleep_pin_wake_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/def ault.vdb -cm_log /dev/null -cm_name 2.chip_sw_sleep_pin_wake.2595752544 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/2.chip_sw_sleep_pin_wake/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/12.chip_tl_errors.2551946442 |
| Short name | T562 |
| Test name | |
| Test status | |
| Simulation time | 4373486406 ps |
| CPU time | 187.88 seconds |
| Started | Aug 24 04:36:35 AM UTC 24 |
| Finished | Aug 24 04:39:46 AM UTC 24 |
| Peak memory | 623320 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enable d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2551946442 -assert nopostpro c +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.chip_tl_errors.2551946442 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/12.chip_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up.2067085146 |
| Short name | T180 |
| Test name | |
| Test status | |
| Simulation time | 5162374152 ps |
| CPU time | 358.31 seconds |
| Started | Aug 24 08:56:46 AM UTC 24 |
| Finished | Aug 24 09:02:49 AM UTC 24 |
| Peak memory | 626756 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=18_000_000 +do_random=1 +sw_build_device =sim_dv +sw_images=pwrmgr_sensor_ctrl_deep_sleep_wake_up:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2067085146 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TES T_SEQ=chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up.2067085146 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/0.chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_uart_tx_rx.1113619555 |
| Short name | T126 |
| Test name | |
| Test status | |
| Simulation time | 4873359440 ps |
| CPU time | 439.04 seconds |
| Started | Aug 24 07:38:47 AM UTC 24 |
| Finished | Aug 24 07:46:11 AM UTC 24 |
| Peak memory | 639164 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/default/simv +uart_idx=0 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw _images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1113619555 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_tx_rx_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 0.chip_sw_uart_tx_rx.1113619555 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/0.chip_sw_uart_tx_rx/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/3.chip_csr_rw.172546347 |
| Short name | T434 |
| Test name | |
| Test status | |
| Simulation time | 3828768976 ps |
| CPU time | 228.89 seconds |
| Started | Aug 24 04:03:27 AM UTC 24 |
| Finished | Aug 24 04:07:19 AM UTC 24 |
| Peak memory | 619288 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +stub_cpu=1 +cdc_instrumentation_ena bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=172546347 -assert nopostp roc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_ regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.chip_csr_rw.172546347 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/3.chip_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_tap_straps_rma.3418317404 |
| Short name | T93 |
| Test name | |
| Test status | |
| Simulation time | 6022785830 ps |
| CPU time | 386.47 seconds |
| Started | Aug 24 02:34:28 PM UTC 24 |
| Finished | Aug 24 02:40:59 PM UTC 24 |
| Peak memory | 639416 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/default/simv +create_jtag_riscv_map=1 +sw_build_device=sim_dv +sw_images= example_test_from_rom:0:test_in_rom:new_rules +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac es/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3418317404 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_tap_straps_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default.vdb - cm_log /dev/null -cm_name 2.chip_tap_straps_rma.3418317404 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/2.chip_tap_straps_rma/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/67.chip_sw_all_escalation_resets.3131186134 |
| Short name | T258 |
| Test name | |
| Test status | |
| Simulation time | 5068427730 ps |
| CPU time | 458.85 seconds |
| Started | Aug 24 04:26:31 PM UTC 24 |
| Finished | Aug 24 04:34:15 PM UTC 24 |
| Peak memory | 627328 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv + sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3131186134 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_es calation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 67.chip_sw_all_escalation_resets.3131186134 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/67.chip_sw_all_escalation_resets/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_entropy_src_csrng.2463945026 |
| Short name | T337 |
| Test name | |
| Test status | |
| Simulation time | 6480074710 ps |
| CPU time | 906.69 seconds |
| Started | Aug 24 08:22:59 AM UTC 24 |
| Finished | Aug 24 08:38:15 AM UTC 24 |
| Peak memory | 624700 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=50_000_000 +rng_srate_value_min=15 +rng_ srate_value_max=30 +sw_build_device=sim_dv +sw_images=entropy_src_csrng_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2463945026 -assert nopostproc +UVM_TESTNAME=chi p_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_2 2/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_entropy_src_csrng.2463945026 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/0.chip_sw_entropy_src_csrng/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_adc_ctrl_sleep_debug_cable_wakeup.2327295270 |
| Short name | T140 |
| Test name | |
| Test status | |
| Simulation time | 19172628604 ps |
| CPU time | 417.71 seconds |
| Started | Aug 24 08:09:12 AM UTC 24 |
| Finished | Aug 24 08:16:15 AM UTC 24 |
| Peak memory | 637180 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_i mages=adc_ctrl_sleep_debug_cable_wakeup_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2327295270 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_s w_adc_ctrl_sleep_debug_cable_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/c hip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_adc_ctrl_sleep_debug_cable_wakeup.2327295270 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/0.chip_sw_adc_ctrl_sleep_debug_cable_wakeup/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_sram_ctrl_execution_main.494794133 |
| Short name | T219 |
| Test name | |
| Test status | |
| Simulation time | 6233925098 ps |
| CPU time | 412.09 seconds |
| Started | Aug 24 08:38:09 AM UTC 24 |
| Finished | Aug 24 08:45:06 AM UTC 24 |
| Peak memory | 626680 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=sram_ctrl_execution_main_ test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=494794133 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sram_ctrl_execution_main_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm _log /dev/null -cm_name 0.chip_sw_sram_ctrl_execution_main.494794133 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/0.chip_sw_sram_ctrl_execution_main/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_sysrst_ctrl_ec_rst_l.1740610083 |
| Short name | T44 |
| Test name | |
| Test status | |
| Simulation time | 21022615577 ps |
| CPU time | 2332.05 seconds |
| Started | Aug 24 08:06:29 AM UTC 24 |
| Finished | Aug 24 08:45:45 AM UTC 24 |
| Peak memory | 629984 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=sysrst_ctrl_ec_rst_l_test :1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/si m.tcl +ntb_random_seed=1740610083 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sysrst_ctrl_ec_rst_l_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /d ev/null -cm_name 0.chip_sw_sysrst_ctrl_ec_rst_l.1740610083 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/0.chip_sw_sysrst_ctrl_ec_rst_l/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/1.xbar_unmapped_addr.127663522 |
| Short name | T538 |
| Test name | |
| Test status | |
| Simulation time | 994095297 ps |
| CPU time | 30.76 seconds |
| Started | Aug 24 03:53:17 AM UTC 24 |
| Finished | Aug 24 03:53:49 AM UTC 24 |
| Peak memory | 597836 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=127663522 -assert nopostproc +UVM_TESTNAME =xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.xbar_unmapped_addr.127663522 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/1.xbar_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/16.chip_tl_errors.2441792281 |
| Short name | T649 |
| Test name | |
| Test status | |
| Simulation time | 3460538584 ps |
| CPU time | 157.17 seconds |
| Started | Aug 24 04:53:58 AM UTC 24 |
| Finished | Aug 24 04:56:38 AM UTC 24 |
| Peak memory | 623328 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enable d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2441792281 -assert nopostpro c +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.chip_tl_errors.2441792281 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/16.chip_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/19.xbar_access_same_device.1550945396 |
| Short name | T501 |
| Test name | |
| Test status | |
| Simulation time | 1712598625 ps |
| CPU time | 58.07 seconds |
| Started | Aug 24 05:06:45 AM UTC 24 |
| Finished | Aug 24 05:07:45 AM UTC 24 |
| Peak memory | 597708 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1550945396 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.xbar_access_same_device.1550945396 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/19.xbar_access_same_device/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/25.xbar_same_source.4260187040 |
| Short name | T527 |
| Test name | |
| Test status | |
| Simulation time | 415225332 ps |
| CPU time | 23.61 seconds |
| Started | Aug 24 05:23:37 AM UTC 24 |
| Finished | Aug 24 05:24:02 AM UTC 24 |
| Peak memory | 597752 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4260187040 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.xbar_same_source.4260187040 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/25.xbar_same_source/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/30.xbar_stress_all_with_reset_error.4071098672 |
| Short name | T604 |
| Test name | |
| Test status | |
| Simulation time | 7176858392 ps |
| CPU time | 461.21 seconds |
| Started | Aug 24 05:35:27 AM UTC 24 |
| Finished | Aug 24 05:43:13 AM UTC 24 |
| Peak memory | 597820 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4071098672 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.xbar_stress_all_with_reset_error.4071098672 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/30.xbar_stress_all_with_reset_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/6.xbar_stress_all_with_reset_error.793432494 |
| Short name | T811 |
| Test name | |
| Test status | |
| Simulation time | 2579743787 ps |
| CPU time | 150.98 seconds |
| Started | Aug 24 04:16:26 AM UTC 24 |
| Finished | Aug 24 04:18:59 AM UTC 24 |
| Peak memory | 597940 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=793432494 -assert nopostproc +UVM_TESTNAME =xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.xbar_stress_all_with_reset_error.793432494 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/6.xbar_stress_all_with_reset_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_pwrmgr_lowpower_cancel.1134000132 |
| Short name | T367 |
| Test name | |
| Test status | |
| Simulation time | 3674560956 ps |
| CPU time | 320.95 seconds |
| Started | Aug 24 08:56:03 AM UTC 24 |
| Finished | Aug 24 09:01:29 AM UTC 24 |
| Peak memory | 624624 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=pwrmgr_lowpower_cancel_te st:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/ sim.tcl +ntb_random_seed=1134000132 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tg l+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_na me 0.chip_sw_pwrmgr_lowpower_cancel.1134000132 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/0.chip_sw_pwrmgr_lowpower_cancel/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_rv_core_ibex_nmi_irq.4075531237 |
| Short name | T402 |
| Test name | |
| Test status | |
| Simulation time | 4951549490 ps |
| CPU time | 543.15 seconds |
| Started | Aug 24 08:13:24 AM UTC 24 |
| Finished | Aug 24 08:22:34 AM UTC 24 |
| Peak memory | 625048 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=10_000_000 +sw_build_device=sim_dv +sw_i mages=rv_core_ibex_nmi_irq_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4075531237 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default .vdb -cm_log /dev/null -cm_name 0.chip_sw_rv_core_ibex_nmi_irq.4075531237 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/0.chip_sw_rv_core_ibex_nmi_irq/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/4.chip_csr_hw_reset.675543346 |
| Short name | T179 |
| Test name | |
| Test status | |
| Simulation time | 5318769344 ps |
| CPU time | 208.79 seconds |
| Started | Aug 24 04:08:13 AM UTC 24 |
| Finished | Aug 24 04:11:45 AM UTC 24 |
| Peak memory | 683156 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +stub_cpu=1 +cdc_instrumentati on_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=675543346 -assert n opostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.chip_csr_hw_reset.675543346 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/4.chip_csr_hw_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_flash_init.3384234946 |
| Short name | T212 |
| Test name | |
| Test status | |
| Simulation time | 22271717647 ps |
| CPU time | 1528.76 seconds |
| Started | Aug 24 07:47:02 AM UTC 24 |
| Finished | Aug 24 08:12:48 AM UTC 24 |
| Peak memory | 629304 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=25_000_000 +sw_build_device=sim_dv +sw_i mages=flash_init_test:0:test_in_rom:new_rules +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac es/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3384234946 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_flash_init_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default.vd b -cm_log /dev/null -cm_name 0.chip_sw_flash_init.3384234946 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/0.chip_sw_flash_init/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_keymgr_sideload_otbn.2512639158 |
| Short name | T316 |
| Test name | |
| Test status | |
| Simulation time | 14340533580 ps |
| CPU time | 2670.91 seconds |
| Started | Aug 24 08:30:25 AM UTC 24 |
| Finished | Aug 24 09:15:24 AM UTC 24 |
| Peak memory | 629792 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=20_000_000 +sw_build_device=sim_dv +sw_i mages=keymgr_sideload_otbn_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2512639158 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default .vdb -cm_log /dev/null -cm_name 0.chip_sw_keymgr_sideload_otbn.2512639158 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/0.chip_sw_keymgr_sideload_otbn/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_lc_ctrl_program_error.1131444280 |
| Short name | T209 |
| Test name | |
| Test status | |
| Simulation time | 4731377000 ps |
| CPU time | 323.39 seconds |
| Started | Aug 24 08:55:36 AM UTC 24 |
| Finished | Aug 24 09:01:03 AM UTC 24 |
| Peak memory | 626636 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/default/simv +en_scb=0 +bypass_alert_ready_to_end_check=1 +sw_build_devic e=sim_dv +sw_images=lc_ctrl_program_error:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1131444280 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_l c_ctrl_program_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_as ic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_lc_ctrl_program_error.1131444280 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/0.chip_sw_lc_ctrl_program_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_pwrmgr_deep_sleep_power_glitch_reset.1943217707 |
| Short name | T155 |
| Test name | |
| Test status | |
| Simulation time | 6835641156 ps |
| CPU time | 259.76 seconds |
| Started | Aug 24 07:59:49 AM UTC 24 |
| Finished | Aug 24 08:04:12 AM UTC 24 |
| Peak memory | 632852 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv + sw_images=pwrmgr_deep_sleep_power_glitch_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu eue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1943217707 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_ sw_deep_power_glitch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_as ic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_pwrmgr_deep_sleep_power_glitch_reset.1943217707 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/0.chip_sw_pwrmgr_deep_sleep_power_glitch_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_otp_ctrl_vendor_test_csr_access.2954391279 |
| Short name | T201 |
| Test name | |
| Test status | |
| Simulation time | 3013408825 ps |
| CPU time | 127.61 seconds |
| Started | Aug 24 01:21:21 PM UTC 24 |
| Finished | Aug 24 01:23:31 PM UTC 24 |
| Peak memory | 640952 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=otp_ctrl_vendor_test_csr_ access_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/ dv/tools/sim.tcl +ntb_random_seed=2954391279 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_otp_ctrl_vendor_test_csr_access _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/ default.vdb -cm_log /dev/null -cm_name 2.chip_sw_otp_ctrl_vendor_test_csr_access.2954391279 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/2.chip_sw_otp_ctrl_vendor_test_csr_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/18.chip_tl_errors.2709388663 |
| Short name | T560 |
| Test name | |
| Test status | |
| Simulation time | 4245291437 ps |
| CPU time | 252.5 seconds |
| Started | Aug 24 05:01:34 AM UTC 24 |
| Finished | Aug 24 05:05:50 AM UTC 24 |
| Peak memory | 623472 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enable d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2709388663 -assert nopostpro c +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.chip_tl_errors.2709388663 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/18.chip_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/25.xbar_error_random.2056477398 |
| Short name | T606 |
| Test name | |
| Test status | |
| Simulation time | 2167254554 ps |
| CPU time | 49.14 seconds |
| Started | Aug 24 05:23:42 AM UTC 24 |
| Finished | Aug 24 05:24:32 AM UTC 24 |
| Peak memory | 598048 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2056477398 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.xbar_error_random.2056477398 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/25.xbar_error_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/27.xbar_stress_all_with_error.3396339614 |
| Short name | T603 |
| Test name | |
| Test status | |
| Simulation time | 9531813920 ps |
| CPU time | 239.56 seconds |
| Started | Aug 24 05:29:31 AM UTC 24 |
| Finished | Aug 24 05:33:34 AM UTC 24 |
| Peak memory | 598024 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3396339614 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.xbar_stress_all_with_error.3396339614 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/27.xbar_stress_all_with_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/30.xbar_stress_all_with_error.3834201869 |
| Short name | T601 |
| Test name | |
| Test status | |
| Simulation time | 11725495734 ps |
| CPU time | 295.49 seconds |
| Started | Aug 24 05:35:14 AM UTC 24 |
| Finished | Aug 24 05:40:13 AM UTC 24 |
| Peak memory | 598084 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3834201869 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.xbar_stress_all_with_error.3834201869 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/30.xbar_stress_all_with_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/38.xbar_error_random.2554877462 |
| Short name | T597 |
| Test name | |
| Test status | |
| Simulation time | 2698854041 ps |
| CPU time | 68.04 seconds |
| Started | Aug 24 05:52:22 AM UTC 24 |
| Finished | Aug 24 05:53:31 AM UTC 24 |
| Peak memory | 597812 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2554877462 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.xbar_error_random.2554877462 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/38.xbar_error_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/52.xbar_stress_all_with_reset_error.3365353055 |
| Short name | T610 |
| Test name | |
| Test status | |
| Simulation time | 4128614880 ps |
| CPU time | 272.35 seconds |
| Started | Aug 24 06:16:24 AM UTC 24 |
| Finished | Aug 24 06:21:00 AM UTC 24 |
| Peak memory | 597764 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3365353055 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 52.xbar_stress_all_with_reset_error.3365353055 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/52.xbar_stress_all_with_reset_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/61.xbar_stress_all_with_reset_error.2102030724 |
| Short name | T612 |
| Test name | |
| Test status | |
| Simulation time | 6361851753 ps |
| CPU time | 240.81 seconds |
| Started | Aug 24 06:31:11 AM UTC 24 |
| Finished | Aug 24 06:35:16 AM UTC 24 |
| Peak memory | 598116 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2102030724 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 61.xbar_stress_all_with_reset_error.2102030724 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/61.xbar_stress_all_with_reset_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/7.xbar_error_random.318558926 |
| Short name | T609 |
| Test name | |
| Test status | |
| Simulation time | 617983093 ps |
| CPU time | 37.17 seconds |
| Started | Aug 24 04:20:59 AM UTC 24 |
| Finished | Aug 24 04:21:38 AM UTC 24 |
| Peak memory | 597696 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=318558926 -assert nopostproc +UVM_TESTNAME =xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.xbar_error_random.318558926 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/7.xbar_error_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/73.xbar_stress_all_with_error.3415452833 |
| Short name | T644 |
| Test name | |
| Test status | |
| Simulation time | 1317890951 ps |
| CPU time | 67.27 seconds |
| Started | Aug 24 06:49:52 AM UTC 24 |
| Finished | Aug 24 06:51:01 AM UTC 24 |
| Peak memory | 597952 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3415452833 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 73.xbar_stress_all_with_error.3415452833 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/73.xbar_stress_all_with_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/74.xbar_stress_all_with_reset_error.3923029072 |
| Short name | T600 |
| Test name | |
| Test status | |
| Simulation time | 6764794456 ps |
| CPU time | 218.89 seconds |
| Started | Aug 24 06:52:13 AM UTC 24 |
| Finished | Aug 24 06:55:55 AM UTC 24 |
| Peak memory | 597828 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3923029072 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 74.xbar_stress_all_with_reset_error.3923029072 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/74.xbar_stress_all_with_reset_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/75.xbar_error_random.919250056 |
| Short name | T598 |
| Test name | |
| Test status | |
| Simulation time | 300222866 ps |
| CPU time | 17.19 seconds |
| Started | Aug 24 06:53:58 AM UTC 24 |
| Finished | Aug 24 06:54:16 AM UTC 24 |
| Peak memory | 597696 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=919250056 -assert nopostproc +UVM_TESTNAME =xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 75.xbar_error_random.919250056 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/75.xbar_error_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/8.xbar_error_and_unmapped_addr.633717262 |
| Short name | T602 |
| Test name | |
| Test status | |
| Simulation time | 1068017406 ps |
| CPU time | 29.67 seconds |
| Started | Aug 24 04:23:48 AM UTC 24 |
| Finished | Aug 24 04:24:18 AM UTC 24 |
| Peak memory | 597948 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=633717262 -assert nopostproc +UVM_TESTNAME =xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.xbar_error_and_unmapped_addr.633717262 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/8.xbar_error_and_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/80.xbar_stress_all_with_error.2818197064 |
| Short name | T611 |
| Test name | |
| Test status | |
| Simulation time | 5024553424 ps |
| CPU time | 251.13 seconds |
| Started | Aug 24 07:02:49 AM UTC 24 |
| Finished | Aug 24 07:07:04 AM UTC 24 |
| Peak memory | 597824 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2818197064 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 80.xbar_stress_all_with_error.2818197064 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/80.xbar_stress_all_with_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/93.xbar_stress_all_with_error.4015046637 |
| Short name | T607 |
| Test name | |
| Test status | |
| Simulation time | 11799914037 ps |
| CPU time | 285.39 seconds |
| Started | Aug 24 07:23:31 AM UTC 24 |
| Finished | Aug 24 07:28:20 AM UTC 24 |
| Peak memory | 597828 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4015046637 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 93.xbar_stress_all_with_error.4015046637 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/93.xbar_stress_all_with_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_pattgen_ios.4154621706 |
| Short name | T135 |
| Test name | |
| Test status | |
| Simulation time | 3679125796 ps |
| CPU time | 170.27 seconds |
| Started | Aug 24 10:57:12 AM UTC 24 |
| Finished | Aug 24 11:00:05 AM UTC 24 |
| Peak memory | 624556 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=5_000_000 +sw_build_device=sim_dv +sw_im ages=pattgen_ios_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace s/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4154621706 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_patt_ios_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default.vdb - cm_log /dev/null -cm_name 1.chip_sw_pattgen_ios.4154621706 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/1.chip_sw_pattgen_ios/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_gpio.916658455 |
| Short name | T47 |
| Test name | |
| Test status | |
| Simulation time | 4587088536 ps |
| CPU time | 356.46 seconds |
| Started | Aug 24 01:10:39 PM UTC 24 |
| Finished | Aug 24 01:16:40 PM UTC 24 |
| Peak memory | 627060 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=gpio_test:1:new_rules,tes t_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_rando m_seed=916658455 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_gpio_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_gpio.916658455 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/2.chip_sw_gpio/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_plic_sw_irq.2458964537 |
| Short name | T268 |
| Test name | |
| Test status | |
| Simulation time | 3387315500 ps |
| CPU time | 208.14 seconds |
| Started | Aug 24 08:43:17 AM UTC 24 |
| Finished | Aug 24 08:46:48 AM UTC 24 |
| Peak memory | 624564 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=plic_sw_irq_test:1:new_ru les,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +nt b_random_seed=2458964537 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as sert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_s w_plic_sw_irq.2458964537 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/0.chip_sw_plic_sw_irq/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_alert_handler_ping_ok.3449938737 |
| Short name | T645 |
| Test name | |
| Test status | |
| Simulation time | 8200273804 ps |
| CPU time | 814.66 seconds |
| Started | Aug 24 08:16:07 AM UTC 24 |
| Finished | Aug 24 08:29:52 AM UTC 24 |
| Peak memory | 624828 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/default/simv +en_scb=0 +sw_test_timeout_ns=24000000 +sw_build_device=sim_ dv +sw_images=alert_handler_ping_ok_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3449938737 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_ba se_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_alert_handler_ping_ok.3449938737 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/0.chip_sw_alert_handler_ping_ok/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_clkmgr_off_aes_trans.1068834583 |
| Short name | T311 |
| Test name | |
| Test status | |
| Simulation time | 4020904004 ps |
| CPU time | 361.4 seconds |
| Started | Aug 24 08:45:01 AM UTC 24 |
| Finished | Aug 24 08:51:07 AM UTC 24 |
| Peak memory | 624568 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=clkmgr_off_aes_trans_test :1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/si m.tcl +ntb_random_seed=1068834583 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_clkmgr_off_aes_trans.1068834583 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/0.chip_sw_clkmgr_off_aes_trans/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_csrng_edn_concurrency_reduced_freq.1056470704 |
| Short name | T142 |
| Test name | |
| Test status | |
| Simulation time | 81048910567 ps |
| CPU time | 10622.6 seconds |
| Started | Aug 24 09:05:53 AM UTC 24 |
| Finished | Aug 24 12:04:48 PM UTC 24 |
| Peak memory | 629948 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=360_000_000 +rng_srate_value_min=15 +rng _srate_value_max=20 +cal_sys_clk_70mhz=1 +en_jitter=1 +accelerate_cold_power_up_time=3 +accelerate_regulators_power_up_time=2 +sw_build_device=sim _dv +sw_images=csrng_edn_concurrency_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1056470704 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_b ase_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/covera ge/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_csrng_edn_concurrency_reduced_freq.1056470704 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/0.chip_sw_csrng_edn_concurrency_reduced_freq/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_edn_boot_mode.1492643127 |
| Short name | T156 |
| Test name | |
| Test status | |
| Simulation time | 3252948332 ps |
| CPU time | 390.01 seconds |
| Started | Aug 24 08:19:22 AM UTC 24 |
| Finished | Aug 24 08:25:57 AM UTC 24 |
| Peak memory | 624888 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=18_000_000 +rng_srate_value=5 +accelerat e_cold_power_up_time=3 +accelerate_regulators_power_up_time=2 +sw_build_device=sim_dv +sw_images=edn_boot_mode:1:new_rules,test_rom:0 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1492643127 -a ssert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re po/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_edn_boot_mode.1492643127 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/0.chip_sw_edn_boot_mode/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_otbn_mem_scramble.1416554297 |
| Short name | T223 |
| Test name | |
| Test status | |
| Simulation time | 3271751896 ps |
| CPU time | 330.68 seconds |
| Started | Aug 24 08:12:45 AM UTC 24 |
| Finished | Aug 24 08:18:20 AM UTC 24 |
| Peak memory | 626616 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=15_000_000 +en_scb_tl_err_chk=0 +bypass_ alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=otbn_mem_scramble_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1416554297 -assert nopostproc +UVM_TEST NAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_otbn_mem_scramble.1416554297 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/0.chip_sw_otbn_mem_scramble/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_rv_core_ibex_lockstep_glitch.1110597753 |
| Short name | T417 |
| Test name | |
| Test status | |
| Simulation time | 2858940784 ps |
| CPU time | 121.95 seconds |
| Started | Aug 24 09:02:10 AM UTC 24 |
| Finished | Aug 24 09:04:14 AM UTC 24 |
| Peak memory | 666428 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/default/simv +disable_assert_final_checks +sw_build_device=sim_dv +sw_ima ges=aes_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/re po/hw/dv/tools/sim.tcl +ntb_random_seed=1110597753 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rv_core_ibex_lockstep_gli tch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/covera ge/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_rv_core_ibex_lockstep_glitch.1110597753 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/0.chip_sw_rv_core_ibex_lockstep_glitch/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/0.rom_e2e_boot_policy_valid_a_bad_b_good_dev.3893768003 |
| Short name | T416 |
| Test name | |
| Test status | |
| Simulation time | 24101823680 ps |
| CPU time | 5274.32 seconds |
| Started | Aug 24 09:17:27 AM UTC 24 |
| Finished | Aug 24 10:46:14 AM UTC 24 |
| Peak memory | 629856 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=100_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a_corrupted:1:ot_flash_binary:signed:fake_ecdsa_prod_key_0,empty_test_slot_b_fake_ecdsa_prod_k ey_0:2:ot_flash_binary,otp_img_boot_policy_valid_dev:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3893768003 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_ base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover age/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_boot_policy_valid_a_bad_b_good_dev.3893768003 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_bad_b_good_dev/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/0.chip_csr_aliasing.3009762179 |
| Short name | T1491 |
| Test name | |
| Test status | |
| Simulation time | 28782994067 ps |
| CPU time | 4313.52 seconds |
| Started | Aug 24 03:44:04 AM UTC 24 |
| Finished | Aug 24 04:56:43 AM UTC 24 |
| Peak memory | 620388 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +test_timeout_ns=120_000_000 +csr_aliasing +en_scb=0 + stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=3009762179 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.chip_ csr_aliasing.3009762179 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/0.chip_csr_aliasing/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/0.chip_csr_bit_bash.4178250222 |
| Short name | T642 |
| Test name | |
| Test status | |
| Simulation time | 6405161500 ps |
| CPU time | 393.02 seconds |
| Started | Aug 24 03:44:02 AM UTC 24 |
| Finished | Aug 24 03:50:40 AM UTC 24 |
| Peak memory | 613396 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +test_timeout_ns=120_000_000 +num_test_csrs=200 +csr_b it_bash +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/to ols/sim.tcl +ntb_random_seed=4178250222 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/nu ll -cm_name 0.chip_csr_bit_bash.4178250222 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/0.chip_csr_bit_bash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/0.chip_csr_mem_rw_with_rand_reset.586639129 |
| Short name | T408 |
| Test name | |
| Test status | |
| Simulation time | 7149891420 ps |
| CPU time | 296.76 seconds |
| Started | Aug 24 03:49:09 AM UTC 24 |
| Finished | Aug 24 03:54:10 AM UTC 24 |
| Peak memory | 662360 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000 000000 +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/too ls/sim.tcl +ntb_random_seed=586639129 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.chip_csr_mem_rw_with_rand_reset.586639129 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/0.chip_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/0.chip_csr_rw.3783905774 |
| Short name | T409 |
| Test name | |
| Test status | |
| Simulation time | 4546272642 ps |
| CPU time | 254.74 seconds |
| Started | Aug 24 03:48:15 AM UTC 24 |
| Finished | Aug 24 03:52:33 AM UTC 24 |
| Peak memory | 619228 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +stub_cpu=1 +cdc_instrumentation_ena bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3783905774 -assert nopost proc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os _regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.chip_csr_rw.3783905774 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/0.chip_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/0.chip_prim_tl_access.1648772879 |
| Short name | T1343 |
| Test name | |
| Test status | |
| Simulation time | 4874970440 ps |
| CPU time | 145.37 seconds |
| Started | Aug 24 03:44:43 AM UTC 24 |
| Finished | Aug 24 03:47:11 AM UTC 24 |
| Peak memory | 609220 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +en_scb=0 +en_scb_tl_err_chk=0 +stub_cpu=1 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1648772879 - assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_prim_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works paces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.chip_prim_tl_access.1648772879 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/0.chip_prim_tl_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/0.chip_rv_dm_lc_disabled.3579355922 |
| Short name | T1344 |
| Test name | |
| Test status | |
| Simulation time | 6942579721 ps |
| CPU time | 232.43 seconds |
| Started | Aug 24 03:44:58 AM UTC 24 |
| Finished | Aug 24 03:48:54 AM UTC 24 |
| Peak memory | 608716 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +en_scb=0 +en_scb_tl_err_chk=0 +use_jtag_dmi=1 +stub_c pu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s eed=3579355922 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_rv_dm_lc_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as sert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0. chip_rv_dm_lc_disabled.3579355922 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/0.chip_rv_dm_lc_disabled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/0.chip_same_csr_outstanding.2644814268 |
| Short name | T404 |
| Test name | |
| Test status | |
| Simulation time | 16576358560 ps |
| CPU time | 1336.94 seconds |
| Started | Aug 24 03:44:12 AM UTC 24 |
| Finished | Aug 24 04:06:43 AM UTC 24 |
| Peak memory | 613148 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +test_timeout_ns=120_000_000 +run_same_csr_outstanding +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim .tcl +ntb_random_seed=2644814268 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_ name 0.chip_same_csr_outstanding.2644814268 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/0.chip_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/0.chip_tl_errors.1105115296 |
| Short name | T105 |
| Test name | |
| Test status | |
| Simulation time | 3362027010 ps |
| CPU time | 130.56 seconds |
| Started | Aug 24 03:44:19 AM UTC 24 |
| Finished | Aug 24 03:46:32 AM UTC 24 |
| Peak memory | 623324 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enable d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1105115296 -assert nopostpro c +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.chip_tl_errors.1105115296 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/0.chip_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/0.xbar_error_and_unmapped_addr.1911675556 |
| Short name | T266 |
| Test name | |
| Test status | |
| Simulation time | 104499128 ps |
| CPU time | 9.82 seconds |
| Started | Aug 24 03:47:35 AM UTC 24 |
| Finished | Aug 24 03:47:46 AM UTC 24 |
| Peak memory | 597820 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1911675556 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.xbar_error_and_unmapped_addr.1911675556 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/0.xbar_error_and_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/0.xbar_error_random.2841353926 |
| Short name | T267 |
| Test name | |
| Test status | |
| Simulation time | 598655442 ps |
| CPU time | 34.8 seconds |
| Started | Aug 24 03:47:16 AM UTC 24 |
| Finished | Aug 24 03:47:52 AM UTC 24 |
| Peak memory | 597884 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2841353926 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.xbar_error_random.2841353926 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/0.xbar_error_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/0.xbar_random_zero_delays.889446056 |
| Short name | T162 |
| Test name | |
| Test status | |
| Simulation time | 199859383 ps |
| CPU time | 15.19 seconds |
| Started | Aug 24 03:46:26 AM UTC 24 |
| Finished | Aug 24 03:46:43 AM UTC 24 |
| Peak memory | 597696 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=889446056 -assert nopostpro c +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.xbar_random_zero_delays.889446056 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/0.xbar_random_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/0.xbar_same_source.1364415493 |
| Short name | T411 |
| Test name | |
| Test status | |
| Simulation time | 363108545 ps |
| CPU time | 10.24 seconds |
| Started | Aug 24 03:47:10 AM UTC 24 |
| Finished | Aug 24 03:47:21 AM UTC 24 |
| Peak memory | 597680 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1364415493 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.xbar_same_source.1364415493 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/0.xbar_same_source/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/0.xbar_smoke_large_delays.2023994591 |
| Short name | T163 |
| Test name | |
| Test status | |
| Simulation time | 8567449403 ps |
| CPU time | 68.19 seconds |
| Started | Aug 24 03:45:46 AM UTC 24 |
| Finished | Aug 24 03:46:56 AM UTC 24 |
| Peak memory | 596148 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max _device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2023994591 -assert nopostproc +U VM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.xbar_smoke_large_delays.2023994591 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/0.xbar_smoke_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/0.xbar_smoke_slow_rsp.1854343284 |
| Short name | T187 |
| Test name | |
| Test status | |
| Simulation time | 4948829455 ps |
| CPU time | 58.23 seconds |
| Started | Aug 24 03:45:47 AM UTC 24 |
| Finished | Aug 24 03:46:47 AM UTC 24 |
| Peak memory | 596020 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1854343284 -assert nopostproc +UVM_T ESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.xbar_smoke_slow_rsp.1854343284 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/0.xbar_smoke_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/0.xbar_smoke_zero_delays.3447159086 |
| Short name | T103 |
| Test name | |
| Test status | |
| Simulation time | 46923107 ps |
| CPU time | 5.11 seconds |
| Started | Aug 24 03:45:27 AM UTC 24 |
| Finished | Aug 24 03:45:33 AM UTC 24 |
| Peak memory | 595636 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3447159086 -assert nopostpr oc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.xbar_smoke_zero_delays.3447159086 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/0.xbar_smoke_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/0.xbar_stress_all.1005955182 |
| Short name | T440 |
| Test name | |
| Test status | |
| Simulation time | 1969099976 ps |
| CPU time | 131.36 seconds |
| Started | Aug 24 03:47:52 AM UTC 24 |
| Finished | Aug 24 03:50:05 AM UTC 24 |
| Peak memory | 597840 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1005955182 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.xbar_stress_all.1005955182 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/0.xbar_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/0.xbar_stress_all_with_rand_reset.3291915635 |
| Short name | T551 |
| Test name | |
| Test status | |
| Simulation time | 356960955 ps |
| CPU time | 83.99 seconds |
| Started | Aug 24 03:47:56 AM UTC 24 |
| Finished | Aug 24 03:49:22 AM UTC 24 |
| Peak memory | 597692 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3291915635 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.xbar_stress_all_with_rand_reset.3291915635 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/0.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/0.xbar_stress_all_with_reset_error.1993587740 |
| Short name | T549 |
| Test name | |
| Test status | |
| Simulation time | 5016502657 ps |
| CPU time | 198.01 seconds |
| Started | Aug 24 03:48:06 AM UTC 24 |
| Finished | Aug 24 03:51:27 AM UTC 24 |
| Peak memory | 597876 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1993587740 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.xbar_stress_all_with_reset_error.1993587740 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/0.xbar_stress_all_with_reset_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/0.xbar_unmapped_addr.1926929288 |
| Short name | T550 |
| Test name | |
| Test status | |
| Simulation time | 106179075 ps |
| CPU time | 11.11 seconds |
| Started | Aug 24 03:47:25 AM UTC 24 |
| Finished | Aug 24 03:47:37 AM UTC 24 |
| Peak memory | 597692 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1926929288 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.xbar_unmapped_addr.1926929288 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/0.xbar_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/1.chip_csr_aliasing.1581441445 |
| Short name | T1811 |
| Test name | |
| Test status | |
| Simulation time | 65246888470 ps |
| CPU time | 7197.74 seconds |
| Started | Aug 24 03:49:36 AM UTC 24 |
| Finished | Aug 24 05:50:44 AM UTC 24 |
| Peak memory | 661212 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +test_timeout_ns=120_000_000 +csr_aliasing +en_scb=0 + stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=1581441445 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.chip_ csr_aliasing.1581441445 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/1.chip_csr_aliasing/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/1.chip_csr_bit_bash.2455404438 |
| Short name | T413 |
| Test name | |
| Test status | |
| Simulation time | 11453281632 ps |
| CPU time | 809.46 seconds |
| Started | Aug 24 03:49:34 AM UTC 24 |
| Finished | Aug 24 04:03:13 AM UTC 24 |
| Peak memory | 611352 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +test_timeout_ns=120_000_000 +num_test_csrs=200 +csr_b it_bash +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/to ols/sim.tcl +ntb_random_seed=2455404438 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/nu ll -cm_name 1.chip_csr_bit_bash.2455404438 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/1.chip_csr_bit_bash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/1.chip_csr_mem_rw_with_rand_reset.1569555868 |
| Short name | T433 |
| Test name | |
| Test status | |
| Simulation time | 6302349787 ps |
| CPU time | 355.71 seconds |
| Started | Aug 24 03:54:11 AM UTC 24 |
| Finished | Aug 24 04:00:11 AM UTC 24 |
| Peak memory | 662592 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000 000000 +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/too ls/sim.tcl +ntb_random_seed=1569555868 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/nul l -cm_name 1.chip_csr_mem_rw_with_rand_reset.1569555868 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/1.chip_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/1.chip_csr_rw.1941665249 |
| Short name | T183 |
| Test name | |
| Test status | |
| Simulation time | 5431847189 ps |
| CPU time | 404.73 seconds |
| Started | Aug 24 03:54:03 AM UTC 24 |
| Finished | Aug 24 04:00:53 AM UTC 24 |
| Peak memory | 619456 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +stub_cpu=1 +cdc_instrumentation_ena bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1941665249 -assert nopost proc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os _regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.chip_csr_rw.1941665249 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/1.chip_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/1.chip_prim_tl_access.1483736334 |
| Short name | T1346 |
| Test name | |
| Test status | |
| Simulation time | 6584472608 ps |
| CPU time | 204.68 seconds |
| Started | Aug 24 03:50:19 AM UTC 24 |
| Finished | Aug 24 03:53:47 AM UTC 24 |
| Peak memory | 608972 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +en_scb=0 +en_scb_tl_err_chk=0 +stub_cpu=1 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1483736334 - assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_prim_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works paces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.chip_prim_tl_access.1483736334 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/1.chip_prim_tl_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/1.chip_rv_dm_lc_disabled.2330588570 |
| Short name | T1347 |
| Test name | |
| Test status | |
| Simulation time | 12527424031 ps |
| CPU time | 322.68 seconds |
| Started | Aug 24 03:50:37 AM UTC 24 |
| Finished | Aug 24 03:56:04 AM UTC 24 |
| Peak memory | 618956 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +en_scb=0 +en_scb_tl_err_chk=0 +use_jtag_dmi=1 +stub_c pu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s eed=2330588570 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_rv_dm_lc_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as sert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1. chip_rv_dm_lc_disabled.2330588570 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/1.chip_rv_dm_lc_disabled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/1.chip_same_csr_outstanding.3941408413 |
| Short name | T1439 |
| Test name | |
| Test status | |
| Simulation time | 29363662110 ps |
| CPU time | 3095.65 seconds |
| Started | Aug 24 03:50:12 AM UTC 24 |
| Finished | Aug 24 04:42:20 AM UTC 24 |
| Peak memory | 614108 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +test_timeout_ns=120_000_000 +run_same_csr_outstanding +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim .tcl +ntb_random_seed=3941408413 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_ name 1.chip_same_csr_outstanding.3941408413 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/1.chip_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/1.xbar_access_same_device.1916655372 |
| Short name | T677 |
| Test name | |
| Test status | |
| Simulation time | 1104357270 ps |
| CPU time | 34.56 seconds |
| Started | Aug 24 03:52:42 AM UTC 24 |
| Finished | Aug 24 03:53:18 AM UTC 24 |
| Peak memory | 597708 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1916655372 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.xbar_access_same_device.1916655372 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/1.xbar_access_same_device/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/1.xbar_access_same_device_slow_rsp.1615991302 |
| Short name | T643 |
| Test name | |
| Test status | |
| Simulation time | 6149645001 ps |
| CPU time | 75.82 seconds |
| Started | Aug 24 03:52:47 AM UTC 24 |
| Finished | Aug 24 03:54:05 AM UTC 24 |
| Peak memory | 598072 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1615991302 -assert nopostproc +UVM_T ESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.xbar_access_same_device_slow_rsp.1615991302 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/1.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/1.xbar_error_and_unmapped_addr.1878943318 |
| Short name | T1345 |
| Test name | |
| Test status | |
| Simulation time | 56930938 ps |
| CPU time | 6.6 seconds |
| Started | Aug 24 03:53:33 AM UTC 24 |
| Finished | Aug 24 03:53:41 AM UTC 24 |
| Peak memory | 597692 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1878943318 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.xbar_error_and_unmapped_addr.1878943318 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/1.xbar_error_and_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/1.xbar_error_random.1443253371 |
| Short name | T664 |
| Test name | |
| Test status | |
| Simulation time | 1637400452 ps |
| CPU time | 42.11 seconds |
| Started | Aug 24 03:53:16 AM UTC 24 |
| Finished | Aug 24 03:53:59 AM UTC 24 |
| Peak memory | 597700 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1443253371 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.xbar_error_random.1443253371 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/1.xbar_error_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/1.xbar_random.54192238 |
| Short name | T553 |
| Test name | |
| Test status | |
| Simulation time | 1049947042 ps |
| CPU time | 28.39 seconds |
| Started | Aug 24 03:51:36 AM UTC 24 |
| Finished | Aug 24 03:52:06 AM UTC 24 |
| Peak memory | 597940 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=54192238 -assert nopostproc +UVM_TESTNAME= xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08 _22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.xbar_random.54192238 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/1.xbar_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/1.xbar_random_large_delays.2207508112 |
| Short name | T464 |
| Test name | |
| Test status | |
| Simulation time | 64358089603 ps |
| CPU time | 513.13 seconds |
| Started | Aug 24 03:52:19 AM UTC 24 |
| Finished | Aug 24 04:00:58 AM UTC 24 |
| Peak memory | 597824 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max _device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2207508112 -assert nopostproc +U VM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.xbar_random_large_delays.2207508112 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/1.xbar_random_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/1.xbar_random_zero_delays.976995147 |
| Short name | T532 |
| Test name | |
| Test status | |
| Simulation time | 361440922 ps |
| CPU time | 22.77 seconds |
| Started | Aug 24 03:51:41 AM UTC 24 |
| Finished | Aug 24 03:52:05 AM UTC 24 |
| Peak memory | 597696 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=976995147 -assert nopostpro c +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.xbar_random_zero_delays.976995147 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/1.xbar_random_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/1.xbar_same_source.1508054408 |
| Short name | T593 |
| Test name | |
| Test status | |
| Simulation time | 297967497 ps |
| CPU time | 8.85 seconds |
| Started | Aug 24 03:52:52 AM UTC 24 |
| Finished | Aug 24 03:53:01 AM UTC 24 |
| Peak memory | 597684 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1508054408 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.xbar_same_source.1508054408 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/1.xbar_same_source/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/1.xbar_smoke.2866597213 |
| Short name | T546 |
| Test name | |
| Test status | |
| Simulation time | 183056022 ps |
| CPU time | 6.37 seconds |
| Started | Aug 24 03:50:54 AM UTC 24 |
| Finished | Aug 24 03:51:01 AM UTC 24 |
| Peak memory | 595880 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2866597213 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 8_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.xbar_smoke.2866597213 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/1.xbar_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/1.xbar_smoke_large_delays.2110034444 |
| Short name | T590 |
| Test name | |
| Test status | |
| Simulation time | 7610270308 ps |
| CPU time | 61.5 seconds |
| Started | Aug 24 03:51:25 AM UTC 24 |
| Finished | Aug 24 03:52:28 AM UTC 24 |
| Peak memory | 595832 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max _device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2110034444 -assert nopostproc +U VM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.xbar_smoke_large_delays.2110034444 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/1.xbar_smoke_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/1.xbar_smoke_slow_rsp.3303084635 |
| Short name | T678 |
| Test name | |
| Test status | |
| Simulation time | 5363531165 ps |
| CPU time | 63.44 seconds |
| Started | Aug 24 03:51:32 AM UTC 24 |
| Finished | Aug 24 03:52:37 AM UTC 24 |
| Peak memory | 596020 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3303084635 -assert nopostproc +UVM_T ESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.xbar_smoke_slow_rsp.3303084635 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/1.xbar_smoke_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/1.xbar_smoke_zero_delays.3018453415 |
| Short name | T552 |
| Test name | |
| Test status | |
| Simulation time | 44512754 ps |
| CPU time | 5.18 seconds |
| Started | Aug 24 03:51:16 AM UTC 24 |
| Finished | Aug 24 03:51:22 AM UTC 24 |
| Peak memory | 595856 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3018453415 -assert nopostpr oc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.xbar_smoke_zero_delays.3018453415 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/1.xbar_smoke_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/1.xbar_stress_all_with_error.1708427752 |
| Short name | T635 |
| Test name | |
| Test status | |
| Simulation time | 6473341659 ps |
| CPU time | 153.22 seconds |
| Started | Aug 24 03:54:00 AM UTC 24 |
| Finished | Aug 24 03:56:36 AM UTC 24 |
| Peak memory | 598096 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1708427752 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.xbar_stress_all_with_error.1708427752 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/1.xbar_stress_all_with_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/1.xbar_stress_all_with_rand_reset.2871218884 |
| Short name | T836 |
| Test name | |
| Test status | |
| Simulation time | 87388115 ps |
| CPU time | 14.41 seconds |
| Started | Aug 24 03:53:55 AM UTC 24 |
| Finished | Aug 24 03:54:10 AM UTC 24 |
| Peak memory | 597960 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2871218884 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.xbar_stress_all_with_rand_reset.2871218884 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/1.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/10.chip_csr_mem_rw_with_rand_reset.2959812945 |
| Short name | T1432 |
| Test name | |
| Test status | |
| Simulation time | 9562901365 ps |
| CPU time | 567.8 seconds |
| Started | Aug 24 04:31:32 AM UTC 24 |
| Finished | Aug 24 04:41:06 AM UTC 24 |
| Peak memory | 672596 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000 000000 +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/too ls/sim.tcl +ntb_random_seed=2959812945 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/nul l -cm_name 10.chip_csr_mem_rw_with_rand_reset.2959812945 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/10.chip_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/10.chip_csr_rw.404307805 |
| Short name | T1419 |
| Test name | |
| Test status | |
| Simulation time | 5965474264 ps |
| CPU time | 393.75 seconds |
| Started | Aug 24 04:31:20 AM UTC 24 |
| Finished | Aug 24 04:37:59 AM UTC 24 |
| Peak memory | 617184 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +stub_cpu=1 +cdc_instrumentation_ena bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=404307805 -assert nopostp roc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_ regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.chip_csr_rw.404307805 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/10.chip_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/10.chip_same_csr_outstanding.1740302673 |
| Short name | T1580 |
| Test name | |
| Test status | |
| Simulation time | 31207165142 ps |
| CPU time | 2952.38 seconds |
| Started | Aug 24 04:28:05 AM UTC 24 |
| Finished | Aug 24 05:17:48 AM UTC 24 |
| Peak memory | 614108 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +test_timeout_ns=120_000_000 +run_same_csr_outstanding +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim .tcl +ntb_random_seed=1740302673 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_ name 10.chip_same_csr_outstanding.1740302673 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/10.chip_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/10.chip_tl_errors.1380413148 |
| Short name | T568 |
| Test name | |
| Test status | |
| Simulation time | 3566266185 ps |
| CPU time | 165.47 seconds |
| Started | Aug 24 04:28:13 AM UTC 24 |
| Finished | Aug 24 04:31:02 AM UTC 24 |
| Peak memory | 623320 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enable d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1380413148 -assert nopostpro c +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.chip_tl_errors.1380413148 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/10.chip_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/10.xbar_access_same_device.794990715 |
| Short name | T809 |
| Test name | |
| Test status | |
| Simulation time | 1402057575 ps |
| CPU time | 48.93 seconds |
| Started | Aug 24 04:30:27 AM UTC 24 |
| Finished | Aug 24 04:31:17 AM UTC 24 |
| Peak memory | 597704 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=794990715 -assert nopostproc +UVM_TESTNAME =xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.xbar_access_same_device.794990715 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/10.xbar_access_same_device/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/10.xbar_access_same_device_slow_rsp.3338250826 |
| Short name | T814 |
| Test name | |
| Test status | |
| Simulation time | 59172607661 ps |
| CPU time | 734.13 seconds |
| Started | Aug 24 04:30:33 AM UTC 24 |
| Finished | Aug 24 04:42:55 AM UTC 24 |
| Peak memory | 598072 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3338250826 -assert nopostproc +UVM_T ESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.xbar_access_same_device_slow_rsp.3338250826 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/10.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/10.xbar_error_and_unmapped_addr.773301115 |
| Short name | T1404 |
| Test name | |
| Test status | |
| Simulation time | 20401540 ps |
| CPU time | 4.17 seconds |
| Started | Aug 24 04:30:52 AM UTC 24 |
| Finished | Aug 24 04:30:58 AM UTC 24 |
| Peak memory | 595636 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=773301115 -assert nopostproc +UVM_TESTNAME =xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.xbar_error_and_unmapped_addr.773301115 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/10.xbar_error_and_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/10.xbar_error_random.1749689207 |
| Short name | T1407 |
| Test name | |
| Test status | |
| Simulation time | 1818378308 ps |
| CPU time | 47.76 seconds |
| Started | Aug 24 04:30:45 AM UTC 24 |
| Finished | Aug 24 04:31:35 AM UTC 24 |
| Peak memory | 597688 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1749689207 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.xbar_error_random.1749689207 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/10.xbar_error_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/10.xbar_random.2406130352 |
| Short name | T614 |
| Test name | |
| Test status | |
| Simulation time | 627150407 ps |
| CPU time | 40.37 seconds |
| Started | Aug 24 04:29:20 AM UTC 24 |
| Finished | Aug 24 04:30:01 AM UTC 24 |
| Peak memory | 597692 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2406130352 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.xbar_random.2406130352 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/10.xbar_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/10.xbar_random_large_delays.301433284 |
| Short name | T515 |
| Test name | |
| Test status | |
| Simulation time | 61009910940 ps |
| CPU time | 494.87 seconds |
| Started | Aug 24 04:30:11 AM UTC 24 |
| Finished | Aug 24 04:38:31 AM UTC 24 |
| Peak memory | 598024 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max _device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=301433284 -assert nopostproc +UV M_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.xbar_random_large_delays.301433284 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/10.xbar_random_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/10.xbar_random_slow_rsp.722141719 |
| Short name | T472 |
| Test name | |
| Test status | |
| Simulation time | 55528596740 ps |
| CPU time | 651.54 seconds |
| Started | Aug 24 04:30:16 AM UTC 24 |
| Finished | Aug 24 04:41:15 AM UTC 24 |
| Peak memory | 598120 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=722141719 -assert nopostproc +UVM_TE STNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.xbar_random_slow_rsp.722141719 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/10.xbar_random_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/10.xbar_random_zero_delays.1183180421 |
| Short name | T623 |
| Test name | |
| Test status | |
| Simulation time | 306565691 ps |
| CPU time | 20.25 seconds |
| Started | Aug 24 04:29:35 AM UTC 24 |
| Finished | Aug 24 04:29:57 AM UTC 24 |
| Peak memory | 597760 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1183180421 -assert nopostpr oc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.xbar_random_zero_delays.1183180421 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/10.xbar_random_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/10.xbar_same_source.3770407924 |
| Short name | T1405 |
| Test name | |
| Test status | |
| Simulation time | 1229965537 ps |
| CPU time | 26.09 seconds |
| Started | Aug 24 04:30:36 AM UTC 24 |
| Finished | Aug 24 04:31:03 AM UTC 24 |
| Peak memory | 597676 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3770407924 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.xbar_same_source.3770407924 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/10.xbar_same_source/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/10.xbar_smoke.1568728195 |
| Short name | T1399 |
| Test name | |
| Test status | |
| Simulation time | 45515886 ps |
| CPU time | 4.97 seconds |
| Started | Aug 24 04:28:40 AM UTC 24 |
| Finished | Aug 24 04:28:46 AM UTC 24 |
| Peak memory | 595628 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1568728195 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 8_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.xbar_smoke.1568728195 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/10.xbar_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/10.xbar_smoke_large_delays.1917710666 |
| Short name | T1403 |
| Test name | |
| Test status | |
| Simulation time | 11154334912 ps |
| CPU time | 93.71 seconds |
| Started | Aug 24 04:29:00 AM UTC 24 |
| Finished | Aug 24 04:30:35 AM UTC 24 |
| Peak memory | 595996 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max _device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1917710666 -assert nopostproc +U VM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.xbar_smoke_large_delays.1917710666 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/10.xbar_smoke_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/10.xbar_smoke_slow_rsp.538480285 |
| Short name | T1402 |
| Test name | |
| Test status | |
| Simulation time | 5511783610 ps |
| CPU time | 67.03 seconds |
| Started | Aug 24 04:29:14 AM UTC 24 |
| Finished | Aug 24 04:30:22 AM UTC 24 |
| Peak memory | 595836 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=538480285 -assert nopostproc +UVM_TE STNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.xbar_smoke_slow_rsp.538480285 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/10.xbar_smoke_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/10.xbar_smoke_zero_delays.3173488013 |
| Short name | T625 |
| Test name | |
| Test status | |
| Simulation time | 44585609 ps |
| CPU time | 4.97 seconds |
| Started | Aug 24 04:28:54 AM UTC 24 |
| Finished | Aug 24 04:29:00 AM UTC 24 |
| Peak memory | 595696 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3173488013 -assert nopostpr oc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.xbar_smoke_zero_delays.3173488013 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/10.xbar_smoke_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/10.xbar_stress_all.2982594612 |
| Short name | T478 |
| Test name | |
| Test status | |
| Simulation time | 1373074623 ps |
| CPU time | 43.42 seconds |
| Started | Aug 24 04:31:12 AM UTC 24 |
| Finished | Aug 24 04:31:56 AM UTC 24 |
| Peak memory | 597696 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2982594612 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.xbar_stress_all.2982594612 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/10.xbar_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/10.xbar_stress_all_with_error.3386627302 |
| Short name | T1408 |
| Test name | |
| Test status | |
| Simulation time | 205573287 ps |
| CPU time | 18.24 seconds |
| Started | Aug 24 04:31:18 AM UTC 24 |
| Finished | Aug 24 04:31:37 AM UTC 24 |
| Peak memory | 597696 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3386627302 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.xbar_stress_all_with_error.3386627302 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/10.xbar_stress_all_with_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/10.xbar_stress_all_with_rand_reset.3295215824 |
| Short name | T526 |
| Test name | |
| Test status | |
| Simulation time | 2949788850 ps |
| CPU time | 299.84 seconds |
| Started | Aug 24 04:31:16 AM UTC 24 |
| Finished | Aug 24 04:36:19 AM UTC 24 |
| Peak memory | 597760 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3295215824 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.xbar_stress_all_with_rand_reset.3295215824 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/10.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/10.xbar_stress_all_with_reset_error.3457829975 |
| Short name | T854 |
| Test name | |
| Test status | |
| Simulation time | 2677726979 ps |
| CPU time | 125.16 seconds |
| Started | Aug 24 04:31:18 AM UTC 24 |
| Finished | Aug 24 04:33:25 AM UTC 24 |
| Peak memory | 598036 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3457829975 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.xbar_stress_all_with_reset_error.3457829975 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/10.xbar_stress_all_with_reset_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/10.xbar_unmapped_addr.4125974583 |
| Short name | T1406 |
| Test name | |
| Test status | |
| Simulation time | 156537753 ps |
| CPU time | 15.07 seconds |
| Started | Aug 24 04:30:49 AM UTC 24 |
| Finished | Aug 24 04:31:06 AM UTC 24 |
| Peak memory | 597688 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4125974583 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.xbar_unmapped_addr.4125974583 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/10.xbar_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/11.chip_csr_mem_rw_with_rand_reset.424409459 |
| Short name | T1435 |
| Test name | |
| Test status | |
| Simulation time | 7121173100 ps |
| CPU time | 304.37 seconds |
| Started | Aug 24 04:36:32 AM UTC 24 |
| Finished | Aug 24 04:41:41 AM UTC 24 |
| Peak memory | 658268 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000 000000 +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/too ls/sim.tcl +ntb_random_seed=424409459 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.chip_csr_mem_rw_with_rand_reset.424409459 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/11.chip_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/11.chip_csr_rw.3239844137 |
| Short name | T1442 |
| Test name | |
| Test status | |
| Simulation time | 5971827299 ps |
| CPU time | 404.76 seconds |
| Started | Aug 24 04:36:17 AM UTC 24 |
| Finished | Aug 24 04:43:07 AM UTC 24 |
| Peak memory | 619516 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +stub_cpu=1 +cdc_instrumentation_ena bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3239844137 -assert nopost proc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os _regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.chip_csr_rw.3239844137 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/11.chip_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/11.chip_same_csr_outstanding.997390011 |
| Short name | T1519 |
| Test name | |
| Test status | |
| Simulation time | 28219775808 ps |
| CPU time | 1933.05 seconds |
| Started | Aug 24 04:31:49 AM UTC 24 |
| Finished | Aug 24 05:04:22 AM UTC 24 |
| Peak memory | 614340 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +test_timeout_ns=120_000_000 +run_same_csr_outstanding +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim .tcl +ntb_random_seed=997390011 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n ame 11.chip_same_csr_outstanding.997390011 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/11.chip_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/11.chip_tl_errors.1193207417 |
| Short name | T574 |
| Test name | |
| Test status | |
| Simulation time | 2499950454 ps |
| CPU time | 95.18 seconds |
| Started | Aug 24 04:31:50 AM UTC 24 |
| Finished | Aug 24 04:33:27 AM UTC 24 |
| Peak memory | 623412 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enable d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1193207417 -assert nopostpro c +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.chip_tl_errors.1193207417 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/11.chip_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/11.xbar_access_same_device.4122257716 |
| Short name | T785 |
| Test name | |
| Test status | |
| Simulation time | 2174002838 ps |
| CPU time | 60.66 seconds |
| Started | Aug 24 04:33:42 AM UTC 24 |
| Finished | Aug 24 04:34:44 AM UTC 24 |
| Peak memory | 597768 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4122257716 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.xbar_access_same_device.4122257716 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/11.xbar_access_same_device/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/11.xbar_error_and_unmapped_addr.2720632912 |
| Short name | T1416 |
| Test name | |
| Test status | |
| Simulation time | 199162404 ps |
| CPU time | 17.76 seconds |
| Started | Aug 24 04:35:11 AM UTC 24 |
| Finished | Aug 24 04:35:30 AM UTC 24 |
| Peak memory | 597840 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2720632912 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.xbar_error_and_unmapped_addr.2720632912 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/11.xbar_error_and_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/11.xbar_error_random.1709272691 |
| Short name | T1414 |
| Test name | |
| Test status | |
| Simulation time | 71510005 ps |
| CPU time | 6.81 seconds |
| Started | Aug 24 04:34:49 AM UTC 24 |
| Finished | Aug 24 04:34:57 AM UTC 24 |
| Peak memory | 597688 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1709272691 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.xbar_error_random.1709272691 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/11.xbar_error_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/11.xbar_random.1632846964 |
| Short name | T487 |
| Test name | |
| Test status | |
| Simulation time | 548414935 ps |
| CPU time | 38.62 seconds |
| Started | Aug 24 04:32:46 AM UTC 24 |
| Finished | Aug 24 04:33:26 AM UTC 24 |
| Peak memory | 597692 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1632846964 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.xbar_random.1632846964 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/11.xbar_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/11.xbar_random_large_delays.1060008677 |
| Short name | T1426 |
| Test name | |
| Test status | |
| Simulation time | 45487327196 ps |
| CPU time | 376.98 seconds |
| Started | Aug 24 04:33:39 AM UTC 24 |
| Finished | Aug 24 04:40:01 AM UTC 24 |
| Peak memory | 597960 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max _device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1060008677 -assert nopostproc +U VM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.xbar_random_large_delays.1060008677 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/11.xbar_random_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/11.xbar_random_slow_rsp.2276377960 |
| Short name | T1417 |
| Test name | |
| Test status | |
| Simulation time | 10644713943 ps |
| CPU time | 126.59 seconds |
| Started | Aug 24 04:33:40 AM UTC 24 |
| Finished | Aug 24 04:35:49 AM UTC 24 |
| Peak memory | 598068 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2276377960 -assert nopostproc +UVM_T ESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.xbar_random_slow_rsp.2276377960 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/11.xbar_random_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/11.xbar_random_zero_delays.719783743 |
| Short name | T1413 |
| Test name | |
| Test status | |
| Simulation time | 242381635 ps |
| CPU time | 18.22 seconds |
| Started | Aug 24 04:33:27 AM UTC 24 |
| Finished | Aug 24 04:33:47 AM UTC 24 |
| Peak memory | 597760 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=719783743 -assert nopostpro c +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.xbar_random_zero_delays.719783743 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/11.xbar_random_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/11.xbar_same_source.3097456032 |
| Short name | T540 |
| Test name | |
| Test status | |
| Simulation time | 582674471 ps |
| CPU time | 32.52 seconds |
| Started | Aug 24 04:34:01 AM UTC 24 |
| Finished | Aug 24 04:34:34 AM UTC 24 |
| Peak memory | 597684 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3097456032 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.xbar_same_source.3097456032 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/11.xbar_same_source/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/11.xbar_smoke.3168223104 |
| Short name | T1409 |
| Test name | |
| Test status | |
| Simulation time | 235794005 ps |
| CPU time | 8.05 seconds |
| Started | Aug 24 04:31:51 AM UTC 24 |
| Finished | Aug 24 04:32:01 AM UTC 24 |
| Peak memory | 595628 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3168223104 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 8_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.xbar_smoke.3168223104 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/11.xbar_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/11.xbar_smoke_large_delays.260754209 |
| Short name | T529 |
| Test name | |
| Test status | |
| Simulation time | 10085189521 ps |
| CPU time | 86.83 seconds |
| Started | Aug 24 04:32:15 AM UTC 24 |
| Finished | Aug 24 04:33:44 AM UTC 24 |
| Peak memory | 595828 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max _device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=260754209 -assert nopostproc +UV M_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.xbar_smoke_large_delays.260754209 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/11.xbar_smoke_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/11.xbar_smoke_slow_rsp.4070204691 |
| Short name | T1412 |
| Test name | |
| Test status | |
| Simulation time | 3288697272 ps |
| CPU time | 40.42 seconds |
| Started | Aug 24 04:32:31 AM UTC 24 |
| Finished | Aug 24 04:33:13 AM UTC 24 |
| Peak memory | 595704 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4070204691 -assert nopostproc +UVM_T ESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.xbar_smoke_slow_rsp.4070204691 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/11.xbar_smoke_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/11.xbar_smoke_zero_delays.2647057013 |
| Short name | T1410 |
| Test name | |
| Test status | |
| Simulation time | 50637364 ps |
| CPU time | 5.41 seconds |
| Started | Aug 24 04:32:11 AM UTC 24 |
| Finished | Aug 24 04:32:17 AM UTC 24 |
| Peak memory | 595700 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2647057013 -assert nopostpr oc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.xbar_smoke_zero_delays.2647057013 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/11.xbar_smoke_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/11.xbar_stress_all.2868338961 |
| Short name | T596 |
| Test name | |
| Test status | |
| Simulation time | 7058792502 ps |
| CPU time | 190.17 seconds |
| Started | Aug 24 04:35:26 AM UTC 24 |
| Finished | Aug 24 04:38:39 AM UTC 24 |
| Peak memory | 597824 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2868338961 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.xbar_stress_all.2868338961 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/11.xbar_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/11.xbar_stress_all_with_error.620557906 |
| Short name | T1424 |
| Test name | |
| Test status | |
| Simulation time | 8894812704 ps |
| CPU time | 201.18 seconds |
| Started | Aug 24 04:35:53 AM UTC 24 |
| Finished | Aug 24 04:39:17 AM UTC 24 |
| Peak memory | 597824 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=620557906 -assert nopostproc +UVM_TESTNAME =xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.xbar_stress_all_with_error.620557906 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/11.xbar_stress_all_with_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/11.xbar_stress_all_with_rand_reset.671124946 |
| Short name | T498 |
| Test name | |
| Test status | |
| Simulation time | 3125156452 ps |
| CPU time | 312.39 seconds |
| Started | Aug 24 04:35:44 AM UTC 24 |
| Finished | Aug 24 04:41:00 AM UTC 24 |
| Peak memory | 597756 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=671124946 -assert nopostproc +UVM_TESTNAME =xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.xbar_stress_all_with_rand_reset.671124946 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/11.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/11.xbar_stress_all_with_reset_error.867782161 |
| Short name | T832 |
| Test name | |
| Test status | |
| Simulation time | 3455174579 ps |
| CPU time | 203.82 seconds |
| Started | Aug 24 04:36:03 AM UTC 24 |
| Finished | Aug 24 04:39:30 AM UTC 24 |
| Peak memory | 597756 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=867782161 -assert nopostproc +UVM_TESTNAME =xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.xbar_stress_all_with_reset_error.867782161 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/11.xbar_stress_all_with_reset_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/11.xbar_unmapped_addr.1885232767 |
| Short name | T1415 |
| Test name | |
| Test status | |
| Simulation time | 299943299 ps |
| CPU time | 12.47 seconds |
| Started | Aug 24 04:34:58 AM UTC 24 |
| Finished | Aug 24 04:35:11 AM UTC 24 |
| Peak memory | 597976 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1885232767 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.xbar_unmapped_addr.1885232767 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/11.xbar_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/12.chip_csr_mem_rw_with_rand_reset.1928510841 |
| Short name | T1456 |
| Test name | |
| Test status | |
| Simulation time | 5990021902 ps |
| CPU time | 399.88 seconds |
| Started | Aug 24 04:40:45 AM UTC 24 |
| Finished | Aug 24 04:47:30 AM UTC 24 |
| Peak memory | 664652 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000 000000 +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/too ls/sim.tcl +ntb_random_seed=1928510841 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/nul l -cm_name 12.chip_csr_mem_rw_with_rand_reset.1928510841 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/12.chip_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/12.chip_csr_rw.330686206 |
| Short name | T1447 |
| Test name | |
| Test status | |
| Simulation time | 4092897916 ps |
| CPU time | 246.99 seconds |
| Started | Aug 24 04:40:32 AM UTC 24 |
| Finished | Aug 24 04:44:43 AM UTC 24 |
| Peak memory | 617244 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +stub_cpu=1 +cdc_instrumentation_ena bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=330686206 -assert nopostp roc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_ regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.chip_csr_rw.330686206 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/12.chip_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/12.chip_same_csr_outstanding.2159204894 |
| Short name | T1620 |
| Test name | |
| Test status | |
| Simulation time | 29584249088 ps |
| CPU time | 2898.18 seconds |
| Started | Aug 24 04:36:34 AM UTC 24 |
| Finished | Aug 24 05:25:22 AM UTC 24 |
| Peak memory | 614112 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +test_timeout_ns=120_000_000 +run_same_csr_outstanding +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim .tcl +ntb_random_seed=2159204894 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_ name 12.chip_same_csr_outstanding.2159204894 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/12.chip_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/12.xbar_access_same_device.951194355 |
| Short name | T789 |
| Test name | |
| Test status | |
| Simulation time | 1158356115 ps |
| CPU time | 29.76 seconds |
| Started | Aug 24 04:39:43 AM UTC 24 |
| Finished | Aug 24 04:40:14 AM UTC 24 |
| Peak memory | 597952 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=951194355 -assert nopostproc +UVM_TESTNAME =xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.xbar_access_same_device.951194355 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/12.xbar_access_same_device/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/12.xbar_access_same_device_slow_rsp.2517632047 |
| Short name | T519 |
| Test name | |
| Test status | |
| Simulation time | 101543511020 ps |
| CPU time | 1267.19 seconds |
| Started | Aug 24 04:39:45 AM UTC 24 |
| Finished | Aug 24 05:01:04 AM UTC 24 |
| Peak memory | 597832 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2517632047 -assert nopostproc +UVM_T ESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.xbar_access_same_device_slow_rsp.2517632047 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/12.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/12.xbar_error_and_unmapped_addr.3461891868 |
| Short name | T1431 |
| Test name | |
| Test status | |
| Simulation time | 1080987577 ps |
| CPU time | 33.05 seconds |
| Started | Aug 24 04:40:15 AM UTC 24 |
| Finished | Aug 24 04:40:49 AM UTC 24 |
| Peak memory | 597700 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3461891868 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.xbar_error_and_unmapped_addr.3461891868 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/12.xbar_error_and_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/12.xbar_error_random.1770267029 |
| Short name | T1430 |
| Test name | |
| Test status | |
| Simulation time | 1310651667 ps |
| CPU time | 32.75 seconds |
| Started | Aug 24 04:39:57 AM UTC 24 |
| Finished | Aug 24 04:40:31 AM UTC 24 |
| Peak memory | 597820 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1770267029 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.xbar_error_random.1770267029 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/12.xbar_error_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/12.xbar_random.1588190419 |
| Short name | T1423 |
| Test name | |
| Test status | |
| Simulation time | 197190311 ps |
| CPU time | 14.66 seconds |
| Started | Aug 24 04:38:57 AM UTC 24 |
| Finished | Aug 24 04:39:13 AM UTC 24 |
| Peak memory | 597828 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1588190419 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.xbar_random.1588190419 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/12.xbar_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/12.xbar_random_large_delays.3804476429 |
| Short name | T509 |
| Test name | |
| Test status | |
| Simulation time | 69996650056 ps |
| CPU time | 553.39 seconds |
| Started | Aug 24 04:39:27 AM UTC 24 |
| Finished | Aug 24 04:48:46 AM UTC 24 |
| Peak memory | 597824 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max _device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3804476429 -assert nopostproc +U VM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.xbar_random_large_delays.3804476429 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/12.xbar_random_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/12.xbar_random_slow_rsp.138391158 |
| Short name | T1428 |
| Test name | |
| Test status | |
| Simulation time | 3566957936 ps |
| CPU time | 43.85 seconds |
| Started | Aug 24 04:39:31 AM UTC 24 |
| Finished | Aug 24 04:40:17 AM UTC 24 |
| Peak memory | 595712 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=138391158 -assert nopostproc +UVM_TE STNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.xbar_random_slow_rsp.138391158 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/12.xbar_random_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/12.xbar_random_zero_delays.2900556246 |
| Short name | T1427 |
| Test name | |
| Test status | |
| Simulation time | 591097736 ps |
| CPU time | 38.5 seconds |
| Started | Aug 24 04:39:21 AM UTC 24 |
| Finished | Aug 24 04:40:01 AM UTC 24 |
| Peak memory | 597844 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2900556246 -assert nopostpr oc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.xbar_random_zero_delays.2900556246 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/12.xbar_random_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/12.xbar_same_source.3217715455 |
| Short name | T588 |
| Test name | |
| Test status | |
| Simulation time | 347042528 ps |
| CPU time | 19.52 seconds |
| Started | Aug 24 04:39:45 AM UTC 24 |
| Finished | Aug 24 04:40:06 AM UTC 24 |
| Peak memory | 597748 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3217715455 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.xbar_same_source.3217715455 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/12.xbar_same_source/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/12.xbar_smoke.448010195 |
| Short name | T1420 |
| Test name | |
| Test status | |
| Simulation time | 229460012 ps |
| CPU time | 7.73 seconds |
| Started | Aug 24 04:38:13 AM UTC 24 |
| Finished | Aug 24 04:38:22 AM UTC 24 |
| Peak memory | 595632 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=448010195 -assert nopostproc +UVM_TESTNAME =xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08 _22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.xbar_smoke.448010195 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/12.xbar_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/12.xbar_smoke_large_delays.2423068147 |
| Short name | T476 |
| Test name | |
| Test status | |
| Simulation time | 5332370179 ps |
| CPU time | 45.35 seconds |
| Started | Aug 24 04:38:45 AM UTC 24 |
| Finished | Aug 24 04:39:32 AM UTC 24 |
| Peak memory | 595764 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max _device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2423068147 -assert nopostproc +U VM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.xbar_smoke_large_delays.2423068147 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/12.xbar_smoke_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/12.xbar_smoke_slow_rsp.621499104 |
| Short name | T1425 |
| Test name | |
| Test status | |
| Simulation time | 3839548456 ps |
| CPU time | 47.52 seconds |
| Started | Aug 24 04:38:53 AM UTC 24 |
| Finished | Aug 24 04:39:42 AM UTC 24 |
| Peak memory | 595704 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=621499104 -assert nopostproc +UVM_TE STNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.xbar_smoke_slow_rsp.621499104 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/12.xbar_smoke_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/12.xbar_smoke_zero_delays.1031942112 |
| Short name | T1421 |
| Test name | |
| Test status | |
| Simulation time | 56000587 ps |
| CPU time | 5.7 seconds |
| Started | Aug 24 04:38:36 AM UTC 24 |
| Finished | Aug 24 04:38:43 AM UTC 24 |
| Peak memory | 595632 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1031942112 -assert nopostpr oc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.xbar_smoke_zero_delays.1031942112 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/12.xbar_smoke_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/12.xbar_stress_all.3712205925 |
| Short name | T490 |
| Test name | |
| Test status | |
| Simulation time | 7738677095 ps |
| CPU time | 224.8 seconds |
| Started | Aug 24 04:40:16 AM UTC 24 |
| Finished | Aug 24 04:44:04 AM UTC 24 |
| Peak memory | 597824 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3712205925 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.xbar_stress_all.3712205925 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/12.xbar_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/12.xbar_stress_all_with_error.1356378612 |
| Short name | T796 |
| Test name | |
| Test status | |
| Simulation time | 4887763313 ps |
| CPU time | 142.03 seconds |
| Started | Aug 24 04:40:29 AM UTC 24 |
| Finished | Aug 24 04:42:54 AM UTC 24 |
| Peak memory | 597824 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1356378612 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.xbar_stress_all_with_error.1356378612 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/12.xbar_stress_all_with_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/12.xbar_stress_all_with_reset_error.313561527 |
| Short name | T862 |
| Test name | |
| Test status | |
| Simulation time | 5656949094 ps |
| CPU time | 192.72 seconds |
| Started | Aug 24 04:40:31 AM UTC 24 |
| Finished | Aug 24 04:43:47 AM UTC 24 |
| Peak memory | 597880 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=313561527 -assert nopostproc +UVM_TESTNAME =xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.xbar_stress_all_with_reset_error.313561527 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/12.xbar_stress_all_with_reset_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/12.xbar_unmapped_addr.839678609 |
| Short name | T1429 |
| Test name | |
| Test status | |
| Simulation time | 418800407 ps |
| CPU time | 16.31 seconds |
| Started | Aug 24 04:40:01 AM UTC 24 |
| Finished | Aug 24 04:40:18 AM UTC 24 |
| Peak memory | 597692 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=839678609 -assert nopostproc +UVM_TESTNAME =xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.xbar_unmapped_addr.839678609 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/12.xbar_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/13.chip_csr_mem_rw_with_rand_reset.1094186474 |
| Short name | T1463 |
| Test name | |
| Test status | |
| Simulation time | 5411222696 ps |
| CPU time | 292.65 seconds |
| Started | Aug 24 04:44:01 AM UTC 24 |
| Finished | Aug 24 04:48:58 AM UTC 24 |
| Peak memory | 664468 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000 000000 +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/too ls/sim.tcl +ntb_random_seed=1094186474 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/nul l -cm_name 13.chip_csr_mem_rw_with_rand_reset.1094186474 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/13.chip_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/13.chip_csr_rw.1226126984 |
| Short name | T1459 |
| Test name | |
| Test status | |
| Simulation time | 4377292076 ps |
| CPU time | 213.55 seconds |
| Started | Aug 24 04:44:00 AM UTC 24 |
| Finished | Aug 24 04:47:37 AM UTC 24 |
| Peak memory | 617404 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +stub_cpu=1 +cdc_instrumentation_ena bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1226126984 -assert nopost proc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os _regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.chip_csr_rw.1226126984 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/13.chip_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/13.chip_same_csr_outstanding.910735474 |
| Short name | T1507 |
| Test name | |
| Test status | |
| Simulation time | 17362482334 ps |
| CPU time | 1202.2 seconds |
| Started | Aug 24 04:41:04 AM UTC 24 |
| Finished | Aug 24 05:01:19 AM UTC 24 |
| Peak memory | 613208 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +test_timeout_ns=120_000_000 +run_same_csr_outstanding +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim .tcl +ntb_random_seed=910735474 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n ame 13.chip_same_csr_outstanding.910735474 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/13.chip_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/13.chip_tl_errors.4014366007 |
| Short name | T575 |
| Test name | |
| Test status | |
| Simulation time | 3334329389 ps |
| CPU time | 188.99 seconds |
| Started | Aug 24 04:41:14 AM UTC 24 |
| Finished | Aug 24 04:44:26 AM UTC 24 |
| Peak memory | 623392 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enable d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4014366007 -assert nopostpro c +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.chip_tl_errors.4014366007 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/13.chip_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/13.xbar_access_same_device.763738600 |
| Short name | T815 |
| Test name | |
| Test status | |
| Simulation time | 2137576648 ps |
| CPU time | 67.89 seconds |
| Started | Aug 24 04:42:34 AM UTC 24 |
| Finished | Aug 24 04:43:44 AM UTC 24 |
| Peak memory | 597704 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=763738600 -assert nopostproc +UVM_TESTNAME =xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.xbar_access_same_device.763738600 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/13.xbar_access_same_device/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/13.xbar_access_same_device_slow_rsp.698534889 |
| Short name | T818 |
| Test name | |
| Test status | |
| Simulation time | 30820512043 ps |
| CPU time | 354.38 seconds |
| Started | Aug 24 04:42:50 AM UTC 24 |
| Finished | Aug 24 04:48:49 AM UTC 24 |
| Peak memory | 597828 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=698534889 -assert nopostproc +UVM_TE STNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os _regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.xbar_access_same_device_slow_rsp.698534889 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/13.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/13.xbar_error_and_unmapped_addr.1256812531 |
| Short name | T1445 |
| Test name | |
| Test status | |
| Simulation time | 639005207 ps |
| CPU time | 21.14 seconds |
| Started | Aug 24 04:43:21 AM UTC 24 |
| Finished | Aug 24 04:43:43 AM UTC 24 |
| Peak memory | 597828 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1256812531 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.xbar_error_and_unmapped_addr.1256812531 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/13.xbar_error_and_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/13.xbar_error_random.1192524398 |
| Short name | T1444 |
| Test name | |
| Test status | |
| Simulation time | 395017602 ps |
| CPU time | 25.38 seconds |
| Started | Aug 24 04:43:08 AM UTC 24 |
| Finished | Aug 24 04:43:35 AM UTC 24 |
| Peak memory | 597948 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1192524398 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.xbar_error_random.1192524398 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/13.xbar_error_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/13.xbar_random.3057802229 |
| Short name | T1437 |
| Test name | |
| Test status | |
| Simulation time | 546908345 ps |
| CPU time | 16.77 seconds |
| Started | Aug 24 04:41:55 AM UTC 24 |
| Finished | Aug 24 04:42:13 AM UTC 24 |
| Peak memory | 597696 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3057802229 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.xbar_random.3057802229 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/13.xbar_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/13.xbar_random_large_delays.1852812594 |
| Short name | T1450 |
| Test name | |
| Test status | |
| Simulation time | 22115808972 ps |
| CPU time | 183.64 seconds |
| Started | Aug 24 04:42:28 AM UTC 24 |
| Finished | Aug 24 04:45:34 AM UTC 24 |
| Peak memory | 597960 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max _device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1852812594 -assert nopostproc +U VM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.xbar_random_large_delays.1852812594 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/13.xbar_random_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/13.xbar_random_slow_rsp.4140387590 |
| Short name | T492 |
| Test name | |
| Test status | |
| Simulation time | 60340620222 ps |
| CPU time | 698.34 seconds |
| Started | Aug 24 04:42:28 AM UTC 24 |
| Finished | Aug 24 04:54:14 AM UTC 24 |
| Peak memory | 598140 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4140387590 -assert nopostproc +UVM_T ESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.xbar_random_slow_rsp.4140387590 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/13.xbar_random_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/13.xbar_random_zero_delays.774469887 |
| Short name | T1438 |
| Test name | |
| Test status | |
| Simulation time | 147673134 ps |
| CPU time | 12.65 seconds |
| Started | Aug 24 04:42:00 AM UTC 24 |
| Finished | Aug 24 04:42:13 AM UTC 24 |
| Peak memory | 597696 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=774469887 -assert nopostpro c +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.xbar_random_zero_delays.774469887 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/13.xbar_random_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/13.xbar_same_source.520863255 |
| Short name | T1443 |
| Test name | |
| Test status | |
| Simulation time | 471528233 ps |
| CPU time | 12.71 seconds |
| Started | Aug 24 04:43:04 AM UTC 24 |
| Finished | Aug 24 04:43:18 AM UTC 24 |
| Peak memory | 597896 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=520863255 -assert nopostproc +UVM_TESTNAME =xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.xbar_same_source.520863255 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/13.xbar_same_source/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/13.xbar_smoke.1962083743 |
| Short name | T1433 |
| Test name | |
| Test status | |
| Simulation time | 178745474 ps |
| CPU time | 6.44 seconds |
| Started | Aug 24 04:41:20 AM UTC 24 |
| Finished | Aug 24 04:41:28 AM UTC 24 |
| Peak memory | 595864 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1962083743 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 8_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.xbar_smoke.1962083743 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/13.xbar_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/13.xbar_smoke_large_delays.2696159191 |
| Short name | T1440 |
| Test name | |
| Test status | |
| Simulation time | 6485100489 ps |
| CPU time | 51.37 seconds |
| Started | Aug 24 04:41:42 AM UTC 24 |
| Finished | Aug 24 04:42:35 AM UTC 24 |
| Peak memory | 595764 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max _device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2696159191 -assert nopostproc +U VM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.xbar_smoke_large_delays.2696159191 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/13.xbar_smoke_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/13.xbar_smoke_slow_rsp.1212054629 |
| Short name | T1441 |
| Test name | |
| Test status | |
| Simulation time | 5020745227 ps |
| CPU time | 58.55 seconds |
| Started | Aug 24 04:41:49 AM UTC 24 |
| Finished | Aug 24 04:42:49 AM UTC 24 |
| Peak memory | 596016 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1212054629 -assert nopostproc +UVM_T ESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.xbar_smoke_slow_rsp.1212054629 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/13.xbar_smoke_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/13.xbar_smoke_zero_delays.1641150137 |
| Short name | T1434 |
| Test name | |
| Test status | |
| Simulation time | 39927140 ps |
| CPU time | 4.82 seconds |
| Started | Aug 24 04:41:29 AM UTC 24 |
| Finished | Aug 24 04:41:35 AM UTC 24 |
| Peak memory | 595696 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1641150137 -assert nopostpr oc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.xbar_smoke_zero_delays.1641150137 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/13.xbar_smoke_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/13.xbar_stress_all.1454115364 |
| Short name | T523 |
| Test name | |
| Test status | |
| Simulation time | 1272373034 ps |
| CPU time | 74.59 seconds |
| Started | Aug 24 04:43:32 AM UTC 24 |
| Finished | Aug 24 04:44:49 AM UTC 24 |
| Peak memory | 597760 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1454115364 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.xbar_stress_all.1454115364 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/13.xbar_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/13.xbar_stress_all_with_error.4159953657 |
| Short name | T828 |
| Test name | |
| Test status | |
| Simulation time | 3517586142 ps |
| CPU time | 174.38 seconds |
| Started | Aug 24 04:43:57 AM UTC 24 |
| Finished | Aug 24 04:46:55 AM UTC 24 |
| Peak memory | 598020 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4159953657 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.xbar_stress_all_with_error.4159953657 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/13.xbar_stress_all_with_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/13.xbar_stress_all_with_rand_reset.533052150 |
| Short name | T621 |
| Test name | |
| Test status | |
| Simulation time | 1579132571 ps |
| CPU time | 342.93 seconds |
| Started | Aug 24 04:43:49 AM UTC 24 |
| Finished | Aug 24 04:49:37 AM UTC 24 |
| Peak memory | 597944 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=533052150 -assert nopostproc +UVM_TESTNAME =xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.xbar_stress_all_with_rand_reset.533052150 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/13.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/13.xbar_stress_all_with_reset_error.3709259863 |
| Short name | T855 |
| Test name | |
| Test status | |
| Simulation time | 2524418662 ps |
| CPU time | 178.38 seconds |
| Started | Aug 24 04:43:59 AM UTC 24 |
| Finished | Aug 24 04:47:00 AM UTC 24 |
| Peak memory | 597992 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3709259863 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.xbar_stress_all_with_reset_error.3709259863 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/13.xbar_stress_all_with_reset_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/13.xbar_unmapped_addr.3361783649 |
| Short name | T1446 |
| Test name | |
| Test status | |
| Simulation time | 1142677471 ps |
| CPU time | 34.45 seconds |
| Started | Aug 24 04:43:10 AM UTC 24 |
| Finished | Aug 24 04:43:46 AM UTC 24 |
| Peak memory | 597948 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3361783649 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.xbar_unmapped_addr.3361783649 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/13.xbar_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/14.chip_csr_mem_rw_with_rand_reset.1005698062 |
| Short name | T1476 |
| Test name | |
| Test status | |
| Simulation time | 6177459511 ps |
| CPU time | 351.09 seconds |
| Started | Aug 24 04:47:52 AM UTC 24 |
| Finished | Aug 24 04:53:47 AM UTC 24 |
| Peak memory | 660308 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000 000000 +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/too ls/sim.tcl +ntb_random_seed=1005698062 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/nul l -cm_name 14.chip_csr_mem_rw_with_rand_reset.1005698062 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/14.chip_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/14.chip_csr_rw.4253309340 |
| Short name | T445 |
| Test name | |
| Test status | |
| Simulation time | 6229064340 ps |
| CPU time | 399.39 seconds |
| Started | Aug 24 04:47:52 AM UTC 24 |
| Finished | Aug 24 04:54:36 AM UTC 24 |
| Peak memory | 619456 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +stub_cpu=1 +cdc_instrumentation_ena bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4253309340 -assert nopost proc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os _regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.chip_csr_rw.4253309340 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/14.chip_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/14.chip_same_csr_outstanding.127187227 |
| Short name | T1509 |
| Test name | |
| Test status | |
| Simulation time | 15941662298 ps |
| CPU time | 1039.35 seconds |
| Started | Aug 24 04:44:18 AM UTC 24 |
| Finished | Aug 24 05:01:49 AM UTC 24 |
| Peak memory | 613320 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +test_timeout_ns=120_000_000 +run_same_csr_outstanding +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim .tcl +ntb_random_seed=127187227 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n ame 14.chip_same_csr_outstanding.127187227 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/14.chip_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/14.chip_tl_errors.4049354142 |
| Short name | T572 |
| Test name | |
| Test status | |
| Simulation time | 3783701965 ps |
| CPU time | 186.63 seconds |
| Started | Aug 24 04:44:28 AM UTC 24 |
| Finished | Aug 24 04:47:37 AM UTC 24 |
| Peak memory | 623632 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enable d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4049354142 -assert nopostpro c +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.chip_tl_errors.4049354142 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/14.chip_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/14.xbar_access_same_device.3276245064 |
| Short name | T463 |
| Test name | |
| Test status | |
| Simulation time | 840300331 ps |
| CPU time | 51.78 seconds |
| Started | Aug 24 04:46:26 AM UTC 24 |
| Finished | Aug 24 04:47:19 AM UTC 24 |
| Peak memory | 597864 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3276245064 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.xbar_access_same_device.3276245064 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/14.xbar_access_same_device/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/14.xbar_access_same_device_slow_rsp.3676533839 |
| Short name | T804 |
| Test name | |
| Test status | |
| Simulation time | 104582783134 ps |
| CPU time | 1185.14 seconds |
| Started | Aug 24 04:46:38 AM UTC 24 |
| Finished | Aug 24 05:06:35 AM UTC 24 |
| Peak memory | 598944 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3676533839 -assert nopostproc +UVM_T ESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.xbar_access_same_device_slow_rsp.3676533839 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/14.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/14.xbar_error_and_unmapped_addr.3108011409 |
| Short name | T1460 |
| Test name | |
| Test status | |
| Simulation time | 1229972589 ps |
| CPU time | 35.45 seconds |
| Started | Aug 24 04:47:33 AM UTC 24 |
| Finished | Aug 24 04:48:10 AM UTC 24 |
| Peak memory | 597840 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3108011409 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.xbar_error_and_unmapped_addr.3108011409 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/14.xbar_error_and_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/14.xbar_error_random.1123862787 |
| Short name | T1455 |
| Test name | |
| Test status | |
| Simulation time | 594889266 ps |
| CPU time | 17.24 seconds |
| Started | Aug 24 04:47:09 AM UTC 24 |
| Finished | Aug 24 04:47:28 AM UTC 24 |
| Peak memory | 597920 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1123862787 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.xbar_error_random.1123862787 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/14.xbar_error_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/14.xbar_random.1466097907 |
| Short name | T524 |
| Test name | |
| Test status | |
| Simulation time | 305721382 ps |
| CPU time | 22.08 seconds |
| Started | Aug 24 04:45:17 AM UTC 24 |
| Finished | Aug 24 04:45:40 AM UTC 24 |
| Peak memory | 597688 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1466097907 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.xbar_random.1466097907 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/14.xbar_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/14.xbar_random_large_delays.3463134000 |
| Short name | T1468 |
| Test name | |
| Test status | |
| Simulation time | 30945608917 ps |
| CPU time | 245.16 seconds |
| Started | Aug 24 04:45:55 AM UTC 24 |
| Finished | Aug 24 04:50:03 AM UTC 24 |
| Peak memory | 597824 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max _device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3463134000 -assert nopostproc +U VM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.xbar_random_large_delays.3463134000 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/14.xbar_random_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/14.xbar_random_slow_rsp.1272495587 |
| Short name | T1454 |
| Test name | |
| Test status | |
| Simulation time | 2805635069 ps |
| CPU time | 33.75 seconds |
| Started | Aug 24 04:46:17 AM UTC 24 |
| Finished | Aug 24 04:46:52 AM UTC 24 |
| Peak memory | 595704 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1272495587 -assert nopostproc +UVM_T ESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.xbar_random_slow_rsp.1272495587 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/14.xbar_random_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/14.xbar_random_zero_delays.2371542208 |
| Short name | T1452 |
| Test name | |
| Test status | |
| Simulation time | 316496169 ps |
| CPU time | 22.94 seconds |
| Started | Aug 24 04:45:48 AM UTC 24 |
| Finished | Aug 24 04:46:12 AM UTC 24 |
| Peak memory | 597824 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2371542208 -assert nopostpr oc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.xbar_random_zero_delays.2371542208 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/14.xbar_random_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/14.xbar_same_source.1046342688 |
| Short name | T1458 |
| Test name | |
| Test status | |
| Simulation time | 1072335094 ps |
| CPU time | 25.6 seconds |
| Started | Aug 24 04:47:06 AM UTC 24 |
| Finished | Aug 24 04:47:33 AM UTC 24 |
| Peak memory | 597836 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1046342688 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.xbar_same_source.1046342688 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/14.xbar_same_source/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/14.xbar_smoke.3000206761 |
| Short name | T1448 |
| Test name | |
| Test status | |
| Simulation time | 49797498 ps |
| CPU time | 5.2 seconds |
| Started | Aug 24 04:44:41 AM UTC 24 |
| Finished | Aug 24 04:44:47 AM UTC 24 |
| Peak memory | 595640 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3000206761 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 8_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.xbar_smoke.3000206761 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/14.xbar_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/14.xbar_smoke_large_delays.2027246841 |
| Short name | T1453 |
| Test name | |
| Test status | |
| Simulation time | 10178073101 ps |
| CPU time | 80.7 seconds |
| Started | Aug 24 04:45:02 AM UTC 24 |
| Finished | Aug 24 04:46:24 AM UTC 24 |
| Peak memory | 595768 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max _device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2027246841 -assert nopostproc +U VM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.xbar_smoke_large_delays.2027246841 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/14.xbar_smoke_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/14.xbar_smoke_slow_rsp.1515951213 |
| Short name | T1451 |
| Test name | |
| Test status | |
| Simulation time | 4842882839 ps |
| CPU time | 58.28 seconds |
| Started | Aug 24 04:45:03 AM UTC 24 |
| Finished | Aug 24 04:46:03 AM UTC 24 |
| Peak memory | 595772 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1515951213 -assert nopostproc +UVM_T ESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.xbar_smoke_slow_rsp.1515951213 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/14.xbar_smoke_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/14.xbar_smoke_zero_delays.1319433668 |
| Short name | T1449 |
| Test name | |
| Test status | |
| Simulation time | 38586144 ps |
| CPU time | 5.06 seconds |
| Started | Aug 24 04:44:57 AM UTC 24 |
| Finished | Aug 24 04:45:03 AM UTC 24 |
| Peak memory | 595836 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1319433668 -assert nopostpr oc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.xbar_smoke_zero_delays.1319433668 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/14.xbar_smoke_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/14.xbar_stress_all.2324884859 |
| Short name | T491 |
| Test name | |
| Test status | |
| Simulation time | 6083761428 ps |
| CPU time | 173.04 seconds |
| Started | Aug 24 04:47:42 AM UTC 24 |
| Finished | Aug 24 04:50:38 AM UTC 24 |
| Peak memory | 597892 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2324884859 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.xbar_stress_all.2324884859 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/14.xbar_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/14.xbar_stress_all_with_error.2929892349 |
| Short name | T1467 |
| Test name | |
| Test status | |
| Simulation time | 5303542966 ps |
| CPU time | 122.85 seconds |
| Started | Aug 24 04:47:46 AM UTC 24 |
| Finished | Aug 24 04:49:52 AM UTC 24 |
| Peak memory | 597824 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2929892349 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.xbar_stress_all_with_error.2929892349 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/14.xbar_stress_all_with_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/14.xbar_stress_all_with_rand_reset.2489159383 |
| Short name | T822 |
| Test name | |
| Test status | |
| Simulation time | 2057041839 ps |
| CPU time | 212.42 seconds |
| Started | Aug 24 04:47:45 AM UTC 24 |
| Finished | Aug 24 04:51:21 AM UTC 24 |
| Peak memory | 597912 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2489159383 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.xbar_stress_all_with_rand_reset.2489159383 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/14.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/14.xbar_stress_all_with_reset_error.4152542018 |
| Short name | T1461 |
| Test name | |
| Test status | |
| Simulation time | 107346665 ps |
| CPU time | 43.57 seconds |
| Started | Aug 24 04:47:48 AM UTC 24 |
| Finished | Aug 24 04:48:33 AM UTC 24 |
| Peak memory | 597920 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4152542018 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.xbar_stress_all_with_reset_error.4152542018 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/14.xbar_stress_all_with_reset_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/14.xbar_unmapped_addr.2129711354 |
| Short name | T1457 |
| Test name | |
| Test status | |
| Simulation time | 443163659 ps |
| CPU time | 16.61 seconds |
| Started | Aug 24 04:47:14 AM UTC 24 |
| Finished | Aug 24 04:47:32 AM UTC 24 |
| Peak memory | 597692 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2129711354 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.xbar_unmapped_addr.2129711354 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/14.xbar_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/15.chip_csr_mem_rw_with_rand_reset.3600085214 |
| Short name | T446 |
| Test name | |
| Test status | |
| Simulation time | 8478910631 ps |
| CPU time | 657.33 seconds |
| Started | Aug 24 04:51:28 AM UTC 24 |
| Finished | Aug 24 05:02:33 AM UTC 24 |
| Peak memory | 666668 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000 000000 +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/too ls/sim.tcl +ntb_random_seed=3600085214 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/nul l -cm_name 15.chip_csr_mem_rw_with_rand_reset.3600085214 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/15.chip_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/15.chip_csr_rw.250585826 |
| Short name | T1486 |
| Test name | |
| Test status | |
| Simulation time | 4182940436 ps |
| CPU time | 266.77 seconds |
| Started | Aug 24 04:51:19 AM UTC 24 |
| Finished | Aug 24 04:55:49 AM UTC 24 |
| Peak memory | 617180 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +stub_cpu=1 +cdc_instrumentation_ena bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=250585826 -assert nopostp roc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_ regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.chip_csr_rw.250585826 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/15.chip_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/15.chip_same_csr_outstanding.256940926 |
| Short name | T1673 |
| Test name | |
| Test status | |
| Simulation time | 31220738855 ps |
| CPU time | 2619.71 seconds |
| Started | Aug 24 04:48:25 AM UTC 24 |
| Finished | Aug 24 05:32:31 AM UTC 24 |
| Peak memory | 614108 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +test_timeout_ns=120_000_000 +run_same_csr_outstanding +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim .tcl +ntb_random_seed=256940926 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n ame 15.chip_same_csr_outstanding.256940926 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/15.chip_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/15.xbar_access_same_device.3465482114 |
| Short name | T824 |
| Test name | |
| Test status | |
| Simulation time | 877235799 ps |
| CPU time | 31.66 seconds |
| Started | Aug 24 04:50:05 AM UTC 24 |
| Finished | Aug 24 04:50:38 AM UTC 24 |
| Peak memory | 597704 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3465482114 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.xbar_access_same_device.3465482114 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/15.xbar_access_same_device/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/15.xbar_error_and_unmapped_addr.345580731 |
| Short name | T1475 |
| Test name | |
| Test status | |
| Simulation time | 222788023 ps |
| CPU time | 19.55 seconds |
| Started | Aug 24 04:50:53 AM UTC 24 |
| Finished | Aug 24 04:51:13 AM UTC 24 |
| Peak memory | 597692 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=345580731 -assert nopostproc +UVM_TESTNAME =xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.xbar_error_and_unmapped_addr.345580731 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/15.xbar_error_and_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/15.xbar_error_random.1553728310 |
| Short name | T1472 |
| Test name | |
| Test status | |
| Simulation time | 254738589 ps |
| CPU time | 8.72 seconds |
| Started | Aug 24 04:50:38 AM UTC 24 |
| Finished | Aug 24 04:50:48 AM UTC 24 |
| Peak memory | 597984 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1553728310 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.xbar_error_random.1553728310 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/15.xbar_error_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/15.xbar_random.3681689686 |
| Short name | T1466 |
| Test name | |
| Test status | |
| Simulation time | 237423529 ps |
| CPU time | 18.31 seconds |
| Started | Aug 24 04:49:23 AM UTC 24 |
| Finished | Aug 24 04:49:42 AM UTC 24 |
| Peak memory | 597688 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3681689686 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.xbar_random.3681689686 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/15.xbar_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/15.xbar_random_large_delays.3978292823 |
| Short name | T510 |
| Test name | |
| Test status | |
| Simulation time | 112250605837 ps |
| CPU time | 861.42 seconds |
| Started | Aug 24 04:49:52 AM UTC 24 |
| Finished | Aug 24 05:04:22 AM UTC 24 |
| Peak memory | 597820 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max _device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3978292823 -assert nopostproc +U VM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.xbar_random_large_delays.3978292823 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/15.xbar_random_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/15.xbar_random_slow_rsp.245689071 |
| Short name | T1490 |
| Test name | |
| Test status | |
| Simulation time | 31316743743 ps |
| CPU time | 378.72 seconds |
| Started | Aug 24 04:49:56 AM UTC 24 |
| Finished | Aug 24 04:56:20 AM UTC 24 |
| Peak memory | 597824 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=245689071 -assert nopostproc +UVM_TE STNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.xbar_random_slow_rsp.245689071 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/15.xbar_random_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/15.xbar_random_zero_delays.2040410864 |
| Short name | T1470 |
| Test name | |
| Test status | |
| Simulation time | 485443099 ps |
| CPU time | 31.93 seconds |
| Started | Aug 24 04:49:50 AM UTC 24 |
| Finished | Aug 24 04:50:24 AM UTC 24 |
| Peak memory | 597700 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2040410864 -assert nopostpr oc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.xbar_random_zero_delays.2040410864 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/15.xbar_random_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/15.xbar_same_source.4238523268 |
| Short name | T1473 |
| Test name | |
| Test status | |
| Simulation time | 506040821 ps |
| CPU time | 25.44 seconds |
| Started | Aug 24 04:50:25 AM UTC 24 |
| Finished | Aug 24 04:50:52 AM UTC 24 |
| Peak memory | 597820 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4238523268 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.xbar_same_source.4238523268 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/15.xbar_same_source/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/15.xbar_smoke.1715645706 |
| Short name | T1462 |
| Test name | |
| Test status | |
| Simulation time | 45268597 ps |
| CPU time | 5.42 seconds |
| Started | Aug 24 04:49:01 AM UTC 24 |
| Finished | Aug 24 04:49:07 AM UTC 24 |
| Peak memory | 595628 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1715645706 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 8_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.xbar_smoke.1715645706 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/15.xbar_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/15.xbar_smoke_large_delays.592864103 |
| Short name | T1469 |
| Test name | |
| Test status | |
| Simulation time | 7204380197 ps |
| CPU time | 57.79 seconds |
| Started | Aug 24 04:49:12 AM UTC 24 |
| Finished | Aug 24 04:50:11 AM UTC 24 |
| Peak memory | 595764 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max _device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=592864103 -assert nopostproc +UV M_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.xbar_smoke_large_delays.592864103 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/15.xbar_smoke_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/15.xbar_smoke_slow_rsp.2948158188 |
| Short name | T1471 |
| Test name | |
| Test status | |
| Simulation time | 5978635663 ps |
| CPU time | 74.86 seconds |
| Started | Aug 24 04:49:22 AM UTC 24 |
| Finished | Aug 24 04:50:38 AM UTC 24 |
| Peak memory | 596020 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2948158188 -assert nopostproc +UVM_T ESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.xbar_smoke_slow_rsp.2948158188 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/15.xbar_smoke_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/15.xbar_smoke_zero_delays.80538753 |
| Short name | T1464 |
| Test name | |
| Test status | |
| Simulation time | 47422109 ps |
| CPU time | 5.21 seconds |
| Started | Aug 24 04:49:03 AM UTC 24 |
| Finished | Aug 24 04:49:09 AM UTC 24 |
| Peak memory | 595632 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=80538753 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.xbar_smoke_zero_delays.80538753 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/15.xbar_smoke_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/15.xbar_stress_all.1044277653 |
| Short name | T473 |
| Test name | |
| Test status | |
| Simulation time | 9963346484 ps |
| CPU time | 240.15 seconds |
| Started | Aug 24 04:50:53 AM UTC 24 |
| Finished | Aug 24 04:54:57 AM UTC 24 |
| Peak memory | 597824 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1044277653 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.xbar_stress_all.1044277653 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/15.xbar_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/15.xbar_stress_all_with_error.4001808781 |
| Short name | T826 |
| Test name | |
| Test status | |
| Simulation time | 14244426947 ps |
| CPU time | 351.4 seconds |
| Started | Aug 24 04:51:06 AM UTC 24 |
| Finished | Aug 24 04:57:02 AM UTC 24 |
| Peak memory | 597820 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4001808781 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.xbar_stress_all_with_error.4001808781 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/15.xbar_stress_all_with_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/15.xbar_stress_all_with_rand_reset.2309858161 |
| Short name | T846 |
| Test name | |
| Test status | |
| Simulation time | 16671941713 ps |
| CPU time | 628.87 seconds |
| Started | Aug 24 04:51:02 AM UTC 24 |
| Finished | Aug 24 05:01:38 AM UTC 24 |
| Peak memory | 597820 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2309858161 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.xbar_stress_all_with_rand_reset.2309858161 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/15.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/15.xbar_stress_all_with_reset_error.2142478904 |
| Short name | T858 |
| Test name | |
| Test status | |
| Simulation time | 2068643274 ps |
| CPU time | 194.63 seconds |
| Started | Aug 24 04:51:09 AM UTC 24 |
| Finished | Aug 24 04:54:27 AM UTC 24 |
| Peak memory | 597920 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2142478904 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.xbar_stress_all_with_reset_error.2142478904 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/15.xbar_stress_all_with_reset_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/15.xbar_unmapped_addr.3068980370 |
| Short name | T1474 |
| Test name | |
| Test status | |
| Simulation time | 109213381 ps |
| CPU time | 11.1 seconds |
| Started | Aug 24 04:50:53 AM UTC 24 |
| Finished | Aug 24 04:51:05 AM UTC 24 |
| Peak memory | 597908 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3068980370 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.xbar_unmapped_addr.3068980370 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/15.xbar_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/16.chip_csr_mem_rw_with_rand_reset.3204844072 |
| Short name | T1514 |
| Test name | |
| Test status | |
| Simulation time | 6733935600 ps |
| CPU time | 387.47 seconds |
| Started | Aug 24 04:56:35 AM UTC 24 |
| Finished | Aug 24 05:03:07 AM UTC 24 |
| Peak memory | 660308 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000 000000 +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/too ls/sim.tcl +ntb_random_seed=3204844072 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/nul l -cm_name 16.chip_csr_mem_rw_with_rand_reset.3204844072 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/16.chip_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/16.chip_csr_rw.2109926676 |
| Short name | T1515 |
| Test name | |
| Test status | |
| Simulation time | 5678222576 ps |
| CPU time | 405.56 seconds |
| Started | Aug 24 04:56:32 AM UTC 24 |
| Finished | Aug 24 05:03:23 AM UTC 24 |
| Peak memory | 619224 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +stub_cpu=1 +cdc_instrumentation_ena bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2109926676 -assert nopost proc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os _regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.chip_csr_rw.2109926676 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/16.chip_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/16.chip_same_csr_outstanding.1431031827 |
| Short name | T1742 |
| Test name | |
| Test status | |
| Simulation time | 34532335374 ps |
| CPU time | 2980.4 seconds |
| Started | Aug 24 04:51:35 AM UTC 24 |
| Finished | Aug 24 05:41:45 AM UTC 24 |
| Peak memory | 614108 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +test_timeout_ns=120_000_000 +run_same_csr_outstanding +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim .tcl +ntb_random_seed=1431031827 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_ name 16.chip_same_csr_outstanding.1431031827 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/16.chip_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/16.xbar_access_same_device.3844118770 |
| Short name | T1482 |
| Test name | |
| Test status | |
| Simulation time | 288232754 ps |
| CPU time | 10.89 seconds |
| Started | Aug 24 04:55:16 AM UTC 24 |
| Finished | Aug 24 04:55:28 AM UTC 24 |
| Peak memory | 595720 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3844118770 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.xbar_access_same_device.3844118770 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/16.xbar_access_same_device/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/16.xbar_access_same_device_slow_rsp.2645898573 |
| Short name | T810 |
| Test name | |
| Test status | |
| Simulation time | 57874739362 ps |
| CPU time | 657.58 seconds |
| Started | Aug 24 04:55:19 AM UTC 24 |
| Finished | Aug 24 05:06:23 AM UTC 24 |
| Peak memory | 597820 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2645898573 -assert nopostproc +UVM_T ESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.xbar_access_same_device_slow_rsp.2645898573 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/16.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/16.xbar_error_and_unmapped_addr.170989445 |
| Short name | T1489 |
| Test name | |
| Test status | |
| Simulation time | 1111909700 ps |
| CPU time | 31.07 seconds |
| Started | Aug 24 04:55:46 AM UTC 24 |
| Finished | Aug 24 04:56:18 AM UTC 24 |
| Peak memory | 597692 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=170989445 -assert nopostproc +UVM_TESTNAME =xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.xbar_error_and_unmapped_addr.170989445 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/16.xbar_error_and_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/16.xbar_error_random.4037557338 |
| Short name | T1487 |
| Test name | |
| Test status | |
| Simulation time | 373999165 ps |
| CPU time | 11.36 seconds |
| Started | Aug 24 04:55:43 AM UTC 24 |
| Finished | Aug 24 04:55:55 AM UTC 24 |
| Peak memory | 597692 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4037557338 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.xbar_error_random.4037557338 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/16.xbar_error_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/16.xbar_random.1968950666 |
| Short name | T1480 |
| Test name | |
| Test status | |
| Simulation time | 298385194 ps |
| CPU time | 21.5 seconds |
| Started | Aug 24 04:54:41 AM UTC 24 |
| Finished | Aug 24 04:55:04 AM UTC 24 |
| Peak memory | 597752 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1968950666 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.xbar_random.1968950666 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/16.xbar_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/16.xbar_random_large_delays.3460166931 |
| Short name | T1500 |
| Test name | |
| Test status | |
| Simulation time | 29226182639 ps |
| CPU time | 235.29 seconds |
| Started | Aug 24 04:54:50 AM UTC 24 |
| Finished | Aug 24 04:58:49 AM UTC 24 |
| Peak memory | 597820 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max _device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3460166931 -assert nopostproc +U VM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.xbar_random_large_delays.3460166931 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/16.xbar_random_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/16.xbar_random_slow_rsp.4121371441 |
| Short name | T488 |
| Test name | |
| Test status | |
| Simulation time | 41335950440 ps |
| CPU time | 499.23 seconds |
| Started | Aug 24 04:55:11 AM UTC 24 |
| Finished | Aug 24 05:03:35 AM UTC 24 |
| Peak memory | 597820 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4121371441 -assert nopostproc +UVM_T ESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.xbar_random_slow_rsp.4121371441 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/16.xbar_random_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/16.xbar_random_zero_delays.3280068568 |
| Short name | T1481 |
| Test name | |
| Test status | |
| Simulation time | 345116295 ps |
| CPU time | 25.36 seconds |
| Started | Aug 24 04:54:42 AM UTC 24 |
| Finished | Aug 24 04:55:09 AM UTC 24 |
| Peak memory | 597696 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3280068568 -assert nopostpr oc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.xbar_random_zero_delays.3280068568 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/16.xbar_random_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/16.xbar_same_source.3022390001 |
| Short name | T1484 |
| Test name | |
| Test status | |
| Simulation time | 82395919 ps |
| CPU time | 7.66 seconds |
| Started | Aug 24 04:55:23 AM UTC 24 |
| Finished | Aug 24 04:55:31 AM UTC 24 |
| Peak memory | 597688 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3022390001 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.xbar_same_source.3022390001 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/16.xbar_same_source/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/16.xbar_smoke.2452993822 |
| Short name | T1477 |
| Test name | |
| Test status | |
| Simulation time | 52812913 ps |
| CPU time | 5.45 seconds |
| Started | Aug 24 04:54:01 AM UTC 24 |
| Finished | Aug 24 04:54:08 AM UTC 24 |
| Peak memory | 595752 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2452993822 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 8_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.xbar_smoke.2452993822 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/16.xbar_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/16.xbar_smoke_large_delays.2874468496 |
| Short name | T1483 |
| Test name | |
| Test status | |
| Simulation time | 7154229467 ps |
| CPU time | 60.43 seconds |
| Started | Aug 24 04:54:28 AM UTC 24 |
| Finished | Aug 24 04:55:30 AM UTC 24 |
| Peak memory | 595764 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max _device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2874468496 -assert nopostproc +U VM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.xbar_smoke_large_delays.2874468496 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/16.xbar_smoke_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/16.xbar_smoke_slow_rsp.1466947008 |
| Short name | T1485 |
| Test name | |
| Test status | |
| Simulation time | 4980102535 ps |
| CPU time | 59.17 seconds |
| Started | Aug 24 04:54:32 AM UTC 24 |
| Finished | Aug 24 04:55:33 AM UTC 24 |
| Peak memory | 595912 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1466947008 -assert nopostproc +UVM_T ESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.xbar_smoke_slow_rsp.1466947008 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/16.xbar_smoke_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/16.xbar_smoke_zero_delays.1804034244 |
| Short name | T1479 |
| Test name | |
| Test status | |
| Simulation time | 46217328 ps |
| CPU time | 4.94 seconds |
| Started | Aug 24 04:54:22 AM UTC 24 |
| Finished | Aug 24 04:54:28 AM UTC 24 |
| Peak memory | 595636 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1804034244 -assert nopostpr oc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.xbar_smoke_zero_delays.1804034244 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/16.xbar_smoke_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/16.xbar_stress_all.60388278 |
| Short name | T479 |
| Test name | |
| Test status | |
| Simulation time | 8770244900 ps |
| CPU time | 242.07 seconds |
| Started | Aug 24 04:55:47 AM UTC 24 |
| Finished | Aug 24 04:59:52 AM UTC 24 |
| Peak memory | 597896 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=60388278 -assert nopostproc +UVM_TESTNAME= xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.xbar_stress_all.60388278 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/16.xbar_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/16.xbar_stress_all_with_error.3539802363 |
| Short name | T1495 |
| Test name | |
| Test status | |
| Simulation time | 2875474435 ps |
| CPU time | 69.25 seconds |
| Started | Aug 24 04:56:10 AM UTC 24 |
| Finished | Aug 24 04:57:21 AM UTC 24 |
| Peak memory | 597756 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3539802363 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.xbar_stress_all_with_error.3539802363 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/16.xbar_stress_all_with_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/16.xbar_stress_all_with_rand_reset.2550831612 |
| Short name | T837 |
| Test name | |
| Test status | |
| Simulation time | 897779604 ps |
| CPU time | 319.88 seconds |
| Started | Aug 24 04:56:04 AM UTC 24 |
| Finished | Aug 24 05:01:28 AM UTC 24 |
| Peak memory | 597692 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2550831612 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.xbar_stress_all_with_rand_reset.2550831612 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/16.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/16.xbar_stress_all_with_reset_error.1011577536 |
| Short name | T865 |
| Test name | |
| Test status | |
| Simulation time | 157632437 ps |
| CPU time | 28.97 seconds |
| Started | Aug 24 04:56:15 AM UTC 24 |
| Finished | Aug 24 04:56:45 AM UTC 24 |
| Peak memory | 597696 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1011577536 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.xbar_stress_all_with_reset_error.1011577536 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/16.xbar_stress_all_with_reset_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/16.xbar_unmapped_addr.2179076124 |
| Short name | T1488 |
| Test name | |
| Test status | |
| Simulation time | 154225434 ps |
| CPU time | 15.71 seconds |
| Started | Aug 24 04:55:44 AM UTC 24 |
| Finished | Aug 24 04:56:01 AM UTC 24 |
| Peak memory | 597696 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2179076124 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.xbar_unmapped_addr.2179076124 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/16.xbar_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/17.chip_csr_mem_rw_with_rand_reset.976416917 |
| Short name | T1538 |
| Test name | |
| Test status | |
| Simulation time | 7804016160 ps |
| CPU time | 474.73 seconds |
| Started | Aug 24 05:01:19 AM UTC 24 |
| Finished | Aug 24 05:09:19 AM UTC 24 |
| Peak memory | 672604 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000 000000 +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/too ls/sim.tcl +ntb_random_seed=976416917 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.chip_csr_mem_rw_with_rand_reset.976416917 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/17.chip_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/17.chip_csr_rw.2793703350 |
| Short name | T1521 |
| Test name | |
| Test status | |
| Simulation time | 4568599234 ps |
| CPU time | 308.43 seconds |
| Started | Aug 24 05:00:06 AM UTC 24 |
| Finished | Aug 24 05:05:19 AM UTC 24 |
| Peak memory | 619224 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +stub_cpu=1 +cdc_instrumentation_ena bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2793703350 -assert nopost proc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os _regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.chip_csr_rw.2793703350 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/17.chip_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/17.chip_same_csr_outstanding.3974826448 |
| Short name | T1715 |
| Test name | |
| Test status | |
| Simulation time | 27581671419 ps |
| CPU time | 2450.02 seconds |
| Started | Aug 24 04:56:52 AM UTC 24 |
| Finished | Aug 24 05:38:06 AM UTC 24 |
| Peak memory | 614256 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +test_timeout_ns=120_000_000 +run_same_csr_outstanding +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim .tcl +ntb_random_seed=3974826448 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_ name 17.chip_same_csr_outstanding.3974826448 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/17.chip_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/17.xbar_access_same_device.2427338670 |
| Short name | T1502 |
| Test name | |
| Test status | |
| Simulation time | 1224364778 ps |
| CPU time | 41.09 seconds |
| Started | Aug 24 04:58:36 AM UTC 24 |
| Finished | Aug 24 04:59:18 AM UTC 24 |
| Peak memory | 597928 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2427338670 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.xbar_access_same_device.2427338670 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/17.xbar_access_same_device/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/17.xbar_error_and_unmapped_addr.2562055011 |
| Short name | T1506 |
| Test name | |
| Test status | |
| Simulation time | 99849972 ps |
| CPU time | 10.25 seconds |
| Started | Aug 24 04:59:32 AM UTC 24 |
| Finished | Aug 24 04:59:43 AM UTC 24 |
| Peak memory | 597904 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2562055011 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.xbar_error_and_unmapped_addr.2562055011 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/17.xbar_error_and_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/17.xbar_error_random.4223721348 |
| Short name | T1504 |
| Test name | |
| Test status | |
| Simulation time | 1330312001 ps |
| CPU time | 32.75 seconds |
| Started | Aug 24 04:59:03 AM UTC 24 |
| Finished | Aug 24 04:59:37 AM UTC 24 |
| Peak memory | 597692 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4223721348 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.xbar_error_random.4223721348 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/17.xbar_error_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/17.xbar_random.3274843234 |
| Short name | T1498 |
| Test name | |
| Test status | |
| Simulation time | 2511942132 ps |
| CPU time | 68.47 seconds |
| Started | Aug 24 04:57:20 AM UTC 24 |
| Finished | Aug 24 04:58:30 AM UTC 24 |
| Peak memory | 597768 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3274843234 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.xbar_random.3274843234 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/17.xbar_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/17.xbar_random_large_delays.854295890 |
| Short name | T1503 |
| Test name | |
| Test status | |
| Simulation time | 12484193666 ps |
| CPU time | 102.28 seconds |
| Started | Aug 24 04:57:35 AM UTC 24 |
| Finished | Aug 24 04:59:19 AM UTC 24 |
| Peak memory | 597820 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max _device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=854295890 -assert nopostproc +UV M_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.xbar_random_large_delays.854295890 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/17.xbar_random_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/17.xbar_random_slow_rsp.544635302 |
| Short name | T1522 |
| Test name | |
| Test status | |
| Simulation time | 36812957914 ps |
| CPU time | 428.78 seconds |
| Started | Aug 24 04:58:14 AM UTC 24 |
| Finished | Aug 24 05:05:27 AM UTC 24 |
| Peak memory | 598064 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=544635302 -assert nopostproc +UVM_TE STNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.xbar_random_slow_rsp.544635302 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/17.xbar_random_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/17.xbar_random_zero_delays.77252647 |
| Short name | T1496 |
| Test name | |
| Test status | |
| Simulation time | 525178583 ps |
| CPU time | 36.93 seconds |
| Started | Aug 24 04:57:22 AM UTC 24 |
| Finished | Aug 24 04:58:00 AM UTC 24 |
| Peak memory | 597760 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=77252647 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.xbar_random_zero_delays.77252647 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/17.xbar_random_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/17.xbar_same_source.698679959 |
| Short name | T1501 |
| Test name | |
| Test status | |
| Simulation time | 932138573 ps |
| CPU time | 21.81 seconds |
| Started | Aug 24 04:58:45 AM UTC 24 |
| Finished | Aug 24 04:59:08 AM UTC 24 |
| Peak memory | 597744 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=698679959 -assert nopostproc +UVM_TESTNAME =xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.xbar_same_source.698679959 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/17.xbar_same_source/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/17.xbar_smoke.1376152525 |
| Short name | T1493 |
| Test name | |
| Test status | |
| Simulation time | 35602284 ps |
| CPU time | 4.8 seconds |
| Started | Aug 24 04:56:59 AM UTC 24 |
| Finished | Aug 24 04:57:05 AM UTC 24 |
| Peak memory | 595848 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1376152525 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 8_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.xbar_smoke.1376152525 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/17.xbar_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/17.xbar_smoke_large_delays.2426052476 |
| Short name | T1499 |
| Test name | |
| Test status | |
| Simulation time | 9029073571 ps |
| CPU time | 74.22 seconds |
| Started | Aug 24 04:57:15 AM UTC 24 |
| Finished | Aug 24 04:58:31 AM UTC 24 |
| Peak memory | 596020 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max _device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2426052476 -assert nopostproc +U VM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.xbar_smoke_large_delays.2426052476 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/17.xbar_smoke_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/17.xbar_smoke_slow_rsp.1025514229 |
| Short name | T1497 |
| Test name | |
| Test status | |
| Simulation time | 4781614122 ps |
| CPU time | 62.29 seconds |
| Started | Aug 24 04:57:18 AM UTC 24 |
| Finished | Aug 24 04:58:21 AM UTC 24 |
| Peak memory | 595896 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1025514229 -assert nopostproc +UVM_T ESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.xbar_smoke_slow_rsp.1025514229 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/17.xbar_smoke_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/17.xbar_smoke_zero_delays.3286969381 |
| Short name | T1494 |
| Test name | |
| Test status | |
| Simulation time | 39694123 ps |
| CPU time | 5.06 seconds |
| Started | Aug 24 04:57:01 AM UTC 24 |
| Finished | Aug 24 04:57:07 AM UTC 24 |
| Peak memory | 595920 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3286969381 -assert nopostpr oc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.xbar_smoke_zero_delays.3286969381 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/17.xbar_smoke_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/17.xbar_stress_all.2237019149 |
| Short name | T520 |
| Test name | |
| Test status | |
| Simulation time | 2647416052 ps |
| CPU time | 143.81 seconds |
| Started | Aug 24 04:59:34 AM UTC 24 |
| Finished | Aug 24 05:02:00 AM UTC 24 |
| Peak memory | 597764 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2237019149 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.xbar_stress_all.2237019149 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/17.xbar_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/17.xbar_stress_all_with_error.3683590924 |
| Short name | T791 |
| Test name | |
| Test status | |
| Simulation time | 15307311957 ps |
| CPU time | 368.76 seconds |
| Started | Aug 24 04:59:54 AM UTC 24 |
| Finished | Aug 24 05:06:07 AM UTC 24 |
| Peak memory | 597992 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3683590924 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.xbar_stress_all_with_error.3683590924 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/17.xbar_stress_all_with_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/17.xbar_stress_all_with_rand_reset.1700223983 |
| Short name | T522 |
| Test name | |
| Test status | |
| Simulation time | 3117369654 ps |
| CPU time | 401.2 seconds |
| Started | Aug 24 04:59:51 AM UTC 24 |
| Finished | Aug 24 05:06:37 AM UTC 24 |
| Peak memory | 597884 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1700223983 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.xbar_stress_all_with_rand_reset.1700223983 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/17.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/17.xbar_stress_all_with_reset_error.630541712 |
| Short name | T833 |
| Test name | |
| Test status | |
| Simulation time | 10957293711 ps |
| CPU time | 387.71 seconds |
| Started | Aug 24 04:59:58 AM UTC 24 |
| Finished | Aug 24 05:06:31 AM UTC 24 |
| Peak memory | 597820 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=630541712 -assert nopostproc +UVM_TESTNAME =xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.xbar_stress_all_with_reset_error.630541712 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/17.xbar_stress_all_with_reset_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/17.xbar_unmapped_addr.3115906633 |
| Short name | T1505 |
| Test name | |
| Test status | |
| Simulation time | 165311716 ps |
| CPU time | 17.13 seconds |
| Started | Aug 24 04:59:22 AM UTC 24 |
| Finished | Aug 24 04:59:40 AM UTC 24 |
| Peak memory | 597700 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3115906633 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.xbar_unmapped_addr.3115906633 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/17.xbar_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/18.chip_csr_mem_rw_with_rand_reset.191606424 |
| Short name | T1556 |
| Test name | |
| Test status | |
| Simulation time | 8702828006 ps |
| CPU time | 509.24 seconds |
| Started | Aug 24 05:04:36 AM UTC 24 |
| Finished | Aug 24 05:13:11 AM UTC 24 |
| Peak memory | 672600 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000 000000 +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/too ls/sim.tcl +ntb_random_seed=191606424 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.chip_csr_mem_rw_with_rand_reset.191606424 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/18.chip_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/18.chip_csr_rw.746629418 |
| Short name | T1536 |
| Test name | |
| Test status | |
| Simulation time | 3871645150 ps |
| CPU time | 239.41 seconds |
| Started | Aug 24 05:04:36 AM UTC 24 |
| Finished | Aug 24 05:08:39 AM UTC 24 |
| Peak memory | 617248 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +stub_cpu=1 +cdc_instrumentation_ena bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=746629418 -assert nopostp roc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_ regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.chip_csr_rw.746629418 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/18.chip_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/18.chip_same_csr_outstanding.1646046693 |
| Short name | T1582 |
| Test name | |
| Test status | |
| Simulation time | 14766173387 ps |
| CPU time | 992.35 seconds |
| Started | Aug 24 05:01:31 AM UTC 24 |
| Finished | Aug 24 05:18:14 AM UTC 24 |
| Peak memory | 613292 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +test_timeout_ns=120_000_000 +run_same_csr_outstanding +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim .tcl +ntb_random_seed=1646046693 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_ name 18.chip_same_csr_outstanding.1646046693 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/18.chip_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/18.xbar_access_same_device.3369140949 |
| Short name | T483 |
| Test name | |
| Test status | |
| Simulation time | 308259569 ps |
| CPU time | 19.28 seconds |
| Started | Aug 24 05:03:11 AM UTC 24 |
| Finished | Aug 24 05:03:31 AM UTC 24 |
| Peak memory | 597928 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3369140949 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.xbar_access_same_device.3369140949 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/18.xbar_access_same_device/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/18.xbar_access_same_device_slow_rsp.3987524018 |
| Short name | T1645 |
| Test name | |
| Test status | |
| Simulation time | 127451111765 ps |
| CPU time | 1514.22 seconds |
| Started | Aug 24 05:03:18 AM UTC 24 |
| Finished | Aug 24 05:28:47 AM UTC 24 |
| Peak memory | 599044 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3987524018 -assert nopostproc +UVM_T ESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.xbar_access_same_device_slow_rsp.3987524018 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/18.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/18.xbar_error_and_unmapped_addr.4056645647 |
| Short name | T1518 |
| Test name | |
| Test status | |
| Simulation time | 282600642 ps |
| CPU time | 22.26 seconds |
| Started | Aug 24 05:03:46 AM UTC 24 |
| Finished | Aug 24 05:04:09 AM UTC 24 |
| Peak memory | 597840 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4056645647 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.xbar_error_and_unmapped_addr.4056645647 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/18.xbar_error_and_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/18.xbar_error_random.205453491 |
| Short name | T1520 |
| Test name | |
| Test status | |
| Simulation time | 2539767197 ps |
| CPU time | 65.74 seconds |
| Started | Aug 24 05:03:28 AM UTC 24 |
| Finished | Aug 24 05:04:35 AM UTC 24 |
| Peak memory | 597828 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=205453491 -assert nopostproc +UVM_TESTNAME =xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.xbar_error_random.205453491 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/18.xbar_error_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/18.xbar_random.1122950011 |
| Short name | T493 |
| Test name | |
| Test status | |
| Simulation time | 2002972645 ps |
| CPU time | 58.51 seconds |
| Started | Aug 24 05:02:13 AM UTC 24 |
| Finished | Aug 24 05:03:13 AM UTC 24 |
| Peak memory | 597828 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1122950011 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.xbar_random.1122950011 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/18.xbar_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/18.xbar_random_large_delays.747823316 |
| Short name | T1560 |
| Test name | |
| Test status | |
| Simulation time | 80253412352 ps |
| CPU time | 664.4 seconds |
| Started | Aug 24 05:02:46 AM UTC 24 |
| Finished | Aug 24 05:13:58 AM UTC 24 |
| Peak memory | 597884 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max _device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=747823316 -assert nopostproc +UV M_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.xbar_random_large_delays.747823316 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/18.xbar_random_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/18.xbar_random_slow_rsp.1463304617 |
| Short name | T1543 |
| Test name | |
| Test status | |
| Simulation time | 37891495612 ps |
| CPU time | 449.07 seconds |
| Started | Aug 24 05:02:52 AM UTC 24 |
| Finished | Aug 24 05:10:26 AM UTC 24 |
| Peak memory | 597824 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1463304617 -assert nopostproc +UVM_T ESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.xbar_random_slow_rsp.1463304617 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/18.xbar_random_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/18.xbar_random_zero_delays.678324601 |
| Short name | T1511 |
| Test name | |
| Test status | |
| Simulation time | 341339771 ps |
| CPU time | 21.73 seconds |
| Started | Aug 24 05:02:14 AM UTC 24 |
| Finished | Aug 24 05:02:37 AM UTC 24 |
| Peak memory | 597844 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=678324601 -assert nopostpro c +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.xbar_random_zero_delays.678324601 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/18.xbar_random_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/18.xbar_same_source.3834560244 |
| Short name | T1516 |
| Test name | |
| Test status | |
| Simulation time | 1207434025 ps |
| CPU time | 25.18 seconds |
| Started | Aug 24 05:03:22 AM UTC 24 |
| Finished | Aug 24 05:03:48 AM UTC 24 |
| Peak memory | 597688 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3834560244 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.xbar_same_source.3834560244 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/18.xbar_same_source/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/18.xbar_smoke.284354448 |
| Short name | T1508 |
| Test name | |
| Test status | |
| Simulation time | 43866966 ps |
| CPU time | 5.21 seconds |
| Started | Aug 24 05:01:42 AM UTC 24 |
| Finished | Aug 24 05:01:48 AM UTC 24 |
| Peak memory | 595628 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=284354448 -assert nopostproc +UVM_TESTNAME =xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08 _22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.xbar_smoke.284354448 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/18.xbar_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/18.xbar_smoke_large_delays.3484896268 |
| Short name | T1513 |
| Test name | |
| Test status | |
| Simulation time | 7317381180 ps |
| CPU time | 59.65 seconds |
| Started | Aug 24 05:02:02 AM UTC 24 |
| Finished | Aug 24 05:03:03 AM UTC 24 |
| Peak memory | 595764 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max _device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3484896268 -assert nopostproc +U VM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.xbar_smoke_large_delays.3484896268 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/18.xbar_smoke_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/18.xbar_smoke_slow_rsp.3747329714 |
| Short name | T1512 |
| Test name | |
| Test status | |
| Simulation time | 4315085176 ps |
| CPU time | 51.46 seconds |
| Started | Aug 24 05:02:03 AM UTC 24 |
| Finished | Aug 24 05:02:56 AM UTC 24 |
| Peak memory | 595908 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3747329714 -assert nopostproc +UVM_T ESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.xbar_smoke_slow_rsp.3747329714 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/18.xbar_smoke_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/18.xbar_smoke_zero_delays.1058167629 |
| Short name | T1510 |
| Test name | |
| Test status | |
| Simulation time | 45443777 ps |
| CPU time | 5.41 seconds |
| Started | Aug 24 05:01:52 AM UTC 24 |
| Finished | Aug 24 05:01:59 AM UTC 24 |
| Peak memory | 595848 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1058167629 -assert nopostpr oc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.xbar_smoke_zero_delays.1058167629 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/18.xbar_smoke_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/18.xbar_stress_all.1676657995 |
| Short name | T1528 |
| Test name | |
| Test status | |
| Simulation time | 6421929644 ps |
| CPU time | 177.02 seconds |
| Started | Aug 24 05:03:50 AM UTC 24 |
| Finished | Aug 24 05:06:50 AM UTC 24 |
| Peak memory | 597828 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1676657995 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.xbar_stress_all.1676657995 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/18.xbar_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/18.xbar_stress_all_with_error.1554264191 |
| Short name | T808 |
| Test name | |
| Test status | |
| Simulation time | 2862595778 ps |
| CPU time | 70.83 seconds |
| Started | Aug 24 05:04:17 AM UTC 24 |
| Finished | Aug 24 05:05:30 AM UTC 24 |
| Peak memory | 597760 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1554264191 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.xbar_stress_all_with_error.1554264191 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/18.xbar_stress_all_with_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/18.xbar_stress_all_with_reset_error.1022417242 |
| Short name | T866 |
| Test name | |
| Test status | |
| Simulation time | 3215659672 ps |
| CPU time | 265.27 seconds |
| Started | Aug 24 05:04:24 AM UTC 24 |
| Finished | Aug 24 05:08:53 AM UTC 24 |
| Peak memory | 597756 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1022417242 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.xbar_stress_all_with_reset_error.1022417242 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/18.xbar_stress_all_with_reset_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/18.xbar_unmapped_addr.2724148665 |
| Short name | T1517 |
| Test name | |
| Test status | |
| Simulation time | 733870482 ps |
| CPU time | 24.67 seconds |
| Started | Aug 24 05:03:37 AM UTC 24 |
| Finished | Aug 24 05:04:03 AM UTC 24 |
| Peak memory | 597696 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2724148665 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.xbar_unmapped_addr.2724148665 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/18.xbar_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/19.chip_csr_mem_rw_with_rand_reset.3555287538 |
| Short name | T1578 |
| Test name | |
| Test status | |
| Simulation time | 8310723498 ps |
| CPU time | 581.85 seconds |
| Started | Aug 24 05:07:45 AM UTC 24 |
| Finished | Aug 24 05:17:33 AM UTC 24 |
| Peak memory | 672824 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000 000000 +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/too ls/sim.tcl +ntb_random_seed=3555287538 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/nul l -cm_name 19.chip_csr_mem_rw_with_rand_reset.3555287538 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/19.chip_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/19.chip_csr_rw.3818727401 |
| Short name | T1567 |
| Test name | |
| Test status | |
| Simulation time | 5260381110 ps |
| CPU time | 441.71 seconds |
| Started | Aug 24 05:07:40 AM UTC 24 |
| Finished | Aug 24 05:15:07 AM UTC 24 |
| Peak memory | 619456 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +stub_cpu=1 +cdc_instrumentation_ena bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3818727401 -assert nopost proc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os _regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.chip_csr_rw.3818727401 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/19.chip_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/19.chip_same_csr_outstanding.3589254176 |
| Short name | T1804 |
| Test name | |
| Test status | |
| Simulation time | 29476587171 ps |
| CPU time | 2688.11 seconds |
| Started | Aug 24 05:04:49 AM UTC 24 |
| Finished | Aug 24 05:50:05 AM UTC 24 |
| Peak memory | 614112 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +test_timeout_ns=120_000_000 +run_same_csr_outstanding +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim .tcl +ntb_random_seed=3589254176 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_ name 19.chip_same_csr_outstanding.3589254176 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/19.chip_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/19.chip_tl_errors.1160300669 |
| Short name | T581 |
| Test name | |
| Test status | |
| Simulation time | 3451274460 ps |
| CPU time | 154.63 seconds |
| Started | Aug 24 05:05:33 AM UTC 24 |
| Finished | Aug 24 05:08:11 AM UTC 24 |
| Peak memory | 623476 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enable d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1160300669 -assert nopostpro c +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.chip_tl_errors.1160300669 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/19.chip_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/19.xbar_access_same_device_slow_rsp.2901292923 |
| Short name | T829 |
| Test name | |
| Test status | |
| Simulation time | 56676472276 ps |
| CPU time | 687.54 seconds |
| Started | Aug 24 05:06:46 AM UTC 24 |
| Finished | Aug 24 05:18:21 AM UTC 24 |
| Peak memory | 597888 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2901292923 -assert nopostproc +UVM_T ESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.xbar_access_same_device_slow_rsp.2901292923 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/19.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/19.xbar_error_and_unmapped_addr.2102803570 |
| Short name | T1532 |
| Test name | |
| Test status | |
| Simulation time | 1193959343 ps |
| CPU time | 36.91 seconds |
| Started | Aug 24 05:06:52 AM UTC 24 |
| Finished | Aug 24 05:07:31 AM UTC 24 |
| Peak memory | 597696 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2102803570 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.xbar_error_and_unmapped_addr.2102803570 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/19.xbar_error_and_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/19.xbar_error_random.3347719540 |
| Short name | T1533 |
| Test name | |
| Test status | |
| Simulation time | 2240852285 ps |
| CPU time | 62.09 seconds |
| Started | Aug 24 05:06:51 AM UTC 24 |
| Finished | Aug 24 05:07:55 AM UTC 24 |
| Peak memory | 597756 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3347719540 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.xbar_error_random.3347719540 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/19.xbar_error_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/19.xbar_random.2555273060 |
| Short name | T1526 |
| Test name | |
| Test status | |
| Simulation time | 1223335091 ps |
| CPU time | 34.85 seconds |
| Started | Aug 24 05:06:02 AM UTC 24 |
| Finished | Aug 24 05:06:38 AM UTC 24 |
| Peak memory | 597752 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2555273060 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.xbar_random.2555273060 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/19.xbar_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/19.xbar_random_large_delays.1960579426 |
| Short name | T1558 |
| Test name | |
| Test status | |
| Simulation time | 54488576922 ps |
| CPU time | 431.03 seconds |
| Started | Aug 24 05:06:22 AM UTC 24 |
| Finished | Aug 24 05:13:37 AM UTC 24 |
| Peak memory | 597964 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max _device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1960579426 -assert nopostproc +U VM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.xbar_random_large_delays.1960579426 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/19.xbar_random_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/19.xbar_random_slow_rsp.952983720 |
| Short name | T1542 |
| Test name | |
| Test status | |
| Simulation time | 17837396900 ps |
| CPU time | 207.03 seconds |
| Started | Aug 24 05:06:37 AM UTC 24 |
| Finished | Aug 24 05:10:07 AM UTC 24 |
| Peak memory | 598200 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=952983720 -assert nopostproc +UVM_TE STNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.xbar_random_slow_rsp.952983720 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/19.xbar_random_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/19.xbar_random_zero_delays.3735139802 |
| Short name | T531 |
| Test name | |
| Test status | |
| Simulation time | 423787763 ps |
| CPU time | 27.12 seconds |
| Started | Aug 24 05:06:04 AM UTC 24 |
| Finished | Aug 24 05:06:32 AM UTC 24 |
| Peak memory | 597700 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3735139802 -assert nopostpr oc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.xbar_random_zero_delays.3735139802 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/19.xbar_random_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/19.xbar_same_source.23594150 |
| Short name | T1530 |
| Test name | |
| Test status | |
| Simulation time | 132412649 ps |
| CPU time | 9.79 seconds |
| Started | Aug 24 05:06:49 AM UTC 24 |
| Finished | Aug 24 05:07:00 AM UTC 24 |
| Peak memory | 597948 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=23594150 -assert nopostproc +UVM_TESTNAME= xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.xbar_same_source.23594150 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/19.xbar_same_source/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/19.xbar_smoke.2268906173 |
| Short name | T1523 |
| Test name | |
| Test status | |
| Simulation time | 41865211 ps |
| CPU time | 4.99 seconds |
| Started | Aug 24 05:05:38 AM UTC 24 |
| Finished | Aug 24 05:05:44 AM UTC 24 |
| Peak memory | 595848 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2268906173 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 8_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.xbar_smoke.2268906173 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/19.xbar_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/19.xbar_smoke_large_delays.2233163277 |
| Short name | T1525 |
| Test name | |
| Test status | |
| Simulation time | 6589061291 ps |
| CPU time | 52.39 seconds |
| Started | Aug 24 05:05:44 AM UTC 24 |
| Finished | Aug 24 05:06:37 AM UTC 24 |
| Peak memory | 596012 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max _device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2233163277 -assert nopostproc +U VM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.xbar_smoke_large_delays.2233163277 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/19.xbar_smoke_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/19.xbar_smoke_slow_rsp.1739260605 |
| Short name | T1527 |
| Test name | |
| Test status | |
| Simulation time | 4053670705 ps |
| CPU time | 47.63 seconds |
| Started | Aug 24 05:05:59 AM UTC 24 |
| Finished | Aug 24 05:06:48 AM UTC 24 |
| Peak memory | 595840 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1739260605 -assert nopostproc +UVM_T ESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.xbar_smoke_slow_rsp.1739260605 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/19.xbar_smoke_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/19.xbar_smoke_zero_delays.1249698651 |
| Short name | T1524 |
| Test name | |
| Test status | |
| Simulation time | 49697587 ps |
| CPU time | 5.26 seconds |
| Started | Aug 24 05:05:41 AM UTC 24 |
| Finished | Aug 24 05:05:48 AM UTC 24 |
| Peak memory | 595632 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1249698651 -assert nopostpr oc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.xbar_smoke_zero_delays.1249698651 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/19.xbar_smoke_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/19.xbar_stress_all.3332422033 |
| Short name | T541 |
| Test name | |
| Test status | |
| Simulation time | 5294588299 ps |
| CPU time | 131.07 seconds |
| Started | Aug 24 05:07:01 AM UTC 24 |
| Finished | Aug 24 05:09:15 AM UTC 24 |
| Peak memory | 597824 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3332422033 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.xbar_stress_all.3332422033 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/19.xbar_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/19.xbar_stress_all_with_error.2782362750 |
| Short name | T825 |
| Test name | |
| Test status | |
| Simulation time | 10320511492 ps |
| CPU time | 255.37 seconds |
| Started | Aug 24 05:07:14 AM UTC 24 |
| Finished | Aug 24 05:11:33 AM UTC 24 |
| Peak memory | 597828 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2782362750 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.xbar_stress_all_with_error.2782362750 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/19.xbar_stress_all_with_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/19.xbar_stress_all_with_rand_reset.2180173099 |
| Short name | T859 |
| Test name | |
| Test status | |
| Simulation time | 5129074989 ps |
| CPU time | 196.34 seconds |
| Started | Aug 24 05:07:04 AM UTC 24 |
| Finished | Aug 24 05:10:24 AM UTC 24 |
| Peak memory | 598036 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2180173099 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.xbar_stress_all_with_rand_reset.2180173099 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/19.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/19.xbar_stress_all_with_reset_error.2016195348 |
| Short name | T1531 |
| Test name | |
| Test status | |
| Simulation time | 42138846 ps |
| CPU time | 9.78 seconds |
| Started | Aug 24 05:07:15 AM UTC 24 |
| Finished | Aug 24 05:07:25 AM UTC 24 |
| Peak memory | 595636 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2016195348 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.xbar_stress_all_with_reset_error.2016195348 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/19.xbar_stress_all_with_reset_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/19.xbar_unmapped_addr.3250681459 |
| Short name | T1529 |
| Test name | |
| Test status | |
| Simulation time | 157348810 ps |
| CPU time | 7.68 seconds |
| Started | Aug 24 05:06:51 AM UTC 24 |
| Finished | Aug 24 05:07:00 AM UTC 24 |
| Peak memory | 595644 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3250681459 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.xbar_unmapped_addr.3250681459 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/19.xbar_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/2.chip_csr_aliasing.4019734650 |
| Short name | T1817 |
| Test name | |
| Test status | |
| Simulation time | 58247954985 ps |
| CPU time | 6954.78 seconds |
| Started | Aug 24 03:54:19 AM UTC 24 |
| Finished | Aug 24 05:51:21 AM UTC 24 |
| Peak memory | 657116 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +test_timeout_ns=120_000_000 +csr_aliasing +en_scb=0 + stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=4019734650 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.chip_ csr_aliasing.4019734650 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/2.chip_csr_aliasing/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/2.chip_csr_bit_bash.782446949 |
| Short name | T1400 |
| Test name | |
| Test status | |
| Simulation time | 31096152407 ps |
| CPU time | 2085.03 seconds |
| Started | Aug 24 03:54:14 AM UTC 24 |
| Finished | Aug 24 04:29:21 AM UTC 24 |
| Peak memory | 619284 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +test_timeout_ns=120_000_000 +num_test_csrs=200 +csr_b it_bash +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/to ols/sim.tcl +ntb_random_seed=782446949 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/nul l -cm_name 2.chip_csr_bit_bash.782446949 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/2.chip_csr_bit_bash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/2.chip_csr_hw_reset.2829690618 |
| Short name | T177 |
| Test name | |
| Test status | |
| Simulation time | 4028545356 ps |
| CPU time | 172.74 seconds |
| Started | Aug 24 03:59:14 AM UTC 24 |
| Finished | Aug 24 04:02:09 AM UTC 24 |
| Peak memory | 682712 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +stub_cpu=1 +cdc_instrumentati on_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2829690618 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra tch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.chip_csr_hw_reset.2829690618 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/2.chip_csr_hw_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/2.chip_csr_mem_rw_with_rand_reset.433385764 |
| Short name | T184 |
| Test name | |
| Test status | |
| Simulation time | 6794398072 ps |
| CPU time | 320.48 seconds |
| Started | Aug 24 03:59:35 AM UTC 24 |
| Finished | Aug 24 04:04:59 AM UTC 24 |
| Peak memory | 658504 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000 000000 +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/too ls/sim.tcl +ntb_random_seed=433385764 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.chip_csr_mem_rw_with_rand_reset.433385764 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/2.chip_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/2.chip_prim_tl_access.1642817120 |
| Short name | T1350 |
| Test name | |
| Test status | |
| Simulation time | 10265044625 ps |
| CPU time | 300.08 seconds |
| Started | Aug 24 03:54:29 AM UTC 24 |
| Finished | Aug 24 03:59:33 AM UTC 24 |
| Peak memory | 609176 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +en_scb=0 +en_scb_tl_err_chk=0 +stub_cpu=1 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1642817120 - assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_prim_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works paces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.chip_prim_tl_access.1642817120 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/2.chip_prim_tl_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/2.chip_rv_dm_lc_disabled.2480857030 |
| Short name | T1351 |
| Test name | |
| Test status | |
| Simulation time | 12606284081 ps |
| CPU time | 275.88 seconds |
| Started | Aug 24 03:55:15 AM UTC 24 |
| Finished | Aug 24 03:59:55 AM UTC 24 |
| Peak memory | 608716 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +en_scb=0 +en_scb_tl_err_chk=0 +use_jtag_dmi=1 +stub_c pu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s eed=2480857030 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_rv_dm_lc_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as sert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2. chip_rv_dm_lc_disabled.2480857030 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/2.chip_rv_dm_lc_disabled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/2.chip_tl_errors.1692974573 |
| Short name | T554 |
| Test name | |
| Test status | |
| Simulation time | 3839974324 ps |
| CPU time | 157.75 seconds |
| Started | Aug 24 03:54:26 AM UTC 24 |
| Finished | Aug 24 03:57:06 AM UTC 24 |
| Peak memory | 623452 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enable d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1692974573 -assert nopostpro c +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.chip_tl_errors.1692974573 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/2.chip_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/2.xbar_access_same_device.2961393467 |
| Short name | T489 |
| Test name | |
| Test status | |
| Simulation time | 507713702 ps |
| CPU time | 29.2 seconds |
| Started | Aug 24 03:57:34 AM UTC 24 |
| Finished | Aug 24 03:58:05 AM UTC 24 |
| Peak memory | 597768 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2961393467 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.xbar_access_same_device.2961393467 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/2.xbar_access_same_device/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/2.xbar_access_same_device_slow_rsp.109681203 |
| Short name | T817 |
| Test name | |
| Test status | |
| Simulation time | 45423980804 ps |
| CPU time | 561.32 seconds |
| Started | Aug 24 03:57:35 AM UTC 24 |
| Finished | Aug 24 04:07:03 AM UTC 24 |
| Peak memory | 597812 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=109681203 -assert nopostproc +UVM_TE STNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os _regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.xbar_access_same_device_slow_rsp.109681203 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/2.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/2.xbar_error_and_unmapped_addr.928200787 |
| Short name | T636 |
| Test name | |
| Test status | |
| Simulation time | 1252610463 ps |
| CPU time | 36.36 seconds |
| Started | Aug 24 03:58:07 AM UTC 24 |
| Finished | Aug 24 03:58:45 AM UTC 24 |
| Peak memory | 597696 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=928200787 -assert nopostproc +UVM_TESTNAME =xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.xbar_error_and_unmapped_addr.928200787 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/2.xbar_error_and_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/2.xbar_error_random.911018195 |
| Short name | T1349 |
| Test name | |
| Test status | |
| Simulation time | 469664016 ps |
| CPU time | 13.48 seconds |
| Started | Aug 24 03:57:38 AM UTC 24 |
| Finished | Aug 24 03:57:53 AM UTC 24 |
| Peak memory | 597696 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=911018195 -assert nopostproc +UVM_TESTNAME =xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.xbar_error_random.911018195 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/2.xbar_error_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/2.xbar_random.1549331925 |
| Short name | T460 |
| Test name | |
| Test status | |
| Simulation time | 1921542459 ps |
| CPU time | 50.85 seconds |
| Started | Aug 24 03:56:29 AM UTC 24 |
| Finished | Aug 24 03:57:21 AM UTC 24 |
| Peak memory | 597752 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1549331925 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.xbar_random.1549331925 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/2.xbar_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/2.xbar_random_large_delays.369893227 |
| Short name | T580 |
| Test name | |
| Test status | |
| Simulation time | 73351851064 ps |
| CPU time | 615.6 seconds |
| Started | Aug 24 03:57:07 AM UTC 24 |
| Finished | Aug 24 04:07:29 AM UTC 24 |
| Peak memory | 597820 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max _device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=369893227 -assert nopostproc +UV M_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.xbar_random_large_delays.369893227 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/2.xbar_random_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/2.xbar_random_slow_rsp.1531235416 |
| Short name | T599 |
| Test name | |
| Test status | |
| Simulation time | 54095869134 ps |
| CPU time | 630.05 seconds |
| Started | Aug 24 03:57:20 AM UTC 24 |
| Finished | Aug 24 04:07:57 AM UTC 24 |
| Peak memory | 597824 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1531235416 -assert nopostproc +UVM_T ESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.xbar_random_slow_rsp.1531235416 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/2.xbar_random_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/2.xbar_random_zero_delays.944505671 |
| Short name | T577 |
| Test name | |
| Test status | |
| Simulation time | 425516185 ps |
| CPU time | 29.89 seconds |
| Started | Aug 24 03:56:50 AM UTC 24 |
| Finished | Aug 24 03:57:21 AM UTC 24 |
| Peak memory | 597700 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=944505671 -assert nopostpro c +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.xbar_random_zero_delays.944505671 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/2.xbar_random_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/2.xbar_same_source.4114983378 |
| Short name | T567 |
| Test name | |
| Test status | |
| Simulation time | 1881719204 ps |
| CPU time | 43.52 seconds |
| Started | Aug 24 03:57:35 AM UTC 24 |
| Finished | Aug 24 03:58:20 AM UTC 24 |
| Peak memory | 597832 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4114983378 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.xbar_same_source.4114983378 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/2.xbar_same_source/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/2.xbar_smoke.2010822239 |
| Short name | T679 |
| Test name | |
| Test status | |
| Simulation time | 41002113 ps |
| CPU time | 5.13 seconds |
| Started | Aug 24 03:55:47 AM UTC 24 |
| Finished | Aug 24 03:55:54 AM UTC 24 |
| Peak memory | 595636 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2010822239 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 8_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.xbar_smoke.2010822239 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/2.xbar_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/2.xbar_smoke_large_delays.449387542 |
| Short name | T869 |
| Test name | |
| Test status | |
| Simulation time | 7891643028 ps |
| CPU time | 63.39 seconds |
| Started | Aug 24 03:56:19 AM UTC 24 |
| Finished | Aug 24 03:57:24 AM UTC 24 |
| Peak memory | 595760 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max _device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=449387542 -assert nopostproc +UV M_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.xbar_smoke_large_delays.449387542 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/2.xbar_smoke_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/2.xbar_smoke_slow_rsp.4182193501 |
| Short name | T578 |
| Test name | |
| Test status | |
| Simulation time | 6206846987 ps |
| CPU time | 74.22 seconds |
| Started | Aug 24 03:56:23 AM UTC 24 |
| Finished | Aug 24 03:57:38 AM UTC 24 |
| Peak memory | 595772 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4182193501 -assert nopostproc +UVM_T ESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.xbar_smoke_slow_rsp.4182193501 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/2.xbar_smoke_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/2.xbar_smoke_zero_delays.2037126847 |
| Short name | T1348 |
| Test name | |
| Test status | |
| Simulation time | 45988376 ps |
| CPU time | 5.27 seconds |
| Started | Aug 24 03:56:08 AM UTC 24 |
| Finished | Aug 24 03:56:15 AM UTC 24 |
| Peak memory | 595636 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2037126847 -assert nopostpr oc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.xbar_smoke_zero_delays.2037126847 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/2.xbar_smoke_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/2.xbar_stress_all.728254830 |
| Short name | T525 |
| Test name | |
| Test status | |
| Simulation time | 12815809573 ps |
| CPU time | 393.66 seconds |
| Started | Aug 24 03:58:19 AM UTC 24 |
| Finished | Aug 24 04:04:58 AM UTC 24 |
| Peak memory | 597824 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=728254830 -assert nopostproc +UVM_TESTNAME =xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.xbar_stress_all.728254830 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/2.xbar_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/2.xbar_stress_all_with_error.714636208 |
| Short name | T640 |
| Test name | |
| Test status | |
| Simulation time | 1907527447 ps |
| CPU time | 42.23 seconds |
| Started | Aug 24 03:58:47 AM UTC 24 |
| Finished | Aug 24 03:59:31 AM UTC 24 |
| Peak memory | 597888 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=714636208 -assert nopostproc +UVM_TESTNAME =xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.xbar_stress_all_with_error.714636208 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/2.xbar_stress_all_with_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/2.xbar_stress_all_with_reset_error.4031862757 |
| Short name | T823 |
| Test name | |
| Test status | |
| Simulation time | 581794807 ps |
| CPU time | 175.39 seconds |
| Started | Aug 24 03:59:00 AM UTC 24 |
| Finished | Aug 24 04:01:58 AM UTC 24 |
| Peak memory | 597696 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4031862757 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.xbar_stress_all_with_reset_error.4031862757 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/2.xbar_stress_all_with_reset_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/2.xbar_unmapped_addr.2251944507 |
| Short name | T619 |
| Test name | |
| Test status | |
| Simulation time | 1410290254 ps |
| CPU time | 40.06 seconds |
| Started | Aug 24 03:57:52 AM UTC 24 |
| Finished | Aug 24 03:58:34 AM UTC 24 |
| Peak memory | 597760 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2251944507 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.xbar_unmapped_addr.2251944507 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/2.xbar_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/20.xbar_access_same_device.3086947281 |
| Short name | T1544 |
| Test name | |
| Test status | |
| Simulation time | 1038807949 ps |
| CPU time | 57.56 seconds |
| Started | Aug 24 05:09:33 AM UTC 24 |
| Finished | Aug 24 05:10:33 AM UTC 24 |
| Peak memory | 597988 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3086947281 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.xbar_access_same_device.3086947281 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/20.xbar_access_same_device/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/20.xbar_access_same_device_slow_rsp.3590807141 |
| Short name | T793 |
| Test name | |
| Test status | |
| Simulation time | 100707171825 ps |
| CPU time | 1145.98 seconds |
| Started | Aug 24 05:09:47 AM UTC 24 |
| Finished | Aug 24 05:29:04 AM UTC 24 |
| Peak memory | 598756 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3590807141 -assert nopostproc +UVM_T ESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.xbar_access_same_device_slow_rsp.3590807141 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/20.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/20.xbar_error_and_unmapped_addr.2965221945 |
| Short name | T1548 |
| Test name | |
| Test status | |
| Simulation time | 739278346 ps |
| CPU time | 22.81 seconds |
| Started | Aug 24 05:10:38 AM UTC 24 |
| Finished | Aug 24 05:11:02 AM UTC 24 |
| Peak memory | 597700 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2965221945 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.xbar_error_and_unmapped_addr.2965221945 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/20.xbar_error_and_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/20.xbar_error_random.3514394019 |
| Short name | T1545 |
| Test name | |
| Test status | |
| Simulation time | 581978890 ps |
| CPU time | 34.73 seconds |
| Started | Aug 24 05:09:57 AM UTC 24 |
| Finished | Aug 24 05:10:34 AM UTC 24 |
| Peak memory | 597692 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3514394019 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.xbar_error_random.3514394019 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/20.xbar_error_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/20.xbar_random.1456898235 |
| Short name | T1537 |
| Test name | |
| Test status | |
| Simulation time | 61750657 ps |
| CPU time | 6.95 seconds |
| Started | Aug 24 05:08:53 AM UTC 24 |
| Finished | Aug 24 05:09:01 AM UTC 24 |
| Peak memory | 597892 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1456898235 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.xbar_random.1456898235 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/20.xbar_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/20.xbar_random_large_delays.679517816 |
| Short name | T1609 |
| Test name | |
| Test status | |
| Simulation time | 92991279299 ps |
| CPU time | 758.41 seconds |
| Started | Aug 24 05:09:15 AM UTC 24 |
| Finished | Aug 24 05:22:02 AM UTC 24 |
| Peak memory | 597964 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max _device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=679517816 -assert nopostproc +UV M_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.xbar_random_large_delays.679517816 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/20.xbar_random_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/20.xbar_random_slow_rsp.137289335 |
| Short name | T1564 |
| Test name | |
| Test status | |
| Simulation time | 26759555359 ps |
| CPU time | 310.99 seconds |
| Started | Aug 24 05:09:29 AM UTC 24 |
| Finished | Aug 24 05:14:44 AM UTC 24 |
| Peak memory | 597824 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=137289335 -assert nopostproc +UVM_TE STNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.xbar_random_slow_rsp.137289335 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/20.xbar_random_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/20.xbar_random_zero_delays.2448122045 |
| Short name | T1539 |
| Test name | |
| Test status | |
| Simulation time | 364918418 ps |
| CPU time | 24.11 seconds |
| Started | Aug 24 05:09:07 AM UTC 24 |
| Finished | Aug 24 05:09:33 AM UTC 24 |
| Peak memory | 597704 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2448122045 -assert nopostpr oc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.xbar_random_zero_delays.2448122045 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/20.xbar_random_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/20.xbar_same_source.3501627753 |
| Short name | T1547 |
| Test name | |
| Test status | |
| Simulation time | 2288016826 ps |
| CPU time | 51.22 seconds |
| Started | Aug 24 05:09:55 AM UTC 24 |
| Finished | Aug 24 05:10:48 AM UTC 24 |
| Peak memory | 597756 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3501627753 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.xbar_same_source.3501627753 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/20.xbar_same_source/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/20.xbar_smoke.2136024859 |
| Short name | T1534 |
| Test name | |
| Test status | |
| Simulation time | 151486412 ps |
| CPU time | 6.26 seconds |
| Started | Aug 24 05:08:09 AM UTC 24 |
| Finished | Aug 24 05:08:16 AM UTC 24 |
| Peak memory | 595632 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2136024859 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 8_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.xbar_smoke.2136024859 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/20.xbar_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/20.xbar_smoke_large_delays.1937818208 |
| Short name | T1541 |
| Test name | |
| Test status | |
| Simulation time | 8784238735 ps |
| CPU time | 70.46 seconds |
| Started | Aug 24 05:08:31 AM UTC 24 |
| Finished | Aug 24 05:09:43 AM UTC 24 |
| Peak memory | 595768 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max _device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1937818208 -assert nopostproc +U VM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.xbar_smoke_large_delays.1937818208 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/20.xbar_smoke_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/20.xbar_smoke_slow_rsp.2002541874 |
| Short name | T1540 |
| Test name | |
| Test status | |
| Simulation time | 4514167800 ps |
| CPU time | 53.71 seconds |
| Started | Aug 24 05:08:46 AM UTC 24 |
| Finished | Aug 24 05:09:41 AM UTC 24 |
| Peak memory | 595768 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2002541874 -assert nopostproc +UVM_T ESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.xbar_smoke_slow_rsp.2002541874 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/20.xbar_smoke_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/20.xbar_smoke_zero_delays.3266769917 |
| Short name | T1535 |
| Test name | |
| Test status | |
| Simulation time | 49065741 ps |
| CPU time | 5.67 seconds |
| Started | Aug 24 05:08:25 AM UTC 24 |
| Finished | Aug 24 05:08:32 AM UTC 24 |
| Peak memory | 595632 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3266769917 -assert nopostpr oc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.xbar_smoke_zero_delays.3266769917 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/20.xbar_smoke_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/20.xbar_stress_all_with_error.1241323639 |
| Short name | T827 |
| Test name | |
| Test status | |
| Simulation time | 9930756260 ps |
| CPU time | 238.99 seconds |
| Started | Aug 24 05:10:48 AM UTC 24 |
| Finished | Aug 24 05:14:50 AM UTC 24 |
| Peak memory | 598168 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1241323639 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.xbar_stress_all_with_error.1241323639 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/20.xbar_stress_all_with_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/20.xbar_stress_all_with_reset_error.1770686305 |
| Short name | T1562 |
| Test name | |
| Test status | |
| Simulation time | 3129515693 ps |
| CPU time | 215.4 seconds |
| Started | Aug 24 05:10:54 AM UTC 24 |
| Finished | Aug 24 05:14:32 AM UTC 24 |
| Peak memory | 597764 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1770686305 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.xbar_stress_all_with_reset_error.1770686305 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/20.xbar_stress_all_with_reset_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/20.xbar_unmapped_addr.1142044501 |
| Short name | T1546 |
| Test name | |
| Test status | |
| Simulation time | 458750811 ps |
| CPU time | 16.48 seconds |
| Started | Aug 24 05:10:22 AM UTC 24 |
| Finished | Aug 24 05:10:39 AM UTC 24 |
| Peak memory | 597752 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1142044501 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.xbar_unmapped_addr.1142044501 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/20.xbar_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/21.chip_tl_errors.501201175 |
| Short name | T648 |
| Test name | |
| Test status | |
| Simulation time | 2947092660 ps |
| CPU time | 133.52 seconds |
| Started | Aug 24 05:11:03 AM UTC 24 |
| Finished | Aug 24 05:13:19 AM UTC 24 |
| Peak memory | 623388 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enable d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=501201175 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.chip_tl_errors.501201175 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/21.chip_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/21.xbar_access_same_device.1799391809 |
| Short name | T831 |
| Test name | |
| Test status | |
| Simulation time | 2984634328 ps |
| CPU time | 91.39 seconds |
| Started | Aug 24 05:13:09 AM UTC 24 |
| Finished | Aug 24 05:14:42 AM UTC 24 |
| Peak memory | 597896 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1799391809 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.xbar_access_same_device.1799391809 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/21.xbar_access_same_device/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/21.xbar_access_same_device_slow_rsp.316425591 |
| Short name | T794 |
| Test name | |
| Test status | |
| Simulation time | 125585707075 ps |
| CPU time | 1472.82 seconds |
| Started | Aug 24 05:13:10 AM UTC 24 |
| Finished | Aug 24 05:37:58 AM UTC 24 |
| Peak memory | 598788 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=316425591 -assert nopostproc +UVM_TE STNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os _regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.xbar_access_same_device_slow_rsp.316425591 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/21.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/21.xbar_error_and_unmapped_addr.4267208163 |
| Short name | T1563 |
| Test name | |
| Test status | |
| Simulation time | 1484352099 ps |
| CPU time | 43.73 seconds |
| Started | Aug 24 05:13:52 AM UTC 24 |
| Finished | Aug 24 05:14:37 AM UTC 24 |
| Peak memory | 597844 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4267208163 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.xbar_error_and_unmapped_addr.4267208163 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/21.xbar_error_and_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/21.xbar_error_random.3591062905 |
| Short name | T1559 |
| Test name | |
| Test status | |
| Simulation time | 173860120 ps |
| CPU time | 13.14 seconds |
| Started | Aug 24 05:13:34 AM UTC 24 |
| Finished | Aug 24 05:13:48 AM UTC 24 |
| Peak memory | 597692 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3591062905 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.xbar_error_random.3591062905 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/21.xbar_error_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/21.xbar_random.2791534002 |
| Short name | T1552 |
| Test name | |
| Test status | |
| Simulation time | 1235111084 ps |
| CPU time | 32.66 seconds |
| Started | Aug 24 05:11:59 AM UTC 24 |
| Finished | Aug 24 05:12:33 AM UTC 24 |
| Peak memory | 597692 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2791534002 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.xbar_random.2791534002 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/21.xbar_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/21.xbar_random_large_delays.3191714573 |
| Short name | T1600 |
| Test name | |
| Test status | |
| Simulation time | 59157702447 ps |
| CPU time | 495.07 seconds |
| Started | Aug 24 05:12:48 AM UTC 24 |
| Finished | Aug 24 05:21:08 AM UTC 24 |
| Peak memory | 597960 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max _device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3191714573 -assert nopostproc +U VM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.xbar_random_large_delays.3191714573 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/21.xbar_random_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/21.xbar_random_slow_rsp.781737466 |
| Short name | T1585 |
| Test name | |
| Test status | |
| Simulation time | 27823394918 ps |
| CPU time | 339.22 seconds |
| Started | Aug 24 05:12:55 AM UTC 24 |
| Finished | Aug 24 05:18:39 AM UTC 24 |
| Peak memory | 598192 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=781737466 -assert nopostproc +UVM_TE STNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.xbar_random_slow_rsp.781737466 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/21.xbar_random_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/21.xbar_random_zero_delays.1833047827 |
| Short name | T1553 |
| Test name | |
| Test status | |
| Simulation time | 166652108 ps |
| CPU time | 11.74 seconds |
| Started | Aug 24 05:12:29 AM UTC 24 |
| Finished | Aug 24 05:12:41 AM UTC 24 |
| Peak memory | 597760 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1833047827 -assert nopostpr oc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.xbar_random_zero_delays.1833047827 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/21.xbar_random_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/21.xbar_same_source.3868064917 |
| Short name | T1557 |
| Test name | |
| Test status | |
| Simulation time | 71383655 ps |
| CPU time | 6.37 seconds |
| Started | Aug 24 05:13:26 AM UTC 24 |
| Finished | Aug 24 05:13:33 AM UTC 24 |
| Peak memory | 597752 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3868064917 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.xbar_same_source.3868064917 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/21.xbar_same_source/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/21.xbar_smoke.2715726794 |
| Short name | T1549 |
| Test name | |
| Test status | |
| Simulation time | 214382821 ps |
| CPU time | 7.37 seconds |
| Started | Aug 24 05:11:16 AM UTC 24 |
| Finished | Aug 24 05:11:24 AM UTC 24 |
| Peak memory | 595848 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2715726794 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 8_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.xbar_smoke.2715726794 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/21.xbar_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/21.xbar_smoke_large_delays.1896901993 |
| Short name | T1555 |
| Test name | |
| Test status | |
| Simulation time | 8059400761 ps |
| CPU time | 65.35 seconds |
| Started | Aug 24 05:11:48 AM UTC 24 |
| Finished | Aug 24 05:12:55 AM UTC 24 |
| Peak memory | 595764 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max _device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1896901993 -assert nopostproc +U VM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.xbar_smoke_large_delays.1896901993 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/21.xbar_smoke_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/21.xbar_smoke_slow_rsp.517068974 |
| Short name | T1554 |
| Test name | |
| Test status | |
| Simulation time | 4741990834 ps |
| CPU time | 55.54 seconds |
| Started | Aug 24 05:11:57 AM UTC 24 |
| Finished | Aug 24 05:12:54 AM UTC 24 |
| Peak memory | 595988 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=517068974 -assert nopostproc +UVM_TE STNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.xbar_smoke_slow_rsp.517068974 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/21.xbar_smoke_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/21.xbar_smoke_zero_delays.1007157863 |
| Short name | T1551 |
| Test name | |
| Test status | |
| Simulation time | 46197649 ps |
| CPU time | 5.26 seconds |
| Started | Aug 24 05:11:39 AM UTC 24 |
| Finished | Aug 24 05:11:46 AM UTC 24 |
| Peak memory | 595856 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1007157863 -assert nopostpr oc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.xbar_smoke_zero_delays.1007157863 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/21.xbar_smoke_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/21.xbar_stress_all_with_error.1993712122 |
| Short name | T1579 |
| Test name | |
| Test status | |
| Simulation time | 7310385743 ps |
| CPU time | 179.18 seconds |
| Started | Aug 24 05:14:33 AM UTC 24 |
| Finished | Aug 24 05:17:35 AM UTC 24 |
| Peak memory | 598084 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1993712122 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.xbar_stress_all_with_error.1993712122 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/21.xbar_stress_all_with_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/21.xbar_stress_all_with_rand_reset.3197466228 |
| Short name | T1569 |
| Test name | |
| Test status | |
| Simulation time | 233203776 ps |
| CPU time | 91.46 seconds |
| Started | Aug 24 05:14:12 AM UTC 24 |
| Finished | Aug 24 05:15:46 AM UTC 24 |
| Peak memory | 597692 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3197466228 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.xbar_stress_all_with_rand_reset.3197466228 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/21.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/21.xbar_stress_all_with_reset_error.1672185677 |
| Short name | T1570 |
| Test name | |
| Test status | |
| Simulation time | 232709061 ps |
| CPU time | 76.54 seconds |
| Started | Aug 24 05:14:40 AM UTC 24 |
| Finished | Aug 24 05:15:58 AM UTC 24 |
| Peak memory | 597760 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1672185677 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.xbar_stress_all_with_reset_error.1672185677 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/21.xbar_stress_all_with_reset_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/21.xbar_unmapped_addr.2867650390 |
| Short name | T1561 |
| Test name | |
| Test status | |
| Simulation time | 1104862647 ps |
| CPU time | 36.83 seconds |
| Started | Aug 24 05:13:48 AM UTC 24 |
| Finished | Aug 24 05:14:26 AM UTC 24 |
| Peak memory | 597692 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2867650390 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.xbar_unmapped_addr.2867650390 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/21.xbar_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/22.chip_tl_errors.2903657465 |
| Short name | T637 |
| Test name | |
| Test status | |
| Simulation time | 4376826770 ps |
| CPU time | 253.35 seconds |
| Started | Aug 24 05:14:46 AM UTC 24 |
| Finished | Aug 24 05:19:03 AM UTC 24 |
| Peak memory | 623476 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enable d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2903657465 -assert nopostpro c +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.chip_tl_errors.2903657465 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/22.chip_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/22.xbar_access_same_device.2897434665 |
| Short name | T1573 |
| Test name | |
| Test status | |
| Simulation time | 749710270 ps |
| CPU time | 46.05 seconds |
| Started | Aug 24 05:15:29 AM UTC 24 |
| Finished | Aug 24 05:16:17 AM UTC 24 |
| Peak memory | 597772 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2897434665 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.xbar_access_same_device.2897434665 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/22.xbar_access_same_device/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/22.xbar_access_same_device_slow_rsp.4282879970 |
| Short name | T830 |
| Test name | |
| Test status | |
| Simulation time | 48388567428 ps |
| CPU time | 589.6 seconds |
| Started | Aug 24 05:16:00 AM UTC 24 |
| Finished | Aug 24 05:25:56 AM UTC 24 |
| Peak memory | 598076 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4282879970 -assert nopostproc +UVM_T ESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.xbar_access_same_device_slow_rsp.4282879970 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/22.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/22.xbar_error_and_unmapped_addr.2109959829 |
| Short name | T1577 |
| Test name | |
| Test status | |
| Simulation time | 510297241 ps |
| CPU time | 15.97 seconds |
| Started | Aug 24 05:16:31 AM UTC 24 |
| Finished | Aug 24 05:16:48 AM UTC 24 |
| Peak memory | 597700 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2109959829 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.xbar_error_and_unmapped_addr.2109959829 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/22.xbar_error_and_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/22.xbar_error_random.1013729076 |
| Short name | T1576 |
| Test name | |
| Test status | |
| Simulation time | 1347391507 ps |
| CPU time | 32.45 seconds |
| Started | Aug 24 05:16:13 AM UTC 24 |
| Finished | Aug 24 05:16:47 AM UTC 24 |
| Peak memory | 597696 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1013729076 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.xbar_error_random.1013729076 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/22.xbar_error_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/22.xbar_random.2947334597 |
| Short name | T1568 |
| Test name | |
| Test status | |
| Simulation time | 281583866 ps |
| CPU time | 9.3 seconds |
| Started | Aug 24 05:15:05 AM UTC 24 |
| Finished | Aug 24 05:15:15 AM UTC 24 |
| Peak memory | 597760 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2947334597 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.xbar_random.2947334597 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/22.xbar_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/22.xbar_random_large_delays.716922106 |
| Short name | T1589 |
| Test name | |
| Test status | |
| Simulation time | 28159986226 ps |
| CPU time | 248.63 seconds |
| Started | Aug 24 05:15:18 AM UTC 24 |
| Finished | Aug 24 05:19:30 AM UTC 24 |
| Peak memory | 597820 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max _device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=716922106 -assert nopostproc +UV M_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.xbar_random_large_delays.716922106 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/22.xbar_random_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/22.xbar_random_slow_rsp.667925017 |
| Short name | T1632 |
| Test name | |
| Test status | |
| Simulation time | 63504663699 ps |
| CPU time | 726.11 seconds |
| Started | Aug 24 05:15:21 AM UTC 24 |
| Finished | Aug 24 05:27:35 AM UTC 24 |
| Peak memory | 597828 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=667925017 -assert nopostproc +UVM_TE STNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.xbar_random_slow_rsp.667925017 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/22.xbar_random_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/22.xbar_random_zero_delays.482264659 |
| Short name | T534 |
| Test name | |
| Test status | |
| Simulation time | 594823961 ps |
| CPU time | 39.5 seconds |
| Started | Aug 24 05:15:13 AM UTC 24 |
| Finished | Aug 24 05:15:54 AM UTC 24 |
| Peak memory | 597924 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=482264659 -assert nopostpro c +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.xbar_random_zero_delays.482264659 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/22.xbar_random_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/22.xbar_same_source.3306233791 |
| Short name | T1572 |
| Test name | |
| Test status | |
| Simulation time | 78995010 ps |
| CPU time | 7.04 seconds |
| Started | Aug 24 05:16:08 AM UTC 24 |
| Finished | Aug 24 05:16:17 AM UTC 24 |
| Peak memory | 597676 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3306233791 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.xbar_same_source.3306233791 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/22.xbar_same_source/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/22.xbar_smoke.317352820 |
| Short name | T1565 |
| Test name | |
| Test status | |
| Simulation time | 56769445 ps |
| CPU time | 5.55 seconds |
| Started | Aug 24 05:14:52 AM UTC 24 |
| Finished | Aug 24 05:14:58 AM UTC 24 |
| Peak memory | 595636 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=317352820 -assert nopostproc +UVM_TESTNAME =xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08 _22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.xbar_smoke.317352820 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/22.xbar_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/22.xbar_smoke_large_delays.4059355286 |
| Short name | T1574 |
| Test name | |
| Test status | |
| Simulation time | 9754877675 ps |
| CPU time | 79.26 seconds |
| Started | Aug 24 05:14:59 AM UTC 24 |
| Finished | Aug 24 05:16:19 AM UTC 24 |
| Peak memory | 595764 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max _device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4059355286 -assert nopostproc +U VM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.xbar_smoke_large_delays.4059355286 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/22.xbar_smoke_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/22.xbar_smoke_slow_rsp.2906734483 |
| Short name | T1575 |
| Test name | |
| Test status | |
| Simulation time | 7832994464 ps |
| CPU time | 91.4 seconds |
| Started | Aug 24 05:15:02 AM UTC 24 |
| Finished | Aug 24 05:16:35 AM UTC 24 |
| Peak memory | 595772 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2906734483 -assert nopostproc +UVM_T ESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.xbar_smoke_slow_rsp.2906734483 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/22.xbar_smoke_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/22.xbar_smoke_zero_delays.2210970842 |
| Short name | T1566 |
| Test name | |
| Test status | |
| Simulation time | 55712047 ps |
| CPU time | 5.43 seconds |
| Started | Aug 24 05:14:57 AM UTC 24 |
| Finished | Aug 24 05:15:03 AM UTC 24 |
| Peak memory | 595632 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2210970842 -assert nopostpr oc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.xbar_smoke_zero_delays.2210970842 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/22.xbar_smoke_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/22.xbar_stress_all.1162085906 |
| Short name | T1612 |
| Test name | |
| Test status | |
| Simulation time | 14261759224 ps |
| CPU time | 355.18 seconds |
| Started | Aug 24 05:16:33 AM UTC 24 |
| Finished | Aug 24 05:22:33 AM UTC 24 |
| Peak memory | 597952 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1162085906 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.xbar_stress_all.1162085906 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/22.xbar_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/22.xbar_stress_all_with_error.2493436406 |
| Short name | T1601 |
| Test name | |
| Test status | |
| Simulation time | 9881624597 ps |
| CPU time | 247.64 seconds |
| Started | Aug 24 05:17:01 AM UTC 24 |
| Finished | Aug 24 05:21:13 AM UTC 24 |
| Peak memory | 597824 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2493436406 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.xbar_stress_all_with_error.2493436406 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/22.xbar_stress_all_with_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/22.xbar_stress_all_with_rand_reset.55528403 |
| Short name | T834 |
| Test name | |
| Test status | |
| Simulation time | 1874652235 ps |
| CPU time | 353.58 seconds |
| Started | Aug 24 05:16:49 AM UTC 24 |
| Finished | Aug 24 05:22:47 AM UTC 24 |
| Peak memory | 597696 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=55528403 -assert nopostproc +UVM_TESTNAME= xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.xbar_stress_all_with_rand_reset.55528403 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/22.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/22.xbar_unmapped_addr.1145059185 |
| Short name | T500 |
| Test name | |
| Test status | |
| Simulation time | 1506466308 ps |
| CPU time | 45.61 seconds |
| Started | Aug 24 05:16:31 AM UTC 24 |
| Finished | Aug 24 05:17:18 AM UTC 24 |
| Peak memory | 597944 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1145059185 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.xbar_unmapped_addr.1145059185 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/22.xbar_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/23.chip_tl_errors.1150101392 |
| Short name | T634 |
| Test name | |
| Test status | |
| Simulation time | 3435196104 ps |
| CPU time | 117.29 seconds |
| Started | Aug 24 05:17:32 AM UTC 24 |
| Finished | Aug 24 05:19:32 AM UTC 24 |
| Peak memory | 623320 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enable d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1150101392 -assert nopostpro c +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.chip_tl_errors.1150101392 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/23.chip_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/23.xbar_access_same_device.240144733 |
| Short name | T1591 |
| Test name | |
| Test status | |
| Simulation time | 645535718 ps |
| CPU time | 39.21 seconds |
| Started | Aug 24 05:18:52 AM UTC 24 |
| Finished | Aug 24 05:19:33 AM UTC 24 |
| Peak memory | 597704 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=240144733 -assert nopostproc +UVM_TESTNAME =xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.xbar_access_same_device.240144733 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/23.xbar_access_same_device/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/23.xbar_access_same_device_slow_rsp.287568497 |
| Short name | T1644 |
| Test name | |
| Test status | |
| Simulation time | 51347102463 ps |
| CPU time | 582.04 seconds |
| Started | Aug 24 05:18:53 AM UTC 24 |
| Finished | Aug 24 05:28:41 AM UTC 24 |
| Peak memory | 598044 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=287568497 -assert nopostproc +UVM_TE STNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os _regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.xbar_access_same_device_slow_rsp.287568497 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/23.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/23.xbar_error_and_unmapped_addr.3830826278 |
| Short name | T1590 |
| Test name | |
| Test status | |
| Simulation time | 20955088 ps |
| CPU time | 4.37 seconds |
| Started | Aug 24 05:19:26 AM UTC 24 |
| Finished | Aug 24 05:19:31 AM UTC 24 |
| Peak memory | 594996 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3830826278 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.xbar_error_and_unmapped_addr.3830826278 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/23.xbar_error_and_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/23.xbar_error_random.2125742229 |
| Short name | T1592 |
| Test name | |
| Test status | |
| Simulation time | 374041831 ps |
| CPU time | 20.58 seconds |
| Started | Aug 24 05:19:17 AM UTC 24 |
| Finished | Aug 24 05:19:39 AM UTC 24 |
| Peak memory | 597952 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2125742229 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.xbar_error_random.2125742229 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/23.xbar_error_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/23.xbar_random.1604117858 |
| Short name | T1583 |
| Test name | |
| Test status | |
| Simulation time | 65831213 ps |
| CPU time | 6.83 seconds |
| Started | Aug 24 05:18:11 AM UTC 24 |
| Finished | Aug 24 05:18:19 AM UTC 24 |
| Peak memory | 597688 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1604117858 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.xbar_random.1604117858 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/23.xbar_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/23.xbar_random_large_delays.3404373279 |
| Short name | T1623 |
| Test name | |
| Test status | |
| Simulation time | 57316738801 ps |
| CPU time | 460.49 seconds |
| Started | Aug 24 05:18:33 AM UTC 24 |
| Finished | Aug 24 05:26:19 AM UTC 24 |
| Peak memory | 597888 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max _device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3404373279 -assert nopostproc +U VM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.xbar_random_large_delays.3404373279 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/23.xbar_random_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/23.xbar_random_slow_rsp.3206481140 |
| Short name | T1602 |
| Test name | |
| Test status | |
| Simulation time | 15178460817 ps |
| CPU time | 170.73 seconds |
| Started | Aug 24 05:18:35 AM UTC 24 |
| Finished | Aug 24 05:21:29 AM UTC 24 |
| Peak memory | 597816 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3206481140 -assert nopostproc +UVM_T ESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.xbar_random_slow_rsp.3206481140 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/23.xbar_random_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/23.xbar_random_zero_delays.453805179 |
| Short name | T1584 |
| Test name | |
| Test status | |
| Simulation time | 118507687 ps |
| CPU time | 9.67 seconds |
| Started | Aug 24 05:18:28 AM UTC 24 |
| Finished | Aug 24 05:18:39 AM UTC 24 |
| Peak memory | 597696 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=453805179 -assert nopostpro c +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.xbar_random_zero_delays.453805179 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/23.xbar_random_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/23.xbar_same_source.357984303 |
| Short name | T1586 |
| Test name | |
| Test status | |
| Simulation time | 186872337 ps |
| CPU time | 12.81 seconds |
| Started | Aug 24 05:18:53 AM UTC 24 |
| Finished | Aug 24 05:19:07 AM UTC 24 |
| Peak memory | 597692 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=357984303 -assert nopostproc +UVM_TESTNAME =xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.xbar_same_source.357984303 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/23.xbar_same_source/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/23.xbar_smoke.1395946739 |
| Short name | T1571 |
| Test name | |
| Test status | |
| Simulation time | 198474919 ps |
| CPU time | 7.01 seconds |
| Started | Aug 24 05:17:48 AM UTC 24 |
| Finished | Aug 24 05:17:56 AM UTC 24 |
| Peak memory | 595916 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1395946739 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 8_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.xbar_smoke.1395946739 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/23.xbar_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/23.xbar_smoke_large_delays.1159166059 |
| Short name | T1588 |
| Test name | |
| Test status | |
| Simulation time | 9504427551 ps |
| CPU time | 75.22 seconds |
| Started | Aug 24 05:18:03 AM UTC 24 |
| Finished | Aug 24 05:19:20 AM UTC 24 |
| Peak memory | 596148 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max _device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1159166059 -assert nopostproc +U VM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.xbar_smoke_large_delays.1159166059 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/23.xbar_smoke_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/23.xbar_smoke_slow_rsp.1276782786 |
| Short name | T1587 |
| Test name | |
| Test status | |
| Simulation time | 5713507844 ps |
| CPU time | 66.85 seconds |
| Started | Aug 24 05:18:10 AM UTC 24 |
| Finished | Aug 24 05:19:18 AM UTC 24 |
| Peak memory | 595908 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1276782786 -assert nopostproc +UVM_T ESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.xbar_smoke_slow_rsp.1276782786 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/23.xbar_smoke_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/23.xbar_smoke_zero_delays.3408338145 |
| Short name | T1581 |
| Test name | |
| Test status | |
| Simulation time | 53076748 ps |
| CPU time | 5.81 seconds |
| Started | Aug 24 05:17:50 AM UTC 24 |
| Finished | Aug 24 05:17:56 AM UTC 24 |
| Peak memory | 595764 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3408338145 -assert nopostpr oc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.xbar_smoke_zero_delays.3408338145 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/23.xbar_smoke_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/23.xbar_stress_all.1404477203 |
| Short name | T516 |
| Test name | |
| Test status | |
| Simulation time | 9821785957 ps |
| CPU time | 256.69 seconds |
| Started | Aug 24 05:19:32 AM UTC 24 |
| Finished | Aug 24 05:23:53 AM UTC 24 |
| Peak memory | 597960 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1404477203 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.xbar_stress_all.1404477203 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/23.xbar_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/23.xbar_stress_all_with_error.1133720022 |
| Short name | T1596 |
| Test name | |
| Test status | |
| Simulation time | 1154091356 ps |
| CPU time | 34.1 seconds |
| Started | Aug 24 05:19:44 AM UTC 24 |
| Finished | Aug 24 05:20:20 AM UTC 24 |
| Peak memory | 597952 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1133720022 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.xbar_stress_all_with_error.1133720022 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/23.xbar_stress_all_with_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/23.xbar_stress_all_with_rand_reset.3439165428 |
| Short name | T839 |
| Test name | |
| Test status | |
| Simulation time | 164286848 ps |
| CPU time | 33.25 seconds |
| Started | Aug 24 05:19:34 AM UTC 24 |
| Finished | Aug 24 05:20:08 AM UTC 24 |
| Peak memory | 597928 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3439165428 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.xbar_stress_all_with_rand_reset.3439165428 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/23.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/23.xbar_stress_all_with_reset_error.44025914 |
| Short name | T1607 |
| Test name | |
| Test status | |
| Simulation time | 389977169 ps |
| CPU time | 111.75 seconds |
| Started | Aug 24 05:19:46 AM UTC 24 |
| Finished | Aug 24 05:21:39 AM UTC 24 |
| Peak memory | 597988 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=44025914 -assert nopostproc +UVM_TESTNAME= xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.xbar_stress_all_with_reset_error.44025914 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/23.xbar_stress_all_with_reset_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/23.xbar_unmapped_addr.4260659423 |
| Short name | T1593 |
| Test name | |
| Test status | |
| Simulation time | 577174441 ps |
| CPU time | 17.62 seconds |
| Started | Aug 24 05:19:21 AM UTC 24 |
| Finished | Aug 24 05:19:40 AM UTC 24 |
| Peak memory | 597688 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4260659423 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.xbar_unmapped_addr.4260659423 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/23.xbar_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/24.chip_tl_errors.614111280 |
| Short name | T650 |
| Test name | |
| Test status | |
| Simulation time | 3688285006 ps |
| CPU time | 208.29 seconds |
| Started | Aug 24 05:19:46 AM UTC 24 |
| Finished | Aug 24 05:23:17 AM UTC 24 |
| Peak memory | 623384 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enable d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=614111280 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.chip_tl_errors.614111280 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/24.chip_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/24.xbar_access_same_device.1700444045 |
| Short name | T1606 |
| Test name | |
| Test status | |
| Simulation time | 777889790 ps |
| CPU time | 25.07 seconds |
| Started | Aug 24 05:21:11 AM UTC 24 |
| Finished | Aug 24 05:21:38 AM UTC 24 |
| Peak memory | 597856 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1700444045 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.xbar_access_same_device.1700444045 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/24.xbar_access_same_device/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/24.xbar_access_same_device_slow_rsp.771404939 |
| Short name | T1803 |
| Test name | |
| Test status | |
| Simulation time | 147842258700 ps |
| CPU time | 1702.3 seconds |
| Started | Aug 24 05:21:12 AM UTC 24 |
| Finished | Aug 24 05:49:52 AM UTC 24 |
| Peak memory | 598788 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=771404939 -assert nopostproc +UVM_TE STNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os _regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.xbar_access_same_device_slow_rsp.771404939 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/24.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/24.xbar_error_and_unmapped_addr.3823949737 |
| Short name | T1604 |
| Test name | |
| Test status | |
| Simulation time | 19376220 ps |
| CPU time | 4.56 seconds |
| Started | Aug 24 05:21:27 AM UTC 24 |
| Finished | Aug 24 05:21:33 AM UTC 24 |
| Peak memory | 595640 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3823949737 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.xbar_error_and_unmapped_addr.3823949737 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/24.xbar_error_and_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/24.xbar_error_random.4021775368 |
| Short name | T1603 |
| Test name | |
| Test status | |
| Simulation time | 138626106 ps |
| CPU time | 11.08 seconds |
| Started | Aug 24 05:21:20 AM UTC 24 |
| Finished | Aug 24 05:21:32 AM UTC 24 |
| Peak memory | 597924 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4021775368 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.xbar_error_random.4021775368 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/24.xbar_error_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/24.xbar_random.3669058479 |
| Short name | T1597 |
| Test name | |
| Test status | |
| Simulation time | 807211286 ps |
| CPU time | 24.1 seconds |
| Started | Aug 24 05:20:13 AM UTC 24 |
| Finished | Aug 24 05:20:38 AM UTC 24 |
| Peak memory | 597828 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3669058479 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.xbar_random.3669058479 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/24.xbar_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/24.xbar_random_large_delays.785251492 |
| Short name | T1626 |
| Test name | |
| Test status | |
| Simulation time | 44720053408 ps |
| CPU time | 371.66 seconds |
| Started | Aug 24 05:20:34 AM UTC 24 |
| Finished | Aug 24 05:26:50 AM UTC 24 |
| Peak memory | 597820 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max _device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=785251492 -assert nopostproc +UV M_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.xbar_random_large_delays.785251492 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/24.xbar_random_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/24.xbar_random_slow_rsp.2701093954 |
| Short name | T1633 |
| Test name | |
| Test status | |
| Simulation time | 35152460523 ps |
| CPU time | 412.36 seconds |
| Started | Aug 24 05:20:52 AM UTC 24 |
| Finished | Aug 24 05:27:49 AM UTC 24 |
| Peak memory | 597816 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2701093954 -assert nopostproc +UVM_T ESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.xbar_random_slow_rsp.2701093954 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/24.xbar_random_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/24.xbar_random_zero_delays.1457934547 |
| Short name | T535 |
| Test name | |
| Test status | |
| Simulation time | 563049065 ps |
| CPU time | 33.86 seconds |
| Started | Aug 24 05:20:22 AM UTC 24 |
| Finished | Aug 24 05:20:57 AM UTC 24 |
| Peak memory | 597840 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1457934547 -assert nopostpr oc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.xbar_random_zero_delays.1457934547 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/24.xbar_random_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/24.xbar_same_source.503657475 |
| Short name | T1610 |
| Test name | |
| Test status | |
| Simulation time | 2455855820 ps |
| CPU time | 50.84 seconds |
| Started | Aug 24 05:21:19 AM UTC 24 |
| Finished | Aug 24 05:22:11 AM UTC 24 |
| Peak memory | 597900 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=503657475 -assert nopostproc +UVM_TESTNAME =xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.xbar_same_source.503657475 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/24.xbar_same_source/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/24.xbar_smoke.2717896042 |
| Short name | T1594 |
| Test name | |
| Test status | |
| Simulation time | 190814219 ps |
| CPU time | 6.51 seconds |
| Started | Aug 24 05:19:47 AM UTC 24 |
| Finished | Aug 24 05:19:54 AM UTC 24 |
| Peak memory | 595880 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2717896042 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 8_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.xbar_smoke.2717896042 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/24.xbar_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/24.xbar_smoke_large_delays.1286878436 |
| Short name | T1599 |
| Test name | |
| Test status | |
| Simulation time | 8096042682 ps |
| CPU time | 69.19 seconds |
| Started | Aug 24 05:19:54 AM UTC 24 |
| Finished | Aug 24 05:21:04 AM UTC 24 |
| Peak memory | 595764 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max _device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1286878436 -assert nopostproc +U VM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.xbar_smoke_large_delays.1286878436 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/24.xbar_smoke_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/24.xbar_smoke_slow_rsp.2193206655 |
| Short name | T1598 |
| Test name | |
| Test status | |
| Simulation time | 4018772021 ps |
| CPU time | 47.96 seconds |
| Started | Aug 24 05:20:09 AM UTC 24 |
| Finished | Aug 24 05:20:58 AM UTC 24 |
| Peak memory | 595844 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2193206655 -assert nopostproc +UVM_T ESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.xbar_smoke_slow_rsp.2193206655 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/24.xbar_smoke_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/24.xbar_smoke_zero_delays.3190381163 |
| Short name | T1595 |
| Test name | |
| Test status | |
| Simulation time | 48372632 ps |
| CPU time | 4.92 seconds |
| Started | Aug 24 05:19:53 AM UTC 24 |
| Finished | Aug 24 05:19:59 AM UTC 24 |
| Peak memory | 595848 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3190381163 -assert nopostpr oc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.xbar_smoke_zero_delays.3190381163 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/24.xbar_smoke_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/24.xbar_stress_all.190040860 |
| Short name | T506 |
| Test name | |
| Test status | |
| Simulation time | 11096839558 ps |
| CPU time | 313.37 seconds |
| Started | Aug 24 05:21:42 AM UTC 24 |
| Finished | Aug 24 05:27:00 AM UTC 24 |
| Peak memory | 598212 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=190040860 -assert nopostproc +UVM_TESTNAME =xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.xbar_stress_all.190040860 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/24.xbar_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/24.xbar_stress_all_with_error.424624203 |
| Short name | T819 |
| Test name | |
| Test status | |
| Simulation time | 12203819406 ps |
| CPU time | 324.04 seconds |
| Started | Aug 24 05:21:47 AM UTC 24 |
| Finished | Aug 24 05:27:16 AM UTC 24 |
| Peak memory | 597824 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=424624203 -assert nopostproc +UVM_TESTNAME =xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.xbar_stress_all_with_error.424624203 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/24.xbar_stress_all_with_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/24.xbar_stress_all_with_rand_reset.3939982260 |
| Short name | T842 |
| Test name | |
| Test status | |
| Simulation time | 729981991 ps |
| CPU time | 215.87 seconds |
| Started | Aug 24 05:21:46 AM UTC 24 |
| Finished | Aug 24 05:25:25 AM UTC 24 |
| Peak memory | 597692 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3939982260 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.xbar_stress_all_with_rand_reset.3939982260 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/24.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/24.xbar_stress_all_with_reset_error.2816871109 |
| Short name | T840 |
| Test name | |
| Test status | |
| Simulation time | 16154368208 ps |
| CPU time | 574.91 seconds |
| Started | Aug 24 05:21:47 AM UTC 24 |
| Finished | Aug 24 05:31:29 AM UTC 24 |
| Peak memory | 597824 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2816871109 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.xbar_stress_all_with_reset_error.2816871109 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/24.xbar_stress_all_with_reset_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/24.xbar_unmapped_addr.2885207520 |
| Short name | T1605 |
| Test name | |
| Test status | |
| Simulation time | 260468506 ps |
| CPU time | 9.75 seconds |
| Started | Aug 24 05:21:22 AM UTC 24 |
| Finished | Aug 24 05:21:33 AM UTC 24 |
| Peak memory | 597696 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2885207520 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.xbar_unmapped_addr.2885207520 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/24.xbar_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/25.chip_tl_errors.60661371 |
| Short name | T1619 |
| Test name | |
| Test status | |
| Simulation time | 4078989752 ps |
| CPU time | 197.96 seconds |
| Started | Aug 24 05:21:52 AM UTC 24 |
| Finished | Aug 24 05:25:13 AM UTC 24 |
| Peak memory | 623384 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enable d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=60661371 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.chip_tl_errors.60661371 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/25.chip_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/25.xbar_access_same_device.182757044 |
| Short name | T1616 |
| Test name | |
| Test status | |
| Simulation time | 1737679692 ps |
| CPU time | 51.82 seconds |
| Started | Aug 24 05:23:17 AM UTC 24 |
| Finished | Aug 24 05:24:10 AM UTC 24 |
| Peak memory | 597952 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=182757044 -assert nopostproc +UVM_TESTNAME =xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.xbar_access_same_device.182757044 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/25.xbar_access_same_device/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/25.xbar_access_same_device_slow_rsp.3441279604 |
| Short name | T1799 |
| Test name | |
| Test status | |
| Simulation time | 124818132124 ps |
| CPU time | 1533.52 seconds |
| Started | Aug 24 05:23:31 AM UTC 24 |
| Finished | Aug 24 05:49:20 AM UTC 24 |
| Peak memory | 599036 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3441279604 -assert nopostproc +UVM_T ESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.xbar_access_same_device_slow_rsp.3441279604 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/25.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/25.xbar_error_and_unmapped_addr.3544363286 |
| Short name | T1618 |
| Test name | |
| Test status | |
| Simulation time | 1039130901 ps |
| CPU time | 29.12 seconds |
| Started | Aug 24 05:24:14 AM UTC 24 |
| Finished | Aug 24 05:24:44 AM UTC 24 |
| Peak memory | 597696 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3544363286 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.xbar_error_and_unmapped_addr.3544363286 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/25.xbar_error_and_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/25.xbar_random.2262641234 |
| Short name | T1613 |
| Test name | |
| Test status | |
| Simulation time | 511625179 ps |
| CPU time | 14.59 seconds |
| Started | Aug 24 05:22:35 AM UTC 24 |
| Finished | Aug 24 05:22:51 AM UTC 24 |
| Peak memory | 597692 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2262641234 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.xbar_random.2262641234 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/25.xbar_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/25.xbar_random_large_delays.2193054111 |
| Short name | T1636 |
| Test name | |
| Test status | |
| Simulation time | 36659646562 ps |
| CPU time | 291.02 seconds |
| Started | Aug 24 05:23:02 AM UTC 24 |
| Finished | Aug 24 05:27:57 AM UTC 24 |
| Peak memory | 597824 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max _device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2193054111 -assert nopostproc +U VM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.xbar_random_large_delays.2193054111 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/25.xbar_random_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/25.xbar_random_slow_rsp.4114825163 |
| Short name | T1637 |
| Test name | |
| Test status | |
| Simulation time | 23449443326 ps |
| CPU time | 288.67 seconds |
| Started | Aug 24 05:23:05 AM UTC 24 |
| Finished | Aug 24 05:27:58 AM UTC 24 |
| Peak memory | 597828 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4114825163 -assert nopostproc +UVM_T ESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.xbar_random_slow_rsp.4114825163 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/25.xbar_random_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/25.xbar_random_zero_delays.726706160 |
| Short name | T512 |
| Test name | |
| Test status | |
| Simulation time | 608011524 ps |
| CPU time | 38.85 seconds |
| Started | Aug 24 05:22:47 AM UTC 24 |
| Finished | Aug 24 05:23:27 AM UTC 24 |
| Peak memory | 597700 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=726706160 -assert nopostpro c +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.xbar_random_zero_delays.726706160 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/25.xbar_random_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/25.xbar_smoke.1023799570 |
| Short name | T1608 |
| Test name | |
| Test status | |
| Simulation time | 50703414 ps |
| CPU time | 5.15 seconds |
| Started | Aug 24 05:21:54 AM UTC 24 |
| Finished | Aug 24 05:22:00 AM UTC 24 |
| Peak memory | 595628 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1023799570 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 8_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.xbar_smoke.1023799570 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/25.xbar_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/25.xbar_smoke_large_delays.1070375280 |
| Short name | T1614 |
| Test name | |
| Test status | |
| Simulation time | 5373721284 ps |
| CPU time | 44.68 seconds |
| Started | Aug 24 05:22:16 AM UTC 24 |
| Finished | Aug 24 05:23:02 AM UTC 24 |
| Peak memory | 595768 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max _device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1070375280 -assert nopostproc +U VM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.xbar_smoke_large_delays.1070375280 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/25.xbar_smoke_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/25.xbar_smoke_slow_rsp.1280312283 |
| Short name | T1615 |
| Test name | |
| Test status | |
| Simulation time | 4622196524 ps |
| CPU time | 55.14 seconds |
| Started | Aug 24 05:22:26 AM UTC 24 |
| Finished | Aug 24 05:23:23 AM UTC 24 |
| Peak memory | 595912 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1280312283 -assert nopostproc +UVM_T ESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.xbar_smoke_slow_rsp.1280312283 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/25.xbar_smoke_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/25.xbar_smoke_zero_delays.3760945293 |
| Short name | T1611 |
| Test name | |
| Test status | |
| Simulation time | 45428396 ps |
| CPU time | 5.02 seconds |
| Started | Aug 24 05:22:15 AM UTC 24 |
| Finished | Aug 24 05:22:21 AM UTC 24 |
| Peak memory | 595632 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3760945293 -assert nopostpr oc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.xbar_smoke_zero_delays.3760945293 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/25.xbar_smoke_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/25.xbar_stress_all.3700375100 |
| Short name | T1627 |
| Test name | |
| Test status | |
| Simulation time | 5466887188 ps |
| CPU time | 155.31 seconds |
| Started | Aug 24 05:24:17 AM UTC 24 |
| Finished | Aug 24 05:26:55 AM UTC 24 |
| Peak memory | 597824 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3700375100 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.xbar_stress_all.3700375100 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/25.xbar_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/25.xbar_stress_all_with_error.3334631150 |
| Short name | T1642 |
| Test name | |
| Test status | |
| Simulation time | 7922227078 ps |
| CPU time | 224.78 seconds |
| Started | Aug 24 05:24:47 AM UTC 24 |
| Finished | Aug 24 05:28:35 AM UTC 24 |
| Peak memory | 598084 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3334631150 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.xbar_stress_all_with_error.3334631150 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/25.xbar_stress_all_with_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/25.xbar_stress_all_with_rand_reset.2659859961 |
| Short name | T517 |
| Test name | |
| Test status | |
| Simulation time | 5909147948 ps |
| CPU time | 370.9 seconds |
| Started | Aug 24 05:24:24 AM UTC 24 |
| Finished | Aug 24 05:30:39 AM UTC 24 |
| Peak memory | 597824 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2659859961 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.xbar_stress_all_with_rand_reset.2659859961 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/25.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/25.xbar_stress_all_with_reset_error.3930966251 |
| Short name | T835 |
| Test name | |
| Test status | |
| Simulation time | 328591163 ps |
| CPU time | 81.15 seconds |
| Started | Aug 24 05:24:50 AM UTC 24 |
| Finished | Aug 24 05:26:13 AM UTC 24 |
| Peak memory | 597756 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3930966251 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.xbar_stress_all_with_reset_error.3930966251 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/25.xbar_stress_all_with_reset_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/25.xbar_unmapped_addr.1705954773 |
| Short name | T1617 |
| Test name | |
| Test status | |
| Simulation time | 306049352 ps |
| CPU time | 27.93 seconds |
| Started | Aug 24 05:24:07 AM UTC 24 |
| Finished | Aug 24 05:24:36 AM UTC 24 |
| Peak memory | 597944 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1705954773 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.xbar_unmapped_addr.1705954773 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/25.xbar_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/26.chip_tl_errors.1404076536 |
| Short name | T1643 |
| Test name | |
| Test status | |
| Simulation time | 4734228496 ps |
| CPU time | 217.19 seconds |
| Started | Aug 24 05:24:58 AM UTC 24 |
| Finished | Aug 24 05:28:38 AM UTC 24 |
| Peak memory | 623388 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enable d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1404076536 -assert nopostpro c +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.chip_tl_errors.1404076536 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/26.chip_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/26.xbar_access_same_device.3524706324 |
| Short name | T1640 |
| Test name | |
| Test status | |
| Simulation time | 3514350267 ps |
| CPU time | 105.57 seconds |
| Started | Aug 24 05:26:37 AM UTC 24 |
| Finished | Aug 24 05:28:24 AM UTC 24 |
| Peak memory | 597988 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3524706324 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.xbar_access_same_device.3524706324 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/26.xbar_access_same_device/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/26.xbar_access_same_device_slow_rsp.2397008352 |
| Short name | T820 |
| Test name | |
| Test status | |
| Simulation time | 62149928466 ps |
| CPU time | 707.46 seconds |
| Started | Aug 24 05:26:41 AM UTC 24 |
| Finished | Aug 24 05:38:36 AM UTC 24 |
| Peak memory | 597892 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2397008352 -assert nopostproc +UVM_T ESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.xbar_access_same_device_slow_rsp.2397008352 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/26.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/26.xbar_error_and_unmapped_addr.913193670 |
| Short name | T1634 |
| Test name | |
| Test status | |
| Simulation time | 1263660808 ps |
| CPU time | 36.63 seconds |
| Started | Aug 24 05:27:14 AM UTC 24 |
| Finished | Aug 24 05:27:52 AM UTC 24 |
| Peak memory | 597692 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=913193670 -assert nopostproc +UVM_TESTNAME =xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.xbar_error_and_unmapped_addr.913193670 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/26.xbar_error_and_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/26.xbar_error_random.770823746 |
| Short name | T1631 |
| Test name | |
| Test status | |
| Simulation time | 1193368082 ps |
| CPU time | 28.65 seconds |
| Started | Aug 24 05:27:04 AM UTC 24 |
| Finished | Aug 24 05:27:34 AM UTC 24 |
| Peak memory | 597696 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=770823746 -assert nopostproc +UVM_TESTNAME =xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.xbar_error_random.770823746 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/26.xbar_error_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/26.xbar_random.429359164 |
| Short name | T505 |
| Test name | |
| Test status | |
| Simulation time | 465455795 ps |
| CPU time | 28.21 seconds |
| Started | Aug 24 05:25:56 AM UTC 24 |
| Finished | Aug 24 05:26:26 AM UTC 24 |
| Peak memory | 597756 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=429359164 -assert nopostproc +UVM_TESTNAME =xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 8_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.xbar_random.429359164 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/26.xbar_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/26.xbar_random_large_delays.1547805307 |
| Short name | T1717 |
| Test name | |
| Test status | |
| Simulation time | 91427851915 ps |
| CPU time | 707.65 seconds |
| Started | Aug 24 05:26:27 AM UTC 24 |
| Finished | Aug 24 05:38:21 AM UTC 24 |
| Peak memory | 597964 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max _device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1547805307 -assert nopostproc +U VM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.xbar_random_large_delays.1547805307 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/26.xbar_random_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/26.xbar_random_slow_rsp.75661278 |
| Short name | T1695 |
| Test name | |
| Test status | |
| Simulation time | 43176225369 ps |
| CPU time | 493.44 seconds |
| Started | Aug 24 05:26:34 AM UTC 24 |
| Finished | Aug 24 05:34:53 AM UTC 24 |
| Peak memory | 597884 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=75661278 -assert nopostproc +UVM_TES TNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.xbar_random_slow_rsp.75661278 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/26.xbar_random_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/26.xbar_random_zero_delays.497580318 |
| Short name | T1624 |
| Test name | |
| Test status | |
| Simulation time | 131037766 ps |
| CPU time | 10.31 seconds |
| Started | Aug 24 05:26:11 AM UTC 24 |
| Finished | Aug 24 05:26:22 AM UTC 24 |
| Peak memory | 597696 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=497580318 -assert nopostpro c +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.xbar_random_zero_delays.497580318 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/26.xbar_random_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/26.xbar_same_source.619908982 |
| Short name | T1630 |
| Test name | |
| Test status | |
| Simulation time | 767594845 ps |
| CPU time | 17.83 seconds |
| Started | Aug 24 05:27:02 AM UTC 24 |
| Finished | Aug 24 05:27:21 AM UTC 24 |
| Peak memory | 597696 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=619908982 -assert nopostproc +UVM_TESTNAME =xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.xbar_same_source.619908982 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/26.xbar_same_source/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/26.xbar_smoke.3351352059 |
| Short name | T1621 |
| Test name | |
| Test status | |
| Simulation time | 134777069 ps |
| CPU time | 5.71 seconds |
| Started | Aug 24 05:25:27 AM UTC 24 |
| Finished | Aug 24 05:25:34 AM UTC 24 |
| Peak memory | 595632 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3351352059 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 8_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.xbar_smoke.3351352059 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/26.xbar_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/26.xbar_smoke_large_delays.2279623560 |
| Short name | T1628 |
| Test name | |
| Test status | |
| Simulation time | 10503968866 ps |
| CPU time | 84.87 seconds |
| Started | Aug 24 05:25:40 AM UTC 24 |
| Finished | Aug 24 05:27:06 AM UTC 24 |
| Peak memory | 595764 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max _device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2279623560 -assert nopostproc +U VM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.xbar_smoke_large_delays.2279623560 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/26.xbar_smoke_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/26.xbar_smoke_slow_rsp.1933258925 |
| Short name | T1625 |
| Test name | |
| Test status | |
| Simulation time | 4883194435 ps |
| CPU time | 57.33 seconds |
| Started | Aug 24 05:25:49 AM UTC 24 |
| Finished | Aug 24 05:26:47 AM UTC 24 |
| Peak memory | 595768 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1933258925 -assert nopostproc +UVM_T ESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.xbar_smoke_slow_rsp.1933258925 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/26.xbar_smoke_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/26.xbar_smoke_zero_delays.228849982 |
| Short name | T1622 |
| Test name | |
| Test status | |
| Simulation time | 49061528 ps |
| CPU time | 5.27 seconds |
| Started | Aug 24 05:25:36 AM UTC 24 |
| Finished | Aug 24 05:25:42 AM UTC 24 |
| Peak memory | 595636 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=228849982 -assert nopostpro c +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.xbar_smoke_zero_delays.228849982 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/26.xbar_smoke_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/26.xbar_stress_all.3018570893 |
| Short name | T514 |
| Test name | |
| Test status | |
| Simulation time | 3372995487 ps |
| CPU time | 199.15 seconds |
| Started | Aug 24 05:27:20 AM UTC 24 |
| Finished | Aug 24 05:30:43 AM UTC 24 |
| Peak memory | 597760 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3018570893 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.xbar_stress_all.3018570893 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/26.xbar_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/26.xbar_stress_all_with_error.1584523669 |
| Short name | T1658 |
| Test name | |
| Test status | |
| Simulation time | 7851017295 ps |
| CPU time | 197.01 seconds |
| Started | Aug 24 05:27:30 AM UTC 24 |
| Finished | Aug 24 05:30:50 AM UTC 24 |
| Peak memory | 597824 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1584523669 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.xbar_stress_all_with_error.1584523669 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/26.xbar_stress_all_with_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/26.xbar_stress_all_with_rand_reset.1886987830 |
| Short name | T1674 |
| Test name | |
| Test status | |
| Simulation time | 2250847133 ps |
| CPU time | 300.08 seconds |
| Started | Aug 24 05:27:29 AM UTC 24 |
| Finished | Aug 24 05:32:33 AM UTC 24 |
| Peak memory | 597760 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1886987830 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.xbar_stress_all_with_rand_reset.1886987830 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/26.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/26.xbar_stress_all_with_reset_error.3802880264 |
| Short name | T851 |
| Test name | |
| Test status | |
| Simulation time | 2190354910 ps |
| CPU time | 262.88 seconds |
| Started | Aug 24 05:27:35 AM UTC 24 |
| Finished | Aug 24 05:32:02 AM UTC 24 |
| Peak memory | 597892 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3802880264 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.xbar_stress_all_with_reset_error.3802880264 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/26.xbar_stress_all_with_reset_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/26.xbar_unmapped_addr.121834206 |
| Short name | T1629 |
| Test name | |
| Test status | |
| Simulation time | 65925207 ps |
| CPU time | 4.85 seconds |
| Started | Aug 24 05:27:09 AM UTC 24 |
| Finished | Aug 24 05:27:15 AM UTC 24 |
| Peak memory | 595632 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=121834206 -assert nopostproc +UVM_TESTNAME =xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.xbar_unmapped_addr.121834206 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/26.xbar_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/27.chip_tl_errors.3968172459 |
| Short name | T1656 |
| Test name | |
| Test status | |
| Simulation time | 3757513850 ps |
| CPU time | 155.11 seconds |
| Started | Aug 24 05:27:48 AM UTC 24 |
| Finished | Aug 24 05:30:26 AM UTC 24 |
| Peak memory | 623324 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enable d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3968172459 -assert nopostpro c +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.chip_tl_errors.3968172459 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/27.chip_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/27.xbar_access_same_device.2522390615 |
| Short name | T502 |
| Test name | |
| Test status | |
| Simulation time | 411897007 ps |
| CPU time | 25.09 seconds |
| Started | Aug 24 05:28:39 AM UTC 24 |
| Finished | Aug 24 05:29:05 AM UTC 24 |
| Peak memory | 597992 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2522390615 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.xbar_access_same_device.2522390615 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/27.xbar_access_same_device/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/27.xbar_access_same_device_slow_rsp.3458883261 |
| Short name | T798 |
| Test name | |
| Test status | |
| Simulation time | 87884094802 ps |
| CPU time | 1072.41 seconds |
| Started | Aug 24 05:28:44 AM UTC 24 |
| Finished | Aug 24 05:46:47 AM UTC 24 |
| Peak memory | 599044 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3458883261 -assert nopostproc +UVM_T ESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.xbar_access_same_device_slow_rsp.3458883261 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/27.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/27.xbar_error_and_unmapped_addr.420121235 |
| Short name | T1646 |
| Test name | |
| Test status | |
| Simulation time | 165627028 ps |
| CPU time | 14.6 seconds |
| Started | Aug 24 05:29:01 AM UTC 24 |
| Finished | Aug 24 05:29:17 AM UTC 24 |
| Peak memory | 597704 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=420121235 -assert nopostproc +UVM_TESTNAME =xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.xbar_error_and_unmapped_addr.420121235 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/27.xbar_error_and_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/27.xbar_error_random.2090667717 |
| Short name | T1648 |
| Test name | |
| Test status | |
| Simulation time | 449890990 ps |
| CPU time | 26.49 seconds |
| Started | Aug 24 05:28:53 AM UTC 24 |
| Finished | Aug 24 05:29:21 AM UTC 24 |
| Peak memory | 597692 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2090667717 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.xbar_error_random.2090667717 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/27.xbar_error_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/27.xbar_random.2142821904 |
| Short name | T1639 |
| Test name | |
| Test status | |
| Simulation time | 301529338 ps |
| CPU time | 10.49 seconds |
| Started | Aug 24 05:28:11 AM UTC 24 |
| Finished | Aug 24 05:28:22 AM UTC 24 |
| Peak memory | 597692 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2142821904 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.xbar_random.2142821904 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/27.xbar_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/27.xbar_random_large_delays.4184737906 |
| Short name | T1720 |
| Test name | |
| Test status | |
| Simulation time | 76287793774 ps |
| CPU time | 611.14 seconds |
| Started | Aug 24 05:28:24 AM UTC 24 |
| Finished | Aug 24 05:38:42 AM UTC 24 |
| Peak memory | 597820 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max _device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4184737906 -assert nopostproc +U VM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.xbar_random_large_delays.4184737906 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/27.xbar_random_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/27.xbar_random_slow_rsp.2124019469 |
| Short name | T1711 |
| Test name | |
| Test status | |
| Simulation time | 42586339601 ps |
| CPU time | 539.96 seconds |
| Started | Aug 24 05:28:37 AM UTC 24 |
| Finished | Aug 24 05:37:43 AM UTC 24 |
| Peak memory | 598112 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2124019469 -assert nopostproc +UVM_T ESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.xbar_random_slow_rsp.2124019469 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/27.xbar_random_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/27.xbar_random_zero_delays.2839178628 |
| Short name | T1641 |
| Test name | |
| Test status | |
| Simulation time | 234163546 ps |
| CPU time | 17.35 seconds |
| Started | Aug 24 05:28:12 AM UTC 24 |
| Finished | Aug 24 05:28:30 AM UTC 24 |
| Peak memory | 597700 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2839178628 -assert nopostpr oc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.xbar_random_zero_delays.2839178628 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/27.xbar_random_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/27.xbar_same_source.3728903453 |
| Short name | T1651 |
| Test name | |
| Test status | |
| Simulation time | 2366919077 ps |
| CPU time | 52.58 seconds |
| Started | Aug 24 05:28:50 AM UTC 24 |
| Finished | Aug 24 05:29:44 AM UTC 24 |
| Peak memory | 597752 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3728903453 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.xbar_same_source.3728903453 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/27.xbar_same_source/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/27.xbar_smoke.4080226300 |
| Short name | T1635 |
| Test name | |
| Test status | |
| Simulation time | 221302965 ps |
| CPU time | 7.27 seconds |
| Started | Aug 24 05:27:48 AM UTC 24 |
| Finished | Aug 24 05:27:57 AM UTC 24 |
| Peak memory | 595628 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4080226300 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 8_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.xbar_smoke.4080226300 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/27.xbar_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/27.xbar_smoke_large_delays.3545729881 |
| Short name | T1649 |
| Test name | |
| Test status | |
| Simulation time | 9382591397 ps |
| CPU time | 79.62 seconds |
| Started | Aug 24 05:28:07 AM UTC 24 |
| Finished | Aug 24 05:29:28 AM UTC 24 |
| Peak memory | 595764 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max _device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3545729881 -assert nopostproc +U VM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.xbar_smoke_large_delays.3545729881 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/27.xbar_smoke_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/27.xbar_smoke_slow_rsp.130906140 |
| Short name | T1647 |
| Test name | |
| Test status | |
| Simulation time | 5741736169 ps |
| CPU time | 67.41 seconds |
| Started | Aug 24 05:28:11 AM UTC 24 |
| Finished | Aug 24 05:29:20 AM UTC 24 |
| Peak memory | 595768 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=130906140 -assert nopostproc +UVM_TE STNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.xbar_smoke_slow_rsp.130906140 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/27.xbar_smoke_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/27.xbar_smoke_zero_delays.4175731661 |
| Short name | T1638 |
| Test name | |
| Test status | |
| Simulation time | 50488017 ps |
| CPU time | 5.09 seconds |
| Started | Aug 24 05:28:04 AM UTC 24 |
| Finished | Aug 24 05:28:10 AM UTC 24 |
| Peak memory | 595696 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4175731661 -assert nopostpr oc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.xbar_smoke_zero_delays.4175731661 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/27.xbar_smoke_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/27.xbar_stress_all.2432147271 |
| Short name | T1655 |
| Test name | |
| Test status | |
| Simulation time | 734208498 ps |
| CPU time | 47.98 seconds |
| Started | Aug 24 05:29:19 AM UTC 24 |
| Finished | Aug 24 05:30:08 AM UTC 24 |
| Peak memory | 597760 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2432147271 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.xbar_stress_all.2432147271 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/27.xbar_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/27.xbar_stress_all_with_reset_error.4037668352 |
| Short name | T1654 |
| Test name | |
| Test status | |
| Simulation time | 55003595 ps |
| CPU time | 24.22 seconds |
| Started | Aug 24 05:29:34 AM UTC 24 |
| Finished | Aug 24 05:30:00 AM UTC 24 |
| Peak memory | 597760 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4037668352 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.xbar_stress_all_with_reset_error.4037668352 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/27.xbar_stress_all_with_reset_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/27.xbar_unmapped_addr.2010533088 |
| Short name | T1650 |
| Test name | |
| Test status | |
| Simulation time | 1326731524 ps |
| CPU time | 41.62 seconds |
| Started | Aug 24 05:28:56 AM UTC 24 |
| Finished | Aug 24 05:29:39 AM UTC 24 |
| Peak memory | 597692 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2010533088 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.xbar_unmapped_addr.2010533088 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/27.xbar_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/28.chip_tl_errors.579150548 |
| Short name | T1672 |
| Test name | |
| Test status | |
| Simulation time | 3576250850 ps |
| CPU time | 171.97 seconds |
| Started | Aug 24 05:29:35 AM UTC 24 |
| Finished | Aug 24 05:32:30 AM UTC 24 |
| Peak memory | 613152 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enable d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=579150548 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.chip_tl_errors.579150548 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/28.chip_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/28.xbar_access_same_device.3569671136 |
| Short name | T1666 |
| Test name | |
| Test status | |
| Simulation time | 2218293912 ps |
| CPU time | 74.63 seconds |
| Started | Aug 24 05:30:42 AM UTC 24 |
| Finished | Aug 24 05:31:58 AM UTC 24 |
| Peak memory | 598052 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3569671136 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.xbar_access_same_device.3569671136 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/28.xbar_access_same_device/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/28.xbar_access_same_device_slow_rsp.2413271267 |
| Short name | T1777 |
| Test name | |
| Test status | |
| Simulation time | 77706334891 ps |
| CPU time | 898.33 seconds |
| Started | Aug 24 05:30:54 AM UTC 24 |
| Finished | Aug 24 05:46:02 AM UTC 24 |
| Peak memory | 599044 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2413271267 -assert nopostproc +UVM_T ESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.xbar_access_same_device_slow_rsp.2413271267 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/28.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/28.xbar_error_and_unmapped_addr.3501929717 |
| Short name | T1663 |
| Test name | |
| Test status | |
| Simulation time | 217304111 ps |
| CPU time | 18.4 seconds |
| Started | Aug 24 05:31:16 AM UTC 24 |
| Finished | Aug 24 05:31:36 AM UTC 24 |
| Peak memory | 597840 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3501929717 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.xbar_error_and_unmapped_addr.3501929717 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/28.xbar_error_and_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/28.xbar_error_random.2998675747 |
| Short name | T1662 |
| Test name | |
| Test status | |
| Simulation time | 441598476 ps |
| CPU time | 26.1 seconds |
| Started | Aug 24 05:31:05 AM UTC 24 |
| Finished | Aug 24 05:31:32 AM UTC 24 |
| Peak memory | 597692 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2998675747 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.xbar_error_random.2998675747 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/28.xbar_error_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/28.xbar_random.1899320684 |
| Short name | T528 |
| Test name | |
| Test status | |
| Simulation time | 1585039499 ps |
| CPU time | 41.31 seconds |
| Started | Aug 24 05:30:13 AM UTC 24 |
| Finished | Aug 24 05:30:56 AM UTC 24 |
| Peak memory | 597544 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1899320684 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.xbar_random.1899320684 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/28.xbar_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/28.xbar_random_large_delays.606410920 |
| Short name | T1661 |
| Test name | |
| Test status | |
| Simulation time | 6801806003 ps |
| CPU time | 60.14 seconds |
| Started | Aug 24 05:30:23 AM UTC 24 |
| Finished | Aug 24 05:31:24 AM UTC 24 |
| Peak memory | 596028 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max _device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=606410920 -assert nopostproc +UV M_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.xbar_random_large_delays.606410920 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/28.xbar_random_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/28.xbar_random_slow_rsp.4167125595 |
| Short name | T1670 |
| Test name | |
| Test status | |
| Simulation time | 7225880071 ps |
| CPU time | 90.41 seconds |
| Started | Aug 24 05:30:40 AM UTC 24 |
| Finished | Aug 24 05:32:12 AM UTC 24 |
| Peak memory | 598068 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4167125595 -assert nopostproc +UVM_T ESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.xbar_random_slow_rsp.4167125595 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/28.xbar_random_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/28.xbar_random_zero_delays.928261320 |
| Short name | T1657 |
| Test name | |
| Test status | |
| Simulation time | 172619729 ps |
| CPU time | 12.71 seconds |
| Started | Aug 24 05:30:13 AM UTC 24 |
| Finished | Aug 24 05:30:27 AM UTC 24 |
| Peak memory | 597380 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=928261320 -assert nopostpro c +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.xbar_random_zero_delays.928261320 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/28.xbar_random_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/28.xbar_same_source.731202956 |
| Short name | T1664 |
| Test name | |
| Test status | |
| Simulation time | 1986376720 ps |
| CPU time | 43.71 seconds |
| Started | Aug 24 05:30:57 AM UTC 24 |
| Finished | Aug 24 05:31:42 AM UTC 24 |
| Peak memory | 597696 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=731202956 -assert nopostproc +UVM_TESTNAME =xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.xbar_same_source.731202956 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/28.xbar_same_source/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/28.xbar_smoke.500965579 |
| Short name | T1652 |
| Test name | |
| Test status | |
| Simulation time | 46423943 ps |
| CPU time | 5.37 seconds |
| Started | Aug 24 05:29:42 AM UTC 24 |
| Finished | Aug 24 05:29:49 AM UTC 24 |
| Peak memory | 595632 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=500965579 -assert nopostproc +UVM_TESTNAME =xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08 _22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.xbar_smoke.500965579 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/28.xbar_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/28.xbar_smoke_large_delays.423844504 |
| Short name | T1659 |
| Test name | |
| Test status | |
| Simulation time | 7404143728 ps |
| CPU time | 62.28 seconds |
| Started | Aug 24 05:29:58 AM UTC 24 |
| Finished | Aug 24 05:31:02 AM UTC 24 |
| Peak memory | 595768 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max _device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=423844504 -assert nopostproc +UV M_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.xbar_smoke_large_delays.423844504 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/28.xbar_smoke_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/28.xbar_smoke_slow_rsp.3784411420 |
| Short name | T1660 |
| Test name | |
| Test status | |
| Simulation time | 5108590860 ps |
| CPU time | 59.66 seconds |
| Started | Aug 24 05:30:03 AM UTC 24 |
| Finished | Aug 24 05:31:04 AM UTC 24 |
| Peak memory | 595772 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3784411420 -assert nopostproc +UVM_T ESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.xbar_smoke_slow_rsp.3784411420 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/28.xbar_smoke_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/28.xbar_smoke_zero_delays.613041751 |
| Short name | T1653 |
| Test name | |
| Test status | |
| Simulation time | 49155651 ps |
| CPU time | 5.26 seconds |
| Started | Aug 24 05:29:53 AM UTC 24 |
| Finished | Aug 24 05:29:59 AM UTC 24 |
| Peak memory | 595696 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=613041751 -assert nopostpro c +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.xbar_smoke_zero_delays.613041751 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/28.xbar_smoke_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/28.xbar_stress_all.4064146254 |
| Short name | T1667 |
| Test name | |
| Test status | |
| Simulation time | 601904765 ps |
| CPU time | 39.64 seconds |
| Started | Aug 24 05:31:19 AM UTC 24 |
| Finished | Aug 24 05:32:00 AM UTC 24 |
| Peak memory | 597692 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4064146254 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.xbar_stress_all.4064146254 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/28.xbar_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/28.xbar_stress_all_with_error.2091097634 |
| Short name | T1690 |
| Test name | |
| Test status | |
| Simulation time | 5682189916 ps |
| CPU time | 153.76 seconds |
| Started | Aug 24 05:31:43 AM UTC 24 |
| Finished | Aug 24 05:34:19 AM UTC 24 |
| Peak memory | 597888 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2091097634 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.xbar_stress_all_with_error.2091097634 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/28.xbar_stress_all_with_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/28.xbar_stress_all_with_rand_reset.1052188168 |
| Short name | T1669 |
| Test name | |
| Test status | |
| Simulation time | 115216209 ps |
| CPU time | 29.52 seconds |
| Started | Aug 24 05:31:38 AM UTC 24 |
| Finished | Aug 24 05:32:09 AM UTC 24 |
| Peak memory | 597752 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1052188168 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.xbar_stress_all_with_rand_reset.1052188168 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/28.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/28.xbar_stress_all_with_reset_error.413773849 |
| Short name | T1677 |
| Test name | |
| Test status | |
| Simulation time | 258242583 ps |
| CPU time | 67.27 seconds |
| Started | Aug 24 05:31:46 AM UTC 24 |
| Finished | Aug 24 05:32:55 AM UTC 24 |
| Peak memory | 597748 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=413773849 -assert nopostproc +UVM_TESTNAME =xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.xbar_stress_all_with_reset_error.413773849 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/28.xbar_stress_all_with_reset_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/28.xbar_unmapped_addr.3946128141 |
| Short name | T1665 |
| Test name | |
| Test status | |
| Simulation time | 1414385346 ps |
| CPU time | 42.83 seconds |
| Started | Aug 24 05:31:11 AM UTC 24 |
| Finished | Aug 24 05:31:55 AM UTC 24 |
| Peak memory | 597756 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3946128141 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.xbar_unmapped_addr.3946128141 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/28.xbar_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/29.chip_tl_errors.1388777915 |
| Short name | T1689 |
| Test name | |
| Test status | |
| Simulation time | 3989879368 ps |
| CPU time | 137.32 seconds |
| Started | Aug 24 05:31:49 AM UTC 24 |
| Finished | Aug 24 05:34:09 AM UTC 24 |
| Peak memory | 623320 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enable d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1388777915 -assert nopostpro c +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.chip_tl_errors.1388777915 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/29.chip_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/29.xbar_access_same_device.2011458790 |
| Short name | T1678 |
| Test name | |
| Test status | |
| Simulation time | 594287798 ps |
| CPU time | 32.7 seconds |
| Started | Aug 24 05:32:30 AM UTC 24 |
| Finished | Aug 24 05:33:04 AM UTC 24 |
| Peak memory | 597768 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2011458790 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.xbar_access_same_device.2011458790 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/29.xbar_access_same_device/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/29.xbar_access_same_device_slow_rsp.1164367505 |
| Short name | T1702 |
| Test name | |
| Test status | |
| Simulation time | 18306760930 ps |
| CPU time | 211.8 seconds |
| Started | Aug 24 05:32:44 AM UTC 24 |
| Finished | Aug 24 05:36:19 AM UTC 24 |
| Peak memory | 598204 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1164367505 -assert nopostproc +UVM_T ESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.xbar_access_same_device_slow_rsp.1164367505 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/29.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/29.xbar_error_and_unmapped_addr.427233239 |
| Short name | T1684 |
| Test name | |
| Test status | |
| Simulation time | 28621769 ps |
| CPU time | 4.99 seconds |
| Started | Aug 24 05:33:05 AM UTC 24 |
| Finished | Aug 24 05:33:11 AM UTC 24 |
| Peak memory | 595644 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=427233239 -assert nopostproc +UVM_TESTNAME =xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.xbar_error_and_unmapped_addr.427233239 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/29.xbar_error_and_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/29.xbar_error_random.2359074293 |
| Short name | T1680 |
| Test name | |
| Test status | |
| Simulation time | 568184293 ps |
| CPU time | 17 seconds |
| Started | Aug 24 05:32:48 AM UTC 24 |
| Finished | Aug 24 05:33:06 AM UTC 24 |
| Peak memory | 597688 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2359074293 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.xbar_error_random.2359074293 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/29.xbar_error_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/29.xbar_random.3638901239 |
| Short name | T1676 |
| Test name | |
| Test status | |
| Simulation time | 562765239 ps |
| CPU time | 33.33 seconds |
| Started | Aug 24 05:32:17 AM UTC 24 |
| Finished | Aug 24 05:32:51 AM UTC 24 |
| Peak memory | 597696 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3638901239 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.xbar_random.3638901239 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/29.xbar_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/29.xbar_random_large_delays.3421709279 |
| Short name | T1738 |
| Test name | |
| Test status | |
| Simulation time | 62668632301 ps |
| CPU time | 532.09 seconds |
| Started | Aug 24 05:32:23 AM UTC 24 |
| Finished | Aug 24 05:41:21 AM UTC 24 |
| Peak memory | 597828 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max _device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3421709279 -assert nopostproc +U VM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.xbar_random_large_delays.3421709279 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/29.xbar_random_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/29.xbar_random_slow_rsp.1503266890 |
| Short name | T1722 |
| Test name | |
| Test status | |
| Simulation time | 32837151330 ps |
| CPU time | 380.96 seconds |
| Started | Aug 24 05:32:26 AM UTC 24 |
| Finished | Aug 24 05:38:51 AM UTC 24 |
| Peak memory | 597820 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1503266890 -assert nopostproc +UVM_T ESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.xbar_random_slow_rsp.1503266890 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/29.xbar_random_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/29.xbar_random_zero_delays.1397179843 |
| Short name | T1675 |
| Test name | |
| Test status | |
| Simulation time | 236301216 ps |
| CPU time | 17.24 seconds |
| Started | Aug 24 05:32:19 AM UTC 24 |
| Finished | Aug 24 05:32:38 AM UTC 24 |
| Peak memory | 597840 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1397179843 -assert nopostpr oc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.xbar_random_zero_delays.1397179843 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/29.xbar_random_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/29.xbar_same_source.3217138279 |
| Short name | T1683 |
| Test name | |
| Test status | |
| Simulation time | 421232138 ps |
| CPU time | 22.46 seconds |
| Started | Aug 24 05:32:45 AM UTC 24 |
| Finished | Aug 24 05:33:09 AM UTC 24 |
| Peak memory | 597692 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3217138279 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.xbar_same_source.3217138279 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/29.xbar_same_source/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/29.xbar_smoke.357731685 |
| Short name | T1668 |
| Test name | |
| Test status | |
| Simulation time | 187878871 ps |
| CPU time | 6.99 seconds |
| Started | Aug 24 05:31:57 AM UTC 24 |
| Finished | Aug 24 05:32:05 AM UTC 24 |
| Peak memory | 595880 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=357731685 -assert nopostproc +UVM_TESTNAME =xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08 _22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.xbar_smoke.357731685 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/29.xbar_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/29.xbar_smoke_large_delays.1684267677 |
| Short name | T1681 |
| Test name | |
| Test status | |
| Simulation time | 6489612225 ps |
| CPU time | 53.43 seconds |
| Started | Aug 24 05:32:13 AM UTC 24 |
| Finished | Aug 24 05:33:07 AM UTC 24 |
| Peak memory | 595764 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max _device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1684267677 -assert nopostproc +U VM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.xbar_smoke_large_delays.1684267677 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/29.xbar_smoke_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/29.xbar_smoke_slow_rsp.2919649846 |
| Short name | T1682 |
| Test name | |
| Test status | |
| Simulation time | 4494106700 ps |
| CPU time | 54.02 seconds |
| Started | Aug 24 05:32:14 AM UTC 24 |
| Finished | Aug 24 05:33:09 AM UTC 24 |
| Peak memory | 595768 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2919649846 -assert nopostproc +UVM_T ESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.xbar_smoke_slow_rsp.2919649846 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/29.xbar_smoke_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/29.xbar_smoke_zero_delays.1619811833 |
| Short name | T1671 |
| Test name | |
| Test status | |
| Simulation time | 51811334 ps |
| CPU time | 5.15 seconds |
| Started | Aug 24 05:32:10 AM UTC 24 |
| Finished | Aug 24 05:32:16 AM UTC 24 |
| Peak memory | 595856 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1619811833 -assert nopostpr oc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.xbar_smoke_zero_delays.1619811833 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/29.xbar_smoke_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/29.xbar_stress_all.2486978828 |
| Short name | T1706 |
| Test name | |
| Test status | |
| Simulation time | 8136096609 ps |
| CPU time | 240.58 seconds |
| Started | Aug 24 05:33:10 AM UTC 24 |
| Finished | Aug 24 05:37:13 AM UTC 24 |
| Peak memory | 597952 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2486978828 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.xbar_stress_all.2486978828 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/29.xbar_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/29.xbar_stress_all_with_error.3663240699 |
| Short name | T1708 |
| Test name | |
| Test status | |
| Simulation time | 9936236911 ps |
| CPU time | 246.16 seconds |
| Started | Aug 24 05:33:19 AM UTC 24 |
| Finished | Aug 24 05:37:28 AM UTC 24 |
| Peak memory | 597824 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3663240699 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.xbar_stress_all_with_error.3663240699 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/29.xbar_stress_all_with_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/29.xbar_stress_all_with_rand_reset.2703358431 |
| Short name | T1721 |
| Test name | |
| Test status | |
| Simulation time | 867060431 ps |
| CPU time | 323.24 seconds |
| Started | Aug 24 05:33:18 AM UTC 24 |
| Finished | Aug 24 05:38:45 AM UTC 24 |
| Peak memory | 597840 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2703358431 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.xbar_stress_all_with_rand_reset.2703358431 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/29.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/29.xbar_stress_all_with_reset_error.3043935615 |
| Short name | T1688 |
| Test name | |
| Test status | |
| Simulation time | 227001883 ps |
| CPU time | 47.02 seconds |
| Started | Aug 24 05:33:20 AM UTC 24 |
| Finished | Aug 24 05:34:08 AM UTC 24 |
| Peak memory | 597820 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3043935615 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.xbar_stress_all_with_reset_error.3043935615 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/29.xbar_stress_all_with_reset_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/29.xbar_unmapped_addr.2580110186 |
| Short name | T1679 |
| Test name | |
| Test status | |
| Simulation time | 299874923 ps |
| CPU time | 11.96 seconds |
| Started | Aug 24 05:32:52 AM UTC 24 |
| Finished | Aug 24 05:33:05 AM UTC 24 |
| Peak memory | 597688 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2580110186 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.xbar_unmapped_addr.2580110186 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/29.xbar_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/3.chip_csr_aliasing.3631963189 |
| Short name | T2066 |
| Test name | |
| Test status | |
| Simulation time | 66361756242 ps |
| CPU time | 8041.57 seconds |
| Started | Aug 24 03:59:45 AM UTC 24 |
| Finished | Aug 24 06:15:07 AM UTC 24 |
| Peak memory | 665312 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +test_timeout_ns=120_000_000 +csr_aliasing +en_scb=0 + stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=3631963189 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.chip_ csr_aliasing.3631963189 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/3.chip_csr_aliasing/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/3.chip_csr_bit_bash.1828097251 |
| Short name | T1367 |
| Test name | |
| Test status | |
| Simulation time | 9351491860 ps |
| CPU time | 706.46 seconds |
| Started | Aug 24 03:59:44 AM UTC 24 |
| Finished | Aug 24 04:11:39 AM UTC 24 |
| Peak memory | 619544 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +test_timeout_ns=120_000_000 +num_test_csrs=200 +csr_b it_bash +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/to ols/sim.tcl +ntb_random_seed=1828097251 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/nu ll -cm_name 3.chip_csr_bit_bash.1828097251 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/3.chip_csr_bit_bash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/3.chip_csr_mem_rw_with_rand_reset.4179016752 |
| Short name | T425 |
| Test name | |
| Test status | |
| Simulation time | 12116512138 ps |
| CPU time | 730.7 seconds |
| Started | Aug 24 04:03:28 AM UTC 24 |
| Finished | Aug 24 04:15:47 AM UTC 24 |
| Peak memory | 672600 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000 000000 +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/too ls/sim.tcl +ntb_random_seed=4179016752 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/nul l -cm_name 3.chip_csr_mem_rw_with_rand_reset.4179016752 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/3.chip_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/3.chip_same_csr_outstanding.1821580421 |
| Short name | T422 |
| Test name | |
| Test status | |
| Simulation time | 32020961420 ps |
| CPU time | 2639.98 seconds |
| Started | Aug 24 03:59:47 AM UTC 24 |
| Finished | Aug 24 04:44:14 AM UTC 24 |
| Peak memory | 614008 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +test_timeout_ns=120_000_000 +run_same_csr_outstanding +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim .tcl +ntb_random_seed=1821580421 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_ name 3.chip_same_csr_outstanding.1821580421 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/3.chip_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/3.chip_tl_errors.2517558064 |
| Short name | T555 |
| Test name | |
| Test status | |
| Simulation time | 3468875738 ps |
| CPU time | 168.75 seconds |
| Started | Aug 24 03:59:53 AM UTC 24 |
| Finished | Aug 24 04:02:45 AM UTC 24 |
| Peak memory | 623324 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enable d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2517558064 -assert nopostpro c +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.chip_tl_errors.2517558064 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/3.chip_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/3.xbar_access_same_device.1380870630 |
| Short name | T801 |
| Test name | |
| Test status | |
| Simulation time | 3053750825 ps |
| CPU time | 91.62 seconds |
| Started | Aug 24 04:01:51 AM UTC 24 |
| Finished | Aug 24 04:03:24 AM UTC 24 |
| Peak memory | 597768 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1380870630 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.xbar_access_same_device.1380870630 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/3.xbar_access_same_device/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/3.xbar_error_and_unmapped_addr.2369364876 |
| Short name | T662 |
| Test name | |
| Test status | |
| Simulation time | 223144837 ps |
| CPU time | 19.12 seconds |
| Started | Aug 24 04:02:24 AM UTC 24 |
| Finished | Aug 24 04:02:44 AM UTC 24 |
| Peak memory | 597696 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2369364876 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.xbar_error_and_unmapped_addr.2369364876 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/3.xbar_error_and_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/3.xbar_error_random.3005293523 |
| Short name | T1355 |
| Test name | |
| Test status | |
| Simulation time | 1615556117 ps |
| CPU time | 37.86 seconds |
| Started | Aug 24 04:02:07 AM UTC 24 |
| Finished | Aug 24 04:02:47 AM UTC 24 |
| Peak memory | 597692 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3005293523 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.xbar_error_random.3005293523 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/3.xbar_error_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/3.xbar_random.2671887899 |
| Short name | T579 |
| Test name | |
| Test status | |
| Simulation time | 102678513 ps |
| CPU time | 10.55 seconds |
| Started | Aug 24 04:01:08 AM UTC 24 |
| Finished | Aug 24 04:01:19 AM UTC 24 |
| Peak memory | 597692 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2671887899 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.xbar_random.2671887899 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/3.xbar_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/3.xbar_random_large_delays.589717646 |
| Short name | T587 |
| Test name | |
| Test status | |
| Simulation time | 43074191915 ps |
| CPU time | 344.21 seconds |
| Started | Aug 24 04:01:34 AM UTC 24 |
| Finished | Aug 24 04:07:22 AM UTC 24 |
| Peak memory | 597820 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max _device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=589717646 -assert nopostproc +UV M_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.xbar_random_large_delays.589717646 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/3.xbar_random_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/3.xbar_random_slow_rsp.60313789 |
| Short name | T475 |
| Test name | |
| Test status | |
| Simulation time | 69760968451 ps |
| CPU time | 906.57 seconds |
| Started | Aug 24 04:01:47 AM UTC 24 |
| Finished | Aug 24 04:17:03 AM UTC 24 |
| Peak memory | 598096 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=60313789 -assert nopostproc +UVM_TES TNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.xbar_random_slow_rsp.60313789 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/3.xbar_random_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/3.xbar_random_zero_delays.244835888 |
| Short name | T465 |
| Test name | |
| Test status | |
| Simulation time | 572434393 ps |
| CPU time | 38.57 seconds |
| Started | Aug 24 04:01:13 AM UTC 24 |
| Finished | Aug 24 04:01:53 AM UTC 24 |
| Peak memory | 597760 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=244835888 -assert nopostpro c +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.xbar_random_zero_delays.244835888 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/3.xbar_random_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/3.xbar_same_source.2724532800 |
| Short name | T518 |
| Test name | |
| Test status | |
| Simulation time | 360803832 ps |
| CPU time | 22.26 seconds |
| Started | Aug 24 04:02:00 AM UTC 24 |
| Finished | Aug 24 04:02:24 AM UTC 24 |
| Peak memory | 597692 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2724532800 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.xbar_same_source.2724532800 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/3.xbar_same_source/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/3.xbar_smoke.1495076640 |
| Short name | T1352 |
| Test name | |
| Test status | |
| Simulation time | 40562280 ps |
| CPU time | 5.13 seconds |
| Started | Aug 24 04:00:10 AM UTC 24 |
| Finished | Aug 24 04:00:16 AM UTC 24 |
| Peak memory | 595692 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1495076640 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 8_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.xbar_smoke.1495076640 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/3.xbar_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/3.xbar_smoke_large_delays.245204802 |
| Short name | T1353 |
| Test name | |
| Test status | |
| Simulation time | 7539436438 ps |
| CPU time | 60.98 seconds |
| Started | Aug 24 04:00:30 AM UTC 24 |
| Finished | Aug 24 04:01:33 AM UTC 24 |
| Peak memory | 595900 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max _device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=245204802 -assert nopostproc +UV M_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.xbar_smoke_large_delays.245204802 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/3.xbar_smoke_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/3.xbar_smoke_slow_rsp.3021399479 |
| Short name | T617 |
| Test name | |
| Test status | |
| Simulation time | 3793105014 ps |
| CPU time | 48.54 seconds |
| Started | Aug 24 04:00:47 AM UTC 24 |
| Finished | Aug 24 04:01:37 AM UTC 24 |
| Peak memory | 595704 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3021399479 -assert nopostproc +UVM_T ESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.xbar_smoke_slow_rsp.3021399479 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/3.xbar_smoke_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/3.xbar_smoke_zero_delays.3421243368 |
| Short name | T482 |
| Test name | |
| Test status | |
| Simulation time | 51546654 ps |
| CPU time | 5.3 seconds |
| Started | Aug 24 04:00:25 AM UTC 24 |
| Finished | Aug 24 04:00:32 AM UTC 24 |
| Peak memory | 595636 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3421243368 -assert nopostpr oc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.xbar_smoke_zero_delays.3421243368 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/3.xbar_smoke_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/3.xbar_stress_all_with_error.2700678252 |
| Short name | T802 |
| Test name | |
| Test status | |
| Simulation time | 1562138572 ps |
| CPU time | 87.04 seconds |
| Started | Aug 24 04:02:58 AM UTC 24 |
| Finished | Aug 24 04:04:27 AM UTC 24 |
| Peak memory | 597704 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2700678252 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.xbar_stress_all_with_error.2700678252 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/3.xbar_stress_all_with_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/3.xbar_stress_all_with_rand_reset.2588786084 |
| Short name | T864 |
| Test name | |
| Test status | |
| Simulation time | 89953411 ps |
| CPU time | 75.46 seconds |
| Started | Aug 24 04:02:49 AM UTC 24 |
| Finished | Aug 24 04:04:06 AM UTC 24 |
| Peak memory | 597832 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2588786084 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.xbar_stress_all_with_rand_reset.2588786084 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/3.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/3.xbar_unmapped_addr.1338828056 |
| Short name | T1354 |
| Test name | |
| Test status | |
| Simulation time | 580650806 ps |
| CPU time | 20.37 seconds |
| Started | Aug 24 04:02:13 AM UTC 24 |
| Finished | Aug 24 04:02:34 AM UTC 24 |
| Peak memory | 597692 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1338828056 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.xbar_unmapped_addr.1338828056 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/3.xbar_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/30.xbar_access_same_device.532227213 |
| Short name | T1700 |
| Test name | |
| Test status | |
| Simulation time | 2265112521 ps |
| CPU time | 70.8 seconds |
| Started | Aug 24 05:34:22 AM UTC 24 |
| Finished | Aug 24 05:35:35 AM UTC 24 |
| Peak memory | 598080 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=532227213 -assert nopostproc +UVM_TESTNAME =xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.xbar_access_same_device.532227213 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/30.xbar_access_same_device/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/30.xbar_error_and_unmapped_addr.407278094 |
| Short name | T1697 |
| Test name | |
| Test status | |
| Simulation time | 925595318 ps |
| CPU time | 26.47 seconds |
| Started | Aug 24 05:34:44 AM UTC 24 |
| Finished | Aug 24 05:35:12 AM UTC 24 |
| Peak memory | 597944 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=407278094 -assert nopostproc +UVM_TESTNAME =xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.xbar_error_and_unmapped_addr.407278094 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/30.xbar_error_and_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/30.xbar_error_random.3714263825 |
| Short name | T1698 |
| Test name | |
| Test status | |
| Simulation time | 581926119 ps |
| CPU time | 32.81 seconds |
| Started | Aug 24 05:34:38 AM UTC 24 |
| Finished | Aug 24 05:35:12 AM UTC 24 |
| Peak memory | 597756 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3714263825 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.xbar_error_random.3714263825 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/30.xbar_error_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/30.xbar_random.2674823759 |
| Short name | T1687 |
| Test name | |
| Test status | |
| Simulation time | 114239839 ps |
| CPU time | 9.68 seconds |
| Started | Aug 24 05:33:44 AM UTC 24 |
| Finished | Aug 24 05:33:55 AM UTC 24 |
| Peak memory | 597696 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2674823759 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.xbar_random.2674823759 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/30.xbar_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/30.xbar_random_large_delays.1450393988 |
| Short name | T1759 |
| Test name | |
| Test status | |
| Simulation time | 67298741846 ps |
| CPU time | 567.97 seconds |
| Started | Aug 24 05:33:48 AM UTC 24 |
| Finished | Aug 24 05:43:23 AM UTC 24 |
| Peak memory | 597816 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max _device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1450393988 -assert nopostproc +U VM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.xbar_random_large_delays.1450393988 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/30.xbar_random_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/30.xbar_random_slow_rsp.1542325265 |
| Short name | T1704 |
| Test name | |
| Test status | |
| Simulation time | 14602103647 ps |
| CPU time | 166.46 seconds |
| Started | Aug 24 05:34:09 AM UTC 24 |
| Finished | Aug 24 05:36:58 AM UTC 24 |
| Peak memory | 597900 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1542325265 -assert nopostproc +UVM_T ESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.xbar_random_slow_rsp.1542325265 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/30.xbar_random_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/30.xbar_random_zero_delays.76275830 |
| Short name | T1691 |
| Test name | |
| Test status | |
| Simulation time | 611299417 ps |
| CPU time | 38.95 seconds |
| Started | Aug 24 05:33:44 AM UTC 24 |
| Finished | Aug 24 05:34:24 AM UTC 24 |
| Peak memory | 597908 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=76275830 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.xbar_random_zero_delays.76275830 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/30.xbar_random_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/30.xbar_same_source.2758841991 |
| Short name | T1694 |
| Test name | |
| Test status | |
| Simulation time | 243652499 ps |
| CPU time | 16.24 seconds |
| Started | Aug 24 05:34:33 AM UTC 24 |
| Finished | Aug 24 05:34:51 AM UTC 24 |
| Peak memory | 597688 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2758841991 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.xbar_same_source.2758841991 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/30.xbar_same_source/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/30.xbar_smoke.1247253528 |
| Short name | T1686 |
| Test name | |
| Test status | |
| Simulation time | 163565485 ps |
| CPU time | 6.74 seconds |
| Started | Aug 24 05:33:22 AM UTC 24 |
| Finished | Aug 24 05:33:30 AM UTC 24 |
| Peak memory | 595848 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1247253528 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 8_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.xbar_smoke.1247253528 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/30.xbar_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/30.xbar_smoke_large_delays.3684304707 |
| Short name | T1692 |
| Test name | |
| Test status | |
| Simulation time | 7679521298 ps |
| CPU time | 63.3 seconds |
| Started | Aug 24 05:33:24 AM UTC 24 |
| Finished | Aug 24 05:34:29 AM UTC 24 |
| Peak memory | 596016 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max _device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3684304707 -assert nopostproc +U VM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.xbar_smoke_large_delays.3684304707 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/30.xbar_smoke_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/30.xbar_smoke_slow_rsp.3355833493 |
| Short name | T1693 |
| Test name | |
| Test status | |
| Simulation time | 5448475910 ps |
| CPU time | 62.63 seconds |
| Started | Aug 24 05:33:26 AM UTC 24 |
| Finished | Aug 24 05:34:30 AM UTC 24 |
| Peak memory | 595760 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3355833493 -assert nopostproc +UVM_T ESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.xbar_smoke_slow_rsp.3355833493 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/30.xbar_smoke_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/30.xbar_smoke_zero_delays.2004982766 |
| Short name | T1685 |
| Test name | |
| Test status | |
| Simulation time | 54971608 ps |
| CPU time | 5.65 seconds |
| Started | Aug 24 05:33:23 AM UTC 24 |
| Finished | Aug 24 05:33:29 AM UTC 24 |
| Peak memory | 595764 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2004982766 -assert nopostpr oc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.xbar_smoke_zero_delays.2004982766 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/30.xbar_smoke_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/30.xbar_stress_all.3985131112 |
| Short name | T1726 |
| Test name | |
| Test status | |
| Simulation time | 9664560780 ps |
| CPU time | 255.73 seconds |
| Started | Aug 24 05:35:05 AM UTC 24 |
| Finished | Aug 24 05:39:24 AM UTC 24 |
| Peak memory | 597824 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3985131112 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.xbar_stress_all.3985131112 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/30.xbar_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/30.xbar_stress_all_with_rand_reset.1730762521 |
| Short name | T536 |
| Test name | |
| Test status | |
| Simulation time | 3619982347 ps |
| CPU time | 109.05 seconds |
| Started | Aug 24 05:35:07 AM UTC 24 |
| Finished | Aug 24 05:36:58 AM UTC 24 |
| Peak memory | 597756 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1730762521 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.xbar_stress_all_with_rand_reset.1730762521 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/30.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/30.xbar_unmapped_addr.3756621445 |
| Short name | T1696 |
| Test name | |
| Test status | |
| Simulation time | 148346834 ps |
| CPU time | 14.44 seconds |
| Started | Aug 24 05:34:43 AM UTC 24 |
| Finished | Aug 24 05:34:59 AM UTC 24 |
| Peak memory | 597692 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3756621445 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.xbar_unmapped_addr.3756621445 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/30.xbar_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/31.xbar_access_same_device.3019269046 |
| Short name | T1710 |
| Test name | |
| Test status | |
| Simulation time | 166979941 ps |
| CPU time | 13.5 seconds |
| Started | Aug 24 05:37:27 AM UTC 24 |
| Finished | Aug 24 05:37:42 AM UTC 24 |
| Peak memory | 597928 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3019269046 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.xbar_access_same_device.3019269046 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/31.xbar_access_same_device/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/31.xbar_access_same_device_slow_rsp.4190920793 |
| Short name | T1788 |
| Test name | |
| Test status | |
| Simulation time | 48175499920 ps |
| CPU time | 599.61 seconds |
| Started | Aug 24 05:37:27 AM UTC 24 |
| Finished | Aug 24 05:47:34 AM UTC 24 |
| Peak memory | 597884 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4190920793 -assert nopostproc +UVM_T ESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.xbar_access_same_device_slow_rsp.4190920793 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/31.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/31.xbar_error_and_unmapped_addr.2747518049 |
| Short name | T1714 |
| Test name | |
| Test status | |
| Simulation time | 58814868 ps |
| CPU time | 6.68 seconds |
| Started | Aug 24 05:37:57 AM UTC 24 |
| Finished | Aug 24 05:38:05 AM UTC 24 |
| Peak memory | 597700 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2747518049 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.xbar_error_and_unmapped_addr.2747518049 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/31.xbar_error_and_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/31.xbar_error_random.1879640584 |
| Short name | T1712 |
| Test name | |
| Test status | |
| Simulation time | 97040590 ps |
| CPU time | 8.08 seconds |
| Started | Aug 24 05:37:42 AM UTC 24 |
| Finished | Aug 24 05:37:52 AM UTC 24 |
| Peak memory | 597688 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1879640584 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.xbar_error_random.1879640584 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/31.xbar_error_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/31.xbar_random.465353602 |
| Short name | T1709 |
| Test name | |
| Test status | |
| Simulation time | 2268411300 ps |
| CPU time | 54.99 seconds |
| Started | Aug 24 05:36:34 AM UTC 24 |
| Finished | Aug 24 05:37:31 AM UTC 24 |
| Peak memory | 597756 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=465353602 -assert nopostproc +UVM_TESTNAME =xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 8_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.xbar_random.465353602 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/31.xbar_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/31.xbar_random_large_delays.1441651705 |
| Short name | T1825 |
| Test name | |
| Test status | |
| Simulation time | 103141638913 ps |
| CPU time | 886.07 seconds |
| Started | Aug 24 05:37:12 AM UTC 24 |
| Finished | Aug 24 05:52:07 AM UTC 24 |
| Peak memory | 598788 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max _device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1441651705 -assert nopostproc +U VM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.xbar_random_large_delays.1441651705 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/31.xbar_random_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/31.xbar_random_slow_rsp.1309388966 |
| Short name | T1763 |
| Test name | |
| Test status | |
| Simulation time | 33127129232 ps |
| CPU time | 380.13 seconds |
| Started | Aug 24 05:37:12 AM UTC 24 |
| Finished | Aug 24 05:43:37 AM UTC 24 |
| Peak memory | 597820 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1309388966 -assert nopostproc +UVM_T ESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.xbar_random_slow_rsp.1309388966 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/31.xbar_random_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/31.xbar_random_zero_delays.3509712109 |
| Short name | T1707 |
| Test name | |
| Test status | |
| Simulation time | 62802979 ps |
| CPU time | 6.55 seconds |
| Started | Aug 24 05:37:10 AM UTC 24 |
| Finished | Aug 24 05:37:18 AM UTC 24 |
| Peak memory | 597700 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3509712109 -assert nopostpr oc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.xbar_random_zero_delays.3509712109 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/31.xbar_random_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/31.xbar_same_source.3086871789 |
| Short name | T1713 |
| Test name | |
| Test status | |
| Simulation time | 489738633 ps |
| CPU time | 25.59 seconds |
| Started | Aug 24 05:37:32 AM UTC 24 |
| Finished | Aug 24 05:37:59 AM UTC 24 |
| Peak memory | 598068 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3086871789 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.xbar_same_source.3086871789 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/31.xbar_same_source/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/31.xbar_smoke.2983869444 |
| Short name | T1699 |
| Test name | |
| Test status | |
| Simulation time | 169767575 ps |
| CPU time | 6.11 seconds |
| Started | Aug 24 05:35:27 AM UTC 24 |
| Finished | Aug 24 05:35:34 AM UTC 24 |
| Peak memory | 595912 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2983869444 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 8_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.xbar_smoke.2983869444 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/31.xbar_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/31.xbar_smoke_large_delays.2999278832 |
| Short name | T1703 |
| Test name | |
| Test status | |
| Simulation time | 8224820201 ps |
| CPU time | 65.49 seconds |
| Started | Aug 24 05:35:49 AM UTC 24 |
| Finished | Aug 24 05:36:56 AM UTC 24 |
| Peak memory | 595764 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max _device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2999278832 -assert nopostproc +U VM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.xbar_smoke_large_delays.2999278832 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/31.xbar_smoke_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/31.xbar_smoke_slow_rsp.922819410 |
| Short name | T1705 |
| Test name | |
| Test status | |
| Simulation time | 4703759022 ps |
| CPU time | 61.27 seconds |
| Started | Aug 24 05:36:10 AM UTC 24 |
| Finished | Aug 24 05:37:13 AM UTC 24 |
| Peak memory | 595832 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=922819410 -assert nopostproc +UVM_TE STNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.xbar_smoke_slow_rsp.922819410 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/31.xbar_smoke_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/31.xbar_smoke_zero_delays.1954224425 |
| Short name | T1701 |
| Test name | |
| Test status | |
| Simulation time | 53540818 ps |
| CPU time | 5.27 seconds |
| Started | Aug 24 05:35:48 AM UTC 24 |
| Finished | Aug 24 05:35:55 AM UTC 24 |
| Peak memory | 595636 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1954224425 -assert nopostpr oc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.xbar_smoke_zero_delays.1954224425 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/31.xbar_smoke_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/31.xbar_stress_all.1287380176 |
| Short name | T1735 |
| Test name | |
| Test status | |
| Simulation time | 6124960569 ps |
| CPU time | 169.72 seconds |
| Started | Aug 24 05:37:57 AM UTC 24 |
| Finished | Aug 24 05:40:49 AM UTC 24 |
| Peak memory | 597960 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1287380176 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.xbar_stress_all.1287380176 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/31.xbar_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/31.xbar_stress_all_with_error.2999423117 |
| Short name | T1752 |
| Test name | |
| Test status | |
| Simulation time | 10121963787 ps |
| CPU time | 248.96 seconds |
| Started | Aug 24 05:38:12 AM UTC 24 |
| Finished | Aug 24 05:42:24 AM UTC 24 |
| Peak memory | 597824 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2999423117 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.xbar_stress_all_with_error.2999423117 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/31.xbar_stress_all_with_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/31.xbar_stress_all_with_rand_reset.1006107532 |
| Short name | T841 |
| Test name | |
| Test status | |
| Simulation time | 812338641 ps |
| CPU time | 139.82 seconds |
| Started | Aug 24 05:38:07 AM UTC 24 |
| Finished | Aug 24 05:40:29 AM UTC 24 |
| Peak memory | 597692 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1006107532 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.xbar_stress_all_with_rand_reset.1006107532 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/31.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/31.xbar_stress_all_with_reset_error.974760844 |
| Short name | T1737 |
| Test name | |
| Test status | |
| Simulation time | 2289475870 ps |
| CPU time | 171.15 seconds |
| Started | Aug 24 05:38:14 AM UTC 24 |
| Finished | Aug 24 05:41:07 AM UTC 24 |
| Peak memory | 597816 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=974760844 -assert nopostproc +UVM_TESTNAME =xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.xbar_stress_all_with_reset_error.974760844 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/31.xbar_stress_all_with_reset_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/31.xbar_unmapped_addr.2847428332 |
| Short name | T1716 |
| Test name | |
| Test status | |
| Simulation time | 347692931 ps |
| CPU time | 30.02 seconds |
| Started | Aug 24 05:37:44 AM UTC 24 |
| Finished | Aug 24 05:38:16 AM UTC 24 |
| Peak memory | 597764 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2847428332 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.xbar_unmapped_addr.2847428332 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/31.xbar_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/32.xbar_access_same_device.2788773204 |
| Short name | T1729 |
| Test name | |
| Test status | |
| Simulation time | 764074196 ps |
| CPU time | 56.25 seconds |
| Started | Aug 24 05:38:59 AM UTC 24 |
| Finished | Aug 24 05:39:57 AM UTC 24 |
| Peak memory | 597772 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2788773204 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.xbar_access_same_device.2788773204 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/32.xbar_access_same_device/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/32.xbar_access_same_device_slow_rsp.656480803 |
| Short name | T1890 |
| Test name | |
| Test status | |
| Simulation time | 92976986096 ps |
| CPU time | 1118.15 seconds |
| Started | Aug 24 05:39:05 AM UTC 24 |
| Finished | Aug 24 05:57:55 AM UTC 24 |
| Peak memory | 599008 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=656480803 -assert nopostproc +UVM_TE STNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os _regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.xbar_access_same_device_slow_rsp.656480803 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/32.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/32.xbar_error_and_unmapped_addr.3974265877 |
| Short name | T1730 |
| Test name | |
| Test status | |
| Simulation time | 699804748 ps |
| CPU time | 19.5 seconds |
| Started | Aug 24 05:39:38 AM UTC 24 |
| Finished | Aug 24 05:39:58 AM UTC 24 |
| Peak memory | 597696 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3974265877 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.xbar_error_and_unmapped_addr.3974265877 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/32.xbar_error_and_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/32.xbar_error_random.4190424864 |
| Short name | T1728 |
| Test name | |
| Test status | |
| Simulation time | 732135097 ps |
| CPU time | 18.71 seconds |
| Started | Aug 24 05:39:36 AM UTC 24 |
| Finished | Aug 24 05:39:56 AM UTC 24 |
| Peak memory | 597688 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4190424864 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.xbar_error_random.4190424864 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/32.xbar_error_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/32.xbar_random.4076432075 |
| Short name | T1723 |
| Test name | |
| Test status | |
| Simulation time | 148289433 ps |
| CPU time | 11.81 seconds |
| Started | Aug 24 05:38:41 AM UTC 24 |
| Finished | Aug 24 05:38:54 AM UTC 24 |
| Peak memory | 597824 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4076432075 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.xbar_random.4076432075 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/32.xbar_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/32.xbar_random_large_delays.3878971631 |
| Short name | T1740 |
| Test name | |
| Test status | |
| Simulation time | 19445023870 ps |
| CPU time | 156.07 seconds |
| Started | Aug 24 05:38:50 AM UTC 24 |
| Finished | Aug 24 05:41:28 AM UTC 24 |
| Peak memory | 597900 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max _device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3878971631 -assert nopostproc +U VM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.xbar_random_large_delays.3878971631 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/32.xbar_random_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/32.xbar_random_slow_rsp.2461888394 |
| Short name | T1753 |
| Test name | |
| Test status | |
| Simulation time | 18116745838 ps |
| CPU time | 207.36 seconds |
| Started | Aug 24 05:38:56 AM UTC 24 |
| Finished | Aug 24 05:42:26 AM UTC 24 |
| Peak memory | 598132 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2461888394 -assert nopostproc +UVM_T ESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.xbar_random_slow_rsp.2461888394 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/32.xbar_random_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/32.xbar_random_zero_delays.881545497 |
| Short name | T1724 |
| Test name | |
| Test status | |
| Simulation time | 598062656 ps |
| CPU time | 38.61 seconds |
| Started | Aug 24 05:38:41 AM UTC 24 |
| Finished | Aug 24 05:39:21 AM UTC 24 |
| Peak memory | 597700 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=881545497 -assert nopostpro c +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.xbar_random_zero_delays.881545497 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/32.xbar_random_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/32.xbar_same_source.3385132350 |
| Short name | T1731 |
| Test name | |
| Test status | |
| Simulation time | 2615414701 ps |
| CPU time | 55.3 seconds |
| Started | Aug 24 05:39:08 AM UTC 24 |
| Finished | Aug 24 05:40:05 AM UTC 24 |
| Peak memory | 597756 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3385132350 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.xbar_same_source.3385132350 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/32.xbar_same_source/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/32.xbar_smoke.3645607524 |
| Short name | T1719 |
| Test name | |
| Test status | |
| Simulation time | 223937849 ps |
| CPU time | 7.2 seconds |
| Started | Aug 24 05:38:19 AM UTC 24 |
| Finished | Aug 24 05:38:27 AM UTC 24 |
| Peak memory | 595848 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3645607524 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 8_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.xbar_smoke.3645607524 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/32.xbar_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/32.xbar_smoke_large_delays.4242596103 |
| Short name | T1725 |
| Test name | |
| Test status | |
| Simulation time | 6175493325 ps |
| CPU time | 52.18 seconds |
| Started | Aug 24 05:38:30 AM UTC 24 |
| Finished | Aug 24 05:39:23 AM UTC 24 |
| Peak memory | 595828 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max _device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4242596103 -assert nopostproc +U VM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.xbar_smoke_large_delays.4242596103 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/32.xbar_smoke_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/32.xbar_smoke_slow_rsp.1510658688 |
| Short name | T1727 |
| Test name | |
| Test status | |
| Simulation time | 4905093679 ps |
| CPU time | 58.7 seconds |
| Started | Aug 24 05:38:36 AM UTC 24 |
| Finished | Aug 24 05:39:36 AM UTC 24 |
| Peak memory | 595768 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1510658688 -assert nopostproc +UVM_T ESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.xbar_smoke_slow_rsp.1510658688 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/32.xbar_smoke_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/32.xbar_smoke_zero_delays.688345243 |
| Short name | T1718 |
| Test name | |
| Test status | |
| Simulation time | 51122162 ps |
| CPU time | 5.38 seconds |
| Started | Aug 24 05:38:20 AM UTC 24 |
| Finished | Aug 24 05:38:26 AM UTC 24 |
| Peak memory | 595632 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=688345243 -assert nopostpro c +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.xbar_smoke_zero_delays.688345243 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/32.xbar_smoke_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/32.xbar_stress_all.1978837111 |
| Short name | T1776 |
| Test name | |
| Test status | |
| Simulation time | 13893981795 ps |
| CPU time | 363.63 seconds |
| Started | Aug 24 05:39:51 AM UTC 24 |
| Finished | Aug 24 05:45:59 AM UTC 24 |
| Peak memory | 597888 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1978837111 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.xbar_stress_all.1978837111 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/32.xbar_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/32.xbar_stress_all_with_error.3533651614 |
| Short name | T1757 |
| Test name | |
| Test status | |
| Simulation time | 6272604439 ps |
| CPU time | 162.56 seconds |
| Started | Aug 24 05:40:11 AM UTC 24 |
| Finished | Aug 24 05:42:56 AM UTC 24 |
| Peak memory | 597824 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3533651614 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.xbar_stress_all_with_error.3533651614 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/32.xbar_stress_all_with_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/32.xbar_stress_all_with_rand_reset.3940138340 |
| Short name | T1744 |
| Test name | |
| Test status | |
| Simulation time | 331301000 ps |
| CPU time | 100.66 seconds |
| Started | Aug 24 05:40:10 AM UTC 24 |
| Finished | Aug 24 05:41:52 AM UTC 24 |
| Peak memory | 597896 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3940138340 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.xbar_stress_all_with_rand_reset.3940138340 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/32.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/32.xbar_stress_all_with_reset_error.2583408971 |
| Short name | T1756 |
| Test name | |
| Test status | |
| Simulation time | 599084041 ps |
| CPU time | 156.6 seconds |
| Started | Aug 24 05:40:13 AM UTC 24 |
| Finished | Aug 24 05:42:52 AM UTC 24 |
| Peak memory | 597756 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2583408971 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.xbar_stress_all_with_reset_error.2583408971 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/32.xbar_stress_all_with_reset_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/32.xbar_unmapped_addr.1345188054 |
| Short name | T1732 |
| Test name | |
| Test status | |
| Simulation time | 1231636262 ps |
| CPU time | 36.72 seconds |
| Started | Aug 24 05:39:38 AM UTC 24 |
| Finished | Aug 24 05:40:16 AM UTC 24 |
| Peak memory | 597688 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1345188054 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.xbar_unmapped_addr.1345188054 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/32.xbar_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/33.xbar_access_same_device.3925988707 |
| Short name | T1746 |
| Test name | |
| Test status | |
| Simulation time | 1213975358 ps |
| CPU time | 33.52 seconds |
| Started | Aug 24 05:41:21 AM UTC 24 |
| Finished | Aug 24 05:41:56 AM UTC 24 |
| Peak memory | 597772 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3925988707 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.xbar_access_same_device.3925988707 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/33.xbar_access_same_device/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/33.xbar_access_same_device_slow_rsp.3929466371 |
| Short name | T2040 |
| Test name | |
| Test status | |
| Simulation time | 148740663556 ps |
| CPU time | 1814.06 seconds |
| Started | Aug 24 05:41:36 AM UTC 24 |
| Finished | Aug 24 06:12:07 AM UTC 24 |
| Peak memory | 598788 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3929466371 -assert nopostproc +UVM_T ESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.xbar_access_same_device_slow_rsp.3929466371 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/33.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/33.xbar_error_and_unmapped_addr.2163913170 |
| Short name | T1749 |
| Test name | |
| Test status | |
| Simulation time | 68587961 ps |
| CPU time | 7.37 seconds |
| Started | Aug 24 05:42:00 AM UTC 24 |
| Finished | Aug 24 05:42:08 AM UTC 24 |
| Peak memory | 597840 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2163913170 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.xbar_error_and_unmapped_addr.2163913170 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/33.xbar_error_and_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/33.xbar_error_random.1942374980 |
| Short name | T1743 |
| Test name | |
| Test status | |
| Simulation time | 32662464 ps |
| CPU time | 4.83 seconds |
| Started | Aug 24 05:41:43 AM UTC 24 |
| Finished | Aug 24 05:41:49 AM UTC 24 |
| Peak memory | 595704 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1942374980 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.xbar_error_random.1942374980 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/33.xbar_error_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/33.xbar_random.490137456 |
| Short name | T1736 |
| Test name | |
| Test status | |
| Simulation time | 561990658 ps |
| CPU time | 16.64 seconds |
| Started | Aug 24 05:40:43 AM UTC 24 |
| Finished | Aug 24 05:41:01 AM UTC 24 |
| Peak memory | 597692 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=490137456 -assert nopostproc +UVM_TESTNAME =xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 8_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.xbar_random.490137456 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/33.xbar_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/33.xbar_random_large_delays.1397731373 |
| Short name | T1815 |
| Test name | |
| Test status | |
| Simulation time | 75002453163 ps |
| CPU time | 601.32 seconds |
| Started | Aug 24 05:41:03 AM UTC 24 |
| Finished | Aug 24 05:51:11 AM UTC 24 |
| Peak memory | 597960 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max _device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1397731373 -assert nopostproc +U VM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.xbar_random_large_delays.1397731373 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/33.xbar_random_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/33.xbar_random_slow_rsp.3190210162 |
| Short name | T1839 |
| Test name | |
| Test status | |
| Simulation time | 62313015841 ps |
| CPU time | 720.59 seconds |
| Started | Aug 24 05:41:15 AM UTC 24 |
| Finished | Aug 24 05:53:23 AM UTC 24 |
| Peak memory | 597824 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3190210162 -assert nopostproc +UVM_T ESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.xbar_random_slow_rsp.3190210162 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/33.xbar_random_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/33.xbar_random_zero_delays.2653413703 |
| Short name | T1739 |
| Test name | |
| Test status | |
| Simulation time | 513917973 ps |
| CPU time | 32.94 seconds |
| Started | Aug 24 05:40:47 AM UTC 24 |
| Finished | Aug 24 05:41:22 AM UTC 24 |
| Peak memory | 597696 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2653413703 -assert nopostpr oc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.xbar_random_zero_delays.2653413703 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/33.xbar_random_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/33.xbar_same_source.3338205867 |
| Short name | T1748 |
| Test name | |
| Test status | |
| Simulation time | 920707382 ps |
| CPU time | 21.14 seconds |
| Started | Aug 24 05:41:36 AM UTC 24 |
| Finished | Aug 24 05:41:58 AM UTC 24 |
| Peak memory | 597680 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3338205867 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.xbar_same_source.3338205867 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/33.xbar_same_source/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/33.xbar_smoke.1416455464 |
| Short name | T1733 |
| Test name | |
| Test status | |
| Simulation time | 188100573 ps |
| CPU time | 6.87 seconds |
| Started | Aug 24 05:40:20 AM UTC 24 |
| Finished | Aug 24 05:40:28 AM UTC 24 |
| Peak memory | 595912 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1416455464 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 8_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.xbar_smoke.1416455464 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/33.xbar_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/33.xbar_smoke_large_delays.2386346411 |
| Short name | T1741 |
| Test name | |
| Test status | |
| Simulation time | 7794469282 ps |
| CPU time | 64.63 seconds |
| Started | Aug 24 05:40:30 AM UTC 24 |
| Finished | Aug 24 05:41:36 AM UTC 24 |
| Peak memory | 595768 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max _device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2386346411 -assert nopostproc +U VM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.xbar_smoke_large_delays.2386346411 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/33.xbar_smoke_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/33.xbar_smoke_slow_rsp.3134401967 |
| Short name | T1745 |
| Test name | |
| Test status | |
| Simulation time | 5971079750 ps |
| CPU time | 71.35 seconds |
| Started | Aug 24 05:40:42 AM UTC 24 |
| Finished | Aug 24 05:41:55 AM UTC 24 |
| Peak memory | 595908 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3134401967 -assert nopostproc +UVM_T ESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.xbar_smoke_slow_rsp.3134401967 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/33.xbar_smoke_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/33.xbar_smoke_zero_delays.3774247539 |
| Short name | T1734 |
| Test name | |
| Test status | |
| Simulation time | 43396939 ps |
| CPU time | 5.12 seconds |
| Started | Aug 24 05:40:27 AM UTC 24 |
| Finished | Aug 24 05:40:33 AM UTC 24 |
| Peak memory | 595632 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3774247539 -assert nopostpr oc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.xbar_smoke_zero_delays.3774247539 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/33.xbar_smoke_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/33.xbar_stress_all.2454633236 |
| Short name | T1792 |
| Test name | |
| Test status | |
| Simulation time | 13991960405 ps |
| CPU time | 366.83 seconds |
| Started | Aug 24 05:42:03 AM UTC 24 |
| Finished | Aug 24 05:48:14 AM UTC 24 |
| Peak memory | 597964 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2454633236 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.xbar_stress_all.2454633236 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/33.xbar_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/33.xbar_stress_all_with_error.3610595675 |
| Short name | T1789 |
| Test name | |
| Test status | |
| Simulation time | 12269972900 ps |
| CPU time | 325.17 seconds |
| Started | Aug 24 05:42:09 AM UTC 24 |
| Finished | Aug 24 05:47:38 AM UTC 24 |
| Peak memory | 597892 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3610595675 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.xbar_stress_all_with_error.3610595675 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/33.xbar_stress_all_with_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/33.xbar_stress_all_with_rand_reset.767731161 |
| Short name | T1754 |
| Test name | |
| Test status | |
| Simulation time | 9666160 ps |
| CPU time | 21.03 seconds |
| Started | Aug 24 05:42:07 AM UTC 24 |
| Finished | Aug 24 05:42:29 AM UTC 24 |
| Peak memory | 597856 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=767731161 -assert nopostproc +UVM_TESTNAME =xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.xbar_stress_all_with_rand_reset.767731161 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/33.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/33.xbar_stress_all_with_reset_error.3733971936 |
| Short name | T1774 |
| Test name | |
| Test status | |
| Simulation time | 5228439146 ps |
| CPU time | 208.26 seconds |
| Started | Aug 24 05:42:10 AM UTC 24 |
| Finished | Aug 24 05:45:41 AM UTC 24 |
| Peak memory | 597964 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3733971936 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.xbar_stress_all_with_reset_error.3733971936 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/33.xbar_stress_all_with_reset_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/33.xbar_unmapped_addr.2101509160 |
| Short name | T1747 |
| Test name | |
| Test status | |
| Simulation time | 82420895 ps |
| CPU time | 5.55 seconds |
| Started | Aug 24 05:41:51 AM UTC 24 |
| Finished | Aug 24 05:41:57 AM UTC 24 |
| Peak memory | 595692 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2101509160 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.xbar_unmapped_addr.2101509160 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/33.xbar_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/34.xbar_access_same_device.1651838647 |
| Short name | T1761 |
| Test name | |
| Test status | |
| Simulation time | 851318695 ps |
| CPU time | 41.63 seconds |
| Started | Aug 24 05:42:44 AM UTC 24 |
| Finished | Aug 24 05:43:27 AM UTC 24 |
| Peak memory | 597708 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1651838647 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.xbar_access_same_device.1651838647 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/34.xbar_access_same_device/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/34.xbar_access_same_device_slow_rsp.1526659277 |
| Short name | T1937 |
| Test name | |
| Test status | |
| Simulation time | 98090761018 ps |
| CPU time | 1150.68 seconds |
| Started | Aug 24 05:43:04 AM UTC 24 |
| Finished | Aug 24 06:02:26 AM UTC 24 |
| Peak memory | 599048 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1526659277 -assert nopostproc +UVM_T ESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.xbar_access_same_device_slow_rsp.1526659277 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/34.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/34.xbar_error_and_unmapped_addr.1665778454 |
| Short name | T1765 |
| Test name | |
| Test status | |
| Simulation time | 149122603 ps |
| CPU time | 7.19 seconds |
| Started | Aug 24 05:43:33 AM UTC 24 |
| Finished | Aug 24 05:43:41 AM UTC 24 |
| Peak memory | 595868 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1665778454 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.xbar_error_and_unmapped_addr.1665778454 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/34.xbar_error_and_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/34.xbar_error_random.1695311768 |
| Short name | T1769 |
| Test name | |
| Test status | |
| Simulation time | 2052611749 ps |
| CPU time | 49.84 seconds |
| Started | Aug 24 05:43:10 AM UTC 24 |
| Finished | Aug 24 05:44:01 AM UTC 24 |
| Peak memory | 597692 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1695311768 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.xbar_error_random.1695311768 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/34.xbar_error_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/34.xbar_random.3330219078 |
| Short name | T1758 |
| Test name | |
| Test status | |
| Simulation time | 1864284531 ps |
| CPU time | 45.45 seconds |
| Started | Aug 24 05:42:32 AM UTC 24 |
| Finished | Aug 24 05:43:19 AM UTC 24 |
| Peak memory | 597892 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3330219078 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.xbar_random.3330219078 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/34.xbar_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/34.xbar_random_large_delays.1233378869 |
| Short name | T1884 |
| Test name | |
| Test status | |
| Simulation time | 110369009373 ps |
| CPU time | 890.95 seconds |
| Started | Aug 24 05:42:38 AM UTC 24 |
| Finished | Aug 24 05:57:38 AM UTC 24 |
| Peak memory | 597820 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max _device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1233378869 -assert nopostproc +U VM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.xbar_random_large_delays.1233378869 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/34.xbar_random_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/34.xbar_random_slow_rsp.1425405642 |
| Short name | T1818 |
| Test name | |
| Test status | |
| Simulation time | 45077274525 ps |
| CPU time | 522.4 seconds |
| Started | Aug 24 05:42:41 AM UTC 24 |
| Finished | Aug 24 05:51:28 AM UTC 24 |
| Peak memory | 598096 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1425405642 -assert nopostproc +UVM_T ESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.xbar_random_slow_rsp.1425405642 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/34.xbar_random_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/34.xbar_random_zero_delays.1977826930 |
| Short name | T1755 |
| Test name | |
| Test status | |
| Simulation time | 202103697 ps |
| CPU time | 15.39 seconds |
| Started | Aug 24 05:42:33 AM UTC 24 |
| Finished | Aug 24 05:42:50 AM UTC 24 |
| Peak memory | 597840 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1977826930 -assert nopostpr oc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.xbar_random_zero_delays.1977826930 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/34.xbar_random_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/34.xbar_same_source.1770885048 |
| Short name | T1764 |
| Test name | |
| Test status | |
| Simulation time | 1387481406 ps |
| CPU time | 29.28 seconds |
| Started | Aug 24 05:43:06 AM UTC 24 |
| Finished | Aug 24 05:43:37 AM UTC 24 |
| Peak memory | 597752 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1770885048 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.xbar_same_source.1770885048 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/34.xbar_same_source/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/34.xbar_smoke.2709514050 |
| Short name | T1751 |
| Test name | |
| Test status | |
| Simulation time | 53150935 ps |
| CPU time | 5.16 seconds |
| Started | Aug 24 05:42:12 AM UTC 24 |
| Finished | Aug 24 05:42:18 AM UTC 24 |
| Peak memory | 595636 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2709514050 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 8_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.xbar_smoke.2709514050 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/34.xbar_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/34.xbar_smoke_large_delays.1426741675 |
| Short name | T1762 |
| Test name | |
| Test status | |
| Simulation time | 7543208699 ps |
| CPU time | 63.98 seconds |
| Started | Aug 24 05:42:22 AM UTC 24 |
| Finished | Aug 24 05:43:28 AM UTC 24 |
| Peak memory | 595764 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max _device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1426741675 -assert nopostproc +U VM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.xbar_smoke_large_delays.1426741675 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/34.xbar_smoke_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/34.xbar_smoke_slow_rsp.572841878 |
| Short name | T1760 |
| Test name | |
| Test status | |
| Simulation time | 4346502196 ps |
| CPU time | 51.39 seconds |
| Started | Aug 24 05:42:32 AM UTC 24 |
| Finished | Aug 24 05:43:25 AM UTC 24 |
| Peak memory | 595768 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=572841878 -assert nopostproc +UVM_TE STNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.xbar_smoke_slow_rsp.572841878 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/34.xbar_smoke_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/34.xbar_smoke_zero_delays.691633288 |
| Short name | T1750 |
| Test name | |
| Test status | |
| Simulation time | 47772646 ps |
| CPU time | 5.12 seconds |
| Started | Aug 24 05:42:12 AM UTC 24 |
| Finished | Aug 24 05:42:18 AM UTC 24 |
| Peak memory | 595636 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=691633288 -assert nopostpro c +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.xbar_smoke_zero_delays.691633288 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/34.xbar_smoke_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/34.xbar_stress_all.2218025556 |
| Short name | T1797 |
| Test name | |
| Test status | |
| Simulation time | 11587498213 ps |
| CPU time | 320.65 seconds |
| Started | Aug 24 05:43:37 AM UTC 24 |
| Finished | Aug 24 05:49:02 AM UTC 24 |
| Peak memory | 597964 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2218025556 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.xbar_stress_all.2218025556 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/34.xbar_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/34.xbar_stress_all_with_error.1838662689 |
| Short name | T1782 |
| Test name | |
| Test status | |
| Simulation time | 7516995392 ps |
| CPU time | 192.2 seconds |
| Started | Aug 24 05:43:41 AM UTC 24 |
| Finished | Aug 24 05:46:56 AM UTC 24 |
| Peak memory | 597824 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1838662689 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.xbar_stress_all_with_error.1838662689 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/34.xbar_stress_all_with_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/34.xbar_stress_all_with_rand_reset.307227748 |
| Short name | T843 |
| Test name | |
| Test status | |
| Simulation time | 3271370831 ps |
| CPU time | 365.22 seconds |
| Started | Aug 24 05:43:39 AM UTC 24 |
| Finished | Aug 24 05:49:49 AM UTC 24 |
| Peak memory | 597760 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=307227748 -assert nopostproc +UVM_TESTNAME =xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.xbar_stress_all_with_rand_reset.307227748 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/34.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/34.xbar_stress_all_with_reset_error.3630314570 |
| Short name | T863 |
| Test name | |
| Test status | |
| Simulation time | 6004371774 ps |
| CPU time | 481.72 seconds |
| Started | Aug 24 05:43:42 AM UTC 24 |
| Finished | Aug 24 05:51:49 AM UTC 24 |
| Peak memory | 598116 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3630314570 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.xbar_stress_all_with_reset_error.3630314570 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/34.xbar_stress_all_with_reset_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/34.xbar_unmapped_addr.2657625928 |
| Short name | T1768 |
| Test name | |
| Test status | |
| Simulation time | 315518594 ps |
| CPU time | 28.09 seconds |
| Started | Aug 24 05:43:28 AM UTC 24 |
| Finished | Aug 24 05:43:58 AM UTC 24 |
| Peak memory | 597692 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2657625928 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.xbar_unmapped_addr.2657625928 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/34.xbar_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/35.xbar_access_same_device.2884093343 |
| Short name | T1775 |
| Test name | |
| Test status | |
| Simulation time | 1275731594 ps |
| CPU time | 39.66 seconds |
| Started | Aug 24 05:45:15 AM UTC 24 |
| Finished | Aug 24 05:45:56 AM UTC 24 |
| Peak memory | 597928 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2884093343 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.xbar_access_same_device.2884093343 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/35.xbar_access_same_device/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/35.xbar_access_same_device_slow_rsp.1392082070 |
| Short name | T1826 |
| Test name | |
| Test status | |
| Simulation time | 35613229056 ps |
| CPU time | 404.03 seconds |
| Started | Aug 24 05:45:20 AM UTC 24 |
| Finished | Aug 24 05:52:09 AM UTC 24 |
| Peak memory | 598052 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1392082070 -assert nopostproc +UVM_T ESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.xbar_access_same_device_slow_rsp.1392082070 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/35.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/35.xbar_error_and_unmapped_addr.2436293873 |
| Short name | T1780 |
| Test name | |
| Test status | |
| Simulation time | 101364965 ps |
| CPU time | 10.34 seconds |
| Started | Aug 24 05:46:13 AM UTC 24 |
| Finished | Aug 24 05:46:24 AM UTC 24 |
| Peak memory | 597904 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2436293873 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.xbar_error_and_unmapped_addr.2436293873 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/35.xbar_error_and_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/35.xbar_error_random.847208554 |
| Short name | T1778 |
| Test name | |
| Test status | |
| Simulation time | 203586112 ps |
| CPU time | 14.46 seconds |
| Started | Aug 24 05:45:55 AM UTC 24 |
| Finished | Aug 24 05:46:11 AM UTC 24 |
| Peak memory | 597948 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=847208554 -assert nopostproc +UVM_TESTNAME =xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.xbar_error_random.847208554 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/35.xbar_error_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/35.xbar_random.2050140048 |
| Short name | T1771 |
| Test name | |
| Test status | |
| Simulation time | 1821306286 ps |
| CPU time | 47.81 seconds |
| Started | Aug 24 05:44:12 AM UTC 24 |
| Finished | Aug 24 05:45:01 AM UTC 24 |
| Peak memory | 597892 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2050140048 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.xbar_random.2050140048 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/35.xbar_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/35.xbar_random_large_delays.3593635765 |
| Short name | T1837 |
| Test name | |
| Test status | |
| Simulation time | 65493987584 ps |
| CPU time | 536.1 seconds |
| Started | Aug 24 05:44:16 AM UTC 24 |
| Finished | Aug 24 05:53:17 AM UTC 24 |
| Peak memory | 597948 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max _device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3593635765 -assert nopostproc +U VM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.xbar_random_large_delays.3593635765 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/35.xbar_random_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/35.xbar_random_slow_rsp.64386484 |
| Short name | T1812 |
| Test name | |
| Test status | |
| Simulation time | 28743976143 ps |
| CPU time | 343.91 seconds |
| Started | Aug 24 05:44:57 AM UTC 24 |
| Finished | Aug 24 05:50:45 AM UTC 24 |
| Peak memory | 597824 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=64386484 -assert nopostproc +UVM_TES TNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.xbar_random_slow_rsp.64386484 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/35.xbar_random_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/35.xbar_random_zero_delays.36211111 |
| Short name | T1770 |
| Test name | |
| Test status | |
| Simulation time | 497222929 ps |
| CPU time | 29.2 seconds |
| Started | Aug 24 05:44:12 AM UTC 24 |
| Finished | Aug 24 05:44:42 AM UTC 24 |
| Peak memory | 597912 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=36211111 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.xbar_random_zero_delays.36211111 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/35.xbar_random_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/35.xbar_same_source.559582882 |
| Short name | T1779 |
| Test name | |
| Test status | |
| Simulation time | 2329025652 ps |
| CPU time | 52.31 seconds |
| Started | Aug 24 05:45:20 AM UTC 24 |
| Finished | Aug 24 05:46:14 AM UTC 24 |
| Peak memory | 597896 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=559582882 -assert nopostproc +UVM_TESTNAME =xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.xbar_same_source.559582882 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/35.xbar_same_source/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/35.xbar_smoke.2494917539 |
| Short name | T1766 |
| Test name | |
| Test status | |
| Simulation time | 52935684 ps |
| CPU time | 5.42 seconds |
| Started | Aug 24 05:43:50 AM UTC 24 |
| Finished | Aug 24 05:43:57 AM UTC 24 |
| Peak memory | 594984 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2494917539 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 8_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.xbar_smoke.2494917539 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/35.xbar_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/35.xbar_smoke_large_delays.4185393847 |
| Short name | T1773 |
| Test name | |
| Test status | |
| Simulation time | 8570470036 ps |
| CPU time | 69.04 seconds |
| Started | Aug 24 05:43:55 AM UTC 24 |
| Finished | Aug 24 05:45:06 AM UTC 24 |
| Peak memory | 595828 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max _device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4185393847 -assert nopostproc +U VM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.xbar_smoke_large_delays.4185393847 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/35.xbar_smoke_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/35.xbar_smoke_slow_rsp.329235223 |
| Short name | T1772 |
| Test name | |
| Test status | |
| Simulation time | 4475422671 ps |
| CPU time | 53.59 seconds |
| Started | Aug 24 05:44:11 AM UTC 24 |
| Finished | Aug 24 05:45:06 AM UTC 24 |
| Peak memory | 595988 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=329235223 -assert nopostproc +UVM_TE STNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.xbar_smoke_slow_rsp.329235223 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/35.xbar_smoke_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/35.xbar_smoke_zero_delays.1329344220 |
| Short name | T1767 |
| Test name | |
| Test status | |
| Simulation time | 38106890 ps |
| CPU time | 4.72 seconds |
| Started | Aug 24 05:43:51 AM UTC 24 |
| Finished | Aug 24 05:43:57 AM UTC 24 |
| Peak memory | 595796 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1329344220 -assert nopostpr oc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.xbar_smoke_zero_delays.1329344220 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/35.xbar_smoke_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/35.xbar_stress_all.170854376 |
| Short name | T1786 |
| Test name | |
| Test status | |
| Simulation time | 1075501081 ps |
| CPU time | 54.17 seconds |
| Started | Aug 24 05:46:15 AM UTC 24 |
| Finished | Aug 24 05:47:11 AM UTC 24 |
| Peak memory | 597952 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=170854376 -assert nopostproc +UVM_TESTNAME =xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.xbar_stress_all.170854376 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/35.xbar_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/35.xbar_stress_all_with_error.4145257204 |
| Short name | T1806 |
| Test name | |
| Test status | |
| Simulation time | 9026749334 ps |
| CPU time | 232.11 seconds |
| Started | Aug 24 05:46:28 AM UTC 24 |
| Finished | Aug 24 05:50:24 AM UTC 24 |
| Peak memory | 598084 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4145257204 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.xbar_stress_all_with_error.4145257204 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/35.xbar_stress_all_with_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/35.xbar_stress_all_with_rand_reset.964614115 |
| Short name | T1785 |
| Test name | |
| Test status | |
| Simulation time | 106514849 ps |
| CPU time | 42.04 seconds |
| Started | Aug 24 05:46:25 AM UTC 24 |
| Finished | Aug 24 05:47:09 AM UTC 24 |
| Peak memory | 597688 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=964614115 -assert nopostproc +UVM_TESTNAME =xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.xbar_stress_all_with_rand_reset.964614115 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/35.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/35.xbar_stress_all_with_reset_error.1649174696 |
| Short name | T1805 |
| Test name | |
| Test status | |
| Simulation time | 4064180496 ps |
| CPU time | 218.45 seconds |
| Started | Aug 24 05:46:38 AM UTC 24 |
| Finished | Aug 24 05:50:20 AM UTC 24 |
| Peak memory | 597756 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1649174696 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.xbar_stress_all_with_reset_error.1649174696 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/35.xbar_stress_all_with_reset_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/35.xbar_unmapped_addr.3938688837 |
| Short name | T1781 |
| Test name | |
| Test status | |
| Simulation time | 313725872 ps |
| CPU time | 27.33 seconds |
| Started | Aug 24 05:46:10 AM UTC 24 |
| Finished | Aug 24 05:46:39 AM UTC 24 |
| Peak memory | 597684 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3938688837 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.xbar_unmapped_addr.3938688837 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/35.xbar_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/36.xbar_access_same_device.3196681674 |
| Short name | T1800 |
| Test name | |
| Test status | |
| Simulation time | 3734996447 ps |
| CPU time | 92.63 seconds |
| Started | Aug 24 05:47:48 AM UTC 24 |
| Finished | Aug 24 05:49:22 AM UTC 24 |
| Peak memory | 597840 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3196681674 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.xbar_access_same_device.3196681674 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/36.xbar_access_same_device/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/36.xbar_access_same_device_slow_rsp.2475365592 |
| Short name | T1857 |
| Test name | |
| Test status | |
| Simulation time | 40777428837 ps |
| CPU time | 462.11 seconds |
| Started | Aug 24 05:47:53 AM UTC 24 |
| Finished | Aug 24 05:55:40 AM UTC 24 |
| Peak memory | 597964 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2475365592 -assert nopostproc +UVM_T ESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.xbar_access_same_device_slow_rsp.2475365592 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/36.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/36.xbar_error_and_unmapped_addr.1859970490 |
| Short name | T1795 |
| Test name | |
| Test status | |
| Simulation time | 576981860 ps |
| CPU time | 16.25 seconds |
| Started | Aug 24 05:48:41 AM UTC 24 |
| Finished | Aug 24 05:48:59 AM UTC 24 |
| Peak memory | 597696 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1859970490 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.xbar_error_and_unmapped_addr.1859970490 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/36.xbar_error_and_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/36.xbar_error_random.2933756870 |
| Short name | T1793 |
| Test name | |
| Test status | |
| Simulation time | 183222109 ps |
| CPU time | 6.96 seconds |
| Started | Aug 24 05:48:19 AM UTC 24 |
| Finished | Aug 24 05:48:27 AM UTC 24 |
| Peak memory | 595640 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2933756870 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.xbar_error_random.2933756870 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/36.xbar_error_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/36.xbar_random.3547672124 |
| Short name | T1790 |
| Test name | |
| Test status | |
| Simulation time | 1203990628 ps |
| CPU time | 32.45 seconds |
| Started | Aug 24 05:47:21 AM UTC 24 |
| Finished | Aug 24 05:47:54 AM UTC 24 |
| Peak memory | 597828 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3547672124 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.xbar_random.3547672124 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/36.xbar_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/36.xbar_random_large_delays.1130438326 |
| Short name | T1874 |
| Test name | |
| Test status | |
| Simulation time | 66793398586 ps |
| CPU time | 548.74 seconds |
| Started | Aug 24 05:47:25 AM UTC 24 |
| Finished | Aug 24 05:56:39 AM UTC 24 |
| Peak memory | 597816 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max _device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1130438326 -assert nopostproc +U VM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.xbar_random_large_delays.1130438326 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/36.xbar_random_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/36.xbar_random_slow_rsp.9461664 |
| Short name | T1923 |
| Test name | |
| Test status | |
| Simulation time | 69269744868 ps |
| CPU time | 808.72 seconds |
| Started | Aug 24 05:47:44 AM UTC 24 |
| Finished | Aug 24 06:01:21 AM UTC 24 |
| Peak memory | 597968 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=9461664 -assert nopostproc +UVM_TEST NAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.xbar_random_slow_rsp.9461664 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/36.xbar_random_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/36.xbar_random_zero_delays.4007683093 |
| Short name | T1787 |
| Test name | |
| Test status | |
| Simulation time | 63934728 ps |
| CPU time | 6.5 seconds |
| Started | Aug 24 05:47:23 AM UTC 24 |
| Finished | Aug 24 05:47:30 AM UTC 24 |
| Peak memory | 597696 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4007683093 -assert nopostpr oc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.xbar_random_zero_delays.4007683093 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/36.xbar_random_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/36.xbar_same_source.4267825541 |
| Short name | T1798 |
| Test name | |
| Test status | |
| Simulation time | 2488421028 ps |
| CPU time | 52.5 seconds |
| Started | Aug 24 05:48:08 AM UTC 24 |
| Finished | Aug 24 05:49:02 AM UTC 24 |
| Peak memory | 597756 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4267825541 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.xbar_same_source.4267825541 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/36.xbar_same_source/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/36.xbar_smoke.3118915020 |
| Short name | T1783 |
| Test name | |
| Test status | |
| Simulation time | 178377266 ps |
| CPU time | 6.36 seconds |
| Started | Aug 24 05:46:53 AM UTC 24 |
| Finished | Aug 24 05:47:00 AM UTC 24 |
| Peak memory | 595636 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3118915020 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 8_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.xbar_smoke.3118915020 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/36.xbar_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/36.xbar_smoke_large_delays.2692662296 |
| Short name | T1794 |
| Test name | |
| Test status | |
| Simulation time | 10370217713 ps |
| CPU time | 83.85 seconds |
| Started | Aug 24 05:47:11 AM UTC 24 |
| Finished | Aug 24 05:48:36 AM UTC 24 |
| Peak memory | 595912 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max _device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2692662296 -assert nopostproc +U VM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.xbar_smoke_large_delays.2692662296 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/36.xbar_smoke_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/36.xbar_smoke_slow_rsp.3953550558 |
| Short name | T1791 |
| Test name | |
| Test status | |
| Simulation time | 4229988866 ps |
| CPU time | 49.94 seconds |
| Started | Aug 24 05:47:14 AM UTC 24 |
| Finished | Aug 24 05:48:05 AM UTC 24 |
| Peak memory | 595704 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3953550558 -assert nopostproc +UVM_T ESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.xbar_smoke_slow_rsp.3953550558 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/36.xbar_smoke_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/36.xbar_smoke_zero_delays.2270056077 |
| Short name | T1784 |
| Test name | |
| Test status | |
| Simulation time | 37983356 ps |
| CPU time | 4.62 seconds |
| Started | Aug 24 05:47:00 AM UTC 24 |
| Finished | Aug 24 05:47:06 AM UTC 24 |
| Peak memory | 595764 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2270056077 -assert nopostpr oc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.xbar_smoke_zero_delays.2270056077 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/36.xbar_smoke_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/36.xbar_stress_all.3927825919 |
| Short name | T539 |
| Test name | |
| Test status | |
| Simulation time | 10433875889 ps |
| CPU time | 263.67 seconds |
| Started | Aug 24 05:48:50 AM UTC 24 |
| Finished | Aug 24 05:53:18 AM UTC 24 |
| Peak memory | 597828 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3927825919 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.xbar_stress_all.3927825919 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/36.xbar_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/36.xbar_stress_all_with_error.402033968 |
| Short name | T1827 |
| Test name | |
| Test status | |
| Simulation time | 3297867646 ps |
| CPU time | 180.51 seconds |
| Started | Aug 24 05:49:13 AM UTC 24 |
| Finished | Aug 24 05:52:17 AM UTC 24 |
| Peak memory | 597824 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=402033968 -assert nopostproc +UVM_TESTNAME =xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.xbar_stress_all_with_error.402033968 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/36.xbar_stress_all_with_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/36.xbar_stress_all_with_rand_reset.2487013423 |
| Short name | T1824 |
| Test name | |
| Test status | |
| Simulation time | 430003661 ps |
| CPU time | 171.78 seconds |
| Started | Aug 24 05:49:12 AM UTC 24 |
| Finished | Aug 24 05:52:07 AM UTC 24 |
| Peak memory | 597688 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2487013423 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.xbar_stress_all_with_rand_reset.2487013423 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/36.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/36.xbar_stress_all_with_reset_error.4020421773 |
| Short name | T868 |
| Test name | |
| Test status | |
| Simulation time | 1391729580 ps |
| CPU time | 225.24 seconds |
| Started | Aug 24 05:49:16 AM UTC 24 |
| Finished | Aug 24 05:53:05 AM UTC 24 |
| Peak memory | 597924 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4020421773 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.xbar_stress_all_with_reset_error.4020421773 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/36.xbar_stress_all_with_reset_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/36.xbar_unmapped_addr.1918419025 |
| Short name | T1796 |
| Test name | |
| Test status | |
| Simulation time | 917804850 ps |
| CPU time | 30.07 seconds |
| Started | Aug 24 05:48:28 AM UTC 24 |
| Finished | Aug 24 05:48:59 AM UTC 24 |
| Peak memory | 597688 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1918419025 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.xbar_unmapped_addr.1918419025 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/36.xbar_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/37.xbar_access_same_device.1159227572 |
| Short name | T1822 |
| Test name | |
| Test status | |
| Simulation time | 2228827722 ps |
| CPU time | 68.27 seconds |
| Started | Aug 24 05:50:34 AM UTC 24 |
| Finished | Aug 24 05:51:44 AM UTC 24 |
| Peak memory | 597988 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1159227572 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.xbar_access_same_device.1159227572 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/37.xbar_access_same_device/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/37.xbar_access_same_device_slow_rsp.1493299303 |
| Short name | T800 |
| Test name | |
| Test status | |
| Simulation time | 64818023339 ps |
| CPU time | 774.05 seconds |
| Started | Aug 24 05:50:37 AM UTC 24 |
| Finished | Aug 24 06:03:39 AM UTC 24 |
| Peak memory | 598472 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1493299303 -assert nopostproc +UVM_T ESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.xbar_access_same_device_slow_rsp.1493299303 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/37.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/37.xbar_error_and_unmapped_addr.2578303700 |
| Short name | T1813 |
| Test name | |
| Test status | |
| Simulation time | 475266772 ps |
| CPU time | 15.44 seconds |
| Started | Aug 24 05:50:52 AM UTC 24 |
| Finished | Aug 24 05:51:09 AM UTC 24 |
| Peak memory | 597824 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2578303700 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.xbar_error_and_unmapped_addr.2578303700 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/37.xbar_error_and_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/37.xbar_error_random.1182750892 |
| Short name | T1820 |
| Test name | |
| Test status | |
| Simulation time | 2202491765 ps |
| CPU time | 52.17 seconds |
| Started | Aug 24 05:50:45 AM UTC 24 |
| Finished | Aug 24 05:51:39 AM UTC 24 |
| Peak memory | 597760 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1182750892 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.xbar_error_random.1182750892 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/37.xbar_error_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/37.xbar_random.3504741165 |
| Short name | T1807 |
| Test name | |
| Test status | |
| Simulation time | 1312333699 ps |
| CPU time | 31.88 seconds |
| Started | Aug 24 05:49:55 AM UTC 24 |
| Finished | Aug 24 05:50:28 AM UTC 24 |
| Peak memory | 597696 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3504741165 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.xbar_random.3504741165 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/37.xbar_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/37.xbar_random_large_delays.711116403 |
| Short name | T1944 |
| Test name | |
| Test status | |
| Simulation time | 92223643553 ps |
| CPU time | 762.96 seconds |
| Started | Aug 24 05:50:06 AM UTC 24 |
| Finished | Aug 24 06:02:57 AM UTC 24 |
| Peak memory | 598464 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max _device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=711116403 -assert nopostproc +UV M_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.xbar_random_large_delays.711116403 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/37.xbar_random_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/37.xbar_random_slow_rsp.2731479140 |
| Short name | T1882 |
| Test name | |
| Test status | |
| Simulation time | 35137378774 ps |
| CPU time | 423.51 seconds |
| Started | Aug 24 05:50:19 AM UTC 24 |
| Finished | Aug 24 05:57:27 AM UTC 24 |
| Peak memory | 597956 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2731479140 -assert nopostproc +UVM_T ESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.xbar_random_slow_rsp.2731479140 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/37.xbar_random_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/37.xbar_random_zero_delays.2133034700 |
| Short name | T1808 |
| Test name | |
| Test status | |
| Simulation time | 432659201 ps |
| CPU time | 27.18 seconds |
| Started | Aug 24 05:50:03 AM UTC 24 |
| Finished | Aug 24 05:50:32 AM UTC 24 |
| Peak memory | 597840 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2133034700 -assert nopostpr oc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.xbar_random_zero_delays.2133034700 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/37.xbar_random_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/37.xbar_same_source.1322189026 |
| Short name | T1814 |
| Test name | |
| Test status | |
| Simulation time | 476868310 ps |
| CPU time | 26.62 seconds |
| Started | Aug 24 05:50:42 AM UTC 24 |
| Finished | Aug 24 05:51:10 AM UTC 24 |
| Peak memory | 597940 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1322189026 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.xbar_same_source.1322189026 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/37.xbar_same_source/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/37.xbar_smoke.1862108166 |
| Short name | T1801 |
| Test name | |
| Test status | |
| Simulation time | 181346677 ps |
| CPU time | 6.54 seconds |
| Started | Aug 24 05:49:16 AM UTC 24 |
| Finished | Aug 24 05:49:24 AM UTC 24 |
| Peak memory | 595692 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1862108166 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 8_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.xbar_smoke.1862108166 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/37.xbar_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/37.xbar_smoke_large_delays.3042956627 |
| Short name | T1809 |
| Test name | |
| Test status | |
| Simulation time | 7258660439 ps |
| CPU time | 58.85 seconds |
| Started | Aug 24 05:49:36 AM UTC 24 |
| Finished | Aug 24 05:50:37 AM UTC 24 |
| Peak memory | 595764 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max _device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3042956627 -assert nopostproc +U VM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.xbar_smoke_large_delays.3042956627 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/37.xbar_smoke_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/37.xbar_smoke_slow_rsp.4171224641 |
| Short name | T1810 |
| Test name | |
| Test status | |
| Simulation time | 4871328707 ps |
| CPU time | 58.35 seconds |
| Started | Aug 24 05:49:39 AM UTC 24 |
| Finished | Aug 24 05:50:38 AM UTC 24 |
| Peak memory | 595772 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4171224641 -assert nopostproc +UVM_T ESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.xbar_smoke_slow_rsp.4171224641 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/37.xbar_smoke_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/37.xbar_smoke_zero_delays.875335031 |
| Short name | T1802 |
| Test name | |
| Test status | |
| Simulation time | 45059807 ps |
| CPU time | 4.8 seconds |
| Started | Aug 24 05:49:34 AM UTC 24 |
| Finished | Aug 24 05:49:40 AM UTC 24 |
| Peak memory | 595704 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=875335031 -assert nopostpro c +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.xbar_smoke_zero_delays.875335031 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/37.xbar_smoke_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/37.xbar_stress_all.3882074462 |
| Short name | T1858 |
| Test name | |
| Test status | |
| Simulation time | 10120686156 ps |
| CPU time | 280.92 seconds |
| Started | Aug 24 05:50:57 AM UTC 24 |
| Finished | Aug 24 05:55:42 AM UTC 24 |
| Peak memory | 597952 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3882074462 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.xbar_stress_all.3882074462 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/37.xbar_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/37.xbar_stress_all_with_error.1909437928 |
| Short name | T1844 |
| Test name | |
| Test status | |
| Simulation time | 3234895056 ps |
| CPU time | 169.33 seconds |
| Started | Aug 24 05:51:23 AM UTC 24 |
| Finished | Aug 24 05:54:14 AM UTC 24 |
| Peak memory | 597760 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1909437928 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.xbar_stress_all_with_error.1909437928 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/37.xbar_stress_all_with_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/37.xbar_stress_all_with_rand_reset.321503490 |
| Short name | T1907 |
| Test name | |
| Test status | |
| Simulation time | 6315969491 ps |
| CPU time | 535.66 seconds |
| Started | Aug 24 05:50:58 AM UTC 24 |
| Finished | Aug 24 06:00:00 AM UTC 24 |
| Peak memory | 597820 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=321503490 -assert nopostproc +UVM_TESTNAME =xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.xbar_stress_all_with_rand_reset.321503490 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/37.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/37.xbar_stress_all_with_reset_error.4233235598 |
| Short name | T844 |
| Test name | |
| Test status | |
| Simulation time | 2467885222 ps |
| CPU time | 217.38 seconds |
| Started | Aug 24 05:51:25 AM UTC 24 |
| Finished | Aug 24 05:55:05 AM UTC 24 |
| Peak memory | 597760 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4233235598 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.xbar_stress_all_with_reset_error.4233235598 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/37.xbar_stress_all_with_reset_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/37.xbar_unmapped_addr.560961304 |
| Short name | T1816 |
| Test name | |
| Test status | |
| Simulation time | 954216875 ps |
| CPU time | 29.17 seconds |
| Started | Aug 24 05:50:50 AM UTC 24 |
| Finished | Aug 24 05:51:21 AM UTC 24 |
| Peak memory | 597756 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=560961304 -assert nopostproc +UVM_TESTNAME =xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.xbar_unmapped_addr.560961304 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/37.xbar_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/38.xbar_access_same_device.1456919850 |
| Short name | T1834 |
| Test name | |
| Test status | |
| Simulation time | 1869391105 ps |
| CPU time | 54.81 seconds |
| Started | Aug 24 05:52:04 AM UTC 24 |
| Finished | Aug 24 05:53:01 AM UTC 24 |
| Peak memory | 597988 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1456919850 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.xbar_access_same_device.1456919850 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/38.xbar_access_same_device/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/38.xbar_access_same_device_slow_rsp.2286560161 |
| Short name | T2134 |
| Test name | |
| Test status | |
| Simulation time | 158789739519 ps |
| CPU time | 1788.17 seconds |
| Started | Aug 24 05:52:16 AM UTC 24 |
| Finished | Aug 24 06:22:21 AM UTC 24 |
| Peak memory | 598788 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2286560161 -assert nopostproc +UVM_T ESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.xbar_access_same_device_slow_rsp.2286560161 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/38.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/38.xbar_error_and_unmapped_addr.1805665678 |
| Short name | T1832 |
| Test name | |
| Test status | |
| Simulation time | 333810592 ps |
| CPU time | 24.06 seconds |
| Started | Aug 24 05:52:31 AM UTC 24 |
| Finished | Aug 24 05:52:56 AM UTC 24 |
| Peak memory | 597700 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1805665678 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.xbar_error_and_unmapped_addr.1805665678 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/38.xbar_error_and_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/38.xbar_random.4289078285 |
| Short name | T1823 |
| Test name | |
| Test status | |
| Simulation time | 202195148 ps |
| CPU time | 13.92 seconds |
| Started | Aug 24 05:51:47 AM UTC 24 |
| Finished | Aug 24 05:52:02 AM UTC 24 |
| Peak memory | 597840 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4289078285 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.xbar_random.4289078285 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/38.xbar_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/38.xbar_random_large_delays.2988131721 |
| Short name | T1854 |
| Test name | |
| Test status | |
| Simulation time | 22727684129 ps |
| CPU time | 202.12 seconds |
| Started | Aug 24 05:51:56 AM UTC 24 |
| Finished | Aug 24 05:55:21 AM UTC 24 |
| Peak memory | 597888 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max _device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2988131721 -assert nopostproc +U VM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.xbar_random_large_delays.2988131721 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/38.xbar_random_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/38.xbar_random_slow_rsp.2415573860 |
| Short name | T1836 |
| Test name | |
| Test status | |
| Simulation time | 6567794036 ps |
| CPU time | 76.96 seconds |
| Started | Aug 24 05:51:58 AM UTC 24 |
| Finished | Aug 24 05:53:17 AM UTC 24 |
| Peak memory | 598064 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2415573860 -assert nopostproc +UVM_T ESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.xbar_random_slow_rsp.2415573860 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/38.xbar_random_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/38.xbar_random_zero_delays.2158530308 |
| Short name | T1828 |
| Test name | |
| Test status | |
| Simulation time | 603230619 ps |
| CPU time | 35.87 seconds |
| Started | Aug 24 05:51:53 AM UTC 24 |
| Finished | Aug 24 05:52:30 AM UTC 24 |
| Peak memory | 597836 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2158530308 -assert nopostpr oc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.xbar_random_zero_delays.2158530308 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/38.xbar_random_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/38.xbar_same_source.3201375344 |
| Short name | T1830 |
| Test name | |
| Test status | |
| Simulation time | 772518412 ps |
| CPU time | 17.42 seconds |
| Started | Aug 24 05:52:21 AM UTC 24 |
| Finished | Aug 24 05:52:39 AM UTC 24 |
| Peak memory | 597688 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3201375344 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.xbar_same_source.3201375344 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/38.xbar_same_source/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/38.xbar_smoke.2694618006 |
| Short name | T1819 |
| Test name | |
| Test status | |
| Simulation time | 220397453 ps |
| CPU time | 6.88 seconds |
| Started | Aug 24 05:51:25 AM UTC 24 |
| Finished | Aug 24 05:51:33 AM UTC 24 |
| Peak memory | 595700 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2694618006 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 8_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.xbar_smoke.2694618006 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/38.xbar_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/38.xbar_smoke_large_delays.3772244572 |
| Short name | T1833 |
| Test name | |
| Test status | |
| Simulation time | 9667933219 ps |
| CPU time | 82.44 seconds |
| Started | Aug 24 05:51:36 AM UTC 24 |
| Finished | Aug 24 05:53:00 AM UTC 24 |
| Peak memory | 596016 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max _device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3772244572 -assert nopostproc +U VM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.xbar_smoke_large_delays.3772244572 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/38.xbar_smoke_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/38.xbar_smoke_slow_rsp.1637101483 |
| Short name | T1829 |
| Test name | |
| Test status | |
| Simulation time | 4428861716 ps |
| CPU time | 51.33 seconds |
| Started | Aug 24 05:51:43 AM UTC 24 |
| Finished | Aug 24 05:52:36 AM UTC 24 |
| Peak memory | 595908 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1637101483 -assert nopostproc +UVM_T ESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.xbar_smoke_slow_rsp.1637101483 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/38.xbar_smoke_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/38.xbar_smoke_zero_delays.2195120221 |
| Short name | T1821 |
| Test name | |
| Test status | |
| Simulation time | 57328686 ps |
| CPU time | 5.89 seconds |
| Started | Aug 24 05:51:35 AM UTC 24 |
| Finished | Aug 24 05:51:42 AM UTC 24 |
| Peak memory | 595636 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2195120221 -assert nopostpr oc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.xbar_smoke_zero_delays.2195120221 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/38.xbar_smoke_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/38.xbar_stress_all.2331025567 |
| Short name | T1859 |
| Test name | |
| Test status | |
| Simulation time | 3544011046 ps |
| CPU time | 188.35 seconds |
| Started | Aug 24 05:52:45 AM UTC 24 |
| Finished | Aug 24 05:55:56 AM UTC 24 |
| Peak memory | 597760 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2331025567 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.xbar_stress_all.2331025567 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/38.xbar_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/38.xbar_stress_all_with_error.2696886985 |
| Short name | T1847 |
| Test name | |
| Test status | |
| Simulation time | 2159682425 ps |
| CPU time | 109.66 seconds |
| Started | Aug 24 05:52:53 AM UTC 24 |
| Finished | Aug 24 05:54:44 AM UTC 24 |
| Peak memory | 597972 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2696886985 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.xbar_stress_all_with_error.2696886985 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/38.xbar_stress_all_with_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/38.xbar_stress_all_with_rand_reset.2588523434 |
| Short name | T1855 |
| Test name | |
| Test status | |
| Simulation time | 1399888627 ps |
| CPU time | 152.82 seconds |
| Started | Aug 24 05:52:50 AM UTC 24 |
| Finished | Aug 24 05:55:25 AM UTC 24 |
| Peak memory | 597692 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2588523434 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.xbar_stress_all_with_rand_reset.2588523434 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/38.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/38.xbar_stress_all_with_reset_error.2079445100 |
| Short name | T1880 |
| Test name | |
| Test status | |
| Simulation time | 5845237945 ps |
| CPU time | 268.55 seconds |
| Started | Aug 24 05:52:54 AM UTC 24 |
| Finished | Aug 24 05:57:26 AM UTC 24 |
| Peak memory | 597832 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2079445100 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.xbar_stress_all_with_reset_error.2079445100 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/38.xbar_stress_all_with_reset_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/38.xbar_unmapped_addr.2744949175 |
| Short name | T1831 |
| Test name | |
| Test status | |
| Simulation time | 462630843 ps |
| CPU time | 16.3 seconds |
| Started | Aug 24 05:52:23 AM UTC 24 |
| Finished | Aug 24 05:52:40 AM UTC 24 |
| Peak memory | 597696 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2744949175 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.xbar_unmapped_addr.2744949175 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/38.xbar_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/39.xbar_access_same_device.2937383574 |
| Short name | T1852 |
| Test name | |
| Test status | |
| Simulation time | 3410435475 ps |
| CPU time | 98.4 seconds |
| Started | Aug 24 05:53:35 AM UTC 24 |
| Finished | Aug 24 05:55:15 AM UTC 24 |
| Peak memory | 598084 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2937383574 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.xbar_access_same_device.2937383574 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/39.xbar_access_same_device/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/39.xbar_access_same_device_slow_rsp.3090594251 |
| Short name | T1947 |
| Test name | |
| Test status | |
| Simulation time | 45129079612 ps |
| CPU time | 564.92 seconds |
| Started | Aug 24 05:53:38 AM UTC 24 |
| Finished | Aug 24 06:03:09 AM UTC 24 |
| Peak memory | 598140 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3090594251 -assert nopostproc +UVM_T ESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.xbar_access_same_device_slow_rsp.3090594251 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/39.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/39.xbar_error_and_unmapped_addr.3586154892 |
| Short name | T1849 |
| Test name | |
| Test status | |
| Simulation time | 1444553524 ps |
| CPU time | 38.62 seconds |
| Started | Aug 24 05:54:20 AM UTC 24 |
| Finished | Aug 24 05:55:00 AM UTC 24 |
| Peak memory | 597696 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3586154892 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.xbar_error_and_unmapped_addr.3586154892 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/39.xbar_error_and_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/39.xbar_error_random.3304800280 |
| Short name | T1845 |
| Test name | |
| Test status | |
| Simulation time | 419073979 ps |
| CPU time | 24.29 seconds |
| Started | Aug 24 05:53:53 AM UTC 24 |
| Finished | Aug 24 05:54:18 AM UTC 24 |
| Peak memory | 597700 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3304800280 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.xbar_error_random.3304800280 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/39.xbar_error_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/39.xbar_random.618083298 |
| Short name | T1842 |
| Test name | |
| Test status | |
| Simulation time | 1325891071 ps |
| CPU time | 33.81 seconds |
| Started | Aug 24 05:53:30 AM UTC 24 |
| Finished | Aug 24 05:54:06 AM UTC 24 |
| Peak memory | 597692 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=618083298 -assert nopostproc +UVM_TESTNAME =xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 8_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.xbar_random.618083298 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/39.xbar_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/39.xbar_random_large_delays.2954955841 |
| Short name | T1994 |
| Test name | |
| Test status | |
| Simulation time | 102517786838 ps |
| CPU time | 830.32 seconds |
| Started | Aug 24 05:53:31 AM UTC 24 |
| Finished | Aug 24 06:07:30 AM UTC 24 |
| Peak memory | 598468 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max _device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2954955841 -assert nopostproc +U VM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.xbar_random_large_delays.2954955841 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/39.xbar_random_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/39.xbar_random_slow_rsp.3246287550 |
| Short name | T1864 |
| Test name | |
| Test status | |
| Simulation time | 13082261905 ps |
| CPU time | 151.12 seconds |
| Started | Aug 24 05:53:32 AM UTC 24 |
| Finished | Aug 24 05:56:05 AM UTC 24 |
| Peak memory | 597820 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3246287550 -assert nopostproc +UVM_T ESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.xbar_random_slow_rsp.3246287550 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/39.xbar_random_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/39.xbar_random_zero_delays.1453383521 |
| Short name | T1840 |
| Test name | |
| Test status | |
| Simulation time | 43533787 ps |
| CPU time | 5.64 seconds |
| Started | Aug 24 05:53:31 AM UTC 24 |
| Finished | Aug 24 05:53:38 AM UTC 24 |
| Peak memory | 595856 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1453383521 -assert nopostpr oc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.xbar_random_zero_delays.1453383521 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/39.xbar_random_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/39.xbar_same_source.60845401 |
| Short name | T1841 |
| Test name | |
| Test status | |
| Simulation time | 279381118 ps |
| CPU time | 15.27 seconds |
| Started | Aug 24 05:53:46 AM UTC 24 |
| Finished | Aug 24 05:54:02 AM UTC 24 |
| Peak memory | 597700 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=60845401 -assert nopostproc +UVM_TESTNAME= xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.xbar_same_source.60845401 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/39.xbar_same_source/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/39.xbar_smoke.3385640195 |
| Short name | T1835 |
| Test name | |
| Test status | |
| Simulation time | 38991435 ps |
| CPU time | 4.71 seconds |
| Started | Aug 24 05:53:10 AM UTC 24 |
| Finished | Aug 24 05:53:16 AM UTC 24 |
| Peak memory | 595908 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3385640195 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 8_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.xbar_smoke.3385640195 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/39.xbar_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/39.xbar_smoke_large_delays.152608867 |
| Short name | T1846 |
| Test name | |
| Test status | |
| Simulation time | 9379164316 ps |
| CPU time | 79.29 seconds |
| Started | Aug 24 05:53:15 AM UTC 24 |
| Finished | Aug 24 05:54:36 AM UTC 24 |
| Peak memory | 595976 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max _device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=152608867 -assert nopostproc +UV M_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.xbar_smoke_large_delays.152608867 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/39.xbar_smoke_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/39.xbar_smoke_slow_rsp.1097767880 |
| Short name | T1843 |
| Test name | |
| Test status | |
| Simulation time | 4023994543 ps |
| CPU time | 48.28 seconds |
| Started | Aug 24 05:53:19 AM UTC 24 |
| Finished | Aug 24 05:54:09 AM UTC 24 |
| Peak memory | 595836 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1097767880 -assert nopostproc +UVM_T ESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.xbar_smoke_slow_rsp.1097767880 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/39.xbar_smoke_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/39.xbar_smoke_zero_delays.411744028 |
| Short name | T1838 |
| Test name | |
| Test status | |
| Simulation time | 43464580 ps |
| CPU time | 5.16 seconds |
| Started | Aug 24 05:53:14 AM UTC 24 |
| Finished | Aug 24 05:53:20 AM UTC 24 |
| Peak memory | 595884 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=411744028 -assert nopostpro c +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.xbar_smoke_zero_delays.411744028 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/39.xbar_smoke_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/39.xbar_stress_all.3441316479 |
| Short name | T1853 |
| Test name | |
| Test status | |
| Simulation time | 867159370 ps |
| CPU time | 52.04 seconds |
| Started | Aug 24 05:54:24 AM UTC 24 |
| Finished | Aug 24 05:55:17 AM UTC 24 |
| Peak memory | 597836 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3441316479 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.xbar_stress_all.3441316479 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/39.xbar_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/39.xbar_stress_all_with_error.180089637 |
| Short name | T1860 |
| Test name | |
| Test status | |
| Simulation time | 1642907830 ps |
| CPU time | 88.37 seconds |
| Started | Aug 24 05:54:32 AM UTC 24 |
| Finished | Aug 24 05:56:02 AM UTC 24 |
| Peak memory | 597696 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=180089637 -assert nopostproc +UVM_TESTNAME =xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.xbar_stress_all_with_error.180089637 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/39.xbar_stress_all_with_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/39.xbar_stress_all_with_rand_reset.3597962753 |
| Short name | T1927 |
| Test name | |
| Test status | |
| Simulation time | 8317821088 ps |
| CPU time | 421.38 seconds |
| Started | Aug 24 05:54:29 AM UTC 24 |
| Finished | Aug 24 06:01:35 AM UTC 24 |
| Peak memory | 597824 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3597962753 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.xbar_stress_all_with_rand_reset.3597962753 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/39.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/39.xbar_stress_all_with_reset_error.4285968801 |
| Short name | T1894 |
| Test name | |
| Test status | |
| Simulation time | 2726029000 ps |
| CPU time | 205.32 seconds |
| Started | Aug 24 05:54:50 AM UTC 24 |
| Finished | Aug 24 05:58:18 AM UTC 24 |
| Peak memory | 597764 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4285968801 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.xbar_stress_all_with_reset_error.4285968801 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/39.xbar_stress_all_with_reset_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/39.xbar_unmapped_addr.2918005975 |
| Short name | T1848 |
| Test name | |
| Test status | |
| Simulation time | 1179856294 ps |
| CPU time | 34.97 seconds |
| Started | Aug 24 05:54:16 AM UTC 24 |
| Finished | Aug 24 05:54:52 AM UTC 24 |
| Peak memory | 598008 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2918005975 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.xbar_unmapped_addr.2918005975 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/39.xbar_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/4.chip_csr_aliasing.838123487 |
| Short name | T2159 |
| Test name | |
| Test status | |
| Simulation time | 53328838880 ps |
| CPU time | 8303.52 seconds |
| Started | Aug 24 04:04:21 AM UTC 24 |
| Finished | Aug 24 06:24:07 AM UTC 24 |
| Peak memory | 655296 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +test_timeout_ns=120_000_000 +csr_aliasing +en_scb=0 + stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=838123487 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert - cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.chip_c sr_aliasing.838123487 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/4.chip_csr_aliasing/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/4.chip_csr_bit_bash.3472050173 |
| Short name | T1550 |
| Test name | |
| Test status | |
| Simulation time | 56274406974 ps |
| CPU time | 4044.93 seconds |
| Started | Aug 24 04:03:38 AM UTC 24 |
| Finished | Aug 24 05:11:43 AM UTC 24 |
| Peak memory | 620252 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +test_timeout_ns=120_000_000 +num_test_csrs=200 +csr_b it_bash +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/to ols/sim.tcl +ntb_random_seed=3472050173 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/nu ll -cm_name 4.chip_csr_bit_bash.3472050173 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/4.chip_csr_bit_bash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/4.chip_csr_mem_rw_with_rand_reset.1261301652 |
| Short name | T457 |
| Test name | |
| Test status | |
| Simulation time | 6774283890 ps |
| CPU time | 292.63 seconds |
| Started | Aug 24 04:08:14 AM UTC 24 |
| Finished | Aug 24 04:13:11 AM UTC 24 |
| Peak memory | 660380 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000 000000 +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/too ls/sim.tcl +ntb_random_seed=1261301652 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/nul l -cm_name 4.chip_csr_mem_rw_with_rand_reset.1261301652 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/4.chip_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/4.chip_same_csr_outstanding.1816302220 |
| Short name | T406 |
| Test name | |
| Test status | |
| Simulation time | 16852933106 ps |
| CPU time | 1133.33 seconds |
| Started | Aug 24 04:04:41 AM UTC 24 |
| Finished | Aug 24 04:23:47 AM UTC 24 |
| Peak memory | 613436 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +test_timeout_ns=120_000_000 +run_same_csr_outstanding +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim .tcl +ntb_random_seed=1816302220 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_ name 4.chip_same_csr_outstanding.1816302220 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/4.chip_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/4.chip_tl_errors.3454341950 |
| Short name | T565 |
| Test name | |
| Test status | |
| Simulation time | 3990371520 ps |
| CPU time | 172.35 seconds |
| Started | Aug 24 04:05:12 AM UTC 24 |
| Finished | Aug 24 04:08:07 AM UTC 24 |
| Peak memory | 623464 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enable d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3454341950 -assert nopostpro c +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.chip_tl_errors.3454341950 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/4.chip_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/4.xbar_access_same_device.2968096142 |
| Short name | T782 |
| Test name | |
| Test status | |
| Simulation time | 582623603 ps |
| CPU time | 35.13 seconds |
| Started | Aug 24 04:07:23 AM UTC 24 |
| Finished | Aug 24 04:08:00 AM UTC 24 |
| Peak memory | 597704 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2968096142 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.xbar_access_same_device.2968096142 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/4.xbar_access_same_device/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/4.xbar_access_same_device_slow_rsp.2130598676 |
| Short name | T783 |
| Test name | |
| Test status | |
| Simulation time | 10829404555 ps |
| CPU time | 123.97 seconds |
| Started | Aug 24 04:07:25 AM UTC 24 |
| Finished | Aug 24 04:09:32 AM UTC 24 |
| Peak memory | 596080 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2130598676 -assert nopostproc +UVM_T ESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.xbar_access_same_device_slow_rsp.2130598676 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/4.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/4.xbar_error_and_unmapped_addr.2878644909 |
| Short name | T1360 |
| Test name | |
| Test status | |
| Simulation time | 1053396906 ps |
| CPU time | 31.54 seconds |
| Started | Aug 24 04:07:37 AM UTC 24 |
| Finished | Aug 24 04:08:10 AM UTC 24 |
| Peak memory | 597696 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2878644909 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.xbar_error_and_unmapped_addr.2878644909 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/4.xbar_error_and_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/4.xbar_error_random.4268985336 |
| Short name | T1359 |
| Test name | |
| Test status | |
| Simulation time | 1127841548 ps |
| CPU time | 25.59 seconds |
| Started | Aug 24 04:07:33 AM UTC 24 |
| Finished | Aug 24 04:08:00 AM UTC 24 |
| Peak memory | 597692 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4268985336 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.xbar_error_random.4268985336 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/4.xbar_error_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/4.xbar_random.2763164669 |
| Short name | T613 |
| Test name | |
| Test status | |
| Simulation time | 68134742 ps |
| CPU time | 7.41 seconds |
| Started | Aug 24 04:06:50 AM UTC 24 |
| Finished | Aug 24 04:06:58 AM UTC 24 |
| Peak memory | 597752 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2763164669 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.xbar_random.2763164669 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/4.xbar_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/4.xbar_random_large_delays.3611451613 |
| Short name | T605 |
| Test name | |
| Test status | |
| Simulation time | 64232911562 ps |
| CPU time | 519.84 seconds |
| Started | Aug 24 04:07:13 AM UTC 24 |
| Finished | Aug 24 04:15:58 AM UTC 24 |
| Peak memory | 597820 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max _device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3611451613 -assert nopostproc +U VM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.xbar_random_large_delays.3611451613 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/4.xbar_random_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/4.xbar_random_slow_rsp.3912668552 |
| Short name | T480 |
| Test name | |
| Test status | |
| Simulation time | 51921879014 ps |
| CPU time | 615.54 seconds |
| Started | Aug 24 04:07:17 AM UTC 24 |
| Finished | Aug 24 04:17:39 AM UTC 24 |
| Peak memory | 597828 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3912668552 -assert nopostproc +UVM_T ESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.xbar_random_slow_rsp.3912668552 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/4.xbar_random_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/4.xbar_random_zero_delays.1343882739 |
| Short name | T467 |
| Test name | |
| Test status | |
| Simulation time | 105740213 ps |
| CPU time | 9.8 seconds |
| Started | Aug 24 04:06:58 AM UTC 24 |
| Finished | Aug 24 04:07:09 AM UTC 24 |
| Peak memory | 597904 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1343882739 -assert nopostpr oc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.xbar_random_zero_delays.1343882739 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/4.xbar_random_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/4.xbar_same_source.3392157112 |
| Short name | T618 |
| Test name | |
| Test status | |
| Simulation time | 850807986 ps |
| CPU time | 19.52 seconds |
| Started | Aug 24 04:07:25 AM UTC 24 |
| Finished | Aug 24 04:07:46 AM UTC 24 |
| Peak memory | 597760 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3392157112 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.xbar_same_source.3392157112 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/4.xbar_same_source/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/4.xbar_smoke.3189237267 |
| Short name | T1356 |
| Test name | |
| Test status | |
| Simulation time | 45386165 ps |
| CPU time | 5.16 seconds |
| Started | Aug 24 04:05:13 AM UTC 24 |
| Finished | Aug 24 04:05:20 AM UTC 24 |
| Peak memory | 595628 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3189237267 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 8_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.xbar_smoke.3189237267 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/4.xbar_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/4.xbar_smoke_large_delays.315237731 |
| Short name | T570 |
| Test name | |
| Test status | |
| Simulation time | 8932748622 ps |
| CPU time | 75.47 seconds |
| Started | Aug 24 04:05:54 AM UTC 24 |
| Finished | Aug 24 04:07:11 AM UTC 24 |
| Peak memory | 595760 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max _device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=315237731 -assert nopostproc +UV M_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.xbar_smoke_large_delays.315237731 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/4.xbar_smoke_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/4.xbar_smoke_slow_rsp.2742670787 |
| Short name | T1358 |
| Test name | |
| Test status | |
| Simulation time | 6178233879 ps |
| CPU time | 70.53 seconds |
| Started | Aug 24 04:06:37 AM UTC 24 |
| Finished | Aug 24 04:07:49 AM UTC 24 |
| Peak memory | 596148 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2742670787 -assert nopostproc +UVM_T ESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.xbar_smoke_slow_rsp.2742670787 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/4.xbar_smoke_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/4.xbar_smoke_zero_delays.1559567517 |
| Short name | T1357 |
| Test name | |
| Test status | |
| Simulation time | 44030885 ps |
| CPU time | 5.23 seconds |
| Started | Aug 24 04:05:33 AM UTC 24 |
| Finished | Aug 24 04:05:40 AM UTC 24 |
| Peak memory | 595636 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1559567517 -assert nopostpr oc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.xbar_smoke_zero_delays.1559567517 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/4.xbar_smoke_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/4.xbar_stress_all.3793331683 |
| Short name | T485 |
| Test name | |
| Test status | |
| Simulation time | 1519550467 ps |
| CPU time | 104.95 seconds |
| Started | Aug 24 04:07:44 AM UTC 24 |
| Finished | Aug 24 04:09:30 AM UTC 24 |
| Peak memory | 597696 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3793331683 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.xbar_stress_all.3793331683 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/4.xbar_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/4.xbar_stress_all_with_error.4169152487 |
| Short name | T641 |
| Test name | |
| Test status | |
| Simulation time | 1937619128 ps |
| CPU time | 110.99 seconds |
| Started | Aug 24 04:08:04 AM UTC 24 |
| Finished | Aug 24 04:09:57 AM UTC 24 |
| Peak memory | 597700 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4169152487 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.xbar_stress_all_with_error.4169152487 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/4.xbar_stress_all_with_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/4.xbar_stress_all_with_rand_reset.2747777259 |
| Short name | T521 |
| Test name | |
| Test status | |
| Simulation time | 397752491 ps |
| CPU time | 127.67 seconds |
| Started | Aug 24 04:08:01 AM UTC 24 |
| Finished | Aug 24 04:10:11 AM UTC 24 |
| Peak memory | 597820 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2747777259 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.xbar_stress_all_with_rand_reset.2747777259 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/4.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/4.xbar_stress_all_with_reset_error.1563665665 |
| Short name | T1362 |
| Test name | |
| Test status | |
| Simulation time | 145502300 ps |
| CPU time | 34.88 seconds |
| Started | Aug 24 04:08:11 AM UTC 24 |
| Finished | Aug 24 04:08:47 AM UTC 24 |
| Peak memory | 597692 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1563665665 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.xbar_stress_all_with_reset_error.1563665665 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/4.xbar_stress_all_with_reset_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/4.xbar_unmapped_addr.3951109626 |
| Short name | T620 |
| Test name | |
| Test status | |
| Simulation time | 222582192 ps |
| CPU time | 21.25 seconds |
| Started | Aug 24 04:07:36 AM UTC 24 |
| Finished | Aug 24 04:07:59 AM UTC 24 |
| Peak memory | 597696 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3951109626 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.xbar_unmapped_addr.3951109626 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/4.xbar_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/40.xbar_access_same_device.3046883105 |
| Short name | T1869 |
| Test name | |
| Test status | |
| Simulation time | 1768536603 ps |
| CPU time | 50.38 seconds |
| Started | Aug 24 05:55:35 AM UTC 24 |
| Finished | Aug 24 05:56:27 AM UTC 24 |
| Peak memory | 597704 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3046883105 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.xbar_access_same_device.3046883105 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/40.xbar_access_same_device/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/40.xbar_access_same_device_slow_rsp.3749451329 |
| Short name | T2081 |
| Test name | |
| Test status | |
| Simulation time | 107925148473 ps |
| CPU time | 1235.35 seconds |
| Started | Aug 24 05:55:40 AM UTC 24 |
| Finished | Aug 24 06:16:27 AM UTC 24 |
| Peak memory | 599044 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3749451329 -assert nopostproc +UVM_T ESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.xbar_access_same_device_slow_rsp.3749451329 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/40.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/40.xbar_error_and_unmapped_addr.932558043 |
| Short name | T1872 |
| Test name | |
| Test status | |
| Simulation time | 313647175 ps |
| CPU time | 23.96 seconds |
| Started | Aug 24 05:56:10 AM UTC 24 |
| Finished | Aug 24 05:56:35 AM UTC 24 |
| Peak memory | 597940 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=932558043 -assert nopostproc +UVM_TESTNAME =xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.xbar_error_and_unmapped_addr.932558043 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/40.xbar_error_and_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/40.xbar_error_random.185850028 |
| Short name | T1870 |
| Test name | |
| Test status | |
| Simulation time | 1413405957 ps |
| CPU time | 31.32 seconds |
| Started | Aug 24 05:55:55 AM UTC 24 |
| Finished | Aug 24 05:56:27 AM UTC 24 |
| Peak memory | 597764 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=185850028 -assert nopostproc +UVM_TESTNAME =xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.xbar_error_random.185850028 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/40.xbar_error_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/40.xbar_random.1286426436 |
| Short name | T1866 |
| Test name | |
| Test status | |
| Simulation time | 2462156217 ps |
| CPU time | 59.21 seconds |
| Started | Aug 24 05:55:21 AM UTC 24 |
| Finished | Aug 24 05:56:21 AM UTC 24 |
| Peak memory | 597820 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1286426436 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.xbar_random.1286426436 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/40.xbar_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/40.xbar_random_large_delays.2427764632 |
| Short name | T1900 |
| Test name | |
| Test status | |
| Simulation time | 25659728539 ps |
| CPU time | 208 seconds |
| Started | Aug 24 05:55:29 AM UTC 24 |
| Finished | Aug 24 05:59:00 AM UTC 24 |
| Peak memory | 597820 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max _device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2427764632 -assert nopostproc +U VM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.xbar_random_large_delays.2427764632 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/40.xbar_random_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/40.xbar_random_slow_rsp.2828932845 |
| Short name | T1861 |
| Test name | |
| Test status | |
| Simulation time | 2438155868 ps |
| CPU time | 30.05 seconds |
| Started | Aug 24 05:55:32 AM UTC 24 |
| Finished | Aug 24 05:56:03 AM UTC 24 |
| Peak memory | 595956 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2828932845 -assert nopostproc +UVM_T ESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.xbar_random_slow_rsp.2828932845 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/40.xbar_random_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/40.xbar_random_zero_delays.2595431620 |
| Short name | T1856 |
| Test name | |
| Test status | |
| Simulation time | 37826623 ps |
| CPU time | 4.84 seconds |
| Started | Aug 24 05:55:27 AM UTC 24 |
| Finished | Aug 24 05:55:32 AM UTC 24 |
| Peak memory | 595712 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2595431620 -assert nopostpr oc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.xbar_random_zero_delays.2595431620 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/40.xbar_random_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/40.xbar_same_source.1405287981 |
| Short name | T1865 |
| Test name | |
| Test status | |
| Simulation time | 563130771 ps |
| CPU time | 29.23 seconds |
| Started | Aug 24 05:55:47 AM UTC 24 |
| Finished | Aug 24 05:56:17 AM UTC 24 |
| Peak memory | 597868 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1405287981 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.xbar_same_source.1405287981 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/40.xbar_same_source/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/40.xbar_smoke.3557665466 |
| Short name | T1850 |
| Test name | |
| Test status | |
| Simulation time | 156166327 ps |
| CPU time | 6.12 seconds |
| Started | Aug 24 05:54:59 AM UTC 24 |
| Finished | Aug 24 05:55:07 AM UTC 24 |
| Peak memory | 595916 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3557665466 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 8_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.xbar_smoke.3557665466 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/40.xbar_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/40.xbar_smoke_large_delays.3865106613 |
| Short name | T1863 |
| Test name | |
| Test status | |
| Simulation time | 5884757170 ps |
| CPU time | 48.06 seconds |
| Started | Aug 24 05:55:14 AM UTC 24 |
| Finished | Aug 24 05:56:04 AM UTC 24 |
| Peak memory | 595764 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max _device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3865106613 -assert nopostproc +U VM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.xbar_smoke_large_delays.3865106613 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/40.xbar_smoke_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/40.xbar_smoke_slow_rsp.3741161159 |
| Short name | T1867 |
| Test name | |
| Test status | |
| Simulation time | 5028945667 ps |
| CPU time | 60.51 seconds |
| Started | Aug 24 05:55:19 AM UTC 24 |
| Finished | Aug 24 05:56:22 AM UTC 24 |
| Peak memory | 596088 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3741161159 -assert nopostproc +UVM_T ESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.xbar_smoke_slow_rsp.3741161159 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/40.xbar_smoke_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/40.xbar_smoke_zero_delays.3267217150 |
| Short name | T1851 |
| Test name | |
| Test status | |
| Simulation time | 47569824 ps |
| CPU time | 5.12 seconds |
| Started | Aug 24 05:55:06 AM UTC 24 |
| Finished | Aug 24 05:55:12 AM UTC 24 |
| Peak memory | 595632 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3267217150 -assert nopostpr oc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.xbar_smoke_zero_delays.3267217150 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/40.xbar_smoke_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/40.xbar_stress_all.3106912630 |
| Short name | T1879 |
| Test name | |
| Test status | |
| Simulation time | 1179633185 ps |
| CPU time | 65.17 seconds |
| Started | Aug 24 05:56:16 AM UTC 24 |
| Finished | Aug 24 05:57:23 AM UTC 24 |
| Peak memory | 597956 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3106912630 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.xbar_stress_all.3106912630 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/40.xbar_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/40.xbar_stress_all_with_error.3784429875 |
| Short name | T1871 |
| Test name | |
| Test status | |
| Simulation time | 209747970 ps |
| CPU time | 11.32 seconds |
| Started | Aug 24 05:56:17 AM UTC 24 |
| Finished | Aug 24 05:56:29 AM UTC 24 |
| Peak memory | 597948 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3784429875 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.xbar_stress_all_with_error.3784429875 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/40.xbar_stress_all_with_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/40.xbar_stress_all_with_rand_reset.2026341492 |
| Short name | T838 |
| Test name | |
| Test status | |
| Simulation time | 5399791557 ps |
| CPU time | 302.05 seconds |
| Started | Aug 24 05:56:17 AM UTC 24 |
| Finished | Aug 24 06:01:23 AM UTC 24 |
| Peak memory | 597824 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2026341492 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.xbar_stress_all_with_rand_reset.2026341492 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/40.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/40.xbar_stress_all_with_reset_error.3487581383 |
| Short name | T1915 |
| Test name | |
| Test status | |
| Simulation time | 3050345616 ps |
| CPU time | 255.02 seconds |
| Started | Aug 24 05:56:18 AM UTC 24 |
| Finished | Aug 24 06:00:36 AM UTC 24 |
| Peak memory | 598052 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3487581383 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.xbar_stress_all_with_reset_error.3487581383 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/40.xbar_stress_all_with_reset_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/40.xbar_unmapped_addr.1397623105 |
| Short name | T1862 |
| Test name | |
| Test status | |
| Simulation time | 44842679 ps |
| CPU time | 6.41 seconds |
| Started | Aug 24 05:55:56 AM UTC 24 |
| Finished | Aug 24 05:56:03 AM UTC 24 |
| Peak memory | 595648 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1397623105 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.xbar_unmapped_addr.1397623105 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/40.xbar_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/41.xbar_access_same_device.2989937202 |
| Short name | T1876 |
| Test name | |
| Test status | |
| Simulation time | 673729699 ps |
| CPU time | 20.61 seconds |
| Started | Aug 24 05:56:49 AM UTC 24 |
| Finished | Aug 24 05:57:11 AM UTC 24 |
| Peak memory | 597924 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2989937202 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.xbar_access_same_device.2989937202 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/41.xbar_access_same_device/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/41.xbar_access_same_device_slow_rsp.858131178 |
| Short name | T2019 |
| Test name | |
| Test status | |
| Simulation time | 67441784700 ps |
| CPU time | 766.65 seconds |
| Started | Aug 24 05:56:52 AM UTC 24 |
| Finished | Aug 24 06:09:46 AM UTC 24 |
| Peak memory | 598036 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=858131178 -assert nopostproc +UVM_TE STNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os _regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.xbar_access_same_device_slow_rsp.858131178 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/41.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/41.xbar_error_and_unmapped_addr.1587711894 |
| Short name | T1886 |
| Test name | |
| Test status | |
| Simulation time | 355917372 ps |
| CPU time | 12.23 seconds |
| Started | Aug 24 05:57:31 AM UTC 24 |
| Finished | Aug 24 05:57:44 AM UTC 24 |
| Peak memory | 597904 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1587711894 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.xbar_error_and_unmapped_addr.1587711894 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/41.xbar_error_and_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/41.xbar_error_random.4287774830 |
| Short name | T1877 |
| Test name | |
| Test status | |
| Simulation time | 158679030 ps |
| CPU time | 10.33 seconds |
| Started | Aug 24 05:57:05 AM UTC 24 |
| Finished | Aug 24 05:57:16 AM UTC 24 |
| Peak memory | 597688 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4287774830 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.xbar_error_random.4287774830 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/41.xbar_error_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/41.xbar_random.605961233 |
| Short name | T1881 |
| Test name | |
| Test status | |
| Simulation time | 1958304319 ps |
| CPU time | 45.57 seconds |
| Started | Aug 24 05:56:39 AM UTC 24 |
| Finished | Aug 24 05:57:26 AM UTC 24 |
| Peak memory | 597700 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=605961233 -assert nopostproc +UVM_TESTNAME =xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 8_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.xbar_random.605961233 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/41.xbar_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/41.xbar_random_large_delays.1036852755 |
| Short name | T1910 |
| Test name | |
| Test status | |
| Simulation time | 26122173881 ps |
| CPU time | 208.38 seconds |
| Started | Aug 24 05:56:41 AM UTC 24 |
| Finished | Aug 24 06:00:12 AM UTC 24 |
| Peak memory | 597820 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max _device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1036852755 -assert nopostproc +U VM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.xbar_random_large_delays.1036852755 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/41.xbar_random_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/41.xbar_random_slow_rsp.1277412796 |
| Short name | T2006 |
| Test name | |
| Test status | |
| Simulation time | 59122089305 ps |
| CPU time | 704.16 seconds |
| Started | Aug 24 05:56:43 AM UTC 24 |
| Finished | Aug 24 06:08:35 AM UTC 24 |
| Peak memory | 598136 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1277412796 -assert nopostproc +UVM_T ESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.xbar_random_slow_rsp.1277412796 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/41.xbar_random_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/41.xbar_random_zero_delays.1138939245 |
| Short name | T1875 |
| Test name | |
| Test status | |
| Simulation time | 95943807 ps |
| CPU time | 8.23 seconds |
| Started | Aug 24 05:56:41 AM UTC 24 |
| Finished | Aug 24 05:56:51 AM UTC 24 |
| Peak memory | 597836 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1138939245 -assert nopostpr oc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.xbar_random_zero_delays.1138939245 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/41.xbar_random_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/41.xbar_same_source.375948875 |
| Short name | T1878 |
| Test name | |
| Test status | |
| Simulation time | 1095595121 ps |
| CPU time | 24.57 seconds |
| Started | Aug 24 05:56:54 AM UTC 24 |
| Finished | Aug 24 05:57:20 AM UTC 24 |
| Peak memory | 597692 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=375948875 -assert nopostproc +UVM_TESTNAME =xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.xbar_same_source.375948875 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/41.xbar_same_source/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/41.xbar_smoke.3719717242 |
| Short name | T1868 |
| Test name | |
| Test status | |
| Simulation time | 54092841 ps |
| CPU time | 5.18 seconds |
| Started | Aug 24 05:56:19 AM UTC 24 |
| Finished | Aug 24 05:56:25 AM UTC 24 |
| Peak memory | 595884 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3719717242 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 8_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.xbar_smoke.3719717242 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/41.xbar_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/41.xbar_smoke_large_delays.856688493 |
| Short name | T1889 |
| Test name | |
| Test status | |
| Simulation time | 8589908999 ps |
| CPU time | 71.69 seconds |
| Started | Aug 24 05:56:35 AM UTC 24 |
| Finished | Aug 24 05:57:49 AM UTC 24 |
| Peak memory | 595764 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max _device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=856688493 -assert nopostproc +UV M_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.xbar_smoke_large_delays.856688493 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/41.xbar_smoke_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/41.xbar_smoke_slow_rsp.1980146619 |
| Short name | T1885 |
| Test name | |
| Test status | |
| Simulation time | 5244846558 ps |
| CPU time | 63.83 seconds |
| Started | Aug 24 05:56:35 AM UTC 24 |
| Finished | Aug 24 05:57:41 AM UTC 24 |
| Peak memory | 595772 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1980146619 -assert nopostproc +UVM_T ESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.xbar_smoke_slow_rsp.1980146619 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/41.xbar_smoke_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/41.xbar_smoke_zero_delays.2109179585 |
| Short name | T1873 |
| Test name | |
| Test status | |
| Simulation time | 45515066 ps |
| CPU time | 4.96 seconds |
| Started | Aug 24 05:56:31 AM UTC 24 |
| Finished | Aug 24 05:56:37 AM UTC 24 |
| Peak memory | 595636 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2109179585 -assert nopostpr oc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.xbar_smoke_zero_delays.2109179585 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/41.xbar_smoke_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/41.xbar_stress_all.2942145432 |
| Short name | T1883 |
| Test name | |
| Test status | |
| Simulation time | 5796635 ps |
| CPU time | 3.26 seconds |
| Started | Aug 24 05:57:34 AM UTC 24 |
| Finished | Aug 24 05:57:38 AM UTC 24 |
| Peak memory | 584480 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2942145432 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.xbar_stress_all.2942145432 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/41.xbar_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/41.xbar_stress_all_with_error.1132553266 |
| Short name | T1935 |
| Test name | |
| Test status | |
| Simulation time | 12087509621 ps |
| CPU time | 281.32 seconds |
| Started | Aug 24 05:57:37 AM UTC 24 |
| Finished | Aug 24 06:02:22 AM UTC 24 |
| Peak memory | 598148 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1132553266 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.xbar_stress_all_with_error.1132553266 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/41.xbar_stress_all_with_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/41.xbar_stress_all_with_rand_reset.3470940795 |
| Short name | T1902 |
| Test name | |
| Test status | |
| Simulation time | 370927508 ps |
| CPU time | 96.61 seconds |
| Started | Aug 24 05:57:37 AM UTC 24 |
| Finished | Aug 24 05:59:15 AM UTC 24 |
| Peak memory | 597904 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3470940795 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.xbar_stress_all_with_rand_reset.3470940795 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/41.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/41.xbar_stress_all_with_reset_error.2584862833 |
| Short name | T1912 |
| Test name | |
| Test status | |
| Simulation time | 3278371153 ps |
| CPU time | 156.11 seconds |
| Started | Aug 24 05:57:40 AM UTC 24 |
| Finished | Aug 24 06:00:19 AM UTC 24 |
| Peak memory | 597912 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2584862833 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.xbar_stress_all_with_reset_error.2584862833 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/41.xbar_stress_all_with_reset_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/41.xbar_unmapped_addr.2151445324 |
| Short name | T1891 |
| Test name | |
| Test status | |
| Simulation time | 332751654 ps |
| CPU time | 27.54 seconds |
| Started | Aug 24 05:57:26 AM UTC 24 |
| Finished | Aug 24 05:57:55 AM UTC 24 |
| Peak memory | 597944 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2151445324 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.xbar_unmapped_addr.2151445324 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/41.xbar_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/42.xbar_access_same_device.214252556 |
| Short name | T1893 |
| Test name | |
| Test status | |
| Simulation time | 115160038 ps |
| CPU time | 8.93 seconds |
| Started | Aug 24 05:58:02 AM UTC 24 |
| Finished | Aug 24 05:58:12 AM UTC 24 |
| Peak memory | 597704 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=214252556 -assert nopostproc +UVM_TESTNAME =xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.xbar_access_same_device.214252556 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/42.xbar_access_same_device/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/42.xbar_access_same_device_slow_rsp.1045805751 |
| Short name | T2186 |
| Test name | |
| Test status | |
| Simulation time | 150237371662 ps |
| CPU time | 1676.94 seconds |
| Started | Aug 24 05:58:09 AM UTC 24 |
| Finished | Aug 24 06:26:22 AM UTC 24 |
| Peak memory | 599176 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1045805751 -assert nopostproc +UVM_T ESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.xbar_access_same_device_slow_rsp.1045805751 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/42.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/42.xbar_error_and_unmapped_addr.1484428610 |
| Short name | T1901 |
| Test name | |
| Test status | |
| Simulation time | 1054624150 ps |
| CPU time | 27.95 seconds |
| Started | Aug 24 05:58:33 AM UTC 24 |
| Finished | Aug 24 05:59:02 AM UTC 24 |
| Peak memory | 597840 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1484428610 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.xbar_error_and_unmapped_addr.1484428610 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/42.xbar_error_and_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/42.xbar_error_random.2994589212 |
| Short name | T1899 |
| Test name | |
| Test status | |
| Simulation time | 1171886632 ps |
| CPU time | 30.22 seconds |
| Started | Aug 24 05:58:25 AM UTC 24 |
| Finished | Aug 24 05:58:56 AM UTC 24 |
| Peak memory | 597752 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2994589212 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.xbar_error_random.2994589212 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/42.xbar_error_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/42.xbar_random.2362768001 |
| Short name | T1892 |
| Test name | |
| Test status | |
| Simulation time | 508159325 ps |
| CPU time | 13.99 seconds |
| Started | Aug 24 05:57:55 AM UTC 24 |
| Finished | Aug 24 05:58:10 AM UTC 24 |
| Peak memory | 597828 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2362768001 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.xbar_random.2362768001 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/42.xbar_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/42.xbar_random_large_delays.3066500284 |
| Short name | T1926 |
| Test name | |
| Test status | |
| Simulation time | 25183895682 ps |
| CPU time | 204.61 seconds |
| Started | Aug 24 05:58:01 AM UTC 24 |
| Finished | Aug 24 06:01:29 AM UTC 24 |
| Peak memory | 597816 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max _device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3066500284 -assert nopostproc +U VM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.xbar_random_large_delays.3066500284 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/42.xbar_random_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/42.xbar_random_slow_rsp.2936687592 |
| Short name | T1908 |
| Test name | |
| Test status | |
| Simulation time | 10481736189 ps |
| CPU time | 118.63 seconds |
| Started | Aug 24 05:58:01 AM UTC 24 |
| Finished | Aug 24 06:00:02 AM UTC 24 |
| Peak memory | 597944 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2936687592 -assert nopostproc +UVM_T ESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.xbar_random_slow_rsp.2936687592 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/42.xbar_random_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/42.xbar_random_zero_delays.1894168131 |
| Short name | T1895 |
| Test name | |
| Test status | |
| Simulation time | 438206596 ps |
| CPU time | 27.23 seconds |
| Started | Aug 24 05:57:59 AM UTC 24 |
| Finished | Aug 24 05:58:27 AM UTC 24 |
| Peak memory | 597700 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1894168131 -assert nopostpr oc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.xbar_random_zero_delays.1894168131 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/42.xbar_random_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/42.xbar_same_source.795498125 |
| Short name | T1897 |
| Test name | |
| Test status | |
| Simulation time | 1411581033 ps |
| CPU time | 28.95 seconds |
| Started | Aug 24 05:58:09 AM UTC 24 |
| Finished | Aug 24 05:58:39 AM UTC 24 |
| Peak memory | 597696 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=795498125 -assert nopostproc +UVM_TESTNAME =xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.xbar_same_source.795498125 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/42.xbar_same_source/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/42.xbar_smoke.3002180004 |
| Short name | T1887 |
| Test name | |
| Test status | |
| Simulation time | 174374968 ps |
| CPU time | 6.22 seconds |
| Started | Aug 24 05:57:40 AM UTC 24 |
| Finished | Aug 24 05:57:47 AM UTC 24 |
| Peak memory | 595628 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3002180004 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 8_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.xbar_smoke.3002180004 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/42.xbar_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/42.xbar_smoke_large_delays.1576987380 |
| Short name | T1904 |
| Test name | |
| Test status | |
| Simulation time | 10384051401 ps |
| CPU time | 83.57 seconds |
| Started | Aug 24 05:57:52 AM UTC 24 |
| Finished | Aug 24 05:59:17 AM UTC 24 |
| Peak memory | 595764 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max _device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1576987380 -assert nopostproc +U VM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.xbar_smoke_large_delays.1576987380 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/42.xbar_smoke_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/42.xbar_smoke_slow_rsp.3657969089 |
| Short name | T1898 |
| Test name | |
| Test status | |
| Simulation time | 4210727713 ps |
| CPU time | 50.75 seconds |
| Started | Aug 24 05:57:53 AM UTC 24 |
| Finished | Aug 24 05:58:45 AM UTC 24 |
| Peak memory | 595708 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3657969089 -assert nopostproc +UVM_T ESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.xbar_smoke_slow_rsp.3657969089 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/42.xbar_smoke_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/42.xbar_smoke_zero_delays.2665936260 |
| Short name | T1888 |
| Test name | |
| Test status | |
| Simulation time | 37648413 ps |
| CPU time | 5 seconds |
| Started | Aug 24 05:57:41 AM UTC 24 |
| Finished | Aug 24 05:57:47 AM UTC 24 |
| Peak memory | 595876 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2665936260 -assert nopostpr oc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.xbar_smoke_zero_delays.2665936260 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/42.xbar_smoke_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/42.xbar_stress_all.3999875451 |
| Short name | T1945 |
| Test name | |
| Test status | |
| Simulation time | 4276718464 ps |
| CPU time | 255.21 seconds |
| Started | Aug 24 05:58:41 AM UTC 24 |
| Finished | Aug 24 06:03:00 AM UTC 24 |
| Peak memory | 597896 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3999875451 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.xbar_stress_all.3999875451 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/42.xbar_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/42.xbar_stress_all_with_error.390514419 |
| Short name | T1909 |
| Test name | |
| Test status | |
| Simulation time | 3171828049 ps |
| CPU time | 73.03 seconds |
| Started | Aug 24 05:58:53 AM UTC 24 |
| Finished | Aug 24 06:00:08 AM UTC 24 |
| Peak memory | 597824 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=390514419 -assert nopostproc +UVM_TESTNAME =xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.xbar_stress_all_with_error.390514419 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/42.xbar_stress_all_with_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/42.xbar_stress_all_with_reset_error.761882433 |
| Short name | T1950 |
| Test name | |
| Test status | |
| Simulation time | 3675548062 ps |
| CPU time | 275.19 seconds |
| Started | Aug 24 05:58:59 AM UTC 24 |
| Finished | Aug 24 06:03:38 AM UTC 24 |
| Peak memory | 597760 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=761882433 -assert nopostproc +UVM_TESTNAME =xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.xbar_stress_all_with_reset_error.761882433 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/42.xbar_stress_all_with_reset_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/42.xbar_unmapped_addr.2498503119 |
| Short name | T1896 |
| Test name | |
| Test status | |
| Simulation time | 80359459 ps |
| CPU time | 9.06 seconds |
| Started | Aug 24 05:58:27 AM UTC 24 |
| Finished | Aug 24 05:58:37 AM UTC 24 |
| Peak memory | 597832 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2498503119 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.xbar_unmapped_addr.2498503119 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/42.xbar_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/43.xbar_access_same_device.488556725 |
| Short name | T1919 |
| Test name | |
| Test status | |
| Simulation time | 1171430965 ps |
| CPU time | 36.11 seconds |
| Started | Aug 24 06:00:15 AM UTC 24 |
| Finished | Aug 24 06:00:52 AM UTC 24 |
| Peak memory | 597848 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=488556725 -assert nopostproc +UVM_TESTNAME =xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.xbar_access_same_device.488556725 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/43.xbar_access_same_device/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/43.xbar_access_same_device_slow_rsp.2127374121 |
| Short name | T2152 |
| Test name | |
| Test status | |
| Simulation time | 120071635562 ps |
| CPU time | 1385.35 seconds |
| Started | Aug 24 06:00:21 AM UTC 24 |
| Finished | Aug 24 06:23:40 AM UTC 24 |
| Peak memory | 599036 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2127374121 -assert nopostproc +UVM_T ESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.xbar_access_same_device_slow_rsp.2127374121 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/43.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/43.xbar_error_and_unmapped_addr.1955420437 |
| Short name | T1917 |
| Test name | |
| Test status | |
| Simulation time | 63214041 ps |
| CPU time | 5.02 seconds |
| Started | Aug 24 06:00:33 AM UTC 24 |
| Finished | Aug 24 06:00:39 AM UTC 24 |
| Peak memory | 595792 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1955420437 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.xbar_error_and_unmapped_addr.1955420437 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/43.xbar_error_and_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/43.xbar_error_random.3607987249 |
| Short name | T1918 |
| Test name | |
| Test status | |
| Simulation time | 545068359 ps |
| CPU time | 14.03 seconds |
| Started | Aug 24 06:00:27 AM UTC 24 |
| Finished | Aug 24 06:00:42 AM UTC 24 |
| Peak memory | 597920 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3607987249 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.xbar_error_random.3607987249 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/43.xbar_error_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/43.xbar_random.782335162 |
| Short name | T1911 |
| Test name | |
| Test status | |
| Simulation time | 1716092009 ps |
| CPU time | 42.98 seconds |
| Started | Aug 24 05:59:30 AM UTC 24 |
| Finished | Aug 24 06:00:15 AM UTC 24 |
| Peak memory | 597912 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=782335162 -assert nopostproc +UVM_TESTNAME =xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 8_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.xbar_random.782335162 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/43.xbar_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/43.xbar_random_large_delays.401043508 |
| Short name | T1985 |
| Test name | |
| Test status | |
| Simulation time | 53387740293 ps |
| CPU time | 418.12 seconds |
| Started | Aug 24 05:59:34 AM UTC 24 |
| Finished | Aug 24 06:06:37 AM UTC 24 |
| Peak memory | 597820 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max _device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=401043508 -assert nopostproc +UV M_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.xbar_random_large_delays.401043508 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/43.xbar_random_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/43.xbar_random_slow_rsp.875522790 |
| Short name | T1998 |
| Test name | |
| Test status | |
| Simulation time | 40904926331 ps |
| CPU time | 480.6 seconds |
| Started | Aug 24 05:59:59 AM UTC 24 |
| Finished | Aug 24 06:08:05 AM UTC 24 |
| Peak memory | 597828 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=875522790 -assert nopostproc +UVM_TE STNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.xbar_random_slow_rsp.875522790 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/43.xbar_random_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/43.xbar_random_zero_delays.4291353268 |
| Short name | T1906 |
| Test name | |
| Test status | |
| Simulation time | 172491906 ps |
| CPU time | 12.88 seconds |
| Started | Aug 24 05:59:31 AM UTC 24 |
| Finished | Aug 24 05:59:45 AM UTC 24 |
| Peak memory | 597700 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4291353268 -assert nopostpr oc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.xbar_random_zero_delays.4291353268 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/43.xbar_random_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/43.xbar_same_source.4105696341 |
| Short name | T1921 |
| Test name | |
| Test status | |
| Simulation time | 1993076610 ps |
| CPU time | 39.09 seconds |
| Started | Aug 24 06:00:22 AM UTC 24 |
| Finished | Aug 24 06:01:02 AM UTC 24 |
| Peak memory | 597924 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4105696341 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.xbar_same_source.4105696341 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/43.xbar_same_source/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/43.xbar_smoke.4106733805 |
| Short name | T1903 |
| Test name | |
| Test status | |
| Simulation time | 44577527 ps |
| CPU time | 4.79 seconds |
| Started | Aug 24 05:59:10 AM UTC 24 |
| Finished | Aug 24 05:59:16 AM UTC 24 |
| Peak memory | 595848 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4106733805 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 8_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.xbar_smoke.4106733805 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/43.xbar_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/43.xbar_smoke_large_delays.2641710767 |
| Short name | T1914 |
| Test name | |
| Test status | |
| Simulation time | 8844720753 ps |
| CPU time | 74.77 seconds |
| Started | Aug 24 05:59:16 AM UTC 24 |
| Finished | Aug 24 06:00:32 AM UTC 24 |
| Peak memory | 595764 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max _device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2641710767 -assert nopostproc +U VM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.xbar_smoke_large_delays.2641710767 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/43.xbar_smoke_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/43.xbar_smoke_slow_rsp.2135634691 |
| Short name | T1913 |
| Test name | |
| Test status | |
| Simulation time | 4609528144 ps |
| CPU time | 55.1 seconds |
| Started | Aug 24 05:59:29 AM UTC 24 |
| Finished | Aug 24 06:00:26 AM UTC 24 |
| Peak memory | 595768 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2135634691 -assert nopostproc +UVM_T ESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.xbar_smoke_slow_rsp.2135634691 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/43.xbar_smoke_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/43.xbar_smoke_zero_delays.3574525153 |
| Short name | T1905 |
| Test name | |
| Test status | |
| Simulation time | 46465134 ps |
| CPU time | 4.99 seconds |
| Started | Aug 24 05:59:14 AM UTC 24 |
| Finished | Aug 24 05:59:20 AM UTC 24 |
| Peak memory | 595700 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3574525153 -assert nopostpr oc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.xbar_smoke_zero_delays.3574525153 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/43.xbar_smoke_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/43.xbar_stress_all.2727381638 |
| Short name | T1930 |
| Test name | |
| Test status | |
| Simulation time | 1216117251 ps |
| CPU time | 71.04 seconds |
| Started | Aug 24 06:00:40 AM UTC 24 |
| Finished | Aug 24 06:01:53 AM UTC 24 |
| Peak memory | 597828 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2727381638 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.xbar_stress_all.2727381638 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/43.xbar_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/43.xbar_stress_all_with_error.665425291 |
| Short name | T1925 |
| Test name | |
| Test status | |
| Simulation time | 1647030683 ps |
| CPU time | 37.01 seconds |
| Started | Aug 24 06:00:50 AM UTC 24 |
| Finished | Aug 24 06:01:29 AM UTC 24 |
| Peak memory | 597832 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=665425291 -assert nopostproc +UVM_TESTNAME =xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.xbar_stress_all_with_error.665425291 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/43.xbar_stress_all_with_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/43.xbar_stress_all_with_rand_reset.734284989 |
| Short name | T1943 |
| Test name | |
| Test status | |
| Simulation time | 1291212086 ps |
| CPU time | 127.8 seconds |
| Started | Aug 24 06:00:46 AM UTC 24 |
| Finished | Aug 24 06:02:56 AM UTC 24 |
| Peak memory | 597872 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=734284989 -assert nopostproc +UVM_TESTNAME =xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.xbar_stress_all_with_rand_reset.734284989 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/43.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/43.xbar_stress_all_with_reset_error.333033072 |
| Short name | T1942 |
| Test name | |
| Test status | |
| Simulation time | 420700051 ps |
| CPU time | 110.03 seconds |
| Started | Aug 24 06:00:53 AM UTC 24 |
| Finished | Aug 24 06:02:45 AM UTC 24 |
| Peak memory | 597848 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=333033072 -assert nopostproc +UVM_TESTNAME =xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.xbar_stress_all_with_reset_error.333033072 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/43.xbar_stress_all_with_reset_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/43.xbar_unmapped_addr.3489127923 |
| Short name | T1916 |
| Test name | |
| Test status | |
| Simulation time | 71654833 ps |
| CPU time | 8.56 seconds |
| Started | Aug 24 06:00:29 AM UTC 24 |
| Finished | Aug 24 06:00:39 AM UTC 24 |
| Peak memory | 597696 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3489127923 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.xbar_unmapped_addr.3489127923 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/43.xbar_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/44.xbar_access_same_device.4188571286 |
| Short name | T1938 |
| Test name | |
| Test status | |
| Simulation time | 1812011001 ps |
| CPU time | 48.1 seconds |
| Started | Aug 24 06:01:40 AM UTC 24 |
| Finished | Aug 24 06:02:30 AM UTC 24 |
| Peak memory | 597708 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4188571286 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.xbar_access_same_device.4188571286 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/44.xbar_access_same_device/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/44.xbar_access_same_device_slow_rsp.1813071348 |
| Short name | T1971 |
| Test name | |
| Test status | |
| Simulation time | 17903577018 ps |
| CPU time | 204.25 seconds |
| Started | Aug 24 06:01:43 AM UTC 24 |
| Finished | Aug 24 06:05:10 AM UTC 24 |
| Peak memory | 597948 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1813071348 -assert nopostproc +UVM_T ESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.xbar_access_same_device_slow_rsp.1813071348 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/44.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/44.xbar_error_and_unmapped_addr.2047514694 |
| Short name | T1933 |
| Test name | |
| Test status | |
| Simulation time | 280812480 ps |
| CPU time | 10.11 seconds |
| Started | Aug 24 06:02:06 AM UTC 24 |
| Finished | Aug 24 06:02:18 AM UTC 24 |
| Peak memory | 597840 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2047514694 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.xbar_error_and_unmapped_addr.2047514694 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/44.xbar_error_and_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/44.xbar_error_random.4234151082 |
| Short name | T1936 |
| Test name | |
| Test status | |
| Simulation time | 1317690621 ps |
| CPU time | 32.9 seconds |
| Started | Aug 24 06:01:49 AM UTC 24 |
| Finished | Aug 24 06:02:24 AM UTC 24 |
| Peak memory | 597752 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4234151082 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.xbar_error_random.4234151082 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/44.xbar_error_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/44.xbar_random.2390260209 |
| Short name | T1928 |
| Test name | |
| Test status | |
| Simulation time | 424283710 ps |
| CPU time | 25.46 seconds |
| Started | Aug 24 06:01:17 AM UTC 24 |
| Finished | Aug 24 06:01:43 AM UTC 24 |
| Peak memory | 597688 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2390260209 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.xbar_random.2390260209 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/44.xbar_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/44.xbar_random_large_delays.2931709869 |
| Short name | T1939 |
| Test name | |
| Test status | |
| Simulation time | 6521522458 ps |
| CPU time | 53.79 seconds |
| Started | Aug 24 06:01:35 AM UTC 24 |
| Finished | Aug 24 06:02:30 AM UTC 24 |
| Peak memory | 595840 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max _device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2931709869 -assert nopostproc +U VM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.xbar_random_large_delays.2931709869 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/44.xbar_random_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/44.xbar_random_slow_rsp.1810409069 |
| Short name | T2033 |
| Test name | |
| Test status | |
| Simulation time | 47327517379 ps |
| CPU time | 557.01 seconds |
| Started | Aug 24 06:01:37 AM UTC 24 |
| Finished | Aug 24 06:11:00 AM UTC 24 |
| Peak memory | 598068 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1810409069 -assert nopostproc +UVM_T ESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.xbar_random_slow_rsp.1810409069 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/44.xbar_random_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/44.xbar_random_zero_delays.1047962906 |
| Short name | T1924 |
| Test name | |
| Test status | |
| Simulation time | 95244601 ps |
| CPU time | 8.01 seconds |
| Started | Aug 24 06:01:17 AM UTC 24 |
| Finished | Aug 24 06:01:26 AM UTC 24 |
| Peak memory | 597836 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1047962906 -assert nopostpr oc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.xbar_random_zero_delays.1047962906 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/44.xbar_random_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/44.xbar_same_source.3118650459 |
| Short name | T1931 |
| Test name | |
| Test status | |
| Simulation time | 379999391 ps |
| CPU time | 20.52 seconds |
| Started | Aug 24 06:01:43 AM UTC 24 |
| Finished | Aug 24 06:02:05 AM UTC 24 |
| Peak memory | 597696 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3118650459 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.xbar_same_source.3118650459 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/44.xbar_same_source/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/44.xbar_smoke.1672380166 |
| Short name | T1920 |
| Test name | |
| Test status | |
| Simulation time | 51688618 ps |
| CPU time | 5.23 seconds |
| Started | Aug 24 06:00:54 AM UTC 24 |
| Finished | Aug 24 06:01:00 AM UTC 24 |
| Peak memory | 595632 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1672380166 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 8_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.xbar_smoke.1672380166 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/44.xbar_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/44.xbar_smoke_large_delays.1726165363 |
| Short name | T1929 |
| Test name | |
| Test status | |
| Simulation time | 5303024234 ps |
| CPU time | 43.98 seconds |
| Started | Aug 24 06:01:06 AM UTC 24 |
| Finished | Aug 24 06:01:52 AM UTC 24 |
| Peak memory | 595764 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max _device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1726165363 -assert nopostproc +U VM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.xbar_smoke_large_delays.1726165363 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/44.xbar_smoke_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/44.xbar_smoke_slow_rsp.4277951556 |
| Short name | T1934 |
| Test name | |
| Test status | |
| Simulation time | 5395944426 ps |
| CPU time | 62.61 seconds |
| Started | Aug 24 06:01:14 AM UTC 24 |
| Finished | Aug 24 06:02:18 AM UTC 24 |
| Peak memory | 595908 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4277951556 -assert nopostproc +UVM_T ESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.xbar_smoke_slow_rsp.4277951556 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/44.xbar_smoke_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/44.xbar_smoke_zero_delays.1052605971 |
| Short name | T1922 |
| Test name | |
| Test status | |
| Simulation time | 58287299 ps |
| CPU time | 5.32 seconds |
| Started | Aug 24 06:00:56 AM UTC 24 |
| Finished | Aug 24 06:01:03 AM UTC 24 |
| Peak memory | 595636 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1052605971 -assert nopostpr oc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.xbar_smoke_zero_delays.1052605971 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/44.xbar_smoke_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/44.xbar_stress_all.1837609699 |
| Short name | T1949 |
| Test name | |
| Test status | |
| Simulation time | 1291745987 ps |
| CPU time | 85.9 seconds |
| Started | Aug 24 06:02:07 AM UTC 24 |
| Finished | Aug 24 06:03:35 AM UTC 24 |
| Peak memory | 597696 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1837609699 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.xbar_stress_all.1837609699 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/44.xbar_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/44.xbar_stress_all_with_error.897811272 |
| Short name | T1951 |
| Test name | |
| Test status | |
| Simulation time | 1541593262 ps |
| CPU time | 78.03 seconds |
| Started | Aug 24 06:02:21 AM UTC 24 |
| Finished | Aug 24 06:03:41 AM UTC 24 |
| Peak memory | 597840 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=897811272 -assert nopostproc +UVM_TESTNAME =xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.xbar_stress_all_with_error.897811272 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/44.xbar_stress_all_with_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/44.xbar_stress_all_with_rand_reset.2947201684 |
| Short name | T1961 |
| Test name | |
| Test status | |
| Simulation time | 331985391 ps |
| CPU time | 105.51 seconds |
| Started | Aug 24 06:02:19 AM UTC 24 |
| Finished | Aug 24 06:04:07 AM UTC 24 |
| Peak memory | 597752 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2947201684 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.xbar_stress_all_with_rand_reset.2947201684 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/44.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/44.xbar_stress_all_with_reset_error.3832999995 |
| Short name | T1979 |
| Test name | |
| Test status | |
| Simulation time | 6394951381 ps |
| CPU time | 203.07 seconds |
| Started | Aug 24 06:02:32 AM UTC 24 |
| Finished | Aug 24 06:05:57 AM UTC 24 |
| Peak memory | 598116 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3832999995 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.xbar_stress_all_with_reset_error.3832999995 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/44.xbar_stress_all_with_reset_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/44.xbar_unmapped_addr.4282229806 |
| Short name | T1932 |
| Test name | |
| Test status | |
| Simulation time | 65055623 ps |
| CPU time | 7.72 seconds |
| Started | Aug 24 06:01:57 AM UTC 24 |
| Finished | Aug 24 06:02:06 AM UTC 24 |
| Peak memory | 597692 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4282229806 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.xbar_unmapped_addr.4282229806 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/44.xbar_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/45.xbar_access_same_device.3929899690 |
| Short name | T1952 |
| Test name | |
| Test status | |
| Simulation time | 1474422793 ps |
| CPU time | 40.6 seconds |
| Started | Aug 24 06:03:00 AM UTC 24 |
| Finished | Aug 24 06:03:42 AM UTC 24 |
| Peak memory | 597988 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3929899690 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.xbar_access_same_device.3929899690 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/45.xbar_access_same_device/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/45.xbar_access_same_device_slow_rsp.620871670 |
| Short name | T2199 |
| Test name | |
| Test status | |
| Simulation time | 129063034799 ps |
| CPU time | 1456.05 seconds |
| Started | Aug 24 06:03:10 AM UTC 24 |
| Finished | Aug 24 06:27:40 AM UTC 24 |
| Peak memory | 599008 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=620871670 -assert nopostproc +UVM_TE STNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os _regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.xbar_access_same_device_slow_rsp.620871670 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/45.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/45.xbar_error_and_unmapped_addr.945464728 |
| Short name | T1957 |
| Test name | |
| Test status | |
| Simulation time | 1133758388 ps |
| CPU time | 30.94 seconds |
| Started | Aug 24 06:03:22 AM UTC 24 |
| Finished | Aug 24 06:03:55 AM UTC 24 |
| Peak memory | 597692 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=945464728 -assert nopostproc +UVM_TESTNAME =xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.xbar_error_and_unmapped_addr.945464728 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/45.xbar_error_and_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/45.xbar_error_random.2607032785 |
| Short name | T1948 |
| Test name | |
| Test status | |
| Simulation time | 242885331 ps |
| CPU time | 15.44 seconds |
| Started | Aug 24 06:03:13 AM UTC 24 |
| Finished | Aug 24 06:03:30 AM UTC 24 |
| Peak memory | 597932 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2607032785 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.xbar_error_random.2607032785 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/45.xbar_error_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/45.xbar_random.450783908 |
| Short name | T1955 |
| Test name | |
| Test status | |
| Simulation time | 2277910026 ps |
| CPU time | 61.7 seconds |
| Started | Aug 24 06:02:44 AM UTC 24 |
| Finished | Aug 24 06:03:47 AM UTC 24 |
| Peak memory | 597756 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=450783908 -assert nopostproc +UVM_TESTNAME =xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 8_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.xbar_random.450783908 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/45.xbar_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/45.xbar_random_large_delays.3602686940 |
| Short name | T1974 |
| Test name | |
| Test status | |
| Simulation time | 17845560780 ps |
| CPU time | 155.35 seconds |
| Started | Aug 24 06:02:54 AM UTC 24 |
| Finished | Aug 24 06:05:32 AM UTC 24 |
| Peak memory | 597964 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max _device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3602686940 -assert nopostproc +U VM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.xbar_random_large_delays.3602686940 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/45.xbar_random_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/45.xbar_random_slow_rsp.11600442 |
| Short name | T2031 |
| Test name | |
| Test status | |
| Simulation time | 39503334576 ps |
| CPU time | 466.15 seconds |
| Started | Aug 24 06:02:56 AM UTC 24 |
| Finished | Aug 24 06:10:47 AM UTC 24 |
| Peak memory | 598064 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=11600442 -assert nopostproc +UVM_TES TNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.xbar_random_slow_rsp.11600442 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/45.xbar_random_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/45.xbar_random_zero_delays.1733771292 |
| Short name | T1946 |
| Test name | |
| Test status | |
| Simulation time | 272610125 ps |
| CPU time | 17.4 seconds |
| Started | Aug 24 06:02:44 AM UTC 24 |
| Finished | Aug 24 06:03:02 AM UTC 24 |
| Peak memory | 597900 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1733771292 -assert nopostpr oc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.xbar_random_zero_delays.1733771292 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/45.xbar_random_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/45.xbar_same_source.3763596945 |
| Short name | T1958 |
| Test name | |
| Test status | |
| Simulation time | 2261708001 ps |
| CPU time | 46.1 seconds |
| Started | Aug 24 06:03:11 AM UTC 24 |
| Finished | Aug 24 06:03:59 AM UTC 24 |
| Peak memory | 597908 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3763596945 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.xbar_same_source.3763596945 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/45.xbar_same_source/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/45.xbar_smoke.4251611506 |
| Short name | T1940 |
| Test name | |
| Test status | |
| Simulation time | 213012480 ps |
| CPU time | 6.96 seconds |
| Started | Aug 24 06:02:32 AM UTC 24 |
| Finished | Aug 24 06:02:40 AM UTC 24 |
| Peak memory | 595996 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4251611506 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 8_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.xbar_smoke.4251611506 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/45.xbar_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/45.xbar_smoke_large_delays.2712484725 |
| Short name | T1954 |
| Test name | |
| Test status | |
| Simulation time | 8146967211 ps |
| CPU time | 66.65 seconds |
| Started | Aug 24 06:02:38 AM UTC 24 |
| Finished | Aug 24 06:03:46 AM UTC 24 |
| Peak memory | 595908 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max _device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2712484725 -assert nopostproc +U VM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.xbar_smoke_large_delays.2712484725 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/45.xbar_smoke_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/45.xbar_smoke_slow_rsp.3876202192 |
| Short name | T1953 |
| Test name | |
| Test status | |
| Simulation time | 5041352449 ps |
| CPU time | 61.55 seconds |
| Started | Aug 24 06:02:40 AM UTC 24 |
| Finished | Aug 24 06:03:43 AM UTC 24 |
| Peak memory | 595908 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3876202192 -assert nopostproc +UVM_T ESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.xbar_smoke_slow_rsp.3876202192 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/45.xbar_smoke_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/45.xbar_smoke_zero_delays.649476950 |
| Short name | T1941 |
| Test name | |
| Test status | |
| Simulation time | 46323552 ps |
| CPU time | 5.11 seconds |
| Started | Aug 24 06:02:36 AM UTC 24 |
| Finished | Aug 24 06:02:42 AM UTC 24 |
| Peak memory | 595632 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=649476950 -assert nopostpro c +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.xbar_smoke_zero_delays.649476950 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/45.xbar_smoke_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/45.xbar_stress_all.2723951102 |
| Short name | T1966 |
| Test name | |
| Test status | |
| Simulation time | 1067374988 ps |
| CPU time | 61.09 seconds |
| Started | Aug 24 06:03:45 AM UTC 24 |
| Finished | Aug 24 06:04:48 AM UTC 24 |
| Peak memory | 597700 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2723951102 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.xbar_stress_all.2723951102 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/45.xbar_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/45.xbar_stress_all_with_error.265377367 |
| Short name | T1984 |
| Test name | |
| Test status | |
| Simulation time | 6399953080 ps |
| CPU time | 159.27 seconds |
| Started | Aug 24 06:03:53 AM UTC 24 |
| Finished | Aug 24 06:06:35 AM UTC 24 |
| Peak memory | 597828 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=265377367 -assert nopostproc +UVM_TESTNAME =xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.xbar_stress_all_with_error.265377367 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/45.xbar_stress_all_with_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/45.xbar_stress_all_with_rand_reset.3371001627 |
| Short name | T1969 |
| Test name | |
| Test status | |
| Simulation time | 255495663 ps |
| CPU time | 62.56 seconds |
| Started | Aug 24 06:03:50 AM UTC 24 |
| Finished | Aug 24 06:04:54 AM UTC 24 |
| Peak memory | 597756 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3371001627 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.xbar_stress_all_with_rand_reset.3371001627 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/45.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/45.xbar_stress_all_with_reset_error.816131483 |
| Short name | T2018 |
| Test name | |
| Test status | |
| Simulation time | 5233194154 ps |
| CPU time | 344.72 seconds |
| Started | Aug 24 06:03:54 AM UTC 24 |
| Finished | Aug 24 06:09:43 AM UTC 24 |
| Peak memory | 598064 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=816131483 -assert nopostproc +UVM_TESTNAME =xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.xbar_stress_all_with_reset_error.816131483 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/45.xbar_stress_all_with_reset_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/45.xbar_unmapped_addr.3490448451 |
| Short name | T1956 |
| Test name | |
| Test status | |
| Simulation time | 1179798230 ps |
| CPU time | 33.02 seconds |
| Started | Aug 24 06:03:17 AM UTC 24 |
| Finished | Aug 24 06:03:51 AM UTC 24 |
| Peak memory | 597944 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3490448451 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.xbar_unmapped_addr.3490448451 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/45.xbar_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/46.xbar_access_same_device.2829146464 |
| Short name | T1977 |
| Test name | |
| Test status | |
| Simulation time | 2990480641 ps |
| CPU time | 79.68 seconds |
| Started | Aug 24 06:04:16 AM UTC 24 |
| Finished | Aug 24 06:05:38 AM UTC 24 |
| Peak memory | 597988 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2829146464 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.xbar_access_same_device.2829146464 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/46.xbar_access_same_device/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/46.xbar_access_same_device_slow_rsp.1245408845 |
| Short name | T2282 |
| Test name | |
| Test status | |
| Simulation time | 156530748529 ps |
| CPU time | 1833.54 seconds |
| Started | Aug 24 06:04:17 AM UTC 24 |
| Finished | Aug 24 06:35:08 AM UTC 24 |
| Peak memory | 598956 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1245408845 -assert nopostproc +UVM_T ESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.xbar_access_same_device_slow_rsp.1245408845 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/46.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/46.xbar_error_and_unmapped_addr.1244376961 |
| Short name | T1970 |
| Test name | |
| Test status | |
| Simulation time | 169257359 ps |
| CPU time | 14.61 seconds |
| Started | Aug 24 06:04:52 AM UTC 24 |
| Finished | Aug 24 06:05:08 AM UTC 24 |
| Peak memory | 597936 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1244376961 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.xbar_error_and_unmapped_addr.1244376961 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/46.xbar_error_and_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/46.xbar_error_random.2256933211 |
| Short name | T1968 |
| Test name | |
| Test status | |
| Simulation time | 531319749 ps |
| CPU time | 28.26 seconds |
| Started | Aug 24 06:04:23 AM UTC 24 |
| Finished | Aug 24 06:04:53 AM UTC 24 |
| Peak memory | 597696 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2256933211 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.xbar_error_random.2256933211 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/46.xbar_error_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/46.xbar_random.3195035509 |
| Short name | T1962 |
| Test name | |
| Test status | |
| Simulation time | 208566454 ps |
| CPU time | 7.44 seconds |
| Started | Aug 24 06:04:01 AM UTC 24 |
| Finished | Aug 24 06:04:09 AM UTC 24 |
| Peak memory | 595796 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3195035509 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.xbar_random.3195035509 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/46.xbar_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/46.xbar_random_large_delays.2448816528 |
| Short name | T2039 |
| Test name | |
| Test status | |
| Simulation time | 54453337105 ps |
| CPU time | 472.19 seconds |
| Started | Aug 24 06:04:09 AM UTC 24 |
| Finished | Aug 24 06:12:06 AM UTC 24 |
| Peak memory | 597824 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max _device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2448816528 -assert nopostproc +U VM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.xbar_random_large_delays.2448816528 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/46.xbar_random_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/46.xbar_random_slow_rsp.817751453 |
| Short name | T2074 |
| Test name | |
| Test status | |
| Simulation time | 56847227138 ps |
| CPU time | 696.55 seconds |
| Started | Aug 24 06:04:13 AM UTC 24 |
| Finished | Aug 24 06:15:57 AM UTC 24 |
| Peak memory | 597968 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=817751453 -assert nopostproc +UVM_TE STNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.xbar_random_slow_rsp.817751453 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/46.xbar_random_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/46.xbar_random_zero_delays.3847668549 |
| Short name | T1965 |
| Test name | |
| Test status | |
| Simulation time | 542191107 ps |
| CPU time | 35.41 seconds |
| Started | Aug 24 06:04:05 AM UTC 24 |
| Finished | Aug 24 06:04:42 AM UTC 24 |
| Peak memory | 597696 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3847668549 -assert nopostpr oc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.xbar_random_zero_delays.3847668549 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/46.xbar_random_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/46.xbar_same_source.676971303 |
| Short name | T1963 |
| Test name | |
| Test status | |
| Simulation time | 535127782 ps |
| CPU time | 12.72 seconds |
| Started | Aug 24 06:04:21 AM UTC 24 |
| Finished | Aug 24 06:04:35 AM UTC 24 |
| Peak memory | 597756 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=676971303 -assert nopostproc +UVM_TESTNAME =xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.xbar_same_source.676971303 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/46.xbar_same_source/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/46.xbar_smoke.297861336 |
| Short name | T1960 |
| Test name | |
| Test status | |
| Simulation time | 235047645 ps |
| CPU time | 7.5 seconds |
| Started | Aug 24 06:03:55 AM UTC 24 |
| Finished | Aug 24 06:04:03 AM UTC 24 |
| Peak memory | 595876 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=297861336 -assert nopostproc +UVM_TESTNAME =xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08 _22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.xbar_smoke.297861336 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/46.xbar_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/46.xbar_smoke_large_delays.158757787 |
| Short name | T1967 |
| Test name | |
| Test status | |
| Simulation time | 6004202818 ps |
| CPU time | 52.68 seconds |
| Started | Aug 24 06:03:57 AM UTC 24 |
| Finished | Aug 24 06:04:51 AM UTC 24 |
| Peak memory | 595976 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max _device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=158757787 -assert nopostproc +UV M_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.xbar_smoke_large_delays.158757787 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/46.xbar_smoke_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/46.xbar_smoke_slow_rsp.4075613741 |
| Short name | T1964 |
| Test name | |
| Test status | |
| Simulation time | 2912606424 ps |
| CPU time | 36.64 seconds |
| Started | Aug 24 06:04:00 AM UTC 24 |
| Finished | Aug 24 06:04:38 AM UTC 24 |
| Peak memory | 595700 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4075613741 -assert nopostproc +UVM_T ESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.xbar_smoke_slow_rsp.4075613741 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/46.xbar_smoke_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/46.xbar_smoke_zero_delays.1625430033 |
| Short name | T1959 |
| Test name | |
| Test status | |
| Simulation time | 45275894 ps |
| CPU time | 4.84 seconds |
| Started | Aug 24 06:03:56 AM UTC 24 |
| Finished | Aug 24 06:04:02 AM UTC 24 |
| Peak memory | 595856 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1625430033 -assert nopostpr oc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.xbar_smoke_zero_delays.1625430033 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/46.xbar_smoke_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/46.xbar_stress_all.2268314040 |
| Short name | T1982 |
| Test name | |
| Test status | |
| Simulation time | 3723685290 ps |
| CPU time | 92.87 seconds |
| Started | Aug 24 06:04:55 AM UTC 24 |
| Finished | Aug 24 06:06:30 AM UTC 24 |
| Peak memory | 597896 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2268314040 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.xbar_stress_all.2268314040 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/46.xbar_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/46.xbar_stress_all_with_error.1697842363 |
| Short name | T1989 |
| Test name | |
| Test status | |
| Simulation time | 4404165988 ps |
| CPU time | 108.92 seconds |
| Started | Aug 24 06:05:06 AM UTC 24 |
| Finished | Aug 24 06:06:57 AM UTC 24 |
| Peak memory | 597828 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1697842363 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.xbar_stress_all_with_error.1697842363 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/46.xbar_stress_all_with_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/46.xbar_stress_all_with_rand_reset.1109996029 |
| Short name | T1997 |
| Test name | |
| Test status | |
| Simulation time | 550248027 ps |
| CPU time | 160.64 seconds |
| Started | Aug 24 06:05:01 AM UTC 24 |
| Finished | Aug 24 06:07:45 AM UTC 24 |
| Peak memory | 597912 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1109996029 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.xbar_stress_all_with_rand_reset.1109996029 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/46.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/46.xbar_stress_all_with_reset_error.537635235 |
| Short name | T1987 |
| Test name | |
| Test status | |
| Simulation time | 370387604 ps |
| CPU time | 97.25 seconds |
| Started | Aug 24 06:05:07 AM UTC 24 |
| Finished | Aug 24 06:06:46 AM UTC 24 |
| Peak memory | 597692 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=537635235 -assert nopostproc +UVM_TESTNAME =xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.xbar_stress_all_with_reset_error.537635235 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/46.xbar_stress_all_with_reset_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/46.xbar_unmapped_addr.2922619195 |
| Short name | T1976 |
| Test name | |
| Test status | |
| Simulation time | 1488075238 ps |
| CPU time | 45.66 seconds |
| Started | Aug 24 06:04:49 AM UTC 24 |
| Finished | Aug 24 06:05:36 AM UTC 24 |
| Peak memory | 597696 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2922619195 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.xbar_unmapped_addr.2922619195 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/46.xbar_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/47.xbar_access_same_device.171836607 |
| Short name | T1988 |
| Test name | |
| Test status | |
| Simulation time | 2080042616 ps |
| CPU time | 62 seconds |
| Started | Aug 24 06:05:52 AM UTC 24 |
| Finished | Aug 24 06:06:56 AM UTC 24 |
| Peak memory | 597704 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=171836607 -assert nopostproc +UVM_TESTNAME =xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.xbar_access_same_device.171836607 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/47.xbar_access_same_device/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/47.xbar_access_same_device_slow_rsp.970849743 |
| Short name | T2140 |
| Test name | |
| Test status | |
| Simulation time | 83985534049 ps |
| CPU time | 982.55 seconds |
| Started | Aug 24 06:06:10 AM UTC 24 |
| Finished | Aug 24 06:22:43 AM UTC 24 |
| Peak memory | 597892 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=970849743 -assert nopostproc +UVM_TE STNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os _regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.xbar_access_same_device_slow_rsp.970849743 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/47.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/47.xbar_error_and_unmapped_addr.834899993 |
| Short name | T1993 |
| Test name | |
| Test status | |
| Simulation time | 1069559076 ps |
| CPU time | 33.05 seconds |
| Started | Aug 24 06:06:45 AM UTC 24 |
| Finished | Aug 24 06:07:19 AM UTC 24 |
| Peak memory | 597896 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=834899993 -assert nopostproc +UVM_TESTNAME =xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.xbar_error_and_unmapped_addr.834899993 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/47.xbar_error_and_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/47.xbar_error_random.754408040 |
| Short name | T1995 |
| Test name | |
| Test status | |
| Simulation time | 2254642932 ps |
| CPU time | 56.93 seconds |
| Started | Aug 24 06:06:36 AM UTC 24 |
| Finished | Aug 24 06:07:35 AM UTC 24 |
| Peak memory | 597756 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=754408040 -assert nopostproc +UVM_TESTNAME =xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.xbar_error_random.754408040 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/47.xbar_error_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/47.xbar_random.3475597646 |
| Short name | T1983 |
| Test name | |
| Test status | |
| Simulation time | 2015586396 ps |
| CPU time | 50.96 seconds |
| Started | Aug 24 06:05:42 AM UTC 24 |
| Finished | Aug 24 06:06:34 AM UTC 24 |
| Peak memory | 597832 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3475597646 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.xbar_random.3475597646 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/47.xbar_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/47.xbar_random_large_delays.3384801559 |
| Short name | T2072 |
| Test name | |
| Test status | |
| Simulation time | 73388648416 ps |
| CPU time | 596.4 seconds |
| Started | Aug 24 06:05:46 AM UTC 24 |
| Finished | Aug 24 06:15:49 AM UTC 24 |
| Peak memory | 597816 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max _device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3384801559 -assert nopostproc +U VM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.xbar_random_large_delays.3384801559 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/47.xbar_random_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/47.xbar_random_slow_rsp.3026689292 |
| Short name | T2061 |
| Test name | |
| Test status | |
| Simulation time | 42078233003 ps |
| CPU time | 519.06 seconds |
| Started | Aug 24 06:05:50 AM UTC 24 |
| Finished | Aug 24 06:14:35 AM UTC 24 |
| Peak memory | 598136 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3026689292 -assert nopostproc +UVM_T ESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.xbar_random_slow_rsp.3026689292 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/47.xbar_random_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/47.xbar_random_zero_delays.1019464577 |
| Short name | T1978 |
| Test name | |
| Test status | |
| Simulation time | 105567328 ps |
| CPU time | 8.96 seconds |
| Started | Aug 24 06:05:46 AM UTC 24 |
| Finished | Aug 24 06:05:56 AM UTC 24 |
| Peak memory | 597936 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1019464577 -assert nopostpr oc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.xbar_random_zero_delays.1019464577 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/47.xbar_random_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/47.xbar_same_source.3804966466 |
| Short name | T1986 |
| Test name | |
| Test status | |
| Simulation time | 1252680494 ps |
| CPU time | 27.28 seconds |
| Started | Aug 24 06:06:11 AM UTC 24 |
| Finished | Aug 24 06:06:40 AM UTC 24 |
| Peak memory | 597752 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3804966466 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.xbar_same_source.3804966466 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/47.xbar_same_source/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/47.xbar_smoke.955390057 |
| Short name | T1972 |
| Test name | |
| Test status | |
| Simulation time | 44202456 ps |
| CPU time | 4.77 seconds |
| Started | Aug 24 06:05:08 AM UTC 24 |
| Finished | Aug 24 06:05:13 AM UTC 24 |
| Peak memory | 595636 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=955390057 -assert nopostproc +UVM_TESTNAME =xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08 _22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.xbar_smoke.955390057 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/47.xbar_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/47.xbar_smoke_large_delays.3027690399 |
| Short name | T1981 |
| Test name | |
| Test status | |
| Simulation time | 8006575479 ps |
| CPU time | 63.68 seconds |
| Started | Aug 24 06:05:24 AM UTC 24 |
| Finished | Aug 24 06:06:29 AM UTC 24 |
| Peak memory | 596080 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max _device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3027690399 -assert nopostproc +U VM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.xbar_smoke_large_delays.3027690399 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/47.xbar_smoke_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/47.xbar_smoke_slow_rsp.1204968508 |
| Short name | T1980 |
| Test name | |
| Test status | |
| Simulation time | 4438337153 ps |
| CPU time | 52.7 seconds |
| Started | Aug 24 06:05:28 AM UTC 24 |
| Finished | Aug 24 06:06:22 AM UTC 24 |
| Peak memory | 595768 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1204968508 -assert nopostproc +UVM_T ESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.xbar_smoke_slow_rsp.1204968508 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/47.xbar_smoke_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/47.xbar_smoke_zero_delays.3665720886 |
| Short name | T1973 |
| Test name | |
| Test status | |
| Simulation time | 36875636 ps |
| CPU time | 4.52 seconds |
| Started | Aug 24 06:05:23 AM UTC 24 |
| Finished | Aug 24 06:05:28 AM UTC 24 |
| Peak memory | 595632 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3665720886 -assert nopostpr oc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.xbar_smoke_zero_delays.3665720886 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/47.xbar_smoke_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/47.xbar_stress_all.2178450073 |
| Short name | T2012 |
| Test name | |
| Test status | |
| Simulation time | 5733333150 ps |
| CPU time | 133.34 seconds |
| Started | Aug 24 06:06:48 AM UTC 24 |
| Finished | Aug 24 06:09:04 AM UTC 24 |
| Peak memory | 597824 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2178450073 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.xbar_stress_all.2178450073 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/47.xbar_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/47.xbar_stress_all_with_error.761514975 |
| Short name | T2028 |
| Test name | |
| Test status | |
| Simulation time | 9422419900 ps |
| CPU time | 219.75 seconds |
| Started | Aug 24 06:06:52 AM UTC 24 |
| Finished | Aug 24 06:10:35 AM UTC 24 |
| Peak memory | 597828 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=761514975 -assert nopostproc +UVM_TESTNAME =xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.xbar_stress_all_with_error.761514975 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/47.xbar_stress_all_with_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/47.xbar_stress_all_with_rand_reset.1544812625 |
| Short name | T2008 |
| Test name | |
| Test status | |
| Simulation time | 540793412 ps |
| CPU time | 110.91 seconds |
| Started | Aug 24 06:06:49 AM UTC 24 |
| Finished | Aug 24 06:08:42 AM UTC 24 |
| Peak memory | 597692 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1544812625 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.xbar_stress_all_with_rand_reset.1544812625 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/47.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/47.xbar_stress_all_with_reset_error.4180122505 |
| Short name | T2005 |
| Test name | |
| Test status | |
| Simulation time | 361262708 ps |
| CPU time | 96.84 seconds |
| Started | Aug 24 06:06:54 AM UTC 24 |
| Finished | Aug 24 06:08:32 AM UTC 24 |
| Peak memory | 597980 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4180122505 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.xbar_stress_all_with_reset_error.4180122505 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/47.xbar_stress_all_with_reset_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/47.xbar_unmapped_addr.3685633386 |
| Short name | T1990 |
| Test name | |
| Test status | |
| Simulation time | 175733093 ps |
| CPU time | 17.25 seconds |
| Started | Aug 24 06:06:43 AM UTC 24 |
| Finished | Aug 24 06:07:02 AM UTC 24 |
| Peak memory | 597948 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3685633386 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.xbar_unmapped_addr.3685633386 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/47.xbar_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/48.xbar_access_same_device.1702189713 |
| Short name | T2003 |
| Test name | |
| Test status | |
| Simulation time | 533544477 ps |
| CPU time | 36.11 seconds |
| Started | Aug 24 06:07:50 AM UTC 24 |
| Finished | Aug 24 06:08:27 AM UTC 24 |
| Peak memory | 597928 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1702189713 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.xbar_access_same_device.1702189713 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/48.xbar_access_same_device/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/48.xbar_access_same_device_slow_rsp.3725291058 |
| Short name | T2105 |
| Test name | |
| Test status | |
| Simulation time | 59518693276 ps |
| CPU time | 673.28 seconds |
| Started | Aug 24 06:07:59 AM UTC 24 |
| Finished | Aug 24 06:19:19 AM UTC 24 |
| Peak memory | 597828 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3725291058 -assert nopostproc +UVM_T ESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.xbar_access_same_device_slow_rsp.3725291058 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/48.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/48.xbar_error_and_unmapped_addr.1438363826 |
| Short name | T2007 |
| Test name | |
| Test status | |
| Simulation time | 35859102 ps |
| CPU time | 5.39 seconds |
| Started | Aug 24 06:08:30 AM UTC 24 |
| Finished | Aug 24 06:08:36 AM UTC 24 |
| Peak memory | 595796 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1438363826 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.xbar_error_and_unmapped_addr.1438363826 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/48.xbar_error_and_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/48.xbar_error_random.1995315124 |
| Short name | T2004 |
| Test name | |
| Test status | |
| Simulation time | 137550049 ps |
| CPU time | 9.8 seconds |
| Started | Aug 24 06:08:20 AM UTC 24 |
| Finished | Aug 24 06:08:30 AM UTC 24 |
| Peak memory | 597688 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1995315124 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.xbar_error_random.1995315124 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/48.xbar_error_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/48.xbar_random.3077149597 |
| Short name | T1999 |
| Test name | |
| Test status | |
| Simulation time | 1863082307 ps |
| CPU time | 49.64 seconds |
| Started | Aug 24 06:07:20 AM UTC 24 |
| Finished | Aug 24 06:08:11 AM UTC 24 |
| Peak memory | 597692 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3077149597 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.xbar_random.3077149597 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/48.xbar_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/48.xbar_random_large_delays.1484822679 |
| Short name | T2016 |
| Test name | |
| Test status | |
| Simulation time | 14952421038 ps |
| CPU time | 123.9 seconds |
| Started | Aug 24 06:07:33 AM UTC 24 |
| Finished | Aug 24 06:09:39 AM UTC 24 |
| Peak memory | 597820 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max _device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1484822679 -assert nopostproc +U VM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.xbar_random_large_delays.1484822679 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/48.xbar_random_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/48.xbar_random_slow_rsp.123590588 |
| Short name | T2046 |
| Test name | |
| Test status | |
| Simulation time | 24721654431 ps |
| CPU time | 283.27 seconds |
| Started | Aug 24 06:07:44 AM UTC 24 |
| Finished | Aug 24 06:12:31 AM UTC 24 |
| Peak memory | 597824 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=123590588 -assert nopostproc +UVM_TE STNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.xbar_random_slow_rsp.123590588 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/48.xbar_random_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/48.xbar_random_zero_delays.3606603147 |
| Short name | T1996 |
| Test name | |
| Test status | |
| Simulation time | 160213203 ps |
| CPU time | 12.88 seconds |
| Started | Aug 24 06:07:30 AM UTC 24 |
| Finished | Aug 24 06:07:45 AM UTC 24 |
| Peak memory | 597840 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3606603147 -assert nopostpr oc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.xbar_random_zero_delays.3606603147 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/48.xbar_random_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/48.xbar_same_source.1196955519 |
| Short name | T2001 |
| Test name | |
| Test status | |
| Simulation time | 341821055 ps |
| CPU time | 17.34 seconds |
| Started | Aug 24 06:07:59 AM UTC 24 |
| Finished | Aug 24 06:08:18 AM UTC 24 |
| Peak memory | 597688 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1196955519 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.xbar_same_source.1196955519 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/48.xbar_same_source/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/48.xbar_smoke.424112707 |
| Short name | T1991 |
| Test name | |
| Test status | |
| Simulation time | 48436251 ps |
| CPU time | 5 seconds |
| Started | Aug 24 06:07:00 AM UTC 24 |
| Finished | Aug 24 06:07:06 AM UTC 24 |
| Peak memory | 595880 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=424112707 -assert nopostproc +UVM_TESTNAME =xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08 _22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.xbar_smoke.424112707 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/48.xbar_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/48.xbar_smoke_large_delays.2853155415 |
| Short name | T2000 |
| Test name | |
| Test status | |
| Simulation time | 7995535275 ps |
| CPU time | 62.85 seconds |
| Started | Aug 24 06:07:11 AM UTC 24 |
| Finished | Aug 24 06:08:15 AM UTC 24 |
| Peak memory | 595764 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max _device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2853155415 -assert nopostproc +U VM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.xbar_smoke_large_delays.2853155415 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/48.xbar_smoke_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/48.xbar_smoke_slow_rsp.1110933074 |
| Short name | T2002 |
| Test name | |
| Test status | |
| Simulation time | 5799009363 ps |
| CPU time | 68.5 seconds |
| Started | Aug 24 06:07:16 AM UTC 24 |
| Finished | Aug 24 06:08:26 AM UTC 24 |
| Peak memory | 595832 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1110933074 -assert nopostproc +UVM_T ESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.xbar_smoke_slow_rsp.1110933074 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/48.xbar_smoke_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/48.xbar_smoke_zero_delays.3911207399 |
| Short name | T1992 |
| Test name | |
| Test status | |
| Simulation time | 46843057 ps |
| CPU time | 5.12 seconds |
| Started | Aug 24 06:07:10 AM UTC 24 |
| Finished | Aug 24 06:07:16 AM UTC 24 |
| Peak memory | 595792 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3911207399 -assert nopostpr oc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.xbar_smoke_zero_delays.3911207399 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/48.xbar_smoke_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/48.xbar_stress_all.1764027757 |
| Short name | T2013 |
| Test name | |
| Test status | |
| Simulation time | 1899179836 ps |
| CPU time | 53.52 seconds |
| Started | Aug 24 06:08:32 AM UTC 24 |
| Finished | Aug 24 06:09:27 AM UTC 24 |
| Peak memory | 597824 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1764027757 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.xbar_stress_all.1764027757 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/48.xbar_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/48.xbar_stress_all_with_error.3227225928 |
| Short name | T2015 |
| Test name | |
| Test status | |
| Simulation time | 974901097 ps |
| CPU time | 53.38 seconds |
| Started | Aug 24 06:08:42 AM UTC 24 |
| Finished | Aug 24 06:09:37 AM UTC 24 |
| Peak memory | 597696 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3227225928 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.xbar_stress_all_with_error.3227225928 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/48.xbar_stress_all_with_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/48.xbar_stress_all_with_rand_reset.1702554709 |
| Short name | T2051 |
| Test name | |
| Test status | |
| Simulation time | 993843114 ps |
| CPU time | 278.74 seconds |
| Started | Aug 24 06:08:41 AM UTC 24 |
| Finished | Aug 24 06:13:23 AM UTC 24 |
| Peak memory | 597688 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1702554709 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.xbar_stress_all_with_rand_reset.1702554709 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/48.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/48.xbar_stress_all_with_reset_error.3851101904 |
| Short name | T2030 |
| Test name | |
| Test status | |
| Simulation time | 1606877186 ps |
| CPU time | 117.03 seconds |
| Started | Aug 24 06:08:45 AM UTC 24 |
| Finished | Aug 24 06:10:44 AM UTC 24 |
| Peak memory | 597760 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3851101904 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.xbar_stress_all_with_reset_error.3851101904 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/48.xbar_stress_all_with_reset_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/48.xbar_unmapped_addr.3836191634 |
| Short name | T2011 |
| Test name | |
| Test status | |
| Simulation time | 963065407 ps |
| CPU time | 29.57 seconds |
| Started | Aug 24 06:08:26 AM UTC 24 |
| Finished | Aug 24 06:08:56 AM UTC 24 |
| Peak memory | 597944 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3836191634 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.xbar_unmapped_addr.3836191634 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/48.xbar_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/49.xbar_access_same_device.1683092371 |
| Short name | T2026 |
| Test name | |
| Test status | |
| Simulation time | 871452725 ps |
| CPU time | 44.91 seconds |
| Started | Aug 24 06:09:40 AM UTC 24 |
| Finished | Aug 24 06:10:27 AM UTC 24 |
| Peak memory | 597704 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1683092371 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.xbar_access_same_device.1683092371 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/49.xbar_access_same_device/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/49.xbar_access_same_device_slow_rsp.1184401854 |
| Short name | T2082 |
| Test name | |
| Test status | |
| Simulation time | 31896618213 ps |
| CPU time | 397.41 seconds |
| Started | Aug 24 06:09:48 AM UTC 24 |
| Finished | Aug 24 06:16:30 AM UTC 24 |
| Peak memory | 598072 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1184401854 -assert nopostproc +UVM_T ESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.xbar_access_same_device_slow_rsp.1184401854 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/49.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/49.xbar_error_and_unmapped_addr.3120720499 |
| Short name | T2022 |
| Test name | |
| Test status | |
| Simulation time | 60241496 ps |
| CPU time | 7.11 seconds |
| Started | Aug 24 06:09:57 AM UTC 24 |
| Finished | Aug 24 06:10:05 AM UTC 24 |
| Peak memory | 597840 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3120720499 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.xbar_error_and_unmapped_addr.3120720499 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/49.xbar_error_and_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/49.xbar_error_random.3510614585 |
| Short name | T2025 |
| Test name | |
| Test status | |
| Simulation time | 1354908199 ps |
| CPU time | 31.14 seconds |
| Started | Aug 24 06:09:53 AM UTC 24 |
| Finished | Aug 24 06:10:26 AM UTC 24 |
| Peak memory | 597816 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3510614585 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.xbar_error_random.3510614585 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/49.xbar_error_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/49.xbar_random.2530062960 |
| Short name | T2017 |
| Test name | |
| Test status | |
| Simulation time | 494092796 ps |
| CPU time | 31.54 seconds |
| Started | Aug 24 06:09:09 AM UTC 24 |
| Finished | Aug 24 06:09:42 AM UTC 24 |
| Peak memory | 597696 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2530062960 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.xbar_random.2530062960 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/49.xbar_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/49.xbar_random_large_delays.2964471657 |
| Short name | T2115 |
| Test name | |
| Test status | |
| Simulation time | 80838874420 ps |
| CPU time | 662.1 seconds |
| Started | Aug 24 06:09:10 AM UTC 24 |
| Finished | Aug 24 06:20:19 AM UTC 24 |
| Peak memory | 597820 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max _device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2964471657 -assert nopostproc +U VM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.xbar_random_large_delays.2964471657 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/49.xbar_random_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/49.xbar_random_slow_rsp.2687576157 |
| Short name | T2052 |
| Test name | |
| Test status | |
| Simulation time | 21384128892 ps |
| CPU time | 246.16 seconds |
| Started | Aug 24 06:09:18 AM UTC 24 |
| Finished | Aug 24 06:13:28 AM UTC 24 |
| Peak memory | 597820 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2687576157 -assert nopostproc +UVM_T ESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.xbar_random_slow_rsp.2687576157 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/49.xbar_random_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/49.xbar_random_zero_delays.3765209549 |
| Short name | T2014 |
| Test name | |
| Test status | |
| Simulation time | 380533985 ps |
| CPU time | 23.85 seconds |
| Started | Aug 24 06:09:09 AM UTC 24 |
| Finished | Aug 24 06:09:35 AM UTC 24 |
| Peak memory | 597704 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3765209549 -assert nopostpr oc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.xbar_random_zero_delays.3765209549 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/49.xbar_random_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/49.xbar_same_source.3144387445 |
| Short name | T2024 |
| Test name | |
| Test status | |
| Simulation time | 1409024678 ps |
| CPU time | 27.49 seconds |
| Started | Aug 24 06:09:50 AM UTC 24 |
| Finished | Aug 24 06:10:19 AM UTC 24 |
| Peak memory | 597992 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3144387445 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.xbar_same_source.3144387445 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/49.xbar_same_source/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/49.xbar_smoke.3010917810 |
| Short name | T2010 |
| Test name | |
| Test status | |
| Simulation time | 224513392 ps |
| CPU time | 7.26 seconds |
| Started | Aug 24 06:08:47 AM UTC 24 |
| Finished | Aug 24 06:08:55 AM UTC 24 |
| Peak memory | 595848 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3010917810 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 8_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.xbar_smoke.3010917810 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/49.xbar_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/49.xbar_smoke_large_delays.3989847721 |
| Short name | T2021 |
| Test name | |
| Test status | |
| Simulation time | 8146252524 ps |
| CPU time | 66.49 seconds |
| Started | Aug 24 06:08:50 AM UTC 24 |
| Finished | Aug 24 06:09:58 AM UTC 24 |
| Peak memory | 595996 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max _device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3989847721 -assert nopostproc +U VM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.xbar_smoke_large_delays.3989847721 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/49.xbar_smoke_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/49.xbar_smoke_slow_rsp.36171428 |
| Short name | T2020 |
| Test name | |
| Test status | |
| Simulation time | 4566225905 ps |
| CPU time | 56.05 seconds |
| Started | Aug 24 06:08:56 AM UTC 24 |
| Finished | Aug 24 06:09:54 AM UTC 24 |
| Peak memory | 595992 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=36171428 -assert nopostproc +UVM_TES TNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.xbar_smoke_slow_rsp.36171428 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/49.xbar_smoke_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/49.xbar_smoke_zero_delays.3585518078 |
| Short name | T2009 |
| Test name | |
| Test status | |
| Simulation time | 41508579 ps |
| CPU time | 4.85 seconds |
| Started | Aug 24 06:08:49 AM UTC 24 |
| Finished | Aug 24 06:08:55 AM UTC 24 |
| Peak memory | 595632 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3585518078 -assert nopostpr oc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.xbar_smoke_zero_delays.3585518078 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/49.xbar_smoke_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/49.xbar_stress_all.1259700115 |
| Short name | T2050 |
| Test name | |
| Test status | |
| Simulation time | 7971998557 ps |
| CPU time | 191.47 seconds |
| Started | Aug 24 06:10:00 AM UTC 24 |
| Finished | Aug 24 06:13:14 AM UTC 24 |
| Peak memory | 597960 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1259700115 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.xbar_stress_all.1259700115 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/49.xbar_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/49.xbar_stress_all_with_error.3652422347 |
| Short name | T2032 |
| Test name | |
| Test status | |
| Simulation time | 725274542 ps |
| CPU time | 38.61 seconds |
| Started | Aug 24 06:10:12 AM UTC 24 |
| Finished | Aug 24 06:10:52 AM UTC 24 |
| Peak memory | 597700 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3652422347 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.xbar_stress_all_with_error.3652422347 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/49.xbar_stress_all_with_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/49.xbar_stress_all_with_rand_reset.172025380 |
| Short name | T2089 |
| Test name | |
| Test status | |
| Simulation time | 4798706941 ps |
| CPU time | 417.07 seconds |
| Started | Aug 24 06:10:08 AM UTC 24 |
| Finished | Aug 24 06:17:10 AM UTC 24 |
| Peak memory | 597824 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=172025380 -assert nopostproc +UVM_TESTNAME =xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.xbar_stress_all_with_rand_reset.172025380 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/49.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/49.xbar_stress_all_with_reset_error.2559194213 |
| Short name | T2059 |
| Test name | |
| Test status | |
| Simulation time | 5200933496 ps |
| CPU time | 235.92 seconds |
| Started | Aug 24 06:10:19 AM UTC 24 |
| Finished | Aug 24 06:14:18 AM UTC 24 |
| Peak memory | 597824 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2559194213 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.xbar_stress_all_with_reset_error.2559194213 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/49.xbar_stress_all_with_reset_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/49.xbar_unmapped_addr.3750387682 |
| Short name | T2023 |
| Test name | |
| Test status | |
| Simulation time | 155077688 ps |
| CPU time | 7.33 seconds |
| Started | Aug 24 06:09:57 AM UTC 24 |
| Finished | Aug 24 06:10:05 AM UTC 24 |
| Peak memory | 595628 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3750387682 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.xbar_unmapped_addr.3750387682 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/49.xbar_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/5.chip_csr_mem_rw_with_rand_reset.4112559314 |
| Short name | T1379 |
| Test name | |
| Test status | |
| Simulation time | 9214398983 ps |
| CPU time | 483.83 seconds |
| Started | Aug 24 04:11:52 AM UTC 24 |
| Finished | Aug 24 04:20:02 AM UTC 24 |
| Peak memory | 668496 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000 000000 +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/too ls/sim.tcl +ntb_random_seed=4112559314 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/nul l -cm_name 5.chip_csr_mem_rw_with_rand_reset.4112559314 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/5.chip_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/5.chip_csr_rw.725995353 |
| Short name | T426 |
| Test name | |
| Test status | |
| Simulation time | 6184569730 ps |
| CPU time | 360.37 seconds |
| Started | Aug 24 04:11:42 AM UTC 24 |
| Finished | Aug 24 04:17:47 AM UTC 24 |
| Peak memory | 621276 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +stub_cpu=1 +cdc_instrumentation_ena bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=725995353 -assert nopostp roc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_ regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.chip_csr_rw.725995353 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/5.chip_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/5.chip_same_csr_outstanding.1765394251 |
| Short name | T1465 |
| Test name | |
| Test status | |
| Simulation time | 28489470212 ps |
| CPU time | 2448.75 seconds |
| Started | Aug 24 04:08:22 AM UTC 24 |
| Finished | Aug 24 04:49:36 AM UTC 24 |
| Peak memory | 613204 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +test_timeout_ns=120_000_000 +run_same_csr_outstanding +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim .tcl +ntb_random_seed=1765394251 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_ name 5.chip_same_csr_outstanding.1765394251 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/5.chip_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/5.chip_tl_errors.3523100006 |
| Short name | T566 |
| Test name | |
| Test status | |
| Simulation time | 2745105374 ps |
| CPU time | 114.73 seconds |
| Started | Aug 24 04:08:24 AM UTC 24 |
| Finished | Aug 24 04:10:21 AM UTC 24 |
| Peak memory | 619164 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enable d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3523100006 -assert nopostpro c +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.chip_tl_errors.3523100006 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/5.chip_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/5.xbar_access_same_device.744720894 |
| Short name | T790 |
| Test name | |
| Test status | |
| Simulation time | 336214054 ps |
| CPU time | 19.55 seconds |
| Started | Aug 24 04:10:12 AM UTC 24 |
| Finished | Aug 24 04:10:32 AM UTC 24 |
| Peak memory | 597908 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=744720894 -assert nopostproc +UVM_TESTNAME =xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.xbar_access_same_device.744720894 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/5.xbar_access_same_device/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/5.xbar_access_same_device_slow_rsp.2396620644 |
| Short name | T486 |
| Test name | |
| Test status | |
| Simulation time | 77740844678 ps |
| CPU time | 961.15 seconds |
| Started | Aug 24 04:10:26 AM UTC 24 |
| Finished | Aug 24 04:26:38 AM UTC 24 |
| Peak memory | 598072 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2396620644 -assert nopostproc +UVM_T ESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.xbar_access_same_device_slow_rsp.2396620644 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/5.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/5.xbar_error_and_unmapped_addr.2349620184 |
| Short name | T1366 |
| Test name | |
| Test status | |
| Simulation time | 162026017 ps |
| CPU time | 14.71 seconds |
| Started | Aug 24 04:10:47 AM UTC 24 |
| Finished | Aug 24 04:11:03 AM UTC 24 |
| Peak memory | 597692 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2349620184 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.xbar_error_and_unmapped_addr.2349620184 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/5.xbar_error_and_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/5.xbar_error_random.2428696882 |
| Short name | T616 |
| Test name | |
| Test status | |
| Simulation time | 2266140653 ps |
| CPU time | 58.82 seconds |
| Started | Aug 24 04:10:28 AM UTC 24 |
| Finished | Aug 24 04:11:28 AM UTC 24 |
| Peak memory | 597820 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2428696882 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.xbar_error_random.2428696882 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/5.xbar_error_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/5.xbar_random.394717002 |
| Short name | T503 |
| Test name | |
| Test status | |
| Simulation time | 2282486497 ps |
| CPU time | 62.59 seconds |
| Started | Aug 24 04:09:44 AM UTC 24 |
| Finished | Aug 24 04:10:49 AM UTC 24 |
| Peak memory | 597904 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=394717002 -assert nopostproc +UVM_TESTNAME =xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 8_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.xbar_random.394717002 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/5.xbar_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/5.xbar_random_large_delays.1275000474 |
| Short name | T543 |
| Test name | |
| Test status | |
| Simulation time | 92734027717 ps |
| CPU time | 749.08 seconds |
| Started | Aug 24 04:09:46 AM UTC 24 |
| Finished | Aug 24 04:22:22 AM UTC 24 |
| Peak memory | 598076 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max _device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1275000474 -assert nopostproc +U VM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.xbar_random_large_delays.1275000474 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/5.xbar_random_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/5.xbar_random_slow_rsp.46248157 |
| Short name | T462 |
| Test name | |
| Test status | |
| Simulation time | 61754761240 ps |
| CPU time | 700.03 seconds |
| Started | Aug 24 04:10:10 AM UTC 24 |
| Finished | Aug 24 04:21:57 AM UTC 24 |
| Peak memory | 597948 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=46248157 -assert nopostproc +UVM_TES TNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.xbar_random_slow_rsp.46248157 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/5.xbar_random_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/5.xbar_random_zero_delays.36031804 |
| Short name | T1364 |
| Test name | |
| Test status | |
| Simulation time | 108788518 ps |
| CPU time | 9.74 seconds |
| Started | Aug 24 04:09:45 AM UTC 24 |
| Finished | Aug 24 04:09:55 AM UTC 24 |
| Peak memory | 597832 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=36031804 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.xbar_random_zero_delays.36031804 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/5.xbar_random_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/5.xbar_same_source.4101483729 |
| Short name | T608 |
| Test name | |
| Test status | |
| Simulation time | 752807684 ps |
| CPU time | 16.79 seconds |
| Started | Aug 24 04:10:26 AM UTC 24 |
| Finished | Aug 24 04:10:44 AM UTC 24 |
| Peak memory | 597944 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4101483729 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.xbar_same_source.4101483729 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/5.xbar_same_source/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/5.xbar_smoke.2076306976 |
| Short name | T1361 |
| Test name | |
| Test status | |
| Simulation time | 235659125 ps |
| CPU time | 7.35 seconds |
| Started | Aug 24 04:08:35 AM UTC 24 |
| Finished | Aug 24 04:08:44 AM UTC 24 |
| Peak memory | 595760 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2076306976 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 8_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.xbar_smoke.2076306976 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/5.xbar_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/5.xbar_smoke_large_delays.454996471 |
| Short name | T595 |
| Test name | |
| Test status | |
| Simulation time | 9056397945 ps |
| CPU time | 71.54 seconds |
| Started | Aug 24 04:09:01 AM UTC 24 |
| Finished | Aug 24 04:10:14 AM UTC 24 |
| Peak memory | 595892 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max _device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=454996471 -assert nopostproc +UV M_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.xbar_smoke_large_delays.454996471 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/5.xbar_smoke_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/5.xbar_smoke_slow_rsp.919711059 |
| Short name | T1365 |
| Test name | |
| Test status | |
| Simulation time | 4103673681 ps |
| CPU time | 51.5 seconds |
| Started | Aug 24 04:09:18 AM UTC 24 |
| Finished | Aug 24 04:10:11 AM UTC 24 |
| Peak memory | 595700 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=919711059 -assert nopostproc +UVM_TE STNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.xbar_smoke_slow_rsp.919711059 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/5.xbar_smoke_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/5.xbar_smoke_zero_delays.71647958 |
| Short name | T1363 |
| Test name | |
| Test status | |
| Simulation time | 44286931 ps |
| CPU time | 5.24 seconds |
| Started | Aug 24 04:08:58 AM UTC 24 |
| Finished | Aug 24 04:09:05 AM UTC 24 |
| Peak memory | 595632 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=71647958 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.xbar_smoke_zero_delays.71647958 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/5.xbar_smoke_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/5.xbar_stress_all.3798481792 |
| Short name | T469 |
| Test name | |
| Test status | |
| Simulation time | 11802496330 ps |
| CPU time | 303.9 seconds |
| Started | Aug 24 04:10:58 AM UTC 24 |
| Finished | Aug 24 04:16:06 AM UTC 24 |
| Peak memory | 597952 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3798481792 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.xbar_stress_all.3798481792 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/5.xbar_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/5.xbar_stress_all_with_error.2202691693 |
| Short name | T795 |
| Test name | |
| Test status | |
| Simulation time | 1134345934 ps |
| CPU time | 60.19 seconds |
| Started | Aug 24 04:11:09 AM UTC 24 |
| Finished | Aug 24 04:12:11 AM UTC 24 |
| Peak memory | 597700 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2202691693 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.xbar_stress_all_with_error.2202691693 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/5.xbar_stress_all_with_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/5.xbar_stress_all_with_rand_reset.2963294483 |
| Short name | T622 |
| Test name | |
| Test status | |
| Simulation time | 2561640025 ps |
| CPU time | 103.26 seconds |
| Started | Aug 24 04:11:03 AM UTC 24 |
| Finished | Aug 24 04:12:48 AM UTC 24 |
| Peak memory | 598028 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2963294483 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.xbar_stress_all_with_rand_reset.2963294483 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/5.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/5.xbar_stress_all_with_reset_error.1491801463 |
| Short name | T805 |
| Test name | |
| Test status | |
| Simulation time | 16239117295 ps |
| CPU time | 560.54 seconds |
| Started | Aug 24 04:11:17 AM UTC 24 |
| Finished | Aug 24 04:20:44 AM UTC 24 |
| Peak memory | 597824 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1491801463 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.xbar_stress_all_with_reset_error.1491801463 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/5.xbar_stress_all_with_reset_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/5.xbar_unmapped_addr.326407276 |
| Short name | T499 |
| Test name | |
| Test status | |
| Simulation time | 199615893 ps |
| CPU time | 18.51 seconds |
| Started | Aug 24 04:10:35 AM UTC 24 |
| Finished | Aug 24 04:10:55 AM UTC 24 |
| Peak memory | 597948 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=326407276 -assert nopostproc +UVM_TESTNAME =xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.xbar_unmapped_addr.326407276 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/5.xbar_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/50.xbar_access_same_device.1306024055 |
| Short name | T2044 |
| Test name | |
| Test status | |
| Simulation time | 3149531079 ps |
| CPU time | 86.05 seconds |
| Started | Aug 24 06:11:01 AM UTC 24 |
| Finished | Aug 24 06:12:29 AM UTC 24 |
| Peak memory | 598120 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1306024055 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 50.xbar_access_same_device.1306024055 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/50.xbar_access_same_device/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/50.xbar_access_same_device_slow_rsp.175573268 |
| Short name | T2248 |
| Test name | |
| Test status | |
| Simulation time | 101450446966 ps |
| CPU time | 1242.58 seconds |
| Started | Aug 24 06:11:06 AM UTC 24 |
| Finished | Aug 24 06:32:02 AM UTC 24 |
| Peak memory | 598788 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=175573268 -assert nopostproc +UVM_TE STNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os _regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 50.xbar_access_same_device_slow_rsp.175573268 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/50.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/50.xbar_error_and_unmapped_addr.2006034780 |
| Short name | T2043 |
| Test name | |
| Test status | |
| Simulation time | 278775133 ps |
| CPU time | 22.07 seconds |
| Started | Aug 24 06:11:57 AM UTC 24 |
| Finished | Aug 24 06:12:20 AM UTC 24 |
| Peak memory | 597700 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2006034780 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 50.xbar_error_and_unmapped_addr.2006034780 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/50.xbar_error_and_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/50.xbar_error_random.757774980 |
| Short name | T2042 |
| Test name | |
| Test status | |
| Simulation time | 1535759996 ps |
| CPU time | 37.39 seconds |
| Started | Aug 24 06:11:33 AM UTC 24 |
| Finished | Aug 24 06:12:12 AM UTC 24 |
| Peak memory | 597700 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=757774980 -assert nopostproc +UVM_TESTNAME =xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 50.xbar_error_random.757774980 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/50.xbar_error_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/50.xbar_random.2055886505 |
| Short name | T2035 |
| Test name | |
| Test status | |
| Simulation time | 2321190048 ps |
| CPU time | 57.2 seconds |
| Started | Aug 24 06:10:41 AM UTC 24 |
| Finished | Aug 24 06:11:40 AM UTC 24 |
| Peak memory | 596464 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2055886505 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 50.xbar_random.2055886505 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/50.xbar_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/50.xbar_random_large_delays.448333315 |
| Short name | T2147 |
| Test name | |
| Test status | |
| Simulation time | 89892060673 ps |
| CPU time | 740.42 seconds |
| Started | Aug 24 06:10:53 AM UTC 24 |
| Finished | Aug 24 06:23:21 AM UTC 24 |
| Peak memory | 597828 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max _device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=448333315 -assert nopostproc +UV M_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 50.xbar_random_large_delays.448333315 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/50.xbar_random_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/50.xbar_random_slow_rsp.1433625902 |
| Short name | T2073 |
| Test name | |
| Test status | |
| Simulation time | 24932206101 ps |
| CPU time | 288.17 seconds |
| Started | Aug 24 06:10:58 AM UTC 24 |
| Finished | Aug 24 06:15:50 AM UTC 24 |
| Peak memory | 597900 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1433625902 -assert nopostproc +UVM_T ESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 50.xbar_random_slow_rsp.1433625902 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/50.xbar_random_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/50.xbar_random_zero_delays.2997835536 |
| Short name | T2034 |
| Test name | |
| Test status | |
| Simulation time | 506617944 ps |
| CPU time | 29.03 seconds |
| Started | Aug 24 06:10:49 AM UTC 24 |
| Finished | Aug 24 06:11:20 AM UTC 24 |
| Peak memory | 597704 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2997835536 -assert nopostpr oc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 50.xbar_random_zero_delays.2997835536 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/50.xbar_random_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/50.xbar_same_source.1331567942 |
| Short name | T2038 |
| Test name | |
| Test status | |
| Simulation time | 2367975181 ps |
| CPU time | 49.46 seconds |
| Started | Aug 24 06:11:14 AM UTC 24 |
| Finished | Aug 24 06:12:05 AM UTC 24 |
| Peak memory | 597964 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1331567942 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 50.xbar_same_source.1331567942 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/50.xbar_same_source/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/50.xbar_smoke.169480568 |
| Short name | T2027 |
| Test name | |
| Test status | |
| Simulation time | 216309230 ps |
| CPU time | 6.65 seconds |
| Started | Aug 24 06:10:19 AM UTC 24 |
| Finished | Aug 24 06:10:27 AM UTC 24 |
| Peak memory | 595764 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=169480568 -assert nopostproc +UVM_TESTNAME =xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08 _22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 50.xbar_smoke.169480568 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/50.xbar_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/50.xbar_smoke_large_delays.345852184 |
| Short name | T2037 |
| Test name | |
| Test status | |
| Simulation time | 10183870005 ps |
| CPU time | 78.56 seconds |
| Started | Aug 24 06:10:40 AM UTC 24 |
| Finished | Aug 24 06:12:00 AM UTC 24 |
| Peak memory | 595764 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max _device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=345852184 -assert nopostproc +UV M_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 50.xbar_smoke_large_delays.345852184 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/50.xbar_smoke_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/50.xbar_smoke_slow_rsp.2307929354 |
| Short name | T2036 |
| Test name | |
| Test status | |
| Simulation time | 5086249172 ps |
| CPU time | 59.45 seconds |
| Started | Aug 24 06:10:41 AM UTC 24 |
| Finished | Aug 24 06:11:42 AM UTC 24 |
| Peak memory | 594468 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2307929354 -assert nopostproc +UVM_T ESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 50.xbar_smoke_slow_rsp.2307929354 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/50.xbar_smoke_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/50.xbar_smoke_zero_delays.4110656307 |
| Short name | T2029 |
| Test name | |
| Test status | |
| Simulation time | 46329040 ps |
| CPU time | 4.9 seconds |
| Started | Aug 24 06:10:33 AM UTC 24 |
| Finished | Aug 24 06:10:39 AM UTC 24 |
| Peak memory | 595856 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4110656307 -assert nopostpr oc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 50.xbar_smoke_zero_delays.4110656307 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/50.xbar_smoke_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/50.xbar_stress_all.883869265 |
| Short name | T2064 |
| Test name | |
| Test status | |
| Simulation time | 2843478040 ps |
| CPU time | 154.41 seconds |
| Started | Aug 24 06:12:15 AM UTC 24 |
| Finished | Aug 24 06:14:52 AM UTC 24 |
| Peak memory | 597756 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=883869265 -assert nopostproc +UVM_TESTNAME =xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 50.xbar_stress_all.883869265 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/50.xbar_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/50.xbar_stress_all_with_error.840839418 |
| Short name | T2067 |
| Test name | |
| Test status | |
| Simulation time | 3563996976 ps |
| CPU time | 177.31 seconds |
| Started | Aug 24 06:12:21 AM UTC 24 |
| Finished | Aug 24 06:15:21 AM UTC 24 |
| Peak memory | 597764 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=840839418 -assert nopostproc +UVM_TESTNAME =xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 50.xbar_stress_all_with_error.840839418 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/50.xbar_stress_all_with_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/50.xbar_stress_all_with_rand_reset.943623084 |
| Short name | T2138 |
| Test name | |
| Test status | |
| Simulation time | 6768025095 ps |
| CPU time | 605.31 seconds |
| Started | Aug 24 06:12:20 AM UTC 24 |
| Finished | Aug 24 06:22:32 AM UTC 24 |
| Peak memory | 598104 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=943623084 -assert nopostproc +UVM_TESTNAME =xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 50.xbar_stress_all_with_rand_reset.943623084 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/50.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/50.xbar_unmapped_addr.1616468726 |
| Short name | T2041 |
| Test name | |
| Test status | |
| Simulation time | 162963042 ps |
| CPU time | 16.05 seconds |
| Started | Aug 24 06:11:54 AM UTC 24 |
| Finished | Aug 24 06:12:11 AM UTC 24 |
| Peak memory | 597688 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1616468726 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 50.xbar_unmapped_addr.1616468726 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/50.xbar_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/51.xbar_access_same_device.1342267316 |
| Short name | T2053 |
| Test name | |
| Test status | |
| Simulation time | 588503101 ps |
| CPU time | 32.81 seconds |
| Started | Aug 24 06:13:10 AM UTC 24 |
| Finished | Aug 24 06:13:44 AM UTC 24 |
| Peak memory | 597924 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1342267316 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 51.xbar_access_same_device.1342267316 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/51.xbar_access_same_device/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/51.xbar_access_same_device_slow_rsp.2891238981 |
| Short name | T2212 |
| Test name | |
| Test status | |
| Simulation time | 75258162966 ps |
| CPU time | 901.2 seconds |
| Started | Aug 24 06:13:28 AM UTC 24 |
| Finished | Aug 24 06:28:39 AM UTC 24 |
| Peak memory | 598464 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2891238981 -assert nopostproc +UVM_T ESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 51.xbar_access_same_device_slow_rsp.2891238981 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/51.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/51.xbar_error_and_unmapped_addr.1274905760 |
| Short name | T2060 |
| Test name | |
| Test status | |
| Simulation time | 724723280 ps |
| CPU time | 21.01 seconds |
| Started | Aug 24 06:14:02 AM UTC 24 |
| Finished | Aug 24 06:14:24 AM UTC 24 |
| Peak memory | 597692 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1274905760 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 51.xbar_error_and_unmapped_addr.1274905760 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/51.xbar_error_and_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/51.xbar_error_random.136986764 |
| Short name | T2058 |
| Test name | |
| Test status | |
| Simulation time | 1210595444 ps |
| CPU time | 29.33 seconds |
| Started | Aug 24 06:13:42 AM UTC 24 |
| Finished | Aug 24 06:14:12 AM UTC 24 |
| Peak memory | 597700 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=136986764 -assert nopostproc +UVM_TESTNAME =xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 51.xbar_error_random.136986764 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/51.xbar_error_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/51.xbar_random.1036498945 |
| Short name | T2049 |
| Test name | |
| Test status | |
| Simulation time | 247457489 ps |
| CPU time | 8.7 seconds |
| Started | Aug 24 06:12:46 AM UTC 24 |
| Finished | Aug 24 06:12:56 AM UTC 24 |
| Peak memory | 597692 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1036498945 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 51.xbar_random.1036498945 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/51.xbar_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/51.xbar_random_large_delays.1967813093 |
| Short name | T2201 |
| Test name | |
| Test status | |
| Simulation time | 105960954598 ps |
| CPU time | 889.2 seconds |
| Started | Aug 24 06:12:46 AM UTC 24 |
| Finished | Aug 24 06:27:45 AM UTC 24 |
| Peak memory | 598604 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max _device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1967813093 -assert nopostproc +U VM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 51.xbar_random_large_delays.1967813093 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/51.xbar_random_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/51.xbar_random_slow_rsp.227872199 |
| Short name | T2119 |
| Test name | |
| Test status | |
| Simulation time | 39294814298 ps |
| CPU time | 453.52 seconds |
| Started | Aug 24 06:13:05 AM UTC 24 |
| Finished | Aug 24 06:20:44 AM UTC 24 |
| Peak memory | 597888 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=227872199 -assert nopostproc +UVM_TE STNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 51.xbar_random_slow_rsp.227872199 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/51.xbar_random_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/51.xbar_random_zero_delays.2342251186 |
| Short name | T2048 |
| Test name | |
| Test status | |
| Simulation time | 34001351 ps |
| CPU time | 4.8 seconds |
| Started | Aug 24 06:12:45 AM UTC 24 |
| Finished | Aug 24 06:12:51 AM UTC 24 |
| Peak memory | 595712 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2342251186 -assert nopostpr oc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 51.xbar_random_zero_delays.2342251186 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/51.xbar_random_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/51.xbar_same_source.2726266256 |
| Short name | T2056 |
| Test name | |
| Test status | |
| Simulation time | 461644132 ps |
| CPU time | 25.92 seconds |
| Started | Aug 24 06:13:37 AM UTC 24 |
| Finished | Aug 24 06:14:05 AM UTC 24 |
| Peak memory | 597688 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2726266256 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 51.xbar_same_source.2726266256 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/51.xbar_same_source/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/51.xbar_smoke.2370190173 |
| Short name | T2045 |
| Test name | |
| Test status | |
| Simulation time | 39378207 ps |
| CPU time | 4.69 seconds |
| Started | Aug 24 06:12:25 AM UTC 24 |
| Finished | Aug 24 06:12:31 AM UTC 24 |
| Peak memory | 595848 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2370190173 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 8_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 51.xbar_smoke.2370190173 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/51.xbar_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/51.xbar_smoke_large_delays.2108307850 |
| Short name | T2054 |
| Test name | |
| Test status | |
| Simulation time | 8984427925 ps |
| CPU time | 71.78 seconds |
| Started | Aug 24 06:12:34 AM UTC 24 |
| Finished | Aug 24 06:13:48 AM UTC 24 |
| Peak memory | 596016 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max _device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2108307850 -assert nopostproc +U VM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 51.xbar_smoke_large_delays.2108307850 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/51.xbar_smoke_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/51.xbar_smoke_slow_rsp.3650685887 |
| Short name | T2055 |
| Test name | |
| Test status | |
| Simulation time | 5466048092 ps |
| CPU time | 66.49 seconds |
| Started | Aug 24 06:12:44 AM UTC 24 |
| Finished | Aug 24 06:13:52 AM UTC 24 |
| Peak memory | 595908 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3650685887 -assert nopostproc +UVM_T ESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 51.xbar_smoke_slow_rsp.3650685887 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/51.xbar_smoke_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/51.xbar_smoke_zero_delays.997812112 |
| Short name | T2047 |
| Test name | |
| Test status | |
| Simulation time | 57383763 ps |
| CPU time | 5.39 seconds |
| Started | Aug 24 06:12:26 AM UTC 24 |
| Finished | Aug 24 06:12:32 AM UTC 24 |
| Peak memory | 595632 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=997812112 -assert nopostpro c +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 51.xbar_smoke_zero_delays.997812112 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/51.xbar_smoke_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/51.xbar_stress_all.1038221164 |
| Short name | T2086 |
| Test name | |
| Test status | |
| Simulation time | 2632910362 ps |
| CPU time | 156.54 seconds |
| Started | Aug 24 06:14:07 AM UTC 24 |
| Finished | Aug 24 06:16:46 AM UTC 24 |
| Peak memory | 597936 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1038221164 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 51.xbar_stress_all.1038221164 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/51.xbar_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/51.xbar_stress_all_with_error.1006725723 |
| Short name | T2120 |
| Test name | |
| Test status | |
| Simulation time | 15277708769 ps |
| CPU time | 382.95 seconds |
| Started | Aug 24 06:14:23 AM UTC 24 |
| Finished | Aug 24 06:20:51 AM UTC 24 |
| Peak memory | 597824 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1006725723 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 51.xbar_stress_all_with_error.1006725723 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/51.xbar_stress_all_with_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/51.xbar_stress_all_with_rand_reset.4218730456 |
| Short name | T2080 |
| Test name | |
| Test status | |
| Simulation time | 458754020 ps |
| CPU time | 119.59 seconds |
| Started | Aug 24 06:14:19 AM UTC 24 |
| Finished | Aug 24 06:16:20 AM UTC 24 |
| Peak memory | 597696 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4218730456 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 51.xbar_stress_all_with_rand_reset.4218730456 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/51.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/51.xbar_stress_all_with_reset_error.1444799384 |
| Short name | T2124 |
| Test name | |
| Test status | |
| Simulation time | 10950859640 ps |
| CPU time | 412.88 seconds |
| Started | Aug 24 06:14:26 AM UTC 24 |
| Finished | Aug 24 06:21:24 AM UTC 24 |
| Peak memory | 598096 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1444799384 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 51.xbar_stress_all_with_reset_error.1444799384 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/51.xbar_stress_all_with_reset_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/51.xbar_unmapped_addr.1949715454 |
| Short name | T2057 |
| Test name | |
| Test status | |
| Simulation time | 84935621 ps |
| CPU time | 9.27 seconds |
| Started | Aug 24 06:13:59 AM UTC 24 |
| Finished | Aug 24 06:14:09 AM UTC 24 |
| Peak memory | 597688 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1949715454 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 51.xbar_unmapped_addr.1949715454 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/51.xbar_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/52.xbar_access_same_device.1130617325 |
| Short name | T2078 |
| Test name | |
| Test status | |
| Simulation time | 1318533412 ps |
| CPU time | 33.78 seconds |
| Started | Aug 24 06:15:36 AM UTC 24 |
| Finished | Aug 24 06:16:11 AM UTC 24 |
| Peak memory | 597772 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1130617325 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 52.xbar_access_same_device.1130617325 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/52.xbar_access_same_device/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/52.xbar_access_same_device_slow_rsp.2817994237 |
| Short name | T2214 |
| Test name | |
| Test status | |
| Simulation time | 63056420672 ps |
| CPU time | 772.05 seconds |
| Started | Aug 24 06:15:50 AM UTC 24 |
| Finished | Aug 24 06:28:50 AM UTC 24 |
| Peak memory | 598728 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2817994237 -assert nopostproc +UVM_T ESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 52.xbar_access_same_device_slow_rsp.2817994237 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/52.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/52.xbar_error_and_unmapped_addr.1577203525 |
| Short name | T2085 |
| Test name | |
| Test status | |
| Simulation time | 1214439979 ps |
| CPU time | 32.34 seconds |
| Started | Aug 24 06:16:04 AM UTC 24 |
| Finished | Aug 24 06:16:38 AM UTC 24 |
| Peak memory | 597852 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1577203525 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 52.xbar_error_and_unmapped_addr.1577203525 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/52.xbar_error_and_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/52.xbar_error_random.3529791318 |
| Short name | T2079 |
| Test name | |
| Test status | |
| Simulation time | 144328983 ps |
| CPU time | 10.61 seconds |
| Started | Aug 24 06:16:03 AM UTC 24 |
| Finished | Aug 24 06:16:14 AM UTC 24 |
| Peak memory | 597920 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3529791318 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 52.xbar_error_random.3529791318 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/52.xbar_error_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/52.xbar_random.2976073672 |
| Short name | T2065 |
| Test name | |
| Test status | |
| Simulation time | 71401956 ps |
| CPU time | 6.41 seconds |
| Started | Aug 24 06:14:58 AM UTC 24 |
| Finished | Aug 24 06:15:06 AM UTC 24 |
| Peak memory | 597752 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2976073672 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 52.xbar_random.2976073672 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/52.xbar_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/52.xbar_random_large_delays.3254499072 |
| Short name | T2139 |
| Test name | |
| Test status | |
| Simulation time | 52920732120 ps |
| CPU time | 433.35 seconds |
| Started | Aug 24 06:15:19 AM UTC 24 |
| Finished | Aug 24 06:22:37 AM UTC 24 |
| Peak memory | 597824 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max _device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3254499072 -assert nopostproc +U VM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 52.xbar_random_large_delays.3254499072 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/52.xbar_random_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/52.xbar_random_slow_rsp.3222564292 |
| Short name | T2171 |
| Test name | |
| Test status | |
| Simulation time | 50602734653 ps |
| CPU time | 588.2 seconds |
| Started | Aug 24 06:15:22 AM UTC 24 |
| Finished | Aug 24 06:25:16 AM UTC 24 |
| Peak memory | 597820 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3222564292 -assert nopostproc +UVM_T ESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 52.xbar_random_slow_rsp.3222564292 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/52.xbar_random_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/52.xbar_random_zero_delays.1752114987 |
| Short name | T2068 |
| Test name | |
| Test status | |
| Simulation time | 472947848 ps |
| CPU time | 27.66 seconds |
| Started | Aug 24 06:15:06 AM UTC 24 |
| Finished | Aug 24 06:15:35 AM UTC 24 |
| Peak memory | 597832 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1752114987 -assert nopostpr oc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 52.xbar_random_zero_delays.1752114987 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/52.xbar_random_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/52.xbar_same_source.1665744071 |
| Short name | T2076 |
| Test name | |
| Test status | |
| Simulation time | 167987960 ps |
| CPU time | 11.2 seconds |
| Started | Aug 24 06:15:52 AM UTC 24 |
| Finished | Aug 24 06:16:04 AM UTC 24 |
| Peak memory | 597944 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1665744071 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 52.xbar_same_source.1665744071 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/52.xbar_same_source/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/52.xbar_smoke.3226572990 |
| Short name | T2062 |
| Test name | |
| Test status | |
| Simulation time | 191420919 ps |
| CPU time | 6.43 seconds |
| Started | Aug 24 06:14:32 AM UTC 24 |
| Finished | Aug 24 06:14:40 AM UTC 24 |
| Peak memory | 595696 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3226572990 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 8_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 52.xbar_smoke.3226572990 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/52.xbar_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/52.xbar_smoke_large_delays.1545671192 |
| Short name | T2071 |
| Test name | |
| Test status | |
| Simulation time | 6985147957 ps |
| CPU time | 58.13 seconds |
| Started | Aug 24 06:14:49 AM UTC 24 |
| Finished | Aug 24 06:15:49 AM UTC 24 |
| Peak memory | 596020 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max _device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1545671192 -assert nopostproc +U VM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 52.xbar_smoke_large_delays.1545671192 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/52.xbar_smoke_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/52.xbar_smoke_slow_rsp.3685182602 |
| Short name | T2075 |
| Test name | |
| Test status | |
| Simulation time | 5269429625 ps |
| CPU time | 63.99 seconds |
| Started | Aug 24 06:14:54 AM UTC 24 |
| Finished | Aug 24 06:15:59 AM UTC 24 |
| Peak memory | 595912 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3685182602 -assert nopostproc +UVM_T ESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 52.xbar_smoke_slow_rsp.3685182602 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/52.xbar_smoke_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/52.xbar_smoke_zero_delays.2480030512 |
| Short name | T2063 |
| Test name | |
| Test status | |
| Simulation time | 59971008 ps |
| CPU time | 5.46 seconds |
| Started | Aug 24 06:14:38 AM UTC 24 |
| Finished | Aug 24 06:14:44 AM UTC 24 |
| Peak memory | 595764 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2480030512 -assert nopostpr oc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 52.xbar_smoke_zero_delays.2480030512 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/52.xbar_smoke_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/52.xbar_stress_all.3854857153 |
| Short name | T2092 |
| Test name | |
| Test status | |
| Simulation time | 1291197865 ps |
| CPU time | 75.99 seconds |
| Started | Aug 24 06:16:11 AM UTC 24 |
| Finished | Aug 24 06:17:29 AM UTC 24 |
| Peak memory | 597696 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3854857153 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 52.xbar_stress_all.3854857153 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/52.xbar_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/52.xbar_stress_all_with_error.3295834014 |
| Short name | T2102 |
| Test name | |
| Test status | |
| Simulation time | 6325899364 ps |
| CPU time | 150.32 seconds |
| Started | Aug 24 06:16:18 AM UTC 24 |
| Finished | Aug 24 06:18:51 AM UTC 24 |
| Peak memory | 598104 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3295834014 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 52.xbar_stress_all_with_error.3295834014 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/52.xbar_stress_all_with_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/52.xbar_stress_all_with_rand_reset.3297030107 |
| Short name | T2121 |
| Test name | |
| Test status | |
| Simulation time | 2959697183 ps |
| CPU time | 291.76 seconds |
| Started | Aug 24 06:16:14 AM UTC 24 |
| Finished | Aug 24 06:21:10 AM UTC 24 |
| Peak memory | 597760 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3297030107 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 52.xbar_stress_all_with_rand_reset.3297030107 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/52.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/52.xbar_unmapped_addr.4256636677 |
| Short name | T2077 |
| Test name | |
| Test status | |
| Simulation time | 82194659 ps |
| CPU time | 5.19 seconds |
| Started | Aug 24 06:16:04 AM UTC 24 |
| Finished | Aug 24 06:16:10 AM UTC 24 |
| Peak memory | 595760 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4256636677 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 52.xbar_unmapped_addr.4256636677 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/52.xbar_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/53.xbar_access_same_device.1783617034 |
| Short name | T2090 |
| Test name | |
| Test status | |
| Simulation time | 398305687 ps |
| CPU time | 19.78 seconds |
| Started | Aug 24 06:17:00 AM UTC 24 |
| Finished | Aug 24 06:17:21 AM UTC 24 |
| Peak memory | 597988 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1783617034 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 53.xbar_access_same_device.1783617034 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/53.xbar_access_same_device/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/53.xbar_access_same_device_slow_rsp.3270544533 |
| Short name | T2145 |
| Test name | |
| Test status | |
| Simulation time | 30663423526 ps |
| CPU time | 339.87 seconds |
| Started | Aug 24 06:17:23 AM UTC 24 |
| Finished | Aug 24 06:23:07 AM UTC 24 |
| Peak memory | 597892 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3270544533 -assert nopostproc +UVM_T ESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 53.xbar_access_same_device_slow_rsp.3270544533 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/53.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/53.xbar_error_and_unmapped_addr.2922353789 |
| Short name | T2098 |
| Test name | |
| Test status | |
| Simulation time | 1309798290 ps |
| CPU time | 37.55 seconds |
| Started | Aug 24 06:17:38 AM UTC 24 |
| Finished | Aug 24 06:18:17 AM UTC 24 |
| Peak memory | 597692 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2922353789 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 53.xbar_error_and_unmapped_addr.2922353789 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/53.xbar_error_and_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/53.xbar_error_random.2621914719 |
| Short name | T2096 |
| Test name | |
| Test status | |
| Simulation time | 567274982 ps |
| CPU time | 32.37 seconds |
| Started | Aug 24 06:17:24 AM UTC 24 |
| Finished | Aug 24 06:17:57 AM UTC 24 |
| Peak memory | 597960 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2621914719 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 53.xbar_error_random.2621914719 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/53.xbar_error_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/53.xbar_random.2895289148 |
| Short name | T2087 |
| Test name | |
| Test status | |
| Simulation time | 350158313 ps |
| CPU time | 22.89 seconds |
| Started | Aug 24 06:16:44 AM UTC 24 |
| Finished | Aug 24 06:17:08 AM UTC 24 |
| Peak memory | 597832 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2895289148 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 53.xbar_random.2895289148 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/53.xbar_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/53.xbar_random_large_delays.1898975213 |
| Short name | T2095 |
| Test name | |
| Test status | |
| Simulation time | 6906602200 ps |
| CPU time | 57.4 seconds |
| Started | Aug 24 06:16:50 AM UTC 24 |
| Finished | Aug 24 06:17:49 AM UTC 24 |
| Peak memory | 595772 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max _device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1898975213 -assert nopostproc +U VM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 53.xbar_random_large_delays.1898975213 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/53.xbar_random_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/53.xbar_random_slow_rsp.1477314756 |
| Short name | T2217 |
| Test name | |
| Test status | |
| Simulation time | 63508391443 ps |
| CPU time | 720.08 seconds |
| Started | Aug 24 06:16:51 AM UTC 24 |
| Finished | Aug 24 06:28:59 AM UTC 24 |
| Peak memory | 598460 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1477314756 -assert nopostproc +UVM_T ESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 53.xbar_random_slow_rsp.1477314756 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/53.xbar_random_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/53.xbar_random_zero_delays.494397540 |
| Short name | T2088 |
| Test name | |
| Test status | |
| Simulation time | 306164731 ps |
| CPU time | 20.12 seconds |
| Started | Aug 24 06:16:47 AM UTC 24 |
| Finished | Aug 24 06:17:09 AM UTC 24 |
| Peak memory | 597844 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=494397540 -assert nopostpro c +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 53.xbar_random_zero_delays.494397540 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/53.xbar_random_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/53.xbar_same_source.3061292586 |
| Short name | T2094 |
| Test name | |
| Test status | |
| Simulation time | 621646125 ps |
| CPU time | 13.84 seconds |
| Started | Aug 24 06:17:23 AM UTC 24 |
| Finished | Aug 24 06:17:38 AM UTC 24 |
| Peak memory | 597692 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3061292586 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 53.xbar_same_source.3061292586 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/53.xbar_same_source/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/53.xbar_smoke.2082615896 |
| Short name | T2083 |
| Test name | |
| Test status | |
| Simulation time | 183160742 ps |
| CPU time | 6.75 seconds |
| Started | Aug 24 06:16:25 AM UTC 24 |
| Finished | Aug 24 06:16:33 AM UTC 24 |
| Peak memory | 595848 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2082615896 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 8_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 53.xbar_smoke.2082615896 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/53.xbar_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/53.xbar_smoke_large_delays.527248595 |
| Short name | T2091 |
| Test name | |
| Test status | |
| Simulation time | 5726166135 ps |
| CPU time | 47.65 seconds |
| Started | Aug 24 06:16:34 AM UTC 24 |
| Finished | Aug 24 06:17:24 AM UTC 24 |
| Peak memory | 595768 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max _device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=527248595 -assert nopostproc +UV M_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 53.xbar_smoke_large_delays.527248595 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/53.xbar_smoke_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/53.xbar_smoke_slow_rsp.3273175534 |
| Short name | T2093 |
| Test name | |
| Test status | |
| Simulation time | 4473979211 ps |
| CPU time | 54.03 seconds |
| Started | Aug 24 06:16:41 AM UTC 24 |
| Finished | Aug 24 06:17:37 AM UTC 24 |
| Peak memory | 595908 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3273175534 -assert nopostproc +UVM_T ESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 53.xbar_smoke_slow_rsp.3273175534 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/53.xbar_smoke_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/53.xbar_smoke_zero_delays.1343328125 |
| Short name | T2084 |
| Test name | |
| Test status | |
| Simulation time | 43927723 ps |
| CPU time | 5.15 seconds |
| Started | Aug 24 06:16:29 AM UTC 24 |
| Finished | Aug 24 06:16:36 AM UTC 24 |
| Peak memory | 595632 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1343328125 -assert nopostpr oc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 53.xbar_smoke_zero_delays.1343328125 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/53.xbar_smoke_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/53.xbar_stress_all.2250463461 |
| Short name | T2104 |
| Test name | |
| Test status | |
| Simulation time | 1426509274 ps |
| CPU time | 89.64 seconds |
| Started | Aug 24 06:17:43 AM UTC 24 |
| Finished | Aug 24 06:19:14 AM UTC 24 |
| Peak memory | 597700 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2250463461 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 53.xbar_stress_all.2250463461 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/53.xbar_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/53.xbar_stress_all_with_error.2706218800 |
| Short name | T2133 |
| Test name | |
| Test status | |
| Simulation time | 10593156377 ps |
| CPU time | 256.38 seconds |
| Started | Aug 24 06:17:52 AM UTC 24 |
| Finished | Aug 24 06:22:12 AM UTC 24 |
| Peak memory | 597828 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2706218800 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 53.xbar_stress_all_with_error.2706218800 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/53.xbar_stress_all_with_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/53.xbar_stress_all_with_rand_reset.1892977796 |
| Short name | T2106 |
| Test name | |
| Test status | |
| Simulation time | 235648160 ps |
| CPU time | 87.85 seconds |
| Started | Aug 24 06:17:51 AM UTC 24 |
| Finished | Aug 24 06:19:21 AM UTC 24 |
| Peak memory | 597816 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1892977796 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 53.xbar_stress_all_with_rand_reset.1892977796 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/53.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/53.xbar_stress_all_with_reset_error.1371352195 |
| Short name | T2101 |
| Test name | |
| Test status | |
| Simulation time | 235098101 ps |
| CPU time | 45.2 seconds |
| Started | Aug 24 06:18:03 AM UTC 24 |
| Finished | Aug 24 06:18:50 AM UTC 24 |
| Peak memory | 597924 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1371352195 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 53.xbar_stress_all_with_reset_error.1371352195 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/53.xbar_stress_all_with_reset_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/53.xbar_unmapped_addr.429319216 |
| Short name | T2097 |
| Test name | |
| Test status | |
| Simulation time | 1070846233 ps |
| CPU time | 33.08 seconds |
| Started | Aug 24 06:17:35 AM UTC 24 |
| Finished | Aug 24 06:18:09 AM UTC 24 |
| Peak memory | 597964 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=429319216 -assert nopostproc +UVM_TESTNAME =xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 53.xbar_unmapped_addr.429319216 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/53.xbar_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/54.xbar_access_same_device.1309816417 |
| Short name | T2109 |
| Test name | |
| Test status | |
| Simulation time | 406009106 ps |
| CPU time | 16.15 seconds |
| Started | Aug 24 06:19:29 AM UTC 24 |
| Finished | Aug 24 06:19:46 AM UTC 24 |
| Peak memory | 597708 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1309816417 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 54.xbar_access_same_device.1309816417 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/54.xbar_access_same_device/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/54.xbar_access_same_device_slow_rsp.559702340 |
| Short name | T2284 |
| Test name | |
| Test status | |
| Simulation time | 82962300396 ps |
| CPU time | 939.42 seconds |
| Started | Aug 24 06:19:34 AM UTC 24 |
| Finished | Aug 24 06:35:23 AM UTC 24 |
| Peak memory | 598788 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=559702340 -assert nopostproc +UVM_TE STNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os _regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 54.xbar_access_same_device_slow_rsp.559702340 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/54.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/54.xbar_error_and_unmapped_addr.508769766 |
| Short name | T2114 |
| Test name | |
| Test status | |
| Simulation time | 190884627 ps |
| CPU time | 16.37 seconds |
| Started | Aug 24 06:20:00 AM UTC 24 |
| Finished | Aug 24 06:20:17 AM UTC 24 |
| Peak memory | 597692 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=508769766 -assert nopostproc +UVM_TESTNAME =xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 54.xbar_error_and_unmapped_addr.508769766 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/54.xbar_error_and_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/54.xbar_error_random.510560313 |
| Short name | T2110 |
| Test name | |
| Test status | |
| Simulation time | 139864592 ps |
| CPU time | 10.37 seconds |
| Started | Aug 24 06:19:38 AM UTC 24 |
| Finished | Aug 24 06:19:49 AM UTC 24 |
| Peak memory | 597948 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=510560313 -assert nopostproc +UVM_TESTNAME =xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 54.xbar_error_random.510560313 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/54.xbar_error_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/54.xbar_random.1635829955 |
| Short name | T2103 |
| Test name | |
| Test status | |
| Simulation time | 829374674 ps |
| CPU time | 22.91 seconds |
| Started | Aug 24 06:18:43 AM UTC 24 |
| Finished | Aug 24 06:19:08 AM UTC 24 |
| Peak memory | 597692 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1635829955 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 54.xbar_random.1635829955 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/54.xbar_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/54.xbar_random_large_delays.1006289138 |
| Short name | T2211 |
| Test name | |
| Test status | |
| Simulation time | 63462131531 ps |
| CPU time | 545.74 seconds |
| Started | Aug 24 06:19:06 AM UTC 24 |
| Finished | Aug 24 06:28:17 AM UTC 24 |
| Peak memory | 597964 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max _device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1006289138 -assert nopostproc +U VM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 54.xbar_random_large_delays.1006289138 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/54.xbar_random_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/54.xbar_random_slow_rsp.2256978324 |
| Short name | T2122 |
| Test name | |
| Test status | |
| Simulation time | 9210866367 ps |
| CPU time | 108.28 seconds |
| Started | Aug 24 06:19:22 AM UTC 24 |
| Finished | Aug 24 06:21:12 AM UTC 24 |
| Peak memory | 598132 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2256978324 -assert nopostproc +UVM_T ESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 54.xbar_random_slow_rsp.2256978324 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/54.xbar_random_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/54.xbar_random_zero_delays.4174462310 |
| Short name | T2107 |
| Test name | |
| Test status | |
| Simulation time | 283355938 ps |
| CPU time | 19.22 seconds |
| Started | Aug 24 06:19:04 AM UTC 24 |
| Finished | Aug 24 06:19:24 AM UTC 24 |
| Peak memory | 597840 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4174462310 -assert nopostpr oc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 54.xbar_random_zero_delays.4174462310 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/54.xbar_random_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/54.xbar_same_source.1548953048 |
| Short name | T2112 |
| Test name | |
| Test status | |
| Simulation time | 333980813 ps |
| CPU time | 18.49 seconds |
| Started | Aug 24 06:19:35 AM UTC 24 |
| Finished | Aug 24 06:19:55 AM UTC 24 |
| Peak memory | 597688 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1548953048 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 54.xbar_same_source.1548953048 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/54.xbar_same_source/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/54.xbar_smoke.1459953641 |
| Short name | T2099 |
| Test name | |
| Test status | |
| Simulation time | 51598317 ps |
| CPU time | 5.42 seconds |
| Started | Aug 24 06:18:11 AM UTC 24 |
| Finished | Aug 24 06:18:18 AM UTC 24 |
| Peak memory | 595704 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1459953641 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 8_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 54.xbar_smoke.1459953641 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/54.xbar_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/54.xbar_smoke_large_delays.3045805462 |
| Short name | T2111 |
| Test name | |
| Test status | |
| Simulation time | 10169373721 ps |
| CPU time | 81.57 seconds |
| Started | Aug 24 06:18:31 AM UTC 24 |
| Finished | Aug 24 06:19:55 AM UTC 24 |
| Peak memory | 595672 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max _device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3045805462 -assert nopostproc +U VM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 54.xbar_smoke_large_delays.3045805462 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/54.xbar_smoke_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/54.xbar_smoke_slow_rsp.1399362877 |
| Short name | T2108 |
| Test name | |
| Test status | |
| Simulation time | 5697763478 ps |
| CPU time | 67.07 seconds |
| Started | Aug 24 06:18:31 AM UTC 24 |
| Finished | Aug 24 06:19:40 AM UTC 24 |
| Peak memory | 595536 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1399362877 -assert nopostproc +UVM_T ESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 54.xbar_smoke_slow_rsp.1399362877 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/54.xbar_smoke_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/54.xbar_smoke_zero_delays.3802205150 |
| Short name | T2100 |
| Test name | |
| Test status | |
| Simulation time | 47210199 ps |
| CPU time | 5.21 seconds |
| Started | Aug 24 06:18:23 AM UTC 24 |
| Finished | Aug 24 06:18:29 AM UTC 24 |
| Peak memory | 595632 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3802205150 -assert nopostpr oc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 54.xbar_smoke_zero_delays.3802205150 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/54.xbar_smoke_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/54.xbar_stress_all.1533007779 |
| Short name | T2118 |
| Test name | |
| Test status | |
| Simulation time | 601294342 ps |
| CPU time | 36.23 seconds |
| Started | Aug 24 06:20:03 AM UTC 24 |
| Finished | Aug 24 06:20:41 AM UTC 24 |
| Peak memory | 597840 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1533007779 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 54.xbar_stress_all.1533007779 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/54.xbar_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/54.xbar_stress_all_with_error.1979143856 |
| Short name | T2178 |
| Test name | |
| Test status | |
| Simulation time | 14603835884 ps |
| CPU time | 336.12 seconds |
| Started | Aug 24 06:20:09 AM UTC 24 |
| Finished | Aug 24 06:25:50 AM UTC 24 |
| Peak memory | 597824 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1979143856 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 54.xbar_stress_all_with_error.1979143856 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/54.xbar_stress_all_with_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/54.xbar_stress_all_with_rand_reset.914934595 |
| Short name | T2132 |
| Test name | |
| Test status | |
| Simulation time | 278545692 ps |
| CPU time | 112.91 seconds |
| Started | Aug 24 06:20:09 AM UTC 24 |
| Finished | Aug 24 06:22:04 AM UTC 24 |
| Peak memory | 597692 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=914934595 -assert nopostproc +UVM_TESTNAME =xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 54.xbar_stress_all_with_rand_reset.914934595 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/54.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/54.xbar_stress_all_with_reset_error.674077409 |
| Short name | T2142 |
| Test name | |
| Test status | |
| Simulation time | 642156245 ps |
| CPU time | 145.23 seconds |
| Started | Aug 24 06:20:21 AM UTC 24 |
| Finished | Aug 24 06:22:49 AM UTC 24 |
| Peak memory | 597692 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=674077409 -assert nopostproc +UVM_TESTNAME =xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 54.xbar_stress_all_with_reset_error.674077409 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/54.xbar_stress_all_with_reset_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/54.xbar_unmapped_addr.3521259464 |
| Short name | T2113 |
| Test name | |
| Test status | |
| Simulation time | 125617069 ps |
| CPU time | 12.15 seconds |
| Started | Aug 24 06:19:54 AM UTC 24 |
| Finished | Aug 24 06:20:07 AM UTC 24 |
| Peak memory | 597688 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3521259464 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 54.xbar_unmapped_addr.3521259464 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/54.xbar_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/55.xbar_access_same_device.1294124033 |
| Short name | T2126 |
| Test name | |
| Test status | |
| Simulation time | 285331783 ps |
| CPU time | 18.17 seconds |
| Started | Aug 24 06:21:24 AM UTC 24 |
| Finished | Aug 24 06:21:43 AM UTC 24 |
| Peak memory | 597776 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1294124033 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 55.xbar_access_same_device.1294124033 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/55.xbar_access_same_device/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/55.xbar_access_same_device_slow_rsp.429220263 |
| Short name | T2238 |
| Test name | |
| Test status | |
| Simulation time | 50261730356 ps |
| CPU time | 565.34 seconds |
| Started | Aug 24 06:21:27 AM UTC 24 |
| Finished | Aug 24 06:30:58 AM UTC 24 |
| Peak memory | 598036 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=429220263 -assert nopostproc +UVM_TE STNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os _regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 55.xbar_access_same_device_slow_rsp.429220263 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/55.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/55.xbar_error_and_unmapped_addr.3757152558 |
| Short name | T2135 |
| Test name | |
| Test status | |
| Simulation time | 320114010 ps |
| CPU time | 22.67 seconds |
| Started | Aug 24 06:21:57 AM UTC 24 |
| Finished | Aug 24 06:22:21 AM UTC 24 |
| Peak memory | 597704 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3757152558 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 55.xbar_error_and_unmapped_addr.3757152558 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/55.xbar_error_and_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/55.xbar_error_random.2806829952 |
| Short name | T2130 |
| Test name | |
| Test status | |
| Simulation time | 945585732 ps |
| CPU time | 22.36 seconds |
| Started | Aug 24 06:21:38 AM UTC 24 |
| Finished | Aug 24 06:22:02 AM UTC 24 |
| Peak memory | 597924 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2806829952 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 55.xbar_error_random.2806829952 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/55.xbar_error_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/55.xbar_random.3128681284 |
| Short name | T2123 |
| Test name | |
| Test status | |
| Simulation time | 346024508 ps |
| CPU time | 22.9 seconds |
| Started | Aug 24 06:20:54 AM UTC 24 |
| Finished | Aug 24 06:21:19 AM UTC 24 |
| Peak memory | 597752 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3128681284 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 55.xbar_random.3128681284 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/55.xbar_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/55.xbar_random_large_delays.3456769919 |
| Short name | T2170 |
| Test name | |
| Test status | |
| Simulation time | 29169196823 ps |
| CPU time | 244.4 seconds |
| Started | Aug 24 06:21:05 AM UTC 24 |
| Finished | Aug 24 06:25:13 AM UTC 24 |
| Peak memory | 597948 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max _device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3456769919 -assert nopostproc +U VM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 55.xbar_random_large_delays.3456769919 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/55.xbar_random_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/55.xbar_random_slow_rsp.3057286631 |
| Short name | T2151 |
| Test name | |
| Test status | |
| Simulation time | 11801115602 ps |
| CPU time | 141.42 seconds |
| Started | Aug 24 06:21:15 AM UTC 24 |
| Finished | Aug 24 06:23:38 AM UTC 24 |
| Peak memory | 597820 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3057286631 -assert nopostproc +UVM_T ESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 55.xbar_random_slow_rsp.3057286631 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/55.xbar_random_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/55.xbar_random_zero_delays.2325190434 |
| Short name | T2125 |
| Test name | |
| Test status | |
| Simulation time | 474923508 ps |
| CPU time | 31.07 seconds |
| Started | Aug 24 06:20:58 AM UTC 24 |
| Finished | Aug 24 06:21:30 AM UTC 24 |
| Peak memory | 597904 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2325190434 -assert nopostpr oc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 55.xbar_random_zero_delays.2325190434 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/55.xbar_random_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/55.xbar_same_source.4071639202 |
| Short name | T2131 |
| Test name | |
| Test status | |
| Simulation time | 1443352971 ps |
| CPU time | 28.67 seconds |
| Started | Aug 24 06:21:33 AM UTC 24 |
| Finished | Aug 24 06:22:03 AM UTC 24 |
| Peak memory | 597944 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4071639202 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 55.xbar_same_source.4071639202 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/55.xbar_same_source/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/55.xbar_smoke.1882281710 |
| Short name | T2117 |
| Test name | |
| Test status | |
| Simulation time | 261450303 ps |
| CPU time | 7.86 seconds |
| Started | Aug 24 06:20:31 AM UTC 24 |
| Finished | Aug 24 06:20:40 AM UTC 24 |
| Peak memory | 595636 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1882281710 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 8_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 55.xbar_smoke.1882281710 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/55.xbar_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/55.xbar_smoke_large_delays.1293171468 |
| Short name | T2127 |
| Test name | |
| Test status | |
| Simulation time | 7793670253 ps |
| CPU time | 62.32 seconds |
| Started | Aug 24 06:20:53 AM UTC 24 |
| Finished | Aug 24 06:21:57 AM UTC 24 |
| Peak memory | 596016 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max _device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1293171468 -assert nopostproc +U VM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 55.xbar_smoke_large_delays.1293171468 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/55.xbar_smoke_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/55.xbar_smoke_slow_rsp.1130685527 |
| Short name | T2128 |
| Test name | |
| Test status | |
| Simulation time | 5497455882 ps |
| CPU time | 63.78 seconds |
| Started | Aug 24 06:20:55 AM UTC 24 |
| Finished | Aug 24 06:22:00 AM UTC 24 |
| Peak memory | 595832 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1130685527 -assert nopostproc +UVM_T ESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 55.xbar_smoke_slow_rsp.1130685527 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/55.xbar_smoke_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/55.xbar_smoke_zero_delays.174306571 |
| Short name | T2116 |
| Test name | |
| Test status | |
| Simulation time | 44461134 ps |
| CPU time | 5 seconds |
| Started | Aug 24 06:20:33 AM UTC 24 |
| Finished | Aug 24 06:20:39 AM UTC 24 |
| Peak memory | 595632 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=174306571 -assert nopostpro c +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 55.xbar_smoke_zero_delays.174306571 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/55.xbar_smoke_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/55.xbar_stress_all.4140803375 |
| Short name | T2165 |
| Test name | |
| Test status | |
| Simulation time | 5729528633 ps |
| CPU time | 144.94 seconds |
| Started | Aug 24 06:22:11 AM UTC 24 |
| Finished | Aug 24 06:24:39 AM UTC 24 |
| Peak memory | 598024 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4140803375 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 55.xbar_stress_all.4140803375 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/55.xbar_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/55.xbar_stress_all_with_error.715301910 |
| Short name | T2203 |
| Test name | |
| Test status | |
| Simulation time | 13933177848 ps |
| CPU time | 330.8 seconds |
| Started | Aug 24 06:22:15 AM UTC 24 |
| Finished | Aug 24 06:27:50 AM UTC 24 |
| Peak memory | 598080 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=715301910 -assert nopostproc +UVM_TESTNAME =xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 55.xbar_stress_all_with_error.715301910 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/55.xbar_stress_all_with_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/55.xbar_stress_all_with_reset_error.3367456370 |
| Short name | T2141 |
| Test name | |
| Test status | |
| Simulation time | 110399832 ps |
| CPU time | 28.3 seconds |
| Started | Aug 24 06:22:15 AM UTC 24 |
| Finished | Aug 24 06:22:45 AM UTC 24 |
| Peak memory | 597692 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3367456370 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 55.xbar_stress_all_with_reset_error.3367456370 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/55.xbar_stress_all_with_reset_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/55.xbar_unmapped_addr.3132426627 |
| Short name | T2129 |
| Test name | |
| Test status | |
| Simulation time | 499771274 ps |
| CPU time | 16.1 seconds |
| Started | Aug 24 06:21:44 AM UTC 24 |
| Finished | Aug 24 06:22:01 AM UTC 24 |
| Peak memory | 597692 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3132426627 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 55.xbar_unmapped_addr.3132426627 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/55.xbar_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/56.xbar_access_same_device.3298444494 |
| Short name | T2154 |
| Test name | |
| Test status | |
| Simulation time | 1105307797 ps |
| CPU time | 49.36 seconds |
| Started | Aug 24 06:22:52 AM UTC 24 |
| Finished | Aug 24 06:23:43 AM UTC 24 |
| Peak memory | 597916 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3298444494 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 56.xbar_access_same_device.3298444494 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/56.xbar_access_same_device/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/56.xbar_access_same_device_slow_rsp.1951509219 |
| Short name | T2300 |
| Test name | |
| Test status | |
| Simulation time | 67670974717 ps |
| CPU time | 805.75 seconds |
| Started | Aug 24 06:22:57 AM UTC 24 |
| Finished | Aug 24 06:36:31 AM UTC 24 |
| Peak memory | 599044 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1951509219 -assert nopostproc +UVM_T ESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 56.xbar_access_same_device_slow_rsp.1951509219 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/56.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/56.xbar_error_and_unmapped_addr.1802692749 |
| Short name | T2155 |
| Test name | |
| Test status | |
| Simulation time | 985455797 ps |
| CPU time | 25.61 seconds |
| Started | Aug 24 06:23:19 AM UTC 24 |
| Finished | Aug 24 06:23:46 AM UTC 24 |
| Peak memory | 597700 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1802692749 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 56.xbar_error_and_unmapped_addr.1802692749 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/56.xbar_error_and_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/56.xbar_error_random.3034947577 |
| Short name | T2150 |
| Test name | |
| Test status | |
| Simulation time | 605938466 ps |
| CPU time | 33.57 seconds |
| Started | Aug 24 06:23:03 AM UTC 24 |
| Finished | Aug 24 06:23:38 AM UTC 24 |
| Peak memory | 597924 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3034947577 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 56.xbar_error_random.3034947577 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/56.xbar_error_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/56.xbar_random.2265398895 |
| Short name | T2146 |
| Test name | |
| Test status | |
| Simulation time | 1669352267 ps |
| CPU time | 39.33 seconds |
| Started | Aug 24 06:22:35 AM UTC 24 |
| Finished | Aug 24 06:23:15 AM UTC 24 |
| Peak memory | 597964 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2265398895 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 56.xbar_random.2265398895 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/56.xbar_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/56.xbar_random_large_delays.3172225581 |
| Short name | T2252 |
| Test name | |
| Test status | |
| Simulation time | 70311554749 ps |
| CPU time | 567.43 seconds |
| Started | Aug 24 06:22:39 AM UTC 24 |
| Finished | Aug 24 06:32:12 AM UTC 24 |
| Peak memory | 597820 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max _device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3172225581 -assert nopostproc +U VM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 56.xbar_random_large_delays.3172225581 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/56.xbar_random_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/56.xbar_random_slow_rsp.669867036 |
| Short name | T2162 |
| Test name | |
| Test status | |
| Simulation time | 8259612586 ps |
| CPU time | 98.86 seconds |
| Started | Aug 24 06:22:46 AM UTC 24 |
| Finished | Aug 24 06:24:27 AM UTC 24 |
| Peak memory | 597824 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=669867036 -assert nopostproc +UVM_TE STNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 56.xbar_random_slow_rsp.669867036 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/56.xbar_random_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/56.xbar_random_zero_delays.651762073 |
| Short name | T2143 |
| Test name | |
| Test status | |
| Simulation time | 178923111 ps |
| CPU time | 13.07 seconds |
| Started | Aug 24 06:22:38 AM UTC 24 |
| Finished | Aug 24 06:22:52 AM UTC 24 |
| Peak memory | 597688 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=651762073 -assert nopostpro c +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 56.xbar_random_zero_delays.651762073 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/56.xbar_random_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/56.xbar_same_source.2274314859 |
| Short name | T2144 |
| Test name | |
| Test status | |
| Simulation time | 39888085 ps |
| CPU time | 4.69 seconds |
| Started | Aug 24 06:22:59 AM UTC 24 |
| Finished | Aug 24 06:23:05 AM UTC 24 |
| Peak memory | 595892 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2274314859 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 56.xbar_same_source.2274314859 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/56.xbar_same_source/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/56.xbar_smoke.2471680247 |
| Short name | T2136 |
| Test name | |
| Test status | |
| Simulation time | 41442345 ps |
| CPU time | 4.69 seconds |
| Started | Aug 24 06:22:17 AM UTC 24 |
| Finished | Aug 24 06:22:23 AM UTC 24 |
| Peak memory | 595696 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2471680247 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 8_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 56.xbar_smoke.2471680247 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/56.xbar_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/56.xbar_smoke_large_delays.2038241517 |
| Short name | T2153 |
| Test name | |
| Test status | |
| Simulation time | 9083025188 ps |
| CPU time | 73.18 seconds |
| Started | Aug 24 06:22:26 AM UTC 24 |
| Finished | Aug 24 06:23:40 AM UTC 24 |
| Peak memory | 595840 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max _device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2038241517 -assert nopostproc +U VM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 56.xbar_smoke_large_delays.2038241517 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/56.xbar_smoke_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/56.xbar_smoke_slow_rsp.3795827659 |
| Short name | T2149 |
| Test name | |
| Test status | |
| Simulation time | 4250179354 ps |
| CPU time | 50.94 seconds |
| Started | Aug 24 06:22:35 AM UTC 24 |
| Finished | Aug 24 06:23:27 AM UTC 24 |
| Peak memory | 595704 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3795827659 -assert nopostproc +UVM_T ESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 56.xbar_smoke_slow_rsp.3795827659 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/56.xbar_smoke_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/56.xbar_smoke_zero_delays.467838277 |
| Short name | T2137 |
| Test name | |
| Test status | |
| Simulation time | 47608041 ps |
| CPU time | 5.01 seconds |
| Started | Aug 24 06:22:18 AM UTC 24 |
| Finished | Aug 24 06:22:25 AM UTC 24 |
| Peak memory | 595884 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=467838277 -assert nopostpro c +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 56.xbar_smoke_zero_delays.467838277 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/56.xbar_smoke_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/56.xbar_stress_all.347300218 |
| Short name | T2166 |
| Test name | |
| Test status | |
| Simulation time | 2933394732 ps |
| CPU time | 82.79 seconds |
| Started | Aug 24 06:23:20 AM UTC 24 |
| Finished | Aug 24 06:24:45 AM UTC 24 |
| Peak memory | 597768 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=347300218 -assert nopostproc +UVM_TESTNAME =xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 56.xbar_stress_all.347300218 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/56.xbar_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/56.xbar_stress_all_with_error.2179326672 |
| Short name | T2157 |
| Test name | |
| Test status | |
| Simulation time | 737862853 ps |
| CPU time | 21.37 seconds |
| Started | Aug 24 06:23:34 AM UTC 24 |
| Finished | Aug 24 06:23:57 AM UTC 24 |
| Peak memory | 597824 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2179326672 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 56.xbar_stress_all_with_error.2179326672 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/56.xbar_stress_all_with_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/56.xbar_stress_all_with_rand_reset.4103447538 |
| Short name | T2177 |
| Test name | |
| Test status | |
| Simulation time | 415471448 ps |
| CPU time | 133.33 seconds |
| Started | Aug 24 06:23:30 AM UTC 24 |
| Finished | Aug 24 06:25:45 AM UTC 24 |
| Peak memory | 597752 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4103447538 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 56.xbar_stress_all_with_rand_reset.4103447538 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/56.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/56.xbar_stress_all_with_reset_error.2644019584 |
| Short name | T2191 |
| Test name | |
| Test status | |
| Simulation time | 7107591803 ps |
| CPU time | 182.09 seconds |
| Started | Aug 24 06:23:39 AM UTC 24 |
| Finished | Aug 24 06:26:43 AM UTC 24 |
| Peak memory | 598036 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2644019584 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 56.xbar_stress_all_with_reset_error.2644019584 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/56.xbar_stress_all_with_reset_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/56.xbar_unmapped_addr.1601672398 |
| Short name | T2148 |
| Test name | |
| Test status | |
| Simulation time | 177877226 ps |
| CPU time | 16.88 seconds |
| Started | Aug 24 06:23:06 AM UTC 24 |
| Finished | Aug 24 06:23:25 AM UTC 24 |
| Peak memory | 598008 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1601672398 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 56.xbar_unmapped_addr.1601672398 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/56.xbar_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/57.xbar_access_same_device.2196828678 |
| Short name | T2161 |
| Test name | |
| Test status | |
| Simulation time | 288675170 ps |
| CPU time | 10.82 seconds |
| Started | Aug 24 06:24:11 AM UTC 24 |
| Finished | Aug 24 06:24:23 AM UTC 24 |
| Peak memory | 597992 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2196828678 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 57.xbar_access_same_device.2196828678 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/57.xbar_access_same_device/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/57.xbar_access_same_device_slow_rsp.2177396522 |
| Short name | T2420 |
| Test name | |
| Test status | |
| Simulation time | 118841486991 ps |
| CPU time | 1360.13 seconds |
| Started | Aug 24 06:24:13 AM UTC 24 |
| Finished | Aug 24 06:47:06 AM UTC 24 |
| Peak memory | 598788 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2177396522 -assert nopostproc +UVM_T ESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 57.xbar_access_same_device_slow_rsp.2177396522 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/57.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/57.xbar_error_and_unmapped_addr.1290422556 |
| Short name | T2167 |
| Test name | |
| Test status | |
| Simulation time | 124842564 ps |
| CPU time | 11.6 seconds |
| Started | Aug 24 06:24:41 AM UTC 24 |
| Finished | Aug 24 06:24:54 AM UTC 24 |
| Peak memory | 597844 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1290422556 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 57.xbar_error_and_unmapped_addr.1290422556 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/57.xbar_error_and_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/57.xbar_error_random.2652178882 |
| Short name | T2164 |
| Test name | |
| Test status | |
| Simulation time | 98327049 ps |
| CPU time | 5.3 seconds |
| Started | Aug 24 06:24:31 AM UTC 24 |
| Finished | Aug 24 06:24:38 AM UTC 24 |
| Peak memory | 595704 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2652178882 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 57.xbar_error_random.2652178882 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/57.xbar_error_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/57.xbar_random.131087288 |
| Short name | T2160 |
| Test name | |
| Test status | |
| Simulation time | 812880988 ps |
| CPU time | 21.3 seconds |
| Started | Aug 24 06:23:55 AM UTC 24 |
| Finished | Aug 24 06:24:17 AM UTC 24 |
| Peak memory | 597824 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=131087288 -assert nopostproc +UVM_TESTNAME =xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 8_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 57.xbar_random.131087288 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/57.xbar_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/57.xbar_random_large_delays.1834831733 |
| Short name | T2317 |
| Test name | |
| Test status | |
| Simulation time | 106062282116 ps |
| CPU time | 846.09 seconds |
| Started | Aug 24 06:24:00 AM UTC 24 |
| Finished | Aug 24 06:38:14 AM UTC 24 |
| Peak memory | 598860 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max _device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1834831733 -assert nopostproc +U VM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 57.xbar_random_large_delays.1834831733 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/57.xbar_random_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/57.xbar_random_slow_rsp.120231673 |
| Short name | T2247 |
| Test name | |
| Test status | |
| Simulation time | 40272327694 ps |
| CPU time | 472.09 seconds |
| Started | Aug 24 06:24:01 AM UTC 24 |
| Finished | Aug 24 06:31:58 AM UTC 24 |
| Peak memory | 598040 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=120231673 -assert nopostproc +UVM_TE STNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 57.xbar_random_slow_rsp.120231673 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/57.xbar_random_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/57.xbar_random_zero_delays.2940667409 |
| Short name | T2163 |
| Test name | |
| Test status | |
| Simulation time | 441652748 ps |
| CPU time | 27.77 seconds |
| Started | Aug 24 06:23:58 AM UTC 24 |
| Finished | Aug 24 06:24:27 AM UTC 24 |
| Peak memory | 597760 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2940667409 -assert nopostpr oc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 57.xbar_random_zero_delays.2940667409 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/57.xbar_random_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/57.xbar_same_source.3306142152 |
| Short name | T2172 |
| Test name | |
| Test status | |
| Simulation time | 2690149924 ps |
| CPU time | 53.53 seconds |
| Started | Aug 24 06:24:21 AM UTC 24 |
| Finished | Aug 24 06:25:16 AM UTC 24 |
| Peak memory | 597756 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3306142152 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 57.xbar_same_source.3306142152 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/57.xbar_same_source/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/57.xbar_smoke.1188726936 |
| Short name | T2156 |
| Test name | |
| Test status | |
| Simulation time | 55919053 ps |
| CPU time | 5.35 seconds |
| Started | Aug 24 06:23:41 AM UTC 24 |
| Finished | Aug 24 06:23:47 AM UTC 24 |
| Peak memory | 595852 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1188726936 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 8_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 57.xbar_smoke.1188726936 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/57.xbar_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/57.xbar_smoke_large_delays.2758009753 |
| Short name | T2169 |
| Test name | |
| Test status | |
| Simulation time | 9501338335 ps |
| CPU time | 75.38 seconds |
| Started | Aug 24 06:23:53 AM UTC 24 |
| Finished | Aug 24 06:25:10 AM UTC 24 |
| Peak memory | 596084 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max _device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2758009753 -assert nopostproc +U VM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 57.xbar_smoke_large_delays.2758009753 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/57.xbar_smoke_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/57.xbar_smoke_slow_rsp.3121912839 |
| Short name | T2168 |
| Test name | |
| Test status | |
| Simulation time | 6270136622 ps |
| CPU time | 74.02 seconds |
| Started | Aug 24 06:23:54 AM UTC 24 |
| Finished | Aug 24 06:25:09 AM UTC 24 |
| Peak memory | 595772 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3121912839 -assert nopostproc +UVM_T ESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 57.xbar_smoke_slow_rsp.3121912839 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/57.xbar_smoke_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/57.xbar_smoke_zero_delays.3815621456 |
| Short name | T2158 |
| Test name | |
| Test status | |
| Simulation time | 45399938 ps |
| CPU time | 5.23 seconds |
| Started | Aug 24 06:23:53 AM UTC 24 |
| Finished | Aug 24 06:23:59 AM UTC 24 |
| Peak memory | 595856 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3815621456 -assert nopostpr oc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 57.xbar_smoke_zero_delays.3815621456 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/57.xbar_smoke_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/57.xbar_stress_all.1864021992 |
| Short name | T2187 |
| Test name | |
| Test status | |
| Simulation time | 4062544220 ps |
| CPU time | 107.01 seconds |
| Started | Aug 24 06:24:41 AM UTC 24 |
| Finished | Aug 24 06:26:30 AM UTC 24 |
| Peak memory | 597896 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1864021992 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 57.xbar_stress_all.1864021992 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/57.xbar_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/57.xbar_stress_all_with_error.1299639974 |
| Short name | T2179 |
| Test name | |
| Test status | |
| Simulation time | 3457411096 ps |
| CPU time | 69.48 seconds |
| Started | Aug 24 06:24:52 AM UTC 24 |
| Finished | Aug 24 06:26:04 AM UTC 24 |
| Peak memory | 597756 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1299639974 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 57.xbar_stress_all_with_error.1299639974 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/57.xbar_stress_all_with_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/57.xbar_stress_all_with_rand_reset.1275636333 |
| Short name | T2210 |
| Test name | |
| Test status | |
| Simulation time | 7563192905 ps |
| CPU time | 202.82 seconds |
| Started | Aug 24 06:24:51 AM UTC 24 |
| Finished | Aug 24 06:28:17 AM UTC 24 |
| Peak memory | 598040 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1275636333 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 57.xbar_stress_all_with_rand_reset.1275636333 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/57.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/57.xbar_stress_all_with_reset_error.2132776397 |
| Short name | T2195 |
| Test name | |
| Test status | |
| Simulation time | 304139323 ps |
| CPU time | 132.29 seconds |
| Started | Aug 24 06:24:59 AM UTC 24 |
| Finished | Aug 24 06:27:14 AM UTC 24 |
| Peak memory | 597984 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2132776397 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 57.xbar_stress_all_with_reset_error.2132776397 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/57.xbar_stress_all_with_reset_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/57.xbar_unmapped_addr.2226896817 |
| Short name | T2174 |
| Test name | |
| Test status | |
| Simulation time | 1417602299 ps |
| CPU time | 41.65 seconds |
| Started | Aug 24 06:24:37 AM UTC 24 |
| Finished | Aug 24 06:25:20 AM UTC 24 |
| Peak memory | 597688 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2226896817 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 57.xbar_unmapped_addr.2226896817 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/57.xbar_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/58.xbar_access_same_device.1625765501 |
| Short name | T2181 |
| Test name | |
| Test status | |
| Simulation time | 1148957866 ps |
| CPU time | 32.59 seconds |
| Started | Aug 24 06:25:35 AM UTC 24 |
| Finished | Aug 24 06:26:09 AM UTC 24 |
| Peak memory | 597772 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1625765501 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 58.xbar_access_same_device.1625765501 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/58.xbar_access_same_device/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/58.xbar_access_same_device_slow_rsp.3188444453 |
| Short name | T2344 |
| Test name | |
| Test status | |
| Simulation time | 73089448129 ps |
| CPU time | 883.67 seconds |
| Started | Aug 24 06:25:43 AM UTC 24 |
| Finished | Aug 24 06:40:35 AM UTC 24 |
| Peak memory | 597884 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3188444453 -assert nopostproc +UVM_T ESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 58.xbar_access_same_device_slow_rsp.3188444453 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/58.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/58.xbar_error_and_unmapped_addr.3162387632 |
| Short name | T2188 |
| Test name | |
| Test status | |
| Simulation time | 356721255 ps |
| CPU time | 12.1 seconds |
| Started | Aug 24 06:26:18 AM UTC 24 |
| Finished | Aug 24 06:26:32 AM UTC 24 |
| Peak memory | 597840 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3162387632 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 58.xbar_error_and_unmapped_addr.3162387632 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/58.xbar_error_and_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/58.xbar_error_random.2140854340 |
| Short name | T2183 |
| Test name | |
| Test status | |
| Simulation time | 380848191 ps |
| CPU time | 10.42 seconds |
| Started | Aug 24 06:25:59 AM UTC 24 |
| Finished | Aug 24 06:26:11 AM UTC 24 |
| Peak memory | 597948 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2140854340 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 58.xbar_error_random.2140854340 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/58.xbar_error_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/58.xbar_random.1614610490 |
| Short name | T2180 |
| Test name | |
| Test status | |
| Simulation time | 567746307 ps |
| CPU time | 34.57 seconds |
| Started | Aug 24 06:25:30 AM UTC 24 |
| Finished | Aug 24 06:26:06 AM UTC 24 |
| Peak memory | 597344 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1614610490 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 58.xbar_random.1614610490 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/58.xbar_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/58.xbar_random_large_delays.1080869128 |
| Short name | T2329 |
| Test name | |
| Test status | |
| Simulation time | 97425152144 ps |
| CPU time | 819.19 seconds |
| Started | Aug 24 06:25:32 AM UTC 24 |
| Finished | Aug 24 06:39:19 AM UTC 24 |
| Peak memory | 597960 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max _device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1080869128 -assert nopostproc +U VM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 58.xbar_random_large_delays.1080869128 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/58.xbar_random_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/58.xbar_random_slow_rsp.1760530390 |
| Short name | T2278 |
| Test name | |
| Test status | |
| Simulation time | 46548381896 ps |
| CPU time | 530.82 seconds |
| Started | Aug 24 06:25:34 AM UTC 24 |
| Finished | Aug 24 06:34:30 AM UTC 24 |
| Peak memory | 598072 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1760530390 -assert nopostproc +UVM_T ESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 58.xbar_random_slow_rsp.1760530390 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/58.xbar_random_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/58.xbar_random_zero_delays.1774939834 |
| Short name | T2176 |
| Test name | |
| Test status | |
| Simulation time | 175757824 ps |
| CPU time | 13.04 seconds |
| Started | Aug 24 06:25:30 AM UTC 24 |
| Finished | Aug 24 06:25:44 AM UTC 24 |
| Peak memory | 597284 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1774939834 -assert nopostpr oc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 58.xbar_random_zero_delays.1774939834 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/58.xbar_random_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/58.xbar_same_source.2581065054 |
| Short name | T2184 |
| Test name | |
| Test status | |
| Simulation time | 339465161 ps |
| CPU time | 18.89 seconds |
| Started | Aug 24 06:25:58 AM UTC 24 |
| Finished | Aug 24 06:26:18 AM UTC 24 |
| Peak memory | 597940 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2581065054 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 58.xbar_same_source.2581065054 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/58.xbar_same_source/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/58.xbar_smoke.722475061 |
| Short name | T2173 |
| Test name | |
| Test status | |
| Simulation time | 237082595 ps |
| CPU time | 7.22 seconds |
| Started | Aug 24 06:25:08 AM UTC 24 |
| Finished | Aug 24 06:25:17 AM UTC 24 |
| Peak memory | 595632 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=722475061 -assert nopostproc +UVM_TESTNAME =xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08 _22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 58.xbar_smoke.722475061 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/58.xbar_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/58.xbar_smoke_large_delays.217163358 |
| Short name | T2185 |
| Test name | |
| Test status | |
| Simulation time | 6781903104 ps |
| CPU time | 53.92 seconds |
| Started | Aug 24 06:25:24 AM UTC 24 |
| Finished | Aug 24 06:26:19 AM UTC 24 |
| Peak memory | 595976 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max _device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=217163358 -assert nopostproc +UV M_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 58.xbar_smoke_large_delays.217163358 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/58.xbar_smoke_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/58.xbar_smoke_slow_rsp.1337025054 |
| Short name | T2182 |
| Test name | |
| Test status | |
| Simulation time | 3522056794 ps |
| CPU time | 41.9 seconds |
| Started | Aug 24 06:25:27 AM UTC 24 |
| Finished | Aug 24 06:26:10 AM UTC 24 |
| Peak memory | 595776 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1337025054 -assert nopostproc +UVM_T ESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 58.xbar_smoke_slow_rsp.1337025054 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/58.xbar_smoke_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/58.xbar_smoke_zero_delays.2533089104 |
| Short name | T2175 |
| Test name | |
| Test status | |
| Simulation time | 33922480 ps |
| CPU time | 4.44 seconds |
| Started | Aug 24 06:25:23 AM UTC 24 |
| Finished | Aug 24 06:25:29 AM UTC 24 |
| Peak memory | 595696 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2533089104 -assert nopostpr oc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 58.xbar_smoke_zero_delays.2533089104 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/58.xbar_smoke_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/58.xbar_stress_all.570186197 |
| Short name | T2230 |
| Test name | |
| Test status | |
| Simulation time | 10278515719 ps |
| CPU time | 234.37 seconds |
| Started | Aug 24 06:26:19 AM UTC 24 |
| Finished | Aug 24 06:30:17 AM UTC 24 |
| Peak memory | 598080 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=570186197 -assert nopostproc +UVM_TESTNAME =xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 58.xbar_stress_all.570186197 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/58.xbar_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/58.xbar_stress_all_with_error.2835812857 |
| Short name | T2193 |
| Test name | |
| Test status | |
| Simulation time | 1745795842 ps |
| CPU time | 38.25 seconds |
| Started | Aug 24 06:26:25 AM UTC 24 |
| Finished | Aug 24 06:27:04 AM UTC 24 |
| Peak memory | 597692 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2835812857 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 58.xbar_stress_all_with_error.2835812857 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/58.xbar_stress_all_with_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/58.xbar_stress_all_with_rand_reset.3300046927 |
| Short name | T2263 |
| Test name | |
| Test status | |
| Simulation time | 10081035028 ps |
| CPU time | 401.69 seconds |
| Started | Aug 24 06:26:22 AM UTC 24 |
| Finished | Aug 24 06:33:09 AM UTC 24 |
| Peak memory | 597820 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3300046927 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 58.xbar_stress_all_with_rand_reset.3300046927 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/58.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/58.xbar_stress_all_with_reset_error.2617917758 |
| Short name | T2197 |
| Test name | |
| Test status | |
| Simulation time | 285939193 ps |
| CPU time | 71.52 seconds |
| Started | Aug 24 06:26:24 AM UTC 24 |
| Finished | Aug 24 06:27:38 AM UTC 24 |
| Peak memory | 597924 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2617917758 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 58.xbar_stress_all_with_reset_error.2617917758 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/58.xbar_stress_all_with_reset_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/58.xbar_unmapped_addr.192796353 |
| Short name | T2192 |
| Test name | |
| Test status | |
| Simulation time | 1279688439 ps |
| CPU time | 38.06 seconds |
| Started | Aug 24 06:26:04 AM UTC 24 |
| Finished | Aug 24 06:26:44 AM UTC 24 |
| Peak memory | 597832 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=192796353 -assert nopostproc +UVM_TESTNAME =xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 58.xbar_unmapped_addr.192796353 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/58.xbar_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/59.xbar_access_same_device.129635326 |
| Short name | T2204 |
| Test name | |
| Test status | |
| Simulation time | 2341797471 ps |
| CPU time | 60.18 seconds |
| Started | Aug 24 06:26:58 AM UTC 24 |
| Finished | Aug 24 06:28:00 AM UTC 24 |
| Peak memory | 597772 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=129635326 -assert nopostproc +UVM_TESTNAME =xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 59.xbar_access_same_device.129635326 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/59.xbar_access_same_device/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/59.xbar_access_same_device_slow_rsp.2627599342 |
| Short name | T2222 |
| Test name | |
| Test status | |
| Simulation time | 10561716278 ps |
| CPU time | 122.94 seconds |
| Started | Aug 24 06:27:18 AM UTC 24 |
| Finished | Aug 24 06:29:23 AM UTC 24 |
| Peak memory | 598084 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2627599342 -assert nopostproc +UVM_T ESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 59.xbar_access_same_device_slow_rsp.2627599342 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/59.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/59.xbar_error_and_unmapped_addr.3575056730 |
| Short name | T2207 |
| Test name | |
| Test status | |
| Simulation time | 534898955 ps |
| CPU time | 16.46 seconds |
| Started | Aug 24 06:27:51 AM UTC 24 |
| Finished | Aug 24 06:28:09 AM UTC 24 |
| Peak memory | 597700 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3575056730 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 59.xbar_error_and_unmapped_addr.3575056730 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/59.xbar_error_and_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/59.xbar_error_random.1271579513 |
| Short name | T2205 |
| Test name | |
| Test status | |
| Simulation time | 1514000731 ps |
| CPU time | 34.31 seconds |
| Started | Aug 24 06:27:28 AM UTC 24 |
| Finished | Aug 24 06:28:04 AM UTC 24 |
| Peak memory | 597756 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1271579513 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 59.xbar_error_random.1271579513 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/59.xbar_error_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/59.xbar_random.1857556242 |
| Short name | T2198 |
| Test name | |
| Test status | |
| Simulation time | 2028739892 ps |
| CPU time | 51.95 seconds |
| Started | Aug 24 06:26:46 AM UTC 24 |
| Finished | Aug 24 06:27:39 AM UTC 24 |
| Peak memory | 597832 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1857556242 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 59.xbar_random.1857556242 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/59.xbar_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/59.xbar_random_large_delays.1082318435 |
| Short name | T2275 |
| Test name | |
| Test status | |
| Simulation time | 54724866301 ps |
| CPU time | 444.68 seconds |
| Started | Aug 24 06:26:55 AM UTC 24 |
| Finished | Aug 24 06:34:24 AM UTC 24 |
| Peak memory | 597896 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max _device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1082318435 -assert nopostproc +U VM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 59.xbar_random_large_delays.1082318435 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/59.xbar_random_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/59.xbar_random_slow_rsp.3495243975 |
| Short name | T2286 |
| Test name | |
| Test status | |
| Simulation time | 43622368922 ps |
| CPU time | 504.25 seconds |
| Started | Aug 24 06:26:58 AM UTC 24 |
| Finished | Aug 24 06:35:28 AM UTC 24 |
| Peak memory | 598072 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3495243975 -assert nopostproc +UVM_T ESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 59.xbar_random_slow_rsp.3495243975 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/59.xbar_random_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/59.xbar_random_zero_delays.2619358561 |
| Short name | T2194 |
| Test name | |
| Test status | |
| Simulation time | 123552611 ps |
| CPU time | 9.68 seconds |
| Started | Aug 24 06:26:54 AM UTC 24 |
| Finished | Aug 24 06:27:05 AM UTC 24 |
| Peak memory | 597696 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2619358561 -assert nopostpr oc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 59.xbar_random_zero_delays.2619358561 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/59.xbar_random_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/59.xbar_same_source.1148802061 |
| Short name | T2196 |
| Test name | |
| Test status | |
| Simulation time | 439284496 ps |
| CPU time | 11.24 seconds |
| Started | Aug 24 06:27:19 AM UTC 24 |
| Finished | Aug 24 06:27:31 AM UTC 24 |
| Peak memory | 597928 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1148802061 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 59.xbar_same_source.1148802061 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/59.xbar_same_source/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/59.xbar_smoke.559967196 |
| Short name | T2190 |
| Test name | |
| Test status | |
| Simulation time | 225399946 ps |
| CPU time | 7.04 seconds |
| Started | Aug 24 06:26:32 AM UTC 24 |
| Finished | Aug 24 06:26:41 AM UTC 24 |
| Peak memory | 595780 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=559967196 -assert nopostproc +UVM_TESTNAME =xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08 _22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 59.xbar_smoke.559967196 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/59.xbar_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/59.xbar_smoke_large_delays.1090136979 |
| Short name | T2202 |
| Test name | |
| Test status | |
| Simulation time | 8793460581 ps |
| CPU time | 70.65 seconds |
| Started | Aug 24 06:26:36 AM UTC 24 |
| Finished | Aug 24 06:27:48 AM UTC 24 |
| Peak memory | 595904 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max _device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1090136979 -assert nopostproc +U VM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 59.xbar_smoke_large_delays.1090136979 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/59.xbar_smoke_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/59.xbar_smoke_slow_rsp.741766624 |
| Short name | T2200 |
| Test name | |
| Test status | |
| Simulation time | 4791314871 ps |
| CPU time | 57.47 seconds |
| Started | Aug 24 06:26:44 AM UTC 24 |
| Finished | Aug 24 06:27:43 AM UTC 24 |
| Peak memory | 595768 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=741766624 -assert nopostproc +UVM_TE STNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 59.xbar_smoke_slow_rsp.741766624 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/59.xbar_smoke_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/59.xbar_smoke_zero_delays.2566932107 |
| Short name | T2189 |
| Test name | |
| Test status | |
| Simulation time | 47861514 ps |
| CPU time | 5.1 seconds |
| Started | Aug 24 06:26:34 AM UTC 24 |
| Finished | Aug 24 06:26:40 AM UTC 24 |
| Peak memory | 595632 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2566932107 -assert nopostpr oc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 59.xbar_smoke_zero_delays.2566932107 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/59.xbar_smoke_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/59.xbar_stress_all.2402512260 |
| Short name | T2235 |
| Test name | |
| Test status | |
| Simulation time | 2976817766 ps |
| CPU time | 177.77 seconds |
| Started | Aug 24 06:27:53 AM UTC 24 |
| Finished | Aug 24 06:30:54 AM UTC 24 |
| Peak memory | 597764 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2402512260 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 59.xbar_stress_all.2402512260 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/59.xbar_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/59.xbar_stress_all_with_error.1420845892 |
| Short name | T2216 |
| Test name | |
| Test status | |
| Simulation time | 1043640271 ps |
| CPU time | 57.54 seconds |
| Started | Aug 24 06:27:57 AM UTC 24 |
| Finished | Aug 24 06:28:56 AM UTC 24 |
| Peak memory | 597952 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1420845892 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 59.xbar_stress_all_with_error.1420845892 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/59.xbar_stress_all_with_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/59.xbar_stress_all_with_rand_reset.3707057017 |
| Short name | T2231 |
| Test name | |
| Test status | |
| Simulation time | 2349436743 ps |
| CPU time | 150.51 seconds |
| Started | Aug 24 06:27:54 AM UTC 24 |
| Finished | Aug 24 06:30:27 AM UTC 24 |
| Peak memory | 598040 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3707057017 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 59.xbar_stress_all_with_rand_reset.3707057017 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/59.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/59.xbar_stress_all_with_reset_error.819625283 |
| Short name | T2237 |
| Test name | |
| Test status | |
| Simulation time | 661731239 ps |
| CPU time | 175.94 seconds |
| Started | Aug 24 06:27:58 AM UTC 24 |
| Finished | Aug 24 06:30:57 AM UTC 24 |
| Peak memory | 597688 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=819625283 -assert nopostproc +UVM_TESTNAME =xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 59.xbar_stress_all_with_reset_error.819625283 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/59.xbar_stress_all_with_reset_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/59.xbar_unmapped_addr.3398618363 |
| Short name | T2208 |
| Test name | |
| Test status | |
| Simulation time | 749199801 ps |
| CPU time | 23.12 seconds |
| Started | Aug 24 06:27:45 AM UTC 24 |
| Finished | Aug 24 06:28:09 AM UTC 24 |
| Peak memory | 598008 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3398618363 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 59.xbar_unmapped_addr.3398618363 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/59.xbar_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/6.chip_csr_mem_rw_with_rand_reset.3914937585 |
| Short name | T420 |
| Test name | |
| Test status | |
| Simulation time | 6920202957 ps |
| CPU time | 288.49 seconds |
| Started | Aug 24 04:16:39 AM UTC 24 |
| Finished | Aug 24 04:21:31 AM UTC 24 |
| Peak memory | 662420 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000 000000 +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/too ls/sim.tcl +ntb_random_seed=3914937585 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/nul l -cm_name 6.chip_csr_mem_rw_with_rand_reset.3914937585 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/6.chip_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/6.chip_csr_rw.1748838671 |
| Short name | T544 |
| Test name | |
| Test status | |
| Simulation time | 5980020920 ps |
| CPU time | 468.5 seconds |
| Started | Aug 24 04:16:30 AM UTC 24 |
| Finished | Aug 24 04:24:24 AM UTC 24 |
| Peak memory | 619228 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +stub_cpu=1 +cdc_instrumentation_ena bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1748838671 -assert nopost proc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os _regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.chip_csr_rw.1748838671 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/6.chip_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/6.chip_same_csr_outstanding.3736495499 |
| Short name | T1492 |
| Test name | |
| Test status | |
| Simulation time | 33023519482 ps |
| CPU time | 2677.8 seconds |
| Started | Aug 24 04:11:59 AM UTC 24 |
| Finished | Aug 24 04:57:04 AM UTC 24 |
| Peak memory | 614108 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +test_timeout_ns=120_000_000 +run_same_csr_outstanding +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim .tcl +ntb_random_seed=3736495499 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_ name 6.chip_same_csr_outstanding.3736495499 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/6.chip_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/6.chip_tl_errors.1967886456 |
| Short name | T564 |
| Test name | |
| Test status | |
| Simulation time | 3188305290 ps |
| CPU time | 96.5 seconds |
| Started | Aug 24 04:12:26 AM UTC 24 |
| Finished | Aug 24 04:14:04 AM UTC 24 |
| Peak memory | 613216 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enable d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1967886456 -assert nopostpro c +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.chip_tl_errors.1967886456 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/6.chip_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/6.xbar_error_and_unmapped_addr.2101943403 |
| Short name | T1373 |
| Test name | |
| Test status | |
| Simulation time | 232240378 ps |
| CPU time | 20.23 seconds |
| Started | Aug 24 04:16:03 AM UTC 24 |
| Finished | Aug 24 04:16:25 AM UTC 24 |
| Peak memory | 597692 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2101943403 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.xbar_error_and_unmapped_addr.2101943403 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/6.xbar_error_and_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/6.xbar_error_random.1086516629 |
| Short name | T1371 |
| Test name | |
| Test status | |
| Simulation time | 342122803 ps |
| CPU time | 11.24 seconds |
| Started | Aug 24 04:15:57 AM UTC 24 |
| Finished | Aug 24 04:16:10 AM UTC 24 |
| Peak memory | 597912 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1086516629 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.xbar_error_random.1086516629 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/6.xbar_error_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/6.xbar_random.1331624975 |
| Short name | T563 |
| Test name | |
| Test status | |
| Simulation time | 1432673155 ps |
| CPU time | 34.51 seconds |
| Started | Aug 24 04:13:44 AM UTC 24 |
| Finished | Aug 24 04:14:20 AM UTC 24 |
| Peak memory | 597696 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1331624975 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.xbar_random.1331624975 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/6.xbar_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/6.xbar_random_large_delays.3696100217 |
| Short name | T477 |
| Test name | |
| Test status | |
| Simulation time | 11112570303 ps |
| CPU time | 95.32 seconds |
| Started | Aug 24 04:14:34 AM UTC 24 |
| Finished | Aug 24 04:16:11 AM UTC 24 |
| Peak memory | 597968 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max _device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3696100217 -assert nopostproc +U VM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.xbar_random_large_delays.3696100217 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/6.xbar_random_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/6.xbar_random_slow_rsp.1083550438 |
| Short name | T591 |
| Test name | |
| Test status | |
| Simulation time | 36601748894 ps |
| CPU time | 424.08 seconds |
| Started | Aug 24 04:14:34 AM UTC 24 |
| Finished | Aug 24 04:21:43 AM UTC 24 |
| Peak memory | 597888 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1083550438 -assert nopostproc +UVM_T ESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.xbar_random_slow_rsp.1083550438 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/6.xbar_random_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/6.xbar_random_zero_delays.290954341 |
| Short name | T594 |
| Test name | |
| Test status | |
| Simulation time | 465737849 ps |
| CPU time | 32.36 seconds |
| Started | Aug 24 04:14:18 AM UTC 24 |
| Finished | Aug 24 04:14:52 AM UTC 24 |
| Peak memory | 597692 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=290954341 -assert nopostpro c +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.xbar_random_zero_delays.290954341 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/6.xbar_random_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/6.xbar_same_source.2926854788 |
| Short name | T494 |
| Test name | |
| Test status | |
| Simulation time | 1345566129 ps |
| CPU time | 30.64 seconds |
| Started | Aug 24 04:15:11 AM UTC 24 |
| Finished | Aug 24 04:15:43 AM UTC 24 |
| Peak memory | 597692 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2926854788 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.xbar_same_source.2926854788 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/6.xbar_same_source/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/6.xbar_smoke.855892118 |
| Short name | T537 |
| Test name | |
| Test status | |
| Simulation time | 49962729 ps |
| CPU time | 5.36 seconds |
| Started | Aug 24 04:13:03 AM UTC 24 |
| Finished | Aug 24 04:13:09 AM UTC 24 |
| Peak memory | 595628 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=855892118 -assert nopostproc +UVM_TESTNAME =xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08 _22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.xbar_smoke.855892118 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/6.xbar_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/6.xbar_smoke_large_delays.994946486 |
| Short name | T1369 |
| Test name | |
| Test status | |
| Simulation time | 6720667010 ps |
| CPU time | 53.55 seconds |
| Started | Aug 24 04:13:25 AM UTC 24 |
| Finished | Aug 24 04:14:20 AM UTC 24 |
| Peak memory | 595764 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max _device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=994946486 -assert nopostproc +UV M_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.xbar_smoke_large_delays.994946486 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/6.xbar_smoke_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/6.xbar_smoke_slow_rsp.2261732080 |
| Short name | T1370 |
| Test name | |
| Test status | |
| Simulation time | 6525150824 ps |
| CPU time | 79.23 seconds |
| Started | Aug 24 04:13:36 AM UTC 24 |
| Finished | Aug 24 04:14:57 AM UTC 24 |
| Peak memory | 596020 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2261732080 -assert nopostproc +UVM_T ESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.xbar_smoke_slow_rsp.2261732080 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/6.xbar_smoke_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/6.xbar_smoke_zero_delays.4218546481 |
| Short name | T1368 |
| Test name | |
| Test status | |
| Simulation time | 45077405 ps |
| CPU time | 5.1 seconds |
| Started | Aug 24 04:13:24 AM UTC 24 |
| Finished | Aug 24 04:13:30 AM UTC 24 |
| Peak memory | 595856 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4218546481 -assert nopostpr oc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.xbar_smoke_zero_delays.4218546481 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/6.xbar_smoke_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/6.xbar_stress_all_with_error.189929403 |
| Short name | T1374 |
| Test name | |
| Test status | |
| Simulation time | 1201141995 ps |
| CPU time | 64.64 seconds |
| Started | Aug 24 04:16:24 AM UTC 24 |
| Finished | Aug 24 04:17:30 AM UTC 24 |
| Peak memory | 597908 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=189929403 -assert nopostproc +UVM_TESTNAME =xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.xbar_stress_all_with_error.189929403 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/6.xbar_stress_all_with_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/6.xbar_stress_all_with_rand_reset.416381542 |
| Short name | T513 |
| Test name | |
| Test status | |
| Simulation time | 5231358966 ps |
| CPU time | 307.05 seconds |
| Started | Aug 24 04:16:21 AM UTC 24 |
| Finished | Aug 24 04:21:32 AM UTC 24 |
| Peak memory | 597888 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=416381542 -assert nopostproc +UVM_TESTNAME =xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.xbar_stress_all_with_rand_reset.416381542 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/6.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/6.xbar_unmapped_addr.601092888 |
| Short name | T1372 |
| Test name | |
| Test status | |
| Simulation time | 150685099 ps |
| CPU time | 14.26 seconds |
| Started | Aug 24 04:16:01 AM UTC 24 |
| Finished | Aug 24 04:16:16 AM UTC 24 |
| Peak memory | 597688 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=601092888 -assert nopostproc +UVM_TESTNAME =xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.xbar_unmapped_addr.601092888 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/6.xbar_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/60.xbar_access_same_device.1026837795 |
| Short name | T2215 |
| Test name | |
| Test status | |
| Simulation time | 248103210 ps |
| CPU time | 20.56 seconds |
| Started | Aug 24 06:28:32 AM UTC 24 |
| Finished | Aug 24 06:28:54 AM UTC 24 |
| Peak memory | 597836 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1026837795 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 60.xbar_access_same_device.1026837795 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/60.xbar_access_same_device/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/60.xbar_access_same_device_slow_rsp.2984287473 |
| Short name | T2535 |
| Test name | |
| Test status | |
| Simulation time | 155319733048 ps |
| CPU time | 1816.5 seconds |
| Started | Aug 24 06:28:32 AM UTC 24 |
| Finished | Aug 24 06:59:05 AM UTC 24 |
| Peak memory | 599036 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2984287473 -assert nopostproc +UVM_T ESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 60.xbar_access_same_device_slow_rsp.2984287473 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/60.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/60.xbar_error_and_unmapped_addr.1934610205 |
| Short name | T2224 |
| Test name | |
| Test status | |
| Simulation time | 243629969 ps |
| CPU time | 18.2 seconds |
| Started | Aug 24 06:29:08 AM UTC 24 |
| Finished | Aug 24 06:29:27 AM UTC 24 |
| Peak memory | 597908 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1934610205 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 60.xbar_error_and_unmapped_addr.1934610205 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/60.xbar_error_and_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/60.xbar_error_random.315770770 |
| Short name | T2219 |
| Test name | |
| Test status | |
| Simulation time | 140094131 ps |
| CPU time | 10.4 seconds |
| Started | Aug 24 06:28:56 AM UTC 24 |
| Finished | Aug 24 06:29:08 AM UTC 24 |
| Peak memory | 597768 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=315770770 -assert nopostproc +UVM_TESTNAME =xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 60.xbar_error_random.315770770 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/60.xbar_error_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/60.xbar_random.3695979147 |
| Short name | T2223 |
| Test name | |
| Test status | |
| Simulation time | 2516039926 ps |
| CPU time | 60.61 seconds |
| Started | Aug 24 06:28:22 AM UTC 24 |
| Finished | Aug 24 06:29:25 AM UTC 24 |
| Peak memory | 597908 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3695979147 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 60.xbar_random.3695979147 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/60.xbar_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/60.xbar_random_large_delays.2215643125 |
| Short name | T2357 |
| Test name | |
| Test status | |
| Simulation time | 96542663894 ps |
| CPU time | 759.19 seconds |
| Started | Aug 24 06:28:24 AM UTC 24 |
| Finished | Aug 24 06:41:12 AM UTC 24 |
| Peak memory | 597964 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max _device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2215643125 -assert nopostproc +U VM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 60.xbar_random_large_delays.2215643125 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/60.xbar_random_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/60.xbar_random_slow_rsp.349827295 |
| Short name | T2298 |
| Test name | |
| Test status | |
| Simulation time | 40884857409 ps |
| CPU time | 467.21 seconds |
| Started | Aug 24 06:28:25 AM UTC 24 |
| Finished | Aug 24 06:36:18 AM UTC 24 |
| Peak memory | 597828 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=349827295 -assert nopostproc +UVM_TE STNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 60.xbar_random_slow_rsp.349827295 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/60.xbar_random_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/60.xbar_random_zero_delays.1094718839 |
| Short name | T2213 |
| Test name | |
| Test status | |
| Simulation time | 248895315 ps |
| CPU time | 17.36 seconds |
| Started | Aug 24 06:28:23 AM UTC 24 |
| Finished | Aug 24 06:28:42 AM UTC 24 |
| Peak memory | 597824 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1094718839 -assert nopostpr oc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 60.xbar_random_zero_delays.1094718839 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/60.xbar_random_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/60.xbar_same_source.4056307976 |
| Short name | T2218 |
| Test name | |
| Test status | |
| Simulation time | 359100901 ps |
| CPU time | 9.99 seconds |
| Started | Aug 24 06:28:53 AM UTC 24 |
| Finished | Aug 24 06:29:04 AM UTC 24 |
| Peak memory | 597680 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4056307976 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 60.xbar_same_source.4056307976 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/60.xbar_same_source/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/60.xbar_smoke.957947321 |
| Short name | T2206 |
| Test name | |
| Test status | |
| Simulation time | 54481046 ps |
| CPU time | 5.38 seconds |
| Started | Aug 24 06:28:01 AM UTC 24 |
| Finished | Aug 24 06:28:08 AM UTC 24 |
| Peak memory | 595756 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=957947321 -assert nopostproc +UVM_TESTNAME =xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08 _22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 60.xbar_smoke.957947321 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/60.xbar_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/60.xbar_smoke_large_delays.3583105899 |
| Short name | T2221 |
| Test name | |
| Test status | |
| Simulation time | 7767298451 ps |
| CPU time | 62.25 seconds |
| Started | Aug 24 06:28:14 AM UTC 24 |
| Finished | Aug 24 06:29:17 AM UTC 24 |
| Peak memory | 595768 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max _device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3583105899 -assert nopostproc +U VM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 60.xbar_smoke_large_delays.3583105899 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/60.xbar_smoke_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/60.xbar_smoke_slow_rsp.4172339631 |
| Short name | T2220 |
| Test name | |
| Test status | |
| Simulation time | 4261647732 ps |
| CPU time | 50.23 seconds |
| Started | Aug 24 06:28:18 AM UTC 24 |
| Finished | Aug 24 06:29:10 AM UTC 24 |
| Peak memory | 595704 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4172339631 -assert nopostproc +UVM_T ESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 60.xbar_smoke_slow_rsp.4172339631 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/60.xbar_smoke_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/60.xbar_smoke_zero_delays.4027483049 |
| Short name | T2209 |
| Test name | |
| Test status | |
| Simulation time | 50031846 ps |
| CPU time | 5.29 seconds |
| Started | Aug 24 06:28:05 AM UTC 24 |
| Finished | Aug 24 06:28:11 AM UTC 24 |
| Peak memory | 595632 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4027483049 -assert nopostpr oc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 60.xbar_smoke_zero_delays.4027483049 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/60.xbar_smoke_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/60.xbar_stress_all.1317800960 |
| Short name | T2268 |
| Test name | |
| Test status | |
| Simulation time | 10547578083 ps |
| CPU time | 286.84 seconds |
| Started | Aug 24 06:29:10 AM UTC 24 |
| Finished | Aug 24 06:34:01 AM UTC 24 |
| Peak memory | 597824 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1317800960 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 60.xbar_stress_all.1317800960 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/60.xbar_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/60.xbar_stress_all_with_error.1630687779 |
| Short name | T2236 |
| Test name | |
| Test status | |
| Simulation time | 1802533171 ps |
| CPU time | 95.68 seconds |
| Started | Aug 24 06:29:19 AM UTC 24 |
| Finished | Aug 24 06:30:56 AM UTC 24 |
| Peak memory | 597700 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1630687779 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 60.xbar_stress_all_with_error.1630687779 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/60.xbar_stress_all_with_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/60.xbar_stress_all_with_rand_reset.2488880751 |
| Short name | T2251 |
| Test name | |
| Test status | |
| Simulation time | 414270940 ps |
| CPU time | 175.49 seconds |
| Started | Aug 24 06:29:14 AM UTC 24 |
| Finished | Aug 24 06:32:12 AM UTC 24 |
| Peak memory | 597688 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2488880751 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 60.xbar_stress_all_with_rand_reset.2488880751 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/60.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/60.xbar_stress_all_with_reset_error.2067272980 |
| Short name | T2265 |
| Test name | |
| Test status | |
| Simulation time | 2043043892 ps |
| CPU time | 256.58 seconds |
| Started | Aug 24 06:29:21 AM UTC 24 |
| Finished | Aug 24 06:33:41 AM UTC 24 |
| Peak memory | 597696 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2067272980 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 60.xbar_stress_all_with_reset_error.2067272980 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/60.xbar_stress_all_with_reset_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/60.xbar_unmapped_addr.818044580 |
| Short name | T2227 |
| Test name | |
| Test status | |
| Simulation time | 1133962204 ps |
| CPU time | 33.22 seconds |
| Started | Aug 24 06:29:04 AM UTC 24 |
| Finished | Aug 24 06:29:39 AM UTC 24 |
| Peak memory | 597756 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=818044580 -assert nopostproc +UVM_TESTNAME =xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 60.xbar_unmapped_addr.818044580 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/60.xbar_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/61.xbar_access_same_device.3550147096 |
| Short name | T2244 |
| Test name | |
| Test status | |
| Simulation time | 3170621259 ps |
| CPU time | 84.45 seconds |
| Started | Aug 24 06:30:10 AM UTC 24 |
| Finished | Aug 24 06:31:36 AM UTC 24 |
| Peak memory | 597768 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3550147096 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 61.xbar_access_same_device.3550147096 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/61.xbar_access_same_device/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/61.xbar_access_same_device_slow_rsp.558350726 |
| Short name | T2349 |
| Test name | |
| Test status | |
| Simulation time | 52183641163 ps |
| CPU time | 619.12 seconds |
| Started | Aug 24 06:30:29 AM UTC 24 |
| Finished | Aug 24 06:40:54 AM UTC 24 |
| Peak memory | 597828 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=558350726 -assert nopostproc +UVM_TE STNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os _regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 61.xbar_access_same_device_slow_rsp.558350726 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/61.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/61.xbar_error_and_unmapped_addr.2031147796 |
| Short name | T2241 |
| Test name | |
| Test status | |
| Simulation time | 84553144 ps |
| CPU time | 8.6 seconds |
| Started | Aug 24 06:31:05 AM UTC 24 |
| Finished | Aug 24 06:31:15 AM UTC 24 |
| Peak memory | 597968 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2031147796 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 61.xbar_error_and_unmapped_addr.2031147796 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/61.xbar_error_and_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/61.xbar_error_random.1365848 |
| Short name | T2233 |
| Test name | |
| Test status | |
| Simulation time | 259507293 ps |
| CPU time | 8.83 seconds |
| Started | Aug 24 06:30:41 AM UTC 24 |
| Finished | Aug 24 06:30:51 AM UTC 24 |
| Peak memory | 595648 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1365848 -assert nopostproc +UVM_TESTNAME=x bar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08 _22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 61.xbar_error_random.1365848 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/61.xbar_error_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/61.xbar_random.3482945532 |
| Short name | T2228 |
| Test name | |
| Test status | |
| Simulation time | 181106179 ps |
| CPU time | 13.32 seconds |
| Started | Aug 24 06:29:42 AM UTC 24 |
| Finished | Aug 24 06:29:56 AM UTC 24 |
| Peak memory | 597760 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3482945532 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 61.xbar_random.3482945532 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/61.xbar_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/61.xbar_random_large_delays.3350735945 |
| Short name | T2245 |
| Test name | |
| Test status | |
| Simulation time | 13886065660 ps |
| CPU time | 111.06 seconds |
| Started | Aug 24 06:29:52 AM UTC 24 |
| Finished | Aug 24 06:31:45 AM UTC 24 |
| Peak memory | 597824 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max _device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3350735945 -assert nopostproc +U VM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 61.xbar_random_large_delays.3350735945 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/61.xbar_random_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/61.xbar_random_slow_rsp.2362871097 |
| Short name | T2293 |
| Test name | |
| Test status | |
| Simulation time | 29810303115 ps |
| CPU time | 360.84 seconds |
| Started | Aug 24 06:29:53 AM UTC 24 |
| Finished | Aug 24 06:35:58 AM UTC 24 |
| Peak memory | 597828 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2362871097 -assert nopostproc +UVM_T ESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 61.xbar_random_slow_rsp.2362871097 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/61.xbar_random_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/61.xbar_random_zero_delays.2462691961 |
| Short name | T2229 |
| Test name | |
| Test status | |
| Simulation time | 499399820 ps |
| CPU time | 29.56 seconds |
| Started | Aug 24 06:29:43 AM UTC 24 |
| Finished | Aug 24 06:30:14 AM UTC 24 |
| Peak memory | 597700 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2462691961 -assert nopostpr oc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 61.xbar_random_zero_delays.2462691961 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/61.xbar_random_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/61.xbar_same_source.3008529715 |
| Short name | T2239 |
| Test name | |
| Test status | |
| Simulation time | 1730538482 ps |
| CPU time | 36.63 seconds |
| Started | Aug 24 06:30:31 AM UTC 24 |
| Finished | Aug 24 06:31:09 AM UTC 24 |
| Peak memory | 597752 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3008529715 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 61.xbar_same_source.3008529715 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/61.xbar_same_source/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/61.xbar_smoke.82357864 |
| Short name | T2225 |
| Test name | |
| Test status | |
| Simulation time | 49552731 ps |
| CPU time | 5.34 seconds |
| Started | Aug 24 06:29:23 AM UTC 24 |
| Finished | Aug 24 06:29:30 AM UTC 24 |
| Peak memory | 595772 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=82357864 -assert nopostproc +UVM_TESTNAME= xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_ 22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 61.xbar_smoke.82357864 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/61.xbar_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/61.xbar_smoke_large_delays.1787576769 |
| Short name | T2234 |
| Test name | |
| Test status | |
| Simulation time | 8755119800 ps |
| CPU time | 74.56 seconds |
| Started | Aug 24 06:29:36 AM UTC 24 |
| Finished | Aug 24 06:30:53 AM UTC 24 |
| Peak memory | 595768 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max _device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1787576769 -assert nopostproc +U VM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 61.xbar_smoke_large_delays.1787576769 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/61.xbar_smoke_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/61.xbar_smoke_slow_rsp.2240633021 |
| Short name | T2232 |
| Test name | |
| Test status | |
| Simulation time | 4120335756 ps |
| CPU time | 50.18 seconds |
| Started | Aug 24 06:29:38 AM UTC 24 |
| Finished | Aug 24 06:30:30 AM UTC 24 |
| Peak memory | 595844 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2240633021 -assert nopostproc +UVM_T ESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 61.xbar_smoke_slow_rsp.2240633021 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/61.xbar_smoke_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/61.xbar_smoke_zero_delays.2515751898 |
| Short name | T2226 |
| Test name | |
| Test status | |
| Simulation time | 46956405 ps |
| CPU time | 5.09 seconds |
| Started | Aug 24 06:29:32 AM UTC 24 |
| Finished | Aug 24 06:29:38 AM UTC 24 |
| Peak memory | 595696 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2515751898 -assert nopostpr oc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 61.xbar_smoke_zero_delays.2515751898 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/61.xbar_smoke_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/61.xbar_stress_all.4100823980 |
| Short name | T2271 |
| Test name | |
| Test status | |
| Simulation time | 3305545178 ps |
| CPU time | 177.47 seconds |
| Started | Aug 24 06:31:07 AM UTC 24 |
| Finished | Aug 24 06:34:07 AM UTC 24 |
| Peak memory | 597900 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4100823980 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 61.xbar_stress_all.4100823980 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/61.xbar_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/61.xbar_stress_all_with_error.2966259611 |
| Short name | T2302 |
| Test name | |
| Test status | |
| Simulation time | 14504213191 ps |
| CPU time | 323.51 seconds |
| Started | Aug 24 06:31:10 AM UTC 24 |
| Finished | Aug 24 06:36:38 AM UTC 24 |
| Peak memory | 597892 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2966259611 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 61.xbar_stress_all_with_error.2966259611 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/61.xbar_stress_all_with_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/61.xbar_stress_all_with_rand_reset.1013001273 |
| Short name | T2249 |
| Test name | |
| Test status | |
| Simulation time | 315896920 ps |
| CPU time | 53.81 seconds |
| Started | Aug 24 06:31:08 AM UTC 24 |
| Finished | Aug 24 06:32:04 AM UTC 24 |
| Peak memory | 597756 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1013001273 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 61.xbar_stress_all_with_rand_reset.1013001273 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/61.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/61.xbar_unmapped_addr.3491579031 |
| Short name | T2240 |
| Test name | |
| Test status | |
| Simulation time | 818024401 ps |
| CPU time | 24.82 seconds |
| Started | Aug 24 06:30:44 AM UTC 24 |
| Finished | Aug 24 06:31:10 AM UTC 24 |
| Peak memory | 597692 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3491579031 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 61.xbar_unmapped_addr.3491579031 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/61.xbar_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/62.xbar_access_same_device.2841181500 |
| Short name | T2256 |
| Test name | |
| Test status | |
| Simulation time | 977818174 ps |
| CPU time | 30.47 seconds |
| Started | Aug 24 06:32:05 AM UTC 24 |
| Finished | Aug 24 06:32:37 AM UTC 24 |
| Peak memory | 597992 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2841181500 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 62.xbar_access_same_device.2841181500 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/62.xbar_access_same_device/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/62.xbar_access_same_device_slow_rsp.2287987919 |
| Short name | T2374 |
| Test name | |
| Test status | |
| Simulation time | 55038331593 ps |
| CPU time | 629.5 seconds |
| Started | Aug 24 06:32:12 AM UTC 24 |
| Finished | Aug 24 06:42:48 AM UTC 24 |
| Peak memory | 597828 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2287987919 -assert nopostproc +UVM_T ESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 62.xbar_access_same_device_slow_rsp.2287987919 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/62.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/62.xbar_error_and_unmapped_addr.1967945732 |
| Short name | T2260 |
| Test name | |
| Test status | |
| Simulation time | 332872758 ps |
| CPU time | 24.92 seconds |
| Started | Aug 24 06:32:26 AM UTC 24 |
| Finished | Aug 24 06:32:52 AM UTC 24 |
| Peak memory | 597828 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1967945732 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 62.xbar_error_and_unmapped_addr.1967945732 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/62.xbar_error_and_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/62.xbar_error_random.3237824492 |
| Short name | T2257 |
| Test name | |
| Test status | |
| Simulation time | 1000835684 ps |
| CPU time | 25.59 seconds |
| Started | Aug 24 06:32:18 AM UTC 24 |
| Finished | Aug 24 06:32:45 AM UTC 24 |
| Peak memory | 597920 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3237824492 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 62.xbar_error_random.3237824492 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/62.xbar_error_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/62.xbar_random.1068789652 |
| Short name | T2250 |
| Test name | |
| Test status | |
| Simulation time | 453148549 ps |
| CPU time | 28.98 seconds |
| Started | Aug 24 06:31:34 AM UTC 24 |
| Finished | Aug 24 06:32:04 AM UTC 24 |
| Peak memory | 597752 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1068789652 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 62.xbar_random.1068789652 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/62.xbar_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/62.xbar_random_large_delays.3651901790 |
| Short name | T2355 |
| Test name | |
| Test status | |
| Simulation time | 68061918201 ps |
| CPU time | 553.76 seconds |
| Started | Aug 24 06:31:50 AM UTC 24 |
| Finished | Aug 24 06:41:10 AM UTC 24 |
| Peak memory | 597824 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max _device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3651901790 -assert nopostproc +U VM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 62.xbar_random_large_delays.3651901790 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/62.xbar_random_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/62.xbar_random_slow_rsp.1861943464 |
| Short name | T2346 |
| Test name | |
| Test status | |
| Simulation time | 44294810856 ps |
| CPU time | 515.03 seconds |
| Started | Aug 24 06:31:59 AM UTC 24 |
| Finished | Aug 24 06:40:39 AM UTC 24 |
| Peak memory | 598032 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1861943464 -assert nopostproc +UVM_T ESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 62.xbar_random_slow_rsp.1861943464 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/62.xbar_random_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/62.xbar_random_zero_delays.2657609209 |
| Short name | T2246 |
| Test name | |
| Test status | |
| Simulation time | 57556376 ps |
| CPU time | 6.57 seconds |
| Started | Aug 24 06:31:43 AM UTC 24 |
| Finished | Aug 24 06:31:50 AM UTC 24 |
| Peak memory | 597760 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2657609209 -assert nopostpr oc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 62.xbar_random_zero_delays.2657609209 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/62.xbar_random_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/62.xbar_same_source.2032811764 |
| Short name | T2254 |
| Test name | |
| Test status | |
| Simulation time | 490726824 ps |
| CPU time | 12.83 seconds |
| Started | Aug 24 06:32:16 AM UTC 24 |
| Finished | Aug 24 06:32:30 AM UTC 24 |
| Peak memory | 597756 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2032811764 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 62.xbar_same_source.2032811764 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/62.xbar_same_source/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/62.xbar_smoke.2477344930 |
| Short name | T2242 |
| Test name | |
| Test status | |
| Simulation time | 56272365 ps |
| CPU time | 5.44 seconds |
| Started | Aug 24 06:31:13 AM UTC 24 |
| Finished | Aug 24 06:31:19 AM UTC 24 |
| Peak memory | 595852 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2477344930 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 8_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 62.xbar_smoke.2477344930 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/62.xbar_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/62.xbar_smoke_large_delays.1634367418 |
| Short name | T2253 |
| Test name | |
| Test status | |
| Simulation time | 7302907774 ps |
| CPU time | 60.8 seconds |
| Started | Aug 24 06:31:25 AM UTC 24 |
| Finished | Aug 24 06:32:27 AM UTC 24 |
| Peak memory | 595772 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max _device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1634367418 -assert nopostproc +U VM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 62.xbar_smoke_large_delays.1634367418 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/62.xbar_smoke_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/62.xbar_smoke_slow_rsp.1244980706 |
| Short name | T2258 |
| Test name | |
| Test status | |
| Simulation time | 6472967192 ps |
| CPU time | 74.9 seconds |
| Started | Aug 24 06:31:29 AM UTC 24 |
| Finished | Aug 24 06:32:45 AM UTC 24 |
| Peak memory | 595972 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1244980706 -assert nopostproc +UVM_T ESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 62.xbar_smoke_slow_rsp.1244980706 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/62.xbar_smoke_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/62.xbar_smoke_zero_delays.2978038246 |
| Short name | T2243 |
| Test name | |
| Test status | |
| Simulation time | 47496029 ps |
| CPU time | 5.14 seconds |
| Started | Aug 24 06:31:23 AM UTC 24 |
| Finished | Aug 24 06:31:29 AM UTC 24 |
| Peak memory | 595636 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2978038246 -assert nopostpr oc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 62.xbar_smoke_zero_delays.2978038246 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/62.xbar_smoke_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/62.xbar_stress_all.1527412711 |
| Short name | T2255 |
| Test name | |
| Test status | |
| Simulation time | 79687187 ps |
| CPU time | 6.93 seconds |
| Started | Aug 24 06:32:27 AM UTC 24 |
| Finished | Aug 24 06:32:34 AM UTC 24 |
| Peak memory | 597832 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1527412711 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 62.xbar_stress_all.1527412711 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/62.xbar_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/62.xbar_stress_all_with_error.2811449602 |
| Short name | T2266 |
| Test name | |
| Test status | |
| Simulation time | 2008960991 ps |
| CPU time | 59.38 seconds |
| Started | Aug 24 06:32:45 AM UTC 24 |
| Finished | Aug 24 06:33:46 AM UTC 24 |
| Peak memory | 597760 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2811449602 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 62.xbar_stress_all_with_error.2811449602 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/62.xbar_stress_all_with_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/62.xbar_stress_all_with_reset_error.152751221 |
| Short name | T847 |
| Test name | |
| Test status | |
| Simulation time | 922480122 ps |
| CPU time | 133.8 seconds |
| Started | Aug 24 06:32:49 AM UTC 24 |
| Finished | Aug 24 06:35:05 AM UTC 24 |
| Peak memory | 597692 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=152751221 -assert nopostproc +UVM_TESTNAME =xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 62.xbar_stress_all_with_reset_error.152751221 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/62.xbar_stress_all_with_reset_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/62.xbar_unmapped_addr.670336928 |
| Short name | T2259 |
| Test name | |
| Test status | |
| Simulation time | 1043261492 ps |
| CPU time | 32.82 seconds |
| Started | Aug 24 06:32:18 AM UTC 24 |
| Finished | Aug 24 06:32:52 AM UTC 24 |
| Peak memory | 597932 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=670336928 -assert nopostproc +UVM_TESTNAME =xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 62.xbar_unmapped_addr.670336928 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/62.xbar_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/63.xbar_access_same_device.1724400164 |
| Short name | T2270 |
| Test name | |
| Test status | |
| Simulation time | 1080449899 ps |
| CPU time | 31.48 seconds |
| Started | Aug 24 06:33:33 AM UTC 24 |
| Finished | Aug 24 06:34:06 AM UTC 24 |
| Peak memory | 597704 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1724400164 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 63.xbar_access_same_device.1724400164 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/63.xbar_access_same_device/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/63.xbar_access_same_device_slow_rsp.3151534131 |
| Short name | T2489 |
| Test name | |
| Test status | |
| Simulation time | 111119792724 ps |
| CPU time | 1263.34 seconds |
| Started | Aug 24 06:33:55 AM UTC 24 |
| Finished | Aug 24 06:55:11 AM UTC 24 |
| Peak memory | 599088 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3151534131 -assert nopostproc +UVM_T ESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 63.xbar_access_same_device_slow_rsp.3151534131 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/63.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/63.xbar_error_and_unmapped_addr.952281125 |
| Short name | T2276 |
| Test name | |
| Test status | |
| Simulation time | 140217438 ps |
| CPU time | 6.22 seconds |
| Started | Aug 24 06:34:18 AM UTC 24 |
| Finished | Aug 24 06:34:26 AM UTC 24 |
| Peak memory | 595648 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=952281125 -assert nopostproc +UVM_TESTNAME =xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 63.xbar_error_and_unmapped_addr.952281125 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/63.xbar_error_and_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/63.xbar_error_random.859559520 |
| Short name | T2273 |
| Test name | |
| Test status | |
| Simulation time | 49681178 ps |
| CPU time | 5.84 seconds |
| Started | Aug 24 06:34:03 AM UTC 24 |
| Finished | Aug 24 06:34:10 AM UTC 24 |
| Peak memory | 595652 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=859559520 -assert nopostproc +UVM_TESTNAME =xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 63.xbar_error_random.859559520 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/63.xbar_error_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/63.xbar_random.2772733957 |
| Short name | T2264 |
| Test name | |
| Test status | |
| Simulation time | 317474144 ps |
| CPU time | 11 seconds |
| Started | Aug 24 06:33:07 AM UTC 24 |
| Finished | Aug 24 06:33:19 AM UTC 24 |
| Peak memory | 597892 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2772733957 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 63.xbar_random.2772733957 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/63.xbar_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/63.xbar_random_large_delays.129909678 |
| Short name | T2421 |
| Test name | |
| Test status | |
| Simulation time | 99678149176 ps |
| CPU time | 838.51 seconds |
| Started | Aug 24 06:33:19 AM UTC 24 |
| Finished | Aug 24 06:47:26 AM UTC 24 |
| Peak memory | 598724 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max _device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=129909678 -assert nopostproc +UV M_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 63.xbar_random_large_delays.129909678 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/63.xbar_random_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/63.xbar_random_slow_rsp.4103434081 |
| Short name | T2325 |
| Test name | |
| Test status | |
| Simulation time | 28803312315 ps |
| CPU time | 327.1 seconds |
| Started | Aug 24 06:33:23 AM UTC 24 |
| Finished | Aug 24 06:38:54 AM UTC 24 |
| Peak memory | 598072 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4103434081 -assert nopostproc +UVM_T ESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 63.xbar_random_slow_rsp.4103434081 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/63.xbar_random_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/63.xbar_random_zero_delays.1940719651 |
| Short name | T2267 |
| Test name | |
| Test status | |
| Simulation time | 592813760 ps |
| CPU time | 35.74 seconds |
| Started | Aug 24 06:33:12 AM UTC 24 |
| Finished | Aug 24 06:33:49 AM UTC 24 |
| Peak memory | 597844 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1940719651 -assert nopostpr oc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 63.xbar_random_zero_delays.1940719651 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/63.xbar_random_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/63.xbar_same_source.4021340833 |
| Short name | T2272 |
| Test name | |
| Test status | |
| Simulation time | 125818475 ps |
| CPU time | 9.02 seconds |
| Started | Aug 24 06:33:59 AM UTC 24 |
| Finished | Aug 24 06:34:09 AM UTC 24 |
| Peak memory | 597692 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4021340833 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 63.xbar_same_source.4021340833 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/63.xbar_same_source/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/63.xbar_smoke.2838949424 |
| Short name | T2261 |
| Test name | |
| Test status | |
| Simulation time | 57811013 ps |
| CPU time | 5.25 seconds |
| Started | Aug 24 06:32:52 AM UTC 24 |
| Finished | Aug 24 06:32:58 AM UTC 24 |
| Peak memory | 595628 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2838949424 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 8_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 63.xbar_smoke.2838949424 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/63.xbar_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/63.xbar_smoke_large_delays.338956255 |
| Short name | T2269 |
| Test name | |
| Test status | |
| Simulation time | 8189662364 ps |
| CPU time | 63.2 seconds |
| Started | Aug 24 06:33:00 AM UTC 24 |
| Finished | Aug 24 06:34:04 AM UTC 24 |
| Peak memory | 595972 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max _device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=338956255 -assert nopostproc +UV M_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 63.xbar_smoke_large_delays.338956255 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/63.xbar_smoke_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/63.xbar_smoke_slow_rsp.3584156375 |
| Short name | T2274 |
| Test name | |
| Test status | |
| Simulation time | 6379219746 ps |
| CPU time | 75.67 seconds |
| Started | Aug 24 06:33:07 AM UTC 24 |
| Finished | Aug 24 06:34:24 AM UTC 24 |
| Peak memory | 595768 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3584156375 -assert nopostproc +UVM_T ESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 63.xbar_smoke_slow_rsp.3584156375 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/63.xbar_smoke_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/63.xbar_smoke_zero_delays.4236967364 |
| Short name | T2262 |
| Test name | |
| Test status | |
| Simulation time | 55928432 ps |
| CPU time | 5.23 seconds |
| Started | Aug 24 06:32:59 AM UTC 24 |
| Finished | Aug 24 06:33:05 AM UTC 24 |
| Peak memory | 595632 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4236967364 -assert nopostpr oc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 63.xbar_smoke_zero_delays.4236967364 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/63.xbar_smoke_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/63.xbar_stress_all.1094845131 |
| Short name | T2303 |
| Test name | |
| Test status | |
| Simulation time | 6055778009 ps |
| CPU time | 142.25 seconds |
| Started | Aug 24 06:34:21 AM UTC 24 |
| Finished | Aug 24 06:36:45 AM UTC 24 |
| Peak memory | 597828 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1094845131 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 63.xbar_stress_all.1094845131 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/63.xbar_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/63.xbar_stress_all_with_error.1147134473 |
| Short name | T2343 |
| Test name | |
| Test status | |
| Simulation time | 14835598831 ps |
| CPU time | 364.78 seconds |
| Started | Aug 24 06:34:24 AM UTC 24 |
| Finished | Aug 24 06:40:33 AM UTC 24 |
| Peak memory | 597824 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1147134473 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 63.xbar_stress_all_with_error.1147134473 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/63.xbar_stress_all_with_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/63.xbar_stress_all_with_rand_reset.403128012 |
| Short name | T2279 |
| Test name | |
| Test status | |
| Simulation time | 50928733 ps |
| CPU time | 19.41 seconds |
| Started | Aug 24 06:34:22 AM UTC 24 |
| Finished | Aug 24 06:34:42 AM UTC 24 |
| Peak memory | 597752 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=403128012 -assert nopostproc +UVM_TESTNAME =xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 63.xbar_stress_all_with_rand_reset.403128012 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/63.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/63.xbar_stress_all_with_reset_error.2327096198 |
| Short name | T2312 |
| Test name | |
| Test status | |
| Simulation time | 1225081590 ps |
| CPU time | 172.65 seconds |
| Started | Aug 24 06:34:25 AM UTC 24 |
| Finished | Aug 24 06:37:20 AM UTC 24 |
| Peak memory | 597924 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2327096198 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 63.xbar_stress_all_with_reset_error.2327096198 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/63.xbar_stress_all_with_reset_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/63.xbar_unmapped_addr.2162153409 |
| Short name | T2277 |
| Test name | |
| Test status | |
| Simulation time | 346810003 ps |
| CPU time | 12.53 seconds |
| Started | Aug 24 06:34:15 AM UTC 24 |
| Finished | Aug 24 06:34:29 AM UTC 24 |
| Peak memory | 597688 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2162153409 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 63.xbar_unmapped_addr.2162153409 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/63.xbar_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/64.xbar_access_same_device.3620138209 |
| Short name | T2297 |
| Test name | |
| Test status | |
| Simulation time | 1027409727 ps |
| CPU time | 55.24 seconds |
| Started | Aug 24 06:35:19 AM UTC 24 |
| Finished | Aug 24 06:36:16 AM UTC 24 |
| Peak memory | 597768 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3620138209 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 64.xbar_access_same_device.3620138209 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/64.xbar_access_same_device/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/64.xbar_access_same_device_slow_rsp.1155368445 |
| Short name | T2507 |
| Test name | |
| Test status | |
| Simulation time | 108812179565 ps |
| CPU time | 1258.71 seconds |
| Started | Aug 24 06:35:22 AM UTC 24 |
| Finished | Aug 24 06:56:33 AM UTC 24 |
| Peak memory | 599040 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1155368445 -assert nopostproc +UVM_T ESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 64.xbar_access_same_device_slow_rsp.1155368445 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/64.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/64.xbar_error_and_unmapped_addr.396360211 |
| Short name | T2289 |
| Test name | |
| Test status | |
| Simulation time | 37848351 ps |
| CPU time | 4.32 seconds |
| Started | Aug 24 06:35:38 AM UTC 24 |
| Finished | Aug 24 06:35:44 AM UTC 24 |
| Peak memory | 595784 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=396360211 -assert nopostproc +UVM_TESTNAME =xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 64.xbar_error_and_unmapped_addr.396360211 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/64.xbar_error_and_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/64.xbar_error_random.3235223865 |
| Short name | T2292 |
| Test name | |
| Test status | |
| Simulation time | 420191256 ps |
| CPU time | 23.73 seconds |
| Started | Aug 24 06:35:31 AM UTC 24 |
| Finished | Aug 24 06:35:56 AM UTC 24 |
| Peak memory | 597688 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3235223865 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 64.xbar_error_random.3235223865 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/64.xbar_error_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/64.xbar_random.807888840 |
| Short name | T2291 |
| Test name | |
| Test status | |
| Simulation time | 2516076869 ps |
| CPU time | 65.71 seconds |
| Started | Aug 24 06:34:45 AM UTC 24 |
| Finished | Aug 24 06:35:52 AM UTC 24 |
| Peak memory | 597760 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=807888840 -assert nopostproc +UVM_TESTNAME =xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 8_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 64.xbar_random.807888840 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/64.xbar_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/64.xbar_random_large_delays.2010671957 |
| Short name | T2437 |
| Test name | |
| Test status | |
| Simulation time | 102633610521 ps |
| CPU time | 812.6 seconds |
| Started | Aug 24 06:34:58 AM UTC 24 |
| Finished | Aug 24 06:48:39 AM UTC 24 |
| Peak memory | 597960 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max _device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2010671957 -assert nopostproc +U VM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 64.xbar_random_large_delays.2010671957 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/64.xbar_random_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/64.xbar_random_slow_rsp.3025211878 |
| Short name | T2288 |
| Test name | |
| Test status | |
| Simulation time | 3451876009 ps |
| CPU time | 41.63 seconds |
| Started | Aug 24 06:34:59 AM UTC 24 |
| Finished | Aug 24 06:35:42 AM UTC 24 |
| Peak memory | 595956 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3025211878 -assert nopostproc +UVM_T ESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 64.xbar_random_slow_rsp.3025211878 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/64.xbar_random_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/64.xbar_random_zero_delays.588517061 |
| Short name | T2283 |
| Test name | |
| Test status | |
| Simulation time | 319056114 ps |
| CPU time | 20.11 seconds |
| Started | Aug 24 06:34:56 AM UTC 24 |
| Finished | Aug 24 06:35:17 AM UTC 24 |
| Peak memory | 597700 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=588517061 -assert nopostpro c +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 64.xbar_random_zero_delays.588517061 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/64.xbar_random_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/64.xbar_same_source.3592065126 |
| Short name | T2290 |
| Test name | |
| Test status | |
| Simulation time | 348913873 ps |
| CPU time | 19.31 seconds |
| Started | Aug 24 06:35:29 AM UTC 24 |
| Finished | Aug 24 06:35:50 AM UTC 24 |
| Peak memory | 597692 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3592065126 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 64.xbar_same_source.3592065126 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/64.xbar_same_source/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/64.xbar_smoke.3412403923 |
| Short name | T2280 |
| Test name | |
| Test status | |
| Simulation time | 54405237 ps |
| CPU time | 5.51 seconds |
| Started | Aug 24 06:34:38 AM UTC 24 |
| Finished | Aug 24 06:34:44 AM UTC 24 |
| Peak memory | 595848 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3412403923 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 8_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 64.xbar_smoke.3412403923 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/64.xbar_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/64.xbar_smoke_large_delays.1209017135 |
| Short name | T2287 |
| Test name | |
| Test status | |
| Simulation time | 7132837563 ps |
| CPU time | 57.94 seconds |
| Started | Aug 24 06:34:40 AM UTC 24 |
| Finished | Aug 24 06:35:39 AM UTC 24 |
| Peak memory | 595896 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max _device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1209017135 -assert nopostproc +U VM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 64.xbar_smoke_large_delays.1209017135 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/64.xbar_smoke_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/64.xbar_smoke_slow_rsp.3588390486 |
| Short name | T2285 |
| Test name | |
| Test status | |
| Simulation time | 3371842870 ps |
| CPU time | 40.59 seconds |
| Started | Aug 24 06:34:43 AM UTC 24 |
| Finished | Aug 24 06:35:25 AM UTC 24 |
| Peak memory | 595952 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3588390486 -assert nopostproc +UVM_T ESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 64.xbar_smoke_slow_rsp.3588390486 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/64.xbar_smoke_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/64.xbar_smoke_zero_delays.3136129557 |
| Short name | T2281 |
| Test name | |
| Test status | |
| Simulation time | 54175121 ps |
| CPU time | 5.13 seconds |
| Started | Aug 24 06:34:39 AM UTC 24 |
| Finished | Aug 24 06:34:45 AM UTC 24 |
| Peak memory | 595632 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3136129557 -assert nopostpr oc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 64.xbar_smoke_zero_delays.3136129557 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/64.xbar_smoke_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/64.xbar_stress_all.2242146153 |
| Short name | T2311 |
| Test name | |
| Test status | |
| Simulation time | 3421735098 ps |
| CPU time | 94.22 seconds |
| Started | Aug 24 06:35:42 AM UTC 24 |
| Finished | Aug 24 06:37:19 AM UTC 24 |
| Peak memory | 597896 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2242146153 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 64.xbar_stress_all.2242146153 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/64.xbar_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/64.xbar_stress_all_with_error.10445240 |
| Short name | T2350 |
| Test name | |
| Test status | |
| Simulation time | 12162661311 ps |
| CPU time | 296.95 seconds |
| Started | Aug 24 06:35:56 AM UTC 24 |
| Finished | Aug 24 06:40:57 AM UTC 24 |
| Peak memory | 597968 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=10445240 -assert nopostproc +UVM_TESTNAME= xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 64.xbar_stress_all_with_error.10445240 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/64.xbar_stress_all_with_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/64.xbar_stress_all_with_rand_reset.1322907644 |
| Short name | T2301 |
| Test name | |
| Test status | |
| Simulation time | 26426275 ps |
| CPU time | 40.64 seconds |
| Started | Aug 24 06:35:54 AM UTC 24 |
| Finished | Aug 24 06:36:36 AM UTC 24 |
| Peak memory | 597688 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1322907644 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 64.xbar_stress_all_with_rand_reset.1322907644 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/64.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/64.xbar_stress_all_with_reset_error.3908497919 |
| Short name | T2411 |
| Test name | |
| Test status | |
| Simulation time | 9929945805 ps |
| CPU time | 620.18 seconds |
| Started | Aug 24 06:35:58 AM UTC 24 |
| Finished | Aug 24 06:46:25 AM UTC 24 |
| Peak memory | 616332 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3908497919 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 64.xbar_stress_all_with_reset_error.3908497919 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/64.xbar_stress_all_with_reset_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/64.xbar_unmapped_addr.3407865861 |
| Short name | T2294 |
| Test name | |
| Test status | |
| Simulation time | 1019050504 ps |
| CPU time | 29.13 seconds |
| Started | Aug 24 06:35:36 AM UTC 24 |
| Finished | Aug 24 06:36:07 AM UTC 24 |
| Peak memory | 597692 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3407865861 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 64.xbar_unmapped_addr.3407865861 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/64.xbar_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/65.xbar_access_same_device.1573055596 |
| Short name | T2310 |
| Test name | |
| Test status | |
| Simulation time | 1375785973 ps |
| CPU time | 43.13 seconds |
| Started | Aug 24 06:36:32 AM UTC 24 |
| Finished | Aug 24 06:37:17 AM UTC 24 |
| Peak memory | 598088 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1573055596 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 65.xbar_access_same_device.1573055596 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/65.xbar_access_same_device/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/65.xbar_access_same_device_slow_rsp.1199833684 |
| Short name | T2494 |
| Test name | |
| Test status | |
| Simulation time | 98567236742 ps |
| CPU time | 1139.51 seconds |
| Started | Aug 24 06:36:44 AM UTC 24 |
| Finished | Aug 24 06:55:55 AM UTC 24 |
| Peak memory | 598668 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1199833684 -assert nopostproc +UVM_T ESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 65.xbar_access_same_device_slow_rsp.1199833684 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/65.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/65.xbar_error_and_unmapped_addr.889504388 |
| Short name | T2307 |
| Test name | |
| Test status | |
| Simulation time | 184544670 ps |
| CPU time | 7.68 seconds |
| Started | Aug 24 06:36:59 AM UTC 24 |
| Finished | Aug 24 06:37:08 AM UTC 24 |
| Peak memory | 597756 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=889504388 -assert nopostproc +UVM_TESTNAME =xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 65.xbar_error_and_unmapped_addr.889504388 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/65.xbar_error_and_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/65.xbar_error_random.4149720441 |
| Short name | T2304 |
| Test name | |
| Test status | |
| Simulation time | 71074489 ps |
| CPU time | 6.29 seconds |
| Started | Aug 24 06:36:50 AM UTC 24 |
| Finished | Aug 24 06:36:57 AM UTC 24 |
| Peak memory | 597924 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4149720441 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 65.xbar_error_random.4149720441 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/65.xbar_error_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/65.xbar_random.681698351 |
| Short name | T2299 |
| Test name | |
| Test status | |
| Simulation time | 197850152 ps |
| CPU time | 7.72 seconds |
| Started | Aug 24 06:36:21 AM UTC 24 |
| Finished | Aug 24 06:36:30 AM UTC 24 |
| Peak memory | 595644 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=681698351 -assert nopostproc +UVM_TESTNAME =xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 8_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 65.xbar_random.681698351 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/65.xbar_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/65.xbar_random_large_delays.2358162409 |
| Short name | T2331 |
| Test name | |
| Test status | |
| Simulation time | 21143114511 ps |
| CPU time | 172.08 seconds |
| Started | Aug 24 06:36:27 AM UTC 24 |
| Finished | Aug 24 06:39:22 AM UTC 24 |
| Peak memory | 598092 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max _device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2358162409 -assert nopostproc +U VM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 65.xbar_random_large_delays.2358162409 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/65.xbar_random_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/65.xbar_random_slow_rsp.1262084153 |
| Short name | T2356 |
| Test name | |
| Test status | |
| Simulation time | 24567280556 ps |
| CPU time | 276.41 seconds |
| Started | Aug 24 06:36:30 AM UTC 24 |
| Finished | Aug 24 06:41:10 AM UTC 24 |
| Peak memory | 598072 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1262084153 -assert nopostproc +UVM_T ESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 65.xbar_random_slow_rsp.1262084153 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/65.xbar_random_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/65.xbar_random_zero_delays.1989031602 |
| Short name | T2305 |
| Test name | |
| Test status | |
| Simulation time | 586408945 ps |
| CPU time | 34.81 seconds |
| Started | Aug 24 06:36:26 AM UTC 24 |
| Finished | Aug 24 06:37:02 AM UTC 24 |
| Peak memory | 597840 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1989031602 -assert nopostpr oc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 65.xbar_random_zero_delays.1989031602 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/65.xbar_random_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/65.xbar_same_source.1288846221 |
| Short name | T2309 |
| Test name | |
| Test status | |
| Simulation time | 540594269 ps |
| CPU time | 27.73 seconds |
| Started | Aug 24 06:36:45 AM UTC 24 |
| Finished | Aug 24 06:37:14 AM UTC 24 |
| Peak memory | 597752 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1288846221 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 65.xbar_same_source.1288846221 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/65.xbar_same_source/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/65.xbar_smoke.3164762787 |
| Short name | T2295 |
| Test name | |
| Test status | |
| Simulation time | 194638392 ps |
| CPU time | 6.85 seconds |
| Started | Aug 24 06:36:04 AM UTC 24 |
| Finished | Aug 24 06:36:12 AM UTC 24 |
| Peak memory | 595700 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3164762787 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 8_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 65.xbar_smoke.3164762787 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/65.xbar_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/65.xbar_smoke_large_delays.880112934 |
| Short name | T2313 |
| Test name | |
| Test status | |
| Simulation time | 9547337571 ps |
| CPU time | 77.66 seconds |
| Started | Aug 24 06:36:11 AM UTC 24 |
| Finished | Aug 24 06:37:30 AM UTC 24 |
| Peak memory | 595768 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max _device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=880112934 -assert nopostproc +UV M_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 65.xbar_smoke_large_delays.880112934 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/65.xbar_smoke_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/65.xbar_smoke_slow_rsp.2151275839 |
| Short name | T2306 |
| Test name | |
| Test status | |
| Simulation time | 4187287800 ps |
| CPU time | 53 seconds |
| Started | Aug 24 06:36:12 AM UTC 24 |
| Finished | Aug 24 06:37:06 AM UTC 24 |
| Peak memory | 595772 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2151275839 -assert nopostproc +UVM_T ESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 65.xbar_smoke_slow_rsp.2151275839 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/65.xbar_smoke_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/65.xbar_smoke_zero_delays.3019563882 |
| Short name | T2296 |
| Test name | |
| Test status | |
| Simulation time | 46476893 ps |
| CPU time | 4.79 seconds |
| Started | Aug 24 06:36:07 AM UTC 24 |
| Finished | Aug 24 06:36:13 AM UTC 24 |
| Peak memory | 595696 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3019563882 -assert nopostpr oc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 65.xbar_smoke_zero_delays.3019563882 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/65.xbar_smoke_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/65.xbar_stress_all.50391191 |
| Short name | T2336 |
| Test name | |
| Test status | |
| Simulation time | 6670573727 ps |
| CPU time | 164.06 seconds |
| Started | Aug 24 06:37:11 AM UTC 24 |
| Finished | Aug 24 06:39:58 AM UTC 24 |
| Peak memory | 598044 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=50391191 -assert nopostproc +UVM_TESTNAME= xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 65.xbar_stress_all.50391191 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/65.xbar_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/65.xbar_stress_all_with_error.4262043509 |
| Short name | T2321 |
| Test name | |
| Test status | |
| Simulation time | 3362437298 ps |
| CPU time | 80.5 seconds |
| Started | Aug 24 06:37:20 AM UTC 24 |
| Finished | Aug 24 06:38:43 AM UTC 24 |
| Peak memory | 597756 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4262043509 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 65.xbar_stress_all_with_error.4262043509 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/65.xbar_stress_all_with_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/65.xbar_stress_all_with_rand_reset.3028467786 |
| Short name | T2335 |
| Test name | |
| Test status | |
| Simulation time | 363239946 ps |
| CPU time | 155.95 seconds |
| Started | Aug 24 06:37:16 AM UTC 24 |
| Finished | Aug 24 06:39:55 AM UTC 24 |
| Peak memory | 597688 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3028467786 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 65.xbar_stress_all_with_rand_reset.3028467786 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/65.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/65.xbar_stress_all_with_reset_error.2117883697 |
| Short name | T2334 |
| Test name | |
| Test status | |
| Simulation time | 1104727532 ps |
| CPU time | 133.03 seconds |
| Started | Aug 24 06:37:22 AM UTC 24 |
| Finished | Aug 24 06:39:38 AM UTC 24 |
| Peak memory | 597988 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2117883697 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 65.xbar_stress_all_with_reset_error.2117883697 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/65.xbar_stress_all_with_reset_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/65.xbar_unmapped_addr.1307867105 |
| Short name | T2308 |
| Test name | |
| Test status | |
| Simulation time | 520361013 ps |
| CPU time | 17.25 seconds |
| Started | Aug 24 06:36:52 AM UTC 24 |
| Finished | Aug 24 06:37:11 AM UTC 24 |
| Peak memory | 597948 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1307867105 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 65.xbar_unmapped_addr.1307867105 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/65.xbar_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/66.xbar_access_same_device.2604529170 |
| Short name | T2328 |
| Test name | |
| Test status | |
| Simulation time | 1714216979 ps |
| CPU time | 54.84 seconds |
| Started | Aug 24 06:38:22 AM UTC 24 |
| Finished | Aug 24 06:39:18 AM UTC 24 |
| Peak memory | 597928 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2604529170 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 66.xbar_access_same_device.2604529170 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/66.xbar_access_same_device/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/66.xbar_access_same_device_slow_rsp.2883666698 |
| Short name | T2632 |
| Test name | |
| Test status | |
| Simulation time | 149523182576 ps |
| CPU time | 1772.47 seconds |
| Started | Aug 24 06:38:28 AM UTC 24 |
| Finished | Aug 24 07:08:17 AM UTC 24 |
| Peak memory | 598788 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2883666698 -assert nopostproc +UVM_T ESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 66.xbar_access_same_device_slow_rsp.2883666698 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/66.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/66.xbar_error_and_unmapped_addr.2043375705 |
| Short name | T2327 |
| Test name | |
| Test status | |
| Simulation time | 136545478 ps |
| CPU time | 12.29 seconds |
| Started | Aug 24 06:38:56 AM UTC 24 |
| Finished | Aug 24 06:39:10 AM UTC 24 |
| Peak memory | 597936 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2043375705 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 66.xbar_error_and_unmapped_addr.2043375705 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/66.xbar_error_and_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/66.xbar_error_random.2162895075 |
| Short name | T2323 |
| Test name | |
| Test status | |
| Simulation time | 90099412 ps |
| CPU time | 7.44 seconds |
| Started | Aug 24 06:38:45 AM UTC 24 |
| Finished | Aug 24 06:38:54 AM UTC 24 |
| Peak memory | 597688 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2162895075 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 66.xbar_error_random.2162895075 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/66.xbar_error_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/66.xbar_random.2465753744 |
| Short name | T2319 |
| Test name | |
| Test status | |
| Simulation time | 2088173853 ps |
| CPU time | 55.81 seconds |
| Started | Aug 24 06:37:34 AM UTC 24 |
| Finished | Aug 24 06:38:31 AM UTC 24 |
| Peak memory | 597828 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2465753744 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 66.xbar_random.2465753744 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/66.xbar_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/66.xbar_random_large_delays.868546908 |
| Short name | T2322 |
| Test name | |
| Test status | |
| Simulation time | 7049313360 ps |
| CPU time | 56.95 seconds |
| Started | Aug 24 06:37:46 AM UTC 24 |
| Finished | Aug 24 06:38:44 AM UTC 24 |
| Peak memory | 595908 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max _device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=868546908 -assert nopostproc +UV M_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 66.xbar_random_large_delays.868546908 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/66.xbar_random_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/66.xbar_random_slow_rsp.3055003973 |
| Short name | T2442 |
| Test name | |
| Test status | |
| Simulation time | 58831820007 ps |
| CPU time | 661.77 seconds |
| Started | Aug 24 06:37:49 AM UTC 24 |
| Finished | Aug 24 06:48:58 AM UTC 24 |
| Peak memory | 597820 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3055003973 -assert nopostproc +UVM_T ESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 66.xbar_random_slow_rsp.3055003973 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/66.xbar_random_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/66.xbar_random_zero_delays.68683735 |
| Short name | T2316 |
| Test name | |
| Test status | |
| Simulation time | 364175430 ps |
| CPU time | 23.06 seconds |
| Started | Aug 24 06:37:44 AM UTC 24 |
| Finished | Aug 24 06:38:08 AM UTC 24 |
| Peak memory | 597696 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=68683735 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 66.xbar_random_zero_delays.68683735 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/66.xbar_random_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/66.xbar_same_source.2533931678 |
| Short name | T2324 |
| Test name | |
| Test status | |
| Simulation time | 386015078 ps |
| CPU time | 10.57 seconds |
| Started | Aug 24 06:38:42 AM UTC 24 |
| Finished | Aug 24 06:38:54 AM UTC 24 |
| Peak memory | 597940 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2533931678 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 66.xbar_same_source.2533931678 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/66.xbar_same_source/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/66.xbar_smoke.3182132355 |
| Short name | T2314 |
| Test name | |
| Test status | |
| Simulation time | 141769260 ps |
| CPU time | 6.02 seconds |
| Started | Aug 24 06:37:25 AM UTC 24 |
| Finished | Aug 24 06:37:32 AM UTC 24 |
| Peak memory | 595808 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3182132355 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 8_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 66.xbar_smoke.3182132355 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/66.xbar_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/66.xbar_smoke_large_delays.2857946239 |
| Short name | T2318 |
| Test name | |
| Test status | |
| Simulation time | 6805171988 ps |
| CPU time | 55.92 seconds |
| Started | Aug 24 06:37:31 AM UTC 24 |
| Finished | Aug 24 06:38:28 AM UTC 24 |
| Peak memory | 596020 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max _device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2857946239 -assert nopostproc +U VM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 66.xbar_smoke_large_delays.2857946239 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/66.xbar_smoke_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/66.xbar_smoke_slow_rsp.78169756 |
| Short name | T2320 |
| Test name | |
| Test status | |
| Simulation time | 4912641666 ps |
| CPU time | 57.13 seconds |
| Started | Aug 24 06:37:33 AM UTC 24 |
| Finished | Aug 24 06:38:31 AM UTC 24 |
| Peak memory | 595764 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=78169756 -assert nopostproc +UVM_TES TNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 66.xbar_smoke_slow_rsp.78169756 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/66.xbar_smoke_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/66.xbar_smoke_zero_delays.3661304508 |
| Short name | T2315 |
| Test name | |
| Test status | |
| Simulation time | 40054571 ps |
| CPU time | 4.94 seconds |
| Started | Aug 24 06:37:29 AM UTC 24 |
| Finished | Aug 24 06:37:35 AM UTC 24 |
| Peak memory | 595860 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3661304508 -assert nopostpr oc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 66.xbar_smoke_zero_delays.3661304508 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/66.xbar_smoke_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/66.xbar_stress_all.2795160601 |
| Short name | T2345 |
| Test name | |
| Test status | |
| Simulation time | 3710718961 ps |
| CPU time | 98.46 seconds |
| Started | Aug 24 06:38:58 AM UTC 24 |
| Finished | Aug 24 06:40:39 AM UTC 24 |
| Peak memory | 597760 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2795160601 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 66.xbar_stress_all.2795160601 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/66.xbar_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/66.xbar_stress_all_with_error.1792709496 |
| Short name | T2330 |
| Test name | |
| Test status | |
| Simulation time | 135303544 ps |
| CPU time | 9.66 seconds |
| Started | Aug 24 06:39:09 AM UTC 24 |
| Finished | Aug 24 06:39:20 AM UTC 24 |
| Peak memory | 597908 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1792709496 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 66.xbar_stress_all_with_error.1792709496 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/66.xbar_stress_all_with_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/66.xbar_stress_all_with_rand_reset.3656517215 |
| Short name | T2376 |
| Test name | |
| Test status | |
| Simulation time | 1102854351 ps |
| CPU time | 232.2 seconds |
| Started | Aug 24 06:39:08 AM UTC 24 |
| Finished | Aug 24 06:43:04 AM UTC 24 |
| Peak memory | 597916 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3656517215 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 66.xbar_stress_all_with_rand_reset.3656517215 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/66.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/66.xbar_stress_all_with_reset_error.3927547072 |
| Short name | T2381 |
| Test name | |
| Test status | |
| Simulation time | 2438141704 ps |
| CPU time | 253.8 seconds |
| Started | Aug 24 06:39:08 AM UTC 24 |
| Finished | Aug 24 06:43:26 AM UTC 24 |
| Peak memory | 598052 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3927547072 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 66.xbar_stress_all_with_reset_error.3927547072 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/66.xbar_stress_all_with_reset_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/66.xbar_unmapped_addr.1113573006 |
| Short name | T2326 |
| Test name | |
| Test status | |
| Simulation time | 520126422 ps |
| CPU time | 17.8 seconds |
| Started | Aug 24 06:38:45 AM UTC 24 |
| Finished | Aug 24 06:39:04 AM UTC 24 |
| Peak memory | 597948 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1113573006 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 66.xbar_unmapped_addr.1113573006 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/66.xbar_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/67.xbar_access_same_device.2929877315 |
| Short name | T2338 |
| Test name | |
| Test status | |
| Simulation time | 464731540 ps |
| CPU time | 14.77 seconds |
| Started | Aug 24 06:39:52 AM UTC 24 |
| Finished | Aug 24 06:40:08 AM UTC 24 |
| Peak memory | 597772 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2929877315 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 67.xbar_access_same_device.2929877315 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/67.xbar_access_same_device/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/67.xbar_access_same_device_slow_rsp.3546418262 |
| Short name | T2402 |
| Test name | |
| Test status | |
| Simulation time | 26288505734 ps |
| CPU time | 315.75 seconds |
| Started | Aug 24 06:40:09 AM UTC 24 |
| Finished | Aug 24 06:45:29 AM UTC 24 |
| Peak memory | 598132 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3546418262 -assert nopostproc +UVM_T ESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 67.xbar_access_same_device_slow_rsp.3546418262 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/67.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/67.xbar_error_and_unmapped_addr.3487168747 |
| Short name | T2348 |
| Test name | |
| Test status | |
| Simulation time | 205710876 ps |
| CPU time | 16.58 seconds |
| Started | Aug 24 06:40:25 AM UTC 24 |
| Finished | Aug 24 06:40:44 AM UTC 24 |
| Peak memory | 598008 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3487168747 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 67.xbar_error_and_unmapped_addr.3487168747 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/67.xbar_error_and_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/67.xbar_error_random.4078842180 |
| Short name | T2341 |
| Test name | |
| Test status | |
| Simulation time | 276850360 ps |
| CPU time | 16.32 seconds |
| Started | Aug 24 06:40:15 AM UTC 24 |
| Finished | Aug 24 06:40:33 AM UTC 24 |
| Peak memory | 597692 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4078842180 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 67.xbar_error_random.4078842180 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/67.xbar_error_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/67.xbar_random.3706912847 |
| Short name | T2340 |
| Test name | |
| Test status | |
| Simulation time | 1690503951 ps |
| CPU time | 41.57 seconds |
| Started | Aug 24 06:39:34 AM UTC 24 |
| Finished | Aug 24 06:40:17 AM UTC 24 |
| Peak memory | 597752 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3706912847 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 67.xbar_random.3706912847 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/67.xbar_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/67.xbar_random_large_delays.2791950143 |
| Short name | T2502 |
| Test name | |
| Test status | |
| Simulation time | 120314612546 ps |
| CPU time | 990.26 seconds |
| Started | Aug 24 06:39:39 AM UTC 24 |
| Finished | Aug 24 06:56:18 AM UTC 24 |
| Peak memory | 598084 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max _device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2791950143 -assert nopostproc +U VM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 67.xbar_random_large_delays.2791950143 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/67.xbar_random_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/67.xbar_random_slow_rsp.306105835 |
| Short name | T2412 |
| Test name | |
| Test status | |
| Simulation time | 34014118895 ps |
| CPU time | 396.11 seconds |
| Started | Aug 24 06:39:45 AM UTC 24 |
| Finished | Aug 24 06:46:25 AM UTC 24 |
| Peak memory | 597828 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=306105835 -assert nopostproc +UVM_TE STNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 67.xbar_random_slow_rsp.306105835 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/67.xbar_random_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/67.xbar_random_zero_delays.4273602760 |
| Short name | T2337 |
| Test name | |
| Test status | |
| Simulation time | 357628301 ps |
| CPU time | 23.87 seconds |
| Started | Aug 24 06:39:36 AM UTC 24 |
| Finished | Aug 24 06:40:01 AM UTC 24 |
| Peak memory | 597768 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4273602760 -assert nopostpr oc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 67.xbar_random_zero_delays.4273602760 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/67.xbar_random_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/67.xbar_same_source.1223538180 |
| Short name | T2342 |
| Test name | |
| Test status | |
| Simulation time | 852377645 ps |
| CPU time | 19.32 seconds |
| Started | Aug 24 06:40:12 AM UTC 24 |
| Finished | Aug 24 06:40:33 AM UTC 24 |
| Peak memory | 597756 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1223538180 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 67.xbar_same_source.1223538180 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/67.xbar_same_source/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/67.xbar_smoke.1699162473 |
| Short name | T2332 |
| Test name | |
| Test status | |
| Simulation time | 53955813 ps |
| CPU time | 5.31 seconds |
| Started | Aug 24 06:39:19 AM UTC 24 |
| Finished | Aug 24 06:39:25 AM UTC 24 |
| Peak memory | 595628 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1699162473 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 8_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 67.xbar_smoke.1699162473 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/67.xbar_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/67.xbar_smoke_large_delays.3027001220 |
| Short name | T2354 |
| Test name | |
| Test status | |
| Simulation time | 9911425199 ps |
| CPU time | 84.32 seconds |
| Started | Aug 24 06:39:33 AM UTC 24 |
| Finished | Aug 24 06:40:59 AM UTC 24 |
| Peak memory | 596016 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max _device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3027001220 -assert nopostproc +U VM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 67.xbar_smoke_large_delays.3027001220 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/67.xbar_smoke_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/67.xbar_smoke_slow_rsp.2172996137 |
| Short name | T2339 |
| Test name | |
| Test status | |
| Simulation time | 2931603156 ps |
| CPU time | 35.95 seconds |
| Started | Aug 24 06:39:34 AM UTC 24 |
| Finished | Aug 24 06:40:11 AM UTC 24 |
| Peak memory | 595848 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2172996137 -assert nopostproc +UVM_T ESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 67.xbar_smoke_slow_rsp.2172996137 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/67.xbar_smoke_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/67.xbar_smoke_zero_delays.1314238785 |
| Short name | T2333 |
| Test name | |
| Test status | |
| Simulation time | 43321375 ps |
| CPU time | 4.77 seconds |
| Started | Aug 24 06:39:25 AM UTC 24 |
| Finished | Aug 24 06:39:30 AM UTC 24 |
| Peak memory | 595632 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1314238785 -assert nopostpr oc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 67.xbar_smoke_zero_delays.1314238785 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/67.xbar_smoke_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/67.xbar_stress_all.283064176 |
| Short name | T2351 |
| Test name | |
| Test status | |
| Simulation time | 438657721 ps |
| CPU time | 24.99 seconds |
| Started | Aug 24 06:40:30 AM UTC 24 |
| Finished | Aug 24 06:40:57 AM UTC 24 |
| Peak memory | 597704 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=283064176 -assert nopostproc +UVM_TESTNAME =xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 67.xbar_stress_all.283064176 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/67.xbar_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/67.xbar_stress_all_with_error.3955797982 |
| Short name | T2358 |
| Test name | |
| Test status | |
| Simulation time | 1153988607 ps |
| CPU time | 30.87 seconds |
| Started | Aug 24 06:40:46 AM UTC 24 |
| Finished | Aug 24 06:41:19 AM UTC 24 |
| Peak memory | 597696 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3955797982 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 67.xbar_stress_all_with_error.3955797982 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/67.xbar_stress_all_with_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/67.xbar_stress_all_with_rand_reset.2579633031 |
| Short name | T2364 |
| Test name | |
| Test status | |
| Simulation time | 322300894 ps |
| CPU time | 64.84 seconds |
| Started | Aug 24 06:40:46 AM UTC 24 |
| Finished | Aug 24 06:41:53 AM UTC 24 |
| Peak memory | 597924 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2579633031 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 67.xbar_stress_all_with_rand_reset.2579633031 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/67.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/67.xbar_unmapped_addr.2555077293 |
| Short name | T2347 |
| Test name | |
| Test status | |
| Simulation time | 189104496 ps |
| CPU time | 16.29 seconds |
| Started | Aug 24 06:40:22 AM UTC 24 |
| Finished | Aug 24 06:40:40 AM UTC 24 |
| Peak memory | 597692 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2555077293 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 67.xbar_unmapped_addr.2555077293 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/67.xbar_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/68.xbar_access_same_device.2734061167 |
| Short name | T2362 |
| Test name | |
| Test status | |
| Simulation time | 642824509 ps |
| CPU time | 35.47 seconds |
| Started | Aug 24 06:41:12 AM UTC 24 |
| Finished | Aug 24 06:41:49 AM UTC 24 |
| Peak memory | 597928 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2734061167 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 68.xbar_access_same_device.2734061167 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/68.xbar_access_same_device/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/68.xbar_access_same_device_slow_rsp.2907281819 |
| Short name | T2460 |
| Test name | |
| Test status | |
| Simulation time | 49837145413 ps |
| CPU time | 588.83 seconds |
| Started | Aug 24 06:41:13 AM UTC 24 |
| Finished | Aug 24 06:51:08 AM UTC 24 |
| Peak memory | 597820 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2907281819 -assert nopostproc +UVM_T ESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 68.xbar_access_same_device_slow_rsp.2907281819 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/68.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/68.xbar_error_and_unmapped_addr.697582006 |
| Short name | T2368 |
| Test name | |
| Test status | |
| Simulation time | 1362729591 ps |
| CPU time | 37.42 seconds |
| Started | Aug 24 06:41:26 AM UTC 24 |
| Finished | Aug 24 06:42:05 AM UTC 24 |
| Peak memory | 597692 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=697582006 -assert nopostproc +UVM_TESTNAME =xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 68.xbar_error_and_unmapped_addr.697582006 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/68.xbar_error_and_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/68.xbar_error_random.2569897641 |
| Short name | T2365 |
| Test name | |
| Test status | |
| Simulation time | 581779886 ps |
| CPU time | 31.96 seconds |
| Started | Aug 24 06:41:24 AM UTC 24 |
| Finished | Aug 24 06:41:57 AM UTC 24 |
| Peak memory | 597920 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2569897641 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 68.xbar_error_random.2569897641 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/68.xbar_error_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/68.xbar_random.3474548642 |
| Short name | T2367 |
| Test name | |
| Test status | |
| Simulation time | 2385940302 ps |
| CPU time | 61.72 seconds |
| Started | Aug 24 06:40:58 AM UTC 24 |
| Finished | Aug 24 06:42:01 AM UTC 24 |
| Peak memory | 597964 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3474548642 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 68.xbar_random.3474548642 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/68.xbar_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/68.xbar_random_large_delays.1931231420 |
| Short name | T2429 |
| Test name | |
| Test status | |
| Simulation time | 51193449869 ps |
| CPU time | 407.65 seconds |
| Started | Aug 24 06:41:11 AM UTC 24 |
| Finished | Aug 24 06:48:03 AM UTC 24 |
| Peak memory | 597960 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max _device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1931231420 -assert nopostproc +U VM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 68.xbar_random_large_delays.1931231420 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/68.xbar_random_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/68.xbar_random_slow_rsp.2293196408 |
| Short name | T2390 |
| Test name | |
| Test status | |
| Simulation time | 15488298966 ps |
| CPU time | 179.63 seconds |
| Started | Aug 24 06:41:12 AM UTC 24 |
| Finished | Aug 24 06:44:14 AM UTC 24 |
| Peak memory | 598048 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2293196408 -assert nopostproc +UVM_T ESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 68.xbar_random_slow_rsp.2293196408 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/68.xbar_random_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/68.xbar_random_zero_delays.2696729528 |
| Short name | T2359 |
| Test name | |
| Test status | |
| Simulation time | 157892935 ps |
| CPU time | 11.12 seconds |
| Started | Aug 24 06:41:09 AM UTC 24 |
| Finished | Aug 24 06:41:21 AM UTC 24 |
| Peak memory | 597836 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2696729528 -assert nopostpr oc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 68.xbar_random_zero_delays.2696729528 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/68.xbar_random_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/68.xbar_same_source.817667575 |
| Short name | T2361 |
| Test name | |
| Test status | |
| Simulation time | 991409154 ps |
| CPU time | 22.33 seconds |
| Started | Aug 24 06:41:13 AM UTC 24 |
| Finished | Aug 24 06:41:37 AM UTC 24 |
| Peak memory | 597696 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=817667575 -assert nopostproc +UVM_TESTNAME =xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 68.xbar_same_source.817667575 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/68.xbar_same_source/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/68.xbar_smoke.2961581276 |
| Short name | T2352 |
| Test name | |
| Test status | |
| Simulation time | 231407710 ps |
| CPU time | 7.28 seconds |
| Started | Aug 24 06:40:50 AM UTC 24 |
| Finished | Aug 24 06:40:58 AM UTC 24 |
| Peak memory | 595696 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2961581276 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 8_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 68.xbar_smoke.2961581276 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/68.xbar_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/68.xbar_smoke_large_delays.974611443 |
| Short name | T2370 |
| Test name | |
| Test status | |
| Simulation time | 8748590505 ps |
| CPU time | 74.79 seconds |
| Started | Aug 24 06:40:54 AM UTC 24 |
| Finished | Aug 24 06:42:10 AM UTC 24 |
| Peak memory | 595976 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max _device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=974611443 -assert nopostproc +UV M_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 68.xbar_smoke_large_delays.974611443 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/68.xbar_smoke_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/68.xbar_smoke_slow_rsp.783504891 |
| Short name | T2363 |
| Test name | |
| Test status | |
| Simulation time | 4769467731 ps |
| CPU time | 57.47 seconds |
| Started | Aug 24 06:40:54 AM UTC 24 |
| Finished | Aug 24 06:41:53 AM UTC 24 |
| Peak memory | 595988 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=783504891 -assert nopostproc +UVM_TE STNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 68.xbar_smoke_slow_rsp.783504891 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/68.xbar_smoke_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/68.xbar_smoke_zero_delays.2618559619 |
| Short name | T2353 |
| Test name | |
| Test status | |
| Simulation time | 43695739 ps |
| CPU time | 4.8 seconds |
| Started | Aug 24 06:40:53 AM UTC 24 |
| Finished | Aug 24 06:40:59 AM UTC 24 |
| Peak memory | 595860 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2618559619 -assert nopostpr oc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 68.xbar_smoke_zero_delays.2618559619 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/68.xbar_smoke_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/68.xbar_stress_all.1545403852 |
| Short name | T2375 |
| Test name | |
| Test status | |
| Simulation time | 1119450435 ps |
| CPU time | 73.94 seconds |
| Started | Aug 24 06:41:33 AM UTC 24 |
| Finished | Aug 24 06:42:49 AM UTC 24 |
| Peak memory | 597832 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1545403852 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 68.xbar_stress_all.1545403852 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/68.xbar_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/68.xbar_stress_all_with_error.376759741 |
| Short name | T2404 |
| Test name | |
| Test status | |
| Simulation time | 10031578420 ps |
| CPU time | 232.49 seconds |
| Started | Aug 24 06:41:46 AM UTC 24 |
| Finished | Aug 24 06:45:42 AM UTC 24 |
| Peak memory | 597888 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=376759741 -assert nopostproc +UVM_TESTNAME =xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 68.xbar_stress_all_with_error.376759741 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/68.xbar_stress_all_with_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/68.xbar_stress_all_with_rand_reset.1395160671 |
| Short name | T2456 |
| Test name | |
| Test status | |
| Simulation time | 5533888887 ps |
| CPU time | 535.73 seconds |
| Started | Aug 24 06:41:35 AM UTC 24 |
| Finished | Aug 24 06:50:37 AM UTC 24 |
| Peak memory | 598040 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1395160671 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 68.xbar_stress_all_with_rand_reset.1395160671 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/68.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/68.xbar_stress_all_with_reset_error.1574665615 |
| Short name | T2383 |
| Test name | |
| Test status | |
| Simulation time | 3713893108 ps |
| CPU time | 99.34 seconds |
| Started | Aug 24 06:41:52 AM UTC 24 |
| Finished | Aug 24 06:43:33 AM UTC 24 |
| Peak memory | 597756 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1574665615 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 68.xbar_stress_all_with_reset_error.1574665615 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/68.xbar_stress_all_with_reset_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/68.xbar_unmapped_addr.23592559 |
| Short name | T2360 |
| Test name | |
| Test status | |
| Simulation time | 54295189 ps |
| CPU time | 6.86 seconds |
| Started | Aug 24 06:41:24 AM UTC 24 |
| Finished | Aug 24 06:41:32 AM UTC 24 |
| Peak memory | 597936 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=23592559 -assert nopostproc +UVM_TESTNAME= xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 68.xbar_unmapped_addr.23592559 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/68.xbar_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/69.xbar_access_same_device.2609822939 |
| Short name | T2382 |
| Test name | |
| Test status | |
| Simulation time | 2209778029 ps |
| CPU time | 65.4 seconds |
| Started | Aug 24 06:42:23 AM UTC 24 |
| Finished | Aug 24 06:43:30 AM UTC 24 |
| Peak memory | 597896 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2609822939 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 69.xbar_access_same_device.2609822939 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/69.xbar_access_same_device/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/69.xbar_access_same_device_slow_rsp.1867060068 |
| Short name | T2606 |
| Test name | |
| Test status | |
| Simulation time | 121623752062 ps |
| CPU time | 1401.08 seconds |
| Started | Aug 24 06:42:24 AM UTC 24 |
| Finished | Aug 24 07:05:59 AM UTC 24 |
| Peak memory | 599004 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1867060068 -assert nopostproc +UVM_T ESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 69.xbar_access_same_device_slow_rsp.1867060068 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/69.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/69.xbar_error_and_unmapped_addr.1320663185 |
| Short name | T2380 |
| Test name | |
| Test status | |
| Simulation time | 694228335 ps |
| CPU time | 21.12 seconds |
| Started | Aug 24 06:43:02 AM UTC 24 |
| Finished | Aug 24 06:43:24 AM UTC 24 |
| Peak memory | 597700 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1320663185 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 69.xbar_error_and_unmapped_addr.1320663185 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/69.xbar_error_and_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/69.xbar_error_random.4065242917 |
| Short name | T2386 |
| Test name | |
| Test status | |
| Simulation time | 2160079992 ps |
| CPU time | 50.52 seconds |
| Started | Aug 24 06:42:53 AM UTC 24 |
| Finished | Aug 24 06:43:45 AM UTC 24 |
| Peak memory | 597752 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4065242917 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 69.xbar_error_random.4065242917 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/69.xbar_error_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/69.xbar_random.2135616087 |
| Short name | T2372 |
| Test name | |
| Test status | |
| Simulation time | 1056072523 ps |
| CPU time | 26.28 seconds |
| Started | Aug 24 06:42:12 AM UTC 24 |
| Finished | Aug 24 06:42:39 AM UTC 24 |
| Peak memory | 597872 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2135616087 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 69.xbar_random.2135616087 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/69.xbar_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/69.xbar_random_large_delays.204892437 |
| Short name | T2403 |
| Test name | |
| Test status | |
| Simulation time | 24830046969 ps |
| CPU time | 199.91 seconds |
| Started | Aug 24 06:42:15 AM UTC 24 |
| Finished | Aug 24 06:45:37 AM UTC 24 |
| Peak memory | 598076 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max _device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=204892437 -assert nopostproc +UV M_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 69.xbar_random_large_delays.204892437 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/69.xbar_random_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/69.xbar_random_slow_rsp.796876506 |
| Short name | T2444 |
| Test name | |
| Test status | |
| Simulation time | 33531966946 ps |
| CPU time | 396.17 seconds |
| Started | Aug 24 06:42:19 AM UTC 24 |
| Finished | Aug 24 06:49:00 AM UTC 24 |
| Peak memory | 598120 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=796876506 -assert nopostproc +UVM_TE STNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 69.xbar_random_slow_rsp.796876506 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/69.xbar_random_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/69.xbar_random_zero_delays.4215730353 |
| Short name | T2371 |
| Test name | |
| Test status | |
| Simulation time | 98406589 ps |
| CPU time | 8.37 seconds |
| Started | Aug 24 06:42:14 AM UTC 24 |
| Finished | Aug 24 06:42:23 AM UTC 24 |
| Peak memory | 597696 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4215730353 -assert nopostpr oc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 69.xbar_random_zero_delays.4215730353 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/69.xbar_random_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/69.xbar_same_source.2847090944 |
| Short name | T2373 |
| Test name | |
| Test status | |
| Simulation time | 291599432 ps |
| CPU time | 8.05 seconds |
| Started | Aug 24 06:42:38 AM UTC 24 |
| Finished | Aug 24 06:42:47 AM UTC 24 |
| Peak memory | 597676 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2847090944 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 69.xbar_same_source.2847090944 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/69.xbar_same_source/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/69.xbar_smoke.2677379497 |
| Short name | T2366 |
| Test name | |
| Test status | |
| Simulation time | 196578727 ps |
| CPU time | 6.67 seconds |
| Started | Aug 24 06:41:52 AM UTC 24 |
| Finished | Aug 24 06:41:59 AM UTC 24 |
| Peak memory | 595884 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2677379497 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 8_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 69.xbar_smoke.2677379497 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/69.xbar_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/69.xbar_smoke_large_delays.2163513582 |
| Short name | T2379 |
| Test name | |
| Test status | |
| Simulation time | 9408100300 ps |
| CPU time | 75.37 seconds |
| Started | Aug 24 06:42:07 AM UTC 24 |
| Finished | Aug 24 06:43:24 AM UTC 24 |
| Peak memory | 596016 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max _device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2163513582 -assert nopostproc +U VM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 69.xbar_smoke_large_delays.2163513582 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/69.xbar_smoke_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/69.xbar_smoke_slow_rsp.1875490648 |
| Short name | T2378 |
| Test name | |
| Test status | |
| Simulation time | 5878495961 ps |
| CPU time | 72.97 seconds |
| Started | Aug 24 06:42:08 AM UTC 24 |
| Finished | Aug 24 06:43:22 AM UTC 24 |
| Peak memory | 595764 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1875490648 -assert nopostproc +UVM_T ESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 69.xbar_smoke_slow_rsp.1875490648 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/69.xbar_smoke_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/69.xbar_smoke_zero_delays.2141886440 |
| Short name | T2369 |
| Test name | |
| Test status | |
| Simulation time | 41199577 ps |
| CPU time | 4.87 seconds |
| Started | Aug 24 06:42:03 AM UTC 24 |
| Finished | Aug 24 06:42:09 AM UTC 24 |
| Peak memory | 595772 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2141886440 -assert nopostpr oc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 69.xbar_smoke_zero_delays.2141886440 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/69.xbar_smoke_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/69.xbar_stress_all.662251364 |
| Short name | T2422 |
| Test name | |
| Test status | |
| Simulation time | 10915041644 ps |
| CPU time | 265.85 seconds |
| Started | Aug 24 06:43:03 AM UTC 24 |
| Finished | Aug 24 06:47:32 AM UTC 24 |
| Peak memory | 597828 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=662251364 -assert nopostproc +UVM_TESTNAME =xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 69.xbar_stress_all.662251364 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/69.xbar_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/69.xbar_stress_all_with_error.1049974550 |
| Short name | T2413 |
| Test name | |
| Test status | |
| Simulation time | 6487356181 ps |
| CPU time | 175.24 seconds |
| Started | Aug 24 06:43:32 AM UTC 24 |
| Finished | Aug 24 06:46:31 AM UTC 24 |
| Peak memory | 597828 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1049974550 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 69.xbar_stress_all_with_error.1049974550 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/69.xbar_stress_all_with_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/69.xbar_stress_all_with_rand_reset.835843258 |
| Short name | T2399 |
| Test name | |
| Test status | |
| Simulation time | 1735003488 ps |
| CPU time | 101.42 seconds |
| Started | Aug 24 06:43:18 AM UTC 24 |
| Finished | Aug 24 06:45:02 AM UTC 24 |
| Peak memory | 597692 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=835843258 -assert nopostproc +UVM_TESTNAME =xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 69.xbar_stress_all_with_rand_reset.835843258 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/69.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/69.xbar_stress_all_with_reset_error.3725915762 |
| Short name | T2391 |
| Test name | |
| Test status | |
| Simulation time | 170663410 ps |
| CPU time | 38.33 seconds |
| Started | Aug 24 06:43:36 AM UTC 24 |
| Finished | Aug 24 06:44:16 AM UTC 24 |
| Peak memory | 597692 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3725915762 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 69.xbar_stress_all_with_reset_error.3725915762 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/69.xbar_stress_all_with_reset_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/69.xbar_unmapped_addr.2209213805 |
| Short name | T2377 |
| Test name | |
| Test status | |
| Simulation time | 179669275 ps |
| CPU time | 16.5 seconds |
| Started | Aug 24 06:43:01 AM UTC 24 |
| Finished | Aug 24 06:43:19 AM UTC 24 |
| Peak memory | 597688 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2209213805 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 69.xbar_unmapped_addr.2209213805 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/69.xbar_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/7.chip_csr_mem_rw_with_rand_reset.1364503026 |
| Short name | T444 |
| Test name | |
| Test status | |
| Simulation time | 8339369452 ps |
| CPU time | 338.49 seconds |
| Started | Aug 24 04:21:58 AM UTC 24 |
| Finished | Aug 24 04:27:40 AM UTC 24 |
| Peak memory | 658456 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000 000000 +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/too ls/sim.tcl +ntb_random_seed=1364503026 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/nul l -cm_name 7.chip_csr_mem_rw_with_rand_reset.1364503026 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/7.chip_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/7.chip_csr_rw.1109154162 |
| Short name | T1393 |
| Test name | |
| Test status | |
| Simulation time | 4373501244 ps |
| CPU time | 288.4 seconds |
| Started | Aug 24 04:21:58 AM UTC 24 |
| Finished | Aug 24 04:26:50 AM UTC 24 |
| Peak memory | 617308 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +stub_cpu=1 +cdc_instrumentation_ena bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1109154162 -assert nopost proc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os _regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.chip_csr_rw.1109154162 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/7.chip_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/7.chip_same_csr_outstanding.2422952038 |
| Short name | T1478 |
| Test name | |
| Test status | |
| Simulation time | 28187069162 ps |
| CPU time | 2198.05 seconds |
| Started | Aug 24 04:17:17 AM UTC 24 |
| Finished | Aug 24 04:54:18 AM UTC 24 |
| Peak memory | 613372 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +test_timeout_ns=120_000_000 +run_same_csr_outstanding +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim .tcl +ntb_random_seed=2422952038 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_ name 7.chip_same_csr_outstanding.2422952038 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/7.chip_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/7.xbar_access_same_device_slow_rsp.3693847138 |
| Short name | T806 |
| Test name | |
| Test status | |
| Simulation time | 37374150336 ps |
| CPU time | 452.98 seconds |
| Started | Aug 24 04:19:58 AM UTC 24 |
| Finished | Aug 24 04:27:36 AM UTC 24 |
| Peak memory | 597820 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3693847138 -assert nopostproc +UVM_T ESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.xbar_access_same_device_slow_rsp.3693847138 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/7.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/7.xbar_error_and_unmapped_addr.71084607 |
| Short name | T1381 |
| Test name | |
| Test status | |
| Simulation time | 1132165575 ps |
| CPU time | 33.13 seconds |
| Started | Aug 24 04:21:15 AM UTC 24 |
| Finished | Aug 24 04:21:50 AM UTC 24 |
| Peak memory | 597752 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=71084607 -assert nopostproc +UVM_TESTNAME= xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.xbar_error_and_unmapped_addr.71084607 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/7.xbar_error_and_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/7.xbar_random.3621292680 |
| Short name | T576 |
| Test name | |
| Test status | |
| Simulation time | 569974223 ps |
| CPU time | 40.36 seconds |
| Started | Aug 24 04:18:40 AM UTC 24 |
| Finished | Aug 24 04:19:22 AM UTC 24 |
| Peak memory | 597908 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3621292680 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.xbar_random.3621292680 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/7.xbar_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/7.xbar_random_large_delays.2609793722 |
| Short name | T508 |
| Test name | |
| Test status | |
| Simulation time | 89254402489 ps |
| CPU time | 711.74 seconds |
| Started | Aug 24 04:19:37 AM UTC 24 |
| Finished | Aug 24 04:31:36 AM UTC 24 |
| Peak memory | 597820 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max _device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2609793722 -assert nopostproc +U VM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.xbar_random_large_delays.2609793722 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/7.xbar_random_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/7.xbar_random_slow_rsp.2898321551 |
| Short name | T504 |
| Test name | |
| Test status | |
| Simulation time | 49717462872 ps |
| CPU time | 561.41 seconds |
| Started | Aug 24 04:19:39 AM UTC 24 |
| Finished | Aug 24 04:29:06 AM UTC 24 |
| Peak memory | 597828 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2898321551 -assert nopostproc +UVM_T ESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.xbar_random_slow_rsp.2898321551 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/7.xbar_random_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/7.xbar_random_zero_delays.1294191086 |
| Short name | T585 |
| Test name | |
| Test status | |
| Simulation time | 398349772 ps |
| CPU time | 28.78 seconds |
| Started | Aug 24 04:19:14 AM UTC 24 |
| Finished | Aug 24 04:19:44 AM UTC 24 |
| Peak memory | 597760 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1294191086 -assert nopostpr oc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.xbar_random_zero_delays.1294191086 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/7.xbar_random_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/7.xbar_same_source.1406217830 |
| Short name | T495 |
| Test name | |
| Test status | |
| Simulation time | 2020875486 ps |
| CPU time | 44.11 seconds |
| Started | Aug 24 04:20:16 AM UTC 24 |
| Finished | Aug 24 04:21:01 AM UTC 24 |
| Peak memory | 597696 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1406217830 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.xbar_same_source.1406217830 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/7.xbar_same_source/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/7.xbar_smoke.480423633 |
| Short name | T1375 |
| Test name | |
| Test status | |
| Simulation time | 122262751 ps |
| CPU time | 6.25 seconds |
| Started | Aug 24 04:17:53 AM UTC 24 |
| Finished | Aug 24 04:18:00 AM UTC 24 |
| Peak memory | 595768 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=480423633 -assert nopostproc +UVM_TESTNAME =xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08 _22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.xbar_smoke.480423633 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/7.xbar_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/7.xbar_smoke_large_delays.1633544578 |
| Short name | T1378 |
| Test name | |
| Test status | |
| Simulation time | 8533456480 ps |
| CPU time | 72.18 seconds |
| Started | Aug 24 04:18:14 AM UTC 24 |
| Finished | Aug 24 04:19:28 AM UTC 24 |
| Peak memory | 595768 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max _device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1633544578 -assert nopostproc +U VM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.xbar_smoke_large_delays.1633544578 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/7.xbar_smoke_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/7.xbar_smoke_slow_rsp.641434160 |
| Short name | T1377 |
| Test name | |
| Test status | |
| Simulation time | 5068012149 ps |
| CPU time | 61.76 seconds |
| Started | Aug 24 04:18:22 AM UTC 24 |
| Finished | Aug 24 04:19:25 AM UTC 24 |
| Peak memory | 595892 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=641434160 -assert nopostproc +UVM_TE STNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.xbar_smoke_slow_rsp.641434160 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/7.xbar_smoke_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/7.xbar_smoke_zero_delays.495227333 |
| Short name | T1376 |
| Test name | |
| Test status | |
| Simulation time | 41931748 ps |
| CPU time | 5.09 seconds |
| Started | Aug 24 04:18:01 AM UTC 24 |
| Finished | Aug 24 04:18:07 AM UTC 24 |
| Peak memory | 595704 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=495227333 -assert nopostpro c +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.xbar_smoke_zero_delays.495227333 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/7.xbar_smoke_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/7.xbar_stress_all.3911482237 |
| Short name | T497 |
| Test name | |
| Test status | |
| Simulation time | 2385389422 ps |
| CPU time | 62.18 seconds |
| Started | Aug 24 04:21:41 AM UTC 24 |
| Finished | Aug 24 04:22:45 AM UTC 24 |
| Peak memory | 597964 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3911482237 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.xbar_stress_all.3911482237 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/7.xbar_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/7.xbar_stress_all_with_error.133026321 |
| Short name | T788 |
| Test name | |
| Test status | |
| Simulation time | 15470804331 ps |
| CPU time | 393.54 seconds |
| Started | Aug 24 04:21:47 AM UTC 24 |
| Finished | Aug 24 04:28:25 AM UTC 24 |
| Peak memory | 597824 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=133026321 -assert nopostproc +UVM_TESTNAME =xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.xbar_stress_all_with_error.133026321 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/7.xbar_stress_all_with_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/7.xbar_stress_all_with_rand_reset.4263459417 |
| Short name | T850 |
| Test name | |
| Test status | |
| Simulation time | 14708166 ps |
| CPU time | 20.89 seconds |
| Started | Aug 24 04:21:45 AM UTC 24 |
| Finished | Aug 24 04:22:07 AM UTC 24 |
| Peak memory | 595644 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4263459417 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.xbar_stress_all_with_rand_reset.4263459417 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/7.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/7.xbar_stress_all_with_reset_error.1468136840 |
| Short name | T638 |
| Test name | |
| Test status | |
| Simulation time | 374154146 ps |
| CPU time | 76.02 seconds |
| Started | Aug 24 04:21:51 AM UTC 24 |
| Finished | Aug 24 04:23:09 AM UTC 24 |
| Peak memory | 597696 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1468136840 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.xbar_stress_all_with_reset_error.1468136840 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/7.xbar_stress_all_with_reset_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/7.xbar_unmapped_addr.3373790331 |
| Short name | T1380 |
| Test name | |
| Test status | |
| Simulation time | 1047531111 ps |
| CPU time | 31.04 seconds |
| Started | Aug 24 04:21:11 AM UTC 24 |
| Finished | Aug 24 04:21:44 AM UTC 24 |
| Peak memory | 597756 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3373790331 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.xbar_unmapped_addr.3373790331 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/7.xbar_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/70.xbar_access_same_device.1223888611 |
| Short name | T2392 |
| Test name | |
| Test status | |
| Simulation time | 236117628 ps |
| CPU time | 13.13 seconds |
| Started | Aug 24 06:44:07 AM UTC 24 |
| Finished | Aug 24 06:44:21 AM UTC 24 |
| Peak memory | 597772 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1223888611 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 70.xbar_access_same_device.1223888611 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/70.xbar_access_same_device/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/70.xbar_access_same_device_slow_rsp.2767060716 |
| Short name | T2565 |
| Test name | |
| Test status | |
| Simulation time | 91201822278 ps |
| CPU time | 1021.88 seconds |
| Started | Aug 24 06:44:25 AM UTC 24 |
| Finished | Aug 24 07:01:37 AM UTC 24 |
| Peak memory | 598084 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2767060716 -assert nopostproc +UVM_T ESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 70.xbar_access_same_device_slow_rsp.2767060716 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/70.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/70.xbar_error_and_unmapped_addr.2165591044 |
| Short name | T2395 |
| Test name | |
| Test status | |
| Simulation time | 54275097 ps |
| CPU time | 4.47 seconds |
| Started | Aug 24 06:44:35 AM UTC 24 |
| Finished | Aug 24 06:44:41 AM UTC 24 |
| Peak memory | 595644 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2165591044 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 70.xbar_error_and_unmapped_addr.2165591044 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/70.xbar_error_and_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/70.xbar_error_random.1368432643 |
| Short name | T2394 |
| Test name | |
| Test status | |
| Simulation time | 151863084 ps |
| CPU time | 11.11 seconds |
| Started | Aug 24 06:44:28 AM UTC 24 |
| Finished | Aug 24 06:44:41 AM UTC 24 |
| Peak memory | 597820 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1368432643 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 70.xbar_error_random.1368432643 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/70.xbar_error_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/70.xbar_random.2958164117 |
| Short name | T2387 |
| Test name | |
| Test status | |
| Simulation time | 31266401 ps |
| CPU time | 4.65 seconds |
| Started | Aug 24 06:43:47 AM UTC 24 |
| Finished | Aug 24 06:43:53 AM UTC 24 |
| Peak memory | 595784 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2958164117 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 70.xbar_random.2958164117 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/70.xbar_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/70.xbar_random_large_delays.1897148309 |
| Short name | T2497 |
| Test name | |
| Test status | |
| Simulation time | 88413246841 ps |
| CPU time | 711.93 seconds |
| Started | Aug 24 06:43:59 AM UTC 24 |
| Finished | Aug 24 06:55:58 AM UTC 24 |
| Peak memory | 597820 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max _device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1897148309 -assert nopostproc +U VM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 70.xbar_random_large_delays.1897148309 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/70.xbar_random_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/70.xbar_random_slow_rsp.1575175938 |
| Short name | T2463 |
| Test name | |
| Test status | |
| Simulation time | 36752299654 ps |
| CPU time | 448.72 seconds |
| Started | Aug 24 06:43:59 AM UTC 24 |
| Finished | Aug 24 06:51:33 AM UTC 24 |
| Peak memory | 598136 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1575175938 -assert nopostproc +UVM_T ESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 70.xbar_random_slow_rsp.1575175938 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/70.xbar_random_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/70.xbar_random_zero_delays.109856364 |
| Short name | T2388 |
| Test name | |
| Test status | |
| Simulation time | 186831926 ps |
| CPU time | 12.54 seconds |
| Started | Aug 24 06:43:57 AM UTC 24 |
| Finished | Aug 24 06:44:11 AM UTC 24 |
| Peak memory | 597760 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=109856364 -assert nopostpro c +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 70.xbar_random_zero_delays.109856364 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/70.xbar_random_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/70.xbar_same_source.2367336150 |
| Short name | T2396 |
| Test name | |
| Test status | |
| Simulation time | 691900330 ps |
| CPU time | 15.16 seconds |
| Started | Aug 24 06:44:27 AM UTC 24 |
| Finished | Aug 24 06:44:44 AM UTC 24 |
| Peak memory | 597676 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2367336150 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 70.xbar_same_source.2367336150 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/70.xbar_same_source/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/70.xbar_smoke.2092996917 |
| Short name | T2384 |
| Test name | |
| Test status | |
| Simulation time | 37349323 ps |
| CPU time | 4.82 seconds |
| Started | Aug 24 06:43:37 AM UTC 24 |
| Finished | Aug 24 06:43:43 AM UTC 24 |
| Peak memory | 595880 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2092996917 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 8_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 70.xbar_smoke.2092996917 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/70.xbar_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/70.xbar_smoke_large_delays.2826197798 |
| Short name | T2397 |
| Test name | |
| Test status | |
| Simulation time | 9195907337 ps |
| CPU time | 72.61 seconds |
| Started | Aug 24 06:43:40 AM UTC 24 |
| Finished | Aug 24 06:44:54 AM UTC 24 |
| Peak memory | 596016 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max _device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2826197798 -assert nopostproc +U VM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 70.xbar_smoke_large_delays.2826197798 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/70.xbar_smoke_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/70.xbar_smoke_slow_rsp.4151098378 |
| Short name | T2393 |
| Test name | |
| Test status | |
| Simulation time | 4056360295 ps |
| CPU time | 47.86 seconds |
| Started | Aug 24 06:43:45 AM UTC 24 |
| Finished | Aug 24 06:44:34 AM UTC 24 |
| Peak memory | 595848 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4151098378 -assert nopostproc +UVM_T ESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 70.xbar_smoke_slow_rsp.4151098378 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/70.xbar_smoke_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/70.xbar_smoke_zero_delays.834631605 |
| Short name | T2385 |
| Test name | |
| Test status | |
| Simulation time | 48746044 ps |
| CPU time | 5.11 seconds |
| Started | Aug 24 06:43:39 AM UTC 24 |
| Finished | Aug 24 06:43:45 AM UTC 24 |
| Peak memory | 595640 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=834631605 -assert nopostpro c +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 70.xbar_smoke_zero_delays.834631605 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/70.xbar_smoke_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/70.xbar_stress_all.3746404319 |
| Short name | T2408 |
| Test name | |
| Test status | |
| Simulation time | 1579284265 ps |
| CPU time | 78.86 seconds |
| Started | Aug 24 06:44:49 AM UTC 24 |
| Finished | Aug 24 06:46:09 AM UTC 24 |
| Peak memory | 597764 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3746404319 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 70.xbar_stress_all.3746404319 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/70.xbar_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/70.xbar_stress_all_with_error.2211459086 |
| Short name | T2407 |
| Test name | |
| Test status | |
| Simulation time | 1061397519 ps |
| CPU time | 58.27 seconds |
| Started | Aug 24 06:44:56 AM UTC 24 |
| Finished | Aug 24 06:45:55 AM UTC 24 |
| Peak memory | 597952 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2211459086 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 70.xbar_stress_all_with_error.2211459086 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/70.xbar_stress_all_with_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/70.xbar_stress_all_with_rand_reset.276664704 |
| Short name | T2491 |
| Test name | |
| Test status | |
| Simulation time | 20906367436 ps |
| CPU time | 644.06 seconds |
| Started | Aug 24 06:44:54 AM UTC 24 |
| Finished | Aug 24 06:55:45 AM UTC 24 |
| Peak memory | 597888 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=276664704 -assert nopostproc +UVM_TESTNAME =xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 70.xbar_stress_all_with_rand_reset.276664704 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/70.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/70.xbar_stress_all_with_reset_error.3491306368 |
| Short name | T2424 |
| Test name | |
| Test status | |
| Simulation time | 642153375 ps |
| CPU time | 158.13 seconds |
| Started | Aug 24 06:44:58 AM UTC 24 |
| Finished | Aug 24 06:47:38 AM UTC 24 |
| Peak memory | 597696 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3491306368 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 70.xbar_stress_all_with_reset_error.3491306368 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/70.xbar_stress_all_with_reset_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/70.xbar_unmapped_addr.388192310 |
| Short name | T2398 |
| Test name | |
| Test status | |
| Simulation time | 791719058 ps |
| CPU time | 23.79 seconds |
| Started | Aug 24 06:44:30 AM UTC 24 |
| Finished | Aug 24 06:44:55 AM UTC 24 |
| Peak memory | 597832 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=388192310 -assert nopostproc +UVM_TESTNAME =xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 70.xbar_unmapped_addr.388192310 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/70.xbar_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/71.xbar_access_same_device.4160961815 |
| Short name | T2427 |
| Test name | |
| Test status | |
| Simulation time | 3978267081 ps |
| CPU time | 104.35 seconds |
| Started | Aug 24 06:46:03 AM UTC 24 |
| Finished | Aug 24 06:47:49 AM UTC 24 |
| Peak memory | 598052 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4160961815 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 71.xbar_access_same_device.4160961815 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/71.xbar_access_same_device/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/71.xbar_access_same_device_slow_rsp.2001627283 |
| Short name | T2616 |
| Test name | |
| Test status | |
| Simulation time | 103061654516 ps |
| CPU time | 1230.66 seconds |
| Started | Aug 24 06:46:07 AM UTC 24 |
| Finished | Aug 24 07:06:50 AM UTC 24 |
| Peak memory | 598788 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2001627283 -assert nopostproc +UVM_T ESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 71.xbar_access_same_device_slow_rsp.2001627283 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/71.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/71.xbar_error_and_unmapped_addr.2247382158 |
| Short name | T2417 |
| Test name | |
| Test status | |
| Simulation time | 137186106 ps |
| CPU time | 6.11 seconds |
| Started | Aug 24 06:46:34 AM UTC 24 |
| Finished | Aug 24 06:46:42 AM UTC 24 |
| Peak memory | 595708 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2247382158 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 71.xbar_error_and_unmapped_addr.2247382158 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/71.xbar_error_and_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/71.xbar_error_random.3194442302 |
| Short name | T2415 |
| Test name | |
| Test status | |
| Simulation time | 164737944 ps |
| CPU time | 10.43 seconds |
| Started | Aug 24 06:46:23 AM UTC 24 |
| Finished | Aug 24 06:46:35 AM UTC 24 |
| Peak memory | 597752 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3194442302 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 71.xbar_error_random.3194442302 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/71.xbar_error_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/71.xbar_random.1555912212 |
| Short name | T2405 |
| Test name | |
| Test status | |
| Simulation time | 685589184 ps |
| CPU time | 17.03 seconds |
| Started | Aug 24 06:45:31 AM UTC 24 |
| Finished | Aug 24 06:45:49 AM UTC 24 |
| Peak memory | 597692 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1555912212 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 71.xbar_random.1555912212 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/71.xbar_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/71.xbar_random_large_delays.1703885649 |
| Short name | T2528 |
| Test name | |
| Test status | |
| Simulation time | 86946998082 ps |
| CPU time | 746.61 seconds |
| Started | Aug 24 06:45:51 AM UTC 24 |
| Finished | Aug 24 06:58:25 AM UTC 24 |
| Peak memory | 597884 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max _device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1703885649 -assert nopostproc +U VM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 71.xbar_random_large_delays.1703885649 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/71.xbar_random_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/71.xbar_random_slow_rsp.4096443016 |
| Short name | T2481 |
| Test name | |
| Test status | |
| Simulation time | 40228051691 ps |
| CPU time | 471.96 seconds |
| Started | Aug 24 06:45:56 AM UTC 24 |
| Finished | Aug 24 06:53:54 AM UTC 24 |
| Peak memory | 597820 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4096443016 -assert nopostproc +UVM_T ESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 71.xbar_random_slow_rsp.4096443016 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/71.xbar_random_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/71.xbar_random_zero_delays.1157566162 |
| Short name | T2406 |
| Test name | |
| Test status | |
| Simulation time | 116052224 ps |
| CPU time | 9.32 seconds |
| Started | Aug 24 06:45:43 AM UTC 24 |
| Finished | Aug 24 06:45:53 AM UTC 24 |
| Peak memory | 597696 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1157566162 -assert nopostpr oc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 71.xbar_random_zero_delays.1157566162 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/71.xbar_random_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/71.xbar_same_source.3919730416 |
| Short name | T2414 |
| Test name | |
| Test status | |
| Simulation time | 1006096220 ps |
| CPU time | 20.86 seconds |
| Started | Aug 24 06:46:09 AM UTC 24 |
| Finished | Aug 24 06:46:31 AM UTC 24 |
| Peak memory | 597744 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3919730416 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 71.xbar_same_source.3919730416 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/71.xbar_same_source/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/71.xbar_smoke.4284931845 |
| Short name | T2401 |
| Test name | |
| Test status | |
| Simulation time | 244362460 ps |
| CPU time | 7.64 seconds |
| Started | Aug 24 06:45:08 AM UTC 24 |
| Finished | Aug 24 06:45:16 AM UTC 24 |
| Peak memory | 595772 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4284931845 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 8_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 71.xbar_smoke.4284931845 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/71.xbar_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/71.xbar_smoke_large_delays.462145273 |
| Short name | T2409 |
| Test name | |
| Test status | |
| Simulation time | 7289318932 ps |
| CPU time | 57.78 seconds |
| Started | Aug 24 06:45:16 AM UTC 24 |
| Finished | Aug 24 06:46:15 AM UTC 24 |
| Peak memory | 595768 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max _device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=462145273 -assert nopostproc +UV M_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 71.xbar_smoke_large_delays.462145273 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/71.xbar_smoke_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/71.xbar_smoke_slow_rsp.1977690128 |
| Short name | T2410 |
| Test name | |
| Test status | |
| Simulation time | 3910934565 ps |
| CPU time | 48.95 seconds |
| Started | Aug 24 06:45:30 AM UTC 24 |
| Finished | Aug 24 06:46:21 AM UTC 24 |
| Peak memory | 595708 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1977690128 -assert nopostproc +UVM_T ESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 71.xbar_smoke_slow_rsp.1977690128 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/71.xbar_smoke_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/71.xbar_smoke_zero_delays.3370096963 |
| Short name | T2400 |
| Test name | |
| Test status | |
| Simulation time | 43906735 ps |
| CPU time | 5.07 seconds |
| Started | Aug 24 06:45:10 AM UTC 24 |
| Finished | Aug 24 06:45:16 AM UTC 24 |
| Peak memory | 595696 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3370096963 -assert nopostpr oc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 71.xbar_smoke_zero_delays.3370096963 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/71.xbar_smoke_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/71.xbar_stress_all.437247597 |
| Short name | T2431 |
| Test name | |
| Test status | |
| Simulation time | 1607514907 ps |
| CPU time | 88.7 seconds |
| Started | Aug 24 06:46:39 AM UTC 24 |
| Finished | Aug 24 06:48:09 AM UTC 24 |
| Peak memory | 597828 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=437247597 -assert nopostproc +UVM_TESTNAME =xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 71.xbar_stress_all.437247597 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/71.xbar_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/71.xbar_stress_all_with_error.1602868949 |
| Short name | T2423 |
| Test name | |
| Test status | |
| Simulation time | 901217949 ps |
| CPU time | 49.89 seconds |
| Started | Aug 24 06:46:45 AM UTC 24 |
| Finished | Aug 24 06:47:36 AM UTC 24 |
| Peak memory | 597948 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1602868949 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 71.xbar_stress_all_with_error.1602868949 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/71.xbar_stress_all_with_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/71.xbar_stress_all_with_rand_reset.276046638 |
| Short name | T2433 |
| Test name | |
| Test status | |
| Simulation time | 430163492 ps |
| CPU time | 98.76 seconds |
| Started | Aug 24 06:46:40 AM UTC 24 |
| Finished | Aug 24 06:48:21 AM UTC 24 |
| Peak memory | 597688 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=276046638 -assert nopostproc +UVM_TESTNAME =xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 71.xbar_stress_all_with_rand_reset.276046638 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/71.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/71.xbar_stress_all_with_reset_error.2340243943 |
| Short name | T2441 |
| Test name | |
| Test status | |
| Simulation time | 648923598 ps |
| CPU time | 124.85 seconds |
| Started | Aug 24 06:46:46 AM UTC 24 |
| Finished | Aug 24 06:48:53 AM UTC 24 |
| Peak memory | 597756 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2340243943 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 71.xbar_stress_all_with_reset_error.2340243943 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/71.xbar_stress_all_with_reset_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/71.xbar_unmapped_addr.3738050290 |
| Short name | T2416 |
| Test name | |
| Test status | |
| Simulation time | 71880822 ps |
| CPU time | 5.46 seconds |
| Started | Aug 24 06:46:29 AM UTC 24 |
| Finished | Aug 24 06:46:36 AM UTC 24 |
| Peak memory | 595628 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3738050290 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 71.xbar_unmapped_addr.3738050290 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/71.xbar_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/72.xbar_access_same_device.1183876422 |
| Short name | T2428 |
| Test name | |
| Test status | |
| Simulation time | 145820334 ps |
| CPU time | 6.52 seconds |
| Started | Aug 24 06:47:50 AM UTC 24 |
| Finished | Aug 24 06:47:58 AM UTC 24 |
| Peak memory | 595656 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1183876422 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 72.xbar_access_same_device.1183876422 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/72.xbar_access_same_device/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/72.xbar_access_same_device_slow_rsp.4212241010 |
| Short name | T2636 |
| Test name | |
| Test status | |
| Simulation time | 101906715608 ps |
| CPU time | 1239.44 seconds |
| Started | Aug 24 06:47:52 AM UTC 24 |
| Finished | Aug 24 07:08:44 AM UTC 24 |
| Peak memory | 598776 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4212241010 -assert nopostproc +UVM_T ESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 72.xbar_access_same_device_slow_rsp.4212241010 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/72.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/72.xbar_error_and_unmapped_addr.2121671830 |
| Short name | T2440 |
| Test name | |
| Test status | |
| Simulation time | 1344546182 ps |
| CPU time | 37.03 seconds |
| Started | Aug 24 06:48:12 AM UTC 24 |
| Finished | Aug 24 06:48:51 AM UTC 24 |
| Peak memory | 597840 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2121671830 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 72.xbar_error_and_unmapped_addr.2121671830 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/72.xbar_error_and_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/72.xbar_error_random.3771259935 |
| Short name | T2434 |
| Test name | |
| Test status | |
| Simulation time | 544280639 ps |
| CPU time | 28.74 seconds |
| Started | Aug 24 06:47:58 AM UTC 24 |
| Finished | Aug 24 06:48:28 AM UTC 24 |
| Peak memory | 597752 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3771259935 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 72.xbar_error_random.3771259935 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/72.xbar_error_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/72.xbar_random.992630154 |
| Short name | T2425 |
| Test name | |
| Test status | |
| Simulation time | 1085790419 ps |
| CPU time | 27.6 seconds |
| Started | Aug 24 06:47:10 AM UTC 24 |
| Finished | Aug 24 06:47:39 AM UTC 24 |
| Peak memory | 597760 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=992630154 -assert nopostproc +UVM_TESTNAME =xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 8_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 72.xbar_random.992630154 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/72.xbar_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/72.xbar_random_large_delays.3497155259 |
| Short name | T2496 |
| Test name | |
| Test status | |
| Simulation time | 58182613109 ps |
| CPU time | 492.17 seconds |
| Started | Aug 24 06:47:40 AM UTC 24 |
| Finished | Aug 24 06:55:57 AM UTC 24 |
| Peak memory | 597824 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max _device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3497155259 -assert nopostproc +U VM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 72.xbar_random_large_delays.3497155259 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/72.xbar_random_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/72.xbar_random_slow_rsp.2469849051 |
| Short name | T2542 |
| Test name | |
| Test status | |
| Simulation time | 61563068174 ps |
| CPU time | 706.49 seconds |
| Started | Aug 24 06:47:47 AM UTC 24 |
| Finished | Aug 24 06:59:41 AM UTC 24 |
| Peak memory | 598072 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2469849051 -assert nopostproc +UVM_T ESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 72.xbar_random_slow_rsp.2469849051 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/72.xbar_random_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/72.xbar_random_zero_delays.3985501418 |
| Short name | T2426 |
| Test name | |
| Test status | |
| Simulation time | 372038259 ps |
| CPU time | 22.96 seconds |
| Started | Aug 24 06:47:20 AM UTC 24 |
| Finished | Aug 24 06:47:44 AM UTC 24 |
| Peak memory | 597700 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3985501418 -assert nopostpr oc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 72.xbar_random_zero_delays.3985501418 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/72.xbar_random_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/72.xbar_same_source.4127101718 |
| Short name | T2436 |
| Test name | |
| Test status | |
| Simulation time | 1885440818 ps |
| CPU time | 37.92 seconds |
| Started | Aug 24 06:47:53 AM UTC 24 |
| Finished | Aug 24 06:48:33 AM UTC 24 |
| Peak memory | 597676 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4127101718 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 72.xbar_same_source.4127101718 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/72.xbar_same_source/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/72.xbar_smoke.4246566043 |
| Short name | T2418 |
| Test name | |
| Test status | |
| Simulation time | 53056566 ps |
| CPU time | 5.19 seconds |
| Started | Aug 24 06:46:49 AM UTC 24 |
| Finished | Aug 24 06:46:55 AM UTC 24 |
| Peak memory | 595632 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4246566043 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 8_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 72.xbar_smoke.4246566043 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/72.xbar_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/72.xbar_smoke_large_delays.2018801702 |
| Short name | T2430 |
| Test name | |
| Test status | |
| Simulation time | 8827160458 ps |
| CPU time | 70.91 seconds |
| Started | Aug 24 06:46:56 AM UTC 24 |
| Finished | Aug 24 06:48:08 AM UTC 24 |
| Peak memory | 595764 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max _device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2018801702 -assert nopostproc +U VM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 72.xbar_smoke_large_delays.2018801702 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/72.xbar_smoke_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/72.xbar_smoke_slow_rsp.2043638341 |
| Short name | T2435 |
| Test name | |
| Test status | |
| Simulation time | 6800022520 ps |
| CPU time | 80.42 seconds |
| Started | Aug 24 06:47:09 AM UTC 24 |
| Finished | Aug 24 06:48:31 AM UTC 24 |
| Peak memory | 595768 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2043638341 -assert nopostproc +UVM_T ESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 72.xbar_smoke_slow_rsp.2043638341 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/72.xbar_smoke_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/72.xbar_smoke_zero_delays.2112215231 |
| Short name | T2419 |
| Test name | |
| Test status | |
| Simulation time | 54369572 ps |
| CPU time | 5.47 seconds |
| Started | Aug 24 06:46:50 AM UTC 24 |
| Finished | Aug 24 06:46:56 AM UTC 24 |
| Peak memory | 595776 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2112215231 -assert nopostpr oc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 72.xbar_smoke_zero_delays.2112215231 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/72.xbar_smoke_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/72.xbar_stress_all.2064334925 |
| Short name | T2443 |
| Test name | |
| Test status | |
| Simulation time | 604415238 ps |
| CPU time | 39.74 seconds |
| Started | Aug 24 06:48:17 AM UTC 24 |
| Finished | Aug 24 06:48:59 AM UTC 24 |
| Peak memory | 597916 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2064334925 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 72.xbar_stress_all.2064334925 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/72.xbar_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/72.xbar_stress_all_with_error.3830654884 |
| Short name | T2459 |
| Test name | |
| Test status | |
| Simulation time | 2773132195 ps |
| CPU time | 138.61 seconds |
| Started | Aug 24 06:48:24 AM UTC 24 |
| Finished | Aug 24 06:50:44 AM UTC 24 |
| Peak memory | 597760 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3830654884 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 72.xbar_stress_all_with_error.3830654884 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/72.xbar_stress_all_with_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/72.xbar_stress_all_with_rand_reset.3020718481 |
| Short name | T2457 |
| Test name | |
| Test status | |
| Simulation time | 426434808 ps |
| CPU time | 133.7 seconds |
| Started | Aug 24 06:48:23 AM UTC 24 |
| Finished | Aug 24 06:50:39 AM UTC 24 |
| Peak memory | 597696 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3020718481 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 72.xbar_stress_all_with_rand_reset.3020718481 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/72.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/72.xbar_stress_all_with_reset_error.1720268121 |
| Short name | T2511 |
| Test name | |
| Test status | |
| Simulation time | 15644871241 ps |
| CPU time | 493.85 seconds |
| Started | Aug 24 06:48:31 AM UTC 24 |
| Finished | Aug 24 06:56:50 AM UTC 24 |
| Peak memory | 598116 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1720268121 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 72.xbar_stress_all_with_reset_error.1720268121 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/72.xbar_stress_all_with_reset_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/72.xbar_unmapped_addr.3503788943 |
| Short name | T2432 |
| Test name | |
| Test status | |
| Simulation time | 112495038 ps |
| CPU time | 11.6 seconds |
| Started | Aug 24 06:48:04 AM UTC 24 |
| Finished | Aug 24 06:48:16 AM UTC 24 |
| Peak memory | 597948 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3503788943 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 72.xbar_unmapped_addr.3503788943 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/72.xbar_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/73.xbar_access_same_device.870758426 |
| Short name | T2458 |
| Test name | |
| Test status | |
| Simulation time | 3168154555 ps |
| CPU time | 91.85 seconds |
| Started | Aug 24 06:49:06 AM UTC 24 |
| Finished | Aug 24 06:50:40 AM UTC 24 |
| Peak memory | 597988 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=870758426 -assert nopostproc +UVM_TESTNAME =xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 73.xbar_access_same_device.870758426 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/73.xbar_access_same_device/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/73.xbar_access_same_device_slow_rsp.2144904844 |
| Short name | T2499 |
| Test name | |
| Test status | |
| Simulation time | 34086933496 ps |
| CPU time | 410.52 seconds |
| Started | Aug 24 06:49:12 AM UTC 24 |
| Finished | Aug 24 06:56:07 AM UTC 24 |
| Peak memory | 598076 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2144904844 -assert nopostproc +UVM_T ESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 73.xbar_access_same_device_slow_rsp.2144904844 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/73.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/73.xbar_error_and_unmapped_addr.1920486231 |
| Short name | T2449 |
| Test name | |
| Test status | |
| Simulation time | 174097990 ps |
| CPU time | 13.84 seconds |
| Started | Aug 24 06:49:23 AM UTC 24 |
| Finished | Aug 24 06:49:38 AM UTC 24 |
| Peak memory | 597696 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1920486231 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 73.xbar_error_and_unmapped_addr.1920486231 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/73.xbar_error_and_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/73.xbar_error_random.473728384 |
| Short name | T2447 |
| Test name | |
| Test status | |
| Simulation time | 67996709 ps |
| CPU time | 6.32 seconds |
| Started | Aug 24 06:49:14 AM UTC 24 |
| Finished | Aug 24 06:49:21 AM UTC 24 |
| Peak memory | 597948 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=473728384 -assert nopostproc +UVM_TESTNAME =xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 73.xbar_error_random.473728384 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/73.xbar_error_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/73.xbar_random.4218710013 |
| Short name | T2446 |
| Test name | |
| Test status | |
| Simulation time | 214262355 ps |
| CPU time | 14.55 seconds |
| Started | Aug 24 06:48:53 AM UTC 24 |
| Finished | Aug 24 06:49:09 AM UTC 24 |
| Peak memory | 597756 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4218710013 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 73.xbar_random.4218710013 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/73.xbar_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/73.xbar_random_large_delays.1458303923 |
| Short name | T2479 |
| Test name | |
| Test status | |
| Simulation time | 33571547835 ps |
| CPU time | 276.17 seconds |
| Started | Aug 24 06:49:03 AM UTC 24 |
| Finished | Aug 24 06:53:43 AM UTC 24 |
| Peak memory | 597964 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max _device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1458303923 -assert nopostproc +U VM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 73.xbar_random_large_delays.1458303923 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/73.xbar_random_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/73.xbar_random_slow_rsp.3515208434 |
| Short name | T2532 |
| Test name | |
| Test status | |
| Simulation time | 52385429020 ps |
| CPU time | 587.75 seconds |
| Started | Aug 24 06:49:05 AM UTC 24 |
| Finished | Aug 24 06:58:59 AM UTC 24 |
| Peak memory | 598108 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3515208434 -assert nopostproc +UVM_T ESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 73.xbar_random_slow_rsp.3515208434 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/73.xbar_random_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/73.xbar_random_zero_delays.112776961 |
| Short name | T2445 |
| Test name | |
| Test status | |
| Simulation time | 93303364 ps |
| CPU time | 8.43 seconds |
| Started | Aug 24 06:48:57 AM UTC 24 |
| Finished | Aug 24 06:49:07 AM UTC 24 |
| Peak memory | 597948 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=112776961 -assert nopostpro c +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 73.xbar_random_zero_delays.112776961 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/73.xbar_random_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/73.xbar_same_source.2345681917 |
| Short name | T2448 |
| Test name | |
| Test status | |
| Simulation time | 365313121 ps |
| CPU time | 20.38 seconds |
| Started | Aug 24 06:49:12 AM UTC 24 |
| Finished | Aug 24 06:49:34 AM UTC 24 |
| Peak memory | 597832 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2345681917 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 73.xbar_same_source.2345681917 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/73.xbar_same_source/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/73.xbar_smoke.3387578468 |
| Short name | T2438 |
| Test name | |
| Test status | |
| Simulation time | 196739041 ps |
| CPU time | 6.77 seconds |
| Started | Aug 24 06:48:35 AM UTC 24 |
| Finished | Aug 24 06:48:43 AM UTC 24 |
| Peak memory | 595916 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3387578468 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 8_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 73.xbar_smoke.3387578468 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/73.xbar_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/73.xbar_smoke_large_delays.1671527957 |
| Short name | T2452 |
| Test name | |
| Test status | |
| Simulation time | 9295034942 ps |
| CPU time | 72.16 seconds |
| Started | Aug 24 06:48:46 AM UTC 24 |
| Finished | Aug 24 06:50:00 AM UTC 24 |
| Peak memory | 595832 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max _device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1671527957 -assert nopostproc +U VM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 73.xbar_smoke_large_delays.1671527957 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/73.xbar_smoke_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/73.xbar_smoke_slow_rsp.2723119942 |
| Short name | T2450 |
| Test name | |
| Test status | |
| Simulation time | 5125746586 ps |
| CPU time | 59.12 seconds |
| Started | Aug 24 06:48:47 AM UTC 24 |
| Finished | Aug 24 06:49:48 AM UTC 24 |
| Peak memory | 596080 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2723119942 -assert nopostproc +UVM_T ESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 73.xbar_smoke_slow_rsp.2723119942 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/73.xbar_smoke_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/73.xbar_smoke_zero_delays.1528947668 |
| Short name | T2439 |
| Test name | |
| Test status | |
| Simulation time | 44683062 ps |
| CPU time | 5.24 seconds |
| Started | Aug 24 06:48:43 AM UTC 24 |
| Finished | Aug 24 06:48:49 AM UTC 24 |
| Peak memory | 595632 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1528947668 -assert nopostpr oc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 73.xbar_smoke_zero_delays.1528947668 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/73.xbar_smoke_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/73.xbar_stress_all.2987940024 |
| Short name | T2472 |
| Test name | |
| Test status | |
| Simulation time | 7688337772 ps |
| CPU time | 175.13 seconds |
| Started | Aug 24 06:49:36 AM UTC 24 |
| Finished | Aug 24 06:52:33 AM UTC 24 |
| Peak memory | 597824 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2987940024 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 73.xbar_stress_all.2987940024 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/73.xbar_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/73.xbar_stress_all_with_rand_reset.3562238852 |
| Short name | T849 |
| Test name | |
| Test status | |
| Simulation time | 1090904798 ps |
| CPU time | 86.44 seconds |
| Started | Aug 24 06:49:48 AM UTC 24 |
| Finished | Aug 24 06:51:16 AM UTC 24 |
| Peak memory | 597696 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3562238852 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 73.xbar_stress_all_with_rand_reset.3562238852 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/73.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/73.xbar_stress_all_with_reset_error.3004294706 |
| Short name | T2578 |
| Test name | |
| Test status | |
| Simulation time | 29062055791 ps |
| CPU time | 769.13 seconds |
| Started | Aug 24 06:50:02 AM UTC 24 |
| Finished | Aug 24 07:02:59 AM UTC 24 |
| Peak memory | 601980 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3004294706 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 73.xbar_stress_all_with_reset_error.3004294706 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/73.xbar_stress_all_with_reset_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/73.xbar_unmapped_addr.3300804588 |
| Short name | T2453 |
| Test name | |
| Test status | |
| Simulation time | 1486372379 ps |
| CPU time | 43.26 seconds |
| Started | Aug 24 06:49:21 AM UTC 24 |
| Finished | Aug 24 06:50:05 AM UTC 24 |
| Peak memory | 597828 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3300804588 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 73.xbar_unmapped_addr.3300804588 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/73.xbar_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/74.xbar_access_same_device.4287551499 |
| Short name | T2469 |
| Test name | |
| Test status | |
| Simulation time | 2057258771 ps |
| CPU time | 60.15 seconds |
| Started | Aug 24 06:51:14 AM UTC 24 |
| Finished | Aug 24 06:52:16 AM UTC 24 |
| Peak memory | 597704 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4287551499 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 74.xbar_access_same_device.4287551499 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/74.xbar_access_same_device/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/74.xbar_access_same_device_slow_rsp.886430233 |
| Short name | T2663 |
| Test name | |
| Test status | |
| Simulation time | 105253205731 ps |
| CPU time | 1189.19 seconds |
| Started | Aug 24 06:51:23 AM UTC 24 |
| Finished | Aug 24 07:11:23 AM UTC 24 |
| Peak memory | 598752 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=886430233 -assert nopostproc +UVM_TE STNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os _regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 74.xbar_access_same_device_slow_rsp.886430233 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/74.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/74.xbar_error_and_unmapped_addr.2669535971 |
| Short name | T2471 |
| Test name | |
| Test status | |
| Simulation time | 1429293403 ps |
| CPU time | 44.37 seconds |
| Started | Aug 24 06:51:47 AM UTC 24 |
| Finished | Aug 24 06:52:33 AM UTC 24 |
| Peak memory | 597700 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2669535971 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 74.xbar_error_and_unmapped_addr.2669535971 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/74.xbar_error_and_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/74.xbar_error_random.4267829756 |
| Short name | T2466 |
| Test name | |
| Test status | |
| Simulation time | 147127227 ps |
| CPU time | 6.78 seconds |
| Started | Aug 24 06:51:43 AM UTC 24 |
| Finished | Aug 24 06:51:51 AM UTC 24 |
| Peak memory | 595640 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4267829756 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 74.xbar_error_random.4267829756 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/74.xbar_error_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/74.xbar_random.4130112780 |
| Short name | T2462 |
| Test name | |
| Test status | |
| Simulation time | 620479234 ps |
| CPU time | 37.48 seconds |
| Started | Aug 24 06:50:51 AM UTC 24 |
| Finished | Aug 24 06:51:30 AM UTC 24 |
| Peak memory | 597696 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4130112780 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 74.xbar_random.4130112780 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/74.xbar_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/74.xbar_random_large_delays.1288707721 |
| Short name | T2495 |
| Test name | |
| Test status | |
| Simulation time | 34153215187 ps |
| CPU time | 297.48 seconds |
| Started | Aug 24 06:50:54 AM UTC 24 |
| Finished | Aug 24 06:55:56 AM UTC 24 |
| Peak memory | 597824 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max _device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1288707721 -assert nopostproc +U VM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 74.xbar_random_large_delays.1288707721 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/74.xbar_random_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/74.xbar_random_slow_rsp.1402230053 |
| Short name | T2482 |
| Test name | |
| Test status | |
| Simulation time | 15213144396 ps |
| CPU time | 178.57 seconds |
| Started | Aug 24 06:50:58 AM UTC 24 |
| Finished | Aug 24 06:54:00 AM UTC 24 |
| Peak memory | 597880 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1402230053 -assert nopostproc +UVM_T ESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 74.xbar_random_slow_rsp.1402230053 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/74.xbar_random_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/74.xbar_random_zero_delays.3777163647 |
| Short name | T2461 |
| Test name | |
| Test status | |
| Simulation time | 574549528 ps |
| CPU time | 34.29 seconds |
| Started | Aug 24 06:50:53 AM UTC 24 |
| Finished | Aug 24 06:51:28 AM UTC 24 |
| Peak memory | 597768 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3777163647 -assert nopostpr oc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 74.xbar_random_zero_delays.3777163647 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/74.xbar_random_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/74.xbar_same_source.2631377249 |
| Short name | T2467 |
| Test name | |
| Test status | |
| Simulation time | 502103151 ps |
| CPU time | 26.61 seconds |
| Started | Aug 24 06:51:31 AM UTC 24 |
| Finished | Aug 24 06:51:59 AM UTC 24 |
| Peak memory | 598008 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2631377249 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 74.xbar_same_source.2631377249 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/74.xbar_same_source/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/74.xbar_smoke.1938268135 |
| Short name | T2454 |
| Test name | |
| Test status | |
| Simulation time | 182451588 ps |
| CPU time | 6.47 seconds |
| Started | Aug 24 06:50:14 AM UTC 24 |
| Finished | Aug 24 06:50:21 AM UTC 24 |
| Peak memory | 595632 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1938268135 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 8_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 74.xbar_smoke.1938268135 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/74.xbar_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/74.xbar_smoke_large_delays.13647953 |
| Short name | T2465 |
| Test name | |
| Test status | |
| Simulation time | 9340278116 ps |
| CPU time | 72.79 seconds |
| Started | Aug 24 06:50:36 AM UTC 24 |
| Finished | Aug 24 06:51:50 AM UTC 24 |
| Peak memory | 595764 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max _device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=13647953 -assert nopostproc +UVM _TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 74.xbar_smoke_large_delays.13647953 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/74.xbar_smoke_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/74.xbar_smoke_slow_rsp.349033570 |
| Short name | T2464 |
| Test name | |
| Test status | |
| Simulation time | 4715693985 ps |
| CPU time | 54.66 seconds |
| Started | Aug 24 06:50:39 AM UTC 24 |
| Finished | Aug 24 06:51:35 AM UTC 24 |
| Peak memory | 595828 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=349033570 -assert nopostproc +UVM_TE STNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 74.xbar_smoke_slow_rsp.349033570 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/74.xbar_smoke_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/74.xbar_smoke_zero_delays.921266462 |
| Short name | T2455 |
| Test name | |
| Test status | |
| Simulation time | 47293304 ps |
| CPU time | 5.27 seconds |
| Started | Aug 24 06:50:19 AM UTC 24 |
| Finished | Aug 24 06:50:25 AM UTC 24 |
| Peak memory | 595632 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=921266462 -assert nopostpro c +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 74.xbar_smoke_zero_delays.921266462 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/74.xbar_smoke_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/74.xbar_stress_all.85599054 |
| Short name | T2476 |
| Test name | |
| Test status | |
| Simulation time | 3294980649 ps |
| CPU time | 81.94 seconds |
| Started | Aug 24 06:51:50 AM UTC 24 |
| Finished | Aug 24 06:53:13 AM UTC 24 |
| Peak memory | 597772 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=85599054 -assert nopostproc +UVM_TESTNAME= xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 74.xbar_stress_all.85599054 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/74.xbar_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/74.xbar_stress_all_with_error.3071533122 |
| Short name | T2478 |
| Test name | |
| Test status | |
| Simulation time | 3331947913 ps |
| CPU time | 80.82 seconds |
| Started | Aug 24 06:52:05 AM UTC 24 |
| Finished | Aug 24 06:53:27 AM UTC 24 |
| Peak memory | 597756 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3071533122 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 74.xbar_stress_all_with_error.3071533122 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/74.xbar_stress_all_with_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/74.xbar_stress_all_with_rand_reset.3828642705 |
| Short name | T2500 |
| Test name | |
| Test status | |
| Simulation time | 5602219138 ps |
| CPU time | 243.86 seconds |
| Started | Aug 24 06:52:05 AM UTC 24 |
| Finished | Aug 24 06:56:12 AM UTC 24 |
| Peak memory | 597828 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3828642705 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 74.xbar_stress_all_with_rand_reset.3828642705 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/74.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/74.xbar_unmapped_addr.10905633 |
| Short name | T2468 |
| Test name | |
| Test status | |
| Simulation time | 179562022 ps |
| CPU time | 17.23 seconds |
| Started | Aug 24 06:51:45 AM UTC 24 |
| Finished | Aug 24 06:52:03 AM UTC 24 |
| Peak memory | 597696 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=10905633 -assert nopostproc +UVM_TESTNAME= xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 74.xbar_unmapped_addr.10905633 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/74.xbar_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/75.xbar_access_same_device.4014062663 |
| Short name | T2480 |
| Test name | |
| Test status | |
| Simulation time | 375027147 ps |
| CPU time | 22.82 seconds |
| Started | Aug 24 06:53:27 AM UTC 24 |
| Finished | Aug 24 06:53:51 AM UTC 24 |
| Peak memory | 597844 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4014062663 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 75.xbar_access_same_device.4014062663 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/75.xbar_access_same_device/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/75.xbar_access_same_device_slow_rsp.4244078752 |
| Short name | T2574 |
| Test name | |
| Test status | |
| Simulation time | 48361698112 ps |
| CPU time | 540.58 seconds |
| Started | Aug 24 06:53:35 AM UTC 24 |
| Finished | Aug 24 07:02:42 AM UTC 24 |
| Peak memory | 598080 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4244078752 -assert nopostproc +UVM_T ESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 75.xbar_access_same_device_slow_rsp.4244078752 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/75.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/75.xbar_error_and_unmapped_addr.1599477710 |
| Short name | T2485 |
| Test name | |
| Test status | |
| Simulation time | 265047397 ps |
| CPU time | 10.18 seconds |
| Started | Aug 24 06:54:08 AM UTC 24 |
| Finished | Aug 24 06:54:19 AM UTC 24 |
| Peak memory | 597700 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1599477710 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 75.xbar_error_and_unmapped_addr.1599477710 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/75.xbar_error_and_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/75.xbar_random.1028548276 |
| Short name | T2474 |
| Test name | |
| Test status | |
| Simulation time | 198540038 ps |
| CPU time | 8.47 seconds |
| Started | Aug 24 06:52:47 AM UTC 24 |
| Finished | Aug 24 06:52:58 AM UTC 24 |
| Peak memory | 595844 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1028548276 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 75.xbar_random.1028548276 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/75.xbar_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/75.xbar_random_large_delays.1222402343 |
| Short name | T2594 |
| Test name | |
| Test status | |
| Simulation time | 85962718740 ps |
| CPU time | 686.46 seconds |
| Started | Aug 24 06:53:12 AM UTC 24 |
| Finished | Aug 24 07:04:46 AM UTC 24 |
| Peak memory | 597960 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max _device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1222402343 -assert nopostproc +U VM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 75.xbar_random_large_delays.1222402343 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/75.xbar_random_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/75.xbar_random_slow_rsp.3876230596 |
| Short name | T2566 |
| Test name | |
| Test status | |
| Simulation time | 43366671342 ps |
| CPU time | 507.55 seconds |
| Started | Aug 24 06:53:24 AM UTC 24 |
| Finished | Aug 24 07:01:58 AM UTC 24 |
| Peak memory | 598132 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3876230596 -assert nopostproc +UVM_T ESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 75.xbar_random_slow_rsp.3876230596 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/75.xbar_random_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/75.xbar_random_zero_delays.402213002 |
| Short name | T2475 |
| Test name | |
| Test status | |
| Simulation time | 254726785 ps |
| CPU time | 17.56 seconds |
| Started | Aug 24 06:52:51 AM UTC 24 |
| Finished | Aug 24 06:53:10 AM UTC 24 |
| Peak memory | 597696 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=402213002 -assert nopostpro c +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 75.xbar_random_zero_delays.402213002 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/75.xbar_random_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/75.xbar_same_source.4142472806 |
| Short name | T2484 |
| Test name | |
| Test status | |
| Simulation time | 1825865167 ps |
| CPU time | 35.39 seconds |
| Started | Aug 24 06:53:41 AM UTC 24 |
| Finished | Aug 24 06:54:18 AM UTC 24 |
| Peak memory | 597696 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4142472806 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 75.xbar_same_source.4142472806 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/75.xbar_same_source/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/75.xbar_smoke.4127298476 |
| Short name | T2470 |
| Test name | |
| Test status | |
| Simulation time | 183633560 ps |
| CPU time | 6.64 seconds |
| Started | Aug 24 06:52:17 AM UTC 24 |
| Finished | Aug 24 06:52:25 AM UTC 24 |
| Peak memory | 595848 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4127298476 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 8_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 75.xbar_smoke.4127298476 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/75.xbar_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/75.xbar_smoke_large_delays.1588612579 |
| Short name | T2483 |
| Test name | |
| Test status | |
| Simulation time | 10004634104 ps |
| CPU time | 83.14 seconds |
| Started | Aug 24 06:52:39 AM UTC 24 |
| Finished | Aug 24 06:54:04 AM UTC 24 |
| Peak memory | 595828 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max _device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1588612579 -assert nopostproc +U VM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 75.xbar_smoke_large_delays.1588612579 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/75.xbar_smoke_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/75.xbar_smoke_slow_rsp.3217512887 |
| Short name | T2477 |
| Test name | |
| Test status | |
| Simulation time | 2629699948 ps |
| CPU time | 31.73 seconds |
| Started | Aug 24 06:52:47 AM UTC 24 |
| Finished | Aug 24 06:53:21 AM UTC 24 |
| Peak memory | 596024 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3217512887 -assert nopostproc +UVM_T ESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 75.xbar_smoke_slow_rsp.3217512887 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/75.xbar_smoke_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/75.xbar_smoke_zero_delays.684639645 |
| Short name | T2473 |
| Test name | |
| Test status | |
| Simulation time | 54234386 ps |
| CPU time | 5.49 seconds |
| Started | Aug 24 06:52:30 AM UTC 24 |
| Finished | Aug 24 06:52:37 AM UTC 24 |
| Peak memory | 595636 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=684639645 -assert nopostpro c +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 75.xbar_smoke_zero_delays.684639645 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/75.xbar_smoke_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/75.xbar_stress_all.1083650372 |
| Short name | T2508 |
| Test name | |
| Test status | |
| Simulation time | 5875535546 ps |
| CPU time | 143.48 seconds |
| Started | Aug 24 06:54:14 AM UTC 24 |
| Finished | Aug 24 06:56:39 AM UTC 24 |
| Peak memory | 597960 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1083650372 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 75.xbar_stress_all.1083650372 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/75.xbar_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/75.xbar_stress_all_with_error.2231748656 |
| Short name | T2522 |
| Test name | |
| Test status | |
| Simulation time | 9378282385 ps |
| CPU time | 211.11 seconds |
| Started | Aug 24 06:54:30 AM UTC 24 |
| Finished | Aug 24 06:58:05 AM UTC 24 |
| Peak memory | 598004 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2231748656 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 75.xbar_stress_all_with_error.2231748656 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/75.xbar_stress_all_with_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/75.xbar_stress_all_with_rand_reset.371627290 |
| Short name | T2490 |
| Test name | |
| Test status | |
| Simulation time | 157737955 ps |
| CPU time | 64.73 seconds |
| Started | Aug 24 06:54:18 AM UTC 24 |
| Finished | Aug 24 06:55:24 AM UTC 24 |
| Peak memory | 597872 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=371627290 -assert nopostproc +UVM_TESTNAME =xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 75.xbar_stress_all_with_rand_reset.371627290 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/75.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/75.xbar_stress_all_with_reset_error.686083350 |
| Short name | T2555 |
| Test name | |
| Test status | |
| Simulation time | 11112577019 ps |
| CPU time | 373.45 seconds |
| Started | Aug 24 06:54:32 AM UTC 24 |
| Finished | Aug 24 07:00:50 AM UTC 24 |
| Peak memory | 597816 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=686083350 -assert nopostproc +UVM_TESTNAME =xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 75.xbar_stress_all_with_reset_error.686083350 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/75.xbar_stress_all_with_reset_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/75.xbar_unmapped_addr.593351842 |
| Short name | T2486 |
| Test name | |
| Test status | |
| Simulation time | 432031547 ps |
| CPU time | 15.93 seconds |
| Started | Aug 24 06:54:06 AM UTC 24 |
| Finished | Aug 24 06:54:23 AM UTC 24 |
| Peak memory | 597832 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=593351842 -assert nopostproc +UVM_TESTNAME =xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 75.xbar_unmapped_addr.593351842 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/75.xbar_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/76.xbar_access_same_device.1449921633 |
| Short name | T2514 |
| Test name | |
| Test status | |
| Simulation time | 2284829794 ps |
| CPU time | 74.99 seconds |
| Started | Aug 24 06:56:06 AM UTC 24 |
| Finished | Aug 24 06:57:23 AM UTC 24 |
| Peak memory | 597772 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1449921633 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 76.xbar_access_same_device.1449921633 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/76.xbar_access_same_device/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/76.xbar_access_same_device_slow_rsp.1284536176 |
| Short name | T2760 |
| Test name | |
| Test status | |
| Simulation time | 118879467774 ps |
| CPU time | 1406.37 seconds |
| Started | Aug 24 06:56:09 AM UTC 24 |
| Finished | Aug 24 07:19:48 AM UTC 24 |
| Peak memory | 598788 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1284536176 -assert nopostproc +UVM_T ESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 76.xbar_access_same_device_slow_rsp.1284536176 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/76.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/76.xbar_error_and_unmapped_addr.246116654 |
| Short name | T2503 |
| Test name | |
| Test status | |
| Simulation time | 415006063 ps |
| CPU time | 14.07 seconds |
| Started | Aug 24 06:56:12 AM UTC 24 |
| Finished | Aug 24 06:56:27 AM UTC 24 |
| Peak memory | 597848 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=246116654 -assert nopostproc +UVM_TESTNAME =xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 76.xbar_error_and_unmapped_addr.246116654 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/76.xbar_error_and_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/76.xbar_error_random.3685424230 |
| Short name | T2505 |
| Test name | |
| Test status | |
| Simulation time | 311662808 ps |
| CPU time | 18.14 seconds |
| Started | Aug 24 06:56:10 AM UTC 24 |
| Finished | Aug 24 06:56:29 AM UTC 24 |
| Peak memory | 597920 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3685424230 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 76.xbar_error_random.3685424230 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/76.xbar_error_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/76.xbar_random.1327444323 |
| Short name | T2492 |
| Test name | |
| Test status | |
| Simulation time | 766687380 ps |
| CPU time | 21.1 seconds |
| Started | Aug 24 06:55:25 AM UTC 24 |
| Finished | Aug 24 06:55:48 AM UTC 24 |
| Peak memory | 597692 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1327444323 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 76.xbar_random.1327444323 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/76.xbar_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/76.xbar_random_large_delays.2811828720 |
| Short name | T2600 |
| Test name | |
| Test status | |
| Simulation time | 64689855342 ps |
| CPU time | 557.22 seconds |
| Started | Aug 24 06:56:00 AM UTC 24 |
| Finished | Aug 24 07:05:23 AM UTC 24 |
| Peak memory | 597828 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max _device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2811828720 -assert nopostproc +U VM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 76.xbar_random_large_delays.2811828720 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/76.xbar_random_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/76.xbar_random_slow_rsp.134453796 |
| Short name | T2520 |
| Test name | |
| Test status | |
| Simulation time | 9083648249 ps |
| CPU time | 110.81 seconds |
| Started | Aug 24 06:56:01 AM UTC 24 |
| Finished | Aug 24 06:57:54 AM UTC 24 |
| Peak memory | 597956 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=134453796 -assert nopostproc +UVM_TE STNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 76.xbar_random_slow_rsp.134453796 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/76.xbar_random_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/76.xbar_random_zero_delays.2406348135 |
| Short name | T2493 |
| Test name | |
| Test status | |
| Simulation time | 170547972 ps |
| CPU time | 12.91 seconds |
| Started | Aug 24 06:55:38 AM UTC 24 |
| Finished | Aug 24 06:55:52 AM UTC 24 |
| Peak memory | 597760 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2406348135 -assert nopostpr oc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 76.xbar_random_zero_delays.2406348135 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/76.xbar_random_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/76.xbar_same_source.3806225946 |
| Short name | T2506 |
| Test name | |
| Test status | |
| Simulation time | 919727348 ps |
| CPU time | 19.98 seconds |
| Started | Aug 24 06:56:09 AM UTC 24 |
| Finished | Aug 24 06:56:30 AM UTC 24 |
| Peak memory | 597940 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3806225946 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 76.xbar_same_source.3806225946 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/76.xbar_same_source/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/76.xbar_smoke.2606969111 |
| Short name | T2487 |
| Test name | |
| Test status | |
| Simulation time | 214906122 ps |
| CPU time | 7.06 seconds |
| Started | Aug 24 06:54:33 AM UTC 24 |
| Finished | Aug 24 06:54:41 AM UTC 24 |
| Peak memory | 595876 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2606969111 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 8_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 76.xbar_smoke.2606969111 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/76.xbar_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/76.xbar_smoke_large_delays.1323083087 |
| Short name | T2501 |
| Test name | |
| Test status | |
| Simulation time | 8862367938 ps |
| CPU time | 76.34 seconds |
| Started | Aug 24 06:54:55 AM UTC 24 |
| Finished | Aug 24 06:56:13 AM UTC 24 |
| Peak memory | 596020 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max _device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1323083087 -assert nopostproc +U VM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 76.xbar_smoke_large_delays.1323083087 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/76.xbar_smoke_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/76.xbar_smoke_slow_rsp.3774464654 |
| Short name | T2498 |
| Test name | |
| Test status | |
| Simulation time | 5412546175 ps |
| CPU time | 64 seconds |
| Started | Aug 24 06:54:57 AM UTC 24 |
| Finished | Aug 24 06:56:02 AM UTC 24 |
| Peak memory | 595768 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3774464654 -assert nopostproc +UVM_T ESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 76.xbar_smoke_slow_rsp.3774464654 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/76.xbar_smoke_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/76.xbar_smoke_zero_delays.4259771810 |
| Short name | T2488 |
| Test name | |
| Test status | |
| Simulation time | 42077555 ps |
| CPU time | 4.73 seconds |
| Started | Aug 24 06:54:37 AM UTC 24 |
| Finished | Aug 24 06:54:43 AM UTC 24 |
| Peak memory | 595700 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4259771810 -assert nopostpr oc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 76.xbar_smoke_zero_delays.4259771810 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/76.xbar_smoke_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/76.xbar_stress_all.2715618148 |
| Short name | T2530 |
| Test name | |
| Test status | |
| Simulation time | 2495378529 ps |
| CPU time | 151.31 seconds |
| Started | Aug 24 06:56:17 AM UTC 24 |
| Finished | Aug 24 06:58:51 AM UTC 24 |
| Peak memory | 597760 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2715618148 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 76.xbar_stress_all.2715618148 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/76.xbar_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/76.xbar_stress_all_with_error.4264106113 |
| Short name | T2524 |
| Test name | |
| Test status | |
| Simulation time | 5175689345 ps |
| CPU time | 105.58 seconds |
| Started | Aug 24 06:56:26 AM UTC 24 |
| Finished | Aug 24 06:58:13 AM UTC 24 |
| Peak memory | 598080 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4264106113 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 76.xbar_stress_all_with_error.4264106113 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/76.xbar_stress_all_with_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/76.xbar_stress_all_with_rand_reset.761563023 |
| Short name | T2536 |
| Test name | |
| Test status | |
| Simulation time | 511673421 ps |
| CPU time | 164.71 seconds |
| Started | Aug 24 06:56:22 AM UTC 24 |
| Finished | Aug 24 06:59:09 AM UTC 24 |
| Peak memory | 597756 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=761563023 -assert nopostproc +UVM_TESTNAME =xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 76.xbar_stress_all_with_rand_reset.761563023 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/76.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/76.xbar_stress_all_with_reset_error.4275795646 |
| Short name | T2517 |
| Test name | |
| Test status | |
| Simulation time | 367359889 ps |
| CPU time | 72.22 seconds |
| Started | Aug 24 06:56:27 AM UTC 24 |
| Finished | Aug 24 06:57:41 AM UTC 24 |
| Peak memory | 597696 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4275795646 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 76.xbar_stress_all_with_reset_error.4275795646 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/76.xbar_stress_all_with_reset_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/76.xbar_unmapped_addr.1776813961 |
| Short name | T2504 |
| Test name | |
| Test status | |
| Simulation time | 401307361 ps |
| CPU time | 14.49 seconds |
| Started | Aug 24 06:56:12 AM UTC 24 |
| Finished | Aug 24 06:56:28 AM UTC 24 |
| Peak memory | 597692 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1776813961 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 76.xbar_unmapped_addr.1776813961 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/76.xbar_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/77.xbar_access_same_device.3903941352 |
| Short name | T2519 |
| Test name | |
| Test status | |
| Simulation time | 1658525306 ps |
| CPU time | 42.95 seconds |
| Started | Aug 24 06:57:01 AM UTC 24 |
| Finished | Aug 24 06:57:46 AM UTC 24 |
| Peak memory | 597768 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3903941352 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 77.xbar_access_same_device.3903941352 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/77.xbar_access_same_device/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/77.xbar_access_same_device_slow_rsp.4072508452 |
| Short name | T2784 |
| Test name | |
| Test status | |
| Simulation time | 129647032831 ps |
| CPU time | 1466.89 seconds |
| Started | Aug 24 06:57:05 AM UTC 24 |
| Finished | Aug 24 07:21:45 AM UTC 24 |
| Peak memory | 598788 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4072508452 -assert nopostproc +UVM_T ESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 77.xbar_access_same_device_slow_rsp.4072508452 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/77.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/77.xbar_error_and_unmapped_addr.2287291539 |
| Short name | T2525 |
| Test name | |
| Test status | |
| Simulation time | 1337310374 ps |
| CPU time | 33.94 seconds |
| Started | Aug 24 06:57:40 AM UTC 24 |
| Finished | Aug 24 06:58:15 AM UTC 24 |
| Peak memory | 597820 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2287291539 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 77.xbar_error_and_unmapped_addr.2287291539 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/77.xbar_error_and_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/77.xbar_error_random.1993284031 |
| Short name | T2521 |
| Test name | |
| Test status | |
| Simulation time | 395039926 ps |
| CPU time | 21.74 seconds |
| Started | Aug 24 06:57:34 AM UTC 24 |
| Finished | Aug 24 06:57:57 AM UTC 24 |
| Peak memory | 598052 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1993284031 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 77.xbar_error_random.1993284031 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/77.xbar_error_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/77.xbar_random.3525862967 |
| Short name | T2512 |
| Test name | |
| Test status | |
| Simulation time | 224825294 ps |
| CPU time | 15.13 seconds |
| Started | Aug 24 06:56:44 AM UTC 24 |
| Finished | Aug 24 06:57:00 AM UTC 24 |
| Peak memory | 597832 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3525862967 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 77.xbar_random.3525862967 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/77.xbar_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/77.xbar_random_large_delays.3753131607 |
| Short name | T2597 |
| Test name | |
| Test status | |
| Simulation time | 59506612983 ps |
| CPU time | 485.59 seconds |
| Started | Aug 24 06:56:53 AM UTC 24 |
| Finished | Aug 24 07:05:04 AM UTC 24 |
| Peak memory | 597820 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max _device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3753131607 -assert nopostproc +U VM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 77.xbar_random_large_delays.3753131607 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/77.xbar_random_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/77.xbar_random_slow_rsp.1956092195 |
| Short name | T2624 |
| Test name | |
| Test status | |
| Simulation time | 56666645226 ps |
| CPU time | 645.7 seconds |
| Started | Aug 24 06:56:56 AM UTC 24 |
| Finished | Aug 24 07:07:49 AM UTC 24 |
| Peak memory | 598160 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1956092195 -assert nopostproc +UVM_T ESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 77.xbar_random_slow_rsp.1956092195 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/77.xbar_random_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/77.xbar_random_zero_delays.374247261 |
| Short name | T2513 |
| Test name | |
| Test status | |
| Simulation time | 517342573 ps |
| CPU time | 31.21 seconds |
| Started | Aug 24 06:56:47 AM UTC 24 |
| Finished | Aug 24 06:57:20 AM UTC 24 |
| Peak memory | 597760 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=374247261 -assert nopostpro c +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 77.xbar_random_zero_delays.374247261 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/77.xbar_random_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/77.xbar_same_source.3809731156 |
| Short name | T2515 |
| Test name | |
| Test status | |
| Simulation time | 119518263 ps |
| CPU time | 9.34 seconds |
| Started | Aug 24 06:57:15 AM UTC 24 |
| Finished | Aug 24 06:57:25 AM UTC 24 |
| Peak memory | 597692 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3809731156 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 77.xbar_same_source.3809731156 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/77.xbar_same_source/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/77.xbar_smoke.3000385565 |
| Short name | T2509 |
| Test name | |
| Test status | |
| Simulation time | 265512709 ps |
| CPU time | 7.74 seconds |
| Started | Aug 24 06:56:33 AM UTC 24 |
| Finished | Aug 24 06:56:42 AM UTC 24 |
| Peak memory | 595696 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3000385565 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 8_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 77.xbar_smoke.3000385565 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/77.xbar_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/77.xbar_smoke_large_delays.1432048811 |
| Short name | T2518 |
| Test name | |
| Test status | |
| Simulation time | 7442566728 ps |
| CPU time | 60.45 seconds |
| Started | Aug 24 06:56:42 AM UTC 24 |
| Finished | Aug 24 06:57:44 AM UTC 24 |
| Peak memory | 595764 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max _device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1432048811 -assert nopostproc +U VM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 77.xbar_smoke_large_delays.1432048811 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/77.xbar_smoke_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/77.xbar_smoke_slow_rsp.95998096 |
| Short name | T2516 |
| Test name | |
| Test status | |
| Simulation time | 4167334600 ps |
| CPU time | 48.65 seconds |
| Started | Aug 24 06:56:43 AM UTC 24 |
| Finished | Aug 24 06:57:33 AM UTC 24 |
| Peak memory | 595764 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=95998096 -assert nopostproc +UVM_TES TNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 77.xbar_smoke_slow_rsp.95998096 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/77.xbar_smoke_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/77.xbar_smoke_zero_delays.2548128527 |
| Short name | T2510 |
| Test name | |
| Test status | |
| Simulation time | 39563486 ps |
| CPU time | 4.73 seconds |
| Started | Aug 24 06:56:41 AM UTC 24 |
| Finished | Aug 24 06:56:47 AM UTC 24 |
| Peak memory | 595856 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2548128527 -assert nopostpr oc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 77.xbar_smoke_zero_delays.2548128527 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/77.xbar_smoke_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/77.xbar_stress_all.480767557 |
| Short name | T2534 |
| Test name | |
| Test status | |
| Simulation time | 1281125537 ps |
| CPU time | 75.99 seconds |
| Started | Aug 24 06:57:47 AM UTC 24 |
| Finished | Aug 24 06:59:05 AM UTC 24 |
| Peak memory | 597952 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=480767557 -assert nopostproc +UVM_TESTNAME =xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 77.xbar_stress_all.480767557 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/77.xbar_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/77.xbar_stress_all_with_error.606057526 |
| Short name | T2549 |
| Test name | |
| Test status | |
| Simulation time | 5799147913 ps |
| CPU time | 135.26 seconds |
| Started | Aug 24 06:57:58 AM UTC 24 |
| Finished | Aug 24 07:00:15 AM UTC 24 |
| Peak memory | 597824 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=606057526 -assert nopostproc +UVM_TESTNAME =xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 77.xbar_stress_all_with_error.606057526 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/77.xbar_stress_all_with_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/77.xbar_stress_all_with_rand_reset.2170331346 |
| Short name | T2553 |
| Test name | |
| Test status | |
| Simulation time | 466832345 ps |
| CPU time | 167.77 seconds |
| Started | Aug 24 06:57:55 AM UTC 24 |
| Finished | Aug 24 07:00:45 AM UTC 24 |
| Peak memory | 598040 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2170331346 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 77.xbar_stress_all_with_rand_reset.2170331346 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/77.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/77.xbar_stress_all_with_reset_error.3498080635 |
| Short name | T2613 |
| Test name | |
| Test status | |
| Simulation time | 7158793673 ps |
| CPU time | 511.53 seconds |
| Started | Aug 24 06:58:00 AM UTC 24 |
| Finished | Aug 24 07:06:37 AM UTC 24 |
| Peak memory | 602196 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3498080635 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 77.xbar_stress_all_with_reset_error.3498080635 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/77.xbar_stress_all_with_reset_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/77.xbar_unmapped_addr.815039880 |
| Short name | T2523 |
| Test name | |
| Test status | |
| Simulation time | 1148783533 ps |
| CPU time | 32.83 seconds |
| Started | Aug 24 06:57:38 AM UTC 24 |
| Finished | Aug 24 06:58:12 AM UTC 24 |
| Peak memory | 597900 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=815039880 -assert nopostproc +UVM_TESTNAME =xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 77.xbar_unmapped_addr.815039880 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/77.xbar_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/78.xbar_access_same_device.2344561716 |
| Short name | T2533 |
| Test name | |
| Test status | |
| Simulation time | 344200903 ps |
| CPU time | 19.03 seconds |
| Started | Aug 24 06:58:40 AM UTC 24 |
| Finished | Aug 24 06:59:00 AM UTC 24 |
| Peak memory | 597924 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2344561716 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 78.xbar_access_same_device.2344561716 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/78.xbar_access_same_device/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/78.xbar_access_same_device_slow_rsp.2106952774 |
| Short name | T2725 |
| Test name | |
| Test status | |
| Simulation time | 93686796236 ps |
| CPU time | 1074.08 seconds |
| Started | Aug 24 06:58:55 AM UTC 24 |
| Finished | Aug 24 07:16:59 AM UTC 24 |
| Peak memory | 597820 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2106952774 -assert nopostproc +UVM_T ESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 78.xbar_access_same_device_slow_rsp.2106952774 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/78.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/78.xbar_error_and_unmapped_addr.2166367310 |
| Short name | T2540 |
| Test name | |
| Test status | |
| Simulation time | 283178107 ps |
| CPU time | 11.31 seconds |
| Started | Aug 24 06:59:14 AM UTC 24 |
| Finished | Aug 24 06:59:26 AM UTC 24 |
| Peak memory | 597760 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2166367310 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 78.xbar_error_and_unmapped_addr.2166367310 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/78.xbar_error_and_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/78.xbar_error_random.2762900997 |
| Short name | T2543 |
| Test name | |
| Test status | |
| Simulation time | 1346208282 ps |
| CPU time | 30.18 seconds |
| Started | Aug 24 06:59:12 AM UTC 24 |
| Finished | Aug 24 06:59:43 AM UTC 24 |
| Peak memory | 597752 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2762900997 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 78.xbar_error_random.2762900997 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/78.xbar_error_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/78.xbar_random.4063853562 |
| Short name | T2529 |
| Test name | |
| Test status | |
| Simulation time | 393066076 ps |
| CPU time | 11.78 seconds |
| Started | Aug 24 06:58:27 AM UTC 24 |
| Finished | Aug 24 06:58:40 AM UTC 24 |
| Peak memory | 597892 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4063853562 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 78.xbar_random.4063853562 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/78.xbar_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/78.xbar_random_large_delays.1885656794 |
| Short name | T2618 |
| Test name | |
| Test status | |
| Simulation time | 63688226397 ps |
| CPU time | 503.54 seconds |
| Started | Aug 24 06:58:31 AM UTC 24 |
| Finished | Aug 24 07:07:01 AM UTC 24 |
| Peak memory | 597820 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max _device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1885656794 -assert nopostproc +U VM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 78.xbar_random_large_delays.1885656794 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/78.xbar_random_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/78.xbar_random_slow_rsp.2716906064 |
| Short name | T2570 |
| Test name | |
| Test status | |
| Simulation time | 20385731765 ps |
| CPU time | 235.21 seconds |
| Started | Aug 24 06:58:31 AM UTC 24 |
| Finished | Aug 24 07:02:30 AM UTC 24 |
| Peak memory | 597828 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2716906064 -assert nopostproc +UVM_T ESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 78.xbar_random_slow_rsp.2716906064 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/78.xbar_random_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/78.xbar_random_zero_delays.2821470273 |
| Short name | T2531 |
| Test name | |
| Test status | |
| Simulation time | 460843309 ps |
| CPU time | 26.7 seconds |
| Started | Aug 24 06:58:29 AM UTC 24 |
| Finished | Aug 24 06:58:57 AM UTC 24 |
| Peak memory | 597696 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2821470273 -assert nopostpr oc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 78.xbar_random_zero_delays.2821470273 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/78.xbar_random_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/78.xbar_same_source.3834477558 |
| Short name | T2537 |
| Test name | |
| Test status | |
| Simulation time | 320546415 ps |
| CPU time | 9.06 seconds |
| Started | Aug 24 06:59:05 AM UTC 24 |
| Finished | Aug 24 06:59:15 AM UTC 24 |
| Peak memory | 597744 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3834477558 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 78.xbar_same_source.3834477558 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/78.xbar_same_source/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/78.xbar_smoke.3727116056 |
| Short name | T2526 |
| Test name | |
| Test status | |
| Simulation time | 240885210 ps |
| CPU time | 7.7 seconds |
| Started | Aug 24 06:58:08 AM UTC 24 |
| Finished | Aug 24 06:58:17 AM UTC 24 |
| Peak memory | 595704 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3727116056 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 8_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 78.xbar_smoke.3727116056 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/78.xbar_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/78.xbar_smoke_large_delays.215893182 |
| Short name | T2538 |
| Test name | |
| Test status | |
| Simulation time | 7961153162 ps |
| CPU time | 64.13 seconds |
| Started | Aug 24 06:58:19 AM UTC 24 |
| Finished | Aug 24 06:59:25 AM UTC 24 |
| Peak memory | 595768 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max _device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=215893182 -assert nopostproc +UV M_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 78.xbar_smoke_large_delays.215893182 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/78.xbar_smoke_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/78.xbar_smoke_slow_rsp.2220254009 |
| Short name | T2541 |
| Test name | |
| Test status | |
| Simulation time | 5711440478 ps |
| CPU time | 66.46 seconds |
| Started | Aug 24 06:58:26 AM UTC 24 |
| Finished | Aug 24 06:59:35 AM UTC 24 |
| Peak memory | 595896 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2220254009 -assert nopostproc +UVM_T ESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 78.xbar_smoke_slow_rsp.2220254009 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/78.xbar_smoke_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/78.xbar_smoke_zero_delays.1612942959 |
| Short name | T2527 |
| Test name | |
| Test status | |
| Simulation time | 45295555 ps |
| CPU time | 5.06 seconds |
| Started | Aug 24 06:58:11 AM UTC 24 |
| Finished | Aug 24 06:58:17 AM UTC 24 |
| Peak memory | 595856 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1612942959 -assert nopostpr oc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 78.xbar_smoke_zero_delays.1612942959 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/78.xbar_smoke_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/78.xbar_stress_all.3957710372 |
| Short name | T2539 |
| Test name | |
| Test status | |
| Simulation time | 58053187 ps |
| CPU time | 5.08 seconds |
| Started | Aug 24 06:59:19 AM UTC 24 |
| Finished | Aug 24 06:59:25 AM UTC 24 |
| Peak memory | 595696 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3957710372 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 78.xbar_stress_all.3957710372 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/78.xbar_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/78.xbar_stress_all_with_error.35778558 |
| Short name | T2557 |
| Test name | |
| Test status | |
| Simulation time | 1993788651 ps |
| CPU time | 93.34 seconds |
| Started | Aug 24 06:59:23 AM UTC 24 |
| Finished | Aug 24 07:00:58 AM UTC 24 |
| Peak memory | 597844 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=35778558 -assert nopostproc +UVM_TESTNAME= xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 78.xbar_stress_all_with_error.35778558 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/78.xbar_stress_all_with_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/78.xbar_stress_all_with_rand_reset.231905252 |
| Short name | T2556 |
| Test name | |
| Test status | |
| Simulation time | 2165089685 ps |
| CPU time | 94.18 seconds |
| Started | Aug 24 06:59:20 AM UTC 24 |
| Finished | Aug 24 07:00:56 AM UTC 24 |
| Peak memory | 597756 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=231905252 -assert nopostproc +UVM_TESTNAME =xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 78.xbar_stress_all_with_rand_reset.231905252 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/78.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/78.xbar_stress_all_with_reset_error.4100397411 |
| Short name | T2564 |
| Test name | |
| Test status | |
| Simulation time | 385733767 ps |
| CPU time | 124.16 seconds |
| Started | Aug 24 06:59:29 AM UTC 24 |
| Finished | Aug 24 07:01:35 AM UTC 24 |
| Peak memory | 597696 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4100397411 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 78.xbar_stress_all_with_reset_error.4100397411 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/78.xbar_stress_all_with_reset_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/78.xbar_unmapped_addr.638867187 |
| Short name | T2545 |
| Test name | |
| Test status | |
| Simulation time | 1033668473 ps |
| CPU time | 32.43 seconds |
| Started | Aug 24 06:59:14 AM UTC 24 |
| Finished | Aug 24 06:59:47 AM UTC 24 |
| Peak memory | 597692 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=638867187 -assert nopostproc +UVM_TESTNAME =xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 78.xbar_unmapped_addr.638867187 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/78.xbar_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/79.xbar_access_same_device.971826812 |
| Short name | T2552 |
| Test name | |
| Test status | |
| Simulation time | 672617690 ps |
| CPU time | 37.36 seconds |
| Started | Aug 24 07:00:02 AM UTC 24 |
| Finished | Aug 24 07:00:45 AM UTC 24 |
| Peak memory | 597844 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=971826812 -assert nopostproc +UVM_TESTNAME =xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 79.xbar_access_same_device.971826812 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/79.xbar_access_same_device/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/79.xbar_access_same_device_slow_rsp.3521166877 |
| Short name | T2858 |
| Test name | |
| Test status | |
| Simulation time | 142154043698 ps |
| CPU time | 1634.64 seconds |
| Started | Aug 24 07:00:21 AM UTC 24 |
| Finished | Aug 24 07:27:51 AM UTC 24 |
| Peak memory | 599044 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3521166877 -assert nopostproc +UVM_T ESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 79.xbar_access_same_device_slow_rsp.3521166877 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/79.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/79.xbar_error_and_unmapped_addr.3361315190 |
| Short name | T2563 |
| Test name | |
| Test status | |
| Simulation time | 1232059050 ps |
| CPU time | 33.14 seconds |
| Started | Aug 24 07:01:00 AM UTC 24 |
| Finished | Aug 24 07:01:34 AM UTC 24 |
| Peak memory | 597836 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3361315190 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 79.xbar_error_and_unmapped_addr.3361315190 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/79.xbar_error_and_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/79.xbar_error_random.874932387 |
| Short name | T2551 |
| Test name | |
| Test status | |
| Simulation time | 509652033 ps |
| CPU time | 13.85 seconds |
| Started | Aug 24 07:00:30 AM UTC 24 |
| Finished | Aug 24 07:00:45 AM UTC 24 |
| Peak memory | 597760 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=874932387 -assert nopostproc +UVM_TESTNAME =xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 79.xbar_error_random.874932387 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/79.xbar_error_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/79.xbar_random.3441371744 |
| Short name | T2547 |
| Test name | |
| Test status | |
| Simulation time | 224864241 ps |
| CPU time | 8.81 seconds |
| Started | Aug 24 06:59:55 AM UTC 24 |
| Finished | Aug 24 07:00:06 AM UTC 24 |
| Peak memory | 597896 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3441371744 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 79.xbar_random.3441371744 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/79.xbar_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/79.xbar_random_large_delays.284931023 |
| Short name | T2691 |
| Test name | |
| Test status | |
| Simulation time | 100945877312 ps |
| CPU time | 827.56 seconds |
| Started | Aug 24 07:00:01 AM UTC 24 |
| Finished | Aug 24 07:14:02 AM UTC 24 |
| Peak memory | 598088 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max _device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=284931023 -assert nopostproc +UV M_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 79.xbar_random_large_delays.284931023 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/79.xbar_random_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/79.xbar_random_slow_rsp.2310272107 |
| Short name | T2577 |
| Test name | |
| Test status | |
| Simulation time | 14003337737 ps |
| CPU time | 165.84 seconds |
| Started | Aug 24 07:00:01 AM UTC 24 |
| Finished | Aug 24 07:02:55 AM UTC 24 |
| Peak memory | 598136 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2310272107 -assert nopostproc +UVM_T ESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 79.xbar_random_slow_rsp.2310272107 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/79.xbar_random_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/79.xbar_random_zero_delays.1251136880 |
| Short name | T2548 |
| Test name | |
| Test status | |
| Simulation time | 140196435 ps |
| CPU time | 10.5 seconds |
| Started | Aug 24 06:59:57 AM UTC 24 |
| Finished | Aug 24 07:00:09 AM UTC 24 |
| Peak memory | 597968 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1251136880 -assert nopostpr oc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 79.xbar_random_zero_delays.1251136880 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/79.xbar_random_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/79.xbar_same_source.3631934027 |
| Short name | T2554 |
| Test name | |
| Test status | |
| Simulation time | 430107922 ps |
| CPU time | 22.62 seconds |
| Started | Aug 24 07:00:24 AM UTC 24 |
| Finished | Aug 24 07:00:47 AM UTC 24 |
| Peak memory | 597752 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3631934027 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 79.xbar_same_source.3631934027 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/79.xbar_same_source/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/79.xbar_smoke.568080097 |
| Short name | T2546 |
| Test name | |
| Test status | |
| Simulation time | 220085624 ps |
| CPU time | 7.02 seconds |
| Started | Aug 24 06:59:40 AM UTC 24 |
| Finished | Aug 24 06:59:48 AM UTC 24 |
| Peak memory | 595948 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=568080097 -assert nopostproc +UVM_TESTNAME =xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08 _22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 79.xbar_smoke.568080097 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/79.xbar_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/79.xbar_smoke_large_delays.539939650 |
| Short name | T2559 |
| Test name | |
| Test status | |
| Simulation time | 9840091282 ps |
| CPU time | 81.17 seconds |
| Started | Aug 24 06:59:40 AM UTC 24 |
| Finished | Aug 24 07:01:03 AM UTC 24 |
| Peak memory | 595764 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max _device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=539939650 -assert nopostproc +UV M_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 79.xbar_smoke_large_delays.539939650 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/79.xbar_smoke_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/79.xbar_smoke_slow_rsp.4127195793 |
| Short name | T2550 |
| Test name | |
| Test status | |
| Simulation time | 4089957333 ps |
| CPU time | 49.76 seconds |
| Started | Aug 24 06:59:49 AM UTC 24 |
| Finished | Aug 24 07:00:41 AM UTC 24 |
| Peak memory | 595704 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4127195793 -assert nopostproc +UVM_T ESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 79.xbar_smoke_slow_rsp.4127195793 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/79.xbar_smoke_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/79.xbar_smoke_zero_delays.2872045191 |
| Short name | T2544 |
| Test name | |
| Test status | |
| Simulation time | 50994691 ps |
| CPU time | 5.39 seconds |
| Started | Aug 24 06:59:40 AM UTC 24 |
| Finished | Aug 24 06:59:46 AM UTC 24 |
| Peak memory | 595856 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2872045191 -assert nopostpr oc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 79.xbar_smoke_zero_delays.2872045191 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/79.xbar_smoke_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/79.xbar_stress_all.3315029491 |
| Short name | T2569 |
| Test name | |
| Test status | |
| Simulation time | 1162663769 ps |
| CPU time | 74.95 seconds |
| Started | Aug 24 07:01:00 AM UTC 24 |
| Finished | Aug 24 07:02:17 AM UTC 24 |
| Peak memory | 597700 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3315029491 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 79.xbar_stress_all.3315029491 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/79.xbar_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/79.xbar_stress_all_with_error.1363309046 |
| Short name | T2583 |
| Test name | |
| Test status | |
| Simulation time | 6192945101 ps |
| CPU time | 142.06 seconds |
| Started | Aug 24 07:01:01 AM UTC 24 |
| Finished | Aug 24 07:03:25 AM UTC 24 |
| Peak memory | 597972 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1363309046 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 79.xbar_stress_all_with_error.1363309046 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/79.xbar_stress_all_with_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/79.xbar_stress_all_with_rand_reset.1605490182 |
| Short name | T853 |
| Test name | |
| Test status | |
| Simulation time | 326093829 ps |
| CPU time | 124.35 seconds |
| Started | Aug 24 07:01:00 AM UTC 24 |
| Finished | Aug 24 07:03:07 AM UTC 24 |
| Peak memory | 597692 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1605490182 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 79.xbar_stress_all_with_rand_reset.1605490182 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/79.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/79.xbar_stress_all_with_reset_error.879759411 |
| Short name | T2584 |
| Test name | |
| Test status | |
| Simulation time | 534506739 ps |
| CPU time | 166.68 seconds |
| Started | Aug 24 07:01:04 AM UTC 24 |
| Finished | Aug 24 07:03:53 AM UTC 24 |
| Peak memory | 598008 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=879759411 -assert nopostproc +UVM_TESTNAME =xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 79.xbar_stress_all_with_reset_error.879759411 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/79.xbar_stress_all_with_reset_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/79.xbar_unmapped_addr.873867320 |
| Short name | T2562 |
| Test name | |
| Test status | |
| Simulation time | 728967938 ps |
| CPU time | 25.16 seconds |
| Started | Aug 24 07:00:55 AM UTC 24 |
| Finished | Aug 24 07:01:21 AM UTC 24 |
| Peak memory | 597696 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=873867320 -assert nopostproc +UVM_TESTNAME =xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 79.xbar_unmapped_addr.873867320 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/79.xbar_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/8.chip_csr_mem_rw_with_rand_reset.3078082234 |
| Short name | T545 |
| Test name | |
| Test status | |
| Simulation time | 7306169468 ps |
| CPU time | 400.82 seconds |
| Started | Aug 24 04:24:18 AM UTC 24 |
| Finished | Aug 24 04:31:03 AM UTC 24 |
| Peak memory | 664532 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000 000000 +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/too ls/sim.tcl +ntb_random_seed=3078082234 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/nul l -cm_name 8.chip_csr_mem_rw_with_rand_reset.3078082234 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/8.chip_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/8.chip_csr_rw.1616430476 |
| Short name | T1411 |
| Test name | |
| Test status | |
| Simulation time | 5621404985 ps |
| CPU time | 500.15 seconds |
| Started | Aug 24 04:24:06 AM UTC 24 |
| Finished | Aug 24 04:32:32 AM UTC 24 |
| Peak memory | 617244 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +stub_cpu=1 +cdc_instrumentation_ena bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1616430476 -assert nopost proc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os _regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.chip_csr_rw.1616430476 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/8.chip_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/8.chip_same_csr_outstanding.2791586889 |
| Short name | T407 |
| Test name | |
| Test status | |
| Simulation time | 15222259758 ps |
| CPU time | 1035.18 seconds |
| Started | Aug 24 04:22:03 AM UTC 24 |
| Finished | Aug 24 04:39:30 AM UTC 24 |
| Peak memory | 613444 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +test_timeout_ns=120_000_000 +run_same_csr_outstanding +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim .tcl +ntb_random_seed=2791586889 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_ name 8.chip_same_csr_outstanding.2791586889 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/8.chip_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/8.xbar_access_same_device.2416923201 |
| Short name | T784 |
| Test name | |
| Test status | |
| Simulation time | 217607299 ps |
| CPU time | 21.12 seconds |
| Started | Aug 24 04:22:59 AM UTC 24 |
| Finished | Aug 24 04:23:21 AM UTC 24 |
| Peak memory | 597700 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2416923201 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.xbar_access_same_device.2416923201 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/8.xbar_access_same_device/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/8.xbar_access_same_device_slow_rsp.1813435975 |
| Short name | T787 |
| Test name | |
| Test status | |
| Simulation time | 2445803415 ps |
| CPU time | 31.55 seconds |
| Started | Aug 24 04:23:09 AM UTC 24 |
| Finished | Aug 24 04:23:42 AM UTC 24 |
| Peak memory | 595776 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1813435975 -assert nopostproc +UVM_T ESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.xbar_access_same_device_slow_rsp.1813435975 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/8.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/8.xbar_error_random.2238741110 |
| Short name | T1387 |
| Test name | |
| Test status | |
| Simulation time | 502016967 ps |
| CPU time | 32.2 seconds |
| Started | Aug 24 04:23:30 AM UTC 24 |
| Finished | Aug 24 04:24:04 AM UTC 24 |
| Peak memory | 597696 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2238741110 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.xbar_error_random.2238741110 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/8.xbar_error_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/8.xbar_random.3982989356 |
| Short name | T1384 |
| Test name | |
| Test status | |
| Simulation time | 149920863 ps |
| CPU time | 6.25 seconds |
| Started | Aug 24 04:22:36 AM UTC 24 |
| Finished | Aug 24 04:22:43 AM UTC 24 |
| Peak memory | 595644 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3982989356 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.xbar_random.3982989356 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/8.xbar_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/8.xbar_random_large_delays.1252239789 |
| Short name | T533 |
| Test name | |
| Test status | |
| Simulation time | 14218401831 ps |
| CPU time | 116.86 seconds |
| Started | Aug 24 04:22:39 AM UTC 24 |
| Finished | Aug 24 04:24:38 AM UTC 24 |
| Peak memory | 597820 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max _device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1252239789 -assert nopostproc +U VM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.xbar_random_large_delays.1252239789 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/8.xbar_random_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/8.xbar_random_slow_rsp.2086398679 |
| Short name | T1401 |
| Test name | |
| Test status | |
| Simulation time | 36886116802 ps |
| CPU time | 430.18 seconds |
| Started | Aug 24 04:22:57 AM UTC 24 |
| Finished | Aug 24 04:30:12 AM UTC 24 |
| Peak memory | 597824 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2086398679 -assert nopostproc +UVM_T ESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.xbar_random_slow_rsp.2086398679 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/8.xbar_random_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/8.xbar_random_zero_delays.482614615 |
| Short name | T592 |
| Test name | |
| Test status | |
| Simulation time | 578342369 ps |
| CPU time | 38.17 seconds |
| Started | Aug 24 04:22:37 AM UTC 24 |
| Finished | Aug 24 04:23:16 AM UTC 24 |
| Peak memory | 597692 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=482614615 -assert nopostpro c +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.xbar_random_zero_delays.482614615 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/8.xbar_random_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/8.xbar_same_source.4200030084 |
| Short name | T583 |
| Test name | |
| Test status | |
| Simulation time | 403397981 ps |
| CPU time | 22.07 seconds |
| Started | Aug 24 04:23:23 AM UTC 24 |
| Finished | Aug 24 04:23:47 AM UTC 24 |
| Peak memory | 597696 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4200030084 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.xbar_same_source.4200030084 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/8.xbar_same_source/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/8.xbar_smoke.2695988410 |
| Short name | T1382 |
| Test name | |
| Test status | |
| Simulation time | 45019773 ps |
| CPU time | 5.06 seconds |
| Started | Aug 24 04:22:12 AM UTC 24 |
| Finished | Aug 24 04:22:18 AM UTC 24 |
| Peak memory | 595628 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2695988410 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 8_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.xbar_smoke.2695988410 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/8.xbar_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/8.xbar_smoke_large_delays.1868748955 |
| Short name | T1386 |
| Test name | |
| Test status | |
| Simulation time | 10481257869 ps |
| CPU time | 88.45 seconds |
| Started | Aug 24 04:22:22 AM UTC 24 |
| Finished | Aug 24 04:23:52 AM UTC 24 |
| Peak memory | 595896 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max _device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1868748955 -assert nopostproc +U VM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.xbar_smoke_large_delays.1868748955 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/8.xbar_smoke_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/8.xbar_smoke_slow_rsp.1724031335 |
| Short name | T615 |
| Test name | |
| Test status | |
| Simulation time | 4858913031 ps |
| CPU time | 59.41 seconds |
| Started | Aug 24 04:22:32 AM UTC 24 |
| Finished | Aug 24 04:23:33 AM UTC 24 |
| Peak memory | 596020 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1724031335 -assert nopostproc +UVM_T ESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.xbar_smoke_slow_rsp.1724031335 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/8.xbar_smoke_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/8.xbar_smoke_zero_delays.3618293140 |
| Short name | T1383 |
| Test name | |
| Test status | |
| Simulation time | 44733013 ps |
| CPU time | 5.4 seconds |
| Started | Aug 24 04:22:18 AM UTC 24 |
| Finished | Aug 24 04:22:24 AM UTC 24 |
| Peak memory | 595920 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3618293140 -assert nopostpr oc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.xbar_smoke_zero_delays.3618293140 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/8.xbar_smoke_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/8.xbar_stress_all.3866074721 |
| Short name | T471 |
| Test name | |
| Test status | |
| Simulation time | 10291818404 ps |
| CPU time | 279.96 seconds |
| Started | Aug 24 04:23:56 AM UTC 24 |
| Finished | Aug 24 04:28:39 AM UTC 24 |
| Peak memory | 597892 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3866074721 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.xbar_stress_all.3866074721 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/8.xbar_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/8.xbar_stress_all_with_error.2107972837 |
| Short name | T1396 |
| Test name | |
| Test status | |
| Simulation time | 3545473304 ps |
| CPU time | 206.79 seconds |
| Started | Aug 24 04:24:01 AM UTC 24 |
| Finished | Aug 24 04:27:31 AM UTC 24 |
| Peak memory | 597768 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2107972837 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.xbar_stress_all_with_error.2107972837 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/8.xbar_stress_all_with_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/8.xbar_stress_all_with_rand_reset.3923837350 |
| Short name | T856 |
| Test name | |
| Test status | |
| Simulation time | 160036852 ps |
| CPU time | 49.84 seconds |
| Started | Aug 24 04:23:56 AM UTC 24 |
| Finished | Aug 24 04:24:48 AM UTC 24 |
| Peak memory | 597900 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3923837350 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.xbar_stress_all_with_rand_reset.3923837350 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/8.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/8.xbar_stress_all_with_reset_error.2527562482 |
| Short name | T639 |
| Test name | |
| Test status | |
| Simulation time | 4952967714 ps |
| CPU time | 391.11 seconds |
| Started | Aug 24 04:24:02 AM UTC 24 |
| Finished | Aug 24 04:30:38 AM UTC 24 |
| Peak memory | 597892 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2527562482 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.xbar_stress_all_with_reset_error.2527562482 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/8.xbar_stress_all_with_reset_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/8.xbar_unmapped_addr.2347854382 |
| Short name | T1385 |
| Test name | |
| Test status | |
| Simulation time | 22554377 ps |
| CPU time | 4.46 seconds |
| Started | Aug 24 04:23:35 AM UTC 24 |
| Finished | Aug 24 04:23:41 AM UTC 24 |
| Peak memory | 595636 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2347854382 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.xbar_unmapped_addr.2347854382 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/8.xbar_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/80.xbar_access_same_device.2617415799 |
| Short name | T2582 |
| Test name | |
| Test status | |
| Simulation time | 3027041104 ps |
| CPU time | 80.64 seconds |
| Started | Aug 24 07:01:52 AM UTC 24 |
| Finished | Aug 24 07:03:14 AM UTC 24 |
| Peak memory | 597988 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2617415799 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 80.xbar_access_same_device.2617415799 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/80.xbar_access_same_device/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/80.xbar_access_same_device_slow_rsp.2131347368 |
| Short name | T2799 |
| Test name | |
| Test status | |
| Simulation time | 109832594334 ps |
| CPU time | 1240.76 seconds |
| Started | Aug 24 07:02:12 AM UTC 24 |
| Finished | Aug 24 07:23:05 AM UTC 24 |
| Peak memory | 598616 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2131347368 -assert nopostproc +UVM_T ESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 80.xbar_access_same_device_slow_rsp.2131347368 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/80.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/80.xbar_error_and_unmapped_addr.1622851188 |
| Short name | T2579 |
| Test name | |
| Test status | |
| Simulation time | 730165755 ps |
| CPU time | 21.16 seconds |
| Started | Aug 24 07:02:44 AM UTC 24 |
| Finished | Aug 24 07:03:06 AM UTC 24 |
| Peak memory | 597932 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1622851188 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 80.xbar_error_and_unmapped_addr.1622851188 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/80.xbar_error_and_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/80.xbar_error_random.2912879545 |
| Short name | T2575 |
| Test name | |
| Test status | |
| Simulation time | 1213121128 ps |
| CPU time | 25.36 seconds |
| Started | Aug 24 07:02:24 AM UTC 24 |
| Finished | Aug 24 07:02:51 AM UTC 24 |
| Peak memory | 597692 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2912879545 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 80.xbar_error_random.2912879545 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/80.xbar_error_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/80.xbar_random.4261211371 |
| Short name | T2568 |
| Test name | |
| Test status | |
| Simulation time | 1542023271 ps |
| CPU time | 36.14 seconds |
| Started | Aug 24 07:01:33 AM UTC 24 |
| Finished | Aug 24 07:02:10 AM UTC 24 |
| Peak memory | 597688 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4261211371 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 80.xbar_random.4261211371 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/80.xbar_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/80.xbar_random_large_delays.2828610613 |
| Short name | T2634 |
| Test name | |
| Test status | |
| Simulation time | 48565228263 ps |
| CPU time | 395.33 seconds |
| Started | Aug 24 07:01:49 AM UTC 24 |
| Finished | Aug 24 07:08:29 AM UTC 24 |
| Peak memory | 598052 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max _device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2828610613 -assert nopostproc +U VM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 80.xbar_random_large_delays.2828610613 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/80.xbar_random_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/80.xbar_random_slow_rsp.3979525492 |
| Short name | T2599 |
| Test name | |
| Test status | |
| Simulation time | 17753683308 ps |
| CPU time | 209.89 seconds |
| Started | Aug 24 07:01:50 AM UTC 24 |
| Finished | Aug 24 07:05:23 AM UTC 24 |
| Peak memory | 597816 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3979525492 -assert nopostproc +UVM_T ESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 80.xbar_random_slow_rsp.3979525492 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/80.xbar_random_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/80.xbar_random_zero_delays.4198017288 |
| Short name | T2567 |
| Test name | |
| Test status | |
| Simulation time | 470200158 ps |
| CPU time | 29.18 seconds |
| Started | Aug 24 07:01:36 AM UTC 24 |
| Finished | Aug 24 07:02:06 AM UTC 24 |
| Peak memory | 597760 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4198017288 -assert nopostpr oc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 80.xbar_random_zero_delays.4198017288 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/80.xbar_random_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/80.xbar_same_source.1910373259 |
| Short name | T2572 |
| Test name | |
| Test status | |
| Simulation time | 417203292 ps |
| CPU time | 10.87 seconds |
| Started | Aug 24 07:02:20 AM UTC 24 |
| Finished | Aug 24 07:02:32 AM UTC 24 |
| Peak memory | 597744 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1910373259 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 80.xbar_same_source.1910373259 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/80.xbar_same_source/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/80.xbar_smoke.1058078805 |
| Short name | T2560 |
| Test name | |
| Test status | |
| Simulation time | 42467943 ps |
| CPU time | 4.85 seconds |
| Started | Aug 24 07:01:10 AM UTC 24 |
| Finished | Aug 24 07:01:16 AM UTC 24 |
| Peak memory | 595720 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1058078805 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 8_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 80.xbar_smoke.1058078805 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/80.xbar_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/80.xbar_smoke_large_delays.1770032060 |
| Short name | T2573 |
| Test name | |
| Test status | |
| Simulation time | 9494661515 ps |
| CPU time | 76.39 seconds |
| Started | Aug 24 07:01:17 AM UTC 24 |
| Finished | Aug 24 07:02:35 AM UTC 24 |
| Peak memory | 595764 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max _device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1770032060 -assert nopostproc +U VM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 80.xbar_smoke_large_delays.1770032060 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/80.xbar_smoke_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/80.xbar_smoke_slow_rsp.3322967086 |
| Short name | T2571 |
| Test name | |
| Test status | |
| Simulation time | 4879626394 ps |
| CPU time | 58.22 seconds |
| Started | Aug 24 07:01:30 AM UTC 24 |
| Finished | Aug 24 07:02:30 AM UTC 24 |
| Peak memory | 595908 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3322967086 -assert nopostproc +UVM_T ESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 80.xbar_smoke_slow_rsp.3322967086 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/80.xbar_smoke_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/80.xbar_smoke_zero_delays.3404155585 |
| Short name | T2561 |
| Test name | |
| Test status | |
| Simulation time | 45091021 ps |
| CPU time | 4.86 seconds |
| Started | Aug 24 07:01:12 AM UTC 24 |
| Finished | Aug 24 07:01:18 AM UTC 24 |
| Peak memory | 595700 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3404155585 -assert nopostpr oc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 80.xbar_smoke_zero_delays.3404155585 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/80.xbar_smoke_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/80.xbar_stress_all.2261849223 |
| Short name | T2601 |
| Test name | |
| Test status | |
| Simulation time | 2789768473 ps |
| CPU time | 156.8 seconds |
| Started | Aug 24 07:02:44 AM UTC 24 |
| Finished | Aug 24 07:05:23 AM UTC 24 |
| Peak memory | 597896 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2261849223 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 80.xbar_stress_all.2261849223 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/80.xbar_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/80.xbar_stress_all_with_rand_reset.2327756725 |
| Short name | T2709 |
| Test name | |
| Test status | |
| Simulation time | 23709318023 ps |
| CPU time | 767.22 seconds |
| Started | Aug 24 07:02:46 AM UTC 24 |
| Finished | Aug 24 07:15:42 AM UTC 24 |
| Peak memory | 597820 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2327756725 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 80.xbar_stress_all_with_rand_reset.2327756725 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/80.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/80.xbar_stress_all_with_reset_error.3173112815 |
| Short name | T2603 |
| Test name | |
| Test status | |
| Simulation time | 2155548876 ps |
| CPU time | 170.83 seconds |
| Started | Aug 24 07:02:56 AM UTC 24 |
| Finished | Aug 24 07:05:50 AM UTC 24 |
| Peak memory | 597948 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3173112815 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 80.xbar_stress_all_with_reset_error.3173112815 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/80.xbar_stress_all_with_reset_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/80.xbar_unmapped_addr.2465495854 |
| Short name | T2576 |
| Test name | |
| Test status | |
| Simulation time | 676388189 ps |
| CPU time | 20.37 seconds |
| Started | Aug 24 07:02:31 AM UTC 24 |
| Finished | Aug 24 07:02:53 AM UTC 24 |
| Peak memory | 597692 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2465495854 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 80.xbar_unmapped_addr.2465495854 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/80.xbar_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/81.xbar_access_same_device.491871505 |
| Short name | T2593 |
| Test name | |
| Test status | |
| Simulation time | 2544225354 ps |
| CPU time | 71.9 seconds |
| Started | Aug 24 07:03:29 AM UTC 24 |
| Finished | Aug 24 07:04:42 AM UTC 24 |
| Peak memory | 598080 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=491871505 -assert nopostproc +UVM_TESTNAME =xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 81.xbar_access_same_device.491871505 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/81.xbar_access_same_device/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/81.xbar_access_same_device_slow_rsp.3295405373 |
| Short name | T2647 |
| Test name | |
| Test status | |
| Simulation time | 31587974100 ps |
| CPU time | 353.96 seconds |
| Started | Aug 24 07:03:40 AM UTC 24 |
| Finished | Aug 24 07:09:38 AM UTC 24 |
| Peak memory | 597820 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3295405373 -assert nopostproc +UVM_T ESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 81.xbar_access_same_device_slow_rsp.3295405373 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/81.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/81.xbar_error_and_unmapped_addr.149910977 |
| Short name | T2592 |
| Test name | |
| Test status | |
| Simulation time | 22911036 ps |
| CPU time | 4.46 seconds |
| Started | Aug 24 07:04:36 AM UTC 24 |
| Finished | Aug 24 07:04:42 AM UTC 24 |
| Peak memory | 595512 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=149910977 -assert nopostproc +UVM_TESTNAME =xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 81.xbar_error_and_unmapped_addr.149910977 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/81.xbar_error_and_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/81.xbar_error_random.3322070183 |
| Short name | T2587 |
| Test name | |
| Test status | |
| Simulation time | 397701300 ps |
| CPU time | 11.55 seconds |
| Started | Aug 24 07:04:09 AM UTC 24 |
| Finished | Aug 24 07:04:22 AM UTC 24 |
| Peak memory | 597752 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3322070183 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 81.xbar_error_random.3322070183 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/81.xbar_error_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/81.xbar_random.2519798415 |
| Short name | T2589 |
| Test name | |
| Test status | |
| Simulation time | 2514365066 ps |
| CPU time | 63.75 seconds |
| Started | Aug 24 07:03:21 AM UTC 24 |
| Finished | Aug 24 07:04:26 AM UTC 24 |
| Peak memory | 597816 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2519798415 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 81.xbar_random.2519798415 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/81.xbar_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/81.xbar_random_large_delays.78782471 |
| Short name | T2598 |
| Test name | |
| Test status | |
| Simulation time | 12947940025 ps |
| CPU time | 103.7 seconds |
| Started | Aug 24 07:03:27 AM UTC 24 |
| Finished | Aug 24 07:05:12 AM UTC 24 |
| Peak memory | 598108 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max _device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=78782471 -assert nopostproc +UVM _TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 81.xbar_random_large_delays.78782471 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/81.xbar_random_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/81.xbar_random_slow_rsp.3449910313 |
| Short name | T2644 |
| Test name | |
| Test status | |
| Simulation time | 30759653877 ps |
| CPU time | 363.11 seconds |
| Started | Aug 24 07:03:27 AM UTC 24 |
| Finished | Aug 24 07:09:34 AM UTC 24 |
| Peak memory | 597884 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3449910313 -assert nopostproc +UVM_T ESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 81.xbar_random_slow_rsp.3449910313 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/81.xbar_random_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/81.xbar_random_zero_delays.744073466 |
| Short name | T2585 |
| Test name | |
| Test status | |
| Simulation time | 569501962 ps |
| CPU time | 32.82 seconds |
| Started | Aug 24 07:03:21 AM UTC 24 |
| Finished | Aug 24 07:03:55 AM UTC 24 |
| Peak memory | 597828 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=744073466 -assert nopostpro c +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 81.xbar_random_zero_delays.744073466 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/81.xbar_random_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/81.xbar_same_source.64716442 |
| Short name | T2588 |
| Test name | |
| Test status | |
| Simulation time | 300869486 ps |
| CPU time | 17.13 seconds |
| Started | Aug 24 07:04:07 AM UTC 24 |
| Finished | Aug 24 07:04:26 AM UTC 24 |
| Peak memory | 597700 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=64716442 -assert nopostproc +UVM_TESTNAME= xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 81.xbar_same_source.64716442 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/81.xbar_same_source/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/81.xbar_smoke.2162438916 |
| Short name | T2581 |
| Test name | |
| Test status | |
| Simulation time | 246863882 ps |
| CPU time | 7.72 seconds |
| Started | Aug 24 07:03:04 AM UTC 24 |
| Finished | Aug 24 07:03:13 AM UTC 24 |
| Peak memory | 595852 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2162438916 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 8_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 81.xbar_smoke.2162438916 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/81.xbar_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/81.xbar_smoke_large_delays.483278597 |
| Short name | T2591 |
| Test name | |
| Test status | |
| Simulation time | 9977184334 ps |
| CPU time | 83.5 seconds |
| Started | Aug 24 07:03:09 AM UTC 24 |
| Finished | Aug 24 07:04:35 AM UTC 24 |
| Peak memory | 595764 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max _device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=483278597 -assert nopostproc +UV M_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 81.xbar_smoke_large_delays.483278597 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/81.xbar_smoke_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/81.xbar_smoke_slow_rsp.2656613463 |
| Short name | T2586 |
| Test name | |
| Test status | |
| Simulation time | 4438847367 ps |
| CPU time | 50.71 seconds |
| Started | Aug 24 07:03:14 AM UTC 24 |
| Finished | Aug 24 07:04:06 AM UTC 24 |
| Peak memory | 595892 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2656613463 -assert nopostproc +UVM_T ESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 81.xbar_smoke_slow_rsp.2656613463 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/81.xbar_smoke_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/81.xbar_smoke_zero_delays.45189061 |
| Short name | T2580 |
| Test name | |
| Test status | |
| Simulation time | 47635064 ps |
| CPU time | 4.98 seconds |
| Started | Aug 24 07:03:06 AM UTC 24 |
| Finished | Aug 24 07:03:12 AM UTC 24 |
| Peak memory | 595636 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=45189061 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 81.xbar_smoke_zero_delays.45189061 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/81.xbar_smoke_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/81.xbar_stress_all.2186904105 |
| Short name | T2625 |
| Test name | |
| Test status | |
| Simulation time | 8314188533 ps |
| CPU time | 186.44 seconds |
| Started | Aug 24 07:04:40 AM UTC 24 |
| Finished | Aug 24 07:07:49 AM UTC 24 |
| Peak memory | 597824 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2186904105 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 81.xbar_stress_all.2186904105 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/81.xbar_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/81.xbar_stress_all_with_error.3319984934 |
| Short name | T2602 |
| Test name | |
| Test status | |
| Simulation time | 1144979014 ps |
| CPU time | 55.22 seconds |
| Started | Aug 24 07:04:48 AM UTC 24 |
| Finished | Aug 24 07:05:45 AM UTC 24 |
| Peak memory | 597696 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3319984934 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 81.xbar_stress_all_with_error.3319984934 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/81.xbar_stress_all_with_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/81.xbar_stress_all_with_rand_reset.794952542 |
| Short name | T2604 |
| Test name | |
| Test status | |
| Simulation time | 129758728 ps |
| CPU time | 72.42 seconds |
| Started | Aug 24 07:04:41 AM UTC 24 |
| Finished | Aug 24 07:05:55 AM UTC 24 |
| Peak memory | 597908 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=794952542 -assert nopostproc +UVM_TESTNAME =xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 81.xbar_stress_all_with_rand_reset.794952542 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/81.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/81.xbar_stress_all_with_reset_error.2080675386 |
| Short name | T861 |
| Test name | |
| Test status | |
| Simulation time | 17775561188 ps |
| CPU time | 604.75 seconds |
| Started | Aug 24 07:04:48 AM UTC 24 |
| Finished | Aug 24 07:15:00 AM UTC 24 |
| Peak memory | 602004 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2080675386 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 81.xbar_stress_all_with_reset_error.2080675386 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/81.xbar_stress_all_with_reset_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/81.xbar_unmapped_addr.104267810 |
| Short name | T2590 |
| Test name | |
| Test status | |
| Simulation time | 364453740 ps |
| CPU time | 12.11 seconds |
| Started | Aug 24 07:04:20 AM UTC 24 |
| Finished | Aug 24 07:04:34 AM UTC 24 |
| Peak memory | 597824 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=104267810 -assert nopostproc +UVM_TESTNAME =xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 81.xbar_unmapped_addr.104267810 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/81.xbar_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/82.xbar_access_same_device.3523574749 |
| Short name | T2617 |
| Test name | |
| Test status | |
| Simulation time | 2969980589 ps |
| CPU time | 73.55 seconds |
| Started | Aug 24 07:05:37 AM UTC 24 |
| Finished | Aug 24 07:06:52 AM UTC 24 |
| Peak memory | 598116 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3523574749 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 82.xbar_access_same_device.3523574749 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/82.xbar_access_same_device/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/82.xbar_access_same_device_slow_rsp.1244546521 |
| Short name | T2754 |
| Test name | |
| Test status | |
| Simulation time | 68878452576 ps |
| CPU time | 816.04 seconds |
| Started | Aug 24 07:05:38 AM UTC 24 |
| Finished | Aug 24 07:19:22 AM UTC 24 |
| Peak memory | 597820 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1244546521 -assert nopostproc +UVM_T ESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 82.xbar_access_same_device_slow_rsp.1244546521 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/82.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/82.xbar_error_and_unmapped_addr.3343184544 |
| Short name | T2609 |
| Test name | |
| Test status | |
| Simulation time | 42787373 ps |
| CPU time | 5.91 seconds |
| Started | Aug 24 07:06:09 AM UTC 24 |
| Finished | Aug 24 07:06:16 AM UTC 24 |
| Peak memory | 597692 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3343184544 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 82.xbar_error_and_unmapped_addr.3343184544 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/82.xbar_error_and_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/82.xbar_error_random.2796086891 |
| Short name | T2612 |
| Test name | |
| Test status | |
| Simulation time | 289877702 ps |
| CPU time | 19.03 seconds |
| Started | Aug 24 07:05:59 AM UTC 24 |
| Finished | Aug 24 07:06:20 AM UTC 24 |
| Peak memory | 597688 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2796086891 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 82.xbar_error_random.2796086891 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/82.xbar_error_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/82.xbar_random.4108126277 |
| Short name | T2558 |
| Test name | |
| Test status | |
| Simulation time | 561476360 ps |
| CPU time | 15.2 seconds |
| Started | Aug 24 07:05:17 AM UTC 24 |
| Finished | Aug 24 07:05:33 AM UTC 24 |
| Peak memory | 597688 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4108126277 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 82.xbar_random.4108126277 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/82.xbar_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/82.xbar_random_large_delays.3846047215 |
| Short name | T2746 |
| Test name | |
| Test status | |
| Simulation time | 98564605435 ps |
| CPU time | 800.39 seconds |
| Started | Aug 24 07:05:27 AM UTC 24 |
| Finished | Aug 24 07:18:55 AM UTC 24 |
| Peak memory | 597820 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max _device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3846047215 -assert nopostproc +U VM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 82.xbar_random_large_delays.3846047215 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/82.xbar_random_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/82.xbar_random_slow_rsp.3696850638 |
| Short name | T2692 |
| Test name | |
| Test status | |
| Simulation time | 44233028689 ps |
| CPU time | 502.26 seconds |
| Started | Aug 24 07:05:37 AM UTC 24 |
| Finished | Aug 24 07:14:05 AM UTC 24 |
| Peak memory | 597884 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3696850638 -assert nopostproc +UVM_T ESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 82.xbar_random_slow_rsp.3696850638 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/82.xbar_random_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/82.xbar_random_zero_delays.3523616768 |
| Short name | T2605 |
| Test name | |
| Test status | |
| Simulation time | 612484116 ps |
| CPU time | 37.79 seconds |
| Started | Aug 24 07:05:19 AM UTC 24 |
| Finished | Aug 24 07:05:58 AM UTC 24 |
| Peak memory | 597840 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3523616768 -assert nopostpr oc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 82.xbar_random_zero_delays.3523616768 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/82.xbar_random_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/82.xbar_same_source.2265404005 |
| Short name | T2607 |
| Test name | |
| Test status | |
| Simulation time | 416334137 ps |
| CPU time | 21.47 seconds |
| Started | Aug 24 07:05:47 AM UTC 24 |
| Finished | Aug 24 07:06:10 AM UTC 24 |
| Peak memory | 597688 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2265404005 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 82.xbar_same_source.2265404005 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/82.xbar_same_source/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/82.xbar_smoke.3627013546 |
| Short name | T2595 |
| Test name | |
| Test status | |
| Simulation time | 46947247 ps |
| CPU time | 5.01 seconds |
| Started | Aug 24 07:04:55 AM UTC 24 |
| Finished | Aug 24 07:05:01 AM UTC 24 |
| Peak memory | 595628 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3627013546 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 8_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 82.xbar_smoke.3627013546 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/82.xbar_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/82.xbar_smoke_large_delays.3689529272 |
| Short name | T2608 |
| Test name | |
| Test status | |
| Simulation time | 8791622045 ps |
| CPU time | 70.38 seconds |
| Started | Aug 24 07:05:00 AM UTC 24 |
| Finished | Aug 24 07:06:12 AM UTC 24 |
| Peak memory | 596020 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max _device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3689529272 -assert nopostproc +U VM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 82.xbar_smoke_large_delays.3689529272 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/82.xbar_smoke_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/82.xbar_smoke_slow_rsp.525959909 |
| Short name | T2611 |
| Test name | |
| Test status | |
| Simulation time | 5125864035 ps |
| CPU time | 61.88 seconds |
| Started | Aug 24 07:05:16 AM UTC 24 |
| Finished | Aug 24 07:06:19 AM UTC 24 |
| Peak memory | 596036 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=525959909 -assert nopostproc +UVM_TE STNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 82.xbar_smoke_slow_rsp.525959909 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/82.xbar_smoke_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/82.xbar_smoke_zero_delays.2867215961 |
| Short name | T2596 |
| Test name | |
| Test status | |
| Simulation time | 50191361 ps |
| CPU time | 5.2 seconds |
| Started | Aug 24 07:04:57 AM UTC 24 |
| Finished | Aug 24 07:05:03 AM UTC 24 |
| Peak memory | 595636 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2867215961 -assert nopostpr oc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 82.xbar_smoke_zero_delays.2867215961 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/82.xbar_smoke_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/82.xbar_stress_all.2387442328 |
| Short name | T2658 |
| Test name | |
| Test status | |
| Simulation time | 11756958684 ps |
| CPU time | 285.49 seconds |
| Started | Aug 24 07:06:12 AM UTC 24 |
| Finished | Aug 24 07:11:01 AM UTC 24 |
| Peak memory | 597900 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2387442328 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 82.xbar_stress_all.2387442328 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/82.xbar_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/82.xbar_stress_all_with_error.4252444807 |
| Short name | T2635 |
| Test name | |
| Test status | |
| Simulation time | 2476639970 ps |
| CPU time | 132.04 seconds |
| Started | Aug 24 07:06:24 AM UTC 24 |
| Finished | Aug 24 07:08:39 AM UTC 24 |
| Peak memory | 597760 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4252444807 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 82.xbar_stress_all_with_error.4252444807 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/82.xbar_stress_all_with_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/82.xbar_stress_all_with_rand_reset.667816890 |
| Short name | T2672 |
| Test name | |
| Test status | |
| Simulation time | 4879386365 ps |
| CPU time | 358.17 seconds |
| Started | Aug 24 07:06:13 AM UTC 24 |
| Finished | Aug 24 07:12:16 AM UTC 24 |
| Peak memory | 597820 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=667816890 -assert nopostproc +UVM_TESTNAME =xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 82.xbar_stress_all_with_rand_reset.667816890 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/82.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/82.xbar_stress_all_with_reset_error.3593998388 |
| Short name | T2620 |
| Test name | |
| Test status | |
| Simulation time | 516364835 ps |
| CPU time | 66.33 seconds |
| Started | Aug 24 07:06:25 AM UTC 24 |
| Finished | Aug 24 07:07:33 AM UTC 24 |
| Peak memory | 597692 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3593998388 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 82.xbar_stress_all_with_reset_error.3593998388 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/82.xbar_stress_all_with_reset_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/82.xbar_unmapped_addr.3292391779 |
| Short name | T2610 |
| Test name | |
| Test status | |
| Simulation time | 110803559 ps |
| CPU time | 11.69 seconds |
| Started | Aug 24 07:06:04 AM UTC 24 |
| Finished | Aug 24 07:06:17 AM UTC 24 |
| Peak memory | 597688 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3292391779 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 82.xbar_unmapped_addr.3292391779 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/82.xbar_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/83.xbar_access_same_device.2664516141 |
| Short name | T2622 |
| Test name | |
| Test status | |
| Simulation time | 654767354 ps |
| CPU time | 35.27 seconds |
| Started | Aug 24 07:07:06 AM UTC 24 |
| Finished | Aug 24 07:07:43 AM UTC 24 |
| Peak memory | 597704 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2664516141 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 83.xbar_access_same_device.2664516141 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/83.xbar_access_same_device/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/83.xbar_access_same_device_slow_rsp.1477955555 |
| Short name | T2776 |
| Test name | |
| Test status | |
| Simulation time | 71177546267 ps |
| CPU time | 816.3 seconds |
| Started | Aug 24 07:07:15 AM UTC 24 |
| Finished | Aug 24 07:21:00 AM UTC 24 |
| Peak memory | 598084 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1477955555 -assert nopostproc +UVM_T ESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 83.xbar_access_same_device_slow_rsp.1477955555 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/83.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/83.xbar_error_and_unmapped_addr.2795976409 |
| Short name | T2631 |
| Test name | |
| Test status | |
| Simulation time | 249927964 ps |
| CPU time | 19.2 seconds |
| Started | Aug 24 07:07:56 AM UTC 24 |
| Finished | Aug 24 07:08:17 AM UTC 24 |
| Peak memory | 597844 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2795976409 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 83.xbar_error_and_unmapped_addr.2795976409 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/83.xbar_error_and_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/83.xbar_error_random.308241457 |
| Short name | T2629 |
| Test name | |
| Test status | |
| Simulation time | 472387921 ps |
| CPU time | 27.1 seconds |
| Started | Aug 24 07:07:35 AM UTC 24 |
| Finished | Aug 24 07:08:04 AM UTC 24 |
| Peak memory | 597696 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=308241457 -assert nopostproc +UVM_TESTNAME =xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 83.xbar_error_random.308241457 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/83.xbar_error_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/83.xbar_random.839784298 |
| Short name | T2626 |
| Test name | |
| Test status | |
| Simulation time | 2363217674 ps |
| CPU time | 58.95 seconds |
| Started | Aug 24 07:06:52 AM UTC 24 |
| Finished | Aug 24 07:07:52 AM UTC 24 |
| Peak memory | 597980 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=839784298 -assert nopostproc +UVM_TESTNAME =xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 8_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 83.xbar_random.839784298 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/83.xbar_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/83.xbar_random_large_delays.844527136 |
| Short name | T2732 |
| Test name | |
| Test status | |
| Simulation time | 81898454921 ps |
| CPU time | 649.56 seconds |
| Started | Aug 24 07:06:52 AM UTC 24 |
| Finished | Aug 24 07:17:48 AM UTC 24 |
| Peak memory | 598068 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max _device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=844527136 -assert nopostproc +UV M_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 83.xbar_random_large_delays.844527136 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/83.xbar_random_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/83.xbar_random_slow_rsp.1230416905 |
| Short name | T2697 |
| Test name | |
| Test status | |
| Simulation time | 38690619428 ps |
| CPU time | 448.06 seconds |
| Started | Aug 24 07:07:04 AM UTC 24 |
| Finished | Aug 24 07:14:37 AM UTC 24 |
| Peak memory | 597816 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1230416905 -assert nopostproc +UVM_T ESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 83.xbar_random_slow_rsp.1230416905 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/83.xbar_random_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/83.xbar_random_zero_delays.341933126 |
| Short name | T2619 |
| Test name | |
| Test status | |
| Simulation time | 459380344 ps |
| CPU time | 27.87 seconds |
| Started | Aug 24 07:06:52 AM UTC 24 |
| Finished | Aug 24 07:07:21 AM UTC 24 |
| Peak memory | 597696 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=341933126 -assert nopostpro c +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 83.xbar_random_zero_delays.341933126 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/83.xbar_random_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/83.xbar_same_source.1046257736 |
| Short name | T2627 |
| Test name | |
| Test status | |
| Simulation time | 2035684476 ps |
| CPU time | 41.37 seconds |
| Started | Aug 24 07:07:18 AM UTC 24 |
| Finished | Aug 24 07:08:02 AM UTC 24 |
| Peak memory | 597816 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1046257736 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 83.xbar_same_source.1046257736 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/83.xbar_same_source/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/83.xbar_smoke.2212753173 |
| Short name | T2614 |
| Test name | |
| Test status | |
| Simulation time | 161859056 ps |
| CPU time | 6.07 seconds |
| Started | Aug 24 07:06:30 AM UTC 24 |
| Finished | Aug 24 07:06:38 AM UTC 24 |
| Peak memory | 595636 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2212753173 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 8_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 83.xbar_smoke.2212753173 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/83.xbar_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/83.xbar_smoke_large_delays.4213366026 |
| Short name | T2621 |
| Test name | |
| Test status | |
| Simulation time | 8483414554 ps |
| CPU time | 66.77 seconds |
| Started | Aug 24 07:06:34 AM UTC 24 |
| Finished | Aug 24 07:07:42 AM UTC 24 |
| Peak memory | 595768 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max _device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4213366026 -assert nopostproc +U VM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 83.xbar_smoke_large_delays.4213366026 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/83.xbar_smoke_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/83.xbar_smoke_slow_rsp.1730441755 |
| Short name | T2623 |
| Test name | |
| Test status | |
| Simulation time | 5741487319 ps |
| CPU time | 69.91 seconds |
| Started | Aug 24 07:06:34 AM UTC 24 |
| Finished | Aug 24 07:07:45 AM UTC 24 |
| Peak memory | 595908 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1730441755 -assert nopostproc +UVM_T ESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 83.xbar_smoke_slow_rsp.1730441755 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/83.xbar_smoke_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/83.xbar_smoke_zero_delays.131901445 |
| Short name | T2615 |
| Test name | |
| Test status | |
| Simulation time | 46385300 ps |
| CPU time | 5.19 seconds |
| Started | Aug 24 07:06:32 AM UTC 24 |
| Finished | Aug 24 07:06:38 AM UTC 24 |
| Peak memory | 595812 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=131901445 -assert nopostpro c +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 83.xbar_smoke_zero_delays.131901445 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/83.xbar_smoke_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/83.xbar_stress_all.4072634067 |
| Short name | T2639 |
| Test name | |
| Test status | |
| Simulation time | 1315128360 ps |
| CPU time | 76.09 seconds |
| Started | Aug 24 07:07:58 AM UTC 24 |
| Finished | Aug 24 07:09:16 AM UTC 24 |
| Peak memory | 597832 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4072634067 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 83.xbar_stress_all.4072634067 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/83.xbar_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/83.xbar_stress_all_with_error.1942229238 |
| Short name | T2665 |
| Test name | |
| Test status | |
| Simulation time | 9141094474 ps |
| CPU time | 208.2 seconds |
| Started | Aug 24 07:08:03 AM UTC 24 |
| Finished | Aug 24 07:11:34 AM UTC 24 |
| Peak memory | 598080 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1942229238 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 83.xbar_stress_all_with_error.1942229238 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/83.xbar_stress_all_with_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/83.xbar_stress_all_with_rand_reset.1477594194 |
| Short name | T2659 |
| Test name | |
| Test status | |
| Simulation time | 2980989475 ps |
| CPU time | 184.62 seconds |
| Started | Aug 24 07:08:00 AM UTC 24 |
| Finished | Aug 24 07:11:07 AM UTC 24 |
| Peak memory | 597976 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1477594194 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 83.xbar_stress_all_with_rand_reset.1477594194 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/83.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/83.xbar_stress_all_with_reset_error.2709022810 |
| Short name | T2682 |
| Test name | |
| Test status | |
| Simulation time | 7614775056 ps |
| CPU time | 303.57 seconds |
| Started | Aug 24 07:08:04 AM UTC 24 |
| Finished | Aug 24 07:13:11 AM UTC 24 |
| Peak memory | 597828 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2709022810 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 83.xbar_stress_all_with_reset_error.2709022810 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/83.xbar_stress_all_with_reset_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/83.xbar_unmapped_addr.1612361339 |
| Short name | T2628 |
| Test name | |
| Test status | |
| Simulation time | 166957690 ps |
| CPU time | 14.79 seconds |
| Started | Aug 24 07:07:47 AM UTC 24 |
| Finished | Aug 24 07:08:03 AM UTC 24 |
| Peak memory | 597944 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1612361339 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 83.xbar_unmapped_addr.1612361339 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/83.xbar_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/84.xbar_access_same_device.2801150160 |
| Short name | T2643 |
| Test name | |
| Test status | |
| Simulation time | 1001704415 ps |
| CPU time | 48.83 seconds |
| Started | Aug 24 07:08:43 AM UTC 24 |
| Finished | Aug 24 07:09:33 AM UTC 24 |
| Peak memory | 597712 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2801150160 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 84.xbar_access_same_device.2801150160 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/84.xbar_access_same_device/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/84.xbar_access_same_device_slow_rsp.168811048 |
| Short name | T2854 |
| Test name | |
| Test status | |
| Simulation time | 99119234848 ps |
| CPU time | 1115.04 seconds |
| Started | Aug 24 07:08:53 AM UTC 24 |
| Finished | Aug 24 07:27:39 AM UTC 24 |
| Peak memory | 599044 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=168811048 -assert nopostproc +UVM_TE STNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os _regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 84.xbar_access_same_device_slow_rsp.168811048 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/84.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/84.xbar_error_and_unmapped_addr.67358463 |
| Short name | T2648 |
| Test name | |
| Test status | |
| Simulation time | 99451425 ps |
| CPU time | 9.57 seconds |
| Started | Aug 24 07:09:30 AM UTC 24 |
| Finished | Aug 24 07:09:41 AM UTC 24 |
| Peak memory | 597692 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=67358463 -assert nopostproc +UVM_TESTNAME= xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 84.xbar_error_and_unmapped_addr.67358463 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/84.xbar_error_and_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/84.xbar_error_random.394765854 |
| Short name | T2645 |
| Test name | |
| Test status | |
| Simulation time | 440634633 ps |
| CPU time | 26.43 seconds |
| Started | Aug 24 07:09:07 AM UTC 24 |
| Finished | Aug 24 07:09:35 AM UTC 24 |
| Peak memory | 597696 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=394765854 -assert nopostproc +UVM_TESTNAME =xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 84.xbar_error_random.394765854 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/84.xbar_error_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/84.xbar_random.2125788290 |
| Short name | T2638 |
| Test name | |
| Test status | |
| Simulation time | 1371466648 ps |
| CPU time | 34.3 seconds |
| Started | Aug 24 07:08:29 AM UTC 24 |
| Finished | Aug 24 07:09:05 AM UTC 24 |
| Peak memory | 597756 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2125788290 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 84.xbar_random.2125788290 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/84.xbar_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/84.xbar_random_large_delays.3687861168 |
| Short name | T2640 |
| Test name | |
| Test status | |
| Simulation time | 5261081362 ps |
| CPU time | 42.65 seconds |
| Started | Aug 24 07:08:32 AM UTC 24 |
| Finished | Aug 24 07:09:16 AM UTC 24 |
| Peak memory | 596000 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max _device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3687861168 -assert nopostproc +U VM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 84.xbar_random_large_delays.3687861168 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/84.xbar_random_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/84.xbar_random_slow_rsp.4246162127 |
| Short name | T2674 |
| Test name | |
| Test status | |
| Simulation time | 19020832740 ps |
| CPU time | 224.18 seconds |
| Started | Aug 24 07:08:36 AM UTC 24 |
| Finished | Aug 24 07:12:23 AM UTC 24 |
| Peak memory | 597824 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4246162127 -assert nopostproc +UVM_T ESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 84.xbar_random_slow_rsp.4246162127 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/84.xbar_random_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/84.xbar_random_zero_delays.3052202299 |
| Short name | T2637 |
| Test name | |
| Test status | |
| Simulation time | 304610131 ps |
| CPU time | 20.38 seconds |
| Started | Aug 24 07:08:31 AM UTC 24 |
| Finished | Aug 24 07:08:53 AM UTC 24 |
| Peak memory | 597840 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3052202299 -assert nopostpr oc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 84.xbar_random_zero_delays.3052202299 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/84.xbar_random_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/84.xbar_same_source.3060631478 |
| Short name | T2641 |
| Test name | |
| Test status | |
| Simulation time | 1283376103 ps |
| CPU time | 27.83 seconds |
| Started | Aug 24 07:08:58 AM UTC 24 |
| Finished | Aug 24 07:09:28 AM UTC 24 |
| Peak memory | 597688 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3060631478 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 84.xbar_same_source.3060631478 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/84.xbar_same_source/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/84.xbar_smoke.1357880454 |
| Short name | T2630 |
| Test name | |
| Test status | |
| Simulation time | 174276137 ps |
| CPU time | 6.31 seconds |
| Started | Aug 24 07:08:07 AM UTC 24 |
| Finished | Aug 24 07:08:14 AM UTC 24 |
| Peak memory | 595760 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1357880454 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 8_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 84.xbar_smoke.1357880454 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/84.xbar_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/84.xbar_smoke_large_delays.1934132459 |
| Short name | T2642 |
| Test name | |
| Test status | |
| Simulation time | 8567749336 ps |
| CPU time | 69.14 seconds |
| Started | Aug 24 07:08:18 AM UTC 24 |
| Finished | Aug 24 07:09:29 AM UTC 24 |
| Peak memory | 596084 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max _device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1934132459 -assert nopostproc +U VM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 84.xbar_smoke_large_delays.1934132459 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/84.xbar_smoke_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/84.xbar_smoke_slow_rsp.518509842 |
| Short name | T2646 |
| Test name | |
| Test status | |
| Simulation time | 6446872756 ps |
| CPU time | 77.41 seconds |
| Started | Aug 24 07:08:18 AM UTC 24 |
| Finished | Aug 24 07:09:37 AM UTC 24 |
| Peak memory | 595992 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=518509842 -assert nopostproc +UVM_TE STNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 84.xbar_smoke_slow_rsp.518509842 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/84.xbar_smoke_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/84.xbar_smoke_zero_delays.1613744665 |
| Short name | T2633 |
| Test name | |
| Test status | |
| Simulation time | 48051160 ps |
| CPU time | 5.07 seconds |
| Started | Aug 24 07:08:16 AM UTC 24 |
| Finished | Aug 24 07:08:22 AM UTC 24 |
| Peak memory | 595632 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1613744665 -assert nopostpr oc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 84.xbar_smoke_zero_delays.1613744665 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/84.xbar_smoke_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/84.xbar_stress_all.2965335518 |
| Short name | T2689 |
| Test name | |
| Test status | |
| Simulation time | 9932569266 ps |
| CPU time | 250.75 seconds |
| Started | Aug 24 07:09:30 AM UTC 24 |
| Finished | Aug 24 07:13:45 AM UTC 24 |
| Peak memory | 597896 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2965335518 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 84.xbar_stress_all.2965335518 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/84.xbar_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/84.xbar_stress_all_with_error.456556324 |
| Short name | T2660 |
| Test name | |
| Test status | |
| Simulation time | 1562099293 ps |
| CPU time | 84.39 seconds |
| Started | Aug 24 07:09:42 AM UTC 24 |
| Finished | Aug 24 07:11:09 AM UTC 24 |
| Peak memory | 597700 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=456556324 -assert nopostproc +UVM_TESTNAME =xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 84.xbar_stress_all_with_error.456556324 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/84.xbar_stress_all_with_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/84.xbar_stress_all_with_rand_reset.2590567439 |
| Short name | T2655 |
| Test name | |
| Test status | |
| Simulation time | 121913248 ps |
| CPU time | 39.01 seconds |
| Started | Aug 24 07:09:41 AM UTC 24 |
| Finished | Aug 24 07:10:22 AM UTC 24 |
| Peak memory | 597756 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2590567439 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 84.xbar_stress_all_with_rand_reset.2590567439 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/84.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/84.xbar_stress_all_with_reset_error.985983766 |
| Short name | T2652 |
| Test name | |
| Test status | |
| Simulation time | 90764322 ps |
| CPU time | 9.93 seconds |
| Started | Aug 24 07:09:47 AM UTC 24 |
| Finished | Aug 24 07:09:58 AM UTC 24 |
| Peak memory | 595888 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=985983766 -assert nopostproc +UVM_TESTNAME =xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 84.xbar_stress_all_with_reset_error.985983766 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/84.xbar_stress_all_with_reset_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/84.xbar_unmapped_addr.3918627942 |
| Short name | T2649 |
| Test name | |
| Test status | |
| Simulation time | 651831282 ps |
| CPU time | 21.58 seconds |
| Started | Aug 24 07:09:19 AM UTC 24 |
| Finished | Aug 24 07:09:42 AM UTC 24 |
| Peak memory | 597948 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3918627942 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 84.xbar_unmapped_addr.3918627942 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/84.xbar_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/85.xbar_access_same_device.3891024770 |
| Short name | T2670 |
| Test name | |
| Test status | |
| Simulation time | 3401001470 ps |
| CPU time | 96.78 seconds |
| Started | Aug 24 07:10:13 AM UTC 24 |
| Finished | Aug 24 07:11:52 AM UTC 24 |
| Peak memory | 597988 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3891024770 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 85.xbar_access_same_device.3891024770 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/85.xbar_access_same_device/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/85.xbar_access_same_device_slow_rsp.2605691996 |
| Short name | T2680 |
| Test name | |
| Test status | |
| Simulation time | 12875138674 ps |
| CPU time | 152.87 seconds |
| Started | Aug 24 07:10:34 AM UTC 24 |
| Finished | Aug 24 07:13:09 AM UTC 24 |
| Peak memory | 598140 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2605691996 -assert nopostproc +UVM_T ESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 85.xbar_access_same_device_slow_rsp.2605691996 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/85.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/85.xbar_error_and_unmapped_addr.3741918522 |
| Short name | T2667 |
| Test name | |
| Test status | |
| Simulation time | 1018148320 ps |
| CPU time | 26.35 seconds |
| Started | Aug 24 07:11:11 AM UTC 24 |
| Finished | Aug 24 07:11:39 AM UTC 24 |
| Peak memory | 597696 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3741918522 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 85.xbar_error_and_unmapped_addr.3741918522 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/85.xbar_error_and_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/85.xbar_error_random.4123550071 |
| Short name | T2656 |
| Test name | |
| Test status | |
| Simulation time | 157661228 ps |
| CPU time | 10.26 seconds |
| Started | Aug 24 07:10:36 AM UTC 24 |
| Finished | Aug 24 07:10:48 AM UTC 24 |
| Peak memory | 597692 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4123550071 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 85.xbar_error_random.4123550071 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/85.xbar_error_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/85.xbar_random.482030021 |
| Short name | T2653 |
| Test name | |
| Test status | |
| Simulation time | 860276568 ps |
| CPU time | 23.6 seconds |
| Started | Aug 24 07:09:55 AM UTC 24 |
| Finished | Aug 24 07:10:20 AM UTC 24 |
| Peak memory | 598040 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=482030021 -assert nopostproc +UVM_TESTNAME =xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 8_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 85.xbar_random.482030021 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/85.xbar_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/85.xbar_random_large_delays.2073404135 |
| Short name | T2708 |
| Test name | |
| Test status | |
| Simulation time | 37222236470 ps |
| CPU time | 312.65 seconds |
| Started | Aug 24 07:10:10 AM UTC 24 |
| Finished | Aug 24 07:15:26 AM UTC 24 |
| Peak memory | 598024 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max _device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2073404135 -assert nopostproc +U VM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 85.xbar_random_large_delays.2073404135 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/85.xbar_random_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/85.xbar_random_slow_rsp.3908114851 |
| Short name | T2780 |
| Test name | |
| Test status | |
| Simulation time | 57789611813 ps |
| CPU time | 684.59 seconds |
| Started | Aug 24 07:10:10 AM UTC 24 |
| Finished | Aug 24 07:21:42 AM UTC 24 |
| Peak memory | 598072 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3908114851 -assert nopostproc +UVM_T ESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 85.xbar_random_slow_rsp.3908114851 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/85.xbar_random_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/85.xbar_random_zero_delays.530928169 |
| Short name | T2654 |
| Test name | |
| Test status | |
| Simulation time | 402139431 ps |
| CPU time | 23.57 seconds |
| Started | Aug 24 07:09:57 AM UTC 24 |
| Finished | Aug 24 07:10:22 AM UTC 24 |
| Peak memory | 597948 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=530928169 -assert nopostpro c +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 85.xbar_random_zero_delays.530928169 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/85.xbar_random_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/85.xbar_same_source.4080381828 |
| Short name | T2666 |
| Test name | |
| Test status | |
| Simulation time | 2715235913 ps |
| CPU time | 57.51 seconds |
| Started | Aug 24 07:10:36 AM UTC 24 |
| Finished | Aug 24 07:11:35 AM UTC 24 |
| Peak memory | 597884 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4080381828 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 85.xbar_same_source.4080381828 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/85.xbar_same_source/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/85.xbar_smoke.3252003501 |
| Short name | T2650 |
| Test name | |
| Test status | |
| Simulation time | 49245881 ps |
| CPU time | 5.32 seconds |
| Started | Aug 24 07:09:49 AM UTC 24 |
| Finished | Aug 24 07:09:55 AM UTC 24 |
| Peak memory | 595848 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3252003501 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 8_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 85.xbar_smoke.3252003501 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/85.xbar_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/85.xbar_smoke_large_delays.3999955737 |
| Short name | T2661 |
| Test name | |
| Test status | |
| Simulation time | 10360851977 ps |
| CPU time | 85.01 seconds |
| Started | Aug 24 07:09:51 AM UTC 24 |
| Finished | Aug 24 07:11:18 AM UTC 24 |
| Peak memory | 595764 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max _device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3999955737 -assert nopostproc +U VM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 85.xbar_smoke_large_delays.3999955737 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/85.xbar_smoke_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/85.xbar_smoke_slow_rsp.3614202551 |
| Short name | T2657 |
| Test name | |
| Test status | |
| Simulation time | 5160801730 ps |
| CPU time | 62.8 seconds |
| Started | Aug 24 07:09:53 AM UTC 24 |
| Finished | Aug 24 07:10:57 AM UTC 24 |
| Peak memory | 595768 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3614202551 -assert nopostproc +UVM_T ESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 85.xbar_smoke_slow_rsp.3614202551 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/85.xbar_smoke_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/85.xbar_smoke_zero_delays.1753668354 |
| Short name | T2651 |
| Test name | |
| Test status | |
| Simulation time | 44556201 ps |
| CPU time | 4.96 seconds |
| Started | Aug 24 07:09:50 AM UTC 24 |
| Finished | Aug 24 07:09:55 AM UTC 24 |
| Peak memory | 595632 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1753668354 -assert nopostpr oc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 85.xbar_smoke_zero_delays.1753668354 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/85.xbar_smoke_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/85.xbar_stress_all.2530353285 |
| Short name | T2675 |
| Test name | |
| Test status | |
| Simulation time | 3423106480 ps |
| CPU time | 76.98 seconds |
| Started | Aug 24 07:11:15 AM UTC 24 |
| Finished | Aug 24 07:12:34 AM UTC 24 |
| Peak memory | 597960 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2530353285 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 85.xbar_stress_all.2530353285 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/85.xbar_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/85.xbar_stress_all_with_error.1281919227 |
| Short name | T2698 |
| Test name | |
| Test status | |
| Simulation time | 8903755765 ps |
| CPU time | 196.71 seconds |
| Started | Aug 24 07:11:22 AM UTC 24 |
| Finished | Aug 24 07:14:42 AM UTC 24 |
| Peak memory | 597888 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1281919227 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 85.xbar_stress_all_with_error.1281919227 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/85.xbar_stress_all_with_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/85.xbar_stress_all_with_rand_reset.1012446572 |
| Short name | T2664 |
| Test name | |
| Test status | |
| Simulation time | 8915417 ps |
| CPU time | 10.33 seconds |
| Started | Aug 24 07:11:21 AM UTC 24 |
| Finished | Aug 24 07:11:33 AM UTC 24 |
| Peak memory | 597680 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1012446572 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 85.xbar_stress_all_with_rand_reset.1012446572 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/85.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/85.xbar_stress_all_with_reset_error.3312459192 |
| Short name | T2671 |
| Test name | |
| Test status | |
| Simulation time | 171463925 ps |
| CPU time | 19.06 seconds |
| Started | Aug 24 07:11:33 AM UTC 24 |
| Finished | Aug 24 07:11:53 AM UTC 24 |
| Peak memory | 597920 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3312459192 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 85.xbar_stress_all_with_reset_error.3312459192 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/85.xbar_stress_all_with_reset_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/85.xbar_unmapped_addr.3357026337 |
| Short name | T2662 |
| Test name | |
| Test status | |
| Simulation time | 198504168 ps |
| CPU time | 18.59 seconds |
| Started | Aug 24 07:11:02 AM UTC 24 |
| Finished | Aug 24 07:11:22 AM UTC 24 |
| Peak memory | 597760 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3357026337 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 85.xbar_unmapped_addr.3357026337 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/85.xbar_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/86.xbar_access_same_device.1559960340 |
| Short name | T2681 |
| Test name | |
| Test status | |
| Simulation time | 2238781351 ps |
| CPU time | 63.25 seconds |
| Started | Aug 24 07:12:06 AM UTC 24 |
| Finished | Aug 24 07:13:11 AM UTC 24 |
| Peak memory | 597768 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1559960340 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 86.xbar_access_same_device.1559960340 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/86.xbar_access_same_device/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/86.xbar_access_same_device_slow_rsp.3575832611 |
| Short name | T2744 |
| Test name | |
| Test status | |
| Simulation time | 32441131650 ps |
| CPU time | 398.15 seconds |
| Started | Aug 24 07:12:07 AM UTC 24 |
| Finished | Aug 24 07:18:50 AM UTC 24 |
| Peak memory | 597884 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3575832611 -assert nopostproc +UVM_T ESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 86.xbar_access_same_device_slow_rsp.3575832611 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/86.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/86.xbar_error_and_unmapped_addr.3355089101 |
| Short name | T2684 |
| Test name | |
| Test status | |
| Simulation time | 891601997 ps |
| CPU time | 25.88 seconds |
| Started | Aug 24 07:12:48 AM UTC 24 |
| Finished | Aug 24 07:13:16 AM UTC 24 |
| Peak memory | 597696 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3355089101 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 86.xbar_error_and_unmapped_addr.3355089101 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/86.xbar_error_and_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/86.xbar_error_random.3939414840 |
| Short name | T2678 |
| Test name | |
| Test status | |
| Simulation time | 138854963 ps |
| CPU time | 9.39 seconds |
| Started | Aug 24 07:12:35 AM UTC 24 |
| Finished | Aug 24 07:12:46 AM UTC 24 |
| Peak memory | 597688 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3939414840 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 86.xbar_error_random.3939414840 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/86.xbar_error_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/86.xbar_random.3734128814 |
| Short name | T2676 |
| Test name | |
| Test status | |
| Simulation time | 1944758973 ps |
| CPU time | 49.18 seconds |
| Started | Aug 24 07:11:50 AM UTC 24 |
| Finished | Aug 24 07:12:40 AM UTC 24 |
| Peak memory | 597828 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3734128814 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 86.xbar_random.3734128814 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/86.xbar_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/86.xbar_random_large_delays.3040094967 |
| Short name | T2677 |
| Test name | |
| Test status | |
| Simulation time | 5093406190 ps |
| CPU time | 42.64 seconds |
| Started | Aug 24 07:11:59 AM UTC 24 |
| Finished | Aug 24 07:12:43 AM UTC 24 |
| Peak memory | 595772 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max _device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3040094967 -assert nopostproc +U VM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 86.xbar_random_large_delays.3040094967 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/86.xbar_random_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/86.xbar_random_slow_rsp.684152577 |
| Short name | T2729 |
| Test name | |
| Test status | |
| Simulation time | 29232105908 ps |
| CPU time | 333.91 seconds |
| Started | Aug 24 07:11:59 AM UTC 24 |
| Finished | Aug 24 07:17:37 AM UTC 24 |
| Peak memory | 597828 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=684152577 -assert nopostproc +UVM_TE STNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 86.xbar_random_slow_rsp.684152577 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/86.xbar_random_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/86.xbar_random_zero_delays.2183888400 |
| Short name | T2673 |
| Test name | |
| Test status | |
| Simulation time | 381788835 ps |
| CPU time | 26.09 seconds |
| Started | Aug 24 07:11:53 AM UTC 24 |
| Finished | Aug 24 07:12:21 AM UTC 24 |
| Peak memory | 597908 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2183888400 -assert nopostpr oc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 86.xbar_random_zero_delays.2183888400 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/86.xbar_random_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/86.xbar_same_source.1515099052 |
| Short name | T2686 |
| Test name | |
| Test status | |
| Simulation time | 2237043966 ps |
| CPU time | 46.35 seconds |
| Started | Aug 24 07:12:30 AM UTC 24 |
| Finished | Aug 24 07:13:18 AM UTC 24 |
| Peak memory | 597760 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1515099052 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 86.xbar_same_source.1515099052 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/86.xbar_same_source/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/86.xbar_smoke.4168957673 |
| Short name | T2669 |
| Test name | |
| Test status | |
| Simulation time | 225213139 ps |
| CPU time | 7.45 seconds |
| Started | Aug 24 07:11:36 AM UTC 24 |
| Finished | Aug 24 07:11:45 AM UTC 24 |
| Peak memory | 595912 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4168957673 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 8_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 86.xbar_smoke.4168957673 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/86.xbar_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/86.xbar_smoke_large_delays.643270773 |
| Short name | T2451 |
| Test name | |
| Test status | |
| Simulation time | 6999960842 ps |
| CPU time | 56.1 seconds |
| Started | Aug 24 07:11:47 AM UTC 24 |
| Finished | Aug 24 07:12:44 AM UTC 24 |
| Peak memory | 595828 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max _device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=643270773 -assert nopostproc +UV M_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 86.xbar_smoke_large_delays.643270773 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/86.xbar_smoke_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/86.xbar_smoke_slow_rsp.1460100825 |
| Short name | T2679 |
| Test name | |
| Test status | |
| Simulation time | 5512392134 ps |
| CPU time | 63.18 seconds |
| Started | Aug 24 07:11:48 AM UTC 24 |
| Finished | Aug 24 07:12:53 AM UTC 24 |
| Peak memory | 595768 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1460100825 -assert nopostproc +UVM_T ESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 86.xbar_smoke_slow_rsp.1460100825 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/86.xbar_smoke_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/86.xbar_smoke_zero_delays.3763537081 |
| Short name | T2668 |
| Test name | |
| Test status | |
| Simulation time | 49415480 ps |
| CPU time | 5.4 seconds |
| Started | Aug 24 07:11:38 AM UTC 24 |
| Finished | Aug 24 07:11:44 AM UTC 24 |
| Peak memory | 595940 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3763537081 -assert nopostpr oc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 86.xbar_smoke_zero_delays.3763537081 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/86.xbar_smoke_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/86.xbar_stress_all.2326872109 |
| Short name | T2688 |
| Test name | |
| Test status | |
| Simulation time | 710155461 ps |
| CPU time | 47.42 seconds |
| Started | Aug 24 07:12:54 AM UTC 24 |
| Finished | Aug 24 07:13:43 AM UTC 24 |
| Peak memory | 597700 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2326872109 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 86.xbar_stress_all.2326872109 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/86.xbar_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/86.xbar_stress_all_with_error.1465112283 |
| Short name | T2711 |
| Test name | |
| Test status | |
| Simulation time | 6585073606 ps |
| CPU time | 166.21 seconds |
| Started | Aug 24 07:12:59 AM UTC 24 |
| Finished | Aug 24 07:15:47 AM UTC 24 |
| Peak memory | 598100 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1465112283 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 86.xbar_stress_all_with_error.1465112283 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/86.xbar_stress_all_with_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/86.xbar_stress_all_with_rand_reset.1145884435 |
| Short name | T2712 |
| Test name | |
| Test status | |
| Simulation time | 814478725 ps |
| CPU time | 174.34 seconds |
| Started | Aug 24 07:12:58 AM UTC 24 |
| Finished | Aug 24 07:15:54 AM UTC 24 |
| Peak memory | 597756 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1145884435 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 86.xbar_stress_all_with_rand_reset.1145884435 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/86.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/86.xbar_stress_all_with_reset_error.3110323328 |
| Short name | T2763 |
| Test name | |
| Test status | |
| Simulation time | 13792561540 ps |
| CPU time | 425.58 seconds |
| Started | Aug 24 07:13:01 AM UTC 24 |
| Finished | Aug 24 07:20:11 AM UTC 24 |
| Peak memory | 597824 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3110323328 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 86.xbar_stress_all_with_reset_error.3110323328 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/86.xbar_stress_all_with_reset_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/86.xbar_unmapped_addr.2823539654 |
| Short name | T2685 |
| Test name | |
| Test status | |
| Simulation time | 1220005827 ps |
| CPU time | 38.54 seconds |
| Started | Aug 24 07:12:37 AM UTC 24 |
| Finished | Aug 24 07:13:17 AM UTC 24 |
| Peak memory | 597692 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2823539654 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 86.xbar_unmapped_addr.2823539654 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/86.xbar_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/87.xbar_access_same_device.2295732638 |
| Short name | T2701 |
| Test name | |
| Test status | |
| Simulation time | 1315390170 ps |
| CPU time | 59.41 seconds |
| Started | Aug 24 07:13:44 AM UTC 24 |
| Finished | Aug 24 07:14:45 AM UTC 24 |
| Peak memory | 597924 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2295732638 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 87.xbar_access_same_device.2295732638 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/87.xbar_access_same_device/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/87.xbar_access_same_device_slow_rsp.2687885330 |
| Short name | T2932 |
| Test name | |
| Test status | |
| Simulation time | 129826529633 ps |
| CPU time | 1544.63 seconds |
| Started | Aug 24 07:13:57 AM UTC 24 |
| Finished | Aug 24 07:39:57 AM UTC 24 |
| Peak memory | 598788 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2687885330 -assert nopostproc +UVM_T ESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 87.xbar_access_same_device_slow_rsp.2687885330 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/87.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/87.xbar_error_and_unmapped_addr.1840100380 |
| Short name | T2699 |
| Test name | |
| Test status | |
| Simulation time | 304452117 ps |
| CPU time | 22.86 seconds |
| Started | Aug 24 07:14:20 AM UTC 24 |
| Finished | Aug 24 07:14:44 AM UTC 24 |
| Peak memory | 597844 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1840100380 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 87.xbar_error_and_unmapped_addr.1840100380 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/87.xbar_error_and_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/87.xbar_error_random.600207592 |
| Short name | T2700 |
| Test name | |
| Test status | |
| Simulation time | 536445853 ps |
| CPU time | 28.81 seconds |
| Started | Aug 24 07:14:14 AM UTC 24 |
| Finished | Aug 24 07:14:44 AM UTC 24 |
| Peak memory | 598008 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=600207592 -assert nopostproc +UVM_TESTNAME =xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 87.xbar_error_random.600207592 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/87.xbar_error_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/87.xbar_random.1806449410 |
| Short name | T2693 |
| Test name | |
| Test status | |
| Simulation time | 1498443988 ps |
| CPU time | 39.34 seconds |
| Started | Aug 24 07:13:28 AM UTC 24 |
| Finished | Aug 24 07:14:09 AM UTC 24 |
| Peak memory | 597828 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1806449410 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 87.xbar_random.1806449410 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/87.xbar_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/87.xbar_random_large_delays.3499478762 |
| Short name | T2736 |
| Test name | |
| Test status | |
| Simulation time | 32436892530 ps |
| CPU time | 260.88 seconds |
| Started | Aug 24 07:13:31 AM UTC 24 |
| Finished | Aug 24 07:17:55 AM UTC 24 |
| Peak memory | 597960 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max _device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3499478762 -assert nopostproc +U VM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 87.xbar_random_large_delays.3499478762 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/87.xbar_random_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/87.xbar_random_slow_rsp.2236681550 |
| Short name | T2733 |
| Test name | |
| Test status | |
| Simulation time | 21946100137 ps |
| CPU time | 253.98 seconds |
| Started | Aug 24 07:13:32 AM UTC 24 |
| Finished | Aug 24 07:17:49 AM UTC 24 |
| Peak memory | 597884 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2236681550 -assert nopostproc +UVM_T ESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 87.xbar_random_slow_rsp.2236681550 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/87.xbar_random_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/87.xbar_random_zero_delays.1029148998 |
| Short name | T2690 |
| Test name | |
| Test status | |
| Simulation time | 454858723 ps |
| CPU time | 28.34 seconds |
| Started | Aug 24 07:13:30 AM UTC 24 |
| Finished | Aug 24 07:14:00 AM UTC 24 |
| Peak memory | 597760 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1029148998 -assert nopostpr oc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 87.xbar_random_zero_delays.1029148998 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/87.xbar_random_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/87.xbar_same_source.1676984383 |
| Short name | T2702 |
| Test name | |
| Test status | |
| Simulation time | 2622653610 ps |
| CPU time | 52.22 seconds |
| Started | Aug 24 07:13:59 AM UTC 24 |
| Finished | Aug 24 07:14:53 AM UTC 24 |
| Peak memory | 597752 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1676984383 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 87.xbar_same_source.1676984383 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/87.xbar_same_source/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/87.xbar_smoke.1690350669 |
| Short name | T2683 |
| Test name | |
| Test status | |
| Simulation time | 176138867 ps |
| CPU time | 6.35 seconds |
| Started | Aug 24 07:13:07 AM UTC 24 |
| Finished | Aug 24 07:13:14 AM UTC 24 |
| Peak memory | 595632 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1690350669 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 8_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 87.xbar_smoke.1690350669 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/87.xbar_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/87.xbar_smoke_large_delays.1993854661 |
| Short name | T2696 |
| Test name | |
| Test status | |
| Simulation time | 7708943065 ps |
| CPU time | 67.9 seconds |
| Started | Aug 24 07:13:25 AM UTC 24 |
| Finished | Aug 24 07:14:34 AM UTC 24 |
| Peak memory | 595828 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max _device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1993854661 -assert nopostproc +U VM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 87.xbar_smoke_large_delays.1993854661 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/87.xbar_smoke_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/87.xbar_smoke_slow_rsp.1443682669 |
| Short name | T2695 |
| Test name | |
| Test status | |
| Simulation time | 4134170319 ps |
| CPU time | 54.9 seconds |
| Started | Aug 24 07:13:26 AM UTC 24 |
| Finished | Aug 24 07:14:22 AM UTC 24 |
| Peak memory | 595848 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1443682669 -assert nopostproc +UVM_T ESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 87.xbar_smoke_slow_rsp.1443682669 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/87.xbar_smoke_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/87.xbar_smoke_zero_delays.3435892930 |
| Short name | T2687 |
| Test name | |
| Test status | |
| Simulation time | 45555774 ps |
| CPU time | 4.99 seconds |
| Started | Aug 24 07:13:24 AM UTC 24 |
| Finished | Aug 24 07:13:30 AM UTC 24 |
| Peak memory | 595860 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3435892930 -assert nopostpr oc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 87.xbar_smoke_zero_delays.3435892930 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/87.xbar_smoke_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/87.xbar_stress_all.2033919802 |
| Short name | T2753 |
| Test name | |
| Test status | |
| Simulation time | 11785193135 ps |
| CPU time | 292.32 seconds |
| Started | Aug 24 07:14:22 AM UTC 24 |
| Finished | Aug 24 07:19:18 AM UTC 24 |
| Peak memory | 597964 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2033919802 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 87.xbar_stress_all.2033919802 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/87.xbar_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/87.xbar_stress_all_with_error.2088426916 |
| Short name | T2747 |
| Test name | |
| Test status | |
| Simulation time | 10150889305 ps |
| CPU time | 261.25 seconds |
| Started | Aug 24 07:14:37 AM UTC 24 |
| Finished | Aug 24 07:19:01 AM UTC 24 |
| Peak memory | 597888 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2088426916 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 87.xbar_stress_all_with_error.2088426916 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/87.xbar_stress_all_with_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/87.xbar_stress_all_with_rand_reset.3595515639 |
| Short name | T2705 |
| Test name | |
| Test status | |
| Simulation time | 117282574 ps |
| CPU time | 30.16 seconds |
| Started | Aug 24 07:14:36 AM UTC 24 |
| Finished | Aug 24 07:15:07 AM UTC 24 |
| Peak memory | 597916 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3595515639 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 87.xbar_stress_all_with_rand_reset.3595515639 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/87.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/87.xbar_stress_all_with_reset_error.2413780850 |
| Short name | T2718 |
| Test name | |
| Test status | |
| Simulation time | 348081674 ps |
| CPU time | 80.15 seconds |
| Started | Aug 24 07:14:49 AM UTC 24 |
| Finished | Aug 24 07:16:10 AM UTC 24 |
| Peak memory | 597696 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2413780850 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 87.xbar_stress_all_with_reset_error.2413780850 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/87.xbar_stress_all_with_reset_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/87.xbar_unmapped_addr.586163330 |
| Short name | T2694 |
| Test name | |
| Test status | |
| Simulation time | 19474245 ps |
| CPU time | 4.43 seconds |
| Started | Aug 24 07:14:15 AM UTC 24 |
| Finished | Aug 24 07:14:21 AM UTC 24 |
| Peak memory | 595776 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=586163330 -assert nopostproc +UVM_TESTNAME =xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 87.xbar_unmapped_addr.586163330 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/87.xbar_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/88.xbar_access_same_device.3638133953 |
| Short name | T2715 |
| Test name | |
| Test status | |
| Simulation time | 671501727 ps |
| CPU time | 47.07 seconds |
| Started | Aug 24 07:15:15 AM UTC 24 |
| Finished | Aug 24 07:16:04 AM UTC 24 |
| Peak memory | 597924 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3638133953 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 88.xbar_access_same_device.3638133953 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/88.xbar_access_same_device/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/88.xbar_access_same_device_slow_rsp.1773456031 |
| Short name | T2917 |
| Test name | |
| Test status | |
| Simulation time | 98409919744 ps |
| CPU time | 1108.02 seconds |
| Started | Aug 24 07:15:21 AM UTC 24 |
| Finished | Aug 24 07:34:00 AM UTC 24 |
| Peak memory | 598788 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1773456031 -assert nopostproc +UVM_T ESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 88.xbar_access_same_device_slow_rsp.1773456031 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/88.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/88.xbar_error_and_unmapped_addr.2464180099 |
| Short name | T2714 |
| Test name | |
| Test status | |
| Simulation time | 23857311 ps |
| CPU time | 4.39 seconds |
| Started | Aug 24 07:15:56 AM UTC 24 |
| Finished | Aug 24 07:16:01 AM UTC 24 |
| Peak memory | 595856 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2464180099 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 88.xbar_error_and_unmapped_addr.2464180099 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/88.xbar_error_and_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/88.xbar_error_random.3332672682 |
| Short name | T2713 |
| Test name | |
| Test status | |
| Simulation time | 451103039 ps |
| CPU time | 25.04 seconds |
| Started | Aug 24 07:15:34 AM UTC 24 |
| Finished | Aug 24 07:16:01 AM UTC 24 |
| Peak memory | 597920 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3332672682 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 88.xbar_error_random.3332672682 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/88.xbar_error_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/88.xbar_random.1204241308 |
| Short name | T2707 |
| Test name | |
| Test status | |
| Simulation time | 306344604 ps |
| CPU time | 19.88 seconds |
| Started | Aug 24 07:14:59 AM UTC 24 |
| Finished | Aug 24 07:15:20 AM UTC 24 |
| Peak memory | 597756 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1204241308 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 88.xbar_random.1204241308 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/88.xbar_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/88.xbar_random_large_delays.1352630680 |
| Short name | T2872 |
| Test name | |
| Test status | |
| Simulation time | 103739245361 ps |
| CPU time | 823.86 seconds |
| Started | Aug 24 07:15:12 AM UTC 24 |
| Finished | Aug 24 07:29:06 AM UTC 24 |
| Peak memory | 597828 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max _device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1352630680 -assert nopostproc +U VM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 88.xbar_random_large_delays.1352630680 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/88.xbar_random_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/88.xbar_random_slow_rsp.2804670344 |
| Short name | T2817 |
| Test name | |
| Test status | |
| Simulation time | 46913902387 ps |
| CPU time | 544.2 seconds |
| Started | Aug 24 07:15:14 AM UTC 24 |
| Finished | Aug 24 07:24:25 AM UTC 24 |
| Peak memory | 597824 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2804670344 -assert nopostproc +UVM_T ESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 88.xbar_random_slow_rsp.2804670344 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/88.xbar_random_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/88.xbar_random_zero_delays.2532227705 |
| Short name | T2706 |
| Test name | |
| Test status | |
| Simulation time | 104348254 ps |
| CPU time | 8.92 seconds |
| Started | Aug 24 07:15:07 AM UTC 24 |
| Finished | Aug 24 07:15:17 AM UTC 24 |
| Peak memory | 597836 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2532227705 -assert nopostpr oc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 88.xbar_random_zero_delays.2532227705 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/88.xbar_random_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/88.xbar_same_source.3369884864 |
| Short name | T2710 |
| Test name | |
| Test status | |
| Simulation time | 381964673 ps |
| CPU time | 10.29 seconds |
| Started | Aug 24 07:15:31 AM UTC 24 |
| Finished | Aug 24 07:15:43 AM UTC 24 |
| Peak memory | 597676 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3369884864 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 88.xbar_same_source.3369884864 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/88.xbar_same_source/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/88.xbar_smoke.957836844 |
| Short name | T2703 |
| Test name | |
| Test status | |
| Simulation time | 185087734 ps |
| CPU time | 6.46 seconds |
| Started | Aug 24 07:14:51 AM UTC 24 |
| Finished | Aug 24 07:14:58 AM UTC 24 |
| Peak memory | 595940 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=957836844 -assert nopostproc +UVM_TESTNAME =xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08 _22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 88.xbar_smoke.957836844 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/88.xbar_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/88.xbar_smoke_large_delays.3095954913 |
| Short name | T2716 |
| Test name | |
| Test status | |
| Simulation time | 7821346097 ps |
| CPU time | 65.63 seconds |
| Started | Aug 24 07:14:58 AM UTC 24 |
| Finished | Aug 24 07:16:05 AM UTC 24 |
| Peak memory | 595764 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max _device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3095954913 -assert nopostproc +U VM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 88.xbar_smoke_large_delays.3095954913 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/88.xbar_smoke_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/88.xbar_smoke_slow_rsp.3124470314 |
| Short name | T2717 |
| Test name | |
| Test status | |
| Simulation time | 5876674986 ps |
| CPU time | 69.03 seconds |
| Started | Aug 24 07:14:59 AM UTC 24 |
| Finished | Aug 24 07:16:09 AM UTC 24 |
| Peak memory | 595912 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3124470314 -assert nopostproc +UVM_T ESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 88.xbar_smoke_slow_rsp.3124470314 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/88.xbar_smoke_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/88.xbar_smoke_zero_delays.3616928169 |
| Short name | T2704 |
| Test name | |
| Test status | |
| Simulation time | 37434385 ps |
| CPU time | 4.51 seconds |
| Started | Aug 24 07:14:56 AM UTC 24 |
| Finished | Aug 24 07:15:01 AM UTC 24 |
| Peak memory | 595700 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3616928169 -assert nopostpr oc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 88.xbar_smoke_zero_delays.3616928169 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/88.xbar_smoke_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/88.xbar_stress_all.3493744224 |
| Short name | T2759 |
| Test name | |
| Test status | |
| Simulation time | 8465139283 ps |
| CPU time | 221.04 seconds |
| Started | Aug 24 07:15:57 AM UTC 24 |
| Finished | Aug 24 07:19:41 AM UTC 24 |
| Peak memory | 597952 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3493744224 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 88.xbar_stress_all.3493744224 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/88.xbar_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/88.xbar_stress_all_with_error.279782974 |
| Short name | T2743 |
| Test name | |
| Test status | |
| Simulation time | 6646330140 ps |
| CPU time | 153.53 seconds |
| Started | Aug 24 07:16:09 AM UTC 24 |
| Finished | Aug 24 07:18:45 AM UTC 24 |
| Peak memory | 598084 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=279782974 -assert nopostproc +UVM_TESTNAME =xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 88.xbar_stress_all_with_error.279782974 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/88.xbar_stress_all_with_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/88.xbar_stress_all_with_rand_reset.352634321 |
| Short name | T2722 |
| Test name | |
| Test status | |
| Simulation time | 38748877 ps |
| CPU time | 27.92 seconds |
| Started | Aug 24 07:16:02 AM UTC 24 |
| Finished | Aug 24 07:16:31 AM UTC 24 |
| Peak memory | 597688 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=352634321 -assert nopostproc +UVM_TESTNAME =xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 88.xbar_stress_all_with_rand_reset.352634321 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/88.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/88.xbar_stress_all_with_reset_error.1523453622 |
| Short name | T2739 |
| Test name | |
| Test status | |
| Simulation time | 534208767 ps |
| CPU time | 130.71 seconds |
| Started | Aug 24 07:16:15 AM UTC 24 |
| Finished | Aug 24 07:18:28 AM UTC 24 |
| Peak memory | 597656 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1523453622 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 88.xbar_stress_all_with_reset_error.1523453622 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/88.xbar_stress_all_with_reset_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/88.xbar_unmapped_addr.874465730 |
| Short name | T2719 |
| Test name | |
| Test status | |
| Simulation time | 1255157104 ps |
| CPU time | 36.12 seconds |
| Started | Aug 24 07:15:40 AM UTC 24 |
| Finished | Aug 24 07:16:18 AM UTC 24 |
| Peak memory | 597832 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=874465730 -assert nopostproc +UVM_TESTNAME =xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 88.xbar_unmapped_addr.874465730 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/88.xbar_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/89.xbar_access_same_device.4203630321 |
| Short name | T2726 |
| Test name | |
| Test status | |
| Simulation time | 499653724 ps |
| CPU time | 26.81 seconds |
| Started | Aug 24 07:16:45 AM UTC 24 |
| Finished | Aug 24 07:17:13 AM UTC 24 |
| Peak memory | 597708 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4203630321 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 89.xbar_access_same_device.4203630321 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/89.xbar_access_same_device/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/89.xbar_access_same_device_slow_rsp.1255290973 |
| Short name | T2863 |
| Test name | |
| Test status | |
| Simulation time | 55434671015 ps |
| CPU time | 666.55 seconds |
| Started | Aug 24 07:17:07 AM UTC 24 |
| Finished | Aug 24 07:28:21 AM UTC 24 |
| Peak memory | 597820 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1255290973 -assert nopostproc +UVM_T ESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 89.xbar_access_same_device_slow_rsp.1255290973 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/89.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/89.xbar_error_and_unmapped_addr.2593963086 |
| Short name | T2735 |
| Test name | |
| Test status | |
| Simulation time | 786805606 ps |
| CPU time | 22.01 seconds |
| Started | Aug 24 07:17:32 AM UTC 24 |
| Finished | Aug 24 07:17:55 AM UTC 24 |
| Peak memory | 597692 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2593963086 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 89.xbar_error_and_unmapped_addr.2593963086 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/89.xbar_error_and_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/89.xbar_error_random.2194537386 |
| Short name | T2730 |
| Test name | |
| Test status | |
| Simulation time | 1009402531 ps |
| CPU time | 23.26 seconds |
| Started | Aug 24 07:17:14 AM UTC 24 |
| Finished | Aug 24 07:17:38 AM UTC 24 |
| Peak memory | 597920 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2194537386 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 89.xbar_error_random.2194537386 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/89.xbar_error_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/89.xbar_random.515206022 |
| Short name | T2724 |
| Test name | |
| Test status | |
| Simulation time | 492772808 ps |
| CPU time | 29.54 seconds |
| Started | Aug 24 07:16:25 AM UTC 24 |
| Finished | Aug 24 07:16:56 AM UTC 24 |
| Peak memory | 597916 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=515206022 -assert nopostproc +UVM_TESTNAME =xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 8_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 89.xbar_random.515206022 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/89.xbar_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/89.xbar_random_large_delays.3904006372 |
| Short name | T2829 |
| Test name | |
| Test status | |
| Simulation time | 62377984091 ps |
| CPU time | 521.67 seconds |
| Started | Aug 24 07:16:37 AM UTC 24 |
| Finished | Aug 24 07:25:24 AM UTC 24 |
| Peak memory | 597820 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max _device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3904006372 -assert nopostproc +U VM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 89.xbar_random_large_delays.3904006372 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/89.xbar_random_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/89.xbar_random_slow_rsp.2851898445 |
| Short name | T2802 |
| Test name | |
| Test status | |
| Simulation time | 34854943514 ps |
| CPU time | 394.25 seconds |
| Started | Aug 24 07:16:38 AM UTC 24 |
| Finished | Aug 24 07:23:17 AM UTC 24 |
| Peak memory | 597816 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2851898445 -assert nopostproc +UVM_T ESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 89.xbar_random_slow_rsp.2851898445 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/89.xbar_random_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/89.xbar_random_zero_delays.1894613191 |
| Short name | T2723 |
| Test name | |
| Test status | |
| Simulation time | 300097243 ps |
| CPU time | 19.95 seconds |
| Started | Aug 24 07:16:32 AM UTC 24 |
| Finished | Aug 24 07:16:53 AM UTC 24 |
| Peak memory | 597760 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1894613191 -assert nopostpr oc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 89.xbar_random_zero_delays.1894613191 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/89.xbar_random_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/89.xbar_same_source.2365121308 |
| Short name | T2731 |
| Test name | |
| Test status | |
| Simulation time | 553974855 ps |
| CPU time | 27.43 seconds |
| Started | Aug 24 07:17:10 AM UTC 24 |
| Finished | Aug 24 07:17:39 AM UTC 24 |
| Peak memory | 597836 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2365121308 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 89.xbar_same_source.2365121308 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/89.xbar_same_source/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/89.xbar_smoke.1373980479 |
| Short name | T2720 |
| Test name | |
| Test status | |
| Simulation time | 237044099 ps |
| CPU time | 7.46 seconds |
| Started | Aug 24 07:16:15 AM UTC 24 |
| Finished | Aug 24 07:16:23 AM UTC 24 |
| Peak memory | 595600 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1373980479 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 8_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 89.xbar_smoke.1373980479 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/89.xbar_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/89.xbar_smoke_large_delays.3042033171 |
| Short name | T2727 |
| Test name | |
| Test status | |
| Simulation time | 7003344852 ps |
| CPU time | 57.21 seconds |
| Started | Aug 24 07:16:19 AM UTC 24 |
| Finished | Aug 24 07:17:18 AM UTC 24 |
| Peak memory | 595764 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max _device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3042033171 -assert nopostproc +U VM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 89.xbar_smoke_large_delays.3042033171 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/89.xbar_smoke_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/89.xbar_smoke_slow_rsp.660875834 |
| Short name | T2728 |
| Test name | |
| Test status | |
| Simulation time | 5579905738 ps |
| CPU time | 65.26 seconds |
| Started | Aug 24 07:16:24 AM UTC 24 |
| Finished | Aug 24 07:17:31 AM UTC 24 |
| Peak memory | 595992 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=660875834 -assert nopostproc +UVM_TE STNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 89.xbar_smoke_slow_rsp.660875834 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/89.xbar_smoke_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/89.xbar_smoke_zero_delays.738713832 |
| Short name | T2721 |
| Test name | |
| Test status | |
| Simulation time | 43689957 ps |
| CPU time | 5 seconds |
| Started | Aug 24 07:16:18 AM UTC 24 |
| Finished | Aug 24 07:16:24 AM UTC 24 |
| Peak memory | 595636 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=738713832 -assert nopostpro c +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 89.xbar_smoke_zero_delays.738713832 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/89.xbar_smoke_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/89.xbar_stress_all.1171741485 |
| Short name | T2778 |
| Test name | |
| Test status | |
| Simulation time | 8483064914 ps |
| CPU time | 225.9 seconds |
| Started | Aug 24 07:17:45 AM UTC 24 |
| Finished | Aug 24 07:21:34 AM UTC 24 |
| Peak memory | 597964 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1171741485 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 89.xbar_stress_all.1171741485 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/89.xbar_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/89.xbar_stress_all_with_error.1774253138 |
| Short name | T2783 |
| Test name | |
| Test status | |
| Simulation time | 4203997453 ps |
| CPU time | 228.6 seconds |
| Started | Aug 24 07:17:52 AM UTC 24 |
| Finished | Aug 24 07:21:43 AM UTC 24 |
| Peak memory | 598016 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1774253138 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 89.xbar_stress_all_with_error.1774253138 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/89.xbar_stress_all_with_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/89.xbar_stress_all_with_rand_reset.1098352843 |
| Short name | T2818 |
| Test name | |
| Test status | |
| Simulation time | 7355323687 ps |
| CPU time | 399.3 seconds |
| Started | Aug 24 07:17:51 AM UTC 24 |
| Finished | Aug 24 07:24:35 AM UTC 24 |
| Peak memory | 597820 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1098352843 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 89.xbar_stress_all_with_rand_reset.1098352843 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/89.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/89.xbar_stress_all_with_reset_error.574643949 |
| Short name | T2741 |
| Test name | |
| Test status | |
| Simulation time | 57166357 ps |
| CPU time | 39.38 seconds |
| Started | Aug 24 07:17:53 AM UTC 24 |
| Finished | Aug 24 07:18:33 AM UTC 24 |
| Peak memory | 598064 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=574643949 -assert nopostproc +UVM_TESTNAME =xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 89.xbar_stress_all_with_reset_error.574643949 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/89.xbar_stress_all_with_reset_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/89.xbar_unmapped_addr.1075932723 |
| Short name | T2734 |
| Test name | |
| Test status | |
| Simulation time | 829724514 ps |
| CPU time | 24.79 seconds |
| Started | Aug 24 07:17:27 AM UTC 24 |
| Finished | Aug 24 07:17:53 AM UTC 24 |
| Peak memory | 597688 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1075932723 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 89.xbar_unmapped_addr.1075932723 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/89.xbar_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/9.chip_csr_mem_rw_with_rand_reset.1671915989 |
| Short name | T1422 |
| Test name | |
| Test status | |
| Simulation time | 9108937250 ps |
| CPU time | 664.09 seconds |
| Started | Aug 24 04:27:54 AM UTC 24 |
| Finished | Aug 24 04:39:06 AM UTC 24 |
| Peak memory | 666456 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000 000000 +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/too ls/sim.tcl +ntb_random_seed=1671915989 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/nul l -cm_name 9.chip_csr_mem_rw_with_rand_reset.1671915989 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/9.chip_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/9.chip_csr_rw.3498805748 |
| Short name | T1418 |
| Test name | |
| Test status | |
| Simulation time | 6827348664 ps |
| CPU time | 504.92 seconds |
| Started | Aug 24 04:27:50 AM UTC 24 |
| Finished | Aug 24 04:36:22 AM UTC 24 |
| Peak memory | 619224 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +stub_cpu=1 +cdc_instrumentation_ena bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3498805748 -assert nopost proc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os _regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.chip_csr_rw.3498805748 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/9.chip_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/9.chip_same_csr_outstanding.92890656 |
| Short name | T423 |
| Test name | |
| Test status | |
| Simulation time | 17824235733 ps |
| CPU time | 1731.96 seconds |
| Started | Aug 24 04:24:33 AM UTC 24 |
| Finished | Aug 24 04:53:44 AM UTC 24 |
| Peak memory | 613148 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +test_timeout_ns=120_000_000 +run_same_csr_outstanding +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim .tcl +ntb_random_seed=92890656 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na me 9.chip_same_csr_outstanding.92890656 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/9.chip_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/9.chip_tl_errors.4151777192 |
| Short name | T561 |
| Test name | |
| Test status | |
| Simulation time | 3115115000 ps |
| CPU time | 141.41 seconds |
| Started | Aug 24 04:24:39 AM UTC 24 |
| Finished | Aug 24 04:27:03 AM UTC 24 |
| Peak memory | 619164 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enable d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4151777192 -assert nopostpro c +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.chip_tl_errors.4151777192 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/9.chip_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/9.xbar_access_same_device.1509822550 |
| Short name | T812 |
| Test name | |
| Test status | |
| Simulation time | 1575429967 ps |
| CPU time | 45.29 seconds |
| Started | Aug 24 04:26:39 AM UTC 24 |
| Finished | Aug 24 04:27:25 AM UTC 24 |
| Peak memory | 597704 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1509822550 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.xbar_access_same_device.1509822550 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/9.xbar_access_same_device/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/9.xbar_access_same_device_slow_rsp.252994335 |
| Short name | T821 |
| Test name | |
| Test status | |
| Simulation time | 17054004725 ps |
| CPU time | 205.36 seconds |
| Started | Aug 24 04:26:51 AM UTC 24 |
| Finished | Aug 24 04:30:19 AM UTC 24 |
| Peak memory | 597820 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=252994335 -assert nopostproc +UVM_TE STNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os _regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.xbar_access_same_device_slow_rsp.252994335 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/9.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/9.xbar_error_and_unmapped_addr.4160635083 |
| Short name | T1398 |
| Test name | |
| Test status | |
| Simulation time | 1389508728 ps |
| CPU time | 36.97 seconds |
| Started | Aug 24 04:27:21 AM UTC 24 |
| Finished | Aug 24 04:27:59 AM UTC 24 |
| Peak memory | 597876 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4160635083 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.xbar_error_and_unmapped_addr.4160635083 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/9.xbar_error_and_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/9.xbar_error_random.2505045599 |
| Short name | T1395 |
| Test name | |
| Test status | |
| Simulation time | 207058559 ps |
| CPU time | 14.59 seconds |
| Started | Aug 24 04:27:04 AM UTC 24 |
| Finished | Aug 24 04:27:20 AM UTC 24 |
| Peak memory | 597692 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2505045599 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.xbar_error_random.2505045599 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/9.xbar_error_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/9.xbar_random.4199205323 |
| Short name | T1390 |
| Test name | |
| Test status | |
| Simulation time | 31762255 ps |
| CPU time | 4.94 seconds |
| Started | Aug 24 04:25:30 AM UTC 24 |
| Finished | Aug 24 04:25:36 AM UTC 24 |
| Peak memory | 595704 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4199205323 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.xbar_random.4199205323 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/9.xbar_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/9.xbar_random_large_delays.585478887 |
| Short name | T1436 |
| Test name | |
| Test status | |
| Simulation time | 110539872392 ps |
| CPU time | 917.77 seconds |
| Started | Aug 24 04:26:19 AM UTC 24 |
| Finished | Aug 24 04:41:46 AM UTC 24 |
| Peak memory | 597820 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max _device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=585478887 -assert nopostproc +UV M_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.xbar_random_large_delays.585478887 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/9.xbar_random_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/9.xbar_random_slow_rsp.529564750 |
| Short name | T571 |
| Test name | |
| Test status | |
| Simulation time | 45480423668 ps |
| CPU time | 566.02 seconds |
| Started | Aug 24 04:26:31 AM UTC 24 |
| Finished | Aug 24 04:36:03 AM UTC 24 |
| Peak memory | 597892 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=529564750 -assert nopostproc +UVM_TE STNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.xbar_random_slow_rsp.529564750 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/9.xbar_random_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/9.xbar_random_zero_delays.1950475750 |
| Short name | T584 |
| Test name | |
| Test status | |
| Simulation time | 492140322 ps |
| CPU time | 34.07 seconds |
| Started | Aug 24 04:25:50 AM UTC 24 |
| Finished | Aug 24 04:26:25 AM UTC 24 |
| Peak memory | 597696 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1950475750 -assert nopostpr oc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.xbar_random_zero_delays.1950475750 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/9.xbar_random_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/9.xbar_same_source.2011807914 |
| Short name | T1394 |
| Test name | |
| Test status | |
| Simulation time | 233923267 ps |
| CPU time | 14.24 seconds |
| Started | Aug 24 04:26:52 AM UTC 24 |
| Finished | Aug 24 04:27:07 AM UTC 24 |
| Peak memory | 597692 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2011807914 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.xbar_same_source.2011807914 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/9.xbar_same_source/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/9.xbar_smoke.1310952668 |
| Short name | T1388 |
| Test name | |
| Test status | |
| Simulation time | 149498236 ps |
| CPU time | 6.67 seconds |
| Started | Aug 24 04:24:52 AM UTC 24 |
| Finished | Aug 24 04:25:00 AM UTC 24 |
| Peak memory | 595896 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1310952668 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 8_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.xbar_smoke.1310952668 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/9.xbar_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/9.xbar_smoke_large_delays.2126377419 |
| Short name | T1391 |
| Test name | |
| Test status | |
| Simulation time | 5766178561 ps |
| CPU time | 49.72 seconds |
| Started | Aug 24 04:25:13 AM UTC 24 |
| Finished | Aug 24 04:26:05 AM UTC 24 |
| Peak memory | 596084 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max _device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2126377419 -assert nopostproc +U VM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.xbar_smoke_large_delays.2126377419 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/9.xbar_smoke_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/9.xbar_smoke_slow_rsp.4266020054 |
| Short name | T1392 |
| Test name | |
| Test status | |
| Simulation time | 4249834012 ps |
| CPU time | 50.95 seconds |
| Started | Aug 24 04:25:23 AM UTC 24 |
| Finished | Aug 24 04:26:16 AM UTC 24 |
| Peak memory | 595932 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4266020054 -assert nopostproc +UVM_T ESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.xbar_smoke_slow_rsp.4266020054 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/9.xbar_smoke_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/9.xbar_smoke_zero_delays.2389087862 |
| Short name | T1389 |
| Test name | |
| Test status | |
| Simulation time | 52040143 ps |
| CPU time | 5.15 seconds |
| Started | Aug 24 04:25:02 AM UTC 24 |
| Finished | Aug 24 04:25:08 AM UTC 24 |
| Peak memory | 595636 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2389087862 -assert nopostpr oc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.xbar_smoke_zero_delays.2389087862 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/9.xbar_smoke_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/9.xbar_stress_all.2889970830 |
| Short name | T484 |
| Test name | |
| Test status | |
| Simulation time | 207009368 ps |
| CPU time | 14.9 seconds |
| Started | Aug 24 04:27:34 AM UTC 24 |
| Finished | Aug 24 04:27:50 AM UTC 24 |
| Peak memory | 597696 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2889970830 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.xbar_stress_all.2889970830 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/9.xbar_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/9.xbar_stress_all_with_error.3469664778 |
| Short name | T813 |
| Test name | |
| Test status | |
| Simulation time | 16992823545 ps |
| CPU time | 467.87 seconds |
| Started | Aug 24 04:27:45 AM UTC 24 |
| Finished | Aug 24 04:35:39 AM UTC 24 |
| Peak memory | 598036 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3469664778 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.xbar_stress_all_with_error.3469664778 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/9.xbar_stress_all_with_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/9.xbar_stress_all_with_rand_reset.3651682337 |
| Short name | T507 |
| Test name | |
| Test status | |
| Simulation time | 15280801353 ps |
| CPU time | 511.95 seconds |
| Started | Aug 24 04:27:40 AM UTC 24 |
| Finished | Aug 24 04:36:18 AM UTC 24 |
| Peak memory | 597824 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3651682337 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.xbar_stress_all_with_rand_reset.3651682337 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/9.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/9.xbar_stress_all_with_reset_error.3706752447 |
| Short name | T845 |
| Test name | |
| Test status | |
| Simulation time | 1484275884 ps |
| CPU time | 161.91 seconds |
| Started | Aug 24 04:27:46 AM UTC 24 |
| Finished | Aug 24 04:30:31 AM UTC 24 |
| Peak memory | 597696 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3706752447 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.xbar_stress_all_with_reset_error.3706752447 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/9.xbar_stress_all_with_reset_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/9.xbar_unmapped_addr.163883932 |
| Short name | T1397 |
| Test name | |
| Test status | |
| Simulation time | 312286248 ps |
| CPU time | 12.07 seconds |
| Started | Aug 24 04:27:18 AM UTC 24 |
| Finished | Aug 24 04:27:31 AM UTC 24 |
| Peak memory | 597752 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=163883932 -assert nopostproc +UVM_TESTNAME =xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.xbar_unmapped_addr.163883932 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/9.xbar_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/90.xbar_access_same_device.624391278 |
| Short name | T2748 |
| Test name | |
| Test status | |
| Simulation time | 533354350 ps |
| CPU time | 13.97 seconds |
| Started | Aug 24 07:18:47 AM UTC 24 |
| Finished | Aug 24 07:19:03 AM UTC 24 |
| Peak memory | 597768 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=624391278 -assert nopostproc +UVM_TESTNAME =xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 90.xbar_access_same_device.624391278 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/90.xbar_access_same_device/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/90.xbar_access_same_device_slow_rsp.3072182178 |
| Short name | T2800 |
| Test name | |
| Test status | |
| Simulation time | 23422584027 ps |
| CPU time | 262.6 seconds |
| Started | Aug 24 07:18:47 AM UTC 24 |
| Finished | Aug 24 07:23:14 AM UTC 24 |
| Peak memory | 597892 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3072182178 -assert nopostproc +UVM_T ESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 90.xbar_access_same_device_slow_rsp.3072182178 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/90.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/90.xbar_error_and_unmapped_addr.13893530 |
| Short name | T2755 |
| Test name | |
| Test status | |
| Simulation time | 485453758 ps |
| CPU time | 15.18 seconds |
| Started | Aug 24 07:19:08 AM UTC 24 |
| Finished | Aug 24 07:19:24 AM UTC 24 |
| Peak memory | 597692 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=13893530 -assert nopostproc +UVM_TESTNAME= xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 90.xbar_error_and_unmapped_addr.13893530 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/90.xbar_error_and_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/90.xbar_error_random.4229875995 |
| Short name | T2758 |
| Test name | |
| Test status | |
| Simulation time | 1490175684 ps |
| CPU time | 36.87 seconds |
| Started | Aug 24 07:19:00 AM UTC 24 |
| Finished | Aug 24 07:19:38 AM UTC 24 |
| Peak memory | 597984 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4229875995 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 90.xbar_error_random.4229875995 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/90.xbar_error_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/90.xbar_random.1674076622 |
| Short name | T2740 |
| Test name | |
| Test status | |
| Simulation time | 813515853 ps |
| CPU time | 21.01 seconds |
| Started | Aug 24 07:18:10 AM UTC 24 |
| Finished | Aug 24 07:18:32 AM UTC 24 |
| Peak memory | 597688 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1674076622 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 90.xbar_random.1674076622 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/90.xbar_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/90.xbar_random_large_delays.3348136017 |
| Short name | T2865 |
| Test name | |
| Test status | |
| Simulation time | 71877017566 ps |
| CPU time | 597.14 seconds |
| Started | Aug 24 07:18:26 AM UTC 24 |
| Finished | Aug 24 07:28:30 AM UTC 24 |
| Peak memory | 597820 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max _device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3348136017 -assert nopostproc +U VM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 90.xbar_random_large_delays.3348136017 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/90.xbar_random_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/90.xbar_random_slow_rsp.3154120664 |
| Short name | T2751 |
| Test name | |
| Test status | |
| Simulation time | 2379772968 ps |
| CPU time | 28.16 seconds |
| Started | Aug 24 07:18:43 AM UTC 24 |
| Finished | Aug 24 07:19:13 AM UTC 24 |
| Peak memory | 595704 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3154120664 -assert nopostproc +UVM_T ESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 90.xbar_random_slow_rsp.3154120664 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/90.xbar_random_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/90.xbar_random_zero_delays.934264796 |
| Short name | T2742 |
| Test name | |
| Test status | |
| Simulation time | 129489491 ps |
| CPU time | 9.99 seconds |
| Started | Aug 24 07:18:24 AM UTC 24 |
| Finished | Aug 24 07:18:35 AM UTC 24 |
| Peak memory | 597696 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=934264796 -assert nopostpro c +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 90.xbar_random_zero_delays.934264796 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/90.xbar_random_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/90.xbar_same_source.3963356062 |
| Short name | T2749 |
| Test name | |
| Test status | |
| Simulation time | 427688279 ps |
| CPU time | 11.01 seconds |
| Started | Aug 24 07:18:51 AM UTC 24 |
| Finished | Aug 24 07:19:03 AM UTC 24 |
| Peak memory | 597680 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3963356062 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 90.xbar_same_source.3963356062 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/90.xbar_same_source/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/90.xbar_smoke.201706787 |
| Short name | T2738 |
| Test name | |
| Test status | |
| Simulation time | 227961786 ps |
| CPU time | 7.32 seconds |
| Started | Aug 24 07:18:03 AM UTC 24 |
| Finished | Aug 24 07:18:12 AM UTC 24 |
| Peak memory | 595952 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=201706787 -assert nopostproc +UVM_TESTNAME =xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08 _22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 90.xbar_smoke.201706787 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/90.xbar_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/90.xbar_smoke_large_delays.390934924 |
| Short name | T2750 |
| Test name | |
| Test status | |
| Simulation time | 7112510920 ps |
| CPU time | 57.91 seconds |
| Started | Aug 24 07:18:08 AM UTC 24 |
| Finished | Aug 24 07:19:07 AM UTC 24 |
| Peak memory | 595832 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max _device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=390934924 -assert nopostproc +UV M_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 90.xbar_smoke_large_delays.390934924 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/90.xbar_smoke_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/90.xbar_smoke_slow_rsp.3637734151 |
| Short name | T2745 |
| Test name | |
| Test status | |
| Simulation time | 3472980193 ps |
| CPU time | 42.54 seconds |
| Started | Aug 24 07:18:09 AM UTC 24 |
| Finished | Aug 24 07:18:53 AM UTC 24 |
| Peak memory | 595760 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3637734151 -assert nopostproc +UVM_T ESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 90.xbar_smoke_slow_rsp.3637734151 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/90.xbar_smoke_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/90.xbar_smoke_zero_delays.3823237013 |
| Short name | T2737 |
| Test name | |
| Test status | |
| Simulation time | 43604122 ps |
| CPU time | 4.86 seconds |
| Started | Aug 24 07:18:04 AM UTC 24 |
| Finished | Aug 24 07:18:10 AM UTC 24 |
| Peak memory | 595632 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3823237013 -assert nopostpr oc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 90.xbar_smoke_zero_delays.3823237013 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/90.xbar_smoke_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/90.xbar_stress_all.310662887 |
| Short name | T2805 |
| Test name | |
| Test status | |
| Simulation time | 9486904065 ps |
| CPU time | 251.48 seconds |
| Started | Aug 24 07:19:10 AM UTC 24 |
| Finished | Aug 24 07:23:24 AM UTC 24 |
| Peak memory | 597892 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=310662887 -assert nopostproc +UVM_TESTNAME =xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 90.xbar_stress_all.310662887 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/90.xbar_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/90.xbar_stress_all_with_error.714903691 |
| Short name | T2764 |
| Test name | |
| Test status | |
| Simulation time | 992728160 ps |
| CPU time | 51.47 seconds |
| Started | Aug 24 07:19:17 AM UTC 24 |
| Finished | Aug 24 07:20:12 AM UTC 24 |
| Peak memory | 598076 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=714903691 -assert nopostproc +UVM_TESTNAME =xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 90.xbar_stress_all_with_error.714903691 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/90.xbar_stress_all_with_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/90.xbar_stress_all_with_rand_reset.3861714981 |
| Short name | T2768 |
| Test name | |
| Test status | |
| Simulation time | 287647980 ps |
| CPU time | 72.6 seconds |
| Started | Aug 24 07:19:16 AM UTC 24 |
| Finished | Aug 24 07:20:30 AM UTC 24 |
| Peak memory | 597688 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3861714981 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 90.xbar_stress_all_with_rand_reset.3861714981 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/90.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/90.xbar_stress_all_with_reset_error.1460775899 |
| Short name | T2773 |
| Test name | |
| Test status | |
| Simulation time | 885642465 ps |
| CPU time | 88.49 seconds |
| Started | Aug 24 07:19:18 AM UTC 24 |
| Finished | Aug 24 07:20:50 AM UTC 24 |
| Peak memory | 597924 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1460775899 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 90.xbar_stress_all_with_reset_error.1460775899 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/90.xbar_stress_all_with_reset_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/90.xbar_unmapped_addr.3331810206 |
| Short name | T2752 |
| Test name | |
| Test status | |
| Simulation time | 272366575 ps |
| CPU time | 10.91 seconds |
| Started | Aug 24 07:19:05 AM UTC 24 |
| Finished | Aug 24 07:19:17 AM UTC 24 |
| Peak memory | 597944 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3331810206 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 90.xbar_unmapped_addr.3331810206 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/90.xbar_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/91.xbar_access_same_device.2972988242 |
| Short name | T2761 |
| Test name | |
| Test status | |
| Simulation time | 15425378 ps |
| CPU time | 4.94 seconds |
| Started | Aug 24 07:19:52 AM UTC 24 |
| Finished | Aug 24 07:19:58 AM UTC 24 |
| Peak memory | 595876 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2972988242 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 91.xbar_access_same_device.2972988242 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/91.xbar_access_same_device/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/91.xbar_access_same_device_slow_rsp.1786482288 |
| Short name | T2874 |
| Test name | |
| Test status | |
| Simulation time | 49266549913 ps |
| CPU time | 549.58 seconds |
| Started | Aug 24 07:19:55 AM UTC 24 |
| Finished | Aug 24 07:29:11 AM UTC 24 |
| Peak memory | 597820 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1786482288 -assert nopostproc +UVM_T ESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 91.xbar_access_same_device_slow_rsp.1786482288 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/91.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/91.xbar_error_and_unmapped_addr.2356846661 |
| Short name | T2769 |
| Test name | |
| Test status | |
| Simulation time | 127317816 ps |
| CPU time | 6.14 seconds |
| Started | Aug 24 07:20:26 AM UTC 24 |
| Finished | Aug 24 07:20:33 AM UTC 24 |
| Peak memory | 595704 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2356846661 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 91.xbar_error_and_unmapped_addr.2356846661 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/91.xbar_error_and_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/91.xbar_error_random.3517342617 |
| Short name | T2767 |
| Test name | |
| Test status | |
| Simulation time | 198088738 ps |
| CPU time | 12.16 seconds |
| Started | Aug 24 07:20:13 AM UTC 24 |
| Finished | Aug 24 07:20:26 AM UTC 24 |
| Peak memory | 597752 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3517342617 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 91.xbar_error_random.3517342617 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/91.xbar_error_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/91.xbar_random.699713210 |
| Short name | T2771 |
| Test name | |
| Test status | |
| Simulation time | 2360078502 ps |
| CPU time | 56.43 seconds |
| Started | Aug 24 07:19:38 AM UTC 24 |
| Finished | Aug 24 07:20:36 AM UTC 24 |
| Peak memory | 597980 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=699713210 -assert nopostproc +UVM_TESTNAME =xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 8_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 91.xbar_random.699713210 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/91.xbar_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/91.xbar_random_large_delays.608373029 |
| Short name | T2914 |
| Test name | |
| Test status | |
| Simulation time | 96476500261 ps |
| CPU time | 800.14 seconds |
| Started | Aug 24 07:19:46 AM UTC 24 |
| Finished | Aug 24 07:33:15 AM UTC 24 |
| Peak memory | 598604 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max _device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=608373029 -assert nopostproc +UV M_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 91.xbar_random_large_delays.608373029 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/91.xbar_random_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/91.xbar_random_slow_rsp.3334701592 |
| Short name | T2870 |
| Test name | |
| Test status | |
| Simulation time | 45854629744 ps |
| CPU time | 538.51 seconds |
| Started | Aug 24 07:19:46 AM UTC 24 |
| Finished | Aug 24 07:28:51 AM UTC 24 |
| Peak memory | 598108 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3334701592 -assert nopostproc +UVM_T ESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 91.xbar_random_slow_rsp.3334701592 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/91.xbar_random_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/91.xbar_random_zero_delays.1243567191 |
| Short name | T2762 |
| Test name | |
| Test status | |
| Simulation time | 440572356 ps |
| CPU time | 27.89 seconds |
| Started | Aug 24 07:19:38 AM UTC 24 |
| Finished | Aug 24 07:20:07 AM UTC 24 |
| Peak memory | 598004 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1243567191 -assert nopostpr oc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 91.xbar_random_zero_delays.1243567191 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/91.xbar_random_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/91.xbar_same_source.1463086558 |
| Short name | T2766 |
| Test name | |
| Test status | |
| Simulation time | 542454827 ps |
| CPU time | 12.53 seconds |
| Started | Aug 24 07:20:02 AM UTC 24 |
| Finished | Aug 24 07:20:16 AM UTC 24 |
| Peak memory | 597688 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1463086558 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 91.xbar_same_source.1463086558 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/91.xbar_same_source/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/91.xbar_smoke.2003991544 |
| Short name | T2756 |
| Test name | |
| Test status | |
| Simulation time | 174071091 ps |
| CPU time | 7.15 seconds |
| Started | Aug 24 07:19:22 AM UTC 24 |
| Finished | Aug 24 07:19:32 AM UTC 24 |
| Peak memory | 595632 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2003991544 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 8_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 91.xbar_smoke.2003991544 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/91.xbar_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/91.xbar_smoke_large_delays.2598342927 |
| Short name | T2765 |
| Test name | |
| Test status | |
| Simulation time | 5242238800 ps |
| CPU time | 42.58 seconds |
| Started | Aug 24 07:19:31 AM UTC 24 |
| Finished | Aug 24 07:20:15 AM UTC 24 |
| Peak memory | 595764 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max _device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2598342927 -assert nopostproc +U VM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 91.xbar_smoke_large_delays.2598342927 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/91.xbar_smoke_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/91.xbar_smoke_slow_rsp.3128711297 |
| Short name | T2772 |
| Test name | |
| Test status | |
| Simulation time | 5754927953 ps |
| CPU time | 67.07 seconds |
| Started | Aug 24 07:19:34 AM UTC 24 |
| Finished | Aug 24 07:20:43 AM UTC 24 |
| Peak memory | 596040 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3128711297 -assert nopostproc +UVM_T ESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 91.xbar_smoke_slow_rsp.3128711297 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/91.xbar_smoke_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/91.xbar_smoke_zero_delays.939947340 |
| Short name | T2757 |
| Test name | |
| Test status | |
| Simulation time | 36648143 ps |
| CPU time | 4.64 seconds |
| Started | Aug 24 07:19:27 AM UTC 24 |
| Finished | Aug 24 07:19:32 AM UTC 24 |
| Peak memory | 595696 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=939947340 -assert nopostpro c +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 91.xbar_smoke_zero_delays.939947340 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/91.xbar_smoke_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/91.xbar_stress_all.3410488994 |
| Short name | T2803 |
| Test name | |
| Test status | |
| Simulation time | 6078032160 ps |
| CPU time | 169.81 seconds |
| Started | Aug 24 07:20:27 AM UTC 24 |
| Finished | Aug 24 07:23:19 AM UTC 24 |
| Peak memory | 597888 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3410488994 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 91.xbar_stress_all.3410488994 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/91.xbar_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/91.xbar_stress_all_with_error.4001219914 |
| Short name | T2826 |
| Test name | |
| Test status | |
| Simulation time | 12201761136 ps |
| CPU time | 266.69 seconds |
| Started | Aug 24 07:20:30 AM UTC 24 |
| Finished | Aug 24 07:25:00 AM UTC 24 |
| Peak memory | 597824 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4001219914 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 91.xbar_stress_all_with_error.4001219914 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/91.xbar_stress_all_with_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/91.xbar_stress_all_with_rand_reset.2114787405 |
| Short name | T2813 |
| Test name | |
| Test status | |
| Simulation time | 3942601541 ps |
| CPU time | 197.86 seconds |
| Started | Aug 24 07:20:29 AM UTC 24 |
| Finished | Aug 24 07:23:49 AM UTC 24 |
| Peak memory | 597752 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2114787405 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 91.xbar_stress_all_with_rand_reset.2114787405 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/91.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/91.xbar_stress_all_with_reset_error.3984731810 |
| Short name | T2777 |
| Test name | |
| Test status | |
| Simulation time | 58668024 ps |
| CPU time | 23.03 seconds |
| Started | Aug 24 07:20:40 AM UTC 24 |
| Finished | Aug 24 07:21:04 AM UTC 24 |
| Peak memory | 597752 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3984731810 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 91.xbar_stress_all_with_reset_error.3984731810 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/91.xbar_stress_all_with_reset_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/91.xbar_unmapped_addr.3197456679 |
| Short name | T2770 |
| Test name | |
| Test status | |
| Simulation time | 130233103 ps |
| CPU time | 11.6 seconds |
| Started | Aug 24 07:20:21 AM UTC 24 |
| Finished | Aug 24 07:20:34 AM UTC 24 |
| Peak memory | 598008 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3197456679 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 91.xbar_unmapped_addr.3197456679 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/91.xbar_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/92.xbar_access_same_device.2208102919 |
| Short name | T2779 |
| Test name | |
| Test status | |
| Simulation time | 388969285 ps |
| CPU time | 20.65 seconds |
| Started | Aug 24 07:21:14 AM UTC 24 |
| Finished | Aug 24 07:21:36 AM UTC 24 |
| Peak memory | 597928 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2208102919 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 92.xbar_access_same_device.2208102919 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/92.xbar_access_same_device/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/92.xbar_access_same_device_slow_rsp.2090010971 |
| Short name | T2940 |
| Test name | |
| Test status | |
| Simulation time | 128717555310 ps |
| CPU time | 1495.31 seconds |
| Started | Aug 24 07:21:19 AM UTC 24 |
| Finished | Aug 24 07:46:29 AM UTC 24 |
| Peak memory | 598792 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2090010971 -assert nopostproc +UVM_T ESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 92.xbar_access_same_device_slow_rsp.2090010971 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/92.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/92.xbar_error_and_unmapped_addr.215007593 |
| Short name | T2787 |
| Test name | |
| Test status | |
| Simulation time | 134121780 ps |
| CPU time | 12.42 seconds |
| Started | Aug 24 07:21:57 AM UTC 24 |
| Finished | Aug 24 07:22:10 AM UTC 24 |
| Peak memory | 597388 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=215007593 -assert nopostproc +UVM_TESTNAME =xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 92.xbar_error_and_unmapped_addr.215007593 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/92.xbar_error_and_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/92.xbar_error_random.96011257 |
| Short name | T2790 |
| Test name | |
| Test status | |
| Simulation time | 445506748 ps |
| CPU time | 24.86 seconds |
| Started | Aug 24 07:21:51 AM UTC 24 |
| Finished | Aug 24 07:22:17 AM UTC 24 |
| Peak memory | 597696 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=96011257 -assert nopostproc +UVM_TESTNAME= xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 8_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 92.xbar_error_random.96011257 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/92.xbar_error_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/92.xbar_random.2075086688 |
| Short name | T2786 |
| Test name | |
| Test status | |
| Simulation time | 2574928647 ps |
| CPU time | 62.34 seconds |
| Started | Aug 24 07:20:57 AM UTC 24 |
| Finished | Aug 24 07:22:01 AM UTC 24 |
| Peak memory | 597756 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2075086688 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 92.xbar_random.2075086688 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/92.xbar_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/92.xbar_random_large_delays.2711780494 |
| Short name | T2833 |
| Test name | |
| Test status | |
| Simulation time | 33999035315 ps |
| CPU time | 272.55 seconds |
| Started | Aug 24 07:21:05 AM UTC 24 |
| Finished | Aug 24 07:25:41 AM UTC 24 |
| Peak memory | 597820 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max _device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2711780494 -assert nopostproc +U VM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 92.xbar_random_large_delays.2711780494 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/92.xbar_random_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/92.xbar_random_slow_rsp.1266498136 |
| Short name | T2792 |
| Test name | |
| Test status | |
| Simulation time | 6651726596 ps |
| CPU time | 76.92 seconds |
| Started | Aug 24 07:21:07 AM UTC 24 |
| Finished | Aug 24 07:22:26 AM UTC 24 |
| Peak memory | 598168 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1266498136 -assert nopostproc +UVM_T ESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 92.xbar_random_slow_rsp.1266498136 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/92.xbar_random_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/92.xbar_random_zero_delays.2140404899 |
| Short name | T2782 |
| Test name | |
| Test status | |
| Simulation time | 576392840 ps |
| CPU time | 36.79 seconds |
| Started | Aug 24 07:21:04 AM UTC 24 |
| Finished | Aug 24 07:21:42 AM UTC 24 |
| Peak memory | 597836 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2140404899 -assert nopostpr oc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 92.xbar_random_zero_delays.2140404899 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/92.xbar_random_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/92.xbar_same_source.373174611 |
| Short name | T2789 |
| Test name | |
| Test status | |
| Simulation time | 1274767211 ps |
| CPU time | 26.16 seconds |
| Started | Aug 24 07:21:47 AM UTC 24 |
| Finished | Aug 24 07:22:15 AM UTC 24 |
| Peak memory | 597820 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=373174611 -assert nopostproc +UVM_TESTNAME =xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 92.xbar_same_source.373174611 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/92.xbar_same_source/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/92.xbar_smoke.2258660817 |
| Short name | T2774 |
| Test name | |
| Test status | |
| Simulation time | 53270710 ps |
| CPU time | 5.39 seconds |
| Started | Aug 24 07:20:45 AM UTC 24 |
| Finished | Aug 24 07:20:51 AM UTC 24 |
| Peak memory | 595628 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2258660817 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 8_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 92.xbar_smoke.2258660817 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/92.xbar_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/92.xbar_smoke_large_delays.2401135308 |
| Short name | T2785 |
| Test name | |
| Test status | |
| Simulation time | 8399787366 ps |
| CPU time | 67.24 seconds |
| Started | Aug 24 07:20:48 AM UTC 24 |
| Finished | Aug 24 07:21:57 AM UTC 24 |
| Peak memory | 595828 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max _device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2401135308 -assert nopostproc +U VM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 92.xbar_smoke_large_delays.2401135308 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/92.xbar_smoke_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/92.xbar_smoke_slow_rsp.2310413384 |
| Short name | T2781 |
| Test name | |
| Test status | |
| Simulation time | 4314877829 ps |
| CPU time | 50.86 seconds |
| Started | Aug 24 07:20:50 AM UTC 24 |
| Finished | Aug 24 07:21:42 AM UTC 24 |
| Peak memory | 595952 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2310413384 -assert nopostproc +UVM_T ESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 92.xbar_smoke_slow_rsp.2310413384 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/92.xbar_smoke_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/92.xbar_smoke_zero_delays.3701240394 |
| Short name | T2775 |
| Test name | |
| Test status | |
| Simulation time | 41252093 ps |
| CPU time | 4.77 seconds |
| Started | Aug 24 07:20:47 AM UTC 24 |
| Finished | Aug 24 07:20:53 AM UTC 24 |
| Peak memory | 595632 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3701240394 -assert nopostpr oc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 92.xbar_smoke_zero_delays.3701240394 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/92.xbar_smoke_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/92.xbar_stress_all.1740933422 |
| Short name | T2797 |
| Test name | |
| Test status | |
| Simulation time | 771475120 ps |
| CPU time | 53.17 seconds |
| Started | Aug 24 07:21:57 AM UTC 24 |
| Finished | Aug 24 07:22:51 AM UTC 24 |
| Peak memory | 597700 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1740933422 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 92.xbar_stress_all.1740933422 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/92.xbar_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/92.xbar_stress_all_with_error.839759549 |
| Short name | T2793 |
| Test name | |
| Test status | |
| Simulation time | 481079708 ps |
| CPU time | 27.38 seconds |
| Started | Aug 24 07:22:00 AM UTC 24 |
| Finished | Aug 24 07:22:29 AM UTC 24 |
| Peak memory | 597692 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=839759549 -assert nopostproc +UVM_TESTNAME =xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 92.xbar_stress_all_with_error.839759549 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/92.xbar_stress_all_with_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/92.xbar_stress_all_with_rand_reset.3183738601 |
| Short name | T2842 |
| Test name | |
| Test status | |
| Simulation time | 797702376 ps |
| CPU time | 270.36 seconds |
| Started | Aug 24 07:21:58 AM UTC 24 |
| Finished | Aug 24 07:26:32 AM UTC 24 |
| Peak memory | 597696 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3183738601 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 92.xbar_stress_all_with_rand_reset.3183738601 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/92.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/92.xbar_stress_all_with_reset_error.3728380199 |
| Short name | T2831 |
| Test name | |
| Test status | |
| Simulation time | 582211867 ps |
| CPU time | 201.91 seconds |
| Started | Aug 24 07:22:11 AM UTC 24 |
| Finished | Aug 24 07:25:36 AM UTC 24 |
| Peak memory | 597924 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3728380199 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 92.xbar_stress_all_with_reset_error.3728380199 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/92.xbar_stress_all_with_reset_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/92.xbar_unmapped_addr.3079191617 |
| Short name | T2788 |
| Test name | |
| Test status | |
| Simulation time | 128345481 ps |
| CPU time | 13.01 seconds |
| Started | Aug 24 07:21:57 AM UTC 24 |
| Finished | Aug 24 07:22:11 AM UTC 24 |
| Peak memory | 597336 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3079191617 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 92.xbar_unmapped_addr.3079191617 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/92.xbar_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/93.xbar_access_same_device.3810458583 |
| Short name | T2798 |
| Test name | |
| Test status | |
| Simulation time | 28183804 ps |
| CPU time | 7.05 seconds |
| Started | Aug 24 07:22:44 AM UTC 24 |
| Finished | Aug 24 07:22:52 AM UTC 24 |
| Peak memory | 597772 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3810458583 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 93.xbar_access_same_device.3810458583 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/93.xbar_access_same_device/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/93.xbar_access_same_device_slow_rsp.109226107 |
| Short name | T2937 |
| Test name | |
| Test status | |
| Simulation time | 97447853916 ps |
| CPU time | 1167.34 seconds |
| Started | Aug 24 07:22:58 AM UTC 24 |
| Finished | Aug 24 07:42:37 AM UTC 24 |
| Peak memory | 598788 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=109226107 -assert nopostproc +UVM_TE STNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os _regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 93.xbar_access_same_device_slow_rsp.109226107 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/93.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/93.xbar_error_and_unmapped_addr.2708909037 |
| Short name | T2812 |
| Test name | |
| Test status | |
| Simulation time | 1001996809 ps |
| CPU time | 27.42 seconds |
| Started | Aug 24 07:23:20 AM UTC 24 |
| Finished | Aug 24 07:23:48 AM UTC 24 |
| Peak memory | 597756 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2708909037 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 93.xbar_error_and_unmapped_addr.2708909037 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/93.xbar_error_and_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/93.xbar_error_random.3268554737 |
| Short name | T2801 |
| Test name | |
| Test status | |
| Simulation time | 108920867 ps |
| CPU time | 8.23 seconds |
| Started | Aug 24 07:23:05 AM UTC 24 |
| Finished | Aug 24 07:23:15 AM UTC 24 |
| Peak memory | 597984 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3268554737 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 93.xbar_error_random.3268554737 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/93.xbar_error_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/93.xbar_random.3233423288 |
| Short name | T2796 |
| Test name | |
| Test status | |
| Simulation time | 252226231 ps |
| CPU time | 16.73 seconds |
| Started | Aug 24 07:22:31 AM UTC 24 |
| Finished | Aug 24 07:22:49 AM UTC 24 |
| Peak memory | 597856 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3233423288 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 93.xbar_random.3233423288 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/93.xbar_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/93.xbar_random_large_delays.3286317499 |
| Short name | T2815 |
| Test name | |
| Test status | |
| Simulation time | 11840236007 ps |
| CPU time | 97.38 seconds |
| Started | Aug 24 07:22:40 AM UTC 24 |
| Finished | Aug 24 07:24:20 AM UTC 24 |
| Peak memory | 597820 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max _device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3286317499 -assert nopostproc +U VM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 93.xbar_random_large_delays.3286317499 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/93.xbar_random_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/93.xbar_random_slow_rsp.4264390614 |
| Short name | T2838 |
| Test name | |
| Test status | |
| Simulation time | 18085934768 ps |
| CPU time | 209.88 seconds |
| Started | Aug 24 07:22:43 AM UTC 24 |
| Finished | Aug 24 07:26:16 AM UTC 24 |
| Peak memory | 598068 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4264390614 -assert nopostproc +UVM_T ESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 93.xbar_random_slow_rsp.4264390614 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/93.xbar_random_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/93.xbar_random_zero_delays.1886220364 |
| Short name | T2795 |
| Test name | |
| Test status | |
| Simulation time | 62077237 ps |
| CPU time | 6.5 seconds |
| Started | Aug 24 07:22:36 AM UTC 24 |
| Finished | Aug 24 07:22:44 AM UTC 24 |
| Peak memory | 597696 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1886220364 -assert nopostpr oc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 93.xbar_random_zero_delays.1886220364 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/93.xbar_random_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/93.xbar_same_source.569998711 |
| Short name | T2806 |
| Test name | |
| Test status | |
| Simulation time | 939058049 ps |
| CPU time | 20.61 seconds |
| Started | Aug 24 07:23:03 AM UTC 24 |
| Finished | Aug 24 07:23:25 AM UTC 24 |
| Peak memory | 597680 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=569998711 -assert nopostproc +UVM_TESTNAME =xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 93.xbar_same_source.569998711 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/93.xbar_same_source/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/93.xbar_smoke.3454245483 |
| Short name | T2791 |
| Test name | |
| Test status | |
| Simulation time | 199795620 ps |
| CPU time | 6.53 seconds |
| Started | Aug 24 07:22:15 AM UTC 24 |
| Finished | Aug 24 07:22:22 AM UTC 24 |
| Peak memory | 595848 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3454245483 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 8_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 93.xbar_smoke.3454245483 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/93.xbar_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/93.xbar_smoke_large_delays.2894430621 |
| Short name | T2807 |
| Test name | |
| Test status | |
| Simulation time | 7427621790 ps |
| CPU time | 59.28 seconds |
| Started | Aug 24 07:22:25 AM UTC 24 |
| Finished | Aug 24 07:23:26 AM UTC 24 |
| Peak memory | 595768 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max _device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2894430621 -assert nopostproc +U VM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 93.xbar_smoke_large_delays.2894430621 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/93.xbar_smoke_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/93.xbar_smoke_slow_rsp.562701854 |
| Short name | T2804 |
| Test name | |
| Test status | |
| Simulation time | 4025507867 ps |
| CPU time | 50.23 seconds |
| Started | Aug 24 07:22:29 AM UTC 24 |
| Finished | Aug 24 07:23:21 AM UTC 24 |
| Peak memory | 595924 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=562701854 -assert nopostproc +UVM_TE STNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 93.xbar_smoke_slow_rsp.562701854 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/93.xbar_smoke_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/93.xbar_smoke_zero_delays.355841385 |
| Short name | T2794 |
| Test name | |
| Test status | |
| Simulation time | 48054575 ps |
| CPU time | 4.95 seconds |
| Started | Aug 24 07:22:24 AM UTC 24 |
| Finished | Aug 24 07:22:30 AM UTC 24 |
| Peak memory | 595632 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=355841385 -assert nopostpro c +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 93.xbar_smoke_zero_delays.355841385 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/93.xbar_smoke_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/93.xbar_stress_all.126566072 |
| Short name | T2069 |
| Test name | |
| Test status | |
| Simulation time | 4572161267 ps |
| CPU time | 119.64 seconds |
| Started | Aug 24 07:23:28 AM UTC 24 |
| Finished | Aug 24 07:25:29 AM UTC 24 |
| Peak memory | 597828 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=126566072 -assert nopostproc +UVM_TESTNAME =xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 93.xbar_stress_all.126566072 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/93.xbar_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/93.xbar_stress_all_with_rand_reset.1605467906 |
| Short name | T2904 |
| Test name | |
| Test status | |
| Simulation time | 4826265711 ps |
| CPU time | 517.11 seconds |
| Started | Aug 24 07:23:29 AM UTC 24 |
| Finished | Aug 24 07:32:12 AM UTC 24 |
| Peak memory | 597820 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1605467906 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 93.xbar_stress_all_with_rand_reset.1605467906 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/93.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/93.xbar_stress_all_with_reset_error.2216302935 |
| Short name | T2810 |
| Test name | |
| Test status | |
| Simulation time | 78941586 ps |
| CPU time | 9.74 seconds |
| Started | Aug 24 07:23:33 AM UTC 24 |
| Finished | Aug 24 07:23:43 AM UTC 24 |
| Peak memory | 597968 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2216302935 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 93.xbar_stress_all_with_reset_error.2216302935 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/93.xbar_stress_all_with_reset_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/93.xbar_unmapped_addr.4271852379 |
| Short name | T2808 |
| Test name | |
| Test status | |
| Simulation time | 1069510432 ps |
| CPU time | 29.05 seconds |
| Started | Aug 24 07:23:06 AM UTC 24 |
| Finished | Aug 24 07:23:37 AM UTC 24 |
| Peak memory | 597912 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4271852379 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 93.xbar_unmapped_addr.4271852379 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/93.xbar_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/94.xbar_access_same_device.2857398199 |
| Short name | T2822 |
| Test name | |
| Test status | |
| Simulation time | 1982373870 ps |
| CPU time | 48.08 seconds |
| Started | Aug 24 07:24:02 AM UTC 24 |
| Finished | Aug 24 07:24:51 AM UTC 24 |
| Peak memory | 597708 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2857398199 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 94.xbar_access_same_device.2857398199 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/94.xbar_access_same_device/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/94.xbar_access_same_device_slow_rsp.611710888 |
| Short name | T2939 |
| Test name | |
| Test status | |
| Simulation time | 105790366380 ps |
| CPU time | 1285.15 seconds |
| Started | Aug 24 07:24:03 AM UTC 24 |
| Finished | Aug 24 07:45:41 AM UTC 24 |
| Peak memory | 599008 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=611710888 -assert nopostproc +UVM_TE STNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os _regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 94.xbar_access_same_device_slow_rsp.611710888 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/94.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/94.xbar_error_and_unmapped_addr.413022044 |
| Short name | T2820 |
| Test name | |
| Test status | |
| Simulation time | 123989970 ps |
| CPU time | 11.16 seconds |
| Started | Aug 24 07:24:38 AM UTC 24 |
| Finished | Aug 24 07:24:51 AM UTC 24 |
| Peak memory | 597692 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=413022044 -assert nopostproc +UVM_TESTNAME =xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 94.xbar_error_and_unmapped_addr.413022044 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/94.xbar_error_and_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/94.xbar_error_random.1600950622 |
| Short name | T2819 |
| Test name | |
| Test status | |
| Simulation time | 32856064 ps |
| CPU time | 4.44 seconds |
| Started | Aug 24 07:24:33 AM UTC 24 |
| Finished | Aug 24 07:24:39 AM UTC 24 |
| Peak memory | 595640 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1600950622 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 94.xbar_error_random.1600950622 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/94.xbar_error_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/94.xbar_random.1585031378 |
| Short name | T2814 |
| Test name | |
| Test status | |
| Simulation time | 913385560 ps |
| CPU time | 23.23 seconds |
| Started | Aug 24 07:23:51 AM UTC 24 |
| Finished | Aug 24 07:24:15 AM UTC 24 |
| Peak memory | 597752 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1585031378 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 94.xbar_random.1585031378 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/94.xbar_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/94.xbar_random_large_delays.627199910 |
| Short name | T2837 |
| Test name | |
| Test status | |
| Simulation time | 16742624591 ps |
| CPU time | 134.37 seconds |
| Started | Aug 24 07:23:58 AM UTC 24 |
| Finished | Aug 24 07:26:14 AM UTC 24 |
| Peak memory | 597824 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max _device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=627199910 -assert nopostproc +UV M_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 94.xbar_random_large_delays.627199910 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/94.xbar_random_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/94.xbar_random_slow_rsp.551819666 |
| Short name | T2908 |
| Test name | |
| Test status | |
| Simulation time | 45850686387 ps |
| CPU time | 524.88 seconds |
| Started | Aug 24 07:23:59 AM UTC 24 |
| Finished | Aug 24 07:32:50 AM UTC 24 |
| Peak memory | 597892 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=551819666 -assert nopostproc +UVM_TE STNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 94.xbar_random_slow_rsp.551819666 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/94.xbar_random_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/94.xbar_random_zero_delays.1934745414 |
| Short name | T2816 |
| Test name | |
| Test status | |
| Simulation time | 373023601 ps |
| CPU time | 24.38 seconds |
| Started | Aug 24 07:23:57 AM UTC 24 |
| Finished | Aug 24 07:24:22 AM UTC 24 |
| Peak memory | 597700 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1934745414 -assert nopostpr oc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 94.xbar_random_zero_delays.1934745414 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/94.xbar_random_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/94.xbar_same_source.618993762 |
| Short name | T2823 |
| Test name | |
| Test status | |
| Simulation time | 435463591 ps |
| CPU time | 22.04 seconds |
| Started | Aug 24 07:24:29 AM UTC 24 |
| Finished | Aug 24 07:24:53 AM UTC 24 |
| Peak memory | 597832 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=618993762 -assert nopostproc +UVM_TESTNAME =xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 94.xbar_same_source.618993762 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/94.xbar_same_source/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/94.xbar_smoke.690060050 |
| Short name | T2809 |
| Test name | |
| Test status | |
| Simulation time | 250130644 ps |
| CPU time | 7.51 seconds |
| Started | Aug 24 07:23:35 AM UTC 24 |
| Finished | Aug 24 07:23:43 AM UTC 24 |
| Peak memory | 595884 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=690060050 -assert nopostproc +UVM_TESTNAME =xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08 _22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 94.xbar_smoke.690060050 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/94.xbar_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/94.xbar_smoke_large_delays.1996671734 |
| Short name | T2825 |
| Test name | |
| Test status | |
| Simulation time | 9274912507 ps |
| CPU time | 77.78 seconds |
| Started | Aug 24 07:23:39 AM UTC 24 |
| Finished | Aug 24 07:24:58 AM UTC 24 |
| Peak memory | 596124 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max _device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1996671734 -assert nopostproc +U VM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 94.xbar_smoke_large_delays.1996671734 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/94.xbar_smoke_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/94.xbar_smoke_slow_rsp.1256501120 |
| Short name | T2824 |
| Test name | |
| Test status | |
| Simulation time | 5989293217 ps |
| CPU time | 72.12 seconds |
| Started | Aug 24 07:23:40 AM UTC 24 |
| Finished | Aug 24 07:24:54 AM UTC 24 |
| Peak memory | 595772 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1256501120 -assert nopostproc +UVM_T ESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 94.xbar_smoke_slow_rsp.1256501120 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/94.xbar_smoke_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/94.xbar_smoke_zero_delays.54184290 |
| Short name | T2811 |
| Test name | |
| Test status | |
| Simulation time | 47899529 ps |
| CPU time | 4.94 seconds |
| Started | Aug 24 07:23:39 AM UTC 24 |
| Finished | Aug 24 07:23:45 AM UTC 24 |
| Peak memory | 595776 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=54184290 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 94.xbar_smoke_zero_delays.54184290 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/94.xbar_smoke_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/94.xbar_stress_all.170204441 |
| Short name | T2832 |
| Test name | |
| Test status | |
| Simulation time | 1785373446 ps |
| CPU time | 46.71 seconds |
| Started | Aug 24 07:24:49 AM UTC 24 |
| Finished | Aug 24 07:25:37 AM UTC 24 |
| Peak memory | 597760 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=170204441 -assert nopostproc +UVM_TESTNAME =xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 94.xbar_stress_all.170204441 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/94.xbar_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/94.xbar_stress_all_with_error.154782316 |
| Short name | T2866 |
| Test name | |
| Test status | |
| Simulation time | 9249113152 ps |
| CPU time | 210.97 seconds |
| Started | Aug 24 07:25:05 AM UTC 24 |
| Finished | Aug 24 07:28:41 AM UTC 24 |
| Peak memory | 597828 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=154782316 -assert nopostproc +UVM_TESTNAME =xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 94.xbar_stress_all_with_error.154782316 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/94.xbar_stress_all_with_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/94.xbar_stress_all_with_rand_reset.3921228069 |
| Short name | T2884 |
| Test name | |
| Test status | |
| Simulation time | 3296269402 ps |
| CPU time | 310.56 seconds |
| Started | Aug 24 07:24:53 AM UTC 24 |
| Finished | Aug 24 07:30:07 AM UTC 24 |
| Peak memory | 597820 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3921228069 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 94.xbar_stress_all_with_rand_reset.3921228069 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/94.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/94.xbar_stress_all_with_reset_error.3594461599 |
| Short name | T2856 |
| Test name | |
| Test status | |
| Simulation time | 499947739 ps |
| CPU time | 154.63 seconds |
| Started | Aug 24 07:25:06 AM UTC 24 |
| Finished | Aug 24 07:27:44 AM UTC 24 |
| Peak memory | 597920 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3594461599 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 94.xbar_stress_all_with_reset_error.3594461599 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/94.xbar_stress_all_with_reset_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/94.xbar_unmapped_addr.3334987281 |
| Short name | T2821 |
| Test name | |
| Test status | |
| Simulation time | 376755649 ps |
| CPU time | 13.45 seconds |
| Started | Aug 24 07:24:37 AM UTC 24 |
| Finished | Aug 24 07:24:51 AM UTC 24 |
| Peak memory | 597948 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3334987281 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 94.xbar_unmapped_addr.3334987281 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/94.xbar_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/95.xbar_access_same_device.1691173856 |
| Short name | T2844 |
| Test name | |
| Test status | |
| Simulation time | 1156420438 ps |
| CPU time | 55.1 seconds |
| Started | Aug 24 07:25:40 AM UTC 24 |
| Finished | Aug 24 07:26:38 AM UTC 24 |
| Peak memory | 597704 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1691173856 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 95.xbar_access_same_device.1691173856 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/95.xbar_access_same_device/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/95.xbar_access_same_device_slow_rsp.583910298 |
| Short name | T2869 |
| Test name | |
| Test status | |
| Simulation time | 15984915319 ps |
| CPU time | 182.49 seconds |
| Started | Aug 24 07:25:43 AM UTC 24 |
| Finished | Aug 24 07:28:48 AM UTC 24 |
| Peak memory | 597820 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=583910298 -assert nopostproc +UVM_TE STNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os _regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 95.xbar_access_same_device_slow_rsp.583910298 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/95.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/95.xbar_error_and_unmapped_addr.549197861 |
| Short name | T2839 |
| Test name | |
| Test status | |
| Simulation time | 24370078 ps |
| CPU time | 4.37 seconds |
| Started | Aug 24 07:26:11 AM UTC 24 |
| Finished | Aug 24 07:26:16 AM UTC 24 |
| Peak memory | 594988 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=549197861 -assert nopostproc +UVM_TESTNAME =xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 95.xbar_error_and_unmapped_addr.549197861 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/95.xbar_error_and_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/95.xbar_error_random.720261823 |
| Short name | T2846 |
| Test name | |
| Test status | |
| Simulation time | 2304815586 ps |
| CPU time | 51.63 seconds |
| Started | Aug 24 07:25:50 AM UTC 24 |
| Finished | Aug 24 07:26:44 AM UTC 24 |
| Peak memory | 597764 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=720261823 -assert nopostproc +UVM_TESTNAME =xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 95.xbar_error_random.720261823 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/95.xbar_error_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/95.xbar_random.2007667116 |
| Short name | T2830 |
| Test name | |
| Test status | |
| Simulation time | 367561422 ps |
| CPU time | 11.45 seconds |
| Started | Aug 24 07:25:14 AM UTC 24 |
| Finished | Aug 24 07:25:27 AM UTC 24 |
| Peak memory | 597832 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2007667116 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 95.xbar_random.2007667116 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/95.xbar_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/95.xbar_random_large_delays.3166042458 |
| Short name | T2930 |
| Test name | |
| Test status | |
| Simulation time | 100073598343 ps |
| CPU time | 849.36 seconds |
| Started | Aug 24 07:25:30 AM UTC 24 |
| Finished | Aug 24 07:39:51 AM UTC 24 |
| Peak memory | 598044 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max _device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3166042458 -assert nopostproc +U VM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 95.xbar_random_large_delays.3166042458 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/95.xbar_random_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/95.xbar_random_slow_rsp.1693879562 |
| Short name | T2886 |
| Test name | |
| Test status | |
| Simulation time | 23365482679 ps |
| CPU time | 283.13 seconds |
| Started | Aug 24 07:25:39 AM UTC 24 |
| Finished | Aug 24 07:30:27 AM UTC 24 |
| Peak memory | 598068 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1693879562 -assert nopostproc +UVM_T ESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 95.xbar_random_slow_rsp.1693879562 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/95.xbar_random_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/95.xbar_random_zero_delays.3087872701 |
| Short name | T2834 |
| Test name | |
| Test status | |
| Simulation time | 459659867 ps |
| CPU time | 27.37 seconds |
| Started | Aug 24 07:25:28 AM UTC 24 |
| Finished | Aug 24 07:25:57 AM UTC 24 |
| Peak memory | 597696 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3087872701 -assert nopostpr oc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 95.xbar_random_zero_delays.3087872701 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/95.xbar_random_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/95.xbar_same_source.158155375 |
| Short name | T2836 |
| Test name | |
| Test status | |
| Simulation time | 815501642 ps |
| CPU time | 18.51 seconds |
| Started | Aug 24 07:25:50 AM UTC 24 |
| Finished | Aug 24 07:26:09 AM UTC 24 |
| Peak memory | 597760 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=158155375 -assert nopostproc +UVM_TESTNAME =xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 95.xbar_same_source.158155375 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/95.xbar_same_source/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/95.xbar_smoke.1363848600 |
| Short name | T2828 |
| Test name | |
| Test status | |
| Simulation time | 237924027 ps |
| CPU time | 7.23 seconds |
| Started | Aug 24 07:25:06 AM UTC 24 |
| Finished | Aug 24 07:25:15 AM UTC 24 |
| Peak memory | 595696 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1363848600 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 8_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 95.xbar_smoke.1363848600 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/95.xbar_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/95.xbar_smoke_large_delays.3168486493 |
| Short name | T2840 |
| Test name | |
| Test status | |
| Simulation time | 7918854333 ps |
| CPU time | 68.42 seconds |
| Started | Aug 24 07:25:08 AM UTC 24 |
| Finished | Aug 24 07:26:18 AM UTC 24 |
| Peak memory | 595912 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max _device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3168486493 -assert nopostproc +U VM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 95.xbar_smoke_large_delays.3168486493 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/95.xbar_smoke_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/95.xbar_smoke_slow_rsp.3583736365 |
| Short name | T2835 |
| Test name | |
| Test status | |
| Simulation time | 4629638345 ps |
| CPU time | 54.11 seconds |
| Started | Aug 24 07:25:13 AM UTC 24 |
| Finished | Aug 24 07:26:09 AM UTC 24 |
| Peak memory | 595908 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3583736365 -assert nopostproc +UVM_T ESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 95.xbar_smoke_slow_rsp.3583736365 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/95.xbar_smoke_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/95.xbar_smoke_zero_delays.207493094 |
| Short name | T2827 |
| Test name | |
| Test status | |
| Simulation time | 42166161 ps |
| CPU time | 5.23 seconds |
| Started | Aug 24 07:25:07 AM UTC 24 |
| Finished | Aug 24 07:25:13 AM UTC 24 |
| Peak memory | 595904 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=207493094 -assert nopostpro c +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 95.xbar_smoke_zero_delays.207493094 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/95.xbar_smoke_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/95.xbar_stress_all.1424824883 |
| Short name | T2849 |
| Test name | |
| Test status | |
| Simulation time | 833025765 ps |
| CPU time | 50.64 seconds |
| Started | Aug 24 07:26:23 AM UTC 24 |
| Finished | Aug 24 07:27:15 AM UTC 24 |
| Peak memory | 597696 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1424824883 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 95.xbar_stress_all.1424824883 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/95.xbar_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/95.xbar_stress_all_with_error.1221261833 |
| Short name | T2848 |
| Test name | |
| Test status | |
| Simulation time | 731513593 ps |
| CPU time | 37.31 seconds |
| Started | Aug 24 07:26:29 AM UTC 24 |
| Finished | Aug 24 07:27:07 AM UTC 24 |
| Peak memory | 597696 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1221261833 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 95.xbar_stress_all_with_error.1221261833 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/95.xbar_stress_all_with_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/95.xbar_stress_all_with_rand_reset.4116023691 |
| Short name | T2850 |
| Test name | |
| Test status | |
| Simulation time | 91202204 ps |
| CPU time | 53.18 seconds |
| Started | Aug 24 07:26:24 AM UTC 24 |
| Finished | Aug 24 07:27:18 AM UTC 24 |
| Peak memory | 597688 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4116023691 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 95.xbar_stress_all_with_rand_reset.4116023691 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/95.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/95.xbar_stress_all_with_reset_error.2838480910 |
| Short name | T2868 |
| Test name | |
| Test status | |
| Simulation time | 1920664911 ps |
| CPU time | 130.74 seconds |
| Started | Aug 24 07:26:30 AM UTC 24 |
| Finished | Aug 24 07:28:43 AM UTC 24 |
| Peak memory | 597824 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2838480910 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 95.xbar_stress_all_with_reset_error.2838480910 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/95.xbar_stress_all_with_reset_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/95.xbar_unmapped_addr.1068011121 |
| Short name | T2841 |
| Test name | |
| Test status | |
| Simulation time | 321041004 ps |
| CPU time | 26.91 seconds |
| Started | Aug 24 07:25:56 AM UTC 24 |
| Finished | Aug 24 07:26:24 AM UTC 24 |
| Peak memory | 597944 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1068011121 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 95.xbar_unmapped_addr.1068011121 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/95.xbar_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/96.xbar_access_same_device.366256326 |
| Short name | T2853 |
| Test name | |
| Test status | |
| Simulation time | 296041119 ps |
| CPU time | 16.82 seconds |
| Started | Aug 24 07:27:10 AM UTC 24 |
| Finished | Aug 24 07:27:28 AM UTC 24 |
| Peak memory | 597952 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=366256326 -assert nopostproc +UVM_TESTNAME =xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 96.xbar_access_same_device.366256326 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/96.xbar_access_same_device/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/96.xbar_access_same_device_slow_rsp.2737019809 |
| Short name | T2910 |
| Test name | |
| Test status | |
| Simulation time | 27372628422 ps |
| CPU time | 332.51 seconds |
| Started | Aug 24 07:27:22 AM UTC 24 |
| Finished | Aug 24 07:32:58 AM UTC 24 |
| Peak memory | 597884 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2737019809 -assert nopostproc +UVM_T ESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 96.xbar_access_same_device_slow_rsp.2737019809 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/96.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/96.xbar_error_and_unmapped_addr.1502714160 |
| Short name | T2857 |
| Test name | |
| Test status | |
| Simulation time | 44932583 ps |
| CPU time | 5.58 seconds |
| Started | Aug 24 07:27:40 AM UTC 24 |
| Finished | Aug 24 07:27:46 AM UTC 24 |
| Peak memory | 595716 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1502714160 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 96.xbar_error_and_unmapped_addr.1502714160 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/96.xbar_error_and_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/96.xbar_error_random.4270051252 |
| Short name | T2864 |
| Test name | |
| Test status | |
| Simulation time | 2303221794 ps |
| CPU time | 54.27 seconds |
| Started | Aug 24 07:27:32 AM UTC 24 |
| Finished | Aug 24 07:28:29 AM UTC 24 |
| Peak memory | 598048 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4270051252 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 96.xbar_error_random.4270051252 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/96.xbar_error_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/96.xbar_random.3407301971 |
| Short name | T2847 |
| Test name | |
| Test status | |
| Simulation time | 39677326 ps |
| CPU time | 5.09 seconds |
| Started | Aug 24 07:26:49 AM UTC 24 |
| Finished | Aug 24 07:26:55 AM UTC 24 |
| Peak memory | 595808 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3407301971 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 96.xbar_random.3407301971 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/96.xbar_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/96.xbar_random_large_delays.949210329 |
| Short name | T2934 |
| Test name | |
| Test status | |
| Simulation time | 99410829304 ps |
| CPU time | 847.41 seconds |
| Started | Aug 24 07:26:52 AM UTC 24 |
| Finished | Aug 24 07:41:09 AM UTC 24 |
| Peak memory | 597976 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max _device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=949210329 -assert nopostproc +UV M_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 96.xbar_random_large_delays.949210329 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/96.xbar_random_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/96.xbar_random_slow_rsp.2885068723 |
| Short name | T2921 |
| Test name | |
| Test status | |
| Simulation time | 38945950340 ps |
| CPU time | 449.53 seconds |
| Started | Aug 24 07:26:57 AM UTC 24 |
| Finished | Aug 24 07:34:32 AM UTC 24 |
| Peak memory | 597816 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2885068723 -assert nopostproc +UVM_T ESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 96.xbar_random_slow_rsp.2885068723 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/96.xbar_random_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/96.xbar_random_zero_delays.1767659279 |
| Short name | T2851 |
| Test name | |
| Test status | |
| Simulation time | 506684537 ps |
| CPU time | 31.7 seconds |
| Started | Aug 24 07:26:52 AM UTC 24 |
| Finished | Aug 24 07:27:25 AM UTC 24 |
| Peak memory | 597756 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1767659279 -assert nopostpr oc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 96.xbar_random_zero_delays.1767659279 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/96.xbar_random_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/96.xbar_same_source.3470988989 |
| Short name | T2859 |
| Test name | |
| Test status | |
| Simulation time | 1127198532 ps |
| CPU time | 24.86 seconds |
| Started | Aug 24 07:27:28 AM UTC 24 |
| Finished | Aug 24 07:27:55 AM UTC 24 |
| Peak memory | 597756 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3470988989 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 96.xbar_same_source.3470988989 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/96.xbar_same_source/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/96.xbar_smoke.1560999945 |
| Short name | T2843 |
| Test name | |
| Test status | |
| Simulation time | 40165611 ps |
| CPU time | 4.73 seconds |
| Started | Aug 24 07:26:30 AM UTC 24 |
| Finished | Aug 24 07:26:35 AM UTC 24 |
| Peak memory | 595880 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1560999945 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 8_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 96.xbar_smoke.1560999945 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/96.xbar_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/96.xbar_smoke_large_delays.502657236 |
| Short name | T2852 |
| Test name | |
| Test status | |
| Simulation time | 5573676618 ps |
| CPU time | 46.24 seconds |
| Started | Aug 24 07:26:38 AM UTC 24 |
| Finished | Aug 24 07:27:25 AM UTC 24 |
| Peak memory | 595968 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max _device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=502657236 -assert nopostproc +UV M_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 96.xbar_smoke_large_delays.502657236 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/96.xbar_smoke_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/96.xbar_smoke_slow_rsp.2779551609 |
| Short name | T2855 |
| Test name | |
| Test status | |
| Simulation time | 4362851594 ps |
| CPU time | 52.38 seconds |
| Started | Aug 24 07:26:46 AM UTC 24 |
| Finished | Aug 24 07:27:40 AM UTC 24 |
| Peak memory | 595908 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2779551609 -assert nopostproc +UVM_T ESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 96.xbar_smoke_slow_rsp.2779551609 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/96.xbar_smoke_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/96.xbar_smoke_zero_delays.2031110639 |
| Short name | T2845 |
| Test name | |
| Test status | |
| Simulation time | 54119180 ps |
| CPU time | 5.49 seconds |
| Started | Aug 24 07:26:32 AM UTC 24 |
| Finished | Aug 24 07:26:38 AM UTC 24 |
| Peak memory | 595860 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2031110639 -assert nopostpr oc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 96.xbar_smoke_zero_delays.2031110639 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/96.xbar_smoke_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/96.xbar_stress_all.2961499098 |
| Short name | T2923 |
| Test name | |
| Test status | |
| Simulation time | 18325304949 ps |
| CPU time | 480.84 seconds |
| Started | Aug 24 07:27:42 AM UTC 24 |
| Finished | Aug 24 07:35:48 AM UTC 24 |
| Peak memory | 597964 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2961499098 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 96.xbar_stress_all.2961499098 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/96.xbar_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/96.xbar_stress_all_with_error.4079858077 |
| Short name | T2893 |
| Test name | |
| Test status | |
| Simulation time | 8524107303 ps |
| CPU time | 192.32 seconds |
| Started | Aug 24 07:27:54 AM UTC 24 |
| Finished | Aug 24 07:31:09 AM UTC 24 |
| Peak memory | 597824 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4079858077 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 96.xbar_stress_all_with_error.4079858077 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/96.xbar_stress_all_with_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/96.xbar_stress_all_with_rand_reset.3817585009 |
| Short name | T2918 |
| Test name | |
| Test status | |
| Simulation time | 2554077813 ps |
| CPU time | 363.12 seconds |
| Started | Aug 24 07:27:54 AM UTC 24 |
| Finished | Aug 24 07:34:01 AM UTC 24 |
| Peak memory | 597828 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3817585009 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 96.xbar_stress_all_with_rand_reset.3817585009 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/96.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/96.xbar_stress_all_with_reset_error.3269296812 |
| Short name | T2911 |
| Test name | |
| Test status | |
| Simulation time | 8819900435 ps |
| CPU time | 295.76 seconds |
| Started | Aug 24 07:27:59 AM UTC 24 |
| Finished | Aug 24 07:32:59 AM UTC 24 |
| Peak memory | 597824 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3269296812 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 96.xbar_stress_all_with_reset_error.3269296812 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/96.xbar_stress_all_with_reset_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/96.xbar_unmapped_addr.1070070449 |
| Short name | T2862 |
| Test name | |
| Test status | |
| Simulation time | 1151830691 ps |
| CPU time | 36.35 seconds |
| Started | Aug 24 07:27:40 AM UTC 24 |
| Finished | Aug 24 07:28:17 AM UTC 24 |
| Peak memory | 597908 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1070070449 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 96.xbar_unmapped_addr.1070070449 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/96.xbar_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/97.xbar_access_same_device.1603775724 |
| Short name | T2878 |
| Test name | |
| Test status | |
| Simulation time | 970342576 ps |
| CPU time | 49.92 seconds |
| Started | Aug 24 07:28:42 AM UTC 24 |
| Finished | Aug 24 07:29:34 AM UTC 24 |
| Peak memory | 597924 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1603775724 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 97.xbar_access_same_device.1603775724 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/97.xbar_access_same_device/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/97.xbar_access_same_device_slow_rsp.1158701229 |
| Short name | T2900 |
| Test name | |
| Test status | |
| Simulation time | 14782441467 ps |
| CPU time | 166.73 seconds |
| Started | Aug 24 07:28:43 AM UTC 24 |
| Finished | Aug 24 07:31:33 AM UTC 24 |
| Peak memory | 597884 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1158701229 -assert nopostproc +UVM_T ESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 97.xbar_access_same_device_slow_rsp.1158701229 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/97.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/97.xbar_error_and_unmapped_addr.231257596 |
| Short name | T2881 |
| Test name | |
| Test status | |
| Simulation time | 1346247214 ps |
| CPU time | 33.91 seconds |
| Started | Aug 24 07:29:03 AM UTC 24 |
| Finished | Aug 24 07:29:38 AM UTC 24 |
| Peak memory | 597944 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=231257596 -assert nopostproc +UVM_TESTNAME =xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 97.xbar_error_and_unmapped_addr.231257596 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/97.xbar_error_and_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/97.xbar_error_random.280406490 |
| Short name | T2880 |
| Test name | |
| Test status | |
| Simulation time | 1682546559 ps |
| CPU time | 39.03 seconds |
| Started | Aug 24 07:28:57 AM UTC 24 |
| Finished | Aug 24 07:29:37 AM UTC 24 |
| Peak memory | 598012 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=280406490 -assert nopostproc +UVM_TESTNAME =xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 97.xbar_error_random.280406490 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/97.xbar_error_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/97.xbar_random.7211592 |
| Short name | T2867 |
| Test name | |
| Test status | |
| Simulation time | 216138587 ps |
| CPU time | 15.32 seconds |
| Started | Aug 24 07:28:25 AM UTC 24 |
| Finished | Aug 24 07:28:42 AM UTC 24 |
| Peak memory | 597836 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=7211592 -assert nopostproc +UVM_TESTNAME=x bar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_ 22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 97.xbar_random.7211592 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/97.xbar_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/97.xbar_random_large_delays.1517171676 |
| Short name | T2935 |
| Test name | |
| Test status | |
| Simulation time | 100016469936 ps |
| CPU time | 793 seconds |
| Started | Aug 24 07:28:34 AM UTC 24 |
| Finished | Aug 24 07:41:56 AM UTC 24 |
| Peak memory | 597952 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max _device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1517171676 -assert nopostproc +U VM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 97.xbar_random_large_delays.1517171676 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/97.xbar_random_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/97.xbar_random_slow_rsp.3363694939 |
| Short name | T2929 |
| Test name | |
| Test status | |
| Simulation time | 47980742582 ps |
| CPU time | 587.99 seconds |
| Started | Aug 24 07:28:35 AM UTC 24 |
| Finished | Aug 24 07:38:30 AM UTC 24 |
| Peak memory | 598048 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3363694939 -assert nopostproc +UVM_T ESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 97.xbar_random_slow_rsp.3363694939 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/97.xbar_random_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/97.xbar_random_zero_delays.3020751030 |
| Short name | T2871 |
| Test name | |
| Test status | |
| Simulation time | 365250279 ps |
| CPU time | 23.87 seconds |
| Started | Aug 24 07:28:31 AM UTC 24 |
| Finished | Aug 24 07:28:56 AM UTC 24 |
| Peak memory | 597696 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3020751030 -assert nopostpr oc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 97.xbar_random_zero_delays.3020751030 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/97.xbar_random_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/97.xbar_same_source.134407019 |
| Short name | T2873 |
| Test name | |
| Test status | |
| Simulation time | 175413122 ps |
| CPU time | 11.89 seconds |
| Started | Aug 24 07:28:55 AM UTC 24 |
| Finished | Aug 24 07:29:08 AM UTC 24 |
| Peak memory | 597832 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=134407019 -assert nopostproc +UVM_TESTNAME =xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 97.xbar_same_source.134407019 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/97.xbar_same_source/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/97.xbar_smoke.1785938647 |
| Short name | T2860 |
| Test name | |
| Test status | |
| Simulation time | 184999784 ps |
| CPU time | 6.95 seconds |
| Started | Aug 24 07:28:00 AM UTC 24 |
| Finished | Aug 24 07:28:08 AM UTC 24 |
| Peak memory | 595852 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1785938647 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 8_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 97.xbar_smoke.1785938647 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/97.xbar_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/97.xbar_smoke_large_delays.992217636 |
| Short name | T2876 |
| Test name | |
| Test status | |
| Simulation time | 8147685098 ps |
| CPU time | 68.71 seconds |
| Started | Aug 24 07:28:09 AM UTC 24 |
| Finished | Aug 24 07:29:20 AM UTC 24 |
| Peak memory | 595972 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max _device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=992217636 -assert nopostproc +UV M_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 97.xbar_smoke_large_delays.992217636 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/97.xbar_smoke_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/97.xbar_smoke_slow_rsp.247122838 |
| Short name | T2882 |
| Test name | |
| Test status | |
| Simulation time | 6369691094 ps |
| CPU time | 74.51 seconds |
| Started | Aug 24 07:28:22 AM UTC 24 |
| Finished | Aug 24 07:29:38 AM UTC 24 |
| Peak memory | 595756 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=247122838 -assert nopostproc +UVM_TE STNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 97.xbar_smoke_slow_rsp.247122838 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/97.xbar_smoke_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/97.xbar_smoke_zero_delays.4090876843 |
| Short name | T2861 |
| Test name | |
| Test status | |
| Simulation time | 42212037 ps |
| CPU time | 4.73 seconds |
| Started | Aug 24 07:28:05 AM UTC 24 |
| Finished | Aug 24 07:28:11 AM UTC 24 |
| Peak memory | 595632 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4090876843 -assert nopostpr oc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 97.xbar_smoke_zero_delays.4090876843 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/97.xbar_smoke_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/97.xbar_stress_all.3708115277 |
| Short name | T2885 |
| Test name | |
| Test status | |
| Simulation time | 2073853631 ps |
| CPU time | 66.51 seconds |
| Started | Aug 24 07:29:05 AM UTC 24 |
| Finished | Aug 24 07:30:13 AM UTC 24 |
| Peak memory | 597760 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3708115277 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 97.xbar_stress_all.3708115277 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/97.xbar_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/97.xbar_stress_all_with_error.3241379317 |
| Short name | T2915 |
| Test name | |
| Test status | |
| Simulation time | 10440995720 ps |
| CPU time | 233.59 seconds |
| Started | Aug 24 07:29:20 AM UTC 24 |
| Finished | Aug 24 07:33:17 AM UTC 24 |
| Peak memory | 598140 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3241379317 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 97.xbar_stress_all_with_error.3241379317 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/97.xbar_stress_all_with_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/97.xbar_stress_all_with_rand_reset.1031307844 |
| Short name | T2895 |
| Test name | |
| Test status | |
| Simulation time | 251739059 ps |
| CPU time | 118.6 seconds |
| Started | Aug 24 07:29:11 AM UTC 24 |
| Finished | Aug 24 07:31:12 AM UTC 24 |
| Peak memory | 597696 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1031307844 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 97.xbar_stress_all_with_rand_reset.1031307844 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/97.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/97.xbar_stress_all_with_reset_error.2275936171 |
| Short name | T2896 |
| Test name | |
| Test status | |
| Simulation time | 403605414 ps |
| CPU time | 107.24 seconds |
| Started | Aug 24 07:29:23 AM UTC 24 |
| Finished | Aug 24 07:31:12 AM UTC 24 |
| Peak memory | 597692 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2275936171 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 97.xbar_stress_all_with_reset_error.2275936171 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/97.xbar_stress_all_with_reset_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/97.xbar_unmapped_addr.100196430 |
| Short name | T2875 |
| Test name | |
| Test status | |
| Simulation time | 413748605 ps |
| CPU time | 14.26 seconds |
| Started | Aug 24 07:28:57 AM UTC 24 |
| Finished | Aug 24 07:29:12 AM UTC 24 |
| Peak memory | 597836 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=100196430 -assert nopostproc +UVM_TESTNAME =xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 97.xbar_unmapped_addr.100196430 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/97.xbar_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/98.xbar_access_same_device.1491448536 |
| Short name | T2890 |
| Test name | |
| Test status | |
| Simulation time | 2133186434 ps |
| CPU time | 58.36 seconds |
| Started | Aug 24 07:29:52 AM UTC 24 |
| Finished | Aug 24 07:30:52 AM UTC 24 |
| Peak memory | 597704 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1491448536 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 98.xbar_access_same_device.1491448536 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/98.xbar_access_same_device/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/98.xbar_access_same_device_slow_rsp.3669960974 |
| Short name | T2941 |
| Test name | |
| Test status | |
| Simulation time | 132271283142 ps |
| CPU time | 1543.49 seconds |
| Started | Aug 24 07:30:14 AM UTC 24 |
| Finished | Aug 24 07:56:14 AM UTC 24 |
| Peak memory | 598788 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3669960974 -assert nopostproc +UVM_T ESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 98.xbar_access_same_device_slow_rsp.3669960974 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/98.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/98.xbar_error_and_unmapped_addr.3266617526 |
| Short name | T2894 |
| Test name | |
| Test status | |
| Simulation time | 625554740 ps |
| CPU time | 17 seconds |
| Started | Aug 24 07:30:53 AM UTC 24 |
| Finished | Aug 24 07:31:11 AM UTC 24 |
| Peak memory | 597836 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3266617526 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 98.xbar_error_and_unmapped_addr.3266617526 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/98.xbar_error_and_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/98.xbar_error_random.2159130740 |
| Short name | T2887 |
| Test name | |
| Test status | |
| Simulation time | 126241945 ps |
| CPU time | 9.45 seconds |
| Started | Aug 24 07:30:27 AM UTC 24 |
| Finished | Aug 24 07:30:38 AM UTC 24 |
| Peak memory | 597692 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2159130740 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 98.xbar_error_random.2159130740 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/98.xbar_error_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/98.xbar_random.370115219 |
| Short name | T2888 |
| Test name | |
| Test status | |
| Simulation time | 2118429677 ps |
| CPU time | 50.79 seconds |
| Started | Aug 24 07:29:48 AM UTC 24 |
| Finished | Aug 24 07:30:40 AM UTC 24 |
| Peak memory | 598048 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=370115219 -assert nopostproc +UVM_TESTNAME =xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 8_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 98.xbar_random.370115219 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/98.xbar_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/98.xbar_random_large_delays.1982057831 |
| Short name | T2926 |
| Test name | |
| Test status | |
| Simulation time | 53081759975 ps |
| CPU time | 440.18 seconds |
| Started | Aug 24 07:29:51 AM UTC 24 |
| Finished | Aug 24 07:37:16 AM UTC 24 |
| Peak memory | 597976 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max _device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1982057831 -assert nopostproc +U VM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 98.xbar_random_large_delays.1982057831 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/98.xbar_random_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/98.xbar_random_slow_rsp.372018175 |
| Short name | T2936 |
| Test name | |
| Test status | |
| Simulation time | 60724301301 ps |
| CPU time | 742.04 seconds |
| Started | Aug 24 07:29:52 AM UTC 24 |
| Finished | Aug 24 07:42:22 AM UTC 24 |
| Peak memory | 597824 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=372018175 -assert nopostproc +UVM_TE STNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 98.xbar_random_slow_rsp.372018175 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/98.xbar_random_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/98.xbar_random_zero_delays.1966000817 |
| Short name | T2883 |
| Test name | |
| Test status | |
| Simulation time | 150885775 ps |
| CPU time | 10.94 seconds |
| Started | Aug 24 07:29:48 AM UTC 24 |
| Finished | Aug 24 07:30:00 AM UTC 24 |
| Peak memory | 597900 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1966000817 -assert nopostpr oc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 98.xbar_random_zero_delays.1966000817 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/98.xbar_random_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/98.xbar_same_source.1019631687 |
| Short name | T2897 |
| Test name | |
| Test status | |
| Simulation time | 2592745009 ps |
| CPU time | 55.95 seconds |
| Started | Aug 24 07:30:21 AM UTC 24 |
| Finished | Aug 24 07:31:19 AM UTC 24 |
| Peak memory | 597816 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1019631687 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 98.xbar_same_source.1019631687 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/98.xbar_same_source/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/98.xbar_smoke.37938922 |
| Short name | T2879 |
| Test name | |
| Test status | |
| Simulation time | 206003197 ps |
| CPU time | 7.15 seconds |
| Started | Aug 24 07:29:25 AM UTC 24 |
| Finished | Aug 24 07:29:34 AM UTC 24 |
| Peak memory | 595888 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=37938922 -assert nopostproc +UVM_TESTNAME= xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_ 22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 98.xbar_smoke.37938922 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/98.xbar_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/98.xbar_smoke_large_delays.2042323220 |
| Short name | T2889 |
| Test name | |
| Test status | |
| Simulation time | 9499397040 ps |
| CPU time | 73.78 seconds |
| Started | Aug 24 07:29:34 AM UTC 24 |
| Finished | Aug 24 07:30:49 AM UTC 24 |
| Peak memory | 595768 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max _device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2042323220 -assert nopostproc +U VM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 98.xbar_smoke_large_delays.2042323220 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/98.xbar_smoke_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/98.xbar_smoke_slow_rsp.3448752876 |
| Short name | T2892 |
| Test name | |
| Test status | |
| Simulation time | 6381038418 ps |
| CPU time | 73.71 seconds |
| Started | Aug 24 07:29:46 AM UTC 24 |
| Finished | Aug 24 07:31:01 AM UTC 24 |
| Peak memory | 595972 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3448752876 -assert nopostproc +UVM_T ESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 98.xbar_smoke_slow_rsp.3448752876 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/98.xbar_smoke_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/98.xbar_smoke_zero_delays.2234290292 |
| Short name | T2877 |
| Test name | |
| Test status | |
| Simulation time | 45918562 ps |
| CPU time | 5.01 seconds |
| Started | Aug 24 07:29:26 AM UTC 24 |
| Finished | Aug 24 07:29:32 AM UTC 24 |
| Peak memory | 595924 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2234290292 -assert nopostpr oc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 98.xbar_smoke_zero_delays.2234290292 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/98.xbar_smoke_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/98.xbar_stress_all.3659188077 |
| Short name | T2920 |
| Test name | |
| Test status | |
| Simulation time | 7133480489 ps |
| CPU time | 212.67 seconds |
| Started | Aug 24 07:30:55 AM UTC 24 |
| Finished | Aug 24 07:34:30 AM UTC 24 |
| Peak memory | 598088 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3659188077 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 98.xbar_stress_all.3659188077 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/98.xbar_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/98.xbar_stress_all_with_error.665121790 |
| Short name | T2919 |
| Test name | |
| Test status | |
| Simulation time | 7239917138 ps |
| CPU time | 191.88 seconds |
| Started | Aug 24 07:31:06 AM UTC 24 |
| Finished | Aug 24 07:34:20 AM UTC 24 |
| Peak memory | 597888 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=665121790 -assert nopostproc +UVM_TESTNAME =xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 98.xbar_stress_all_with_error.665121790 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/98.xbar_stress_all_with_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/98.xbar_stress_all_with_rand_reset.561742029 |
| Short name | T2925 |
| Test name | |
| Test status | |
| Simulation time | 9716687388 ps |
| CPU time | 367.25 seconds |
| Started | Aug 24 07:31:04 AM UTC 24 |
| Finished | Aug 24 07:37:16 AM UTC 24 |
| Peak memory | 597820 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=561742029 -assert nopostproc +UVM_TESTNAME =xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 98.xbar_stress_all_with_rand_reset.561742029 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/98.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/98.xbar_stress_all_with_reset_error.1639035069 |
| Short name | T2927 |
| Test name | |
| Test status | |
| Simulation time | 4437655879 ps |
| CPU time | 360.46 seconds |
| Started | Aug 24 07:31:15 AM UTC 24 |
| Finished | Aug 24 07:37:21 AM UTC 24 |
| Peak memory | 597888 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1639035069 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 98.xbar_stress_all_with_reset_error.1639035069 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/98.xbar_stress_all_with_reset_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/98.xbar_unmapped_addr.3233734801 |
| Short name | T2891 |
| Test name | |
| Test status | |
| Simulation time | 493735147 ps |
| CPU time | 16.46 seconds |
| Started | Aug 24 07:30:42 AM UTC 24 |
| Finished | Aug 24 07:30:59 AM UTC 24 |
| Peak memory | 597688 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3233734801 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 98.xbar_unmapped_addr.3233734801 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/98.xbar_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/99.xbar_access_same_device.2527069604 |
| Short name | T2903 |
| Test name | |
| Test status | |
| Simulation time | 450614585 ps |
| CPU time | 22.75 seconds |
| Started | Aug 24 07:31:47 AM UTC 24 |
| Finished | Aug 24 07:32:11 AM UTC 24 |
| Peak memory | 597920 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2527069604 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 99.xbar_access_same_device.2527069604 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/99.xbar_access_same_device/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/99.xbar_access_same_device_slow_rsp.2579005951 |
| Short name | T2933 |
| Test name | |
| Test status | |
| Simulation time | 40602527189 ps |
| CPU time | 477.64 seconds |
| Started | Aug 24 07:32:01 AM UTC 24 |
| Finished | Aug 24 07:40:05 AM UTC 24 |
| Peak memory | 597820 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2579005951 -assert nopostproc +UVM_T ESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 99.xbar_access_same_device_slow_rsp.2579005951 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/99.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/99.xbar_error_and_unmapped_addr.1909807241 |
| Short name | T2912 |
| Test name | |
| Test status | |
| Simulation time | 279065314 ps |
| CPU time | 24.12 seconds |
| Started | Aug 24 07:32:46 AM UTC 24 |
| Finished | Aug 24 07:33:11 AM UTC 24 |
| Peak memory | 597964 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1909807241 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 99.xbar_error_and_unmapped_addr.1909807241 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/99.xbar_error_and_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/99.xbar_error_random.1576475118 |
| Short name | T2909 |
| Test name | |
| Test status | |
| Simulation time | 524645918 ps |
| CPU time | 26.77 seconds |
| Started | Aug 24 07:32:25 AM UTC 24 |
| Finished | Aug 24 07:32:53 AM UTC 24 |
| Peak memory | 597992 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1576475118 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 99.xbar_error_random.1576475118 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/99.xbar_error_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/99.xbar_random.2036297010 |
| Short name | T2901 |
| Test name | |
| Test status | |
| Simulation time | 642221904 ps |
| CPU time | 19.08 seconds |
| Started | Aug 24 07:31:26 AM UTC 24 |
| Finished | Aug 24 07:31:46 AM UTC 24 |
| Peak memory | 597828 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2036297010 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 99.xbar_random.2036297010 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/99.xbar_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/99.xbar_random_large_delays.2892674501 |
| Short name | T2928 |
| Test name | |
| Test status | |
| Simulation time | 44764411062 ps |
| CPU time | 367.48 seconds |
| Started | Aug 24 07:31:36 AM UTC 24 |
| Finished | Aug 24 07:37:48 AM UTC 24 |
| Peak memory | 597812 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max _device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2892674501 -assert nopostproc +U VM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 99.xbar_random_large_delays.2892674501 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/99.xbar_random_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/99.xbar_random_slow_rsp.1711308583 |
| Short name | T2938 |
| Test name | |
| Test status | |
| Simulation time | 55775143029 ps |
| CPU time | 679.91 seconds |
| Started | Aug 24 07:31:42 AM UTC 24 |
| Finished | Aug 24 07:43:10 AM UTC 24 |
| Peak memory | 598072 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1711308583 -assert nopostproc +UVM_T ESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 99.xbar_random_slow_rsp.1711308583 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/99.xbar_random_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/99.xbar_random_zero_delays.1596007302 |
| Short name | T2902 |
| Test name | |
| Test status | |
| Simulation time | 330593865 ps |
| CPU time | 21 seconds |
| Started | Aug 24 07:31:33 AM UTC 24 |
| Finished | Aug 24 07:31:55 AM UTC 24 |
| Peak memory | 597836 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1596007302 -assert nopostpr oc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 99.xbar_random_zero_delays.1596007302 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/99.xbar_random_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/99.xbar_same_source.2310052888 |
| Short name | T2906 |
| Test name | |
| Test status | |
| Simulation time | 1339736272 ps |
| CPU time | 29.86 seconds |
| Started | Aug 24 07:32:09 AM UTC 24 |
| Finished | Aug 24 07:32:41 AM UTC 24 |
| Peak memory | 597944 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2310052888 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 99.xbar_same_source.2310052888 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/99.xbar_same_source/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/99.xbar_smoke.389428392 |
| Short name | T2898 |
| Test name | |
| Test status | |
| Simulation time | 48010343 ps |
| CPU time | 5.16 seconds |
| Started | Aug 24 07:31:16 AM UTC 24 |
| Finished | Aug 24 07:31:22 AM UTC 24 |
| Peak memory | 595888 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=389428392 -assert nopostproc +UVM_TESTNAME =xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08 _22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 99.xbar_smoke.389428392 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/99.xbar_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/99.xbar_smoke_large_delays.2547933868 |
| Short name | T2907 |
| Test name | |
| Test status | |
| Simulation time | 9248329799 ps |
| CPU time | 76.23 seconds |
| Started | Aug 24 07:31:25 AM UTC 24 |
| Finished | Aug 24 07:32:43 AM UTC 24 |
| Peak memory | 595768 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max _device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2547933868 -assert nopostproc +U VM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 99.xbar_smoke_large_delays.2547933868 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/99.xbar_smoke_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/99.xbar_smoke_slow_rsp.3434503781 |
| Short name | T2905 |
| Test name | |
| Test status | |
| Simulation time | 5563368211 ps |
| CPU time | 64.19 seconds |
| Started | Aug 24 07:31:26 AM UTC 24 |
| Finished | Aug 24 07:32:32 AM UTC 24 |
| Peak memory | 595772 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3434503781 -assert nopostproc +UVM_T ESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 99.xbar_smoke_slow_rsp.3434503781 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/99.xbar_smoke_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/99.xbar_smoke_zero_delays.2945256888 |
| Short name | T2899 |
| Test name | |
| Test status | |
| Simulation time | 37709120 ps |
| CPU time | 4.58 seconds |
| Started | Aug 24 07:31:23 AM UTC 24 |
| Finished | Aug 24 07:31:28 AM UTC 24 |
| Peak memory | 595856 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2945256888 -assert nopostpr oc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 99.xbar_smoke_zero_delays.2945256888 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/99.xbar_smoke_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/99.xbar_stress_all.2133715609 |
| Short name | T2924 |
| Test name | |
| Test status | |
| Simulation time | 7941870992 ps |
| CPU time | 222.71 seconds |
| Started | Aug 24 07:32:55 AM UTC 24 |
| Finished | Aug 24 07:36:41 AM UTC 24 |
| Peak memory | 597896 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2133715609 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 99.xbar_stress_all.2133715609 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/99.xbar_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/99.xbar_stress_all_with_error.2156134804 |
| Short name | T2916 |
| Test name | |
| Test status | |
| Simulation time | 2606765939 ps |
| CPU time | 52.1 seconds |
| Started | Aug 24 07:33:04 AM UTC 24 |
| Finished | Aug 24 07:33:58 AM UTC 24 |
| Peak memory | 597924 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2156134804 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 99.xbar_stress_all_with_error.2156134804 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/99.xbar_stress_all_with_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/99.xbar_stress_all_with_rand_reset.3815215042 |
| Short name | T2931 |
| Test name | |
| Test status | |
| Simulation time | 7783925327 ps |
| CPU time | 413.07 seconds |
| Started | Aug 24 07:32:58 AM UTC 24 |
| Finished | Aug 24 07:39:56 AM UTC 24 |
| Peak memory | 598180 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3815215042 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 99.xbar_stress_all_with_rand_reset.3815215042 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/99.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/99.xbar_stress_all_with_reset_error.3488845891 |
| Short name | T2922 |
| Test name | |
| Test status | |
| Simulation time | 1450228176 ps |
| CPU time | 105.81 seconds |
| Started | Aug 24 07:33:07 AM UTC 24 |
| Finished | Aug 24 07:34:55 AM UTC 24 |
| Peak memory | 598000 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3488845891 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 99.xbar_stress_all_with_reset_error.3488845891 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/99.xbar_stress_all_with_reset_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/99.xbar_unmapped_addr.1719007761 |
| Short name | T2913 |
| Test name | |
| Test status | |
| Simulation time | 1416187157 ps |
| CPU time | 45.05 seconds |
| Started | Aug 24 07:32:26 AM UTC 24 |
| Finished | Aug 24 07:33:12 AM UTC 24 |
| Peak memory | 597944 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1719007761 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 99.xbar_unmapped_addr.1719007761 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/99.xbar_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_jtag_mem_access.2724113698 |
| Short name | T41 |
| Test name | |
| Test status | |
| Simulation time | 14010476488 ps |
| CPU time | 1012.52 seconds |
| Started | Aug 24 08:54:14 AM UTC 24 |
| Finished | Aug 24 09:11:18 AM UTC 24 |
| Peak memory | 627288 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/default/simv +create_jtag_riscv_map=1 +stub_cpu=1 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2724113698 -assert nopos tproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_jtag_mem_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_jtag_mem_access.2724113698 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/0.chip_jtag_mem_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_rv_dm_ndm_reset_req.377007290 |
| Short name | T63 |
| Test name | |
| Test status | |
| Simulation time | 4555323468 ps |
| CPU time | 243.24 seconds |
| Started | Aug 24 08:57:21 AM UTC 24 |
| Finished | Aug 24 09:01:27 AM UTC 24 |
| Peak memory | 637028 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/default/simv +en_scb_tl_err_chk=0 +use_jtag_dmi=1 +sw_build_device=sim_dv +sw_images=rv_dm_ndm_reset_req_rma:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=377007290 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_rv_dm_ndm_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover age/default.vdb -cm_log /dev/null -cm_name 0.chip_rv_dm_ndm_reset_req.377007290 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/0.chip_rv_dm_ndm_reset_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sival_flash_info_access.3285677352 |
| Short name | T5 |
| Test name | |
| Test status | |
| Simulation time | 3173659930 ps |
| CPU time | 219.23 seconds |
| Started | Aug 24 07:38:36 AM UTC 24 |
| Finished | Aug 24 07:42:19 AM UTC 24 |
| Peak memory | 624648 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/default/simv +use_otp_image=OtpTypeLcStTestUnlocked0 +sw_build_device=sim _dv +sw_images=flash_ctrl_info_access_lc:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3285677352 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_ba se_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 0.chip_sival_flash_info_access.3285677352 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/0.chip_sival_flash_info_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_aes_enc.4213650013 |
| Short name | T653 |
| Test name | |
| Test status | |
| Simulation time | 2361909292 ps |
| CPU time | 225.79 seconds |
| Started | Aug 24 08:13:24 AM UTC 24 |
| Finished | Aug 24 08:17:13 AM UTC 24 |
| Peak memory | 624772 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=22_000_000 +sw_build_device=sim_dv +sw_i mages=aes_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/ repo/hw/dv/tools/sim.tcl +ntb_random_seed=4213650013 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_aes_enc.4213650013 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/0.chip_sw_aes_enc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_aes_enc_jitter_en.3641949833 |
| Short name | T654 |
| Test name | |
| Test status | |
| Simulation time | 3329183627 ps |
| CPU time | 169.94 seconds |
| Started | Aug 24 08:13:26 AM UTC 24 |
| Finished | Aug 24 08:16:19 AM UTC 24 |
| Peak memory | 624560 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=26_000_000 +en_jitter=1 +sw_build_device =sim_dv +sw_images=aes_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3641949833 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/defaul t.vdb -cm_log /dev/null -cm_name 0.chip_sw_aes_enc_jitter_en.3641949833 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/0.chip_sw_aes_enc_jitter_en/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_aes_enc_jitter_en_reduced_freq.2092271956 |
| Short name | T302 |
| Test name | |
| Test status | |
| Simulation time | 3389369789 ps |
| CPU time | 206.53 seconds |
| Started | Aug 24 09:04:38 AM UTC 24 |
| Finished | Aug 24 09:08:08 AM UTC 24 |
| Peak memory | 626860 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=26_000_000 +en_jitter=1 +cal_sys_clk_70m hz=1 +sw_build_device=sim_dv +sw_images=aes_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2092271956 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_S EQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_aes_enc_jitter_en_reduced_freq.2092271956 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/0.chip_sw_aes_enc_jitter_en_reduced_freq/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_aes_entropy.3028895167 |
| Short name | T401 |
| Test name | |
| Test status | |
| Simulation time | 2682824492 ps |
| CPU time | 143.22 seconds |
| Started | Aug 24 08:18:12 AM UTC 24 |
| Finished | Aug 24 08:20:38 AM UTC 24 |
| Peak memory | 624808 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=15_000_000 +sw_build_device=sim_dv +sw_i mages=aes_entropy_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac es/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3028895167 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_ log /dev/null -cm_name 0.chip_sw_aes_entropy.3028895167 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/0.chip_sw_aes_entropy/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_aes_idle.1506390767 |
| Short name | T655 |
| Test name | |
| Test status | |
| Simulation time | 2655928636 ps |
| CPU time | 190.21 seconds |
| Started | Aug 24 08:13:56 AM UTC 24 |
| Finished | Aug 24 08:17:09 AM UTC 24 |
| Peak memory | 624552 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=25_000_000 +sw_build_device=sim_dv +sw_i mages=aes_idle_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/ repo/hw/dv/tools/sim.tcl +ntb_random_seed=1506390767 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_aes_idle.1506390767 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/0.chip_sw_aes_idle/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_aes_masking_off.2101535160 |
| Short name | T450 |
| Test name | |
| Test status | |
| Simulation time | 2348054616 ps |
| CPU time | 186.32 seconds |
| Started | Aug 24 08:14:14 AM UTC 24 |
| Finished | Aug 24 08:17:23 AM UTC 24 |
| Peak memory | 625028 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=aes_masking_off_test:1:ne w_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2101535160 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_aes_masking_off_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -c m_name 0.chip_sw_aes_masking_off.2101535160 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/0.chip_sw_aes_masking_off/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_aes_smoketest.3184695913 |
| Short name | T910 |
| Test name | |
| Test status | |
| Simulation time | 3759604620 ps |
| CPU time | 224.96 seconds |
| Started | Aug 24 10:46:38 AM UTC 24 |
| Finished | Aug 24 10:50:26 AM UTC 24 |
| Peak memory | 624824 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=aes_smoketest:1:new_rules ,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_r andom_seed=3184695913 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_a es_smoketest.3184695913 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/0.chip_sw_aes_smoketest/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_alert_handler_entropy.2368404336 |
| Short name | T106 |
| Test name | |
| Test status | |
| Simulation time | 2916421598 ps |
| CPU time | 214.07 seconds |
| Started | Aug 24 08:17:58 AM UTC 24 |
| Finished | Aug 24 08:21:36 AM UTC 24 |
| Peak memory | 626872 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/default/simv +en_scb=0 +bypass_alert_ready_to_end_check=1 +sw_build_devic e=sim_dv +sw_images=alert_handler_entropy_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2368404336 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip _sw_alert_handler_entropy_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgr ey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_alert_handler_entropy.2368404336 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/0.chip_sw_alert_handler_entropy/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_alert_handler_escalation.4292859360 |
| Short name | T262 |
| Test name | |
| Test status | |
| Simulation time | 5238105424 ps |
| CPU time | 376.58 seconds |
| Started | Aug 24 08:15:15 AM UTC 24 |
| Finished | Aug 24 08:21:36 AM UTC 24 |
| Peak memory | 637088 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/default/simv +en_scb=0 +bypass_alert_ready_to_end_check=1 +sw_build_devic e=sim_dv +sw_images=alert_handler_escalation_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4292859360 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=c hip_sw_alert_handler_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/chip_ earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_alert_handler_escalation.4292859360 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/0.chip_sw_alert_handler_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_alert_handler_lpg_clkoff.1332713924 |
| Short name | T362 |
| Test name | |
| Test status | |
| Simulation time | 7503725176 ps |
| CPU time | 1133.52 seconds |
| Started | Aug 24 08:17:59 AM UTC 24 |
| Finished | Aug 24 08:37:05 AM UTC 24 |
| Peak memory | 626872 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +sw_build_device= sim_dv +sw_images=alert_handler_lpg_clkoff_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1332713924 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chi p_sw_alert_handler_lpg_clkoff_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/chip_ea rlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_alert_handler_lpg_clkoff.1332713924 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/0.chip_sw_alert_handler_lpg_clkoff/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_alert_handler_lpg_reset_toggle.1677932817 |
| Short name | T249 |
| Test name | |
| Test status | |
| Simulation time | 7651412108 ps |
| CPU time | 1154.21 seconds |
| Started | Aug 24 08:17:58 AM UTC 24 |
| Finished | Aug 24 08:37:25 AM UTC 24 |
| Peak memory | 626844 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +sw_build_device= sim_dv +sw_images=alert_handler_lpg_reset_toggle_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1677932817 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_S EQ=chip_sw_alert_handler_shorten_ping_wait_cycle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_alert_handler_lpg_reset_toggle.1677932817 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/0.chip_sw_alert_handler_lpg_reset_toggle/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_alert_handler_lpg_sleep_mode_alerts.3823927794 |
| Short name | T199 |
| Test name | |
| Test status | |
| Simulation time | 3308548896 ps |
| CPU time | 297.41 seconds |
| Started | Aug 24 08:16:48 AM UTC 24 |
| Finished | Aug 24 08:21:50 AM UTC 24 |
| Peak memory | 637764 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_rea dy_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv _core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_handler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3823927794 -assert nopos tproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_alert_handler_lpg_s leep_mode_alerts.3823927794 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/0.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_alert_handler_ping_timeout.1531717315 |
| Short name | T400 |
| Test name | |
| Test status | |
| Simulation time | 3249952856 ps |
| CPU time | 257.57 seconds |
| Started | Aug 24 08:15:26 AM UTC 24 |
| Finished | Aug 24 08:19:47 AM UTC 24 |
| Peak memory | 626612 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/default/simv +en_scb=0 +sw_test_timeout_ns=24000000 +sw_build_device=sim_ dv +sw_images=alert_handler_ping_timeout_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu eue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1531717315 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_ sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_alert_handler_ping_timeout.1531717315 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/0.chip_sw_alert_handler_ping_timeout/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_alert_handler_reverse_ping_in_deep_sleep.1836453348 |
| Short name | T108 |
| Test name | |
| Test status | |
| Simulation time | 256081612496 ps |
| CPU time | 10920.6 seconds |
| Started | Aug 24 08:16:48 AM UTC 24 |
| Finished | Aug 24 11:20:45 AM UTC 24 |
| Peak memory | 629988 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/default/simv +en_scb=0 +sw_test_timeout_ns=300_000_000 +sw_build_device=s im_dv +sw_images=alert_handler_reverse_ping_in_deep_sleep_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1836453348 -assert nopostproc +UVM_TESTNAME=chip_base_test +U VM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgre y_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_alert_handler_reverse_ping_in_deep_sleep.1836453348 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/0.chip_sw_alert_handler_reverse_ping_in_deep_sleep/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_aon_timer_irq.1256511542 |
| Short name | T252 |
| Test name | |
| Test status | |
| Simulation time | 4609027008 ps |
| CPU time | 311.6 seconds |
| Started | Aug 24 08:07:07 AM UTC 24 |
| Finished | Aug 24 08:12:23 AM UTC 24 |
| Peak memory | 626740 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_i mages=aon_timer_irq_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp aces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1256511542 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -c m_log /dev/null -cm_name 0.chip_sw_aon_timer_irq.1256511542 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/0.chip_sw_aon_timer_irq/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_aon_timer_sleep_wdog_sleep_pause.1193920927 |
| Short name | T871 |
| Test name | |
| Test status | |
| Simulation time | 7246029880 ps |
| CPU time | 339.65 seconds |
| Started | Aug 24 08:08:15 AM UTC 24 |
| Finished | Aug 24 08:13:59 AM UTC 24 |
| Peak memory | 626676 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_i mages=aon_timer_sleep_wdog_sleep_pause_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu e -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1193920927 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw _base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cove rage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_aon_timer_sleep_wdog_sleep_pause.1193920927 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/0.chip_sw_aon_timer_sleep_wdog_sleep_pause/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_aon_timer_smoketest.1843655145 |
| Short name | T913 |
| Test name | |
| Test status | |
| Simulation time | 3718274978 ps |
| CPU time | 246.32 seconds |
| Started | Aug 24 10:47:03 AM UTC 24 |
| Finished | Aug 24 10:51:12 AM UTC 24 |
| Peak memory | 624572 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=aon_timer_smoketest:1:new _rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1843655145 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.chi p_sw_aon_timer_smoketest.1843655145 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/0.chip_sw_aon_timer_smoketest/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_aon_timer_wdog_bite_reset.1198059536 |
| Short name | T873 |
| Test name | |
| Test status | |
| Simulation time | 6931699210 ps |
| CPU time | 399.65 seconds |
| Started | Aug 24 08:08:59 AM UTC 24 |
| Finished | Aug 24 08:15:44 AM UTC 24 |
| Peak memory | 626832 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_i mages=aon_timer_wdog_bite_reset_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1198059536 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/de fault.vdb -cm_log /dev/null -cm_name 0.chip_sw_aon_timer_wdog_bite_reset.1198059536 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/0.chip_sw_aon_timer_wdog_bite_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_aon_timer_wdog_lc_escalate.4266456603 |
| Short name | T363 |
| Test name | |
| Test status | |
| Simulation time | 6158669650 ps |
| CPU time | 488.74 seconds |
| Started | Aug 24 08:09:01 AM UTC 24 |
| Finished | Aug 24 08:17:15 AM UTC 24 |
| Peak memory | 626868 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_i mages=aon_timer_wdog_lc_escalate_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4266456603 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 0.chip_sw_aon_timer_wdog_lc_escalate.4266456603 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/0.chip_sw_aon_timer_wdog_lc_escalate/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_ast_clk_outputs.3241762085 |
| Short name | T300 |
| Test name | |
| Test status | |
| Simulation time | 8355715430 ps |
| CPU time | 717.47 seconds |
| Started | Aug 24 08:54:24 AM UTC 24 |
| Finished | Aug 24 09:06:30 AM UTC 24 |
| Peak memory | 632836 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/default/simv +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=ast_ clk_outs_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/h w/dv/tools/sim.tcl +ntb_random_seed=3241762085 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_ast_clk_outputs_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -c m_log /dev/null -cm_name 0.chip_sw_ast_clk_outputs.3241762085 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/0.chip_sw_ast_clk_outputs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_lc.2104654339 |
| Short name | T229 |
| Test name | |
| Test status | |
| Simulation time | 11450501043 ps |
| CPU time | 567.39 seconds |
| Started | Aug 24 08:46:16 AM UTC 24 |
| Finished | Aug 24 08:55:50 AM UTC 24 |
| Peak memory | 637004 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/default/simv +chip_clock_source=ChipClockSourceExternal48Mhz +sw_build_de vice=sim_dv +sw_images=clkmgr_external_clk_src_for_lc_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2104654339 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_T EST_SEQ=chip_sw_lc_ctrl_transition_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/ch ip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_clkmgr_external_clk_src_for_lc.2104654339 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/0.chip_sw_clkmgr_external_clk_src_for_lc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_sw_fast_rma.3660983762 |
| Short name | T883 |
| Test name | |
| Test status | |
| Simulation time | 3359419680 ps |
| CPU time | 425.21 seconds |
| Started | Aug 24 08:50:22 AM UTC 24 |
| Finished | Aug 24 08:57:32 AM UTC 24 |
| Peak memory | 626820 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/default/simv +chip_clock_source=ChipClockSourceExternal96Mhz +calibrate_u sb_clk=1 +src_dec_state=DecLcStRma +sw_build_device=sim_dv +sw_images=clkmgr_external_clk_src_for_sw_fast_test:1:new_rules,test_rom:0 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3660983762 -a ssert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces /repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_clkmgr_external_clk_sr c_for_sw_fast_rma.3660983762 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/0.chip_sw_clkmgr_external_clk_src_for_sw_fast_rma/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0.352375194 |
| Short name | T153 |
| Test name | |
| Test status | |
| Simulation time | 4291783400 ps |
| CPU time | 458.27 seconds |
| Started | Aug 24 08:46:17 AM UTC 24 |
| Finished | Aug 24 08:54:01 AM UTC 24 |
| Peak memory | 626724 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/default/simv +chip_clock_source=ChipClockSourceExternal96Mhz +calibrate_u sb_clk=1 +src_dec_state=DecLcStTestUnlocked0 +sw_build_device=sim_dv +sw_images=clkmgr_external_clk_src_for_sw_fast_test:1:new_rules,test_rom:0 +c dc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=352 375194 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_clkmgr_extern al_clk_src_for_sw_fast_test_unlocked0.352375194 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/0.chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_sw_slow_dev.3970454605 |
| Short name | T881 |
| Test name | |
| Test status | |
| Simulation time | 4400892998 ps |
| CPU time | 400.54 seconds |
| Started | Aug 24 08:49:36 AM UTC 24 |
| Finished | Aug 24 08:56:22 AM UTC 24 |
| Peak memory | 626620 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/default/simv +chip_clock_source=ChipClockSourceExternal48Mhz +calibrate_u sb_clk=1 +src_dec_state=DecLcStDev +sw_build_device=sim_dv +sw_images=clkmgr_external_clk_src_for_sw_slow_test:1:new_rules,test_rom:0 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3970454605 -a ssert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces /repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_clkmgr_external_clk_sr c_for_sw_slow_dev.3970454605 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/0.chip_sw_clkmgr_external_clk_src_for_sw_slow_dev/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_sw_slow_rma.1655243043 |
| Short name | T884 |
| Test name | |
| Test status | |
| Simulation time | 4563600772 ps |
| CPU time | 451.61 seconds |
| Started | Aug 24 08:50:22 AM UTC 24 |
| Finished | Aug 24 08:57:59 AM UTC 24 |
| Peak memory | 628872 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/default/simv +chip_clock_source=ChipClockSourceExternal48Mhz +calibrate_u sb_clk=1 +src_dec_state=DecLcStRma +sw_build_device=sim_dv +sw_images=clkmgr_external_clk_src_for_sw_slow_test:1:new_rules,test_rom:0 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1655243043 -a ssert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces /repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_clkmgr_external_clk_sr c_for_sw_slow_rma.1655243043 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/0.chip_sw_clkmgr_external_clk_src_for_sw_slow_rma/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0.1931021013 |
| Short name | T152 |
| Test name | |
| Test status | |
| Simulation time | 5262669590 ps |
| CPU time | 402.18 seconds |
| Started | Aug 24 08:47:12 AM UTC 24 |
| Finished | Aug 24 08:53:59 AM UTC 24 |
| Peak memory | 626620 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/default/simv +chip_clock_source=ChipClockSourceExternal48Mhz +calibrate_u sb_clk=1 +src_dec_state=DecLcStTestUnlocked0 +sw_build_device=sim_dv +sw_images=clkmgr_external_clk_src_for_sw_slow_test:1:new_rules,test_rom:0 +c dc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=193 1021013 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_clkmgr_exter nal_clk_src_for_sw_slow_test_unlocked0.1931021013 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/0.chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_clkmgr_jitter.231741957 |
| Short name | T880 |
| Test name | |
| Test status | |
| Simulation time | 2585089901 ps |
| CPU time | 199.78 seconds |
| Started | Aug 24 08:52:44 AM UTC 24 |
| Finished | Aug 24 08:56:06 AM UTC 24 |
| Peak memory | 624820 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=clkmgr_jitter_test:1:new_ rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl + ntb_random_seed=231741957 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a ssert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_ sw_clkmgr_jitter.231741957 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/0.chip_sw_clkmgr_jitter/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_clkmgr_jitter_frequency.2661636375 |
| Short name | T882 |
| Test name | |
| Test status | |
| Simulation time | 3730160020 ps |
| CPU time | 321.85 seconds |
| Started | Aug 24 08:51:31 AM UTC 24 |
| Finished | Aug 24 08:56:57 AM UTC 24 |
| Peak memory | 626620 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=clkmgr_jitter_frequency_t est:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools /sim.tcl +ntb_random_seed=2661636375 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_n ame 0.chip_sw_clkmgr_jitter_frequency.2661636375 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/0.chip_sw_clkmgr_jitter_frequency/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_clkmgr_jitter_reduced_freq.265969829 |
| Short name | T298 |
| Test name | |
| Test status | |
| Simulation time | 2281585028 ps |
| CPU time | 137.65 seconds |
| Started | Aug 24 09:03:20 AM UTC 24 |
| Finished | Aug 24 09:05:40 AM UTC 24 |
| Peak memory | 624820 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/default/simv +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +sw_images=clkm gr_jitter_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/ hw/dv/tools/sim.tcl +ntb_random_seed=265969829 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/ null -cm_name 0.chip_sw_clkmgr_jitter_reduced_freq.265969829 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/0.chip_sw_clkmgr_jitter_reduced_freq/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_clkmgr_off_hmac_trans.1956759960 |
| Short name | T309 |
| Test name | |
| Test status | |
| Simulation time | 4545614224 ps |
| CPU time | 289.96 seconds |
| Started | Aug 24 08:45:01 AM UTC 24 |
| Finished | Aug 24 08:49:55 AM UTC 24 |
| Peak memory | 626620 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=clkmgr_off_hmac_trans_tes t:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/s im.tcl +ntb_random_seed=1956759960 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam e 0.chip_sw_clkmgr_off_hmac_trans.1956759960 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/0.chip_sw_clkmgr_off_hmac_trans/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_clkmgr_off_kmac_trans.3510746206 |
| Short name | T310 |
| Test name | |
| Test status | |
| Simulation time | 4243176840 ps |
| CPU time | 301.56 seconds |
| Started | Aug 24 08:45:16 AM UTC 24 |
| Finished | Aug 24 08:50:21 AM UTC 24 |
| Peak memory | 626876 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=clkmgr_off_kmac_trans_tes t:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/s im.tcl +ntb_random_seed=3510746206 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam e 0.chip_sw_clkmgr_off_kmac_trans.3510746206 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/0.chip_sw_clkmgr_off_kmac_trans/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_clkmgr_off_otbn_trans.2953918159 |
| Short name | T308 |
| Test name | |
| Test status | |
| Simulation time | 4671089732 ps |
| CPU time | 255.96 seconds |
| Started | Aug 24 08:45:31 AM UTC 24 |
| Finished | Aug 24 08:49:50 AM UTC 24 |
| Peak memory | 626696 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=clkmgr_off_otbn_trans_tes t:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/s im.tcl +ntb_random_seed=2953918159 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam e 0.chip_sw_clkmgr_off_otbn_trans.2953918159 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/0.chip_sw_clkmgr_off_otbn_trans/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_clkmgr_off_peri.886836213 |
| Short name | T432 |
| Test name | |
| Test status | |
| Simulation time | 13313705198 ps |
| CPU time | 1048.7 seconds |
| Started | Aug 24 08:43:51 AM UTC 24 |
| Finished | Aug 24 09:01:32 AM UTC 24 |
| Peak memory | 626616 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=30_000_000 +sw_build_device=sim_dv +sw_i mages=clkmgr_off_peri_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=886836213 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default.vdb - cm_log /dev/null -cm_name 0.chip_sw_clkmgr_off_peri.886836213 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/0.chip_sw_clkmgr_off_peri/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_clkmgr_reset_frequency.1860844250 |
| Short name | T674 |
| Test name | |
| Test status | |
| Simulation time | 3267030184 ps |
| CPU time | 290.75 seconds |
| Started | Aug 24 08:50:45 AM UTC 24 |
| Finished | Aug 24 08:55:39 AM UTC 24 |
| Peak memory | 626756 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/default/simv +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=clkm gr_reset_frequency_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1860844250 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm _log /dev/null -cm_name 0.chip_sw_clkmgr_reset_frequency.1860844250 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/0.chip_sw_clkmgr_reset_frequency/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_clkmgr_sleep_frequency.2716961586 |
| Short name | T885 |
| Test name | |
| Test status | |
| Simulation time | 4996233996 ps |
| CPU time | 416.78 seconds |
| Started | Aug 24 08:53:30 AM UTC 24 |
| Finished | Aug 24 09:00:32 AM UTC 24 |
| Peak memory | 626816 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/default/simv +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=clkm gr_sleep_frequency_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2716961586 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm _log /dev/null -cm_name 0.chip_sw_clkmgr_sleep_frequency.2716961586 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/0.chip_sw_clkmgr_sleep_frequency/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_clkmgr_smoketest.3205415012 |
| Short name | T909 |
| Test name | |
| Test status | |
| Simulation time | 2475359890 ps |
| CPU time | 148.43 seconds |
| Started | Aug 24 10:47:33 AM UTC 24 |
| Finished | Aug 24 10:50:04 AM UTC 24 |
| Peak memory | 624568 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=clkmgr_smoketest:1:new_ru les,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +nt b_random_seed=3205415012 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as sert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_s w_clkmgr_smoketest.3205415012 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/0.chip_sw_clkmgr_smoketest/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_coremark.2089345432 |
| Short name | T1051 |
| Test name | |
| Test status | |
| Simulation time | 71604258350 ps |
| CPU time | 14450.9 seconds |
| Started | Aug 24 08:38:39 AM UTC 24 |
| Finished | Aug 24 12:41:59 PM UTC 24 |
| Peak memory | 629668 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/default/simv +en_uart_logger=1 +sw_test_timeout_ns=200_000_000 +sw_build_ device=sim_dv +sw_images=coremark_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2089345432 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart _tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/covera ge/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_coremark.2089345432 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/0.chip_sw_coremark/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_csrng_edn_concurrency.3337541042 |
| Short name | T274 |
| Test name | |
| Test status | |
| Simulation time | 24806571732 ps |
| CPU time | 5130.5 seconds |
| Started | Aug 24 08:22:14 AM UTC 24 |
| Finished | Aug 24 09:48:40 AM UTC 24 |
| Peak memory | 629936 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=140_000_000 +rng_srate_value_min=15 +rng _srate_value_max=20 +accelerate_cold_power_up_time=3 +accelerate_regulators_power_up_time=2 +sw_build_device=sim_dv +sw_images=csrng_edn_concurren cy_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/t ools/sim.tcl +ntb_random_seed=3337541042 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null - cm_name 0.chip_sw_csrng_edn_concurrency.3337541042 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/0.chip_sw_csrng_edn_concurrency/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_csrng_fuse_en_sw_app_read_test.663715134 |
| Short name | T225 |
| Test name | |
| Test status | |
| Simulation time | 4389872896 ps |
| CPU time | 325.94 seconds |
| Started | Aug 24 08:22:16 AM UTC 24 |
| Finished | Aug 24 08:27:46 AM UTC 24 |
| Peak memory | 626616 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=15_000_000 +sw_build_device=sim_dv +sw_i mages=csrng_fuse_en_sw_app_read:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=663715134 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_entropy_src_ fuse_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover age/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_csrng_fuse_en_sw_app_read_test.663715134 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/0.chip_sw_csrng_fuse_en_sw_app_read_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_csrng_kat_test.688137537 |
| Short name | T876 |
| Test name | |
| Test status | |
| Simulation time | 2887539068 ps |
| CPU time | 226.01 seconds |
| Started | Aug 24 08:22:14 AM UTC 24 |
| Finished | Aug 24 08:26:03 AM UTC 24 |
| Peak memory | 624880 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_i mages=csrng_kat_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces /repo/hw/dv/tools/sim.tcl +ntb_random_seed=688137537 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_csrng_kat_test.688137537 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/0.chip_sw_csrng_kat_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_csrng_smoketest.3243112816 |
| Short name | T912 |
| Test name | |
| Test status | |
| Simulation time | 2846686880 ps |
| CPU time | 136.35 seconds |
| Started | Aug 24 10:48:24 AM UTC 24 |
| Finished | Aug 24 10:50:43 AM UTC 24 |
| Peak memory | 624824 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=csrng_smoketest:1:new_rul es,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb _random_seed=3243112816 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw _csrng_smoketest.3243112816 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/0.chip_sw_csrng_smoketest/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_edn_entropy_reqs.226637657 |
| Short name | T331 |
| Test name | |
| Test status | |
| Simulation time | 6102467050 ps |
| CPU time | 815.85 seconds |
| Started | Aug 24 08:23:57 AM UTC 24 |
| Finished | Aug 24 08:37:42 AM UTC 24 |
| Peak memory | 626984 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=15000000 +rng_srate_value_min=15 +rng_sr ate_value_max=30 +sw_build_device=sim_dv +sw_images=entropy_src_edn_reqs_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=226637657 -assert nopostproc +UVM_TESTNAME=chi p_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_2 2/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_edn_entropy_reqs.226637657 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/0.chip_sw_edn_entropy_reqs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_edn_entropy_reqs_jitter.1431974451 |
| Short name | T144 |
| Test name | |
| Test status | |
| Simulation time | 5183075508 ps |
| CPU time | 618.23 seconds |
| Started | Aug 24 08:24:45 AM UTC 24 |
| Finished | Aug 24 08:35:11 AM UTC 24 |
| Peak memory | 627252 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=15000000 +rng_srate_value_min=15 +rng_sr ate_value_max=30 +en_jitter=1 +sw_build_device=sim_dv +sw_images=entropy_src_edn_reqs_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1431974451 -assert nopostproc +UV M_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_edn_entropy_reqs_jitter.1431974451 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/0.chip_sw_edn_entropy_reqs_jitter/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_edn_kat.1722923307 |
| Short name | T157 |
| Test name | |
| Test status | |
| Simulation time | 3382341590 ps |
| CPU time | 436.04 seconds |
| Started | Aug 24 08:19:53 AM UTC 24 |
| Finished | Aug 24 08:27:15 AM UTC 24 |
| Peak memory | 631228 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=18_000_000 +rng_srate_value=5 +disable_a ssert_edn_output_diff_from_prev=1 +accelerate_cold_power_up_time=3 +accelerate_regulators_power_up_time=2 +sw_build_device=sim_dv +sw_images=edn_k at:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/ sim.tcl +ntb_random_seed=1722923307 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tg l+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_na me 0.chip_sw_edn_kat.1722923307 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/0.chip_sw_edn_kat/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_edn_sw_mode.3253489407 |
| Short name | T627 |
| Test name | |
| Test status | |
| Simulation time | 6318201284 ps |
| CPU time | 790.63 seconds |
| Started | Aug 24 08:20:11 AM UTC 24 |
| Finished | Aug 24 08:33:32 AM UTC 24 |
| Peak memory | 626596 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_i mages=edn_sw_mode:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/re po/hw/dv/tools/sim.tcl +ntb_random_seed=3253489407 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 0.chip_sw_edn_sw_mode.3253489407 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/0.chip_sw_edn_sw_mode/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_entropy_src_ast_rng_req.412170620 |
| Short name | T875 |
| Test name | |
| Test status | |
| Simulation time | 2683128460 ps |
| CPU time | 173.15 seconds |
| Started | Aug 24 08:22:25 AM UTC 24 |
| Finished | Aug 24 08:25:21 AM UTC 24 |
| Peak memory | 624560 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=15_000_000 +sw_build_device=sim_dv +sw_i mages=entropy_src_ast_rng_req_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli - do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=412170620 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 0.chip_sw_entropy_src_ast_rng_req.412170620 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/0.chip_sw_entropy_src_ast_rng_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_entropy_src_kat_test.3059910101 |
| Short name | T160 |
| Test name | |
| Test status | |
| Simulation time | 2627933060 ps |
| CPU time | 190.46 seconds |
| Started | Aug 24 08:18:47 AM UTC 24 |
| Finished | Aug 24 08:22:01 AM UTC 24 |
| Peak memory | 624560 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_i mages=entropy_src_kat_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3059910101 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_entropy_src_kat_test.3059910101 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/0.chip_sw_entropy_src_kat_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_entropy_src_smoketest.4122654479 |
| Short name | T921 |
| Test name | |
| Test status | |
| Simulation time | 4369369604 ps |
| CPU time | 406.6 seconds |
| Started | Aug 24 10:48:34 AM UTC 24 |
| Finished | Aug 24 10:55:26 AM UTC 24 |
| Peak memory | 624568 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/default/simv +rng_srate_value_min=15 +rng_srate_value_max=30 +sw_build_de vice=sim_dv +sw_images=entropy_src_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4122654479 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_s w_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_entropy_src_smoketest.4122654479 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/0.chip_sw_entropy_src_smoketest/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_example_concurrency.1476573709 |
| Short name | T4 |
| Test name | |
| Test status | |
| Simulation time | 3117769526 ps |
| CPU time | 183.03 seconds |
| Started | Aug 24 07:36:12 AM UTC 24 |
| Finished | Aug 24 07:39:18 AM UTC 24 |
| Peak memory | 624568 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=example_concurrency_test: 1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim .tcl +ntb_random_seed=1476573709 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_example_concurrency.1476573709 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/0.chip_sw_example_concurrency/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_example_flash.1778061035 |
| Short name | T3 |
| Test name | |
| Test status | |
| Simulation time | 3066409232 ps |
| CPU time | 132.55 seconds |
| Started | Aug 24 07:35:47 AM UTC 24 |
| Finished | Aug 24 07:38:02 AM UTC 24 |
| Peak memory | 624572 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=example_test_from_flash:1 :new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim. tcl +ntb_random_seed=1778061035 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0 .chip_sw_example_flash.1778061035 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/0.chip_sw_example_flash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_example_manufacturer.467350020 |
| Short name | T2 |
| Test name | |
| Test status | |
| Simulation time | 2342548948 ps |
| CPU time | 124.56 seconds |
| Started | Aug 24 07:35:47 AM UTC 24 |
| Finished | Aug 24 07:37:54 AM UTC 24 |
| Peak memory | 624708 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=example_test:1:new_rules, test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=467350020 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_exa mple_manufacturer.467350020 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/0.chip_sw_example_manufacturer/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_example_rom.1518978389 |
| Short name | T1 |
| Test name | |
| Test status | |
| Simulation time | 2788325496 ps |
| CPU time | 107.93 seconds |
| Started | Aug 24 07:35:45 AM UTC 24 |
| Finished | Aug 24 07:37:35 AM UTC 24 |
| Peak memory | 624488 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=example_test_from_rom:0:t est_in_rom:new_rules +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.t cl +ntb_random_seed=1518978389 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0. chip_sw_example_rom.1518978389 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/0.chip_sw_example_rom/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_exit_test_unlocked_bootstrap.2177052269 |
| Short name | T188 |
| Test name | |
| Test status | |
| Simulation time | 60406352951 ps |
| CPU time | 9829.89 seconds |
| Started | Aug 24 07:40:41 AM UTC 24 |
| Finished | Aug 24 10:26:13 AM UTC 24 |
| Peak memory | 644188 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/default/simv +flash_program_latency=5 +sw_test_timeout_ns=150_000_000 +sw _build_device=sim_dv +sw_images=exit_test_unlocked_bootstrap:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY =UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2177052269 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM _TEST_SEQ=chip_sw_exit_test_unlocked_bootstrap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_exit_test_unlocked_bootstrap.2177052269 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/0.chip_sw_exit_test_unlocked_bootstrap/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_flash_crash_alert.1933809171 |
| Short name | T344 |
| Test name | |
| Test status | |
| Simulation time | 5306551072 ps |
| CPU time | 436.66 seconds |
| Started | Aug 24 09:02:50 AM UTC 24 |
| Finished | Aug 24 09:10:12 AM UTC 24 |
| Peak memory | 627044 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/default/simv +test_timeout_ns=8_000_000 +bypass_alert_ready_to_end_check= 1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1933809171 -assert nopostproc +UVM_TESTNAME=chip_base_test + UVM_TEST_SEQ=chip_sw_flash_host_gnt_err_inj_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _08_22/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_flash_crash_alert.1933809171 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/0.chip_sw_flash_crash_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_flash_ctrl_access.1705294518 |
| Short name | T870 |
| Test name | |
| Test status | |
| Simulation time | 5286767248 ps |
| CPU time | 663.43 seconds |
| Started | Aug 24 07:47:01 AM UTC 24 |
| Finished | Aug 24 07:58:12 AM UTC 24 |
| Peak memory | 624700 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=flash_ctrl_test:1:new_rul es,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb _random_seed=1705294518 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw _flash_ctrl_access.1705294518 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/0.chip_sw_flash_ctrl_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_flash_ctrl_access_jitter_en.480930283 |
| Short name | T147 |
| Test name | |
| Test status | |
| Simulation time | 5924054425 ps |
| CPU time | 653.02 seconds |
| Started | Aug 24 07:47:01 AM UTC 24 |
| Finished | Aug 24 07:58:02 AM UTC 24 |
| Peak memory | 626924 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/default/simv +en_jitter=1 +sw_build_device=sim_dv +sw_images=flash_ctrl_t est:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools /sim.tcl +ntb_random_seed=480930283 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tg l+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_na me 0.chip_sw_flash_ctrl_access_jitter_en.480930283 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/0.chip_sw_flash_ctrl_access_jitter_en/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_flash_ctrl_access_jitter_en_reduced_freq.3670241933 |
| Short name | T888 |
| Test name | |
| Test status | |
| Simulation time | 8069992724 ps |
| CPU time | 811.85 seconds |
| Started | Aug 24 09:04:04 AM UTC 24 |
| Finished | Aug 24 09:17:45 AM UTC 24 |
| Peak memory | 624788 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/default/simv +en_jitter=1 +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +s w_images=flash_ctrl_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp aces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3670241933 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -c m_log /dev/null -cm_name 0.chip_sw_flash_ctrl_access_jitter_en_reduced_freq.3670241933 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/0.chip_sw_flash_ctrl_access_jitter_en_reduced_freq/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_flash_ctrl_clock_freqs.1880902799 |
| Short name | T148 |
| Test name | |
| Test status | |
| Simulation time | 5865859388 ps |
| CPU time | 688.15 seconds |
| Started | Aug 24 07:47:08 AM UTC 24 |
| Finished | Aug 24 07:58:44 AM UTC 24 |
| Peak memory | 624644 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=flash_ctrl_clock_freqs_te st:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/ sim.tcl +ntb_random_seed=1880902799 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tg l+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_na me 0.chip_sw_flash_ctrl_clock_freqs.1880902799 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/0.chip_sw_flash_ctrl_clock_freqs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_flash_ctrl_idle_low_power.3080113373 |
| Short name | T251 |
| Test name | |
| Test status | |
| Simulation time | 4173035096 ps |
| CPU time | 278.94 seconds |
| Started | Aug 24 07:47:08 AM UTC 24 |
| Finished | Aug 24 07:51:51 AM UTC 24 |
| Peak memory | 626676 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=flash_ctrl_idle_low_power _test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/too ls/sim.tcl +ntb_random_seed=3080113373 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm _name 0.chip_sw_flash_ctrl_idle_low_power.3080113373 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/0.chip_sw_flash_ctrl_idle_low_power/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_flash_ctrl_mem_protection.2031685245 |
| Short name | T435 |
| Test name | |
| Test status | |
| Simulation time | 5303049946 ps |
| CPU time | 786.36 seconds |
| Started | Aug 24 09:07:04 AM UTC 24 |
| Finished | Aug 24 09:20:19 AM UTC 24 |
| Peak memory | 624832 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=flash_ctrl_mem_protection _test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/too ls/sim.tcl +ntb_random_seed=2031685245 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm _name 0.chip_sw_flash_ctrl_mem_protection.2031685245 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/0.chip_sw_flash_ctrl_mem_protection/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_flash_ctrl_ops_jitter_en.4197686234 |
| Short name | T146 |
| Test name | |
| Test status | |
| Simulation time | 4284587759 ps |
| CPU time | 441.41 seconds |
| Started | Aug 24 07:45:54 AM UTC 24 |
| Finished | Aug 24 07:53:21 AM UTC 24 |
| Peak memory | 624788 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=50_000_000 +en_jitter=1 +sw_build_device =sim_dv +sw_images=flash_ctrl_ops_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4197686234 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/ default.vdb -cm_log /dev/null -cm_name 0.chip_sw_flash_ctrl_ops_jitter_en.4197686234 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/0.chip_sw_flash_ctrl_ops_jitter_en/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_flash_ctrl_ops_jitter_en_reduced_freq.3979959234 |
| Short name | T371 |
| Test name | |
| Test status | |
| Simulation time | 5551015970 ps |
| CPU time | 423.81 seconds |
| Started | Aug 24 09:03:45 AM UTC 24 |
| Finished | Aug 24 09:10:54 AM UTC 24 |
| Peak memory | 624564 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=50_000_000 +en_jitter=1 +cal_sys_clk_70m hz=1 +sw_build_device=sim_dv +sw_images=flash_ctrl_ops_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3979959234 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_ TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_a sic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_flash_ctrl_ops_jitter_en_reduced_freq.3979959234 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/0.chip_sw_flash_ctrl_ops_jitter_en_reduced_freq/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_flash_ctrl_write_clear.4088586369 |
| Short name | T301 |
| Test name | |
| Test status | |
| Simulation time | 3032762902 ps |
| CPU time | 229.89 seconds |
| Started | Aug 24 09:03:20 AM UTC 24 |
| Finished | Aug 24 09:07:13 AM UTC 24 |
| Peak memory | 624960 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/default/simv +test_timeout_ns=8_000_000 +sw_build_device=sim_dv +sw_image s=flash_ctrl_write_clear_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4088586369 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 0.chip_sw_flash_ctrl_write_clear.4088586369 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/0.chip_sw_flash_ctrl_write_clear/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_flash_init_reduced_freq.2029410477 |
| Short name | T321 |
| Test name | |
| Test status | |
| Simulation time | 27433746353 ps |
| CPU time | 1366.86 seconds |
| Started | Aug 24 09:05:41 AM UTC 24 |
| Finished | Aug 24 09:28:44 AM UTC 24 |
| Peak memory | 634088 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=25_000_000 +cal_sys_clk_70mhz=1 +sw_buil d_device=sim_dv +sw_images=flash_init_test:0:test_in_rom:new_rules +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu e -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2029410477 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw _flash_init_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vc s/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_flash_init_reduced_freq.2029410477 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/0.chip_sw_flash_init_reduced_freq/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_flash_scrambling_smoketest.1781871820 |
| Short name | T304 |
| Test name | |
| Test status | |
| Simulation time | 2999726460 ps |
| CPU time | 137.06 seconds |
| Started | Aug 24 09:07:06 AM UTC 24 |
| Finished | Aug 24 09:09:25 AM UTC 24 |
| Peak memory | 624568 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/default/simv +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_ima ges=flash_scrambling_smoketest:1:new_rules,flash_scrambling_smoketest_otp_img_rma:4,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1781871820 -assert nopostproc +UVM_TESTNAME=chip_bas e_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/chi p_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_flash_scrambling_smoketest.1781871820 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/0.chip_sw_flash_scrambling_smoketest/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_gpio_smoketest.1154167872 |
| Short name | T45 |
| Test name | |
| Test status | |
| Simulation time | 3390260971 ps |
| CPU time | 169.09 seconds |
| Started | Aug 24 10:49:21 AM UTC 24 |
| Finished | Aug 24 10:52:13 AM UTC 24 |
| Peak memory | 626812 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=gpio_smoketest:1:new_rule s,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ random_seed=1154167872 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.ch ip_sw_gpio_smoketest.1154167872 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/0.chip_sw_gpio_smoketest/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_hmac_enc.1741952954 |
| Short name | T335 |
| Test name | |
| Test status | |
| Simulation time | 2660819144 ps |
| CPU time | 182.11 seconds |
| Started | Aug 24 08:25:24 AM UTC 24 |
| Finished | Aug 24 08:28:29 AM UTC 24 |
| Peak memory | 626932 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=hmac_enc_test:1:new_rules ,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_r andom_seed=1741952954 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_h mac_enc.1741952954 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/0.chip_sw_hmac_enc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_hmac_enc_idle.3266788206 |
| Short name | T656 |
| Test name | |
| Test status | |
| Simulation time | 3055310656 ps |
| CPU time | 203.63 seconds |
| Started | Aug 24 08:26:29 AM UTC 24 |
| Finished | Aug 24 08:29:55 AM UTC 24 |
| Peak memory | 624572 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=hmac_enc_idle_test:1:new_ rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl + ntb_random_seed=3266788206 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip _sw_hmac_enc_idle.3266788206 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/0.chip_sw_hmac_enc_idle/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_hmac_enc_jitter_en.1600882134 |
| Short name | T336 |
| Test name | |
| Test status | |
| Simulation time | 3533335356 ps |
| CPU time | 178.93 seconds |
| Started | Aug 24 08:25:45 AM UTC 24 |
| Finished | Aug 24 08:28:47 AM UTC 24 |
| Peak memory | 626616 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/default/simv +en_jitter=1 +sw_build_device=sim_dv +sw_images=hmac_enc_tes t:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/s im.tcl +ntb_random_seed=1600882134 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam e 0.chip_sw_hmac_enc_jitter_en.1600882134 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/0.chip_sw_hmac_enc_jitter_en/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_hmac_enc_jitter_en_reduced_freq.466173214 |
| Short name | T303 |
| Test name | |
| Test status | |
| Simulation time | 3316955036 ps |
| CPU time | 163.29 seconds |
| Started | Aug 24 09:05:55 AM UTC 24 |
| Finished | Aug 24 09:08:41 AM UTC 24 |
| Peak memory | 625124 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/default/simv +en_jitter=1 +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +s w_images=hmac_enc_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac es/repo/hw/dv/tools/sim.tcl +ntb_random_seed=466173214 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_l og /dev/null -cm_name 0.chip_sw_hmac_enc_jitter_en_reduced_freq.466173214 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/0.chip_sw_hmac_enc_jitter_en_reduced_freq/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_hmac_multistream.3504840377 |
| Short name | T307 |
| Test name | |
| Test status | |
| Simulation time | 7591009584 ps |
| CPU time | 1191.24 seconds |
| Started | Aug 24 08:27:39 AM UTC 24 |
| Finished | Aug 24 08:47:43 AM UTC 24 |
| Peak memory | 624840 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=hmac_multistream_functest :1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/si m.tcl +ntb_random_seed=3504840377 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_hmac_multistream.3504840377 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/0.chip_sw_hmac_multistream/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_hmac_oneshot.2221089417 |
| Short name | T877 |
| Test name | |
| Test status | |
| Simulation time | 2847908184 ps |
| CPU time | 259.87 seconds |
| Started | Aug 24 08:26:29 AM UTC 24 |
| Finished | Aug 24 08:30:53 AM UTC 24 |
| Peak memory | 626616 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=hmac_functest:1:new_rules ,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_r andom_seed=2221089417 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_h mac_oneshot.2221089417 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/0.chip_sw_hmac_oneshot/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_hmac_smoketest.2516175016 |
| Short name | T919 |
| Test name | |
| Test status | |
| Simulation time | 3435153464 ps |
| CPU time | 280.85 seconds |
| Started | Aug 24 10:49:22 AM UTC 24 |
| Finished | Aug 24 10:54:06 AM UTC 24 |
| Peak memory | 624828 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=hmac_smoketest:1:new_rule s,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ random_seed=2516175016 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_ hmac_smoketest.2516175016 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/0.chip_sw_hmac_smoketest/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_i2c_device_tx_rx.131343918 |
| Short name | T35 |
| Test name | |
| Test status | |
| Simulation time | 4227612808 ps |
| CPU time | 356.26 seconds |
| Started | Aug 24 07:43:19 AM UTC 24 |
| Finished | Aug 24 07:49:20 AM UTC 24 |
| Peak memory | 624772 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=i2c_device_tx_rx_test:1:n ew_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc l +ntb_random_seed=131343918 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_i2c_device_tx_rx_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null - cm_name 0.chip_sw_i2c_device_tx_rx.131343918 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/0.chip_sw_i2c_device_tx_rx/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_i2c_host_tx_rx.1457885156 |
| Short name | T73 |
| Test name | |
| Test status | |
| Simulation time | 5775162338 ps |
| CPU time | 607.68 seconds |
| Started | Aug 24 07:42:20 AM UTC 24 |
| Finished | Aug 24 07:52:35 AM UTC 24 |
| Peak memory | 625016 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/default/simv +i2c_idx=0 +sw_build_device=sim_dv +sw_images=i2c_host_tx_rx _test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/too ls/sim.tcl +ntb_random_seed=1457885156 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_i2c_host_tx_rx_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /de v/null -cm_name 0.chip_sw_i2c_host_tx_rx.1457885156 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/0.chip_sw_i2c_host_tx_rx/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_i2c_host_tx_rx_idx1.451662472 |
| Short name | T75 |
| Test name | |
| Test status | |
| Simulation time | 4441742472 ps |
| CPU time | 504.33 seconds |
| Started | Aug 24 07:43:12 AM UTC 24 |
| Finished | Aug 24 07:51:43 AM UTC 24 |
| Peak memory | 624756 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/default/simv +i2c_idx=1 +sw_build_device=sim_dv +sw_images=i2c_host_tx_rx _test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/too ls/sim.tcl +ntb_random_seed=451662472 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_i2c_host_tx_rx_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev /null -cm_name 0.chip_sw_i2c_host_tx_rx_idx1.451662472 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/0.chip_sw_i2c_host_tx_rx_idx1/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_i2c_host_tx_rx_idx2.1328972431 |
| Short name | T76 |
| Test name | |
| Test status | |
| Simulation time | 4961454120 ps |
| CPU time | 518 seconds |
| Started | Aug 24 07:43:18 AM UTC 24 |
| Finished | Aug 24 07:52:03 AM UTC 24 |
| Peak memory | 625084 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/default/simv +i2c_idx=2 +sw_build_device=sim_dv +sw_images=i2c_host_tx_rx _test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/too ls/sim.tcl +ntb_random_seed=1328972431 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_i2c_host_tx_rx_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /de v/null -cm_name 0.chip_sw_i2c_host_tx_rx_idx2.1328972431 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/0.chip_sw_i2c_host_tx_rx_idx2/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_inject_scramble_seed.2504414109 |
| Short name | T244 |
| Test name | |
| Test status | |
| Simulation time | 66864617916 ps |
| CPU time | 11563.5 seconds |
| Started | Aug 24 07:40:39 AM UTC 24 |
| Finished | Aug 24 10:55:25 AM UTC 24 |
| Peak memory | 644444 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/default/simv +lc_at_prod=1 +flash_program_latency=5 +sw_test_timeout_ns=1 50_000_000 +sw_build_device=sim_dv +sw_images=inject_scramble_seed:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2504414109 -assert nopostproc +UVM_TESTNAME=chip_base_tes t +UVM_TEST_SEQ=chip_sw_inject_scramble_seed_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_08_22/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_inject_scramble_seed.2504414109 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/0.chip_sw_inject_scramble_seed/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_keymgr_key_derivation.2495261468 |
| Short name | T313 |
| Test name | |
| Test status | |
| Simulation time | 9621861838 ps |
| CPU time | 1507.61 seconds |
| Started | Aug 24 08:28:10 AM UTC 24 |
| Finished | Aug 24 08:53:35 AM UTC 24 |
| Peak memory | 632852 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=20_000_000 +sw_build_device=sim_dv +sw_i mages=keymgr_key_derivation_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2495261468 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_keymgr_key _derivation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vc s/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_keymgr_key_derivation.2495261468 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/0.chip_sw_keymgr_key_derivation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_keymgr_key_derivation_jitter_en.4128577527 |
| Short name | T149 |
| Test name | |
| Test status | |
| Simulation time | 6329258491 ps |
| CPU time | 701.88 seconds |
| Started | Aug 24 08:29:11 AM UTC 24 |
| Finished | Aug 24 08:41:01 AM UTC 24 |
| Peak memory | 632856 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=20_000_000 +en_jitter=1 +sw_build_device =sim_dv +sw_images=keymgr_key_derivation_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu eue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4128577527 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_ sw_keymgr_key_derivation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgre y_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_keymgr_key_derivation_jitter_en.4128577527 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/0.chip_sw_keymgr_key_derivation_jitter_en/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_keymgr_key_derivation_jitter_en_reduced_freq.1491570611 |
| Short name | T887 |
| Test name | |
| Test status | |
| Simulation time | 7326852134 ps |
| CPU time | 664.58 seconds |
| Started | Aug 24 09:05:40 AM UTC 24 |
| Finished | Aug 24 09:16:52 AM UTC 24 |
| Peak memory | 632852 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=20_000_000 +en_jitter=1 +cal_sys_clk_70m hz=1 +sw_build_device=sim_dv +sw_images=keymgr_key_derivation_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1491570611 -assert nopostproc +UVM_TESTNAME=chip_base_tes t +UVM_TEST_SEQ=chip_sw_keymgr_key_derivation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_22/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_keymgr_key_derivation_jitter_en_reduced_freq.1491570611 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/0.chip_sw_keymgr_key_derivation_jitter_en_reduced_freq/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_keymgr_key_derivation_prod.319792223 |
| Short name | T314 |
| Test name | |
| Test status | |
| Simulation time | 9670291040 ps |
| CPU time | 1437.69 seconds |
| Started | Aug 24 08:28:53 AM UTC 24 |
| Finished | Aug 24 08:53:06 AM UTC 24 |
| Peak memory | 632856 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/default/simv +lc_at_prod=1 +sw_test_timeout_ns=20_000_000 +sw_build_devic e=sim_dv +sw_images=keymgr_key_derivation_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=319792223 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_ sw_keymgr_key_derivation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgre y_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_keymgr_key_derivation_prod.319792223 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/0.chip_sw_keymgr_key_derivation_prod/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_keymgr_sideload_kmac.2403911823 |
| Short name | T315 |
| Test name | |
| Test status | |
| Simulation time | 13505955900 ps |
| CPU time | 2047.94 seconds |
| Started | Aug 24 08:30:07 AM UTC 24 |
| Finished | Aug 24 09:04:37 AM UTC 24 |
| Peak memory | 629960 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=20_000_000 +sw_build_device=sim_dv +sw_i mages=keymgr_sideload_kmac_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2403911823 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_keymgr_side load_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_keymgr_sideload_kmac.2403911823 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/0.chip_sw_keymgr_sideload_kmac/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_kmac_app_rom.1164140536 |
| Short name | T429 |
| Test name | |
| Test status | |
| Simulation time | 2757896946 ps |
| CPU time | 195.32 seconds |
| Started | Aug 24 08:33:56 AM UTC 24 |
| Finished | Aug 24 08:37:14 AM UTC 24 |
| Peak memory | 624816 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=kmac_app_rom_test:1:new_r ules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +n tb_random_seed=1164140536 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a ssert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_ sw_kmac_app_rom.1164140536 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/0.chip_sw_kmac_app_rom/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_kmac_entropy.4098680532 |
| Short name | T447 |
| Test name | |
| Test status | |
| Simulation time | 2992252650 ps |
| CPU time | 204.21 seconds |
| Started | Aug 24 07:47:07 AM UTC 24 |
| Finished | Aug 24 07:50:34 AM UTC 24 |
| Peak memory | 624896 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=kmac_entropy_test:1:new_r ules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +n tb_random_seed=4098680532 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a ssert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_ sw_kmac_entropy.4098680532 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/0.chip_sw_kmac_entropy/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_kmac_idle.2707569670 |
| Short name | T879 |
| Test name | |
| Test status | |
| Simulation time | 3299432854 ps |
| CPU time | 184.21 seconds |
| Started | Aug 24 08:34:49 AM UTC 24 |
| Finished | Aug 24 08:37:56 AM UTC 24 |
| Peak memory | 624564 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=kmac_idle_test:1:new_rule s,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ random_seed=2707569670 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_ kmac_idle.2707569670 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/0.chip_sw_kmac_idle/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_kmac_mode_cshake.1553713437 |
| Short name | T448 |
| Test name | |
| Test status | |
| Simulation time | 2552863432 ps |
| CPU time | 206.15 seconds |
| Started | Aug 24 08:30:57 AM UTC 24 |
| Finished | Aug 24 08:34:26 AM UTC 24 |
| Peak memory | 624564 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=kmac_mode_cshake_test:1:n ew_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc l +ntb_random_seed=1553713437 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.c hip_sw_kmac_mode_cshake.1553713437 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/0.chip_sw_kmac_mode_cshake/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_kmac_mode_kmac.1258718585 |
| Short name | T449 |
| Test name | |
| Test status | |
| Simulation time | 3365284164 ps |
| CPU time | 226.87 seconds |
| Started | Aug 24 08:31:16 AM UTC 24 |
| Finished | Aug 24 08:35:07 AM UTC 24 |
| Peak memory | 624552 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=kmac_mode_kmac_test:1:new _rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1258718585 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.chi p_sw_kmac_mode_kmac.1258718585 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/0.chip_sw_kmac_mode_kmac/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_kmac_mode_kmac_jitter_en.2949569151 |
| Short name | T878 |
| Test name | |
| Test status | |
| Simulation time | 3157197099 ps |
| CPU time | 246.29 seconds |
| Started | Aug 24 08:33:03 AM UTC 24 |
| Finished | Aug 24 08:37:13 AM UTC 24 |
| Peak memory | 624884 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/default/simv +en_jitter=1 +sw_build_device=sim_dv +sw_images=kmac_mode_km ac_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/t ools/sim.tcl +ntb_random_seed=2949569151 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null - cm_name 0.chip_sw_kmac_mode_kmac_jitter_en.2949569151 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/0.chip_sw_kmac_mode_kmac_jitter_en/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_kmac_mode_kmac_jitter_en_reduced_freq.2899018766 |
| Short name | T421 |
| Test name | |
| Test status | |
| Simulation time | 3532008818 ps |
| CPU time | 222.97 seconds |
| Started | Aug 24 09:05:40 AM UTC 24 |
| Finished | Aug 24 09:09:26 AM UTC 24 |
| Peak memory | 625068 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/default/simv +en_jitter=1 +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +s w_images=kmac_mode_kmac_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo rkspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2899018766 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default.vd b -cm_log /dev/null -cm_name 0.chip_sw_kmac_mode_kmac_jitter_en_reduced_freq.2899018766 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/0.chip_sw_kmac_mode_kmac_jitter_en_reduced_freq/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_kmac_smoketest.2755515050 |
| Short name | T917 |
| Test name | |
| Test status | |
| Simulation time | 3507072058 ps |
| CPU time | 206.95 seconds |
| Started | Aug 24 10:50:05 AM UTC 24 |
| Finished | Aug 24 10:53:35 AM UTC 24 |
| Peak memory | 624564 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=kmac_smoketest:1:new_rule s,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ random_seed=2755515050 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_ kmac_smoketest.2755515050 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/0.chip_sw_kmac_smoketest/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_lc_ctrl_otp_hw_cfg0.51480925 |
| Short name | T191 |
| Test name | |
| Test status | |
| Simulation time | 2603640064 ps |
| CPU time | 168.39 seconds |
| Started | Aug 24 07:47:09 AM UTC 24 |
| Finished | Aug 24 07:50:00 AM UTC 24 |
| Peak memory | 624564 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=lc_ctrl_otp_hw_cfg0_test: 1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim .tcl +ntb_random_seed=51480925 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0. chip_sw_lc_ctrl_otp_hw_cfg0.51480925 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/0.chip_sw_lc_ctrl_otp_hw_cfg0/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_lc_ctrl_rand_to_scrap.2910707165 |
| Short name | T151 |
| Test name | |
| Test status | |
| Simulation time | 3311907625 ps |
| CPU time | 195.99 seconds |
| Started | Aug 24 07:53:46 AM UTC 24 |
| Finished | Aug 24 07:57:05 AM UTC 24 |
| Peak memory | 637180 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv + sw_images=lc_ctrl_scrap_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo rkspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2910707165 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_ctrl_scrap_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 0.chip_sw_lc_ctrl_rand_to_scrap.2910707165 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/0.chip_sw_lc_ctrl_rand_to_scrap/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_lc_ctrl_raw_to_scrap.945508511 |
| Short name | T37 |
| Test name | |
| Test status | |
| Simulation time | 3564153564 ps |
| CPU time | 108.04 seconds |
| Started | Aug 24 07:52:27 AM UTC 24 |
| Finished | Aug 24 07:54:17 AM UTC 24 |
| Peak memory | 636396 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/default/simv +bypass_alert_ready_to_end_check=1 +src_dec_state=DecLcStRaw +sw_build_device=sim_dv +sw_images=lc_ctrl_scrap_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=945508511 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_S EQ=chip_sw_lc_ctrl_scrap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgre y_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_lc_ctrl_raw_to_scrap.945508511 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/0.chip_sw_lc_ctrl_raw_to_scrap/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_lc_ctrl_test_locked0_to_scrap.4044744586 |
| Short name | T43 |
| Test name | |
| Test status | |
| Simulation time | 3387864163 ps |
| CPU time | 103.9 seconds |
| Started | Aug 24 07:52:59 AM UTC 24 |
| Finished | Aug 24 07:54:45 AM UTC 24 |
| Peak memory | 636404 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/default/simv +bypass_alert_ready_to_end_check=1 +src_dec_state=DecLcStTes tLocked0 +sw_build_device=sim_dv +sw_images=lc_ctrl_scrap_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4044744586 -assert nopostproc +UVM_TESTNAME=chip_base_test +U VM_TEST_SEQ=chip_sw_lc_ctrl_scrap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/chi p_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_lc_ctrl_test_locked0_to_scrap.4044744586 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/0.chip_sw_lc_ctrl_test_locked0_to_scrap/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_lc_ctrl_volatile_raw_unlock.2491835976 |
| Short name | T204 |
| Test name | |
| Test status | |
| Simulation time | 2643344477 ps |
| CPU time | 101.4 seconds |
| Started | Aug 24 07:53:49 AM UTC 24 |
| Finished | Aug 24 07:55:32 AM UTC 24 |
| Peak memory | 634420 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/default/simv +use_otp_image=OtpTypeLcStRaw +exp_volatile_raw_unlock_en=0 +sw_build_device=sim_dv +sw_images=lc_ctrl_volatile_raw_unlock_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2491835976 -assert nopostproc +UVM_TESTNAME=chip_base_te st +UVM_TEST_SEQ=chip_sw_lc_volatile_raw_unlock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_lc_ctrl_volatile_raw_unlock.2491835976 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/0.chip_sw_lc_ctrl_volatile_raw_unlock/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz.1826849894 |
| Short name | T90 |
| Test name | |
| Test status | |
| Simulation time | 2156236246 ps |
| CPU time | 83.71 seconds |
| Started | Aug 24 07:54:05 AM UTC 24 |
| Finished | Aug 24 07:55:31 AM UTC 24 |
| Peak memory | 634284 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/default/simv +use_otp_image=OtpTypeLcStRaw +chip_clock_source=ChipClockSo urceExternal48Mhz +exp_volatile_raw_unlock_en=0 +sw_build_device=sim_dv +sw_images=lc_ctrl_volatile_raw_unlock_test:1:new_rules,test_rom:0 +cdc_in strumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=18268498 94 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_volatile_raw_unlock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_lc _ctrl_volatile_raw_unlock_ext_clk_48mhz.1826849894 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/0.chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_lc_walkthrough_prod.2116414638 |
| Short name | T324 |
| Test name | |
| Test status | |
| Simulation time | 48490652878 ps |
| CPU time | 4020.8 seconds |
| Started | Aug 24 07:53:46 AM UTC 24 |
| Finished | Aug 24 09:01:29 AM UTC 24 |
| Peak memory | 644516 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/default/simv +flash_program_latency=5 +use_otp_image=OtpTypeLcStRaw +dest _dec_state=DecLcStProd +sw_test_timeout_ns=200_000_000 +sw_build_device=sim_dv +sw_images=lc_walkthrough_test:1:new_rules,test_rom:0 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2116414638 -as sert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_walkthrough_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work spaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_lc_walkthrough_prod.2116414638 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/0.chip_sw_lc_walkthrough_prod/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_lc_walkthrough_rma.3981694935 |
| Short name | T323 |
| Test name | |
| Test status | |
| Simulation time | 45186815560 ps |
| CPU time | 4114.48 seconds |
| Started | Aug 24 07:54:41 AM UTC 24 |
| Finished | Aug 24 09:03:59 AM UTC 24 |
| Peak memory | 644260 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/default/simv +use_otp_image=OtpTypeLcStRaw +dest_dec_state=DecLcStRma +fl ash_program_latency=5 +sw_test_timeout_ns=200_000_000 +sw_build_device=sim_dv +sw_images=lc_walkthrough_test:1:new_rules,test_rom:0 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3981694935 -ass ert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_walkthrough_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works paces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_lc_walkthrough_rma.3981694935 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/0.chip_sw_lc_walkthrough_rma/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_lc_walkthrough_testunlocks.2879633058 |
| Short name | T207 |
| Test name | |
| Test status | |
| Simulation time | 31701741560 ps |
| CPU time | 1360.69 seconds |
| Started | Aug 24 07:55:20 AM UTC 24 |
| Finished | Aug 24 08:18:16 AM UTC 24 |
| Peak memory | 641092 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/default/simv +use_otp_image=OtpTypeLcStRaw +dest_dec_state=DecLcStTestUnl ock7 +sw_build_device=sim_dv +sw_images=lc_walkthrough_testunlocks_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2879633058 -assert nopostproc +UVM_TESTNAME=chip_bas e_test +UVM_TEST_SEQ=chip_sw_lc_walkthrough_testunlocks_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_lc_walkthrough_testunlocks.2879633058 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/0.chip_sw_lc_walkthrough_testunlocks/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_otbn_ecdsa_op_irq.2234564335 |
| Short name | T185 |
| Test name | |
| Test status | |
| Simulation time | 17190946840 ps |
| CPU time | 2881.29 seconds |
| Started | Aug 24 08:10:28 AM UTC 24 |
| Finished | Aug 24 08:59:00 AM UTC 24 |
| Peak memory | 630020 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=28_000_000 +rng_srate_value=30 +sw_build _device=sim_dv +sw_images=otbn_ecdsa_op_irq_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2234564335 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=ch ip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_otbn_ecdsa_op_irq.2234564335 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/0.chip_sw_otbn_ecdsa_op_irq/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_otbn_ecdsa_op_irq_jitter_en.1489536561 |
| Short name | T145 |
| Test name | |
| Test status | |
| Simulation time | 18430543604 ps |
| CPU time | 3210.44 seconds |
| Started | Aug 24 08:10:50 AM UTC 24 |
| Finished | Aug 24 09:04:56 AM UTC 24 |
| Peak memory | 629796 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=33_000_000 +rng_srate_value=30 +en_jitte r=1 +sw_build_device=sim_dv +sw_images=otbn_ecdsa_op_irq_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1489536561 -assert nopostproc +UVM_TESTNAME=chip_base_test +UV M_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey _asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_otbn_ecdsa_op_irq_jitter_en.1489536561 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/0.chip_sw_otbn_ecdsa_op_irq_jitter_en/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_otbn_randomness.442140791 |
| Short name | T159 |
| Test name | |
| Test status | |
| Simulation time | 5258440134 ps |
| CPU time | 595.23 seconds |
| Started | Aug 24 08:09:27 AM UTC 24 |
| Finished | Aug 24 08:19:30 AM UTC 24 |
| Peak memory | 627012 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=18_000_000 +rng_srate_value=30 +sw_build _device=sim_dv +sw_images=otbn_randomness_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=442140791 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_ sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_otbn_randomness.442140791 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/0.chip_sw_otbn_randomness/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_otbn_smoketest.1777955615 |
| Short name | T934 |
| Test name | |
| Test status | |
| Simulation time | 6324100484 ps |
| CPU time | 743.22 seconds |
| Started | Aug 24 10:50:29 AM UTC 24 |
| Finished | Aug 24 11:03:01 AM UTC 24 |
| Peak memory | 624764 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=otbn_smoketest:1:new_rule s,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ random_seed=1777955615 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_ otbn_smoketest.1777955615 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/0.chip_sw_otbn_smoketest/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_otp_ctrl_dai_lock.1444188186 |
| Short name | T886 |
| Test name | |
| Test status | |
| Simulation time | 27190503218 ps |
| CPU time | 4374.94 seconds |
| Started | Aug 24 07:51:06 AM UTC 24 |
| Finished | Aug 24 09:04:46 AM UTC 24 |
| Peak memory | 630044 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=30_000_000 +sw_build_device=sim_dv +sw_i mages=otp_ctrl_mem_access_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1444188186 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default. vdb -cm_log /dev/null -cm_name 0.chip_sw_otp_ctrl_dai_lock.1444188186 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/0.chip_sw_otp_ctrl_dai_lock/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_otp_ctrl_ecc_error_vendor_test.3025678749 |
| Short name | T192 |
| Test name | |
| Test status | |
| Simulation time | 2514347954 ps |
| CPU time | 212.59 seconds |
| Started | Aug 24 07:51:05 AM UTC 24 |
| Finished | Aug 24 07:54:42 AM UTC 24 |
| Peak memory | 624812 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=otp_ctrl_vendor_test_ecc_ error_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/d v/tools/sim.tcl +ntb_random_seed=3025678749 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_otp_ctrl_vendor_test_ecc_error_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/de fault.vdb -cm_log /dev/null -cm_name 0.chip_sw_otp_ctrl_ecc_error_vendor_test.3025678749 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/0.chip_sw_otp_ctrl_ecc_error_vendor_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_otp_ctrl_lc_signals_dev.1649291971 |
| Short name | T208 |
| Test name | |
| Test status | |
| Simulation time | 6940601350 ps |
| CPU time | 817.22 seconds |
| Started | Aug 24 07:47:54 AM UTC 24 |
| Finished | Aug 24 08:01:41 AM UTC 24 |
| Peak memory | 626628 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/default/simv +use_otp_image=OtpTypeLcStDev +otp_clear_secret2=1 +sw_build _device=sim_dv +sw_images=otp_ctrl_lc_signals_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1649291971 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ= chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_otp_ctrl_lc_signals_dev.1649291971 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/0.chip_sw_otp_ctrl_lc_signals_dev/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_otp_ctrl_lc_signals_prod.1924401316 |
| Short name | T279 |
| Test name | |
| Test status | |
| Simulation time | 8708277548 ps |
| CPU time | 908.96 seconds |
| Started | Aug 24 07:48:18 AM UTC 24 |
| Finished | Aug 24 08:03:38 AM UTC 24 |
| Peak memory | 626876 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/default/simv +use_otp_image=OtpTypeLcStProd +otp_clear_secret2=1 +sw_buil d_device=sim_dv +sw_images=otp_ctrl_lc_signals_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1924401316 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ =chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_otp_ctrl_lc_signals_prod.1924401316 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/0.chip_sw_otp_ctrl_lc_signals_prod/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_otp_ctrl_lc_signals_rma.1123141966 |
| Short name | T214 |
| Test name | |
| Test status | |
| Simulation time | 7661523526 ps |
| CPU time | 808.01 seconds |
| Started | Aug 24 07:49:45 AM UTC 24 |
| Finished | Aug 24 08:03:22 AM UTC 24 |
| Peak memory | 626624 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/default/simv +use_otp_image=OtpTypeLcStRma +otp_clear_secret2=1 +sw_build _device=sim_dv +sw_images=otp_ctrl_lc_signals_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1123141966 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ= chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_otp_ctrl_lc_signals_rma.1123141966 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/0.chip_sw_otp_ctrl_lc_signals_rma/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_otp_ctrl_lc_signals_test_unlocked0.2212771056 |
| Short name | T206 |
| Test name | |
| Test status | |
| Simulation time | 3989621024 ps |
| CPU time | 441.18 seconds |
| Started | Aug 24 07:47:19 AM UTC 24 |
| Finished | Aug 24 07:54:46 AM UTC 24 |
| Peak memory | 626616 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/default/simv +use_otp_image=OtpTypeLcStTestUnlocked0 +otp_clear_secret2=1 +sw_build_device=sim_dv +sw_images=otp_ctrl_lc_signals_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY =UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2212771056 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM _TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_ asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_otp_ctrl_lc_signals_test_unlocked0.2212771056 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/0.chip_sw_otp_ctrl_lc_signals_test_unlocked0/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_otp_ctrl_smoketest.3153208548 |
| Short name | T918 |
| Test name | |
| Test status | |
| Simulation time | 2582033620 ps |
| CPU time | 211.93 seconds |
| Started | Aug 24 10:50:29 AM UTC 24 |
| Finished | Aug 24 10:54:04 AM UTC 24 |
| Peak memory | 624564 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=otp_ctrl_smoketest:1:new_ rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl + ntb_random_seed=3153208548 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip _sw_otp_ctrl_smoketest.3153208548 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/0.chip_sw_otp_ctrl_smoketest/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_pattgen_ios.3434217176 |
| Short name | T6 |
| Test name | |
| Test status | |
| Simulation time | 2897402854 ps |
| CPU time | 185.65 seconds |
| Started | Aug 24 07:39:16 AM UTC 24 |
| Finished | Aug 24 07:42:24 AM UTC 24 |
| Peak memory | 624632 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=5_000_000 +sw_build_device=sim_dv +sw_im ages=pattgen_ios_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace s/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3434217176 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_patt_ios_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default.vdb - cm_log /dev/null -cm_name 0.chip_sw_pattgen_ios.3434217176 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/0.chip_sw_pattgen_ios/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_power_idle_load.584703760 |
| Short name | T136 |
| Test name | |
| Test status | |
| Simulation time | 4035676622 ps |
| CPU time | 429.34 seconds |
| Started | Aug 24 09:05:54 AM UTC 24 |
| Finished | Aug 24 09:13:09 AM UTC 24 |
| Peak memory | 624640 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=chip_power_idle_load:1:ne w_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=584703760 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_power_idle_load_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm _name 0.chip_sw_power_idle_load.584703760 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/0.chip_sw_power_idle_load/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_power_sleep_load.779941375 |
| Short name | T86 |
| Test name | |
| Test status | |
| Simulation time | 5159569708 ps |
| CPU time | 335.96 seconds |
| Started | Aug 24 09:05:55 AM UTC 24 |
| Finished | Aug 24 09:11:36 AM UTC 24 |
| Peak memory | 624876 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=chip_power_sleep_load:1:n ew_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc l +ntb_random_seed=779941375 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_power_sleep_load_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null - cm_name 0.chip_sw_power_sleep_load.779941375 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/0.chip_sw_power_sleep_load/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_pwrmgr_all_reset_reqs.35952953 |
| Short name | T343 |
| Test name | |
| Test status | |
| Simulation time | 10989334072 ps |
| CPU time | 932.21 seconds |
| Started | Aug 24 07:58:07 AM UTC 24 |
| Finished | Aug 24 08:13:50 AM UTC 24 |
| Peak memory | 627016 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=50_000_000 +sw_build_device=sim_dv +sw_i mages=pwrmgr_all_reset_reqs_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=35952953 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_deep_sleep_a ll_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_pwrmgr_all_reset_reqs.35952953 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/0.chip_sw_pwrmgr_all_reset_reqs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_pwrmgr_b2b_sleep_reset_req.1001852084 |
| Short name | T439 |
| Test name | |
| Test status | |
| Simulation time | 30134514587 ps |
| CPU time | 1258.56 seconds |
| Started | Aug 24 08:41:13 AM UTC 24 |
| Finished | Aug 24 09:02:25 AM UTC 24 |
| Peak memory | 626940 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=35_000_000 +sw_build_device=sim_dv +sw_i mages=pwrmgr_b2b_sleep_reset_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1001852084 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_repeat_re set_wkup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_pwrmgr_b2b_sleep_reset_req.1001852084 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/0.chip_sw_pwrmgr_b2b_sleep_reset_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_pwrmgr_deep_sleep_por_reset.4000463720 |
| Short name | T83 |
| Test name | |
| Test status | |
| Simulation time | 8354465436 ps |
| CPU time | 545.38 seconds |
| Started | Aug 24 07:59:14 AM UTC 24 |
| Finished | Aug 24 08:08:26 AM UTC 24 |
| Peak memory | 626676 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=pwrmgr_deep_sleep_por_res et_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/t ools/sim.tcl +ntb_random_seed=4000463720 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sleep_por_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_pwrmgr_deep_sleep_por_reset.4000463720 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/0.chip_sw_pwrmgr_deep_sleep_por_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_pwrmgr_main_power_glitch_reset.4081652946 |
| Short name | T278 |
| Test name | |
| Test status | |
| Simulation time | 4204241400 ps |
| CPU time | 320.96 seconds |
| Started | Aug 24 07:56:38 AM UTC 24 |
| Finished | Aug 24 08:02:03 AM UTC 24 |
| Peak memory | 632784 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv + sw_images=pwrmgr_main_power_glitch_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4081652946 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_mai n_power_glitch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_pwrmgr_main_power_glitch_reset.4081652946 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/0.chip_sw_pwrmgr_main_power_glitch_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_pwrmgr_normal_sleep_all_reset_reqs.208601776 |
| Short name | T874 |
| Test name | |
| Test status | |
| Simulation time | 11607862629 ps |
| CPU time | 1131.64 seconds |
| Started | Aug 24 07:58:44 AM UTC 24 |
| Finished | Aug 24 08:17:48 AM UTC 24 |
| Peak memory | 626756 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=pwrmgr_normal_sleep_all_r eset_reqs_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/ hw/dv/tools/sim.tcl +ntb_random_seed=208601776 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_deep_sleep_all_reset_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 0.chip_sw_pwrmgr_normal_sleep_all_reset_reqs.208601776 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/0.chip_sw_pwrmgr_normal_sleep_all_reset_reqs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_pwrmgr_normal_sleep_all_wake_ups.1459563544 |
| Short name | T68 |
| Test name | |
| Test status | |
| Simulation time | 7863851458 ps |
| CPU time | 379.88 seconds |
| Started | Aug 24 08:55:50 AM UTC 24 |
| Finished | Aug 24 09:02:15 AM UTC 24 |
| Peak memory | 627152 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=pwrmgr_normal_sleep_all_w ake_ups:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/t ools/sim.tcl +ntb_random_seed=1459563544 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_pwrmgr_deep_sleep_all_wake_ups_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 0.chip_sw_pwrmgr_normal_sleep_all_wake_ups.1459563544 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/0.chip_sw_pwrmgr_normal_sleep_all_wake_ups/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_pwrmgr_normal_sleep_por_reset.1208688103 |
| Short name | T84 |
| Test name | |
| Test status | |
| Simulation time | 7871606212 ps |
| CPU time | 546.71 seconds |
| Started | Aug 24 07:59:14 AM UTC 24 |
| Finished | Aug 24 08:08:28 AM UTC 24 |
| Peak memory | 626936 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=pwrmgr_normal_sleep_por_r eset_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv /tools/sim.tcl +ntb_random_seed=1208688103 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sleep_por_reset_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_lo g /dev/null -cm_name 0.chip_sw_pwrmgr_normal_sleep_por_reset.1208688103 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/0.chip_sw_pwrmgr_normal_sleep_por_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_pwrmgr_random_sleep_all_reset_reqs.3211682277 |
| Short name | T403 |
| Test name | |
| Test status | |
| Simulation time | 23345678643 ps |
| CPU time | 1475.23 seconds |
| Started | Aug 24 07:58:40 AM UTC 24 |
| Finished | Aug 24 08:23:32 AM UTC 24 |
| Peak memory | 627020 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=50_000_000 +sw_build_device=sim_dv +sw_i mages=pwrmgr_random_sleep_all_reset_reqs_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu eue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3211682277 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_ sw_deep_sleep_all_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey _asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_pwrmgr_random_sleep_all_reset_reqs.3211682277 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/0.chip_sw_pwrmgr_random_sleep_all_reset_reqs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_pwrmgr_random_sleep_all_wake_ups.4241512303 |
| Short name | T69 |
| Test name | |
| Test status | |
| Simulation time | 23146830416 ps |
| CPU time | 897.21 seconds |
| Started | Aug 24 08:56:30 AM UTC 24 |
| Finished | Aug 24 09:11:37 AM UTC 24 |
| Peak memory | 627316 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=18_000_000 +do_random=1 +sw_build_device =sim_dv +sw_images=pwrmgr_random_sleep_all_wake_ups:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4241512303 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ =chip_sw_pwrmgr_deep_sleep_all_wake_ups_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_ 22/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_pwrmgr_random_sleep_all_wake_ups.4241512303 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/0.chip_sw_pwrmgr_random_sleep_all_wake_ups/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_pwrmgr_sleep_disabled.1351161959 |
| Short name | T280 |
| Test name | |
| Test status | |
| Simulation time | 3522804988 ps |
| CPU time | 197.93 seconds |
| Started | Aug 24 08:02:05 AM UTC 24 |
| Finished | Aug 24 08:05:25 AM UTC 24 |
| Peak memory | 624824 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=pwrmgr_sleep_disabled_tes t:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/s im.tcl +ntb_random_seed=1351161959 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam e 0.chip_sw_pwrmgr_sleep_disabled.1351161959 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/0.chip_sw_pwrmgr_sleep_disabled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_pwrmgr_sleep_wake_5_bug.1237771397 |
| Short name | T166 |
| Test name | |
| Test status | |
| Simulation time | 6630594740 ps |
| CPU time | 373.11 seconds |
| Started | Aug 24 08:56:32 AM UTC 24 |
| Finished | Aug 24 09:02:50 AM UTC 24 |
| Peak memory | 626684 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=18_000_000 +do_random=1 +sw_build_device =sim_dv +sw_images=pwrmgr_sleep_wake_5_bug_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1237771397 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chi p_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_pwrmgr_sleep_wake_5_bug.1237771397 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/0.chip_sw_pwrmgr_sleep_wake_5_bug/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_pwrmgr_smoketest.4157832351 |
| Short name | T927 |
| Test name | |
| Test status | |
| Simulation time | 5597150890 ps |
| CPU time | 368.11 seconds |
| Started | Aug 24 10:50:57 AM UTC 24 |
| Finished | Aug 24 10:57:10 AM UTC 24 |
| Peak memory | 627144 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=10000000 +sw_build_device=sim_dv +sw_ima ges=pwrmgr_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces /repo/hw/dv/tools/sim.tcl +ntb_random_seed=4157832351 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_lo g /dev/null -cm_name 0.chip_sw_pwrmgr_smoketest.4157832351 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/0.chip_sw_pwrmgr_smoketest/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_pwrmgr_sysrst_ctrl_reset.2640741991 |
| Short name | T137 |
| Test name | |
| Test status | |
| Simulation time | 7552740088 ps |
| CPU time | 670.34 seconds |
| Started | Aug 24 07:57:29 AM UTC 24 |
| Finished | Aug 24 08:08:47 AM UTC 24 |
| Peak memory | 626624 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=pwrmgr_sysrst_ctrl_test:1 :new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim. tcl +ntb_random_seed=2640741991 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sysrst_ctrl_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm _name 0.chip_sw_pwrmgr_sysrst_ctrl_reset.2640741991 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/0.chip_sw_pwrmgr_sysrst_ctrl_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_pwrmgr_usb_clk_disabled_when_active.2055606560 |
| Short name | T261 |
| Test name | |
| Test status | |
| Simulation time | 4814227200 ps |
| CPU time | 348.13 seconds |
| Started | Aug 24 08:02:27 AM UTC 24 |
| Finished | Aug 24 08:08:20 AM UTC 24 |
| Peak memory | 627104 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=pwrmgr_usb_clk_disabled_w hen_active_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo /hw/dv/tools/sim.tcl +ntb_random_seed=2055606560 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /de v/null -cm_name 0.chip_sw_pwrmgr_usb_clk_disabled_when_active.2055606560 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/0.chip_sw_pwrmgr_usb_clk_disabled_when_active/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_pwrmgr_usbdev_smoketest.3729549465 |
| Short name | T427 |
| Test name | |
| Test status | |
| Simulation time | 5039253264 ps |
| CPU time | 334.33 seconds |
| Started | Aug 24 10:50:58 AM UTC 24 |
| Finished | Aug 24 10:56:36 AM UTC 24 |
| Peak memory | 624868 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=pwrmgr_usbdev_smoketest:1 :new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim. tcl +ntb_random_seed=3729549465 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0 .chip_sw_pwrmgr_usbdev_smoketest.3729549465 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/0.chip_sw_pwrmgr_usbdev_smoketest/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_pwrmgr_wdog_reset.845711630 |
| Short name | T872 |
| Test name | |
| Test status | |
| Simulation time | 5052154392 ps |
| CPU time | 346.95 seconds |
| Started | Aug 24 08:09:00 AM UTC 24 |
| Finished | Aug 24 08:14:52 AM UTC 24 |
| Peak memory | 624744 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_i mages=pwrmgr_wdog_reset_reqs_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=845711630 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/defaul t.vdb -cm_log /dev/null -cm_name 0.chip_sw_pwrmgr_wdog_reset.845711630 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/0.chip_sw_pwrmgr_wdog_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_rom_ctrl_integrity_check.227729353 |
| Short name | T281 |
| Test name | |
| Test status | |
| Simulation time | 8943971664 ps |
| CPU time | 421.82 seconds |
| Started | Aug 24 08:35:38 AM UTC 24 |
| Finished | Aug 24 08:42:45 AM UTC 24 |
| Peak memory | 624700 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=rom_ctrl_integrity_check_ test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=227729353 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rom_ctrl_integrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm _log /dev/null -cm_name 0.chip_sw_rom_ctrl_integrity_check.227729353 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/0.chip_sw_rom_ctrl_integrity_check/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_rstmgr_rst_cnsty_escalation.3650874418 |
| Short name | T49 |
| Test name | |
| Test status | |
| Simulation time | 6280168936 ps |
| CPU time | 391.29 seconds |
| Started | Aug 24 07:39:10 AM UTC 24 |
| Finished | Aug 24 07:45:46 AM UTC 24 |
| Peak memory | 669360 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv + sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3650874418 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rstmgr _cnsty_fault_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_rstmgr_rst_cnsty_escalation.3650874418 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/0.chip_sw_rstmgr_rst_cnsty_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_rstmgr_smoketest.1354491353 |
| Short name | T920 |
| Test name | |
| Test status | |
| Simulation time | 2707708820 ps |
| CPU time | 158.94 seconds |
| Started | Aug 24 10:52:37 AM UTC 24 |
| Finished | Aug 24 10:55:18 AM UTC 24 |
| Peak memory | 624888 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=rstmgr_smoketest:1:new_ru les,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +nt b_random_seed=1354491353 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as sert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_s w_rstmgr_smoketest.1354491353 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/0.chip_sw_rstmgr_smoketest/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_rstmgr_sw_req.1325248439 |
| Short name | T236 |
| Test name | |
| Test status | |
| Simulation time | 3830801578 ps |
| CPU time | 241.31 seconds |
| Started | Aug 24 07:55:20 AM UTC 24 |
| Finished | Aug 24 07:59:25 AM UTC 24 |
| Peak memory | 624788 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=rstmgr_sw_req_test:1:new_ rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl + ntb_random_seed=1325248439 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip _sw_rstmgr_sw_req.1325248439 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/0.chip_sw_rstmgr_sw_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_rstmgr_sw_rst.3408549766 |
| Short name | T412 |
| Test name | |
| Test status | |
| Simulation time | 2408275276 ps |
| CPU time | 169.26 seconds |
| Started | Aug 24 07:55:20 AM UTC 24 |
| Finished | Aug 24 07:58:11 AM UTC 24 |
| Peak memory | 624764 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=rstmgr_sw_rst_ctrl_test:1 :new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim. tcl +ntb_random_seed=3408549766 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0 .chip_sw_rstmgr_sw_rst.3408549766 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/0.chip_sw_rstmgr_sw_rst/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_rv_core_ibex_icache_invalidate.2945807071 |
| Short name | T220 |
| Test name | |
| Test status | |
| Simulation time | 3110800088 ps |
| CPU time | 180.33 seconds |
| Started | Aug 24 09:02:11 AM UTC 24 |
| Finished | Aug 24 09:05:14 AM UTC 24 |
| Peak memory | 624556 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=rv_core_ibex_icache_inval idate_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/d v/tools/sim.tcl +ntb_random_seed=2945807071 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rv_core_ibex_icache_invalidate_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/de fault.vdb -cm_log /dev/null -cm_name 0.chip_sw_rv_core_ibex_icache_invalidate.2945807071 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/0.chip_sw_rv_core_ibex_icache_invalidate/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_rv_core_ibex_rnd.1734576444 |
| Short name | T161 |
| Test name | |
| Test status | |
| Simulation time | 5327103940 ps |
| CPU time | 685.3 seconds |
| Started | Aug 24 08:12:47 AM UTC 24 |
| Finished | Aug 24 08:24:20 AM UTC 24 |
| Peak memory | 626936 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=20_000_000 +rng_srate_value_max=32 +sw_b uild_device=sim_dv +sw_images=rv_core_ibex_rnd_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1734576444 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ =chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_rv_core_ibex_rnd.1734576444 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/0.chip_sw_rv_core_ibex_rnd/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_rv_dm_access_after_wakeup.346365580 |
| Short name | T98 |
| Test name | |
| Test status | |
| Simulation time | 6386078724 ps |
| CPU time | 397.5 seconds |
| Started | Aug 24 08:58:23 AM UTC 24 |
| Finished | Aug 24 09:05:06 AM UTC 24 |
| Peak memory | 636844 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/default/simv +use_jtag_dmi=1 +sw_build_device=sim_dv +sw_images=rv_dm_acc ess_after_wakeup_rma:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces /repo/hw/dv/tools/sim.tcl +ntb_random_seed=346365580 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rv_dm_access_after_wake up_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_rv_dm_access_after_wakeup.346365580 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/0.chip_sw_rv_dm_access_after_wakeup/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_rv_plic_smoketest.2635209044 |
| Short name | T376 |
| Test name | |
| Test status | |
| Simulation time | 2964520060 ps |
| CPU time | 175.57 seconds |
| Started | Aug 24 10:51:07 AM UTC 24 |
| Finished | Aug 24 10:54:05 AM UTC 24 |
| Peak memory | 624820 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=rv_plic_smoketest:1:new_r ules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +n tb_random_seed=2635209044 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a ssert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_ sw_rv_plic_smoketest.2635209044 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/0.chip_sw_rv_plic_smoketest/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_rv_timer_irq.818525971 |
| Short name | T127 |
| Test name | |
| Test status | |
| Simulation time | 2801212904 ps |
| CPU time | 209.69 seconds |
| Started | Aug 24 08:03:10 AM UTC 24 |
| Finished | Aug 24 08:06:43 AM UTC 24 |
| Peak memory | 624764 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=rv_timer_smoketest:1:new_ rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl + ntb_random_seed=818525971 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a ssert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_ sw_rv_timer_irq.818525971 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/0.chip_sw_rv_timer_irq/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_rv_timer_smoketest.3163723604 |
| Short name | T270 |
| Test name | |
| Test status | |
| Simulation time | 2592021832 ps |
| CPU time | 137.29 seconds |
| Started | Aug 24 10:51:35 AM UTC 24 |
| Finished | Aug 24 10:53:55 AM UTC 24 |
| Peak memory | 625064 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=rv_timer_smoketest:1:new_ rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl + ntb_random_seed=3163723604 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip _sw_rv_timer_smoketest.3163723604 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/0.chip_sw_rv_timer_smoketest/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_rv_timer_systick_test.538343542 |
| Short name | T129 |
| Test name | |
| Test status | |
| Simulation time | 38433488888 ps |
| CPU time | 6973.53 seconds |
| Started | Aug 24 08:03:21 AM UTC 24 |
| Finished | Aug 24 10:00:49 AM UTC 24 |
| Peak memory | 627620 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=50_000_000 +sw_build_device=sim_dv +sw_i mages=rv_timer_systick_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor kspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=538343542 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_rv_timer_systick_test.538343542 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/0.chip_sw_rv_timer_systick_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_sensor_ctrl_status.342842774 |
| Short name | T181 |
| Test name | |
| Test status | |
| Simulation time | 3364555671 ps |
| CPU time | 155.72 seconds |
| Started | Aug 24 08:38:11 AM UTC 24 |
| Finished | Aug 24 08:40:49 AM UTC 24 |
| Peak memory | 627076 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=40_000_000 +sw_build_device=sim_dv +sw_i mages=sensor_ctrl_status_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=342842774 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sensor_ctrl_st atus_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_sensor_ctrl_status.342842774 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/0.chip_sw_sensor_ctrl_status/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_sleep_pwm_pulses.2610483556 |
| Short name | T39 |
| Test name | |
| Test status | |
| Simulation time | 8903252856 ps |
| CPU time | 878.05 seconds |
| Started | Aug 24 07:38:54 AM UTC 24 |
| Finished | Aug 24 07:53:42 AM UTC 24 |
| Peak memory | 629728 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=sleep_pwm_pulses_test:1:n ew_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc l +ntb_random_seed=2610483556 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_pwm_pulses_vseq +en_cov=1 -cm line+cond+fsm+tg l+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_na me 0.chip_sw_sleep_pwm_pulses.2610483556 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/0.chip_sw_sleep_pwm_pulses/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_sleep_sram_ret_contents_no_scramble.679754384 |
| Short name | T624 |
| Test name | |
| Test status | |
| Simulation time | 7387148336 ps |
| CPU time | 379.93 seconds |
| Started | Aug 24 08:38:08 AM UTC 24 |
| Finished | Aug 24 08:44:33 AM UTC 24 |
| Peak memory | 626756 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=20_000_000 +en_scb_tl_err_chk=0 +bypass_ alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=sram_ctrl_sleep_sram_ret_contents_no_scramble_test:1:new_rules,test_rom:0 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=679754384 - assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r epo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_sleep_sram_ret_contents_ no_scramble.679754384 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/0.chip_sw_sleep_sram_ret_contents_no_scramble/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_sleep_sram_ret_contents_scramble.3824417576 |
| Short name | T218 |
| Test name | |
| Test status | |
| Simulation time | 6454935880 ps |
| CPU time | 451.98 seconds |
| Started | Aug 24 08:38:10 AM UTC 24 |
| Finished | Aug 24 08:45:48 AM UTC 24 |
| Peak memory | 626756 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=20_000_000 +en_scb_tl_err_chk=0 +bypass_ alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=sram_ctrl_sleep_sram_ret_contents_scramble_test:1:new_rules,test_rom:0 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3824417576 -as sert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/rep o/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_sleep_sram_ret_contents_sc ramble.3824417576 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/0.chip_sw_sleep_sram_ret_contents_scramble/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_spi_device_pass_through.360921844 |
| Short name | T14 |
| Test name | |
| Test status | |
| Simulation time | 7726839024 ps |
| CPU time | 552.02 seconds |
| Started | Aug 24 07:43:35 AM UTC 24 |
| Finished | Aug 24 07:52:53 AM UTC 24 |
| Peak memory | 641156 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=spi_passthrough_test:1:ne w_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=360921844 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_spi_passthrough_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm _name 0.chip_sw_spi_device_pass_through.360921844 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/0.chip_sw_spi_device_pass_through/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_spi_device_tpm.1403843236 |
| Short name | T17 |
| Test name | |
| Test status | |
| Simulation time | 3725184875 ps |
| CPU time | 272.12 seconds |
| Started | Aug 24 07:43:19 AM UTC 24 |
| Finished | Aug 24 07:47:55 AM UTC 24 |
| Peak memory | 637296 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=spi_device_tpm_tx_rx_test :1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/si m.tcl +ntb_random_seed=1403843236 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_spi_device_tpm_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/nul l -cm_name 0.chip_sw_spi_device_tpm.1403843236 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/0.chip_sw_spi_device_tpm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_spi_host_tx_rx.431577075 |
| Short name | T12 |
| Test name | |
| Test status | |
| Simulation time | 2157096360 ps |
| CPU time | 175.51 seconds |
| Started | Aug 24 07:43:18 AM UTC 24 |
| Finished | Aug 24 07:46:16 AM UTC 24 |
| Peak memory | 625168 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=spi_host_tx_rx_test:1:new _rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=431577075 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_spi_host_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_n ame 0.chip_sw_spi_host_tx_rx.431577075 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/0.chip_sw_spi_host_tx_rx/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_sram_ctrl_scrambled_access.3751324725 |
| Short name | T216 |
| Test name | |
| Test status | |
| Simulation time | 4630476876 ps |
| CPU time | 387.62 seconds |
| Started | Aug 24 08:35:39 AM UTC 24 |
| Finished | Aug 24 08:42:12 AM UTC 24 |
| Peak memory | 626884 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=12_000_000 +en_scb_tl_err_chk=0 +bypass_ alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=sram_ctrl_scrambled_access_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled= 1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3751324725 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sram_ctrl_scrambled_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac es/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_sram_ctrl_scrambled_ access.3751324725 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/0.chip_sw_sram_ctrl_scrambled_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq.116682732 |
| Short name | T217 |
| Test name | |
| Test status | |
| Simulation time | 3888674596 ps |
| CPU time | 340.8 seconds |
| Started | Aug 24 09:05:40 AM UTC 24 |
| Finished | Aug 24 09:11:25 AM UTC 24 |
| Peak memory | 626892 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/default/simv +mem_sel=main +sw_test_timeout_ns=12_000_000 +bypass_alert_r eady_to_end_check=1 +en_jitter=1 +en_scb_tl_err_chk=0 +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +sw_images=sram_ctrl_scrambled_access_test:1:ne w_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=116682732 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sram_ctrl_scrambled_access_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /d ev/null -cm_name 0.chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq.116682732 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/0.chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_sram_ctrl_smoketest.2242126139 |
| Short name | T922 |
| Test name | |
| Test status | |
| Simulation time | 3147072062 ps |
| CPU time | 156.29 seconds |
| Started | Aug 24 10:52:48 AM UTC 24 |
| Finished | Aug 24 10:55:27 AM UTC 24 |
| Peak memory | 624568 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=sram_ctrl_smoketest:1:new _rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2242126139 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.chi p_sw_sram_ctrl_smoketest.2242126139 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/0.chip_sw_sram_ctrl_smoketest/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_sysrst_ctrl_inputs.842156673 |
| Short name | T34 |
| Test name | |
| Test status | |
| Simulation time | 2969301449 ps |
| CPU time | 240.88 seconds |
| Started | Aug 24 08:03:46 AM UTC 24 |
| Finished | Aug 24 08:07:51 AM UTC 24 |
| Peak memory | 629164 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=sysrst_ctrl_inputs_test:1 :new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim. tcl +ntb_random_seed=842156673 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sysrst_ctrl_inputs_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/nu ll -cm_name 0.chip_sw_sysrst_ctrl_inputs.842156673 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/0.chip_sw_sysrst_ctrl_inputs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_sysrst_ctrl_outputs.774481984 |
| Short name | T18 |
| Test name | |
| Test status | |
| Simulation time | 3758473074 ps |
| CPU time | 249.46 seconds |
| Started | Aug 24 08:05:50 AM UTC 24 |
| Finished | Aug 24 08:10:03 AM UTC 24 |
| Peak memory | 625076 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=sysrst_ctrl_outputs_test: 1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim .tcl +ntb_random_seed=774481984 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sysrst_ctrl_outputs_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/ null -cm_name 0.chip_sw_sysrst_ctrl_outputs.774481984 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/0.chip_sw_sysrst_ctrl_outputs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_sysrst_ctrl_reset.568216236 |
| Short name | T19 |
| Test name | |
| Test status | |
| Simulation time | 22900854174 ps |
| CPU time | 1205.84 seconds |
| Started | Aug 24 08:04:41 AM UTC 24 |
| Finished | Aug 24 08:25:00 AM UTC 24 |
| Peak memory | 631424 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=36_000_000 +sw_build_device=sim_dv +sw_i mages=sysrst_ctrl_reset_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo rkspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=568216236 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sysrst_ctrl_res et_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_sysrst_ctrl_reset.568216236 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/0.chip_sw_sysrst_ctrl_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_uart_rand_baudrate.1996269189 |
| Short name | T79 |
| Test name | |
| Test status | |
| Simulation time | 13019630348 ps |
| CPU time | 1886.72 seconds |
| Started | Aug 24 07:41:12 AM UTC 24 |
| Finished | Aug 24 08:13:00 AM UTC 24 |
| Peak memory | 637372 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=80_000_000 +calibrate_usb_clk=1 +sw_buil d_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1996269189 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_ uart_rand_baudrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_uart_rand_baudrate.1996269189 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/0.chip_sw_uart_rand_baudrate/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_uart_smoketest.2505641421 |
| Short name | T925 |
| Test name | |
| Test status | |
| Simulation time | 2642912216 ps |
| CPU time | 186.68 seconds |
| Started | Aug 24 10:53:15 AM UTC 24 |
| Finished | Aug 24 10:56:24 AM UTC 24 |
| Peak memory | 624560 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=uart_smoketest:1:new_rule s,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ random_seed=2505641421 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.ch ip_sw_uart_smoketest.2505641421 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/0.chip_sw_uart_smoketest/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_uart_tx_rx_alt_clk_freq.3522909360 |
| Short name | T78 |
| Test name | |
| Test status | |
| Simulation time | 8073310461 ps |
| CPU time | 1038.11 seconds |
| Started | Aug 24 07:41:41 AM UTC 24 |
| Finished | Aug 24 07:59:11 AM UTC 24 |
| Peak memory | 634812 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=80_000_000 +chip_clock_source=ChipClockS ourceExternal96Mhz +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3522909360 -assert nopostproc +UV M_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_baudrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr atch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_uart_tx_rx_alt_clk_freq.3522909360 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/0.chip_sw_uart_tx_rx_alt_clk_freq/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_uart_tx_rx_bootstrap.873824041 |
| Short name | T250 |
| Test name | |
| Test status | |
| Simulation time | 80309071784 ps |
| CPU time | 12832.7 seconds |
| Started | Aug 24 07:39:09 AM UTC 24 |
| Finished | Aug 24 11:15:15 AM UTC 24 |
| Peak memory | 656620 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/default/simv +use_spi_load_bootstrap=1 +calibrate_usb_clk=1 +test_timeout _ns=160_000_000 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=873824041 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/chi p_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_uart_tx_rx_bootstrap.873824041 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/0.chip_sw_uart_tx_rx_bootstrap/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_usb_ast_clk_calib.3538151702 |
| Short name | T299 |
| Test name | |
| Test status | |
| Simulation time | 3129311219 ps |
| CPU time | 227.07 seconds |
| Started | Aug 24 09:02:39 AM UTC 24 |
| Finished | Aug 24 09:06:29 AM UTC 24 |
| Peak memory | 624704 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/default/simv +usb_max_drift=1 +usb_fast_sof=1 +sw_build_device=sim_dv +sw _images=ast_usb_clk_calib:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works paces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3538151702 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_usb_ast_clk_calib _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/ default.vdb -cm_log /dev/null -cm_name 0.chip_sw_usb_ast_clk_calib.3538151702 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/0.chip_sw_usb_ast_clk_calib/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_usbdev_dpi.4254989400 |
| Short name | T22 |
| Test name | |
| Test status | |
| Simulation time | 11985168544 ps |
| CPU time | 1992.16 seconds |
| Started | Aug 24 07:39:12 AM UTC 24 |
| Finished | Aug 24 08:12:46 AM UTC 24 |
| Peak memory | 627696 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/default/simv +uart_idx=0 +calibrate_usb_clk=1 +sw_test_timeout_ns=30_000_ 000 +sw_build_device=sim_dv +sw_images=usbdev_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4254989400 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ= chip_sw_usbdev_dpi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_usbdev_dpi.4254989400 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/0.chip_sw_usbdev_dpi/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_usbdev_pincfg.3013309829 |
| Short name | T101 |
| Test name | |
| Test status | |
| Simulation time | 31481263620 ps |
| CPU time | 6221.29 seconds |
| Started | Aug 24 07:40:38 AM UTC 24 |
| Finished | Aug 24 09:25:26 AM UTC 24 |
| Peak memory | 627624 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/default/simv +uart_idx=0 +calibrate_usb_clk=1 +sw_test_timeout_ns=100_000 _000 +sw_build_device=sim_dv +sw_images=usbdev_pincfg_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3013309829 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_T EST_SEQ=chip_sw_usbdev_dpi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlg rey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_usbdev_pincfg.3013309829 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/0.chip_sw_usbdev_pincfg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_usbdev_pullup.295522704 |
| Short name | T9 |
| Test name | |
| Test status | |
| Simulation time | 2696841260 ps |
| CPU time | 178.44 seconds |
| Started | Aug 24 07:39:10 AM UTC 24 |
| Finished | Aug 24 07:42:12 AM UTC 24 |
| Peak memory | 626852 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/default/simv +uart_idx=0 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw _images=usbdev_pullup_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=295522704 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_usbdev_dpi_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default .vdb -cm_log /dev/null -cm_name 0.chip_sw_usbdev_pullup.295522704 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/0.chip_sw_usbdev_pullup/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_usbdev_setuprx.2919076047 |
| Short name | T11 |
| Test name | |
| Test status | |
| Simulation time | 4249616410 ps |
| CPU time | 367.64 seconds |
| Started | Aug 24 07:39:18 AM UTC 24 |
| Finished | Aug 24 07:45:30 AM UTC 24 |
| Peak memory | 624564 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/default/simv +uart_idx=0 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw _images=usbdev_setuprx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor kspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2919076047 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_usbdev_dpi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 0.chip_sw_usbdev_setuprx.2919076047 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/0.chip_sw_usbdev_setuprx/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_usbdev_stream.3833582951 |
| Short name | T428 |
| Test name | |
| Test status | |
| Simulation time | 19066748468 ps |
| CPU time | 3353.14 seconds |
| Started | Aug 24 07:40:39 AM UTC 24 |
| Finished | Aug 24 08:37:08 AM UTC 24 |
| Peak memory | 627816 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/default/simv +uart_idx=0 +calibrate_usb_clk=1 +sw_test_timeout_ns=60_000_ 000 +sw_build_device=sim_dv +sw_images=usbdev_stream_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3833582951 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TE ST_SEQ=chip_sw_usbdev_stream_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/chip_ear lgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_usbdev_stream.3833582951 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/0.chip_sw_usbdev_stream/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_usbdev_vbus.1442065356 |
| Short name | T38 |
| Test name | |
| Test status | |
| Simulation time | 2631750990 ps |
| CPU time | 126.66 seconds |
| Started | Aug 24 07:39:03 AM UTC 24 |
| Finished | Aug 24 07:41:13 AM UTC 24 |
| Peak memory | 626604 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/default/simv +uart_idx=0 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw _images=usbdev_vbus_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp aces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1442065356 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_usbdev_dpi_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default. vdb -cm_log /dev/null -cm_name 0.chip_sw_usbdev_vbus.1442065356 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/0.chip_sw_usbdev_vbus/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_tap_straps_dev.1527765515 |
| Short name | T95 |
| Test name | |
| Test status | |
| Simulation time | 3747350562 ps |
| CPU time | 229.01 seconds |
| Started | Aug 24 08:59:47 AM UTC 24 |
| Finished | Aug 24 09:03:39 AM UTC 24 |
| Peak memory | 641204 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/default/simv +use_otp_image=OtpTypeLcStDev +create_jtag_riscv_map=1 +sw_b uild_device=sim_dv +sw_images=example_test_from_rom:0:test_in_rom:new_rules +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1527765515 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SE Q=chip_tap_straps_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_tap_straps_dev.1527765515 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/0.chip_tap_straps_dev/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_tap_straps_prod.3465942410 |
| Short name | T100 |
| Test name | |
| Test status | |
| Simulation time | 17761642183 ps |
| CPU time | 1367.4 seconds |
| Started | Aug 24 09:02:05 AM UTC 24 |
| Finished | Aug 24 09:25:08 AM UTC 24 |
| Peak memory | 644676 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/default/simv +use_otp_image=OtpTypeLcStProd +create_jtag_riscv_map=1 +sw_ build_device=sim_dv +sw_images=example_test_from_rom:0:test_in_rom:new_rules +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3465942410 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_S EQ=chip_tap_straps_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_tap_straps_prod.3465942410 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/0.chip_tap_straps_prod/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_tap_straps_testunlock0.3470944798 |
| Short name | T99 |
| Test name | |
| Test status | |
| Simulation time | 4534853267 ps |
| CPU time | 291.13 seconds |
| Started | Aug 24 09:00:52 AM UTC 24 |
| Finished | Aug 24 09:05:47 AM UTC 24 |
| Peak memory | 641480 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/default/simv +use_otp_image=OtpTypeLcStTestUnlocked0 +create_jtag_riscv_m ap=1 +sw_build_device=sim_dv +sw_images=example_test_from_rom:0:test_in_rom:new_rules +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3470944798 -assert nopostproc +UVM_TESTNAME=chip_base_test +U VM_TEST_SEQ=chip_tap_straps_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/chip_earl grey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_tap_straps_testunlock0.3470944798 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/0.chip_tap_straps_testunlock0/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/0.rom_e2e_asm_init_dev.1234861454 |
| Short name | T930 |
| Test name | |
| Test status | |
| Simulation time | 15913624086 ps |
| CPU time | 3121.66 seconds |
| Started | Aug 24 10:05:03 AM UTC 24 |
| Finished | Aug 24 10:57:38 AM UTC 24 |
| Peak memory | 627812 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/default/simv +use_otp_image=OtpTypeCustom +sw_test_timeout_ns=20000000 +s w_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_prod_key_0:1:ot_flash_binary,otp_img_e2e_bootstrap_entry_dev:4,mask_rom:0 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1234861454 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rom_e2e_asm_init_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_asm_init_dev.1234861454 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/0.rom_e2e_asm_init_dev/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/0.rom_e2e_asm_init_prod.492700354 |
| Short name | T926 |
| Test name | |
| Test status | |
| Simulation time | 15906376410 ps |
| CPU time | 3001.44 seconds |
| Started | Aug 24 10:05:59 AM UTC 24 |
| Finished | Aug 24 10:56:33 AM UTC 24 |
| Peak memory | 630020 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/default/simv +use_otp_image=OtpTypeCustom +sw_test_timeout_ns=20000000 +s w_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_prod_key_0:1:ot_flash_binary,otp_img_e2e_bootstrap_entry_prod:4,mask_rom:0 +cdc_inst rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=492700354 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rom_e2e_asm_init_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_asm_init_prod.492700354 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/0.rom_e2e_asm_init_prod/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/0.rom_e2e_asm_init_prod_end.4098992432 |
| Short name | T932 |
| Test name | |
| Test status | |
| Simulation time | 15876119576 ps |
| CPU time | 3236.75 seconds |
| Started | Aug 24 10:06:01 AM UTC 24 |
| Finished | Aug 24 11:00:33 AM UTC 24 |
| Peak memory | 627808 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/default/simv +use_otp_image=OtpTypeCustom +sw_test_timeout_ns=20000000 +s w_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_prod_key_0:1:ot_flash_binary,otp_img_e2e_bootstrap_entry_prod_end:4,mask_rom:0 +cdc_ instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=409899 2432 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rom_e2e_asm_init_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_asm_in it_prod_end.4098992432 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/0.rom_e2e_asm_init_prod_end/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/0.rom_e2e_asm_init_rma.1244203699 |
| Short name | T924 |
| Test name | |
| Test status | |
| Simulation time | 14671794252 ps |
| CPU time | 2941.58 seconds |
| Started | Aug 24 10:06:50 AM UTC 24 |
| Finished | Aug 24 10:56:22 AM UTC 24 |
| Peak memory | 624756 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/default/simv +use_otp_image=OtpTypeCustom +sw_test_timeout_ns=20000000 +s w_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_prod_key_0:1:ot_flash_binary,otp_img_e2e_bootstrap_entry_rma:4,mask_rom:0 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1244203699 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rom_e2e_asm_init_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_asm_init_rma.1244203699 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/0.rom_e2e_asm_init_rma/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/0.rom_e2e_asm_init_test_unlocked0.2510969019 |
| Short name | T900 |
| Test name | |
| Test status | |
| Simulation time | 10732845742 ps |
| CPU time | 2285.71 seconds |
| Started | Aug 24 10:03:42 AM UTC 24 |
| Finished | Aug 24 10:42:12 AM UTC 24 |
| Peak memory | 626808 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/default/simv +use_otp_image=OtpTypeCustom +sw_test_timeout_ns=410_000_000 +sw_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_prod_key_0:1:ot_flash_binary,otp_img_e2e_bootstrap_entry_test_unlocked0:4,mask_ro m:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_se ed=2510969019 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rom_e2e_asm_init_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a ssert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e 2e_asm_init_test_unlocked0.2510969019 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/0.rom_e2e_asm_init_test_unlocked0/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/0.rom_e2e_boot_policy_valid_a_bad_b_good_prod.4036850348 |
| Short name | T415 |
| Test name | |
| Test status | |
| Simulation time | 23912528592 ps |
| CPU time | 4973.4 seconds |
| Started | Aug 24 09:18:19 AM UTC 24 |
| Finished | Aug 24 10:42:05 AM UTC 24 |
| Peak memory | 627812 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=100_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a_corrupted:1:ot_flash_binary:signed:fake_ecdsa_prod_key_0,empty_test_slot_b_fake_ecdsa_prod_k ey_0:2:ot_flash_binary,otp_img_boot_policy_valid_prod:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu e -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4036850348 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw _base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cove rage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_boot_policy_valid_a_bad_b_good_prod.4036850348 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_bad_b_good_prod/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/0.rom_e2e_boot_policy_valid_a_bad_b_good_prod_end.640211031 |
| Short name | T905 |
| Test name | |
| Test status | |
| Simulation time | 23911534792 ps |
| CPU time | 5292.75 seconds |
| Started | Aug 24 09:19:00 AM UTC 24 |
| Finished | Aug 24 10:48:09 AM UTC 24 |
| Peak memory | 627816 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=100_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a_corrupted:1:ot_flash_binary:signed:fake_ecdsa_prod_key_0,empty_test_slot_b_fake_ecdsa_prod_k ey_0:2:ot_flash_binary,otp_img_boot_policy_valid_prod_end:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=640211031 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip _sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_boot_policy_valid_a_bad_b_good_prod_end.640211031 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_bad_b_good_prod_end/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/0.rom_e2e_boot_policy_valid_a_bad_b_good_rma.333992446 |
| Short name | T908 |
| Test name | |
| Test status | |
| Simulation time | 23031619010 ps |
| CPU time | 5287.3 seconds |
| Started | Aug 24 09:20:54 AM UTC 24 |
| Finished | Aug 24 10:49:57 AM UTC 24 |
| Peak memory | 628056 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=100_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a_corrupted:1:ot_flash_binary:signed:fake_ecdsa_prod_key_0,empty_test_slot_b_fake_ecdsa_prod_k ey_0:2:ot_flash_binary,otp_img_boot_policy_valid_rma:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=333992446 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_b ase_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/covera ge/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_boot_policy_valid_a_bad_b_good_rma.333992446 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_bad_b_good_rma/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/0.rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0.3413809148 |
| Short name | T414 |
| Test name | |
| Test status | |
| Simulation time | 18296405724 ps |
| CPU time | 3999.36 seconds |
| Started | Aug 24 09:16:03 AM UTC 24 |
| Finished | Aug 24 10:23:25 AM UTC 24 |
| Peak memory | 629860 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=410_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a_corrupted:1:ot_flash_binary:signed:fake_ecdsa_prod_key_0,empty_test_slot_b_fake_ecdsa_prod_k ey_0:2:ot_flash_binary,otp_img_boot_policy_valid_test_unlocked0:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3413809148 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_S EQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0.3413809148 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_bad_dev.1191078878 |
| Short name | T895 |
| Test name | |
| Test status | |
| Simulation time | 15369688574 ps |
| CPU time | 3175.61 seconds |
| Started | Aug 24 09:12:51 AM UTC 24 |
| Finished | Aug 24 10:06:21 AM UTC 24 |
| Peak memory | 629952 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=100_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_prod_key_0:1:ot_flash_binary,empty_test_slot_b_corrupted:2:ot_flash_binary:signed :fake_ecdsa_prod_key_0,otp_img_boot_policy_valid_dev:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1191078878 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_ base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover age/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_boot_policy_valid_a_good_b_bad_dev.1191078878 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_good_b_bad_dev/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_bad_prod.4050040014 |
| Short name | T896 |
| Test name | |
| Test status | |
| Simulation time | 15681090148 ps |
| CPU time | 3222.21 seconds |
| Started | Aug 24 09:12:53 AM UTC 24 |
| Finished | Aug 24 10:07:10 AM UTC 24 |
| Peak memory | 628060 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=100_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_prod_key_0:1:ot_flash_binary,empty_test_slot_b_corrupted:2:ot_flash_binary:signed :fake_ecdsa_prod_key_0,otp_img_boot_policy_valid_prod:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu e -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4050040014 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw _base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cove rage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_boot_policy_valid_a_good_b_bad_prod.4050040014 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_good_b_bad_prod/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_bad_prod_end.2061982600 |
| Short name | T891 |
| Test name | |
| Test status | |
| Simulation time | 15078910864 ps |
| CPU time | 2937.03 seconds |
| Started | Aug 24 09:13:44 AM UTC 24 |
| Finished | Aug 24 10:03:12 AM UTC 24 |
| Peak memory | 624764 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=100_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_prod_key_0:1:ot_flash_binary,empty_test_slot_b_corrupted:2:ot_flash_binary:signed :fake_ecdsa_prod_key_0,otp_img_boot_policy_valid_prod_end:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2061982600 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chi p_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_boot_policy_valid_a_good_b_bad_prod_end.2061982600 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_good_b_bad_prod_end/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_bad_rma.872478969 |
| Short name | T894 |
| Test name | |
| Test status | |
| Simulation time | 14737481930 ps |
| CPU time | 3000.33 seconds |
| Started | Aug 24 09:14:54 AM UTC 24 |
| Finished | Aug 24 10:05:26 AM UTC 24 |
| Peak memory | 624760 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=100_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_prod_key_0:1:ot_flash_binary,empty_test_slot_b_corrupted:2:ot_flash_binary:signed :fake_ecdsa_prod_key_0,otp_img_boot_policy_valid_rma:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=872478969 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_b ase_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/covera ge/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_boot_policy_valid_a_good_b_bad_rma.872478969 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_good_b_bad_rma/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_bad_test_unlocked0.688670986 |
| Short name | T61 |
| Test name | |
| Test status | |
| Simulation time | 12210605788 ps |
| CPU time | 2220.01 seconds |
| Started | Aug 24 09:12:43 AM UTC 24 |
| Finished | Aug 24 09:50:07 AM UTC 24 |
| Peak memory | 627288 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=410_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_prod_key_0:1:ot_flash_binary,empty_test_slot_b_corrupted:2:ot_flash_binary:signed :fake_ecdsa_prod_key_0,otp_img_boot_policy_valid_test_unlocked0:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=688670986 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SE Q=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_boot_policy_valid_a_good_b_bad_test_unlocked0.688670986 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_good_b_bad_test_unlocked0/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_good_dev.1137805272 |
| Short name | T893 |
| Test name | |
| Test status | |
| Simulation time | 15116303246 ps |
| CPU time | 3264.31 seconds |
| Started | Aug 24 09:10:18 AM UTC 24 |
| Finished | Aug 24 10:05:18 AM UTC 24 |
| Peak memory | 630028 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=100_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_prod_key_0:1:ot_flash_binary,empty_test_slot_b_fake_ecdsa_prod_key_0:2:ot_flash_b inary,otp_img_boot_policy_valid_dev:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works paces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1137805272 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default.vdb - cm_log /dev/null -cm_name 0.rom_e2e_boot_policy_valid_a_good_b_good_dev.1137805272 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_good_b_good_dev/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_good_prod.2557491267 |
| Short name | T892 |
| Test name | |
| Test status | |
| Simulation time | 15704145290 ps |
| CPU time | 3192.57 seconds |
| Started | Aug 24 09:10:46 AM UTC 24 |
| Finished | Aug 24 10:04:33 AM UTC 24 |
| Peak memory | 629796 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=100_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_prod_key_0:1:ot_flash_binary,empty_test_slot_b_fake_ecdsa_prod_key_0:2:ot_flash_b inary,otp_img_boot_policy_valid_prod:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2557491267 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_boot_policy_valid_a_good_b_good_prod.2557491267 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_good_b_good_prod/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_good_prod_end.2531418415 |
| Short name | T387 |
| Test name | |
| Test status | |
| Simulation time | 15348611956 ps |
| CPU time | 2955.53 seconds |
| Started | Aug 24 09:11:29 AM UTC 24 |
| Finished | Aug 24 10:01:16 AM UTC 24 |
| Peak memory | 629856 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=100_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_prod_key_0:1:ot_flash_binary,empty_test_slot_b_fake_ecdsa_prod_key_0:2:ot_flash_b inary,otp_img_boot_policy_valid_prod_end:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2531418415 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default. vdb -cm_log /dev/null -cm_name 0.rom_e2e_boot_policy_valid_a_good_b_good_prod_end.2531418415 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_good_b_good_prod_end/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_good_rma.732930347 |
| Short name | T890 |
| Test name | |
| Test status | |
| Simulation time | 14665078640 ps |
| CPU time | 2941.57 seconds |
| Started | Aug 24 09:12:28 AM UTC 24 |
| Finished | Aug 24 10:02:02 AM UTC 24 |
| Peak memory | 627824 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=100_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_prod_key_0:1:ot_flash_binary,empty_test_slot_b_fake_ecdsa_prod_key_0:2:ot_flash_b inary,otp_img_boot_policy_valid_rma:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works paces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=732930347 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -c m_log /dev/null -cm_name 0.rom_e2e_boot_policy_valid_a_good_b_good_rma.732930347 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_good_b_good_rma/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_good_test_unlocked0.1476495097 |
| Short name | T60 |
| Test name | |
| Test status | |
| Simulation time | 11269824706 ps |
| CPU time | 2315.59 seconds |
| Started | Aug 24 09:10:18 AM UTC 24 |
| Finished | Aug 24 09:49:19 AM UTC 24 |
| Peak memory | 627984 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=410_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_prod_key_0:1:ot_flash_binary,empty_test_slot_b_fake_ecdsa_prod_key_0:2:ot_flash_b inary,otp_img_boot_policy_valid_test_unlocked0:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1476495097 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/de fault.vdb -cm_log /dev/null -cm_name 0.rom_e2e_boot_policy_valid_a_good_b_good_test_unlocked0.1476495097 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_good_b_good_test_unlocked0/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/0.rom_e2e_jtag_debug_dev.3243942308 |
| Short name | T272 |
| Test name | |
| Test status | |
| Simulation time | 10947608496 ps |
| CPU time | 1386.5 seconds |
| Started | Aug 24 10:23:46 AM UTC 24 |
| Finished | Aug 24 10:47:09 AM UTC 24 |
| Peak memory | 641400 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/default/simv +use_jtag_dmi=1 +use_otp_image=OtpTypeCustom +sw_build_devic e=sim_dv +sw_images=img_dev_exec_disabled:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3243942308 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rom_e2e_jta g_debug_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_jtag_debug_dev.3243942308 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/0.rom_e2e_jtag_debug_dev/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/0.rom_e2e_jtag_debug_rma.3520052680 |
| Short name | T273 |
| Test name | |
| Test status | |
| Simulation time | 10900512227 ps |
| CPU time | 1344.08 seconds |
| Started | Aug 24 10:26:15 AM UTC 24 |
| Finished | Aug 24 10:48:56 AM UTC 24 |
| Peak memory | 641164 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/default/simv +use_jtag_dmi=1 +use_otp_image=OtpTypeCustom +sw_build_devic e=sim_dv +sw_images=img_rma_exec_disabled:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3520052680 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rom_e2e_jta g_debug_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_jtag_debug_rma.3520052680 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/0.rom_e2e_jtag_debug_rma/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/0.rom_e2e_jtag_debug_test_unlocked0.936225902 |
| Short name | T271 |
| Test name | |
| Test status | |
| Simulation time | 11923831833 ps |
| CPU time | 1466.02 seconds |
| Started | Aug 24 10:07:32 AM UTC 24 |
| Finished | Aug 24 10:32:17 AM UTC 24 |
| Peak memory | 637048 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/default/simv +use_jtag_dmi=1 +use_otp_image=OtpTypeCustom +sw_build_devic e=sim_dv +sw_images=img_test_unlocked0_exec_disabled:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=936225902 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_r om_e2e_jtag_debug_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_jtag_debug_test_unlocked0.936225902 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/0.rom_e2e_jtag_debug_test_unlocked0/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/0.rom_e2e_jtag_inject_dev.1737555623 |
| Short name | T659 |
| Test name | |
| Test status | |
| Simulation time | 31023571643 ps |
| CPU time | 2608.25 seconds |
| Started | Aug 24 10:32:40 AM UTC 24 |
| Finished | Aug 24 11:16:37 AM UTC 24 |
| Peak memory | 641612 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=40_000_000 +use_jtag_dmi=1 +use_otp_imag e=OtpTypeCustom +sw_build_device=sim_dv +sw_images=img_dev_exec_disabled:4,sram_program:5,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1737555623 -assert nopostproc +UVM_TESTNAME=ch ip_base_test +UVM_TEST_SEQ=chip_sw_rom_e2e_jtag_inject_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_jtag_inject_dev.1737555623 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/0.rom_e2e_jtag_inject_dev/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/0.rom_e2e_jtag_inject_rma.3768989989 |
| Short name | T443 |
| Test name | |
| Test status | |
| Simulation time | 40168307275 ps |
| CPU time | 2998.47 seconds |
| Started | Aug 24 10:34:26 AM UTC 24 |
| Finished | Aug 24 11:24:56 AM UTC 24 |
| Peak memory | 639556 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=40_000_000 +use_jtag_dmi=1 +use_otp_imag e=OtpTypeCustom +sw_build_device=sim_dv +sw_images=img_rma_exec_disabled:4,sram_program:5,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3768989989 -assert nopostproc +UVM_TESTNAME=ch ip_base_test +UVM_TEST_SEQ=chip_sw_rom_e2e_jtag_inject_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_jtag_inject_rma.3768989989 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/0.rom_e2e_jtag_inject_rma/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/0.rom_e2e_jtag_inject_test_unlocked0.775615472 |
| Short name | T442 |
| Test name | |
| Test status | |
| Simulation time | 32214643316 ps |
| CPU time | 2139.36 seconds |
| Started | Aug 24 10:26:38 AM UTC 24 |
| Finished | Aug 24 11:02:41 AM UTC 24 |
| Peak memory | 639468 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=40_000_000 +use_jtag_dmi=1 +use_otp_imag e=OtpTypeCustom +sw_build_device=sim_dv +sw_images=img_test_unlocked0_exec_disabled:4,sram_program:5,mask_rom:0 +cdc_instrumentation_enabled=1 +UV M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=775615472 -assert nopostproc +UVM_T ESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rom_e2e_jtag_inject_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_jtag_inject_test_unlocked0.775615472 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/0.rom_e2e_jtag_inject_test_unlocked0/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/0.rom_e2e_keymgr_init_rom_ext_invalid_meas.1936591381 |
| Short name | T963 |
| Test name | |
| Test status | |
| Simulation time | 15105732896 ps |
| CPU time | 2977.21 seconds |
| Started | Aug 24 10:42:47 AM UTC 24 |
| Finished | Aug 24 11:32:55 AM UTC 24 |
| Peak memory | 630120 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=40_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=rom_e2e_keymgr_init_otp_invalid_meas:1:new_rules,otp_img_keymgr_otp_invalid_meas:4,mask_rom:0 +cdc_instrumentat ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1936591381 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc ratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_keymgr_init_rom_ext_invalid_meas.1936591381 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/0.rom_e2e_keymgr_init_rom_ext_invalid_meas/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/0.rom_e2e_keymgr_init_rom_ext_meas.4124465508 |
| Short name | T961 |
| Test name | |
| Test status | |
| Simulation time | 15498321896 ps |
| CPU time | 3085.44 seconds |
| Started | Aug 24 10:39:57 AM UTC 24 |
| Finished | Aug 24 11:31:56 AM UTC 24 |
| Peak memory | 629792 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=40_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=rom_e2e_keymgr_init_otp_meas:1:new_rules,otp_img_keymgr_otp_meas:4,mask_rom:0 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4124465508 -assert nopostproc +UVM _TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_keymgr_init_rom_ext_meas.4124465508 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/0.rom_e2e_keymgr_init_rom_ext_meas/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/0.rom_e2e_keymgr_init_rom_ext_no_meas.135677769 |
| Short name | T966 |
| Test name | |
| Test status | |
| Simulation time | 14784671336 ps |
| CPU time | 3188.12 seconds |
| Started | Aug 24 10:42:45 AM UTC 24 |
| Finished | Aug 24 11:36:27 AM UTC 24 |
| Peak memory | 627736 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=40_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=rom_e2e_keymgr_init_otp_no_meas:1:new_rules,otp_img_keymgr_otp_no_meas:4,mask_rom:0 +cdc_instrumentation_enable d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=135677769 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_keymgr_init_rom_ext_no_meas.135677769 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/0.rom_e2e_keymgr_init_rom_ext_no_meas/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/0.rom_e2e_self_hash.3421771704 |
| Short name | T1014 |
| Test name | |
| Test status | |
| Simulation time | 26766039128 ps |
| CPU time | 5285.95 seconds |
| Started | Aug 24 10:46:23 AM UTC 24 |
| Finished | Aug 24 12:15:25 PM UTC 24 |
| Peak memory | 628020 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=200_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=rom_e2e_self_hash_test:1:new_rules,otp_img_sigverify_spx_prod:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3421771704 -assert nopostproc +UVM_T ESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_self_hash.3421771704 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/0.rom_e2e_self_hash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/0.rom_e2e_shutdown_exception_c.4220402377 |
| Short name | T57 |
| Test name | |
| Test status | |
| Simulation time | 14569191155 ps |
| CPU time | 2843.6 seconds |
| Started | Aug 24 09:08:35 AM UTC 24 |
| Finished | Aug 24 09:56:28 AM UTC 24 |
| Peak memory | 627856 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=40000000 +use_otp_image=OtpTypeCustom +s w_build_device=sim_dv +sw_images=rom_e2e_shutdown_exception_c:1:new_rules,otp_img_secret2_locked_rma:4,mask_rom:0 +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4220402377 -assert nopostproc +UV M_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rom_e2e_shutdown_exception_c_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace s/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_shutdown_exception_c.4220402377 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/0.rom_e2e_shutdown_exception_c/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_bad_dev.838174065 |
| Short name | T916 |
| Test name | |
| Test status | |
| Simulation time | 23347126805 ps |
| CPU time | 5200.65 seconds |
| Started | Aug 24 09:25:53 AM UTC 24 |
| Finished | Aug 24 10:53:29 AM UTC 24 |
| Peak memory | 627924 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=100_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a_corrupted:1:ot_flash_binary:signed:fake_ecdsa_dev_key_0,empty_test_slot_b_corrupted:2:ot_fla sh_binary:signed:fake_ecdsa_dev_key_0,otp_img_sigverify_always_dev:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=838174065 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST _SEQ=chip_sw_rom_e2e_sigverify_always_a_bad_b_bad_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_sigverify_always_a_bad_b_bad_dev.838174065 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_bad_b_bad_dev/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_bad_prod.3345453279 |
| Short name | T914 |
| Test name | |
| Test status | |
| Simulation time | 23157885796 ps |
| CPU time | 5122.82 seconds |
| Started | Aug 24 09:26:07 AM UTC 24 |
| Finished | Aug 24 10:52:24 AM UTC 24 |
| Peak memory | 627928 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=100_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a_corrupted:1:ot_flash_binary:signed:fake_ecdsa_prod_key_0,empty_test_slot_b_corrupted:2:ot_fl ash_binary:signed:fake_ecdsa_prod_key_0,otp_img_sigverify_always_prod:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3345453279 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_ TEST_SEQ=chip_sw_rom_e2e_sigverify_always_a_bad_b_bad_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_sigverify_always_a_bad_b_bad_prod.3345453279 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_bad_b_bad_prod/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_bad_prod_end.3795907483 |
| Short name | T933 |
| Test name | |
| Test status | |
| Simulation time | 23293400961 ps |
| CPU time | 5464.86 seconds |
| Started | Aug 24 09:29:18 AM UTC 24 |
| Finished | Aug 24 11:01:22 AM UTC 24 |
| Peak memory | 628100 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=100_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a_corrupted:1:ot_flash_binary:signed:fake_ecdsa_prod_key_0,empty_test_slot_b_corrupted:2:ot_fl ash_binary:signed:fake_ecdsa_prod_key_0,otp_img_sigverify_always_prod_end:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3795907483 -assert nopostproc +UVM_TESTNAME=chip_base_test + UVM_TEST_SEQ=chip_sw_rom_e2e_sigverify_always_a_bad_b_bad_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_sigverify_always_a_bad_b_bad_prod_end.3795907483 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_bad_b_bad_prod_end/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_bad_rma.2673040497 |
| Short name | T941 |
| Test name | |
| Test status | |
| Simulation time | 23343334754 ps |
| CPU time | 5053.11 seconds |
| Started | Aug 24 09:49:13 AM UTC 24 |
| Finished | Aug 24 11:14:21 AM UTC 24 |
| Peak memory | 628432 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=100_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a_corrupted:1:ot_flash_binary:signed:fake_ecdsa_prod_key_0,empty_test_slot_b_corrupted:2:ot_fl ash_binary:signed:fake_ecdsa_prod_key_0,otp_img_sigverify_always_rma:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2673040497 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_T EST_SEQ=chip_sw_rom_e2e_sigverify_always_a_bad_b_bad_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_sigverify_always_a_bad_b_bad_rma.2673040497 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_bad_b_bad_rma/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_bad_test_unlocked0.892503610 |
| Short name | T898 |
| Test name | |
| Test status | |
| Simulation time | 18364985715 ps |
| CPU time | 4234.1 seconds |
| Started | Aug 24 09:25:38 AM UTC 24 |
| Finished | Aug 24 10:36:57 AM UTC 24 |
| Peak memory | 628164 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=600_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a_corrupted:1:ot_flash_binary:signed:fake_ecdsa_test_key_0,empty_test_slot_b_corrupted:2:ot_fl ash_binary:signed:fake_ecdsa_test_key_0,otp_img_sigverify_always_test_unlocked0:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=892503610 -assert nopostproc +UVM_TESTNAME=chip_base_t est +UVM_TEST_SEQ=chip_sw_rom_e2e_sigverify_always_a_bad_b_bad_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_sigverify_always_a_bad_b_bad_test_unlocked0.892503610 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_bad_b_bad_test_unlocked0/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_nothing_dev.1145302526 |
| Short name | T899 |
| Test name | |
| Test status | |
| Simulation time | 15249089948 ps |
| CPU time | 2905.1 seconds |
| Started | Aug 24 09:50:33 AM UTC 24 |
| Finished | Aug 24 10:39:29 AM UTC 24 |
| Peak memory | 626860 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=100_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a_corrupted:1:ot_flash_binary:signed:fake_ecdsa_dev_key_0,otp_img_sigverify_always_dev:4,mask_ rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_ seed=1145302526 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rom_e2e_sigverify_always_a_bad_b_bad_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev /null -cm_name 0.rom_e2e_sigverify_always_a_bad_b_nothing_dev.1145302526 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_bad_b_nothing_dev/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_nothing_prod.4243393108 |
| Short name | T902 |
| Test name | |
| Test status | |
| Simulation time | 13626774039 ps |
| CPU time | 2928.51 seconds |
| Started | Aug 24 09:55:12 AM UTC 24 |
| Finished | Aug 24 10:44:33 AM UTC 24 |
| Peak memory | 629912 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=100_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a_corrupted:1:ot_flash_binary:signed:fake_ecdsa_prod_key_0,otp_img_sigverify_always_prod:4,mas k_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_rando m_seed=4243393108 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rom_e2e_sigverify_always_a_bad_b_bad_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /d ev/null -cm_name 0.rom_e2e_sigverify_always_a_bad_b_nothing_prod.4243393108 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_bad_b_nothing_prod/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_nothing_prod_end.3704703313 |
| Short name | T904 |
| Test name | |
| Test status | |
| Simulation time | 15055002692 ps |
| CPU time | 2947.97 seconds |
| Started | Aug 24 09:56:59 AM UTC 24 |
| Finished | Aug 24 10:46:39 AM UTC 24 |
| Peak memory | 630092 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=100_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a_corrupted:1:ot_flash_binary:signed:fake_ecdsa_prod_key_0,otp_img_sigverify_always_prod_end:4 ,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_r andom_seed=3704703313 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rom_e2e_sigverify_always_a_bad_b_bad_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_lo g /dev/null -cm_name 0.rom_e2e_sigverify_always_a_bad_b_nothing_prod_end.3704703313 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_bad_b_nothing_prod_end/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_nothing_rma.1160700321 |
| Short name | T901 |
| Test name | |
| Test status | |
| Simulation time | 13524197692 ps |
| CPU time | 2774.09 seconds |
| Started | Aug 24 09:57:08 AM UTC 24 |
| Finished | Aug 24 10:43:52 AM UTC 24 |
| Peak memory | 626856 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=100_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a_corrupted:1:ot_flash_binary:signed:fake_ecdsa_prod_key_0,otp_img_sigverify_always_rma:4,mask _rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=1160700321 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rom_e2e_sigverify_always_a_bad_b_bad_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /de v/null -cm_name 0.rom_e2e_sigverify_always_a_bad_b_nothing_rma.1160700321 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_bad_b_nothing_rma/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_nothing_test_unlocked0.3666614577 |
| Short name | T59 |
| Test name | |
| Test status | |
| Simulation time | 11630215263 ps |
| CPU time | 2144.75 seconds |
| Started | Aug 24 09:49:46 AM UTC 24 |
| Finished | Aug 24 10:25:54 AM UTC 24 |
| Peak memory | 627400 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=410_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a_corrupted:1:ot_flash_binary:signed:fake_ecdsa_test_key_0:new_rules,otp_img_sigverify_always_ test_unlocked0:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=3666614577 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rom_e2e_sigverify_always_a_bad_b_bad_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/de fault.vdb -cm_log /dev/null -cm_name 0.rom_e2e_sigverify_always_a_bad_b_nothing_test_unlocked0.3666614577 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_bad_b_nothing_test_unlocked0/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/0.rom_e2e_sigverify_always_a_nothing_b_bad_dev.765243812 |
| Short name | T907 |
| Test name | |
| Test status | |
| Simulation time | 14382295449 ps |
| CPU time | 2897.45 seconds |
| Started | Aug 24 10:00:51 AM UTC 24 |
| Finished | Aug 24 10:49:40 AM UTC 24 |
| Peak memory | 629976 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=100_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_b_corrupted:1:ot_flash_binary:signed:fake_ecdsa_dev_key_0,otp_img_sigverify_always_dev:4,mask_ rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_ seed=765243812 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rom_e2e_sigverify_always_a_bad_b_bad_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/ null -cm_name 0.rom_e2e_sigverify_always_a_nothing_b_bad_dev.765243812 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_nothing_b_bad_dev/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/0.rom_e2e_sigverify_always_a_nothing_b_bad_prod.1549780791 |
| Short name | T906 |
| Test name | |
| Test status | |
| Simulation time | 14901911956 ps |
| CPU time | 2824.01 seconds |
| Started | Aug 24 10:01:16 AM UTC 24 |
| Finished | Aug 24 10:48:51 AM UTC 24 |
| Peak memory | 624884 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=100_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_b_corrupted:1:ot_flash_binary:signed:fake_ecdsa_prod_key_0,otp_img_sigverify_always_prod:4,mas k_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_rando m_seed=1549780791 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rom_e2e_sigverify_always_a_bad_b_bad_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /d ev/null -cm_name 0.rom_e2e_sigverify_always_a_nothing_b_bad_prod.1549780791 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_nothing_b_bad_prod/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/0.rom_e2e_sigverify_always_a_nothing_b_bad_prod_end.2383702178 |
| Short name | T911 |
| Test name | |
| Test status | |
| Simulation time | 14723975008 ps |
| CPU time | 2894.22 seconds |
| Started | Aug 24 10:01:43 AM UTC 24 |
| Finished | Aug 24 10:50:28 AM UTC 24 |
| Peak memory | 627816 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=100_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_b_corrupted:1:ot_flash_binary:signed:fake_ecdsa_prod_key_0,otp_img_sigverify_always_prod_end:4 ,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_r andom_seed=2383702178 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rom_e2e_sigverify_always_a_bad_b_bad_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_lo g /dev/null -cm_name 0.rom_e2e_sigverify_always_a_nothing_b_bad_prod_end.2383702178 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_nothing_b_bad_prod_end/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/0.rom_e2e_sigverify_always_a_nothing_b_bad_rma.3910226952 |
| Short name | T903 |
| Test name | |
| Test status | |
| Simulation time | 13904616292 ps |
| CPU time | 2569.24 seconds |
| Started | Aug 24 10:02:29 AM UTC 24 |
| Finished | Aug 24 10:45:44 AM UTC 24 |
| Peak memory | 626940 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=100_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_b_corrupted:1:ot_flash_binary:signed:fake_ecdsa_prod_key_0,otp_img_sigverify_always_rma:4,mask _rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=3910226952 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rom_e2e_sigverify_always_a_bad_b_bad_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /de v/null -cm_name 0.rom_e2e_sigverify_always_a_nothing_b_bad_rma.3910226952 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_nothing_b_bad_rma/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/0.rom_e2e_sigverify_always_a_nothing_b_bad_test_unlocked0.3036449641 |
| Short name | T897 |
| Test name | |
| Test status | |
| Simulation time | 11345660349 ps |
| CPU time | 1981.34 seconds |
| Started | Aug 24 10:00:40 AM UTC 24 |
| Finished | Aug 24 10:34:02 AM UTC 24 |
| Peak memory | 627072 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=410_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_b_corrupted:1:ot_flash_binary:signed:fake_ecdsa_test_key_0,otp_img_sigverify_always_test_unloc ked0:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3036449641 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rom_e2e_sigverify_always_a_bad_b_bad_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_sigverify_always_a_nothing_b_bad_test_unlocked0.3036449641 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_nothing_b_bad_test_unlocked0/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/0.rom_e2e_smoke.2096147465 |
| Short name | T889 |
| Test name | |
| Test status | |
| Simulation time | 15456715040 ps |
| CPU time | 3115.68 seconds |
| Started | Aug 24 09:07:42 AM UTC 24 |
| Finished | Aug 24 10:00:12 AM UTC 24 |
| Peak memory | 627740 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=40000000 +use_otp_image=OtpTypeCustom +s w_build_device=sim_dv +sw_images=rom_e2e_smoke:1:new_rules,otp_img_secret2_locked_rma:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2096147465 -assert nopostproc +UVM_TESTNAME=chip _base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22 /chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_smoke.2096147465 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/0.rom_e2e_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/0.rom_e2e_static_critical.913855108 |
| Short name | T964 |
| Test name | |
| Test status | |
| Simulation time | 17248456728 ps |
| CPU time | 3333.4 seconds |
| Started | Aug 24 10:37:26 AM UTC 24 |
| Finished | Aug 24 11:33:35 AM UTC 24 |
| Peak memory | 627744 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=40000000 +use_otp_image=OtpTypeCustom +s w_build_device=sim_dv +sw_images=rom_e2e_static_critical:1:new_rules,otp_img_secret2_locked_rma:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=913855108 -assert nopostproc +UVM_TEST NAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_static_critical.913855108 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/0.rom_e2e_static_critical/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/0.rom_keymgr_functest.3295926644 |
| Short name | T915 |
| Test name | |
| Test status | |
| Simulation time | 4105385940 ps |
| CPU time | 385.17 seconds |
| Started | Aug 24 10:46:21 AM UTC 24 |
| Finished | Aug 24 10:52:52 AM UTC 24 |
| Peak memory | 624572 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=10_000_000 +sw_build_device=sim_dv +sw_i mages=keymgr_functest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace s/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3295926644 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_l og /dev/null -cm_name 0.rom_keymgr_functest.3295926644 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/0.rom_keymgr_functest/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/0.rom_raw_unlock.2243409662 |
| Short name | T189 |
| Test name | |
| Test status | |
| Simulation time | 5667056052 ps |
| CPU time | 180.25 seconds |
| Started | Aug 24 10:44:57 AM UTC 24 |
| Finished | Aug 24 10:48:00 AM UTC 24 |
| Peak memory | 638488 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/default/simv +do_creator_sw_cfg_ast_cfg=0 +sw_test_timeout_ns=200_000_000 +use_otp_image=OtpTypeLcStRaw +chip_clock_source=ChipClockSourceExternal48Mhz +rom_prod_mode=1 +use_jtag_dmi=1 +sw_build_device=sim_dv +sw_images =empty_test_slot_a_fake_ecdsa_test_key_0:1:ot_flash_binary,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2243409662 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip _sw_lc_raw_unlock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_raw_unlock.2243409662 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/0.rom_raw_unlock/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/0.rom_volatile_raw_unlock.749269448 |
| Short name | T630 |
| Test name | |
| Test status | |
| Simulation time | 2209828442 ps |
| CPU time | 89.31 seconds |
| Started | Aug 24 10:44:16 AM UTC 24 |
| Finished | Aug 24 10:45:47 AM UTC 24 |
| Peak memory | 634552 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=200_000_000 +use_otp_image=OtpTypeLcStRa w +chip_clock_source=ChipClockSourceExternal48Mhz +rom_prod_mode=1 +sw_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_test_key_0:1:ot _flash_binary,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/s im.tcl +ntb_random_seed=749269448 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_volatile_raw_unlock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_volatile_raw_unlock.749269448 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/0.rom_volatile_raw_unlock/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_jtag_mem_access.3879706742 |
| Short name | T242 |
| Test name | |
| Test status | |
| Simulation time | 13894783444 ps |
| CPU time | 898.76 seconds |
| Started | Aug 24 12:15:40 PM UTC 24 |
| Finished | Aug 24 12:30:50 PM UTC 24 |
| Peak memory | 627288 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/default/simv +create_jtag_riscv_map=1 +stub_cpu=1 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3879706742 -assert nopos tproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_jtag_mem_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_jtag_mem_access.3879706742 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/1.chip_jtag_mem_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_rv_dm_ndm_reset_req.1089545732 |
| Short name | T410 |
| Test name | |
| Test status | |
| Simulation time | 4412350688 ps |
| CPU time | 319.06 seconds |
| Started | Aug 24 12:18:53 PM UTC 24 |
| Finished | Aug 24 12:24:16 PM UTC 24 |
| Peak memory | 637148 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/default/simv +en_scb_tl_err_chk=0 +use_jtag_dmi=1 +sw_build_device=sim_dv +sw_images=rv_dm_ndm_reset_req_rma:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1089545732 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_rv_dm_ndm_ reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cove rage/default.vdb -cm_log /dev/null -cm_name 1.chip_rv_dm_ndm_reset_req.1089545732 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/1.chip_rv_dm_ndm_reset_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sival_flash_info_access.3910114738 |
| Short name | T385 |
| Test name | |
| Test status | |
| Simulation time | 3516587366 ps |
| CPU time | 228.46 seconds |
| Started | Aug 24 10:54:45 AM UTC 24 |
| Finished | Aug 24 10:58:37 AM UTC 24 |
| Peak memory | 624996 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/default/simv +use_otp_image=OtpTypeLcStTestUnlocked0 +sw_build_device=sim _dv +sw_images=flash_ctrl_info_access_lc:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3910114738 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_ba se_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 1.chip_sival_flash_info_access.3910114738 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/1.chip_sival_flash_info_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_adc_ctrl_sleep_debug_cable_wakeup.2298350535 |
| Short name | T382 |
| Test name | |
| Test status | |
| Simulation time | 19594032392 ps |
| CPU time | 367.31 seconds |
| Started | Aug 24 11:33:21 AM UTC 24 |
| Finished | Aug 24 11:39:33 AM UTC 24 |
| Peak memory | 636932 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_i mages=adc_ctrl_sleep_debug_cable_wakeup_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2298350535 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_s w_adc_ctrl_sleep_debug_cable_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/c hip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_adc_ctrl_sleep_debug_cable_wakeup.2298350535 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/1.chip_sw_adc_ctrl_sleep_debug_cable_wakeup/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_aes_enc.4195527538 |
| Short name | T971 |
| Test name | |
| Test status | |
| Simulation time | 2887216620 ps |
| CPU time | 218.82 seconds |
| Started | Aug 24 11:35:39 AM UTC 24 |
| Finished | Aug 24 11:39:21 AM UTC 24 |
| Peak memory | 624680 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=22_000_000 +sw_build_device=sim_dv +sw_i mages=aes_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/ repo/hw/dv/tools/sim.tcl +ntb_random_seed=4195527538 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_aes_enc.4195527538 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/1.chip_sw_aes_enc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_aes_enc_jitter_en.823704712 |
| Short name | T974 |
| Test name | |
| Test status | |
| Simulation time | 3232060594 ps |
| CPU time | 195.15 seconds |
| Started | Aug 24 11:36:59 AM UTC 24 |
| Finished | Aug 24 11:40:17 AM UTC 24 |
| Peak memory | 624564 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=26_000_000 +en_jitter=1 +sw_build_device =sim_dv +sw_images=aes_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=823704712 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default .vdb -cm_log /dev/null -cm_name 1.chip_sw_aes_enc_jitter_en.823704712 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/1.chip_sw_aes_enc_jitter_en/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_aes_enc_jitter_en_reduced_freq.3695512744 |
| Short name | T1037 |
| Test name | |
| Test status | |
| Simulation time | 3670311867 ps |
| CPU time | 209.4 seconds |
| Started | Aug 24 12:26:14 PM UTC 24 |
| Finished | Aug 24 12:29:46 PM UTC 24 |
| Peak memory | 624564 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=26_000_000 +en_jitter=1 +cal_sys_clk_70m hz=1 +sw_build_device=sim_dv +sw_images=aes_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3695512744 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_S EQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_aes_enc_jitter_en_reduced_freq.3695512744 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/1.chip_sw_aes_enc_jitter_en_reduced_freq/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_aes_entropy.3597284254 |
| Short name | T980 |
| Test name | |
| Test status | |
| Simulation time | 2324647408 ps |
| CPU time | 172.76 seconds |
| Started | Aug 24 11:41:10 AM UTC 24 |
| Finished | Aug 24 11:44:05 AM UTC 24 |
| Peak memory | 624808 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=15_000_000 +sw_build_device=sim_dv +sw_i mages=aes_entropy_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac es/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3597284254 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_ log /dev/null -cm_name 1.chip_sw_aes_entropy.3597284254 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/1.chip_sw_aes_entropy/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_aes_idle.726955 |
| Short name | T975 |
| Test name | |
| Test status | |
| Simulation time | 2653466368 ps |
| CPU time | 201.96 seconds |
| Started | Aug 24 11:36:59 AM UTC 24 |
| Finished | Aug 24 11:40:24 AM UTC 24 |
| Peak memory | 624880 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=25_000_000 +sw_build_device=sim_dv +sw_i mages=aes_idle_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/ repo/hw/dv/tools/sim.tcl +ntb_random_seed=726955 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /de v/null -cm_name 1.chip_sw_aes_idle.726955 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/1.chip_sw_aes_idle/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_aes_masking_off.546583668 |
| Short name | T976 |
| Test name | |
| Test status | |
| Simulation time | 3215445831 ps |
| CPU time | 255.86 seconds |
| Started | Aug 24 11:37:44 AM UTC 24 |
| Finished | Aug 24 11:42:04 AM UTC 24 |
| Peak memory | 624776 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=aes_masking_off_test:1:ne w_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=546583668 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_aes_masking_off_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm _name 1.chip_sw_aes_masking_off.546583668 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/1.chip_sw_aes_masking_off/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_aes_smoketest.127217297 |
| Short name | T1046 |
| Test name | |
| Test status | |
| Simulation time | 2635246568 ps |
| CPU time | 155.55 seconds |
| Started | Aug 24 12:38:29 PM UTC 24 |
| Finished | Aug 24 12:41:07 PM UTC 24 |
| Peak memory | 624696 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=aes_smoketest:1:new_rules ,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_r andom_seed=127217297 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_ae s_smoketest.127217297 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/1.chip_sw_aes_smoketest/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_alert_handler_entropy.305152411 |
| Short name | T196 |
| Test name | |
| Test status | |
| Simulation time | 3194223593 ps |
| CPU time | 220.8 seconds |
| Started | Aug 24 11:41:09 AM UTC 24 |
| Finished | Aug 24 11:44:53 AM UTC 24 |
| Peak memory | 624756 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/default/simv +en_scb=0 +bypass_alert_ready_to_end_check=1 +sw_build_devic e=sim_dv +sw_images=alert_handler_entropy_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=305152411 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_ sw_alert_handler_entropy_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgre y_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_alert_handler_entropy.305152411 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/1.chip_sw_alert_handler_entropy/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_alert_handler_escalation.4172987822 |
| Short name | T981 |
| Test name | |
| Test status | |
| Simulation time | 5372643762 ps |
| CPU time | 312.72 seconds |
| Started | Aug 24 11:39:01 AM UTC 24 |
| Finished | Aug 24 11:44:18 AM UTC 24 |
| Peak memory | 636992 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/default/simv +en_scb=0 +bypass_alert_ready_to_end_check=1 +sw_build_devic e=sim_dv +sw_images=alert_handler_escalation_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4172987822 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=c hip_sw_alert_handler_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/chip_ earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_alert_handler_escalation.4172987822 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/1.chip_sw_alert_handler_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_alert_handler_lpg_clkoff.949820374 |
| Short name | T996 |
| Test name | |
| Test status | |
| Simulation time | 7557465144 ps |
| CPU time | 1002 seconds |
| Started | Aug 24 11:40:50 AM UTC 24 |
| Finished | Aug 24 11:57:43 AM UTC 24 |
| Peak memory | 626752 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +sw_build_device= sim_dv +sw_images=alert_handler_lpg_clkoff_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=949820374 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip _sw_alert_handler_lpg_clkoff_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/chip_ear lgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_alert_handler_lpg_clkoff.949820374 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/1.chip_sw_alert_handler_lpg_clkoff/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_alert_handler_lpg_reset_toggle.868095858 |
| Short name | T1001 |
| Test name | |
| Test status | |
| Simulation time | 7893970948 ps |
| CPU time | 1190.8 seconds |
| Started | Aug 24 11:40:51 AM UTC 24 |
| Finished | Aug 24 12:00:55 PM UTC 24 |
| Peak memory | 626608 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +sw_build_device= sim_dv +sw_images=alert_handler_lpg_reset_toggle_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=868095858 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SE Q=chip_sw_alert_handler_shorten_ping_wait_cycle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_alert_handler_lpg_reset_toggle.868095858 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/1.chip_sw_alert_handler_lpg_reset_toggle/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_alert_handler_lpg_sleep_mode_pings.1234323285 |
| Short name | T197 |
| Test name | |
| Test status | |
| Simulation time | 11181412624 ps |
| CPU time | 877.47 seconds |
| Started | Aug 24 11:40:14 AM UTC 24 |
| Finished | Aug 24 11:55:02 AM UTC 24 |
| Peak memory | 626692 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_rea dy_to_end_check=1 +sw_build_device=sim_dv +sw_images=alert_handler_lpg_sleep_mode_pings_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1234323285 -assert nopostproc + UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_alert_handler_shorten_ping_wait_cycle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_alert_hand ler_lpg_sleep_mode_pings.1234323285 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/1.chip_sw_alert_handler_lpg_sleep_mode_pings/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_alert_handler_ping_ok.740334028 |
| Short name | T993 |
| Test name | |
| Test status | |
| Simulation time | 7054284840 ps |
| CPU time | 910.5 seconds |
| Started | Aug 24 11:39:45 AM UTC 24 |
| Finished | Aug 24 11:55:06 AM UTC 24 |
| Peak memory | 624768 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/default/simv +en_scb=0 +sw_test_timeout_ns=24000000 +sw_build_device=sim_ dv +sw_images=alert_handler_ping_ok_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=740334028 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_bas e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage /default.vdb -cm_log /dev/null -cm_name 1.chip_sw_alert_handler_ping_ok.740334028 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/1.chip_sw_alert_handler_ping_ok/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_alert_handler_ping_timeout.1809766314 |
| Short name | T982 |
| Test name | |
| Test status | |
| Simulation time | 5271370820 ps |
| CPU time | 362.75 seconds |
| Started | Aug 24 11:39:14 AM UTC 24 |
| Finished | Aug 24 11:45:22 AM UTC 24 |
| Peak memory | 626960 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/default/simv +en_scb=0 +sw_test_timeout_ns=24000000 +sw_build_device=sim_ dv +sw_images=alert_handler_ping_timeout_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu eue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1809766314 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_ sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_alert_handler_ping_timeout.1809766314 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/1.chip_sw_alert_handler_ping_timeout/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_alert_handler_reverse_ping_in_deep_sleep.2293328563 |
| Short name | T1241 |
| Test name | |
| Test status | |
| Simulation time | 254962225056 ps |
| CPU time | 11896.6 seconds |
| Started | Aug 24 11:40:11 AM UTC 24 |
| Finished | Aug 24 03:00:31 PM UTC 24 |
| Peak memory | 629820 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/default/simv +en_scb=0 +sw_test_timeout_ns=300_000_000 +sw_build_device=s im_dv +sw_images=alert_handler_reverse_ping_in_deep_sleep_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2293328563 -assert nopostproc +UVM_TESTNAME=chip_base_test +U VM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgre y_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_alert_handler_reverse_ping_in_deep_sleep.2293328563 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/1.chip_sw_alert_handler_reverse_ping_in_deep_sleep/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_alert_test.2811185708 |
| Short name | T88 |
| Test name | |
| Test status | |
| Simulation time | 3536391104 ps |
| CPU time | 180.35 seconds |
| Started | Aug 24 11:37:56 AM UTC 24 |
| Finished | Aug 24 11:41:00 AM UTC 24 |
| Peak memory | 626612 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=alert_test:1:new_rules,te st_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_rand om_seed=2811185708 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert - cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_aler t_test.2811185708 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/1.chip_sw_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_aon_timer_irq.335564149 |
| Short name | T384 |
| Test name | |
| Test status | |
| Simulation time | 3292427184 ps |
| CPU time | 241.1 seconds |
| Started | Aug 24 11:31:09 AM UTC 24 |
| Finished | Aug 24 11:35:13 AM UTC 24 |
| Peak memory | 626688 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_i mages=aon_timer_irq_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp aces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=335564149 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm _log /dev/null -cm_name 1.chip_sw_aon_timer_irq.335564149 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/1.chip_sw_aon_timer_irq/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_aon_timer_sleep_wdog_sleep_pause.662327087 |
| Short name | T968 |
| Test name | |
| Test status | |
| Simulation time | 8255505872 ps |
| CPU time | 377.4 seconds |
| Started | Aug 24 11:31:09 AM UTC 24 |
| Finished | Aug 24 11:37:32 AM UTC 24 |
| Peak memory | 626680 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_i mages=aon_timer_sleep_wdog_sleep_pause_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu e -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=662327087 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_ base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover age/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_aon_timer_sleep_wdog_sleep_pause.662327087 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/1.chip_sw_aon_timer_sleep_wdog_sleep_pause/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_aon_timer_smoketest.2809223165 |
| Short name | T1050 |
| Test name | |
| Test status | |
| Simulation time | 2958492600 ps |
| CPU time | 202.95 seconds |
| Started | Aug 24 12:38:29 PM UTC 24 |
| Finished | Aug 24 12:41:55 PM UTC 24 |
| Peak memory | 624772 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=aon_timer_smoketest:1:new _rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2809223165 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.chi p_sw_aon_timer_smoketest.2809223165 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/1.chip_sw_aon_timer_smoketest/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_aon_timer_wdog_bite_reset.3301035544 |
| Short name | T978 |
| Test name | |
| Test status | |
| Simulation time | 7289094640 ps |
| CPU time | 661.41 seconds |
| Started | Aug 24 11:32:10 AM UTC 24 |
| Finished | Aug 24 11:43:20 AM UTC 24 |
| Peak memory | 626920 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_i mages=aon_timer_wdog_bite_reset_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3301035544 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/de fault.vdb -cm_log /dev/null -cm_name 1.chip_sw_aon_timer_wdog_bite_reset.3301035544 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/1.chip_sw_aon_timer_wdog_bite_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_aon_timer_wdog_lc_escalate.1333816226 |
| Short name | T972 |
| Test name | |
| Test status | |
| Simulation time | 6165096694 ps |
| CPU time | 399.53 seconds |
| Started | Aug 24 11:32:47 AM UTC 24 |
| Finished | Aug 24 11:39:31 AM UTC 24 |
| Peak memory | 626888 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_i mages=aon_timer_wdog_lc_escalate_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1333816226 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 1.chip_sw_aon_timer_wdog_lc_escalate.1333816226 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/1.chip_sw_aon_timer_wdog_lc_escalate/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_ast_clk_outputs.4013999656 |
| Short name | T1032 |
| Test name | |
| Test status | |
| Simulation time | 8667432750 ps |
| CPU time | 617.28 seconds |
| Started | Aug 24 12:16:33 PM UTC 24 |
| Finished | Aug 24 12:26:58 PM UTC 24 |
| Peak memory | 632832 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/default/simv +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=ast_ clk_outs_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/h w/dv/tools/sim.tcl +ntb_random_seed=4013999656 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_ast_clk_outputs_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -c m_log /dev/null -cm_name 1.chip_sw_ast_clk_outputs.4013999656 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/1.chip_sw_ast_clk_outputs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_ast_clk_rst_inputs.171623675 |
| Short name | T143 |
| Test name | |
| Test status | |
| Simulation time | 20830585044 ps |
| CPU time | 2367.13 seconds |
| Started | Aug 24 12:27:53 PM UTC 24 |
| Finished | Aug 24 01:07:46 PM UTC 24 |
| Peak memory | 629932 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=200_000_000 +sw_build_device=sim_dv +sw_ images=ast_clk_rst_inputs:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works paces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=171623675 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_ast_clk_rst_inputs _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/ default.vdb -cm_log /dev/null -cm_name 1.chip_sw_ast_clk_rst_inputs.171623675 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/1.chip_sw_ast_clk_rst_inputs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_clkmgr_external_clk_src_for_lc.647815209 |
| Short name | T1026 |
| Test name | |
| Test status | |
| Simulation time | 9494208238 ps |
| CPU time | 688.51 seconds |
| Started | Aug 24 12:10:31 PM UTC 24 |
| Finished | Aug 24 12:22:08 PM UTC 24 |
| Peak memory | 639736 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/default/simv +chip_clock_source=ChipClockSourceExternal48Mhz +sw_build_de vice=sim_dv +sw_images=clkmgr_external_clk_src_for_lc_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=647815209 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TE ST_SEQ=chip_sw_lc_ctrl_transition_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/chi p_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_clkmgr_external_clk_src_for_lc.647815209 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/1.chip_sw_clkmgr_external_clk_src_for_lc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_clkmgr_external_clk_src_for_sw_fast_dev.1756270586 |
| Short name | T1022 |
| Test name | |
| Test status | |
| Simulation time | 4959345818 ps |
| CPU time | 476.35 seconds |
| Started | Aug 24 12:10:50 PM UTC 24 |
| Finished | Aug 24 12:18:53 PM UTC 24 |
| Peak memory | 626616 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/default/simv +chip_clock_source=ChipClockSourceExternal96Mhz +calibrate_u sb_clk=1 +src_dec_state=DecLcStDev +sw_build_device=sim_dv +sw_images=clkmgr_external_clk_src_for_sw_fast_test:1:new_rules,test_rom:0 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1756270586 -a ssert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces /repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_clkmgr_external_clk_sr c_for_sw_fast_dev.1756270586 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/1.chip_sw_clkmgr_external_clk_src_for_sw_fast_dev/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_clkmgr_external_clk_src_for_sw_fast_rma.3638042408 |
| Short name | T1023 |
| Test name | |
| Test status | |
| Simulation time | 3712514698 ps |
| CPU time | 442.77 seconds |
| Started | Aug 24 12:11:27 PM UTC 24 |
| Finished | Aug 24 12:18:55 PM UTC 24 |
| Peak memory | 628604 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/default/simv +chip_clock_source=ChipClockSourceExternal96Mhz +calibrate_u sb_clk=1 +src_dec_state=DecLcStRma +sw_build_device=sim_dv +sw_images=clkmgr_external_clk_src_for_sw_fast_test:1:new_rules,test_rom:0 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3638042408 -a ssert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces /repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_clkmgr_external_clk_sr c_for_sw_fast_rma.3638042408 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/1.chip_sw_clkmgr_external_clk_src_for_sw_fast_rma/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0.898983582 |
| Short name | T1017 |
| Test name | |
| Test status | |
| Simulation time | 4181299998 ps |
| CPU time | 417.65 seconds |
| Started | Aug 24 12:10:31 PM UTC 24 |
| Finished | Aug 24 12:17:34 PM UTC 24 |
| Peak memory | 628756 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/default/simv +chip_clock_source=ChipClockSourceExternal96Mhz +calibrate_u sb_clk=1 +src_dec_state=DecLcStTestUnlocked0 +sw_build_device=sim_dv +sw_images=clkmgr_external_clk_src_for_sw_fast_test:1:new_rules,test_rom:0 +c dc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=898 983582 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_clkmgr_extern al_clk_src_for_sw_fast_test_unlocked0.898983582 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/1.chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_clkmgr_external_clk_src_for_sw_slow_dev.2922649726 |
| Short name | T1019 |
| Test name | |
| Test status | |
| Simulation time | 4545878720 ps |
| CPU time | 404.93 seconds |
| Started | Aug 24 12:11:00 PM UTC 24 |
| Finished | Aug 24 12:17:50 PM UTC 24 |
| Peak memory | 628748 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/default/simv +chip_clock_source=ChipClockSourceExternal48Mhz +calibrate_u sb_clk=1 +src_dec_state=DecLcStDev +sw_build_device=sim_dv +sw_images=clkmgr_external_clk_src_for_sw_slow_test:1:new_rules,test_rom:0 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2922649726 -a ssert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces /repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_clkmgr_external_clk_sr c_for_sw_slow_dev.2922649726 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/1.chip_sw_clkmgr_external_clk_src_for_sw_slow_dev/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_clkmgr_external_clk_src_for_sw_slow_rma.4199195264 |
| Short name | T1024 |
| Test name | |
| Test status | |
| Simulation time | 4763342184 ps |
| CPU time | 448.43 seconds |
| Started | Aug 24 12:11:49 PM UTC 24 |
| Finished | Aug 24 12:19:23 PM UTC 24 |
| Peak memory | 626936 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/default/simv +chip_clock_source=ChipClockSourceExternal48Mhz +calibrate_u sb_clk=1 +src_dec_state=DecLcStRma +sw_build_device=sim_dv +sw_images=clkmgr_external_clk_src_for_sw_slow_test:1:new_rules,test_rom:0 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4199195264 -a ssert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces /repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_clkmgr_external_clk_sr c_for_sw_slow_rma.4199195264 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/1.chip_sw_clkmgr_external_clk_src_for_sw_slow_rma/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0.1874658803 |
| Short name | T1018 |
| Test name | |
| Test status | |
| Simulation time | 4318867818 ps |
| CPU time | 405.18 seconds |
| Started | Aug 24 12:10:50 PM UTC 24 |
| Finished | Aug 24 12:17:41 PM UTC 24 |
| Peak memory | 628700 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/default/simv +chip_clock_source=ChipClockSourceExternal48Mhz +calibrate_u sb_clk=1 +src_dec_state=DecLcStTestUnlocked0 +sw_build_device=sim_dv +sw_images=clkmgr_external_clk_src_for_sw_slow_test:1:new_rules,test_rom:0 +c dc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=187 4658803 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_clkmgr_exter nal_clk_src_for_sw_slow_test_unlocked0.1874658803 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/1.chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_clkmgr_jitter.1588584161 |
| Short name | T1021 |
| Test name | |
| Test status | |
| Simulation time | 2857972485 ps |
| CPU time | 188.52 seconds |
| Started | Aug 24 12:15:09 PM UTC 24 |
| Finished | Aug 24 12:18:21 PM UTC 24 |
| Peak memory | 624568 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=clkmgr_jitter_test:1:new_ rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl + ntb_random_seed=1588584161 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip _sw_clkmgr_jitter.1588584161 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/1.chip_sw_clkmgr_jitter/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_clkmgr_jitter_frequency.503477735 |
| Short name | T1020 |
| Test name | |
| Test status | |
| Simulation time | 2921166544 ps |
| CPU time | 300.69 seconds |
| Started | Aug 24 12:13:06 PM UTC 24 |
| Finished | Aug 24 12:18:11 PM UTC 24 |
| Peak memory | 624580 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=clkmgr_jitter_frequency_t est:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools /sim.tcl +ntb_random_seed=503477735 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tg l+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_na me 1.chip_sw_clkmgr_jitter_frequency.503477735 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/1.chip_sw_clkmgr_jitter_frequency/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_clkmgr_jitter_reduced_freq.3547534109 |
| Short name | T1033 |
| Test name | |
| Test status | |
| Simulation time | 2873321224 ps |
| CPU time | 149.49 seconds |
| Started | Aug 24 12:24:40 PM UTC 24 |
| Finished | Aug 24 12:27:12 PM UTC 24 |
| Peak memory | 624680 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/default/simv +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +sw_images=clkm gr_jitter_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/ hw/dv/tools/sim.tcl +ntb_random_seed=3547534109 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev /null -cm_name 1.chip_sw_clkmgr_jitter_reduced_freq.3547534109 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/1.chip_sw_clkmgr_jitter_reduced_freq/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_clkmgr_off_aes_trans.3227682820 |
| Short name | T1012 |
| Test name | |
| Test status | |
| Simulation time | 5015934028 ps |
| CPU time | 369.3 seconds |
| Started | Aug 24 12:08:55 PM UTC 24 |
| Finished | Aug 24 12:15:09 PM UTC 24 |
| Peak memory | 626876 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=clkmgr_off_aes_trans_test :1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/si m.tcl +ntb_random_seed=3227682820 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_clkmgr_off_aes_trans.3227682820 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/1.chip_sw_clkmgr_off_aes_trans/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_clkmgr_off_hmac_trans.145402811 |
| Short name | T1013 |
| Test name | |
| Test status | |
| Simulation time | 5907420600 ps |
| CPU time | 370.07 seconds |
| Started | Aug 24 12:08:56 PM UTC 24 |
| Finished | Aug 24 12:15:11 PM UTC 24 |
| Peak memory | 625140 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=clkmgr_off_hmac_trans_tes t:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/s im.tcl +ntb_random_seed=145402811 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_clkmgr_off_hmac_trans.145402811 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/1.chip_sw_clkmgr_off_hmac_trans/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_clkmgr_off_kmac_trans.3143763502 |
| Short name | T1015 |
| Test name | |
| Test status | |
| Simulation time | 5471863960 ps |
| CPU time | 399.28 seconds |
| Started | Aug 24 12:09:18 PM UTC 24 |
| Finished | Aug 24 12:16:03 PM UTC 24 |
| Peak memory | 626848 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=clkmgr_off_kmac_trans_tes t:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/s im.tcl +ntb_random_seed=3143763502 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam e 1.chip_sw_clkmgr_off_kmac_trans.3143763502 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/1.chip_sw_clkmgr_off_kmac_trans/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_clkmgr_off_otbn_trans.4007299724 |
| Short name | T1011 |
| Test name | |
| Test status | |
| Simulation time | 3779486100 ps |
| CPU time | 294.16 seconds |
| Started | Aug 24 12:09:47 PM UTC 24 |
| Finished | Aug 24 12:14:45 PM UTC 24 |
| Peak memory | 624572 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=clkmgr_off_otbn_trans_tes t:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/s im.tcl +ntb_random_seed=4007299724 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam e 1.chip_sw_clkmgr_off_otbn_trans.4007299724 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/1.chip_sw_clkmgr_off_otbn_trans/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_clkmgr_off_peri.3594369442 |
| Short name | T1025 |
| Test name | |
| Test status | |
| Simulation time | 8282988134 ps |
| CPU time | 692.43 seconds |
| Started | Aug 24 12:08:55 PM UTC 24 |
| Finished | Aug 24 12:20:36 PM UTC 24 |
| Peak memory | 626944 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=30_000_000 +sw_build_device=sim_dv +sw_i mages=clkmgr_off_peri_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3594369442 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_clkmgr_off_peri.3594369442 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/1.chip_sw_clkmgr_off_peri/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_clkmgr_reset_frequency.3232413672 |
| Short name | T1016 |
| Test name | |
| Test status | |
| Simulation time | 3056705894 ps |
| CPU time | 281.52 seconds |
| Started | Aug 24 12:12:26 PM UTC 24 |
| Finished | Aug 24 12:17:11 PM UTC 24 |
| Peak memory | 624580 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/default/simv +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=clkm gr_reset_frequency_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3232413672 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm _log /dev/null -cm_name 1.chip_sw_clkmgr_reset_frequency.3232413672 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/1.chip_sw_clkmgr_reset_frequency/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_clkmgr_sleep_frequency.3914011925 |
| Short name | T1027 |
| Test name | |
| Test status | |
| Simulation time | 4972149172 ps |
| CPU time | 433.81 seconds |
| Started | Aug 24 12:15:33 PM UTC 24 |
| Finished | Aug 24 12:22:53 PM UTC 24 |
| Peak memory | 626752 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/default/simv +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=clkm gr_sleep_frequency_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3914011925 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm _log /dev/null -cm_name 1.chip_sw_clkmgr_sleep_frequency.3914011925 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/1.chip_sw_clkmgr_sleep_frequency/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_clkmgr_smoketest.667281754 |
| Short name | T1048 |
| Test name | |
| Test status | |
| Simulation time | 2887464940 ps |
| CPU time | 196.7 seconds |
| Started | Aug 24 12:38:28 PM UTC 24 |
| Finished | Aug 24 12:41:48 PM UTC 24 |
| Peak memory | 624564 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=clkmgr_smoketest:1:new_ru les,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +nt b_random_seed=667281754 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw _clkmgr_smoketest.667281754 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/1.chip_sw_clkmgr_smoketest/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_csrng_edn_concurrency.921661037 |
| Short name | T1053 |
| Test name | |
| Test status | |
| Simulation time | 18172256068 ps |
| CPU time | 3591.17 seconds |
| Started | Aug 24 11:44:42 AM UTC 24 |
| Finished | Aug 24 12:45:13 PM UTC 24 |
| Peak memory | 629800 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=140_000_000 +rng_srate_value_min=15 +rng _srate_value_max=20 +accelerate_cold_power_up_time=3 +accelerate_regulators_power_up_time=2 +sw_build_device=sim_dv +sw_images=csrng_edn_concurren cy_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/t ools/sim.tcl +ntb_random_seed=921661037 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -c m_name 1.chip_sw_csrng_edn_concurrency.921661037 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/1.chip_sw_csrng_edn_concurrency/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_csrng_edn_concurrency_reduced_freq.1541720035 |
| Short name | T1135 |
| Test name | |
| Test status | |
| Simulation time | 31912503205 ps |
| CPU time | 4549.45 seconds |
| Started | Aug 24 12:27:35 PM UTC 24 |
| Finished | Aug 24 01:44:13 PM UTC 24 |
| Peak memory | 627752 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=360_000_000 +rng_srate_value_min=15 +rng _srate_value_max=20 +cal_sys_clk_70mhz=1 +en_jitter=1 +accelerate_cold_power_up_time=3 +accelerate_regulators_power_up_time=2 +sw_build_device=sim _dv +sw_images=csrng_edn_concurrency_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1541720035 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_b ase_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/covera ge/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_csrng_edn_concurrency_reduced_freq.1541720035 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/1.chip_sw_csrng_edn_concurrency_reduced_freq/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_csrng_fuse_en_sw_app_read_test.1888008810 |
| Short name | T989 |
| Test name | |
| Test status | |
| Simulation time | 5375595300 ps |
| CPU time | 400.14 seconds |
| Started | Aug 24 11:45:18 AM UTC 24 |
| Finished | Aug 24 11:52:03 AM UTC 24 |
| Peak memory | 626612 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=15_000_000 +sw_build_device=sim_dv +sw_i mages=csrng_fuse_en_sw_app_read:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1888008810 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_entropy_src _fuse_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cove rage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_csrng_fuse_en_sw_app_read_test.1888008810 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/1.chip_sw_csrng_fuse_en_sw_app_read_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_csrng_kat_test.3250366919 |
| Short name | T986 |
| Test name | |
| Test status | |
| Simulation time | 3527012304 ps |
| CPU time | 232.89 seconds |
| Started | Aug 24 11:45:04 AM UTC 24 |
| Finished | Aug 24 11:49:00 AM UTC 24 |
| Peak memory | 626872 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_i mages=csrng_kat_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces /repo/hw/dv/tools/sim.tcl +ntb_random_seed=3250366919 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_lo g /dev/null -cm_name 1.chip_sw_csrng_kat_test.3250366919 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/1.chip_sw_csrng_kat_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_csrng_lc_hw_debug_en_test.3225219493 |
| Short name | T988 |
| Test name | |
| Test status | |
| Simulation time | 6347025576 ps |
| CPU time | 415.43 seconds |
| Started | Aug 24 11:44:30 AM UTC 24 |
| Finished | Aug 24 11:51:30 AM UTC 24 |
| Peak memory | 626948 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=15_000_000 +rng_srate_value_min=15 +use_ otp_image=OtpTypeLcStTestUnlocked0 +sw_build_device=sim_dv +sw_images=csrng_lc_hw_debug_en_test:1:new_rules,test_rom:0 +cdc_instrumentation_enable d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3225219493 -assert nopostpro c +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_csrng_lc_hw_debug_en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r epo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_csrng_lc_hw_debug_en_test.3225219493 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/1.chip_sw_csrng_lc_hw_debug_en_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_csrng_smoketest.2109424067 |
| Short name | T1049 |
| Test name | |
| Test status | |
| Simulation time | 2943396860 ps |
| CPU time | 144.23 seconds |
| Started | Aug 24 12:39:28 PM UTC 24 |
| Finished | Aug 24 12:41:55 PM UTC 24 |
| Peak memory | 624888 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=csrng_smoketest:1:new_rul es,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb _random_seed=2109424067 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw _csrng_smoketest.2109424067 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/1.chip_sw_csrng_smoketest/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_data_integrity_escalation.1201015906 |
| Short name | T282 |
| Test name | |
| Test status | |
| Simulation time | 5059089720 ps |
| CPU time | 515.12 seconds |
| Started | Aug 24 10:56:18 AM UTC 24 |
| Finished | Aug 24 11:04:59 AM UTC 24 |
| Peak memory | 626696 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv + sw_images=data_integrity_escalation_reset_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1201015906 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip _sw_data_integrity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_data_integrity_escalation.1201015906 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/1.chip_sw_data_integrity_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_edn_auto_mode.379911865 |
| Short name | T453 |
| Test name | |
| Test status | |
| Simulation time | 5647025310 ps |
| CPU time | 961.36 seconds |
| Started | Aug 24 11:42:28 AM UTC 24 |
| Finished | Aug 24 11:58:40 AM UTC 24 |
| Peak memory | 624692 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=18_000_000 +rng_srate_value=5 +accelerat e_cold_power_up_time=3 +accelerate_regulators_power_up_time=2 +sw_build_device=sim_dv +sw_images=edn_auto_mode:1:new_rules,test_rom:0 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=379911865 -as sert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/rep o/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_edn_auto_mode.379911865 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/1.chip_sw_edn_auto_mode/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_edn_boot_mode.308790294 |
| Short name | T451 |
| Test name | |
| Test status | |
| Simulation time | 3348725090 ps |
| CPU time | 394.2 seconds |
| Started | Aug 24 11:43:08 AM UTC 24 |
| Finished | Aug 24 11:49:47 AM UTC 24 |
| Peak memory | 624948 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=18_000_000 +rng_srate_value=5 +accelerat e_cold_power_up_time=3 +accelerate_regulators_power_up_time=2 +sw_build_device=sim_dv +sw_images=edn_boot_mode:1:new_rules,test_rom:0 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=308790294 -as sert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/rep o/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_edn_boot_mode.308790294 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/1.chip_sw_edn_boot_mode/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_edn_entropy_reqs.1142928526 |
| Short name | T995 |
| Test name | |
| Test status | |
| Simulation time | 6773573440 ps |
| CPU time | 600.12 seconds |
| Started | Aug 24 11:46:29 AM UTC 24 |
| Finished | Aug 24 11:56:37 AM UTC 24 |
| Peak memory | 626740 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=15000000 +rng_srate_value_min=15 +rng_sr ate_value_max=30 +sw_build_device=sim_dv +sw_images=entropy_src_edn_reqs_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1142928526 -assert nopostproc +UVM_TESTNAME=ch ip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_ 22/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_edn_entropy_reqs.1142928526 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/1.chip_sw_edn_entropy_reqs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_edn_entropy_reqs_jitter.3374126954 |
| Short name | T999 |
| Test name | |
| Test status | |
| Simulation time | 7305727188 ps |
| CPU time | 785.33 seconds |
| Started | Aug 24 11:47:02 AM UTC 24 |
| Finished | Aug 24 12:00:17 PM UTC 24 |
| Peak memory | 626744 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=15000000 +rng_srate_value_min=15 +rng_sr ate_value_max=30 +en_jitter=1 +sw_build_device=sim_dv +sw_images=entropy_src_edn_reqs_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3374126954 -assert nopostproc +UV M_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_edn_entropy_reqs_jitter.3374126954 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/1.chip_sw_edn_entropy_reqs_jitter/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_edn_kat.758230230 |
| Short name | T987 |
| Test name | |
| Test status | |
| Simulation time | 3291522206 ps |
| CPU time | 435.86 seconds |
| Started | Aug 24 11:43:44 AM UTC 24 |
| Finished | Aug 24 11:51:05 AM UTC 24 |
| Peak memory | 632772 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=18_000_000 +rng_srate_value=5 +disable_a ssert_edn_output_diff_from_prev=1 +accelerate_cold_power_up_time=3 +accelerate_regulators_power_up_time=2 +sw_build_device=sim_dv +sw_images=edn_k at:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/ sim.tcl +ntb_random_seed=758230230 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam e 1.chip_sw_edn_kat.758230230 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/1.chip_sw_edn_kat/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_edn_sw_mode.1630830944 |
| Short name | T1008 |
| Test name | |
| Test status | |
| Simulation time | 10604347920 ps |
| CPU time | 1538.39 seconds |
| Started | Aug 24 11:44:09 AM UTC 24 |
| Finished | Aug 24 12:10:05 PM UTC 24 |
| Peak memory | 627104 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_i mages=edn_sw_mode:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/re po/hw/dv/tools/sim.tcl +ntb_random_seed=1630830944 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 1.chip_sw_edn_sw_mode.1630830944 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/1.chip_sw_edn_sw_mode/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_entropy_src_ast_rng_req.775278674 |
| Short name | T985 |
| Test name | |
| Test status | |
| Simulation time | 3145551952 ps |
| CPU time | 139.37 seconds |
| Started | Aug 24 11:45:49 AM UTC 24 |
| Finished | Aug 24 11:48:11 AM UTC 24 |
| Peak memory | 624744 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=15_000_000 +sw_build_device=sim_dv +sw_i mages=entropy_src_ast_rng_req_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli - do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=775278674 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 1.chip_sw_entropy_src_ast_rng_req.775278674 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/1.chip_sw_entropy_src_ast_rng_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_entropy_src_csrng.3428391475 |
| Short name | T347 |
| Test name | |
| Test status | |
| Simulation time | 7439290660 ps |
| CPU time | 1187.7 seconds |
| Started | Aug 24 11:45:50 AM UTC 24 |
| Finished | Aug 24 12:05:51 PM UTC 24 |
| Peak memory | 624704 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=50_000_000 +rng_srate_value_min=15 +rng_ srate_value_max=30 +sw_build_device=sim_dv +sw_images=entropy_src_csrng_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3428391475 -assert nopostproc +UVM_TESTNAME=chi p_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_2 2/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_entropy_src_csrng.3428391475 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/1.chip_sw_entropy_src_csrng/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_entropy_src_kat_test.2256728515 |
| Short name | T979 |
| Test name | |
| Test status | |
| Simulation time | 2001307256 ps |
| CPU time | 139.3 seconds |
| Started | Aug 24 11:41:23 AM UTC 24 |
| Finished | Aug 24 11:43:45 AM UTC 24 |
| Peak memory | 624496 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_i mages=entropy_src_kat_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2256728515 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_entropy_src_kat_test.2256728515 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/1.chip_sw_entropy_src_kat_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_entropy_src_smoketest.578741299 |
| Short name | T1057 |
| Test name | |
| Test status | |
| Simulation time | 3447710792 ps |
| CPU time | 290.15 seconds |
| Started | Aug 24 12:41:32 PM UTC 24 |
| Finished | Aug 24 12:46:26 PM UTC 24 |
| Peak memory | 624824 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/default/simv +rng_srate_value_min=15 +rng_srate_value_max=30 +sw_build_de vice=sim_dv +sw_images=entropy_src_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=578741299 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw _base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cove rage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_entropy_src_smoketest.578741299 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/1.chip_sw_entropy_src_smoketest/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_example_concurrency.3493507714 |
| Short name | T928 |
| Test name | |
| Test status | |
| Simulation time | 2552675720 ps |
| CPU time | 149.91 seconds |
| Started | Aug 24 10:54:44 AM UTC 24 |
| Finished | Aug 24 10:57:17 AM UTC 24 |
| Peak memory | 624820 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=example_concurrency_test: 1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim .tcl +ntb_random_seed=3493507714 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_example_concurrency.3493507714 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/1.chip_sw_example_concurrency/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_example_flash.610206834 |
| Short name | T929 |
| Test name | |
| Test status | |
| Simulation time | 2718217800 ps |
| CPU time | 202.01 seconds |
| Started | Aug 24 10:53:57 AM UTC 24 |
| Finished | Aug 24 10:57:22 AM UTC 24 |
| Peak memory | 624748 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=example_test_from_flash:1 :new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim. tcl +ntb_random_seed=610206834 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1. chip_sw_example_flash.610206834 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/1.chip_sw_example_flash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_example_manufacturer.4132651229 |
| Short name | T931 |
| Test name | |
| Test status | |
| Simulation time | 3585424520 ps |
| CPU time | 200.8 seconds |
| Started | Aug 24 10:54:18 AM UTC 24 |
| Finished | Aug 24 10:57:42 AM UTC 24 |
| Peak memory | 624796 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=example_test:1:new_rules, test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=4132651229 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_ex ample_manufacturer.4132651229 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/1.chip_sw_example_manufacturer/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_example_rom.4292908690 |
| Short name | T923 |
| Test name | |
| Test status | |
| Simulation time | 3034687040 ps |
| CPU time | 101.35 seconds |
| Started | Aug 24 10:53:55 AM UTC 24 |
| Finished | Aug 24 10:55:39 AM UTC 24 |
| Peak memory | 624624 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=example_test_from_rom:0:t est_in_rom:new_rules +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.t cl +ntb_random_seed=4292908690 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1. chip_sw_example_rom.4292908690 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/1.chip_sw_example_rom/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_exit_test_unlocked_bootstrap.3464088595 |
| Short name | T1137 |
| Test name | |
| Test status | |
| Simulation time | 58629726184 ps |
| CPU time | 9946.48 seconds |
| Started | Aug 24 10:58:10 AM UTC 24 |
| Finished | Aug 24 01:45:40 PM UTC 24 |
| Peak memory | 644192 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/default/simv +flash_program_latency=5 +sw_test_timeout_ns=150_000_000 +sw _build_device=sim_dv +sw_images=exit_test_unlocked_bootstrap:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY =UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3464088595 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM _TEST_SEQ=chip_sw_exit_test_unlocked_bootstrap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_exit_test_unlocked_bootstrap.3464088595 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/1.chip_sw_exit_test_unlocked_bootstrap/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_flash_crash_alert.46126350 |
| Short name | T660 |
| Test name | |
| Test status | |
| Simulation time | 4333565160 ps |
| CPU time | 366.55 seconds |
| Started | Aug 24 12:24:07 PM UTC 24 |
| Finished | Aug 24 12:30:18 PM UTC 24 |
| Peak memory | 627088 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/default/simv +test_timeout_ns=8_000_000 +bypass_alert_ready_to_end_check= 1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=46126350 -assert nopostproc +UVM_TESTNAME=chip_base_test +UV M_TEST_SEQ=chip_sw_flash_host_gnt_err_inj_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 8_22/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_flash_crash_alert.46126350 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/1.chip_sw_flash_crash_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_flash_ctrl_access.2292674388 |
| Short name | T943 |
| Test name | |
| Test status | |
| Simulation time | 5478015732 ps |
| CPU time | 652.43 seconds |
| Started | Aug 24 11:06:33 AM UTC 24 |
| Finished | Aug 24 11:17:33 AM UTC 24 |
| Peak memory | 624708 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=flash_ctrl_test:1:new_rul es,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb _random_seed=2292674388 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw _flash_ctrl_access.2292674388 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/1.chip_sw_flash_ctrl_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_flash_ctrl_access_jitter_en.1953373195 |
| Short name | T945 |
| Test name | |
| Test status | |
| Simulation time | 5915535307 ps |
| CPU time | 710.91 seconds |
| Started | Aug 24 11:06:33 AM UTC 24 |
| Finished | Aug 24 11:18:32 AM UTC 24 |
| Peak memory | 624800 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/default/simv +en_jitter=1 +sw_build_device=sim_dv +sw_images=flash_ctrl_t est:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools /sim.tcl +ntb_random_seed=1953373195 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_n ame 1.chip_sw_flash_ctrl_access_jitter_en.1953373195 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/1.chip_sw_flash_ctrl_access_jitter_en/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_flash_ctrl_access_jitter_en_reduced_freq.3962254913 |
| Short name | T1043 |
| Test name | |
| Test status | |
| Simulation time | 7748211751 ps |
| CPU time | 727.98 seconds |
| Started | Aug 24 12:25:18 PM UTC 24 |
| Finished | Aug 24 12:37:34 PM UTC 24 |
| Peak memory | 624568 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/default/simv +en_jitter=1 +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +s w_images=flash_ctrl_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp aces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3962254913 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -c m_log /dev/null -cm_name 1.chip_sw_flash_ctrl_access_jitter_en_reduced_freq.3962254913 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/1.chip_sw_flash_ctrl_access_jitter_en_reduced_freq/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_flash_ctrl_clock_freqs.663467015 |
| Short name | T949 |
| Test name | |
| Test status | |
| Simulation time | 5544454778 ps |
| CPU time | 712.47 seconds |
| Started | Aug 24 11:09:32 AM UTC 24 |
| Finished | Aug 24 11:21:33 AM UTC 24 |
| Peak memory | 625088 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=flash_ctrl_clock_freqs_te st:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/ sim.tcl +ntb_random_seed=663467015 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam e 1.chip_sw_flash_ctrl_clock_freqs.663467015 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/1.chip_sw_flash_ctrl_clock_freqs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_flash_ctrl_idle_low_power.2951065876 |
| Short name | T383 |
| Test name | |
| Test status | |
| Simulation time | 3646500460 ps |
| CPU time | 264.12 seconds |
| Started | Aug 24 11:06:49 AM UTC 24 |
| Finished | Aug 24 11:11:17 AM UTC 24 |
| Peak memory | 627012 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=flash_ctrl_idle_low_power _test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/too ls/sim.tcl +ntb_random_seed=2951065876 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm _name 1.chip_sw_flash_ctrl_idle_low_power.2951065876 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/1.chip_sw_flash_ctrl_idle_low_power/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_flash_ctrl_lc_rw_en.1161282192 |
| Short name | T325 |
| Test name | |
| Test status | |
| Simulation time | 5204750120 ps |
| CPU time | 266.91 seconds |
| Started | Aug 24 11:05:52 AM UTC 24 |
| Finished | Aug 24 11:10:23 AM UTC 24 |
| Peak memory | 626940 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv + sw_images=flash_ctrl_lc_rw_en_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli - do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1161282192 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_flash_ct rl_lc_rw_en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vc s/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_flash_ctrl_lc_rw_en.1161282192 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/1.chip_sw_flash_ctrl_lc_rw_en/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_flash_ctrl_mem_protection.3416270692 |
| Short name | T1047 |
| Test name | |
| Test status | |
| Simulation time | 5982393822 ps |
| CPU time | 772.67 seconds |
| Started | Aug 24 12:28:40 PM UTC 24 |
| Finished | Aug 24 12:41:42 PM UTC 24 |
| Peak memory | 627096 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=flash_ctrl_mem_protection _test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/too ls/sim.tcl +ntb_random_seed=3416270692 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm _name 1.chip_sw_flash_ctrl_mem_protection.3416270692 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/1.chip_sw_flash_ctrl_mem_protection/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_flash_ctrl_ops.1083148951 |
| Short name | T938 |
| Test name | |
| Test status | |
| Simulation time | 4057613960 ps |
| CPU time | 399.09 seconds |
| Started | Aug 24 11:05:23 AM UTC 24 |
| Finished | Aug 24 11:12:07 AM UTC 24 |
| Peak memory | 626928 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=50_000_000 +sw_build_device=sim_dv +sw_i mages=flash_ctrl_ops_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works paces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1083148951 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default.vdb - cm_log /dev/null -cm_name 1.chip_sw_flash_ctrl_ops.1083148951 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/1.chip_sw_flash_ctrl_ops/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_flash_ctrl_ops_jitter_en.2927429677 |
| Short name | T370 |
| Test name | |
| Test status | |
| Simulation time | 4717498394 ps |
| CPU time | 411.92 seconds |
| Started | Aug 24 11:05:52 AM UTC 24 |
| Finished | Aug 24 11:12:50 AM UTC 24 |
| Peak memory | 624644 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=50_000_000 +en_jitter=1 +sw_build_device =sim_dv +sw_images=flash_ctrl_ops_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2927429677 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/ default.vdb -cm_log /dev/null -cm_name 1.chip_sw_flash_ctrl_ops_jitter_en.2927429677 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/1.chip_sw_flash_ctrl_ops_jitter_en/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_flash_ctrl_ops_jitter_en_reduced_freq.3044668608 |
| Short name | T1040 |
| Test name | |
| Test status | |
| Simulation time | 4690919498 ps |
| CPU time | 459.92 seconds |
| Started | Aug 24 12:25:17 PM UTC 24 |
| Finished | Aug 24 12:33:03 PM UTC 24 |
| Peak memory | 624784 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=50_000_000 +en_jitter=1 +cal_sys_clk_70m hz=1 +sw_build_device=sim_dv +sw_images=flash_ctrl_ops_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3044668608 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_ TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_a sic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_flash_ctrl_ops_jitter_en_reduced_freq.3044668608 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/1.chip_sw_flash_ctrl_ops_jitter_en_reduced_freq/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_flash_ctrl_write_clear.963856324 |
| Short name | T1034 |
| Test name | |
| Test status | |
| Simulation time | 3199393864 ps |
| CPU time | 222.33 seconds |
| Started | Aug 24 12:24:17 PM UTC 24 |
| Finished | Aug 24 12:28:03 PM UTC 24 |
| Peak memory | 624564 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/default/simv +test_timeout_ns=8_000_000 +sw_build_device=sim_dv +sw_image s=flash_ctrl_write_clear_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=963856324 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default.vd b -cm_log /dev/null -cm_name 1.chip_sw_flash_ctrl_write_clear.963856324 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/1.chip_sw_flash_ctrl_write_clear/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_flash_init.2058555120 |
| Short name | T322 |
| Test name | |
| Test status | |
| Simulation time | 24792233786 ps |
| CPU time | 1542.12 seconds |
| Started | Aug 24 11:06:50 AM UTC 24 |
| Finished | Aug 24 11:32:49 AM UTC 24 |
| Peak memory | 628928 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=25_000_000 +sw_build_device=sim_dv +sw_i mages=flash_init_test:0:test_in_rom:new_rules +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac es/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2058555120 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_flash_init_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default.vd b -cm_log /dev/null -cm_name 1.chip_sw_flash_init.2058555120 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/1.chip_sw_flash_init/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_flash_init_reduced_freq.1519242100 |
| Short name | T328 |
| Test name | |
| Test status | |
| Simulation time | 23683068055 ps |
| CPU time | 1244.89 seconds |
| Started | Aug 24 12:26:39 PM UTC 24 |
| Finished | Aug 24 12:47:38 PM UTC 24 |
| Peak memory | 629924 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=25_000_000 +cal_sys_clk_70mhz=1 +sw_buil d_device=sim_dv +sw_images=flash_init_test:0:test_in_rom:new_rules +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu e -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1519242100 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw _flash_init_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vc s/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_flash_init_reduced_freq.1519242100 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/1.chip_sw_flash_init_reduced_freq/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_flash_scrambling_smoketest.3073760215 |
| Short name | T1039 |
| Test name | |
| Test status | |
| Simulation time | 2552976712 ps |
| CPU time | 164.24 seconds |
| Started | Aug 24 12:28:41 PM UTC 24 |
| Finished | Aug 24 12:31:28 PM UTC 24 |
| Peak memory | 624824 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/default/simv +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_ima ges=flash_scrambling_smoketest:1:new_rules,flash_scrambling_smoketest_otp_img_rma:4,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3073760215 -assert nopostproc +UVM_TESTNAME=chip_bas e_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/chi p_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_flash_scrambling_smoketest.3073760215 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/1.chip_sw_flash_scrambling_smoketest/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_gpio_smoketest.3457212690 |
| Short name | T1054 |
| Test name | |
| Test status | |
| Simulation time | 3083290918 ps |
| CPU time | 181.65 seconds |
| Started | Aug 24 12:42:34 PM UTC 24 |
| Finished | Aug 24 12:45:39 PM UTC 24 |
| Peak memory | 624820 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=gpio_smoketest:1:new_rule s,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ random_seed=3457212690 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.ch ip_sw_gpio_smoketest.3457212690 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/1.chip_sw_gpio_smoketest/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_hmac_enc.2070507535 |
| Short name | T991 |
| Test name | |
| Test status | |
| Simulation time | 3656219514 ps |
| CPU time | 259.66 seconds |
| Started | Aug 24 11:48:35 AM UTC 24 |
| Finished | Aug 24 11:52:59 AM UTC 24 |
| Peak memory | 624564 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=hmac_enc_test:1:new_rules ,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_r andom_seed=2070507535 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_h mac_enc.2070507535 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/1.chip_sw_hmac_enc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_hmac_enc_idle.1709908520 |
| Short name | T992 |
| Test name | |
| Test status | |
| Simulation time | 3243201400 ps |
| CPU time | 168.05 seconds |
| Started | Aug 24 11:50:11 AM UTC 24 |
| Finished | Aug 24 11:53:02 AM UTC 24 |
| Peak memory | 624572 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=hmac_enc_idle_test:1:new_ rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl + ntb_random_seed=1709908520 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip _sw_hmac_enc_idle.1709908520 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/1.chip_sw_hmac_enc_idle/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_hmac_enc_jitter_en.2616918908 |
| Short name | T990 |
| Test name | |
| Test status | |
| Simulation time | 2329764728 ps |
| CPU time | 173.9 seconds |
| Started | Aug 24 11:49:24 AM UTC 24 |
| Finished | Aug 24 11:52:21 AM UTC 24 |
| Peak memory | 626612 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/default/simv +en_jitter=1 +sw_build_device=sim_dv +sw_images=hmac_enc_tes t:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/s im.tcl +ntb_random_seed=2616918908 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam e 1.chip_sw_hmac_enc_jitter_en.2616918908 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/1.chip_sw_hmac_enc_jitter_en/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_hmac_enc_jitter_en_reduced_freq.1321867003 |
| Short name | T1036 |
| Test name | |
| Test status | |
| Simulation time | 2923101874 ps |
| CPU time | 167.72 seconds |
| Started | Aug 24 12:26:20 PM UTC 24 |
| Finished | Aug 24 12:29:11 PM UTC 24 |
| Peak memory | 626864 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/default/simv +en_jitter=1 +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +s w_images=hmac_enc_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac es/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1321867003 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_ log /dev/null -cm_name 1.chip_sw_hmac_enc_jitter_en_reduced_freq.1321867003 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/1.chip_sw_hmac_enc_jitter_en_reduced_freq/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_hmac_multistream.3375738606 |
| Short name | T1007 |
| Test name | |
| Test status | |
| Simulation time | 7969905204 ps |
| CPU time | 1097.64 seconds |
| Started | Aug 24 11:51:29 AM UTC 24 |
| Finished | Aug 24 12:10:00 PM UTC 24 |
| Peak memory | 626752 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=hmac_multistream_functest :1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/si m.tcl +ntb_random_seed=3375738606 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_hmac_multistream.3375738606 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/1.chip_sw_hmac_multistream/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_hmac_oneshot.2759989589 |
| Short name | T994 |
| Test name | |
| Test status | |
| Simulation time | 3678693072 ps |
| CPU time | 242.07 seconds |
| Started | Aug 24 11:51:06 AM UTC 24 |
| Finished | Aug 24 11:55:11 AM UTC 24 |
| Peak memory | 624564 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=hmac_functest:1:new_rules ,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_r andom_seed=2759989589 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_h mac_oneshot.2759989589 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/1.chip_sw_hmac_oneshot/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_hmac_smoketest.1381780796 |
| Short name | T1058 |
| Test name | |
| Test status | |
| Simulation time | 2940195200 ps |
| CPU time | 265.87 seconds |
| Started | Aug 24 12:42:36 PM UTC 24 |
| Finished | Aug 24 12:47:06 PM UTC 24 |
| Peak memory | 626804 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=hmac_smoketest:1:new_rule s,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ random_seed=1381780796 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_ hmac_smoketest.1381780796 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/1.chip_sw_hmac_smoketest/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_i2c_device_tx_rx.1144668479 |
| Short name | T77 |
| Test name | |
| Test status | |
| Simulation time | 4688319072 ps |
| CPU time | 451.75 seconds |
| Started | Aug 24 11:01:03 AM UTC 24 |
| Finished | Aug 24 11:08:40 AM UTC 24 |
| Peak memory | 624940 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=i2c_device_tx_rx_test:1:n ew_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc l +ntb_random_seed=1144668479 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_i2c_device_tx_rx_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_i2c_device_tx_rx.1144668479 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/1.chip_sw_i2c_device_tx_rx/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_i2c_host_tx_rx.1455976699 |
| Short name | T74 |
| Test name | |
| Test status | |
| Simulation time | 5870688120 ps |
| CPU time | 664.24 seconds |
| Started | Aug 24 11:00:42 AM UTC 24 |
| Finished | Aug 24 11:11:54 AM UTC 24 |
| Peak memory | 624756 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/default/simv +i2c_idx=0 +sw_build_device=sim_dv +sw_images=i2c_host_tx_rx _test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/too ls/sim.tcl +ntb_random_seed=1455976699 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_i2c_host_tx_rx_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /de v/null -cm_name 1.chip_sw_i2c_host_tx_rx.1455976699 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/1.chip_sw_i2c_host_tx_rx/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_i2c_host_tx_rx_idx1.4161372282 |
| Short name | T138 |
| Test name | |
| Test status | |
| Simulation time | 4712236116 ps |
| CPU time | 500.08 seconds |
| Started | Aug 24 11:00:41 AM UTC 24 |
| Finished | Aug 24 11:09:08 AM UTC 24 |
| Peak memory | 624756 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/default/simv +i2c_idx=1 +sw_build_device=sim_dv +sw_images=i2c_host_tx_rx _test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/too ls/sim.tcl +ntb_random_seed=4161372282 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_i2c_host_tx_rx_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /de v/null -cm_name 1.chip_sw_i2c_host_tx_rx_idx1.4161372282 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/1.chip_sw_i2c_host_tx_rx_idx1/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_i2c_host_tx_rx_idx2.4044318792 |
| Short name | T139 |
| Test name | |
| Test status | |
| Simulation time | 5167076168 ps |
| CPU time | 504.15 seconds |
| Started | Aug 24 11:01:03 AM UTC 24 |
| Finished | Aug 24 11:09:33 AM UTC 24 |
| Peak memory | 625004 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/default/simv +i2c_idx=2 +sw_build_device=sim_dv +sw_images=i2c_host_tx_rx _test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/too ls/sim.tcl +ntb_random_seed=4044318792 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_i2c_host_tx_rx_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /de v/null -cm_name 1.chip_sw_i2c_host_tx_rx_idx2.4044318792 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/1.chip_sw_i2c_host_tx_rx_idx2/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_inject_scramble_seed.1192202516 |
| Short name | T1175 |
| Test name | |
| Test status | |
| Simulation time | 64045576971 ps |
| CPU time | 11696.2 seconds |
| Started | Aug 24 10:58:10 AM UTC 24 |
| Finished | Aug 24 02:15:08 PM UTC 24 |
| Peak memory | 644676 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/default/simv +lc_at_prod=1 +flash_program_latency=5 +sw_test_timeout_ns=1 50_000_000 +sw_build_device=sim_dv +sw_images=inject_scramble_seed:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1192202516 -assert nopostproc +UVM_TESTNAME=chip_base_tes t +UVM_TEST_SEQ=chip_sw_inject_scramble_seed_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_08_22/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_inject_scramble_seed.1192202516 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/1.chip_sw_inject_scramble_seed/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_keymgr_key_derivation.960686755 |
| Short name | T1003 |
| Test name | |
| Test status | |
| Simulation time | 5667358548 ps |
| CPU time | 629.24 seconds |
| Started | Aug 24 11:51:55 AM UTC 24 |
| Finished | Aug 24 12:02:32 PM UTC 24 |
| Peak memory | 632868 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=20_000_000 +sw_build_device=sim_dv +sw_i mages=keymgr_key_derivation_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=960686755 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_keymgr_key_ derivation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_keymgr_key_derivation.960686755 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/1.chip_sw_keymgr_key_derivation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_keymgr_key_derivation_jitter_en.1244192934 |
| Short name | T1005 |
| Test name | |
| Test status | |
| Simulation time | 8949067650 ps |
| CPU time | 878.7 seconds |
| Started | Aug 24 11:52:46 AM UTC 24 |
| Finished | Aug 24 12:07:35 PM UTC 24 |
| Peak memory | 632856 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=20_000_000 +en_jitter=1 +sw_build_device =sim_dv +sw_images=keymgr_key_derivation_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu eue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1244192934 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_ sw_keymgr_key_derivation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgre y_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_keymgr_key_derivation_jitter_en.1244192934 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/1.chip_sw_keymgr_key_derivation_jitter_en/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_keymgr_key_derivation_jitter_en_reduced_freq.3886339551 |
| Short name | T1060 |
| Test name | |
| Test status | |
| Simulation time | 12317457891 ps |
| CPU time | 1331.85 seconds |
| Started | Aug 24 12:26:20 PM UTC 24 |
| Finished | Aug 24 12:48:47 PM UTC 24 |
| Peak memory | 637948 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=20_000_000 +en_jitter=1 +cal_sys_clk_70m hz=1 +sw_build_device=sim_dv +sw_images=keymgr_key_derivation_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3886339551 -assert nopostproc +UVM_TESTNAME=chip_base_tes t +UVM_TEST_SEQ=chip_sw_keymgr_key_derivation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_22/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_keymgr_key_derivation_jitter_en_reduced_freq.3886339551 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/1.chip_sw_keymgr_key_derivation_jitter_en_reduced_freq/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_keymgr_key_derivation_prod.3312225163 |
| Short name | T1004 |
| Test name | |
| Test status | |
| Simulation time | 6034948786 ps |
| CPU time | 713.23 seconds |
| Started | Aug 24 11:52:27 AM UTC 24 |
| Finished | Aug 24 12:04:29 PM UTC 24 |
| Peak memory | 633184 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/default/simv +lc_at_prod=1 +sw_test_timeout_ns=20_000_000 +sw_build_devic e=sim_dv +sw_images=keymgr_key_derivation_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3312225163 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip _sw_keymgr_key_derivation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgr ey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_keymgr_key_derivation_prod.3312225163 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/1.chip_sw_keymgr_key_derivation_prod/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_keymgr_sideload_aes.2561218224 |
| Short name | T317 |
| Test name | |
| Test status | |
| Simulation time | 8239985990 ps |
| CPU time | 1061.17 seconds |
| Started | Aug 24 11:53:31 AM UTC 24 |
| Finished | Aug 24 12:11:25 PM UTC 24 |
| Peak memory | 627040 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=20_000_000 +sw_build_device=sim_dv +sw_i mages=keymgr_sideload_aes_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2561218224 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_keymgr_sidel oad_aes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_keymgr_sideload_aes.2561218224 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/1.chip_sw_keymgr_sideload_aes/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_keymgr_sideload_kmac.2568094670 |
| Short name | T1009 |
| Test name | |
| Test status | |
| Simulation time | 8851683868 ps |
| CPU time | 996.17 seconds |
| Started | Aug 24 11:53:31 AM UTC 24 |
| Finished | Aug 24 12:10:19 PM UTC 24 |
| Peak memory | 627004 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=20_000_000 +sw_build_device=sim_dv +sw_i mages=keymgr_sideload_kmac_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2568094670 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_keymgr_side load_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_keymgr_sideload_kmac.2568094670 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/1.chip_sw_keymgr_sideload_kmac/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_keymgr_sideload_otbn.2959990950 |
| Short name | T319 |
| Test name | |
| Test status | |
| Simulation time | 12232602562 ps |
| CPU time | 2374.94 seconds |
| Started | Aug 24 11:55:42 AM UTC 24 |
| Finished | Aug 24 12:35:43 PM UTC 24 |
| Peak memory | 629852 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=20_000_000 +sw_build_device=sim_dv +sw_i mages=keymgr_sideload_otbn_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2959990950 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default .vdb -cm_log /dev/null -cm_name 1.chip_sw_keymgr_sideload_otbn.2959990950 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/1.chip_sw_keymgr_sideload_otbn/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_kmac_app_rom.3186595270 |
| Short name | T430 |
| Test name | |
| Test status | |
| Simulation time | 3220726520 ps |
| CPU time | 161.93 seconds |
| Started | Aug 24 11:58:07 AM UTC 24 |
| Finished | Aug 24 12:00:52 PM UTC 24 |
| Peak memory | 624556 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=kmac_app_rom_test:1:new_r ules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +n tb_random_seed=3186595270 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a ssert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_ sw_kmac_app_rom.3186595270 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/1.chip_sw_kmac_app_rom/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_kmac_entropy.2544343439 |
| Short name | T939 |
| Test name | |
| Test status | |
| Simulation time | 2039672322 ps |
| CPU time | 163.43 seconds |
| Started | Aug 24 11:09:56 AM UTC 24 |
| Finished | Aug 24 11:12:42 AM UTC 24 |
| Peak memory | 624632 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=kmac_entropy_test:1:new_r ules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +n tb_random_seed=2544343439 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a ssert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_ sw_kmac_entropy.2544343439 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/1.chip_sw_kmac_entropy/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_kmac_idle.1361531139 |
| Short name | T1002 |
| Test name | |
| Test status | |
| Simulation time | 2486920540 ps |
| CPU time | 162.34 seconds |
| Started | Aug 24 11:59:04 AM UTC 24 |
| Finished | Aug 24 12:01:49 PM UTC 24 |
| Peak memory | 624816 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=kmac_idle_test:1:new_rule s,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ random_seed=1361531139 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_ kmac_idle.1361531139 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/1.chip_sw_kmac_idle/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_kmac_mode_cshake.606039197 |
| Short name | T997 |
| Test name | |
| Test status | |
| Simulation time | 3028898828 ps |
| CPU time | 206.23 seconds |
| Started | Aug 24 11:55:43 AM UTC 24 |
| Finished | Aug 24 11:59:12 AM UTC 24 |
| Peak memory | 624740 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=kmac_mode_cshake_test:1:n ew_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc l +ntb_random_seed=606039197 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.ch ip_sw_kmac_mode_cshake.606039197 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/1.chip_sw_kmac_mode_cshake/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_kmac_mode_kmac.1731235011 |
| Short name | T998 |
| Test name | |
| Test status | |
| Simulation time | 2866906656 ps |
| CPU time | 216.12 seconds |
| Started | Aug 24 11:55:43 AM UTC 24 |
| Finished | Aug 24 11:59:22 AM UTC 24 |
| Peak memory | 624556 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=kmac_mode_kmac_test:1:new _rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1731235011 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.chi p_sw_kmac_mode_kmac.1731235011 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/1.chip_sw_kmac_mode_kmac/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_kmac_mode_kmac_jitter_en.4202509294 |
| Short name | T1000 |
| Test name | |
| Test status | |
| Simulation time | 3108617718 ps |
| CPU time | 224.43 seconds |
| Started | Aug 24 11:57:00 AM UTC 24 |
| Finished | Aug 24 12:00:48 PM UTC 24 |
| Peak memory | 624564 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/default/simv +en_jitter=1 +sw_build_device=sim_dv +sw_images=kmac_mode_km ac_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/t ools/sim.tcl +ntb_random_seed=4202509294 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null - cm_name 1.chip_sw_kmac_mode_kmac_jitter_en.4202509294 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/1.chip_sw_kmac_mode_kmac_jitter_en/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_kmac_mode_kmac_jitter_en_reduced_freq.1645368570 |
| Short name | T1038 |
| Test name | |
| Test status | |
| Simulation time | 2902493451 ps |
| CPU time | 208.16 seconds |
| Started | Aug 24 12:26:21 PM UTC 24 |
| Finished | Aug 24 12:29:52 PM UTC 24 |
| Peak memory | 624784 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/default/simv +en_jitter=1 +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +s w_images=kmac_mode_kmac_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo rkspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1645368570 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default.vd b -cm_log /dev/null -cm_name 1.chip_sw_kmac_mode_kmac_jitter_en_reduced_freq.1645368570 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/1.chip_sw_kmac_mode_kmac_jitter_en_reduced_freq/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_kmac_smoketest.3808913577 |
| Short name | T1056 |
| Test name | |
| Test status | |
| Simulation time | 3481977784 ps |
| CPU time | 223.31 seconds |
| Started | Aug 24 12:42:37 PM UTC 24 |
| Finished | Aug 24 12:46:23 PM UTC 24 |
| Peak memory | 625044 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=kmac_smoketest:1:new_rule s,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ random_seed=3808913577 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_ kmac_smoketest.3808913577 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/1.chip_sw_kmac_smoketest/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_lc_ctrl_otp_hw_cfg0.3170845641 |
| Short name | T940 |
| Test name | |
| Test status | |
| Simulation time | 3128746600 ps |
| CPU time | 178.8 seconds |
| Started | Aug 24 11:10:11 AM UTC 24 |
| Finished | Aug 24 11:13:12 AM UTC 24 |
| Peak memory | 624568 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=lc_ctrl_otp_hw_cfg0_test: 1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim .tcl +ntb_random_seed=3170845641 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_lc_ctrl_otp_hw_cfg0.3170845641 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/1.chip_sw_lc_ctrl_otp_hw_cfg0/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_lc_ctrl_program_error.2444310562 |
| Short name | T210 |
| Test name | |
| Test status | |
| Simulation time | 5392933568 ps |
| CPU time | 295.6 seconds |
| Started | Aug 24 12:16:33 PM UTC 24 |
| Finished | Aug 24 12:21:33 PM UTC 24 |
| Peak memory | 626756 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/default/simv +en_scb=0 +bypass_alert_ready_to_end_check=1 +sw_build_devic e=sim_dv +sw_images=lc_ctrl_program_error:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2444310562 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_l c_ctrl_program_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_as ic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_lc_ctrl_program_error.2444310562 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/1.chip_sw_lc_ctrl_program_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_lc_ctrl_rand_to_scrap.1084339486 |
| Short name | T631 |
| Test name | |
| Test status | |
| Simulation time | 3462553866 ps |
| CPU time | 109.48 seconds |
| Started | Aug 24 11:12:37 AM UTC 24 |
| Finished | Aug 24 11:14:28 AM UTC 24 |
| Peak memory | 636900 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv + sw_images=lc_ctrl_scrap_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo rkspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1084339486 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_ctrl_scrap_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 1.chip_sw_lc_ctrl_rand_to_scrap.1084339486 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/1.chip_sw_lc_ctrl_rand_to_scrap/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_lc_ctrl_transition.2953358883 |
| Short name | T952 |
| Test name | |
| Test status | |
| Simulation time | 12874653734 ps |
| CPU time | 697.47 seconds |
| Started | Aug 24 11:12:36 AM UTC 24 |
| Finished | Aug 24 11:24:22 AM UTC 24 |
| Peak memory | 637164 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=lc_ctrl_transition_test:1 :new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim. tcl +ntb_random_seed=2953358883 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_ctrl_transition_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/n ull -cm_name 1.chip_sw_lc_ctrl_transition.2953358883 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/1.chip_sw_lc_ctrl_transition/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_lc_ctrl_volatile_raw_unlock.3193354884 |
| Short name | T633 |
| Test name | |
| Test status | |
| Simulation time | 1875124398 ps |
| CPU time | 90.57 seconds |
| Started | Aug 24 11:14:51 AM UTC 24 |
| Finished | Aug 24 11:16:23 AM UTC 24 |
| Peak memory | 634224 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/default/simv +use_otp_image=OtpTypeLcStRaw +exp_volatile_raw_unlock_en=0 +sw_build_device=sim_dv +sw_images=lc_ctrl_volatile_raw_unlock_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3193354884 -assert nopostproc +UVM_TESTNAME=chip_base_te st +UVM_TEST_SEQ=chip_sw_lc_volatile_raw_unlock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_lc_ctrl_volatile_raw_unlock.3193354884 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/1.chip_sw_lc_ctrl_volatile_raw_unlock/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz.2369265206 |
| Short name | T632 |
| Test name | |
| Test status | |
| Simulation time | 2306632209 ps |
| CPU time | 83.45 seconds |
| Started | Aug 24 11:14:54 AM UTC 24 |
| Finished | Aug 24 11:16:19 AM UTC 24 |
| Peak memory | 634284 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/default/simv +use_otp_image=OtpTypeLcStRaw +chip_clock_source=ChipClockSo urceExternal48Mhz +exp_volatile_raw_unlock_en=0 +sw_build_device=sim_dv +sw_images=lc_ctrl_volatile_raw_unlock_test:1:new_rules,test_rom:0 +cdc_in strumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=23692652 06 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_volatile_raw_unlock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_lc _ctrl_volatile_raw_unlock_ext_clk_48mhz.2369265206 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/1.chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_lc_walkthrough_dev.1734886826 |
| Short name | T327 |
| Test name | |
| Test status | |
| Simulation time | 47531946913 ps |
| CPU time | 4549 seconds |
| Started | Aug 24 11:13:12 AM UTC 24 |
| Finished | Aug 24 12:29:47 PM UTC 24 |
| Peak memory | 644268 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/default/simv +flash_program_latency=5 +use_otp_image=OtpTypeLcStRaw +dest _dec_state=DecLcStDev +sw_test_timeout_ns=200_000_000 +sw_build_device=sim_dv +sw_images=lc_walkthrough_test:1:new_rules,test_rom:0 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1734886826 -ass ert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_walkthrough_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works paces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_lc_walkthrough_dev.1734886826 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/1.chip_sw_lc_walkthrough_dev/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_lc_walkthrough_prod.4152402351 |
| Short name | T330 |
| Test name | |
| Test status | |
| Simulation time | 48789157596 ps |
| CPU time | 4251.38 seconds |
| Started | Aug 24 11:13:14 AM UTC 24 |
| Finished | Aug 24 12:24:51 PM UTC 24 |
| Peak memory | 644260 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/default/simv +flash_program_latency=5 +use_otp_image=OtpTypeLcStRaw +dest _dec_state=DecLcStProd +sw_test_timeout_ns=200_000_000 +sw_build_device=sim_dv +sw_images=lc_walkthrough_test:1:new_rules,test_rom:0 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4152402351 -as sert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_walkthrough_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work spaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_lc_walkthrough_prod.4152402351 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/1.chip_sw_lc_walkthrough_prod/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_lc_walkthrough_prodend.526951646 |
| Short name | T953 |
| Test name | |
| Test status | |
| Simulation time | 11289574592 ps |
| CPU time | 671.33 seconds |
| Started | Aug 24 11:13:36 AM UTC 24 |
| Finished | Aug 24 11:24:56 AM UTC 24 |
| Peak memory | 641308 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/default/simv +flash_program_latency=5 +use_otp_image=OtpTypeLcStRaw +dest _dec_state=DecLcStProdEnd +sw_build_device=sim_dv +sw_images=lc_walkthrough_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=526951646 -assert nopostproc +UVM_TESTNAME= chip_base_test +UVM_TEST_SEQ=chip_sw_lc_walkthrough_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_lc_walkthrough_prodend.526951646 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/1.chip_sw_lc_walkthrough_prodend/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_lc_walkthrough_rma.513841729 |
| Short name | T326 |
| Test name | |
| Test status | |
| Simulation time | 46186469027 ps |
| CPU time | 4120.72 seconds |
| Started | Aug 24 11:15:22 AM UTC 24 |
| Finished | Aug 24 12:24:45 PM UTC 24 |
| Peak memory | 644588 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/default/simv +use_otp_image=OtpTypeLcStRaw +dest_dec_state=DecLcStRma +fl ash_program_latency=5 +sw_test_timeout_ns=200_000_000 +sw_build_device=sim_dv +sw_images=lc_walkthrough_test:1:new_rules,test_rom:0 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=513841729 -asse rt nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_walkthrough_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp aces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_lc_walkthrough_rma.513841729 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/1.chip_sw_lc_walkthrough_rma/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_lc_walkthrough_testunlocks.869344688 |
| Short name | T973 |
| Test name | |
| Test status | |
| Simulation time | 33880500318 ps |
| CPU time | 1432.92 seconds |
| Started | Aug 24 11:15:39 AM UTC 24 |
| Finished | Aug 24 11:39:47 AM UTC 24 |
| Peak memory | 641384 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/default/simv +use_otp_image=OtpTypeLcStRaw +dest_dec_state=DecLcStTestUnl ock7 +sw_build_device=sim_dv +sw_images=lc_walkthrough_testunlocks_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=869344688 -assert nopostproc +UVM_TESTNAME=chip_base _test +UVM_TEST_SEQ=chip_sw_lc_walkthrough_testunlocks_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_lc_walkthrough_testunlocks.869344688 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/1.chip_sw_lc_walkthrough_testunlocks/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_otbn_ecdsa_op_irq.703529299 |
| Short name | T1035 |
| Test name | |
| Test status | |
| Simulation time | 16745125486 ps |
| CPU time | 3217.28 seconds |
| Started | Aug 24 11:33:59 AM UTC 24 |
| Finished | Aug 24 12:28:12 PM UTC 24 |
| Peak memory | 629792 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=28_000_000 +rng_srate_value=30 +sw_build _device=sim_dv +sw_images=otbn_ecdsa_op_irq_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=703529299 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chi p_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_otbn_ecdsa_op_irq.703529299 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/1.chip_sw_otbn_ecdsa_op_irq/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_otbn_ecdsa_op_irq_jitter_en.2088452657 |
| Short name | T1030 |
| Test name | |
| Test status | |
| Simulation time | 18656084274 ps |
| CPU time | 3015.54 seconds |
| Started | Aug 24 11:34:42 AM UTC 24 |
| Finished | Aug 24 12:25:30 PM UTC 24 |
| Peak memory | 630048 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=33_000_000 +rng_srate_value=30 +en_jitte r=1 +sw_build_device=sim_dv +sw_images=otbn_ecdsa_op_irq_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2088452657 -assert nopostproc +UVM_TESTNAME=chip_base_test +UV M_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey _asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_otbn_ecdsa_op_irq_jitter_en.2088452657 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/1.chip_sw_otbn_ecdsa_op_irq_jitter_en/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq.793301939 |
| Short name | T1093 |
| Test name | |
| Test status | |
| Simulation time | 24701741560 ps |
| CPU time | 3343.59 seconds |
| Started | Aug 24 12:25:45 PM UTC 24 |
| Finished | Aug 24 01:22:04 PM UTC 24 |
| Peak memory | 629792 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=33_000_000 +rng_srate_value=30 +en_jitte r=1 +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +sw_images=otbn_ecdsa_op_irq_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=793301939 -assert nopostproc +UVM_TESTNAM E=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _08_22/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq.793301939 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/1.chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_otbn_mem_scramble.232435212 |
| Short name | T283 |
| Test name | |
| Test status | |
| Simulation time | 3669331066 ps |
| CPU time | 351.78 seconds |
| Started | Aug 24 11:34:43 AM UTC 24 |
| Finished | Aug 24 11:40:39 AM UTC 24 |
| Peak memory | 626760 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=15_000_000 +en_scb_tl_err_chk=0 +bypass_ alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=otbn_mem_scramble_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=232435212 -assert nopostproc +UVM_TESTN AME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_22/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_otbn_mem_scramble.232435212 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/1.chip_sw_otbn_mem_scramble/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_otbn_randomness.3096566248 |
| Short name | T977 |
| Test name | |
| Test status | |
| Simulation time | 5594113488 ps |
| CPU time | 555.67 seconds |
| Started | Aug 24 11:33:21 AM UTC 24 |
| Finished | Aug 24 11:42:44 AM UTC 24 |
| Peak memory | 626756 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=18_000_000 +rng_srate_value=30 +sw_build _device=sim_dv +sw_images=otbn_randomness_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3096566248 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip _sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_otbn_randomness.3096566248 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/1.chip_sw_otbn_randomness/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_otbn_smoketest.883349302 |
| Short name | T1077 |
| Test name | |
| Test status | |
| Simulation time | 8034387548 ps |
| CPU time | 1207.78 seconds |
| Started | Aug 24 12:42:38 PM UTC 24 |
| Finished | Aug 24 01:02:58 PM UTC 24 |
| Peak memory | 624840 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=otbn_smoketest:1:new_rule s,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ random_seed=883349302 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_o tbn_smoketest.883349302 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/1.chip_sw_otbn_smoketest/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_otp_ctrl_ecc_error_vendor_test.2501316194 |
| Short name | T942 |
| Test name | |
| Test status | |
| Simulation time | 2847509610 ps |
| CPU time | 183.25 seconds |
| Started | Aug 24 11:12:20 AM UTC 24 |
| Finished | Aug 24 11:15:26 AM UTC 24 |
| Peak memory | 624556 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=otp_ctrl_vendor_test_ecc_ error_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/d v/tools/sim.tcl +ntb_random_seed=2501316194 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_otp_ctrl_vendor_test_ecc_error_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/de fault.vdb -cm_log /dev/null -cm_name 1.chip_sw_otp_ctrl_ecc_error_vendor_test.2501316194 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/1.chip_sw_otp_ctrl_ecc_error_vendor_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_otp_ctrl_lc_signals_dev.2001662419 |
| Short name | T951 |
| Test name | |
| Test status | |
| Simulation time | 8459379260 ps |
| CPU time | 795.83 seconds |
| Started | Aug 24 11:10:55 AM UTC 24 |
| Finished | Aug 24 11:24:20 AM UTC 24 |
| Peak memory | 626624 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/default/simv +use_otp_image=OtpTypeLcStDev +otp_clear_secret2=1 +sw_build _device=sim_dv +sw_images=otp_ctrl_lc_signals_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2001662419 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ= chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_otp_ctrl_lc_signals_dev.2001662419 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/1.chip_sw_otp_ctrl_lc_signals_dev/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_otp_ctrl_lc_signals_prod.1391933841 |
| Short name | T955 |
| Test name | |
| Test status | |
| Simulation time | 7340327200 ps |
| CPU time | 968.1 seconds |
| Started | Aug 24 11:11:41 AM UTC 24 |
| Finished | Aug 24 11:28:00 AM UTC 24 |
| Peak memory | 626948 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/default/simv +use_otp_image=OtpTypeLcStProd +otp_clear_secret2=1 +sw_buil d_device=sim_dv +sw_images=otp_ctrl_lc_signals_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1391933841 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ =chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_otp_ctrl_lc_signals_prod.1391933841 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/1.chip_sw_otp_ctrl_lc_signals_prod/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_otp_ctrl_lc_signals_rma.3216897910 |
| Short name | T954 |
| Test name | |
| Test status | |
| Simulation time | 8505018672 ps |
| CPU time | 878.58 seconds |
| Started | Aug 24 11:12:17 AM UTC 24 |
| Finished | Aug 24 11:27:05 AM UTC 24 |
| Peak memory | 624840 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/default/simv +use_otp_image=OtpTypeLcStRma +otp_clear_secret2=1 +sw_build _device=sim_dv +sw_images=otp_ctrl_lc_signals_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3216897910 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ= chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_otp_ctrl_lc_signals_rma.3216897910 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/1.chip_sw_otp_ctrl_lc_signals_rma/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_otp_ctrl_lc_signals_test_unlocked0.2313176038 |
| Short name | T946 |
| Test name | |
| Test status | |
| Simulation time | 4527699088 ps |
| CPU time | 457.16 seconds |
| Started | Aug 24 11:10:55 AM UTC 24 |
| Finished | Aug 24 11:18:38 AM UTC 24 |
| Peak memory | 626684 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/default/simv +use_otp_image=OtpTypeLcStTestUnlocked0 +otp_clear_secret2=1 +sw_build_device=sim_dv +sw_images=otp_ctrl_lc_signals_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY =UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2313176038 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM _TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_ asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_otp_ctrl_lc_signals_test_unlocked0.2313176038 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/1.chip_sw_otp_ctrl_lc_signals_test_unlocked0/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_otp_ctrl_smoketest.1773814245 |
| Short name | T1055 |
| Test name | |
| Test status | |
| Simulation time | 2818243124 ps |
| CPU time | 200.88 seconds |
| Started | Aug 24 12:42:40 PM UTC 24 |
| Finished | Aug 24 12:46:03 PM UTC 24 |
| Peak memory | 624812 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=otp_ctrl_smoketest:1:new_ rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl + ntb_random_seed=1773814245 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip _sw_otp_ctrl_smoketest.1773814245 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/1.chip_sw_otp_ctrl_smoketest/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_plic_sw_irq.75513455 |
| Short name | T269 |
| Test name | |
| Test status | |
| Simulation time | 2199593260 ps |
| CPU time | 155.57 seconds |
| Started | Aug 24 12:07:58 PM UTC 24 |
| Finished | Aug 24 12:10:36 PM UTC 24 |
| Peak memory | 624564 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=plic_sw_irq_test:1:new_ru les,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +nt b_random_seed=75513455 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_ plic_sw_irq.75513455 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/1.chip_sw_plic_sw_irq/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_power_idle_load.2070398284 |
| Short name | T1041 |
| Test name | |
| Test status | |
| Simulation time | 5172033896 ps |
| CPU time | 461.52 seconds |
| Started | Aug 24 12:27:52 PM UTC 24 |
| Finished | Aug 24 12:35:39 PM UTC 24 |
| Peak memory | 624560 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=chip_power_idle_load:1:ne w_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2070398284 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_power_idle_load_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -c m_name 1.chip_sw_power_idle_load.2070398284 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/1.chip_sw_power_idle_load/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_power_sleep_load.1387717476 |
| Short name | T651 |
| Test name | |
| Test status | |
| Simulation time | 4485379404 ps |
| CPU time | 220.2 seconds |
| Started | Aug 24 12:27:53 PM UTC 24 |
| Finished | Aug 24 12:31:36 PM UTC 24 |
| Peak memory | 625132 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=chip_power_sleep_load:1:n ew_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc l +ntb_random_seed=1387717476 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_power_sleep_load_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_power_sleep_load.1387717476 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/1.chip_sw_power_sleep_load/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_power_virus.1496247399 |
| Short name | T85 |
| Test name | |
| Test status | |
| Simulation time | 5287441172 ps |
| CPU time | 1023.69 seconds |
| Started | Aug 24 12:28:00 PM UTC 24 |
| Finished | Aug 24 12:45:15 PM UTC 24 |
| Peak memory | 641428 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/default/simv +rng_srate_value_min=15 +rng_srate_value_max=20 +sw_test_tim eout_ns=400_000_000 +use_otp_image=OtpTypeCustom +accelerate_cold_power_up_time=3 +accelerate_regulators_power_up_time=2 +sw_build_device=sim_dv + sw_images=power_virus_systemtest:1:new_rules,power_virus_systemtest_otp_img_rma:4,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1496247399 -assert nopostproc +UVM_TESTNAME=chip_base_ test +UVM_TEST_SEQ=chip_sw_power_virus_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_2 2/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_power_virus.1496247399 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/1.chip_sw_power_virus/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_pwrmgr_all_reset_reqs.2882020998 |
| Short name | T965 |
| Test name | |
| Test status | |
| Simulation time | 11654686307 ps |
| CPU time | 898.77 seconds |
| Started | Aug 24 11:19:05 AM UTC 24 |
| Finished | Aug 24 11:34:14 AM UTC 24 |
| Peak memory | 626696 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=50_000_000 +sw_build_device=sim_dv +sw_i mages=pwrmgr_all_reset_reqs_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2882020998 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_deep_sleep _all_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_pwrmgr_all_reset_reqs.2882020998 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/1.chip_sw_pwrmgr_all_reset_reqs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_pwrmgr_b2b_sleep_reset_req.4021897082 |
| Short name | T1042 |
| Test name | |
| Test status | |
| Simulation time | 28355928612 ps |
| CPU time | 1917.69 seconds |
| Started | Aug 24 12:05:12 PM UTC 24 |
| Finished | Aug 24 12:37:31 PM UTC 24 |
| Peak memory | 629728 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=35_000_000 +sw_build_device=sim_dv +sw_i mages=pwrmgr_b2b_sleep_reset_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4021897082 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_repeat_re set_wkup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_pwrmgr_b2b_sleep_reset_req.4021897082 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/1.chip_sw_pwrmgr_b2b_sleep_reset_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_pwrmgr_deep_sleep_all_reset_reqs.518076052 |
| Short name | T969 |
| Test name | |
| Test status | |
| Simulation time | 18016320135 ps |
| CPU time | 1031.86 seconds |
| Started | Aug 24 11:21:13 AM UTC 24 |
| Finished | Aug 24 11:38:36 AM UTC 24 |
| Peak memory | 627012 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=50_000_000 +sw_build_device=sim_dv +sw_i mages=pwrmgr_deep_sleep_all_reset_reqs_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu e -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=518076052 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_ deep_sleep_all_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_as ic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_pwrmgr_deep_sleep_all_reset_reqs.518076052 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/1.chip_sw_pwrmgr_deep_sleep_all_reset_reqs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_pwrmgr_deep_sleep_all_wake_ups.683122145 |
| Short name | T437 |
| Test name | |
| Test status | |
| Simulation time | 23343809926 ps |
| CPU time | 1143.41 seconds |
| Started | Aug 24 12:18:13 PM UTC 24 |
| Finished | Aug 24 12:37:29 PM UTC 24 |
| Peak memory | 627832 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_i mages=pwrmgr_deep_sleep_all_wake_ups:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=683122145 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_pwrmgr_ deep_sleep_all_wake_ups_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey _asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_pwrmgr_deep_sleep_all_wake_ups.683122145 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/1.chip_sw_pwrmgr_deep_sleep_all_wake_ups/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_pwrmgr_deep_sleep_por_reset.204358264 |
| Short name | T956 |
| Test name | |
| Test status | |
| Simulation time | 8422179870 ps |
| CPU time | 373.04 seconds |
| Started | Aug 24 11:21:57 AM UTC 24 |
| Finished | Aug 24 11:28:14 AM UTC 24 |
| Peak memory | 626680 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=pwrmgr_deep_sleep_por_res et_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/t ools/sim.tcl +ntb_random_seed=204358264 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sleep_por_reset_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 1.chip_sw_pwrmgr_deep_sleep_por_reset.204358264 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/1.chip_sw_pwrmgr_deep_sleep_por_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_pwrmgr_deep_sleep_power_glitch_reset.403233180 |
| Short name | T960 |
| Test name | |
| Test status | |
| Simulation time | 5545997992 ps |
| CPU time | 345.45 seconds |
| Started | Aug 24 11:24:53 AM UTC 24 |
| Finished | Aug 24 11:30:43 AM UTC 24 |
| Peak memory | 632848 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv + sw_images=pwrmgr_deep_sleep_power_glitch_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu eue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=403233180 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_s w_deep_power_glitch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asi c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_pwrmgr_deep_sleep_power_glitch_reset.403233180 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/1.chip_sw_pwrmgr_deep_sleep_power_glitch_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_pwrmgr_full_aon_reset.936060616 |
| Short name | T182 |
| Test name | |
| Test status | |
| Simulation time | 8349065192 ps |
| CPU time | 352.55 seconds |
| Started | Aug 24 11:17:57 AM UTC 24 |
| Finished | Aug 24 11:23:55 AM UTC 24 |
| Peak memory | 626752 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=rstmgr_smoketest:1:new_ru les,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +nt b_random_seed=936060616 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_full_aon_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_pwrmgr_full_aon_reset.936060616 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/1.chip_sw_pwrmgr_full_aon_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_pwrmgr_lowpower_cancel.3733703734 |
| Short name | T368 |
| Test name | |
| Test status | |
| Simulation time | 4478331200 ps |
| CPU time | 334.92 seconds |
| Started | Aug 24 12:18:14 PM UTC 24 |
| Finished | Aug 24 12:23:53 PM UTC 24 |
| Peak memory | 624632 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=pwrmgr_lowpower_cancel_te st:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/ sim.tcl +ntb_random_seed=3733703734 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tg l+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_na me 1.chip_sw_pwrmgr_lowpower_cancel.3733703734 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/1.chip_sw_pwrmgr_lowpower_cancel/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_pwrmgr_main_power_glitch_reset.231396320 |
| Short name | T950 |
| Test name | |
| Test status | |
| Simulation time | 4246918625 ps |
| CPU time | 271.95 seconds |
| Started | Aug 24 11:18:47 AM UTC 24 |
| Finished | Aug 24 11:23:23 AM UTC 24 |
| Peak memory | 632960 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv + sw_images=pwrmgr_main_power_glitch_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=231396320 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_main _power_glitch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_pwrmgr_main_power_glitch_reset.231396320 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/1.chip_sw_pwrmgr_main_power_glitch_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_pwrmgr_normal_sleep_all_reset_reqs.1442634212 |
| Short name | T970 |
| Test name | |
| Test status | |
| Simulation time | 11661182897 ps |
| CPU time | 1044.52 seconds |
| Started | Aug 24 11:21:13 AM UTC 24 |
| Finished | Aug 24 11:38:50 AM UTC 24 |
| Peak memory | 627068 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=pwrmgr_normal_sleep_all_r eset_reqs_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/ hw/dv/tools/sim.tcl +ntb_random_seed=1442634212 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_deep_sleep_all_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default. vdb -cm_log /dev/null -cm_name 1.chip_sw_pwrmgr_normal_sleep_all_reset_reqs.1442634212 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/1.chip_sw_pwrmgr_normal_sleep_all_reset_reqs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_pwrmgr_normal_sleep_all_wake_ups.4173889840 |
| Short name | T125 |
| Test name | |
| Test status | |
| Simulation time | 7785448576 ps |
| CPU time | 353.62 seconds |
| Started | Aug 24 12:17:36 PM UTC 24 |
| Finished | Aug 24 12:23:34 PM UTC 24 |
| Peak memory | 626892 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=pwrmgr_normal_sleep_all_w ake_ups:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/t ools/sim.tcl +ntb_random_seed=4173889840 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_pwrmgr_deep_sleep_all_wake_ups_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 1.chip_sw_pwrmgr_normal_sleep_all_wake_ups.4173889840 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/1.chip_sw_pwrmgr_normal_sleep_all_wake_ups/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_pwrmgr_normal_sleep_por_reset.2428196798 |
| Short name | T958 |
| Test name | |
| Test status | |
| Simulation time | 6480662022 ps |
| CPU time | 329.24 seconds |
| Started | Aug 24 11:23:47 AM UTC 24 |
| Finished | Aug 24 11:29:20 AM UTC 24 |
| Peak memory | 626904 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=pwrmgr_normal_sleep_por_r eset_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv /tools/sim.tcl +ntb_random_seed=2428196798 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sleep_por_reset_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_lo g /dev/null -cm_name 1.chip_sw_pwrmgr_normal_sleep_por_reset.2428196798 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/1.chip_sw_pwrmgr_normal_sleep_por_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_pwrmgr_random_sleep_all_reset_reqs.4030731148 |
| Short name | T983 |
| Test name | |
| Test status | |
| Simulation time | 24336656147 ps |
| CPU time | 1535.56 seconds |
| Started | Aug 24 11:20:12 AM UTC 24 |
| Finished | Aug 24 11:46:04 AM UTC 24 |
| Peak memory | 626908 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=50_000_000 +sw_build_device=sim_dv +sw_i mages=pwrmgr_random_sleep_all_reset_reqs_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu eue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4030731148 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_ sw_deep_sleep_all_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey _asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_pwrmgr_random_sleep_all_reset_reqs.4030731148 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/1.chip_sw_pwrmgr_random_sleep_all_reset_reqs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_pwrmgr_random_sleep_all_wake_ups.3897073150 |
| Short name | T436 |
| Test name | |
| Test status | |
| Simulation time | 24309001952 ps |
| CPU time | 988.17 seconds |
| Started | Aug 24 12:18:16 PM UTC 24 |
| Finished | Aug 24 12:34:56 PM UTC 24 |
| Peak memory | 629588 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=18_000_000 +do_random=1 +sw_build_device =sim_dv +sw_images=pwrmgr_random_sleep_all_wake_ups:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3897073150 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ =chip_sw_pwrmgr_deep_sleep_all_wake_ups_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_ 22/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_pwrmgr_random_sleep_all_wake_ups.3897073150 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/1.chip_sw_pwrmgr_random_sleep_all_wake_ups/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up.69864503 |
| Short name | T388 |
| Test name | |
| Test status | |
| Simulation time | 5461276144 ps |
| CPU time | 283.17 seconds |
| Started | Aug 24 12:18:53 PM UTC 24 |
| Finished | Aug 24 12:23:40 PM UTC 24 |
| Peak memory | 627004 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=18_000_000 +do_random=1 +sw_build_device =sim_dv +sw_images=pwrmgr_sensor_ctrl_deep_sleep_wake_up:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=69864503 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_ SEQ=chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up.69864503 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/1.chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_pwrmgr_sleep_disabled.2356837496 |
| Short name | T646 |
| Test name | |
| Test status | |
| Simulation time | 3181971188 ps |
| CPU time | 222.8 seconds |
| Started | Aug 24 11:25:27 AM UTC 24 |
| Finished | Aug 24 11:29:13 AM UTC 24 |
| Peak memory | 624564 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=pwrmgr_sleep_disabled_tes t:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/s im.tcl +ntb_random_seed=2356837496 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam e 1.chip_sw_pwrmgr_sleep_disabled.2356837496 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/1.chip_sw_pwrmgr_sleep_disabled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup.3673491178 |
| Short name | T170 |
| Test name | |
| Test status | |
| Simulation time | 4713997692 ps |
| CPU time | 324.95 seconds |
| Started | Aug 24 12:04:53 PM UTC 24 |
| Finished | Aug 24 12:10:22 PM UTC 24 |
| Peak memory | 624760 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=8_000_000 +sw_build_device=sim_dv +sw_im ages=sensor_ctrl_wakeup_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo rkspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3673491178 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default.vd b -cm_log /dev/null -cm_name 1.chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup.3673491178 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/1.chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_pwrmgr_sleep_wake_5_bug.731212395 |
| Short name | T1029 |
| Test name | |
| Test status | |
| Simulation time | 5827382060 ps |
| CPU time | 379.66 seconds |
| Started | Aug 24 12:18:50 PM UTC 24 |
| Finished | Aug 24 12:25:15 PM UTC 24 |
| Peak memory | 627168 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=18_000_000 +do_random=1 +sw_build_device =sim_dv +sw_images=pwrmgr_sleep_wake_5_bug_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=731212395 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip _sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_pwrmgr_sleep_wake_5_bug.731212395 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/1.chip_sw_pwrmgr_sleep_wake_5_bug/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_pwrmgr_smoketest.3472668782 |
| Short name | T1066 |
| Test name | |
| Test status | |
| Simulation time | 5723201132 ps |
| CPU time | 373.74 seconds |
| Started | Aug 24 12:44:03 PM UTC 24 |
| Finished | Aug 24 12:50:22 PM UTC 24 |
| Peak memory | 624892 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=10000000 +sw_build_device=sim_dv +sw_ima ges=pwrmgr_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces /repo/hw/dv/tools/sim.tcl +ntb_random_seed=3472668782 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_lo g /dev/null -cm_name 1.chip_sw_pwrmgr_smoketest.3472668782 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/1.chip_sw_pwrmgr_smoketest/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_pwrmgr_sysrst_ctrl_reset.1506097624 |
| Short name | T962 |
| Test name | |
| Test status | |
| Simulation time | 8789809630 ps |
| CPU time | 788.56 seconds |
| Started | Aug 24 11:19:04 AM UTC 24 |
| Finished | Aug 24 11:32:23 AM UTC 24 |
| Peak memory | 624716 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=pwrmgr_sysrst_ctrl_test:1 :new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim. tcl +ntb_random_seed=1506097624 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sysrst_ctrl_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm _name 1.chip_sw_pwrmgr_sysrst_ctrl_reset.1506097624 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/1.chip_sw_pwrmgr_sysrst_ctrl_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_pwrmgr_usb_clk_disabled_when_active.3480259792 |
| Short name | T959 |
| Test name | |
| Test status | |
| Simulation time | 5664292160 ps |
| CPU time | 305.6 seconds |
| Started | Aug 24 11:25:27 AM UTC 24 |
| Finished | Aug 24 11:30:37 AM UTC 24 |
| Peak memory | 626824 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=pwrmgr_usb_clk_disabled_w hen_active_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo /hw/dv/tools/sim.tcl +ntb_random_seed=3480259792 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /de v/null -cm_name 1.chip_sw_pwrmgr_usb_clk_disabled_when_active.3480259792 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/1.chip_sw_pwrmgr_usb_clk_disabled_when_active/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_pwrmgr_usbdev_smoketest.2586455142 |
| Short name | T1069 |
| Test name | |
| Test status | |
| Simulation time | 6213112940 ps |
| CPU time | 348.15 seconds |
| Started | Aug 24 12:45:45 PM UTC 24 |
| Finished | Aug 24 12:51:37 PM UTC 24 |
| Peak memory | 624764 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=pwrmgr_usbdev_smoketest:1 :new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim. tcl +ntb_random_seed=2586455142 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1 .chip_sw_pwrmgr_usbdev_smoketest.2586455142 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/1.chip_sw_pwrmgr_usbdev_smoketest/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_pwrmgr_wdog_reset.1447052091 |
| Short name | T967 |
| Test name | |
| Test status | |
| Simulation time | 4310373400 ps |
| CPU time | 296.47 seconds |
| Started | Aug 24 11:32:20 AM UTC 24 |
| Finished | Aug 24 11:37:21 AM UTC 24 |
| Peak memory | 626872 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_i mages=pwrmgr_wdog_reset_reqs_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1447052091 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 1.chip_sw_pwrmgr_wdog_reset.1447052091 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/1.chip_sw_pwrmgr_wdog_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_rom_ctrl_integrity_check.58894484 |
| Short name | T431 |
| Test name | |
| Test status | |
| Simulation time | 7846801641 ps |
| CPU time | 422.47 seconds |
| Started | Aug 24 11:59:36 AM UTC 24 |
| Finished | Aug 24 12:06:44 PM UTC 24 |
| Peak memory | 626996 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=rom_ctrl_integrity_check_ test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=58894484 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rom_ctrl_integrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_ log /dev/null -cm_name 1.chip_sw_rom_ctrl_integrity_check.58894484 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/1.chip_sw_rom_ctrl_integrity_check/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_rstmgr_alert_info.3780124073 |
| Short name | T345 |
| Test name | |
| Test status | |
| Simulation time | 12230313114 ps |
| CPU time | 1167.53 seconds |
| Started | Aug 24 11:16:51 AM UTC 24 |
| Finished | Aug 24 11:36:32 AM UTC 24 |
| Peak memory | 626880 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=30_000_000 +en_scb_tl_err_chk=0 +sw_buil d_device=sim_dv +sw_images=rstmgr_alert_info_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3780124073 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=c hip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vc s/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_rstmgr_alert_info.3780124073 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/1.chip_sw_rstmgr_alert_info/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_rstmgr_cpu_info.2553795499 |
| Short name | T254 |
| Test name | |
| Test status | |
| Simulation time | 7051005250 ps |
| CPU time | 521.4 seconds |
| Started | Aug 24 11:17:01 AM UTC 24 |
| Finished | Aug 24 11:25:49 AM UTC 24 |
| Peak memory | 624592 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=rstmgr_cpu_info_test:1:ne w_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2553795499 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.ch ip_sw_rstmgr_cpu_info.2553795499 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/1.chip_sw_rstmgr_cpu_info/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_rstmgr_rst_cnsty_escalation.2049538188 |
| Short name | T377 |
| Test name | |
| Test status | |
| Simulation time | 5772762924 ps |
| CPU time | 389.47 seconds |
| Started | Aug 24 10:56:14 AM UTC 24 |
| Finished | Aug 24 11:02:48 AM UTC 24 |
| Peak memory | 671288 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv + sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2049538188 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rstmgr _cnsty_fault_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_rstmgr_rst_cnsty_escalation.2049538188 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/1.chip_sw_rstmgr_rst_cnsty_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_rstmgr_smoketest.2881875962 |
| Short name | T1059 |
| Test name | |
| Test status | |
| Simulation time | 2580724744 ps |
| CPU time | 120.81 seconds |
| Started | Aug 24 12:46:27 PM UTC 24 |
| Finished | Aug 24 12:48:31 PM UTC 24 |
| Peak memory | 624820 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=rstmgr_smoketest:1:new_ru les,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +nt b_random_seed=2881875962 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as sert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_s w_rstmgr_smoketest.2881875962 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/1.chip_sw_rstmgr_smoketest/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_rstmgr_sw_req.3853471274 |
| Short name | T948 |
| Test name | |
| Test status | |
| Simulation time | 4369967368 ps |
| CPU time | 286.81 seconds |
| Started | Aug 24 11:15:49 AM UTC 24 |
| Finished | Aug 24 11:20:40 AM UTC 24 |
| Peak memory | 624768 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=rstmgr_sw_req_test:1:new_ rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl + ntb_random_seed=3853471274 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip _sw_rstmgr_sw_req.3853471274 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/1.chip_sw_rstmgr_sw_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_rstmgr_sw_rst.3184874502 |
| Short name | T947 |
| Test name | |
| Test status | |
| Simulation time | 2644757192 ps |
| CPU time | 174.2 seconds |
| Started | Aug 24 11:16:51 AM UTC 24 |
| Finished | Aug 24 11:19:48 AM UTC 24 |
| Peak memory | 624808 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=rstmgr_sw_rst_ctrl_test:1 :new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim. tcl +ntb_random_seed=3184874502 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1 .chip_sw_rstmgr_sw_rst.3184874502 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/1.chip_sw_rstmgr_sw_rst/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_rv_core_ibex_address_translation.1290917379 |
| Short name | T256 |
| Test name | |
| Test status | |
| Simulation time | 2374751808 ps |
| CPU time | 225.05 seconds |
| Started | Aug 24 12:23:16 PM UTC 24 |
| Finished | Aug 24 12:27:05 PM UTC 24 |
| Peak memory | 626864 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=7_000_000 +sw_build_device=sim_dv +sw_im ages=rv_core_ibex_address_translation_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1290917379 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_ base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover age/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_rv_core_ibex_address_translation.1290917379 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/1.chip_sw_rv_core_ibex_address_translation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_rv_core_ibex_icache_invalidate.540618322 |
| Short name | T222 |
| Test name | |
| Test status | |
| Simulation time | 2866014241 ps |
| CPU time | 160.21 seconds |
| Started | Aug 24 12:24:07 PM UTC 24 |
| Finished | Aug 24 12:26:50 PM UTC 24 |
| Peak memory | 626864 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=rv_core_ibex_icache_inval idate_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/d v/tools/sim.tcl +ntb_random_seed=540618322 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rv_core_ibex_icache_invalidate_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/def ault.vdb -cm_log /dev/null -cm_name 1.chip_sw_rv_core_ibex_icache_invalidate.540618322 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/1.chip_sw_rv_core_ibex_icache_invalidate/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_rv_core_ibex_lockstep_glitch.2850154934 |
| Short name | T418 |
| Test name | |
| Test status | |
| Simulation time | 2888151200 ps |
| CPU time | 135.08 seconds |
| Started | Aug 24 12:23:27 PM UTC 24 |
| Finished | Aug 24 12:25:44 PM UTC 24 |
| Peak memory | 626424 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/default/simv +disable_assert_final_checks +sw_build_device=sim_dv +sw_ima ges=aes_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/re po/hw/dv/tools/sim.tcl +ntb_random_seed=2850154934 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rv_core_ibex_lockstep_gli tch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/covera ge/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_rv_core_ibex_lockstep_glitch.2850154934 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/1.chip_sw_rv_core_ibex_lockstep_glitch/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_rv_core_ibex_nmi_irq.166659015 |
| Short name | T454 |
| Test name | |
| Test status | |
| Simulation time | 4278632352 ps |
| CPU time | 572.15 seconds |
| Started | Aug 24 11:35:39 AM UTC 24 |
| Finished | Aug 24 11:45:17 AM UTC 24 |
| Peak memory | 624560 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=10_000_000 +sw_build_device=sim_dv +sw_i mages=rv_core_ibex_nmi_irq_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=166659015 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default. vdb -cm_log /dev/null -cm_name 1.chip_sw_rv_core_ibex_nmi_irq.166659015 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/1.chip_sw_rv_core_ibex_nmi_irq/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_rv_core_ibex_rnd.3130079506 |
| Short name | T984 |
| Test name | |
| Test status | |
| Simulation time | 6049757448 ps |
| CPU time | 706.5 seconds |
| Started | Aug 24 11:34:43 AM UTC 24 |
| Finished | Aug 24 11:46:38 AM UTC 24 |
| Peak memory | 624824 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=20_000_000 +rng_srate_value_max=32 +sw_b uild_device=sim_dv +sw_images=rv_core_ibex_rnd_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3130079506 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ =chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_rv_core_ibex_rnd.3130079506 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/1.chip_sw_rv_core_ibex_rnd/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_rv_dm_access_after_escalation_reset.3162099930 |
| Short name | T628 |
| Test name | |
| Test status | |
| Simulation time | 4328818229 ps |
| CPU time | 409.35 seconds |
| Started | Aug 24 12:19:25 PM UTC 24 |
| Finished | Aug 24 12:26:20 PM UTC 24 |
| Peak memory | 639052 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/default/simv +use_jtag_dmi=1 +sw_build_device=sim_dv +sw_images=alert_han dler_escalation_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces /repo/hw/dv/tools/sim.tcl +ntb_random_seed=3162099930 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rv_dm_access_after_esc alation_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_rv_dm_access_after_escalation_reset.3162099930 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/1.chip_sw_rv_dm_access_after_escalation_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_rv_dm_access_after_wakeup.1056009922 |
| Short name | T1031 |
| Test name | |
| Test status | |
| Simulation time | 5707234840 ps |
| CPU time | 362.31 seconds |
| Started | Aug 24 12:19:24 PM UTC 24 |
| Finished | Aug 24 12:25:32 PM UTC 24 |
| Peak memory | 637012 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/default/simv +use_jtag_dmi=1 +sw_build_device=sim_dv +sw_images=rv_dm_acc ess_after_wakeup_rma:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces /repo/hw/dv/tools/sim.tcl +ntb_random_seed=1056009922 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rv_dm_access_after_wak eup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/covera ge/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_rv_dm_access_after_wakeup.1056009922 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/1.chip_sw_rv_dm_access_after_wakeup/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_rv_dm_ndm_reset_req_when_cpu_halted.3780576421 |
| Short name | T360 |
| Test name | |
| Test status | |
| Simulation time | 4968853256 ps |
| CPU time | 376.96 seconds |
| Started | Aug 24 12:19:02 PM UTC 24 |
| Finished | Aug 24 12:25:24 PM UTC 24 |
| Peak memory | 637236 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/default/simv +use_jtag_dmi=1 +sw_build_device=sim_dv +sw_images=rv_dm_ndm _reset_req_when_cpu_halted_rma:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3780576421 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rv_dm_ndm_re set_when_cpu_halted_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asi c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_rv_dm_ndm_reset_req_when_cpu_halted.3780576421 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/1.chip_sw_rv_dm_ndm_reset_req_when_cpu_halted/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_rv_plic_smoketest.3470337326 |
| Short name | T1062 |
| Test name | |
| Test status | |
| Simulation time | 2704294272 ps |
| CPU time | 205.3 seconds |
| Started | Aug 24 12:45:45 PM UTC 24 |
| Finished | Aug 24 12:49:13 PM UTC 24 |
| Peak memory | 624764 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=rv_plic_smoketest:1:new_r ules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +n tb_random_seed=3470337326 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a ssert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_ sw_rv_plic_smoketest.3470337326 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/1.chip_sw_rv_plic_smoketest/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_rv_timer_irq.2374137142 |
| Short name | T957 |
| Test name | |
| Test status | |
| Simulation time | 2382598936 ps |
| CPU time | 166.55 seconds |
| Started | Aug 24 11:26:12 AM UTC 24 |
| Finished | Aug 24 11:29:02 AM UTC 24 |
| Peak memory | 624820 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=rv_timer_smoketest:1:new_ rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl + ntb_random_seed=2374137142 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip _sw_rv_timer_irq.2374137142 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/1.chip_sw_rv_timer_irq/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_rv_timer_smoketest.378286150 |
| Short name | T1061 |
| Test name | |
| Test status | |
| Simulation time | 2815473840 ps |
| CPU time | 164.24 seconds |
| Started | Aug 24 12:46:02 PM UTC 24 |
| Finished | Aug 24 12:48:49 PM UTC 24 |
| Peak memory | 624800 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=rv_timer_smoketest:1:new_ rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl + ntb_random_seed=378286150 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a ssert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_ sw_rv_timer_smoketest.378286150 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/1.chip_sw_rv_timer_smoketest/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_rv_timer_systick_test.1648072015 |
| Short name | T1096 |
| Test name | |
| Test status | |
| Simulation time | 39075442432 ps |
| CPU time | 6860.44 seconds |
| Started | Aug 24 11:27:30 AM UTC 24 |
| Finished | Aug 24 01:23:01 PM UTC 24 |
| Peak memory | 629672 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=50_000_000 +sw_build_device=sim_dv +sw_i mages=rv_timer_systick_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor kspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1648072015 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_rv_timer_systick_test.1648072015 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/1.chip_sw_rv_timer_systick_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_sensor_ctrl_alert.14863500 |
| Short name | T168 |
| Test name | |
| Test status | |
| Simulation time | 4580389440 ps |
| CPU time | 397.41 seconds |
| Started | Aug 24 12:02:13 PM UTC 24 |
| Finished | Aug 24 12:08:55 PM UTC 24 |
| Peak memory | 626620 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=40_000_000 +sw_build_device=sim_dv +sw_i mages=sensor_ctrl_alert_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo rkspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=14863500 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_sensor_ctrl_alert.14863500 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/1.chip_sw_sensor_ctrl_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_sensor_ctrl_status.3756532713 |
| Short name | T346 |
| Test name | |
| Test status | |
| Simulation time | 3132579731 ps |
| CPU time | 208.94 seconds |
| Started | Aug 24 12:02:56 PM UTC 24 |
| Finished | Aug 24 12:06:28 PM UTC 24 |
| Peak memory | 626804 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=40_000_000 +sw_build_device=sim_dv +sw_i mages=sensor_ctrl_status_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3756532713 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sensor_ctrl_s tatus_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_sensor_ctrl_status.3756532713 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/1.chip_sw_sensor_ctrl_status/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_sleep_pin_retention.2466101096 |
| Short name | T71 |
| Test name | |
| Test status | |
| Simulation time | 3441017476 ps |
| CPU time | 229.69 seconds |
| Started | Aug 24 10:56:17 AM UTC 24 |
| Finished | Aug 24 11:00:11 AM UTC 24 |
| Peak memory | 624632 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=sleep_pin_retention_test: 1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim .tcl +ntb_random_seed=2466101096 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sleep_pin_retention_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev /null -cm_name 1.chip_sw_sleep_pin_retention.2466101096 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/1.chip_sw_sleep_pin_retention/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_sleep_pwm_pulses.1484209894 |
| Short name | T937 |
| Test name | |
| Test status | |
| Simulation time | 8901178890 ps |
| CPU time | 861.31 seconds |
| Started | Aug 24 10:57:11 AM UTC 24 |
| Finished | Aug 24 11:11:42 AM UTC 24 |
| Peak memory | 626752 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=sleep_pwm_pulses_test:1:n ew_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc l +ntb_random_seed=1484209894 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_pwm_pulses_vseq +en_cov=1 -cm line+cond+fsm+tg l+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_na me 1.chip_sw_sleep_pwm_pulses.1484209894 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/1.chip_sw_sleep_pwm_pulses/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_sleep_sram_ret_contents_no_scramble.977636812 |
| Short name | T1006 |
| Test name | |
| Test status | |
| Simulation time | 7249295896 ps |
| CPU time | 413.1 seconds |
| Started | Aug 24 12:01:30 PM UTC 24 |
| Finished | Aug 24 12:08:28 PM UTC 24 |
| Peak memory | 626908 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=20_000_000 +en_scb_tl_err_chk=0 +bypass_ alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=sram_ctrl_sleep_sram_ret_contents_no_scramble_test:1:new_rules,test_rom:0 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=977636812 - assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r epo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_sleep_sram_ret_contents_ no_scramble.977636812 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/1.chip_sw_sleep_sram_ret_contents_no_scramble/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_sleep_sram_ret_contents_scramble.120762311 |
| Short name | T286 |
| Test name | |
| Test status | |
| Simulation time | 8533659472 ps |
| CPU time | 468.45 seconds |
| Started | Aug 24 12:01:30 PM UTC 24 |
| Finished | Aug 24 12:09:24 PM UTC 24 |
| Peak memory | 626684 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=20_000_000 +en_scb_tl_err_chk=0 +bypass_ alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=sram_ctrl_sleep_sram_ret_contents_scramble_test:1:new_rules,test_rom:0 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=120762311 -ass ert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo /scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_sleep_sram_ret_contents_scramble.120762311 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/1.chip_sw_sleep_sram_ret_contents_scramble/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_spi_device_pass_through.754227085 |
| Short name | T238 |
| Test name | |
| Test status | |
| Simulation time | 5826156370 ps |
| CPU time | 415.61 seconds |
| Started | Aug 24 11:03:25 AM UTC 24 |
| Finished | Aug 24 11:10:26 AM UTC 24 |
| Peak memory | 641420 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=spi_passthrough_test:1:ne w_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=754227085 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_spi_passthrough_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm _name 1.chip_sw_spi_device_pass_through.754227085 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/1.chip_sw_spi_device_pass_through/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_spi_device_pass_through_collision.2739826219 |
| Short name | T239 |
| Test name | |
| Test status | |
| Simulation time | 4387541905 ps |
| CPU time | 414.93 seconds |
| Started | Aug 24 11:04:39 AM UTC 24 |
| Finished | Aug 24 11:11:39 AM UTC 24 |
| Peak memory | 641344 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=spi_passthrough_test:1:ne w_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2739826219 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_spi_passthrough_collision_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /d ev/null -cm_name 1.chip_sw_spi_device_pass_through_collision.2739826219 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/1.chip_sw_spi_device_pass_through_collision/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_spi_device_pinmux_sleep_retention.4014287901 |
| Short name | T66 |
| Test name | |
| Test status | |
| Simulation time | 3702720882 ps |
| CPU time | 170.42 seconds |
| Started | Aug 24 11:03:14 AM UTC 24 |
| Finished | Aug 24 11:06:07 AM UTC 24 |
| Peak memory | 637548 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=spi_device_sleep_test:1:n ew_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc l +ntb_random_seed=4014287901 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_spi_device_pinmux_sleep_retention_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default.vdb - cm_log /dev/null -cm_name 1.chip_sw_spi_device_pinmux_sleep_retention.4014287901 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/1.chip_sw_spi_device_pinmux_sleep_retention/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_spi_device_tpm.1950494928 |
| Short name | T55 |
| Test name | |
| Test status | |
| Simulation time | 3158354533 ps |
| CPU time | 251.76 seconds |
| Started | Aug 24 11:01:46 AM UTC 24 |
| Finished | Aug 24 11:06:01 AM UTC 24 |
| Peak memory | 637232 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=spi_device_tpm_tx_rx_test :1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/si m.tcl +ntb_random_seed=1950494928 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_spi_device_tpm_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/nul l -cm_name 1.chip_sw_spi_device_tpm.1950494928 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/1.chip_sw_spi_device_tpm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_spi_host_tx_rx.3126427578 |
| Short name | T51 |
| Test name | |
| Test status | |
| Simulation time | 3095317050 ps |
| CPU time | 194.65 seconds |
| Started | Aug 24 11:03:12 AM UTC 24 |
| Finished | Aug 24 11:06:30 AM UTC 24 |
| Peak memory | 624692 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=spi_host_tx_rx_test:1:new _rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3126427578 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_spi_host_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_ name 1.chip_sw_spi_host_tx_rx.3126427578 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/1.chip_sw_spi_host_tx_rx/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_sram_ctrl_execution_main.1062919102 |
| Short name | T305 |
| Test name | |
| Test status | |
| Simulation time | 7123221259 ps |
| CPU time | 566.99 seconds |
| Started | Aug 24 12:01:29 PM UTC 24 |
| Finished | Aug 24 12:11:03 PM UTC 24 |
| Peak memory | 626820 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=sram_ctrl_execution_main_ test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=1062919102 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sram_ctrl_execution_main_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -c m_log /dev/null -cm_name 1.chip_sw_sram_ctrl_execution_main.1062919102 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/1.chip_sw_sram_ctrl_execution_main/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_sram_ctrl_scrambled_access.3567522001 |
| Short name | T284 |
| Test name | |
| Test status | |
| Simulation time | 5070146040 ps |
| CPU time | 502.64 seconds |
| Started | Aug 24 11:59:46 AM UTC 24 |
| Finished | Aug 24 12:08:15 PM UTC 24 |
| Peak memory | 627140 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=12_000_000 +en_scb_tl_err_chk=0 +bypass_ alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=sram_ctrl_scrambled_access_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled= 1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3567522001 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sram_ctrl_scrambled_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac es/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_sram_ctrl_scrambled_ access.3567522001 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/1.chip_sw_sram_ctrl_scrambled_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_sram_ctrl_scrambled_access_jitter_en.2108488509 |
| Short name | T285 |
| Test name | |
| Test status | |
| Simulation time | 4811786826 ps |
| CPU time | 450.54 seconds |
| Started | Aug 24 12:00:41 PM UTC 24 |
| Finished | Aug 24 12:08:18 PM UTC 24 |
| Peak memory | 626952 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=12_000_000 +bypass_alert_ready_to_end_ch eck=1 +en_jitter=1 +en_scb_tl_err_chk=0 +sw_build_device=sim_dv +sw_images=sram_ctrl_scrambled_access_test:1:new_rules,test_rom:0 +cdc_instrumenta tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2108488509 -asser t nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sram_ctrl_scrambled_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_sram_ct rl_scrambled_access_jitter_en.2108488509 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/1.chip_sw_sram_ctrl_scrambled_access_jitter_en/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq.36338402 |
| Short name | T455 |
| Test name | |
| Test status | |
| Simulation time | 5152676848 ps |
| CPU time | 391.65 seconds |
| Started | Aug 24 12:26:21 PM UTC 24 |
| Finished | Aug 24 12:32:58 PM UTC 24 |
| Peak memory | 626856 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/default/simv +mem_sel=main +sw_test_timeout_ns=12_000_000 +bypass_alert_r eady_to_end_check=1 +en_jitter=1 +en_scb_tl_err_chk=0 +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +sw_images=sram_ctrl_scrambled_access_test:1:ne w_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=36338402 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sram_ctrl_scrambled_access_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /de v/null -cm_name 1.chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq.36338402 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/1.chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_sram_ctrl_smoketest.68110837 |
| Short name | T1065 |
| Test name | |
| Test status | |
| Simulation time | 3131496862 ps |
| CPU time | 179.05 seconds |
| Started | Aug 24 12:46:54 PM UTC 24 |
| Finished | Aug 24 12:49:56 PM UTC 24 |
| Peak memory | 626872 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=sram_ctrl_smoketest:1:new _rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=68110837 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a ssert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_ sw_sram_ctrl_smoketest.68110837 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/1.chip_sw_sram_ctrl_smoketest/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_sysrst_ctrl_ec_rst_l.4003202060 |
| Short name | T1010 |
| Test name | |
| Test status | |
| Simulation time | 20409037022 ps |
| CPU time | 2508.6 seconds |
| Started | Aug 24 11:29:46 AM UTC 24 |
| Finished | Aug 24 12:12:02 PM UTC 24 |
| Peak memory | 629984 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=sysrst_ctrl_ec_rst_l_test :1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/si m.tcl +ntb_random_seed=4003202060 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sysrst_ctrl_ec_rst_l_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /d ev/null -cm_name 1.chip_sw_sysrst_ctrl_ec_rst_l.4003202060 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/1.chip_sw_sysrst_ctrl_ec_rst_l/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_sysrst_ctrl_in_irq.3708329815 |
| Short name | T247 |
| Test name | |
| Test status | |
| Simulation time | 4493220182 ps |
| CPU time | 395.75 seconds |
| Started | Aug 24 11:28:25 AM UTC 24 |
| Finished | Aug 24 11:35:07 AM UTC 24 |
| Peak memory | 629236 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=sysrst_ctrl_in_irq_test:1 :new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim. tcl +ntb_random_seed=3708329815 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sysrst_ctrl_in_irq_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/n ull -cm_name 1.chip_sw_sysrst_ctrl_in_irq.3708329815 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/1.chip_sw_sysrst_ctrl_in_irq/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_sysrst_ctrl_inputs.169924321 |
| Short name | T245 |
| Test name | |
| Test status | |
| Simulation time | 3288054202 ps |
| CPU time | 217.87 seconds |
| Started | Aug 24 11:28:04 AM UTC 24 |
| Finished | Aug 24 11:31:46 AM UTC 24 |
| Peak memory | 628972 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=sysrst_ctrl_inputs_test:1 :new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim. tcl +ntb_random_seed=169924321 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sysrst_ctrl_inputs_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/nu ll -cm_name 1.chip_sw_sysrst_ctrl_inputs.169924321 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/1.chip_sw_sysrst_ctrl_inputs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_sysrst_ctrl_outputs.316466774 |
| Short name | T246 |
| Test name | |
| Test status | |
| Simulation time | 3811587416 ps |
| CPU time | 256.75 seconds |
| Started | Aug 24 11:29:46 AM UTC 24 |
| Finished | Aug 24 11:34:06 AM UTC 24 |
| Peak memory | 624816 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=sysrst_ctrl_outputs_test: 1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim .tcl +ntb_random_seed=316466774 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sysrst_ctrl_outputs_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/ null -cm_name 1.chip_sw_sysrst_ctrl_outputs.316466774 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/1.chip_sw_sysrst_ctrl_outputs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_sysrst_ctrl_reset.410045564 |
| Short name | T248 |
| Test name | |
| Test status | |
| Simulation time | 23014938156 ps |
| CPU time | 1262.13 seconds |
| Started | Aug 24 11:29:26 AM UTC 24 |
| Finished | Aug 24 11:50:42 AM UTC 24 |
| Peak memory | 631348 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=36_000_000 +sw_build_device=sim_dv +sw_i mages=sysrst_ctrl_reset_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo rkspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=410045564 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sysrst_ctrl_res et_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_sysrst_ctrl_reset.410045564 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/1.chip_sw_sysrst_ctrl_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_sysrst_ctrl_ulp_z3_wakeup.908900536 |
| Short name | T53 |
| Test name | |
| Test status | |
| Simulation time | 5892316260 ps |
| CPU time | 320.57 seconds |
| Started | Aug 24 11:28:38 AM UTC 24 |
| Finished | Aug 24 11:34:03 AM UTC 24 |
| Peak memory | 627008 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=sysrst_ctrl_ulp_z3_wakeup _test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/too ls/sim.tcl +ntb_random_seed=908900536 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sysrst_ctrl_ulp_z3_wakeup_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default.vdb - cm_log /dev/null -cm_name 1.chip_sw_sysrst_ctrl_ulp_z3_wakeup.908900536 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/1.chip_sw_sysrst_ctrl_ulp_z3_wakeup/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_uart_rand_baudrate.116995054 |
| Short name | T944 |
| Test name | |
| Test status | |
| Simulation time | 8894134916 ps |
| CPU time | 1149.2 seconds |
| Started | Aug 24 10:59:01 AM UTC 24 |
| Finished | Aug 24 11:18:23 AM UTC 24 |
| Peak memory | 636868 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=80_000_000 +calibrate_usb_clk=1 +sw_buil d_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=116995054 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_u art_rand_baudrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_uart_rand_baudrate.116995054 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/1.chip_sw_uart_rand_baudrate/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_uart_smoketest.4156981730 |
| Short name | T1067 |
| Test name | |
| Test status | |
| Simulation time | 2714207000 ps |
| CPU time | 208.76 seconds |
| Started | Aug 24 12:46:55 PM UTC 24 |
| Finished | Aug 24 12:50:27 PM UTC 24 |
| Peak memory | 624696 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=uart_smoketest:1:new_rule s,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ random_seed=4156981730 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.ch ip_sw_uart_smoketest.4156981730 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/1.chip_sw_uart_smoketest/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_uart_tx_rx.382299711 |
| Short name | T372 |
| Test name | |
| Test status | |
| Simulation time | 3903020736 ps |
| CPU time | 420.17 seconds |
| Started | Aug 24 10:57:10 AM UTC 24 |
| Finished | Aug 24 11:04:15 AM UTC 24 |
| Peak memory | 637088 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/default/simv +uart_idx=0 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw _images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=382299711 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_tx_rx_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default.vd b -cm_log /dev/null -cm_name 1.chip_sw_uart_tx_rx.382299711 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/1.chip_sw_uart_tx_rx/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_uart_tx_rx_alt_clk_freq.3527774140 |
| Short name | T936 |
| Test name | |
| Test status | |
| Simulation time | 3405076027 ps |
| CPU time | 362.19 seconds |
| Started | Aug 24 11:00:14 AM UTC 24 |
| Finished | Aug 24 11:06:21 AM UTC 24 |
| Peak memory | 637052 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=80_000_000 +chip_clock_source=ChipClockS ourceExternal96Mhz +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3527774140 -assert nopostproc +UV M_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_baudrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr atch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_uart_tx_rx_alt_clk_freq.3527774140 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/1.chip_sw_uart_tx_rx_alt_clk_freq/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_uart_tx_rx_alt_clk_freq_low_speed.2899634991 |
| Short name | T373 |
| Test name | |
| Test status | |
| Simulation time | 9103906865 ps |
| CPU time | 676.45 seconds |
| Started | Aug 24 11:00:41 AM UTC 24 |
| Finished | Aug 24 11:12:05 AM UTC 24 |
| Peak memory | 637108 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=80_000_000 +calibrate_usb_clk=1 +chip_cl ock_source=ChipClockSourceExternal48Mhz +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2899634991 -assert nopostproc +UV M_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_baudrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr atch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_uart_tx_rx_alt_clk_freq_low_speed.2899634991 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/1.chip_sw_uart_tx_rx_alt_clk_freq_low_speed/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_uart_tx_rx_bootstrap.2842322799 |
| Short name | T1216 |
| Test name | |
| Test status | |
| Simulation time | 78785630288 ps |
| CPU time | 13217.5 seconds |
| Started | Aug 24 10:58:00 AM UTC 24 |
| Finished | Aug 24 02:40:38 PM UTC 24 |
| Peak memory | 656680 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/default/simv +use_spi_load_bootstrap=1 +calibrate_usb_clk=1 +test_timeout _ns=160_000_000 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2842322799 -assert nopostproc +UVM_TESTNAME=chip_base_tes t +UVM_TEST_SEQ=chip_sw_uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/ch ip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_uart_tx_rx_bootstrap.2842322799 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/1.chip_sw_uart_tx_rx_bootstrap/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_uart_tx_rx_idx1.2782485713 |
| Short name | T132 |
| Test name | |
| Test status | |
| Simulation time | 3630113406 ps |
| CPU time | 411.03 seconds |
| Started | Aug 24 10:57:11 AM UTC 24 |
| Finished | Aug 24 11:04:08 AM UTC 24 |
| Peak memory | 637048 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/default/simv +uart_idx=1 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw _images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2782485713 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_tx_rx_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 1.chip_sw_uart_tx_rx_idx1.2782485713 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/1.chip_sw_uart_tx_rx_idx1/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_uart_tx_rx_idx2.2730789988 |
| Short name | T935 |
| Test name | |
| Test status | |
| Simulation time | 4406788756 ps |
| CPU time | 442.53 seconds |
| Started | Aug 24 10:57:52 AM UTC 24 |
| Finished | Aug 24 11:05:20 AM UTC 24 |
| Peak memory | 637084 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/default/simv +uart_idx=2 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw _images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2730789988 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_tx_rx_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 1.chip_sw_uart_tx_rx_idx2.2730789988 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/1.chip_sw_uart_tx_rx_idx2/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_uart_tx_rx_idx3.100748039 |
| Short name | T80 |
| Test name | |
| Test status | |
| Simulation time | 4146521826 ps |
| CPU time | 438.95 seconds |
| Started | Aug 24 10:58:00 AM UTC 24 |
| Finished | Aug 24 11:05:24 AM UTC 24 |
| Peak memory | 637340 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/default/simv +uart_idx=3 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw _images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=100748039 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_tx_rx_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default.vd b -cm_log /dev/null -cm_name 1.chip_sw_uart_tx_rx_idx3.100748039 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/1.chip_sw_uart_tx_rx_idx3/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_tap_straps_dev.1056973882 |
| Short name | T1028 |
| Test name | |
| Test status | |
| Simulation time | 3883762651 ps |
| CPU time | 197.46 seconds |
| Started | Aug 24 12:19:43 PM UTC 24 |
| Finished | Aug 24 12:23:03 PM UTC 24 |
| Peak memory | 640956 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/default/simv +use_otp_image=OtpTypeLcStDev +create_jtag_riscv_map=1 +sw_b uild_device=sim_dv +sw_images=example_test_from_rom:0:test_in_rom:new_rules +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1056973882 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SE Q=chip_tap_straps_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_tap_straps_dev.1056973882 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/1.chip_tap_straps_dev/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_tap_straps_prod.2679565263 |
| Short name | T1045 |
| Test name | |
| Test status | |
| Simulation time | 13546665574 ps |
| CPU time | 916.47 seconds |
| Started | Aug 24 12:22:27 PM UTC 24 |
| Finished | Aug 24 12:37:54 PM UTC 24 |
| Peak memory | 644492 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/default/simv +use_otp_image=OtpTypeLcStProd +create_jtag_riscv_map=1 +sw_ build_device=sim_dv +sw_images=example_test_from_rom:0:test_in_rom:new_rules +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2679565263 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_S EQ=chip_tap_straps_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_tap_straps_prod.2679565263 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/1.chip_tap_straps_prod/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_tap_straps_rma.1494933170 |
| Short name | T91 |
| Test name | |
| Test status | |
| Simulation time | 4550958554 ps |
| CPU time | 222.6 seconds |
| Started | Aug 24 12:21:53 PM UTC 24 |
| Finished | Aug 24 12:25:39 PM UTC 24 |
| Peak memory | 643516 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/default/simv +create_jtag_riscv_map=1 +sw_build_device=sim_dv +sw_images= example_test_from_rom:0:test_in_rom:new_rules +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac es/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1494933170 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_tap_straps_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default.vdb - cm_log /dev/null -cm_name 1.chip_tap_straps_rma.1494933170 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/1.chip_tap_straps_rma/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_tap_straps_testunlock0.1313299830 |
| Short name | T92 |
| Test name | |
| Test status | |
| Simulation time | 6312330743 ps |
| CPU time | 363.89 seconds |
| Started | Aug 24 12:20:56 PM UTC 24 |
| Finished | Aug 24 12:27:04 PM UTC 24 |
| Peak memory | 651720 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/default/simv +use_otp_image=OtpTypeLcStTestUnlocked0 +create_jtag_riscv_m ap=1 +sw_build_device=sim_dv +sw_images=example_test_from_rom:0:test_in_rom:new_rules +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1313299830 -assert nopostproc +UVM_TESTNAME=chip_base_test +U VM_TEST_SEQ=chip_tap_straps_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/chip_earl grey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_tap_straps_testunlock0.1313299830 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/1.chip_tap_straps_testunlock0/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/1.rom_e2e_asm_init_dev.62748448 |
| Short name | T1094 |
| Test name | |
| Test status | |
| Simulation time | 15933132391 ps |
| CPU time | 3036.99 seconds |
| Started | Aug 24 12:31:06 PM UTC 24 |
| Finished | Aug 24 01:22:16 PM UTC 24 |
| Peak memory | 629996 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/default/simv +use_otp_image=OtpTypeCustom +sw_test_timeout_ns=20000000 +s w_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_prod_key_0:1:ot_flash_binary,otp_img_e2e_bootstrap_entry_dev:4,mask_rom:0 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=62748448 -a ssert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rom_e2e_asm_init_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_e2e_asm_init_dev.62748448 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/1.rom_e2e_asm_init_dev/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/1.rom_e2e_asm_init_prod.609385514 |
| Short name | T1104 |
| Test name | |
| Test status | |
| Simulation time | 15639282184 ps |
| CPU time | 3187.92 seconds |
| Started | Aug 24 12:31:14 PM UTC 24 |
| Finished | Aug 24 01:24:56 PM UTC 24 |
| Peak memory | 628060 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/default/simv +use_otp_image=OtpTypeCustom +sw_test_timeout_ns=20000000 +s w_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_prod_key_0:1:ot_flash_binary,otp_img_e2e_bootstrap_entry_prod:4,mask_rom:0 +cdc_inst rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=609385514 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rom_e2e_asm_init_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_e2e_asm_init_prod.609385514 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/1.rom_e2e_asm_init_prod/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/1.rom_e2e_asm_init_prod_end.29243301 |
| Short name | T1100 |
| Test name | |
| Test status | |
| Simulation time | 15334724097 ps |
| CPU time | 3150.32 seconds |
| Started | Aug 24 12:31:21 PM UTC 24 |
| Finished | Aug 24 01:24:26 PM UTC 24 |
| Peak memory | 628032 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/default/simv +use_otp_image=OtpTypeCustom +sw_test_timeout_ns=20000000 +s w_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_prod_key_0:1:ot_flash_binary,otp_img_e2e_bootstrap_entry_prod_end:4,mask_rom:0 +cdc_ instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=292433 01 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rom_e2e_asm_init_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_e2e_asm_init _prod_end.29243301 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/1.rom_e2e_asm_init_prod_end/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/1.rom_e2e_asm_init_rma.1812973681 |
| Short name | T1095 |
| Test name | |
| Test status | |
| Simulation time | 14987232010 ps |
| CPU time | 3009.57 seconds |
| Started | Aug 24 12:32:08 PM UTC 24 |
| Finished | Aug 24 01:22:49 PM UTC 24 |
| Peak memory | 628044 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/default/simv +use_otp_image=OtpTypeCustom +sw_test_timeout_ns=20000000 +s w_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_prod_key_0:1:ot_flash_binary,otp_img_e2e_bootstrap_entry_rma:4,mask_rom:0 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1812973681 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rom_e2e_asm_init_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_e2e_asm_init_rma.1812973681 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/1.rom_e2e_asm_init_rma/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/1.rom_e2e_asm_init_test_unlocked0.2426962134 |
| Short name | T1080 |
| Test name | |
| Test status | |
| Simulation time | 11576062799 ps |
| CPU time | 2328.07 seconds |
| Started | Aug 24 12:30:54 PM UTC 24 |
| Finished | Aug 24 01:10:07 PM UTC 24 |
| Peak memory | 630308 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/default/simv +use_otp_image=OtpTypeCustom +sw_test_timeout_ns=410_000_000 +sw_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_prod_key_0:1:ot_flash_binary,otp_img_e2e_bootstrap_entry_test_unlocked0:4,mask_ro m:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_se ed=2426962134 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rom_e2e_asm_init_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a ssert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_e 2e_asm_init_test_unlocked0.2426962134 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/1.rom_e2e_asm_init_test_unlocked0/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/1.rom_e2e_keymgr_init_rom_ext_invalid_meas.2055630805 |
| Short name | T1106 |
| Test name | |
| Test status | |
| Simulation time | 15503026310 ps |
| CPU time | 3003.03 seconds |
| Started | Aug 24 12:35:24 PM UTC 24 |
| Finished | Aug 24 01:26:00 PM UTC 24 |
| Peak memory | 627508 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=40_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=rom_e2e_keymgr_init_otp_invalid_meas:1:new_rules,otp_img_keymgr_otp_invalid_meas:4,mask_rom:0 +cdc_instrumentat ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2055630805 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc ratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_e2e_keymgr_init_rom_ext_invalid_meas.2055630805 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/1.rom_e2e_keymgr_init_rom_ext_invalid_meas/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/1.rom_e2e_keymgr_init_rom_ext_meas.146477394 |
| Short name | T1091 |
| Test name | |
| Test status | |
| Simulation time | 15071135000 ps |
| CPU time | 2857.15 seconds |
| Started | Aug 24 12:33:39 PM UTC 24 |
| Finished | Aug 24 01:21:46 PM UTC 24 |
| Peak memory | 624692 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=40_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=rom_e2e_keymgr_init_otp_meas:1:new_rules,otp_img_keymgr_otp_meas:4,mask_rom:0 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=146477394 -assert nopostproc +UVM_ TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_e2e_keymgr_init_rom_ext_meas.146477394 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/1.rom_e2e_keymgr_init_rom_ext_meas/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/1.rom_e2e_keymgr_init_rom_ext_no_meas.2477713390 |
| Short name | T1098 |
| Test name | |
| Test status | |
| Simulation time | 14894848856 ps |
| CPU time | 3005.34 seconds |
| Started | Aug 24 12:33:39 PM UTC 24 |
| Finished | Aug 24 01:24:18 PM UTC 24 |
| Peak memory | 624704 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=40_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=rom_e2e_keymgr_init_otp_no_meas:1:new_rules,otp_img_keymgr_otp_no_meas:4,mask_rom:0 +cdc_instrumentation_enable d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2477713390 -assert nopostpro c +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_e2e_keymgr_init_rom_ext_no_meas.2477713390 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/1.rom_e2e_keymgr_init_rom_ext_no_meas/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/1.rom_e2e_self_hash.3428965044 |
| Short name | T1168 |
| Test name | |
| Test status | |
| Simulation time | 26465435924 ps |
| CPU time | 5450.04 seconds |
| Started | Aug 24 12:38:32 PM UTC 24 |
| Finished | Aug 24 02:10:21 PM UTC 24 |
| Peak memory | 627852 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=200_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=rom_e2e_self_hash_test:1:new_rules,otp_img_sigverify_spx_prod:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3428965044 -assert nopostproc +UVM_T ESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_e2e_self_hash.3428965044 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/1.rom_e2e_self_hash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/1.rom_e2e_shutdown_exception_c.2342091815 |
| Short name | T1088 |
| Test name | |
| Test status | |
| Simulation time | 14391187124 ps |
| CPU time | 2977.01 seconds |
| Started | Aug 24 12:30:36 PM UTC 24 |
| Finished | Aug 24 01:20:45 PM UTC 24 |
| Peak memory | 630060 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=40000000 +use_otp_image=OtpTypeCustom +s w_build_device=sim_dv +sw_images=rom_e2e_shutdown_exception_c:1:new_rules,otp_img_secret2_locked_rma:4,mask_rom:0 +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2342091815 -assert nopostproc +UV M_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rom_e2e_shutdown_exception_c_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace s/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_e2e_shutdown_exception_c.2342091815 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/1.rom_e2e_shutdown_exception_c/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/1.rom_e2e_shutdown_output.3907444878 |
| Short name | T1084 |
| Test name | |
| Test status | |
| Simulation time | 25322441933 ps |
| CPU time | 2670.85 seconds |
| Started | Aug 24 12:30:51 PM UTC 24 |
| Finished | Aug 24 01:15:51 PM UTC 24 |
| Peak memory | 629928 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=20000000 +use_otp_image=OtpTypeCustom +s w_build_device=sim_dv +sw_images=empty_test_slot_a_unsigned:1:ot_flash_binary,otp_img_shutdown_output_test_unlocked0:4,mask_rom:0 +cdc_instrumenta tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3907444878 -asser t nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rom_e2e_shutdown_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_e2e_shutdown_output.3907444878 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/1.rom_e2e_shutdown_output/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/1.rom_e2e_smoke.587669565 |
| Short name | T1089 |
| Test name | |
| Test status | |
| Simulation time | 15121951480 ps |
| CPU time | 3036.14 seconds |
| Started | Aug 24 12:29:39 PM UTC 24 |
| Finished | Aug 24 01:20:48 PM UTC 24 |
| Peak memory | 627748 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=40000000 +use_otp_image=OtpTypeCustom +s w_build_device=sim_dv +sw_images=rom_e2e_smoke:1:new_rules,otp_img_secret2_locked_rma:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=587669565 -assert nopostproc +UVM_TESTNAME=chip_ base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/ chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_e2e_smoke.587669565 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/1.rom_e2e_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/1.rom_e2e_static_critical.1558305889 |
| Short name | T1110 |
| Test name | |
| Test status | |
| Simulation time | 17858663112 ps |
| CPU time | 3378.54 seconds |
| Started | Aug 24 12:32:10 PM UTC 24 |
| Finished | Aug 24 01:29:05 PM UTC 24 |
| Peak memory | 627740 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=40000000 +use_otp_image=OtpTypeCustom +s w_build_device=sim_dv +sw_images=rom_e2e_static_critical:1:new_rules,otp_img_secret2_locked_rma:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1558305889 -assert nopostproc +UVM_TES TNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_e2e_static_critical.1558305889 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/1.rom_e2e_static_critical/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/1.rom_keymgr_functest.1647466157 |
| Short name | T1052 |
| Test name | |
| Test status | |
| Simulation time | 5061359008 ps |
| CPU time | 305.18 seconds |
| Started | Aug 24 12:38:30 PM UTC 24 |
| Finished | Aug 24 12:43:39 PM UTC 24 |
| Peak memory | 626812 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=10_000_000 +sw_build_device=sim_dv +sw_i mages=keymgr_functest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace s/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1647466157 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_l og /dev/null -cm_name 1.rom_keymgr_functest.1647466157 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/1.rom_keymgr_functest/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/1.rom_raw_unlock.2844362313 |
| Short name | T190 |
| Test name | |
| Test status | |
| Simulation time | 5051595771 ps |
| CPU time | 169.72 seconds |
| Started | Aug 24 12:36:12 PM UTC 24 |
| Finished | Aug 24 12:39:04 PM UTC 24 |
| Peak memory | 638740 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/default/simv +do_creator_sw_cfg_ast_cfg=0 +sw_test_timeout_ns=200_000_000 +use_otp_image=OtpTypeLcStRaw +chip_clock_source=ChipClockSourceExternal48Mhz +rom_prod_mode=1 +use_jtag_dmi=1 +sw_build_device=sim_dv +sw_images =empty_test_slot_a_fake_ecdsa_test_key_0:1:ot_flash_binary,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2844362313 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip _sw_lc_raw_unlock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_raw_unlock.2844362313 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/1.rom_raw_unlock/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/1.rom_volatile_raw_unlock.864460594 |
| Short name | T1044 |
| Test name | |
| Test status | |
| Simulation time | 2492550722 ps |
| CPU time | 93.03 seconds |
| Started | Aug 24 12:36:11 PM UTC 24 |
| Finished | Aug 24 12:37:46 PM UTC 24 |
| Peak memory | 634296 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=200_000_000 +use_otp_image=OtpTypeLcStRa w +chip_clock_source=ChipClockSourceExternal48Mhz +rom_prod_mode=1 +sw_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_test_key_0:1:ot _flash_binary,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/s im.tcl +ntb_random_seed=864460594 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_volatile_raw_unlock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_volatile_raw_unlock.864460594 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/1.rom_volatile_raw_unlock/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/10.chip_sw_lc_ctrl_transition.2769339345 |
| Short name | T123 |
| Test name | |
| Test status | |
| Simulation time | 9046599690 ps |
| CPU time | 649.63 seconds |
| Started | Aug 24 03:39:35 PM UTC 24 |
| Finished | Aug 24 03:50:33 PM UTC 24 |
| Peak memory | 639308 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=lc_ctrl_transition_test:1 :new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim. tcl +ntb_random_seed=2769339345 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_ctrl_transition_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/n ull -cm_name 10.chip_sw_lc_ctrl_transition.2769339345 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/10.chip_sw_lc_ctrl_transition/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/10.chip_sw_uart_rand_baudrate.2161645702 |
| Short name | T1309 |
| Test name | |
| Test status | |
| Simulation time | 8817306736 ps |
| CPU time | 1111.9 seconds |
| Started | Aug 24 03:38:32 PM UTC 24 |
| Finished | Aug 24 03:57:16 PM UTC 24 |
| Peak memory | 636864 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=80_000_000 +calibrate_usb_clk=1 +sw_buil d_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2161645702 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_ uart_rand_baudrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.chip_sw_uart_rand_baudrate.2161645702 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/10.chip_sw_uart_rand_baudrate/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/11.chip_sw_lc_ctrl_transition.2359346099 |
| Short name | T116 |
| Test name | |
| Test status | |
| Simulation time | 5175512138 ps |
| CPU time | 340.69 seconds |
| Started | Aug 24 03:40:41 PM UTC 24 |
| Finished | Aug 24 03:46:26 PM UTC 24 |
| Peak memory | 639372 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=lc_ctrl_transition_test:1 :new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim. tcl +ntb_random_seed=2359346099 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_ctrl_transition_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/n ull -cm_name 11.chip_sw_lc_ctrl_transition.2359346099 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/11.chip_sw_lc_ctrl_transition/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/11.chip_sw_uart_rand_baudrate.1030954723 |
| Short name | T117 |
| Test name | |
| Test status | |
| Simulation time | 4052683280 ps |
| CPU time | 376.37 seconds |
| Started | Aug 24 03:40:41 PM UTC 24 |
| Finished | Aug 24 03:47:02 PM UTC 24 |
| Peak memory | 637056 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=80_000_000 +calibrate_usb_clk=1 +sw_buil d_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1030954723 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_ uart_rand_baudrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.chip_sw_uart_rand_baudrate.1030954723 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/11.chip_sw_uart_rand_baudrate/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/12.chip_sw_lc_ctrl_transition.3843689910 |
| Short name | T121 |
| Test name | |
| Test status | |
| Simulation time | 6000814556 ps |
| CPU time | 352.44 seconds |
| Started | Aug 24 03:43:50 PM UTC 24 |
| Finished | Aug 24 03:49:47 PM UTC 24 |
| Peak memory | 639540 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=lc_ctrl_transition_test:1 :new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim. tcl +ntb_random_seed=3843689910 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_ctrl_transition_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/n ull -cm_name 12.chip_sw_lc_ctrl_transition.3843689910 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/12.chip_sw_lc_ctrl_transition/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/12.chip_sw_uart_rand_baudrate.601530532 |
| Short name | T1305 |
| Test name | |
| Test status | |
| Simulation time | 4211862912 ps |
| CPU time | 471.57 seconds |
| Started | Aug 24 03:43:13 PM UTC 24 |
| Finished | Aug 24 03:51:10 PM UTC 24 |
| Peak memory | 636872 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=80_000_000 +calibrate_usb_clk=1 +sw_buil d_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=601530532 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_u art_rand_baudrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.chip_sw_uart_rand_baudrate.601530532 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/12.chip_sw_uart_rand_baudrate/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/13.chip_sw_lc_ctrl_transition.3388832155 |
| Short name | T122 |
| Test name | |
| Test status | |
| Simulation time | 5590241058 ps |
| CPU time | 287.84 seconds |
| Started | Aug 24 03:45:00 PM UTC 24 |
| Finished | Aug 24 03:49:53 PM UTC 24 |
| Peak memory | 639564 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=lc_ctrl_transition_test:1 :new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim. tcl +ntb_random_seed=3388832155 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_ctrl_transition_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/n ull -cm_name 13.chip_sw_lc_ctrl_transition.3388832155 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/13.chip_sw_lc_ctrl_transition/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/13.chip_sw_uart_rand_baudrate.314757720 |
| Short name | T1314 |
| Test name | |
| Test status | |
| Simulation time | 8696474512 ps |
| CPU time | 1058.21 seconds |
| Started | Aug 24 03:44:24 PM UTC 24 |
| Finished | Aug 24 04:02:14 PM UTC 24 |
| Peak memory | 637128 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=80_000_000 +calibrate_usb_clk=1 +sw_buil d_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=314757720 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_u art_rand_baudrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.chip_sw_uart_rand_baudrate.314757720 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/13.chip_sw_uart_rand_baudrate/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/14.chip_sw_lc_ctrl_transition.1153638653 |
| Short name | T1310 |
| Test name | |
| Test status | |
| Simulation time | 12526944444 ps |
| CPU time | 642.97 seconds |
| Started | Aug 24 03:46:26 PM UTC 24 |
| Finished | Aug 24 03:57:17 PM UTC 24 |
| Peak memory | 639372 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=lc_ctrl_transition_test:1 :new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim. tcl +ntb_random_seed=1153638653 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_ctrl_transition_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/n ull -cm_name 14.chip_sw_lc_ctrl_transition.1153638653 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/14.chip_sw_lc_ctrl_transition/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/14.chip_sw_uart_rand_baudrate.3933316929 |
| Short name | T1316 |
| Test name | |
| Test status | |
| Simulation time | 7935659764 ps |
| CPU time | 1099.93 seconds |
| Started | Aug 24 03:46:26 PM UTC 24 |
| Finished | Aug 24 04:04:58 PM UTC 24 |
| Peak memory | 636868 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=80_000_000 +calibrate_usb_clk=1 +sw_buil d_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3933316929 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_ uart_rand_baudrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.chip_sw_uart_rand_baudrate.3933316929 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/14.chip_sw_uart_rand_baudrate/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/15.chip_sw_uart_rand_baudrate.2087588302 |
| Short name | T1308 |
| Test name | |
| Test status | |
| Simulation time | 4311316952 ps |
| CPU time | 398.01 seconds |
| Started | Aug 24 03:47:26 PM UTC 24 |
| Finished | Aug 24 03:54:10 PM UTC 24 |
| Peak memory | 636876 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=80_000_000 +calibrate_usb_clk=1 +sw_buil d_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2087588302 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_ uart_rand_baudrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.chip_sw_uart_rand_baudrate.2087588302 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/15.chip_sw_uart_rand_baudrate/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/16.chip_sw_all_escalation_resets.217783659 |
| Short name | T688 |
| Test name | |
| Test status | |
| Simulation time | 5178921148 ps |
| CPU time | 421.78 seconds |
| Started | Aug 24 03:48:45 PM UTC 24 |
| Finished | Aug 24 03:55:52 PM UTC 24 |
| Peak memory | 675208 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv + sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=217783659 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_esc alation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.chip_sw_all_escalation_resets.217783659 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/16.chip_sw_all_escalation_resets/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/16.chip_sw_uart_rand_baudrate.824075081 |
| Short name | T1322 |
| Test name | |
| Test status | |
| Simulation time | 13137136800 ps |
| CPU time | 1862.03 seconds |
| Started | Aug 24 03:49:16 PM UTC 24 |
| Finished | Aug 24 04:20:39 PM UTC 24 |
| Peak memory | 639916 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=80_000_000 +calibrate_usb_clk=1 +sw_buil d_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=824075081 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_u art_rand_baudrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.chip_sw_uart_rand_baudrate.824075081 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/16.chip_sw_uart_rand_baudrate/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/17.chip_sw_all_escalation_resets.3634041092 |
| Short name | T774 |
| Test name | |
| Test status | |
| Simulation time | 5189026720 ps |
| CPU time | 480.97 seconds |
| Started | Aug 24 03:50:21 PM UTC 24 |
| Finished | Aug 24 03:58:28 PM UTC 24 |
| Peak memory | 675436 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv + sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3634041092 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_es calation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.chip_sw_all_escalation_resets.3634041092 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/17.chip_sw_all_escalation_resets/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/17.chip_sw_uart_rand_baudrate.757804236 |
| Short name | T1324 |
| Test name | |
| Test status | |
| Simulation time | 12552975732 ps |
| CPU time | 1951.2 seconds |
| Started | Aug 24 03:51:05 PM UTC 24 |
| Finished | Aug 24 04:23:58 PM UTC 24 |
| Peak memory | 640188 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=80_000_000 +calibrate_usb_clk=1 +sw_buil d_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=757804236 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_u art_rand_baudrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.chip_sw_uart_rand_baudrate.757804236 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/17.chip_sw_uart_rand_baudrate/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/18.chip_sw_all_escalation_resets.237840929 |
| Short name | T1311 |
| Test name | |
| Test status | |
| Simulation time | 4601269600 ps |
| CPU time | 358.44 seconds |
| Started | Aug 24 03:51:35 PM UTC 24 |
| Finished | Aug 24 03:57:39 PM UTC 24 |
| Peak memory | 637384 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv + sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=237840929 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_esc alation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.chip_sw_all_escalation_resets.237840929 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/18.chip_sw_all_escalation_resets/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/18.chip_sw_uart_rand_baudrate.2569196489 |
| Short name | T296 |
| Test name | |
| Test status | |
| Simulation time | 7640135516 ps |
| CPU time | 1034.53 seconds |
| Started | Aug 24 03:52:01 PM UTC 24 |
| Finished | Aug 24 04:09:27 PM UTC 24 |
| Peak memory | 636868 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=80_000_000 +calibrate_usb_clk=1 +sw_buil d_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2569196489 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_ uart_rand_baudrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.chip_sw_uart_rand_baudrate.2569196489 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/18.chip_sw_uart_rand_baudrate/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/19.chip_sw_uart_rand_baudrate.1538892161 |
| Short name | T1312 |
| Test name | |
| Test status | |
| Simulation time | 3342654124 ps |
| CPU time | 333.94 seconds |
| Started | Aug 24 03:52:43 PM UTC 24 |
| Finished | Aug 24 03:58:21 PM UTC 24 |
| Peak memory | 641196 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=80_000_000 +calibrate_usb_clk=1 +sw_buil d_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1538892161 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_ uart_rand_baudrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.chip_sw_uart_rand_baudrate.1538892161 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/19.chip_sw_uart_rand_baudrate/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_jtag_mem_access.1515699025 |
| Short name | T243 |
| Test name | |
| Test status | |
| Simulation time | 13585778955 ps |
| CPU time | 990.07 seconds |
| Started | Aug 24 02:28:27 PM UTC 24 |
| Finished | Aug 24 02:45:08 PM UTC 24 |
| Peak memory | 627428 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/default/simv +create_jtag_riscv_map=1 +stub_cpu=1 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1515699025 -assert nopos tproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_jtag_mem_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_jtag_mem_access.1515699025 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/2.chip_jtag_mem_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_rv_dm_ndm_reset_req.2960285409 |
| Short name | T441 |
| Test name | |
| Test status | |
| Simulation time | 4426411160 ps |
| CPU time | 190.02 seconds |
| Started | Aug 24 02:32:20 PM UTC 24 |
| Finished | Aug 24 02:35:33 PM UTC 24 |
| Peak memory | 637032 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/default/simv +en_scb_tl_err_chk=0 +use_jtag_dmi=1 +sw_build_device=sim_dv +sw_images=rv_dm_ndm_reset_req_rma:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2960285409 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_rv_dm_ndm_ reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cove rage/default.vdb -cm_log /dev/null -cm_name 2.chip_rv_dm_ndm_reset_req.2960285409 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/2.chip_rv_dm_ndm_reset_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sival_flash_info_access.360513927 |
| Short name | T1071 |
| Test name | |
| Test status | |
| Simulation time | 2918829132 ps |
| CPU time | 195.76 seconds |
| Started | Aug 24 12:49:19 PM UTC 24 |
| Finished | Aug 24 12:52:38 PM UTC 24 |
| Peak memory | 624876 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/default/simv +use_otp_image=OtpTypeLcStTestUnlocked0 +sw_build_device=sim _dv +sw_images=flash_ctrl_info_access_lc:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=360513927 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_bas e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage /default.vdb -cm_log /dev/null -cm_name 2.chip_sival_flash_info_access.360513927 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/2.chip_sival_flash_info_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_adc_ctrl_sleep_debug_cable_wakeup.513756129 |
| Short name | T1142 |
| Test name | |
| Test status | |
| Simulation time | 19086957032 ps |
| CPU time | 546.73 seconds |
| Started | Aug 24 01:38:59 PM UTC 24 |
| Finished | Aug 24 01:48:12 PM UTC 24 |
| Peak memory | 636924 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_i mages=adc_ctrl_sleep_debug_cable_wakeup_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=513756129 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw _adc_ctrl_sleep_debug_cable_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/ch ip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_adc_ctrl_sleep_debug_cable_wakeup.513756129 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/2.chip_sw_adc_ctrl_sleep_debug_cable_wakeup/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_aes_enc.1926530897 |
| Short name | T1138 |
| Test name | |
| Test status | |
| Simulation time | 3011820906 ps |
| CPU time | 171.44 seconds |
| Started | Aug 24 01:43:30 PM UTC 24 |
| Finished | Aug 24 01:46:24 PM UTC 24 |
| Peak memory | 624556 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=22_000_000 +sw_build_device=sim_dv +sw_i mages=aes_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/ repo/hw/dv/tools/sim.tcl +ntb_random_seed=1926530897 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_aes_enc.1926530897 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/2.chip_sw_aes_enc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_aes_enc_jitter_en.2986733029 |
| Short name | T1140 |
| Test name | |
| Test status | |
| Simulation time | 3041069106 ps |
| CPU time | 199.37 seconds |
| Started | Aug 24 01:44:02 PM UTC 24 |
| Finished | Aug 24 01:47:25 PM UTC 24 |
| Peak memory | 626736 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=26_000_000 +en_jitter=1 +sw_build_device =sim_dv +sw_images=aes_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2986733029 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/defaul t.vdb -cm_log /dev/null -cm_name 2.chip_sw_aes_enc_jitter_en.2986733029 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/2.chip_sw_aes_enc_jitter_en/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_aes_enc_jitter_en_reduced_freq.2112891183 |
| Short name | T1219 |
| Test name | |
| Test status | |
| Simulation time | 2912961212 ps |
| CPU time | 203.25 seconds |
| Started | Aug 24 02:37:54 PM UTC 24 |
| Finished | Aug 24 02:41:21 PM UTC 24 |
| Peak memory | 626864 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=26_000_000 +en_jitter=1 +cal_sys_clk_70m hz=1 +sw_build_device=sim_dv +sw_images=aes_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2112891183 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_S EQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_aes_enc_jitter_en_reduced_freq.2112891183 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/2.chip_sw_aes_enc_jitter_en_reduced_freq/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_aes_entropy.1023536042 |
| Short name | T1147 |
| Test name | |
| Test status | |
| Simulation time | 2708478288 ps |
| CPU time | 167.19 seconds |
| Started | Aug 24 01:49:04 PM UTC 24 |
| Finished | Aug 24 01:51:54 PM UTC 24 |
| Peak memory | 626600 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=15_000_000 +sw_build_device=sim_dv +sw_i mages=aes_entropy_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac es/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1023536042 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_ log /dev/null -cm_name 2.chip_sw_aes_entropy.1023536042 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/2.chip_sw_aes_entropy/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_aes_idle.431713156 |
| Short name | T1139 |
| Test name | |
| Test status | |
| Simulation time | 2484553600 ps |
| CPU time | 137.44 seconds |
| Started | Aug 24 01:44:25 PM UTC 24 |
| Finished | Aug 24 01:46:45 PM UTC 24 |
| Peak memory | 624700 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=25_000_000 +sw_build_device=sim_dv +sw_i mages=aes_idle_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/ repo/hw/dv/tools/sim.tcl +ntb_random_seed=431713156 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_aes_idle.431713156 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/2.chip_sw_aes_idle/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_aes_masking_off.4250786895 |
| Short name | T1141 |
| Test name | |
| Test status | |
| Simulation time | 2841132658 ps |
| CPU time | 196.8 seconds |
| Started | Aug 24 01:44:25 PM UTC 24 |
| Finished | Aug 24 01:47:45 PM UTC 24 |
| Peak memory | 624564 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=aes_masking_off_test:1:ne w_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4250786895 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_aes_masking_off_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -c m_name 2.chip_sw_aes_masking_off.4250786895 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/2.chip_sw_aes_masking_off/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_aes_smoketest.2560217481 |
| Short name | T1231 |
| Test name | |
| Test status | |
| Simulation time | 2972556040 ps |
| CPU time | 181.66 seconds |
| Started | Aug 24 02:50:36 PM UTC 24 |
| Finished | Aug 24 02:53:40 PM UTC 24 |
| Peak memory | 624556 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=aes_smoketest:1:new_rules ,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_r andom_seed=2560217481 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_a es_smoketest.2560217481 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/2.chip_sw_aes_smoketest/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_alert_handler_entropy.1646151973 |
| Short name | T1148 |
| Test name | |
| Test status | |
| Simulation time | 3295921981 ps |
| CPU time | 190.95 seconds |
| Started | Aug 24 01:48:48 PM UTC 24 |
| Finished | Aug 24 01:52:02 PM UTC 24 |
| Peak memory | 626800 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/default/simv +en_scb=0 +bypass_alert_ready_to_end_check=1 +sw_build_devic e=sim_dv +sw_images=alert_handler_entropy_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1646151973 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip _sw_alert_handler_entropy_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgr ey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_alert_handler_entropy.1646151973 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/2.chip_sw_alert_handler_entropy/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_alert_handler_escalation.2659333627 |
| Short name | T1149 |
| Test name | |
| Test status | |
| Simulation time | 5671895572 ps |
| CPU time | 404.93 seconds |
| Started | Aug 24 01:45:48 PM UTC 24 |
| Finished | Aug 24 01:52:38 PM UTC 24 |
| Peak memory | 637108 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/default/simv +en_scb=0 +bypass_alert_ready_to_end_check=1 +sw_build_devic e=sim_dv +sw_images=alert_handler_escalation_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2659333627 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=c hip_sw_alert_handler_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/chip_ earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_alert_handler_escalation.2659333627 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/2.chip_sw_alert_handler_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_alert_handler_lpg_clkoff.736204347 |
| Short name | T1167 |
| Test name | |
| Test status | |
| Simulation time | 7533367544 ps |
| CPU time | 1268.09 seconds |
| Started | Aug 24 01:48:48 PM UTC 24 |
| Finished | Aug 24 02:10:10 PM UTC 24 |
| Peak memory | 627076 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +sw_build_device= sim_dv +sw_images=alert_handler_lpg_clkoff_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=736204347 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip _sw_alert_handler_lpg_clkoff_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/chip_ear lgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_alert_handler_lpg_clkoff.736204347 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/2.chip_sw_alert_handler_lpg_clkoff/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_alert_handler_lpg_reset_toggle.600796568 |
| Short name | T1166 |
| Test name | |
| Test status | |
| Simulation time | 7555201872 ps |
| CPU time | 1172.97 seconds |
| Started | Aug 24 01:48:49 PM UTC 24 |
| Finished | Aug 24 02:08:35 PM UTC 24 |
| Peak memory | 626608 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +sw_build_device= sim_dv +sw_images=alert_handler_lpg_reset_toggle_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=600796568 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SE Q=chip_sw_alert_handler_shorten_ping_wait_cycle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_alert_handler_lpg_reset_toggle.600796568 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/2.chip_sw_alert_handler_lpg_reset_toggle/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_alert_handler_lpg_sleep_mode_pings.771205034 |
| Short name | T676 |
| Test name | |
| Test status | |
| Simulation time | 9564589368 ps |
| CPU time | 766.85 seconds |
| Started | Aug 24 01:48:10 PM UTC 24 |
| Finished | Aug 24 02:01:05 PM UTC 24 |
| Peak memory | 626696 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_rea dy_to_end_check=1 +sw_build_device=sim_dv +sw_images=alert_handler_lpg_sleep_mode_pings_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=771205034 -assert nopostproc +U VM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_alert_handler_shorten_ping_wait_cycle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_alert_handl er_lpg_sleep_mode_pings.771205034 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/2.chip_sw_alert_handler_lpg_sleep_mode_pings/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_alert_handler_ping_ok.4141740008 |
| Short name | T1163 |
| Test name | |
| Test status | |
| Simulation time | 7917589440 ps |
| CPU time | 1058.07 seconds |
| Started | Aug 24 01:46:48 PM UTC 24 |
| Finished | Aug 24 02:04:38 PM UTC 24 |
| Peak memory | 626616 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/default/simv +en_scb=0 +sw_test_timeout_ns=24000000 +sw_build_device=sim_ dv +sw_images=alert_handler_ping_ok_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4141740008 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_ba se_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_alert_handler_ping_ok.4141740008 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/2.chip_sw_alert_handler_ping_ok/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_alert_handler_ping_timeout.757849651 |
| Short name | T1145 |
| Test name | |
| Test status | |
| Simulation time | 3484913800 ps |
| CPU time | 237.09 seconds |
| Started | Aug 24 01:46:04 PM UTC 24 |
| Finished | Aug 24 01:50:04 PM UTC 24 |
| Peak memory | 626616 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/default/simv +en_scb=0 +sw_test_timeout_ns=24000000 +sw_build_device=sim_ dv +sw_images=alert_handler_ping_timeout_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu eue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=757849651 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_s w_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_alert_handler_ping_timeout.757849651 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/2.chip_sw_alert_handler_ping_timeout/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_alert_handler_reverse_ping_in_deep_sleep.1218252920 |
| Short name | T1341 |
| Test name | |
| Test status | |
| Simulation time | 254909919480 ps |
| CPU time | 10703.2 seconds |
| Started | Aug 24 01:47:09 PM UTC 24 |
| Finished | Aug 24 04:47:26 PM UTC 24 |
| Peak memory | 629736 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/default/simv +en_scb=0 +sw_test_timeout_ns=300_000_000 +sw_build_device=s im_dv +sw_images=alert_handler_reverse_ping_in_deep_sleep_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1218252920 -assert nopostproc +UVM_TESTNAME=chip_base_test +U VM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgre y_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_alert_handler_reverse_ping_in_deep_sleep.1218252920 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/2.chip_sw_alert_handler_reverse_ping_in_deep_sleep/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_alert_test.305546160 |
| Short name | T89 |
| Test name | |
| Test status | |
| Simulation time | 2575928016 ps |
| CPU time | 206.92 seconds |
| Started | Aug 24 01:44:38 PM UTC 24 |
| Finished | Aug 24 01:48:08 PM UTC 24 |
| Peak memory | 624564 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=alert_test:1:new_rules,te st_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_rand om_seed=305546160 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_alert _test.305546160 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/2.chip_sw_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_aon_timer_irq.3498635708 |
| Short name | T1128 |
| Test name | |
| Test status | |
| Simulation time | 4275108664 ps |
| CPU time | 306.6 seconds |
| Started | Aug 24 01:36:21 PM UTC 24 |
| Finished | Aug 24 01:41:32 PM UTC 24 |
| Peak memory | 624704 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_i mages=aon_timer_irq_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp aces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3498635708 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -c m_log /dev/null -cm_name 2.chip_sw_aon_timer_irq.3498635708 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/2.chip_sw_aon_timer_irq/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_aon_timer_sleep_wdog_sleep_pause.2595310356 |
| Short name | T1130 |
| Test name | |
| Test status | |
| Simulation time | 6806571320 ps |
| CPU time | 391.58 seconds |
| Started | Aug 24 01:36:21 PM UTC 24 |
| Finished | Aug 24 01:42:58 PM UTC 24 |
| Peak memory | 626676 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_i mages=aon_timer_sleep_wdog_sleep_pause_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu e -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2595310356 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw _base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cove rage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_aon_timer_sleep_wdog_sleep_pause.2595310356 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/2.chip_sw_aon_timer_sleep_wdog_sleep_pause/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_aon_timer_smoketest.3772891332 |
| Short name | T1234 |
| Test name | |
| Test status | |
| Simulation time | 3701098352 ps |
| CPU time | 259.37 seconds |
| Started | Aug 24 02:51:15 PM UTC 24 |
| Finished | Aug 24 02:55:38 PM UTC 24 |
| Peak memory | 624564 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=aon_timer_smoketest:1:new _rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3772891332 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.chi p_sw_aon_timer_smoketest.3772891332 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/2.chip_sw_aon_timer_smoketest/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_aon_timer_wdog_bite_reset.3782285191 |
| Short name | T1136 |
| Test name | |
| Test status | |
| Simulation time | 8578636028 ps |
| CPU time | 469.34 seconds |
| Started | Aug 24 01:37:28 PM UTC 24 |
| Finished | Aug 24 01:45:24 PM UTC 24 |
| Peak memory | 626940 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_i mages=aon_timer_wdog_bite_reset_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3782285191 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/de fault.vdb -cm_log /dev/null -cm_name 2.chip_sw_aon_timer_wdog_bite_reset.3782285191 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/2.chip_sw_aon_timer_wdog_bite_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_aon_timer_wdog_lc_escalate.3079202693 |
| Short name | T1133 |
| Test name | |
| Test status | |
| Simulation time | 5371593088 ps |
| CPU time | 346.03 seconds |
| Started | Aug 24 01:38:03 PM UTC 24 |
| Finished | Aug 24 01:43:54 PM UTC 24 |
| Peak memory | 626624 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_i mages=aon_timer_wdog_lc_escalate_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3079202693 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 2.chip_sw_aon_timer_wdog_lc_escalate.3079202693 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/2.chip_sw_aon_timer_wdog_lc_escalate/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_ast_clk_outputs.3159289137 |
| Short name | T1212 |
| Test name | |
| Test status | |
| Simulation time | 6636899374 ps |
| CPU time | 641.04 seconds |
| Started | Aug 24 02:28:45 PM UTC 24 |
| Finished | Aug 24 02:39:33 PM UTC 24 |
| Peak memory | 632836 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/default/simv +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=ast_ clk_outs_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/h w/dv/tools/sim.tcl +ntb_random_seed=3159289137 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_ast_clk_outputs_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -c m_log /dev/null -cm_name 2.chip_sw_ast_clk_outputs.3159289137 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/2.chip_sw_ast_clk_outputs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_ast_clk_rst_inputs.2799780583 |
| Short name | T178 |
| Test name | |
| Test status | |
| Simulation time | 17981196684 ps |
| CPU time | 1664.84 seconds |
| Started | Aug 24 02:41:01 PM UTC 24 |
| Finished | Aug 24 03:09:04 PM UTC 24 |
| Peak memory | 629936 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=200_000_000 +sw_build_device=sim_dv +sw_ images=ast_clk_rst_inputs:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works paces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2799780583 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_ast_clk_rst_input s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage /default.vdb -cm_log /dev/null -cm_name 2.chip_sw_ast_clk_rst_inputs.2799780583 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/2.chip_sw_ast_clk_rst_inputs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_clkmgr_external_clk_src_for_lc.3502606723 |
| Short name | T1196 |
| Test name | |
| Test status | |
| Simulation time | 10092491849 ps |
| CPU time | 562.27 seconds |
| Started | Aug 24 02:22:05 PM UTC 24 |
| Finished | Aug 24 02:31:34 PM UTC 24 |
| Peak memory | 639316 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/default/simv +chip_clock_source=ChipClockSourceExternal48Mhz +sw_build_de vice=sim_dv +sw_images=clkmgr_external_clk_src_for_lc_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3502606723 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_T EST_SEQ=chip_sw_lc_ctrl_transition_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/ch ip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_clkmgr_external_clk_src_for_lc.3502606723 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/2.chip_sw_clkmgr_external_clk_src_for_lc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_clkmgr_external_clk_src_for_sw_fast_dev.1424691117 |
| Short name | T1194 |
| Test name | |
| Test status | |
| Simulation time | 4244953076 ps |
| CPU time | 416.83 seconds |
| Started | Aug 24 02:23:57 PM UTC 24 |
| Finished | Aug 24 02:30:59 PM UTC 24 |
| Peak memory | 628864 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/default/simv +chip_clock_source=ChipClockSourceExternal96Mhz +calibrate_u sb_clk=1 +src_dec_state=DecLcStDev +sw_build_device=sim_dv +sw_images=clkmgr_external_clk_src_for_sw_fast_test:1:new_rules,test_rom:0 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1424691117 -a ssert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces /repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_clkmgr_external_clk_sr c_for_sw_fast_dev.1424691117 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/2.chip_sw_clkmgr_external_clk_src_for_sw_fast_dev/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_clkmgr_external_clk_src_for_sw_fast_rma.4088846672 |
| Short name | T1200 |
| Test name | |
| Test status | |
| Simulation time | 4028025580 ps |
| CPU time | 452.46 seconds |
| Started | Aug 24 02:24:56 PM UTC 24 |
| Finished | Aug 24 02:32:34 PM UTC 24 |
| Peak memory | 628628 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/default/simv +chip_clock_source=ChipClockSourceExternal96Mhz +calibrate_u sb_clk=1 +src_dec_state=DecLcStRma +sw_build_device=sim_dv +sw_images=clkmgr_external_clk_src_for_sw_fast_test:1:new_rules,test_rom:0 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4088846672 -a ssert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces /repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_clkmgr_external_clk_sr c_for_sw_fast_rma.4088846672 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/2.chip_sw_clkmgr_external_clk_src_for_sw_fast_rma/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0.1651912347 |
| Short name | T1192 |
| Test name | |
| Test status | |
| Simulation time | 3570705320 ps |
| CPU time | 395.14 seconds |
| Started | Aug 24 02:22:46 PM UTC 24 |
| Finished | Aug 24 02:29:26 PM UTC 24 |
| Peak memory | 626844 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/default/simv +chip_clock_source=ChipClockSourceExternal96Mhz +calibrate_u sb_clk=1 +src_dec_state=DecLcStTestUnlocked0 +sw_build_device=sim_dv +sw_images=clkmgr_external_clk_src_for_sw_fast_test:1:new_rules,test_rom:0 +c dc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=165 1912347 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_clkmgr_exter nal_clk_src_for_sw_fast_test_unlocked0.1651912347 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/2.chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_clkmgr_external_clk_src_for_sw_slow_dev.1786121166 |
| Short name | T1198 |
| Test name | |
| Test status | |
| Simulation time | 4488357480 ps |
| CPU time | 439.1 seconds |
| Started | Aug 24 02:24:21 PM UTC 24 |
| Finished | Aug 24 02:31:46 PM UTC 24 |
| Peak memory | 628640 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/default/simv +chip_clock_source=ChipClockSourceExternal48Mhz +calibrate_u sb_clk=1 +src_dec_state=DecLcStDev +sw_build_device=sim_dv +sw_images=clkmgr_external_clk_src_for_sw_slow_test:1:new_rules,test_rom:0 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1786121166 -a ssert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces /repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_clkmgr_external_clk_sr c_for_sw_slow_dev.1786121166 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/2.chip_sw_clkmgr_external_clk_src_for_sw_slow_dev/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_clkmgr_external_clk_src_for_sw_slow_rma.3059370378 |
| Short name | T1201 |
| Test name | |
| Test status | |
| Simulation time | 4708608358 ps |
| CPU time | 387.98 seconds |
| Started | Aug 24 02:26:46 PM UTC 24 |
| Finished | Aug 24 02:33:18 PM UTC 24 |
| Peak memory | 626872 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/default/simv +chip_clock_source=ChipClockSourceExternal48Mhz +calibrate_u sb_clk=1 +src_dec_state=DecLcStRma +sw_build_device=sim_dv +sw_images=clkmgr_external_clk_src_for_sw_slow_test:1:new_rules,test_rom:0 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3059370378 -a ssert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces /repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_clkmgr_external_clk_sr c_for_sw_slow_rma.3059370378 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/2.chip_sw_clkmgr_external_clk_src_for_sw_slow_rma/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0.4241733381 |
| Short name | T1195 |
| Test name | |
| Test status | |
| Simulation time | 4574353056 ps |
| CPU time | 450.04 seconds |
| Started | Aug 24 02:23:55 PM UTC 24 |
| Finished | Aug 24 02:31:30 PM UTC 24 |
| Peak memory | 628824 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/default/simv +chip_clock_source=ChipClockSourceExternal48Mhz +calibrate_u sb_clk=1 +src_dec_state=DecLcStTestUnlocked0 +sw_build_device=sim_dv +sw_images=clkmgr_external_clk_src_for_sw_slow_test:1:new_rules,test_rom:0 +c dc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=424 1733381 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_clkmgr_exter nal_clk_src_for_sw_slow_test_unlocked0.4241733381 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/2.chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_clkmgr_jitter.3313197597 |
| Short name | T1193 |
| Test name | |
| Test status | |
| Simulation time | 2045067121 ps |
| CPU time | 150.27 seconds |
| Started | Aug 24 02:27:56 PM UTC 24 |
| Finished | Aug 24 02:30:29 PM UTC 24 |
| Peak memory | 624824 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=clkmgr_jitter_test:1:new_ rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl + ntb_random_seed=3313197597 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip _sw_clkmgr_jitter.3313197597 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/2.chip_sw_clkmgr_jitter/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_clkmgr_jitter_frequency.3693629625 |
| Short name | T1199 |
| Test name | |
| Test status | |
| Simulation time | 3361267736 ps |
| CPU time | 299.44 seconds |
| Started | Aug 24 02:27:13 PM UTC 24 |
| Finished | Aug 24 02:32:17 PM UTC 24 |
| Peak memory | 624824 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=clkmgr_jitter_frequency_t est:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools /sim.tcl +ntb_random_seed=3693629625 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_n ame 2.chip_sw_clkmgr_jitter_frequency.3693629625 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/2.chip_sw_clkmgr_jitter_frequency/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_clkmgr_jitter_reduced_freq.2950390353 |
| Short name | T1213 |
| Test name | |
| Test status | |
| Simulation time | 2781498917 ps |
| CPU time | 165.9 seconds |
| Started | Aug 24 02:37:04 PM UTC 24 |
| Finished | Aug 24 02:39:53 PM UTC 24 |
| Peak memory | 626924 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/default/simv +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +sw_images=clkm gr_jitter_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/ hw/dv/tools/sim.tcl +ntb_random_seed=2950390353 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev /null -cm_name 2.chip_sw_clkmgr_jitter_reduced_freq.2950390353 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/2.chip_sw_clkmgr_jitter_reduced_freq/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_clkmgr_off_aes_trans.1886190845 |
| Short name | T1188 |
| Test name | |
| Test status | |
| Simulation time | 5254737428 ps |
| CPU time | 349.96 seconds |
| Started | Aug 24 02:20:55 PM UTC 24 |
| Finished | Aug 24 02:26:49 PM UTC 24 |
| Peak memory | 624824 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=clkmgr_off_aes_trans_test :1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/si m.tcl +ntb_random_seed=1886190845 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_clkmgr_off_aes_trans.1886190845 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/2.chip_sw_clkmgr_off_aes_trans/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_clkmgr_off_hmac_trans.3208032572 |
| Short name | T1187 |
| Test name | |
| Test status | |
| Simulation time | 4873149264 ps |
| CPU time | 315.88 seconds |
| Started | Aug 24 02:20:57 PM UTC 24 |
| Finished | Aug 24 02:26:17 PM UTC 24 |
| Peak memory | 626624 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=clkmgr_off_hmac_trans_tes t:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/s im.tcl +ntb_random_seed=3208032572 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam e 2.chip_sw_clkmgr_off_hmac_trans.3208032572 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/2.chip_sw_clkmgr_off_hmac_trans/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_clkmgr_off_kmac_trans.3331687344 |
| Short name | T1190 |
| Test name | |
| Test status | |
| Simulation time | 5832804712 ps |
| CPU time | 373.05 seconds |
| Started | Aug 24 02:21:14 PM UTC 24 |
| Finished | Aug 24 02:27:32 PM UTC 24 |
| Peak memory | 626856 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=clkmgr_off_kmac_trans_tes t:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/s im.tcl +ntb_random_seed=3331687344 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam e 2.chip_sw_clkmgr_off_kmac_trans.3331687344 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/2.chip_sw_clkmgr_off_kmac_trans/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_clkmgr_off_otbn_trans.3969771033 |
| Short name | T1189 |
| Test name | |
| Test status | |
| Simulation time | 4508164938 ps |
| CPU time | 353.94 seconds |
| Started | Aug 24 02:21:27 PM UTC 24 |
| Finished | Aug 24 02:27:26 PM UTC 24 |
| Peak memory | 626612 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=clkmgr_off_otbn_trans_tes t:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/s im.tcl +ntb_random_seed=3969771033 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam e 2.chip_sw_clkmgr_off_otbn_trans.3969771033 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/2.chip_sw_clkmgr_off_otbn_trans/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_clkmgr_off_peri.3478105916 |
| Short name | T1204 |
| Test name | |
| Test status | |
| Simulation time | 10936943282 ps |
| CPU time | 930.67 seconds |
| Started | Aug 24 02:19:39 PM UTC 24 |
| Finished | Aug 24 02:35:20 PM UTC 24 |
| Peak memory | 626616 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=30_000_000 +sw_build_device=sim_dv +sw_i mages=clkmgr_off_peri_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3478105916 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_clkmgr_off_peri.3478105916 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/2.chip_sw_clkmgr_off_peri/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_clkmgr_reset_frequency.3855548330 |
| Short name | T1197 |
| Test name | |
| Test status | |
| Simulation time | 3113756500 ps |
| CPU time | 286.3 seconds |
| Started | Aug 24 02:26:46 PM UTC 24 |
| Finished | Aug 24 02:31:36 PM UTC 24 |
| Peak memory | 627120 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/default/simv +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=clkm gr_reset_frequency_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3855548330 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm _log /dev/null -cm_name 2.chip_sw_clkmgr_reset_frequency.3855548330 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/2.chip_sw_clkmgr_reset_frequency/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_clkmgr_sleep_frequency.547629533 |
| Short name | T1205 |
| Test name | |
| Test status | |
| Simulation time | 5143084290 ps |
| CPU time | 455.51 seconds |
| Started | Aug 24 02:27:58 PM UTC 24 |
| Finished | Aug 24 02:35:39 PM UTC 24 |
| Peak memory | 626948 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/default/simv +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=clkm gr_sleep_frequency_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=547629533 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_ log /dev/null -cm_name 2.chip_sw_clkmgr_sleep_frequency.547629533 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/2.chip_sw_clkmgr_sleep_frequency/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_clkmgr_smoketest.2341388915 |
| Short name | T1233 |
| Test name | |
| Test status | |
| Simulation time | 3134653720 ps |
| CPU time | 141.98 seconds |
| Started | Aug 24 02:52:07 PM UTC 24 |
| Finished | Aug 24 02:54:31 PM UTC 24 |
| Peak memory | 624824 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=clkmgr_smoketest:1:new_ru les,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +nt b_random_seed=2341388915 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as sert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_s w_clkmgr_smoketest.2341388915 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/2.chip_sw_clkmgr_smoketest/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_csrng_edn_concurrency.1332810235 |
| Short name | T1271 |
| Test name | |
| Test status | |
| Simulation time | 26879685640 ps |
| CPU time | 5462.25 seconds |
| Started | Aug 24 01:53:03 PM UTC 24 |
| Finished | Aug 24 03:25:03 PM UTC 24 |
| Peak memory | 629804 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=140_000_000 +rng_srate_value_min=15 +rng _srate_value_max=20 +accelerate_cold_power_up_time=3 +accelerate_regulators_power_up_time=2 +sw_build_device=sim_dv +sw_images=csrng_edn_concurren cy_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/t ools/sim.tcl +ntb_random_seed=1332810235 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null - cm_name 2.chip_sw_csrng_edn_concurrency.1332810235 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/2.chip_sw_csrng_edn_concurrency/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_csrng_edn_concurrency_reduced_freq.4011335849 |
| Short name | T626 |
| Test name | |
| Test status | |
| Simulation time | 153178968724 ps |
| CPU time | 17714.3 seconds |
| Started | Aug 24 02:39:46 PM UTC 24 |
| Finished | Aug 24 07:37:50 PM UTC 24 |
| Peak memory | 629944 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=360_000_000 +rng_srate_value_min=15 +rng _srate_value_max=20 +cal_sys_clk_70mhz=1 +en_jitter=1 +accelerate_cold_power_up_time=3 +accelerate_regulators_power_up_time=2 +sw_build_device=sim _dv +sw_images=csrng_edn_concurrency_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4011335849 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_b ase_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/covera ge/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_csrng_edn_concurrency_reduced_freq.4011335849 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/2.chip_sw_csrng_edn_concurrency_reduced_freq/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_csrng_fuse_en_sw_app_read_test.3020017803 |
| Short name | T1156 |
| Test name | |
| Test status | |
| Simulation time | 4443842640 ps |
| CPU time | 296.35 seconds |
| Started | Aug 24 01:54:06 PM UTC 24 |
| Finished | Aug 24 01:59:07 PM UTC 24 |
| Peak memory | 626864 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=15_000_000 +sw_build_device=sim_dv +sw_i mages=csrng_fuse_en_sw_app_read:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3020017803 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_entropy_src _fuse_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cove rage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_csrng_fuse_en_sw_app_read_test.3020017803 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/2.chip_sw_csrng_fuse_en_sw_app_read_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_csrng_kat_test.463495247 |
| Short name | T1154 |
| Test name | |
| Test status | |
| Simulation time | 3188486504 ps |
| CPU time | 190.47 seconds |
| Started | Aug 24 01:53:34 PM UTC 24 |
| Finished | Aug 24 01:56:47 PM UTC 24 |
| Peak memory | 626608 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_i mages=csrng_kat_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces /repo/hw/dv/tools/sim.tcl +ntb_random_seed=463495247 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_csrng_kat_test.463495247 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/2.chip_sw_csrng_kat_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_csrng_lc_hw_debug_en_test.1139467419 |
| Short name | T1160 |
| Test name | |
| Test status | |
| Simulation time | 7492824709 ps |
| CPU time | 544.32 seconds |
| Started | Aug 24 01:52:47 PM UTC 24 |
| Finished | Aug 24 02:01:59 PM UTC 24 |
| Peak memory | 626888 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=15_000_000 +rng_srate_value_min=15 +use_ otp_image=OtpTypeLcStTestUnlocked0 +sw_build_device=sim_dv +sw_images=csrng_lc_hw_debug_en_test:1:new_rules,test_rom:0 +cdc_instrumentation_enable d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1139467419 -assert nopostpro c +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_csrng_lc_hw_debug_en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r epo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_csrng_lc_hw_debug_en_test.1139467419 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/2.chip_sw_csrng_lc_hw_debug_en_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_csrng_smoketest.1004530776 |
| Short name | T1236 |
| Test name | |
| Test status | |
| Simulation time | 3402164524 ps |
| CPU time | 205.32 seconds |
| Started | Aug 24 02:54:04 PM UTC 24 |
| Finished | Aug 24 02:57:32 PM UTC 24 |
| Peak memory | 624572 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=csrng_smoketest:1:new_rul es,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb _random_seed=1004530776 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw _csrng_smoketest.1004530776 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/2.chip_sw_csrng_smoketest/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_data_integrity_escalation.1124500503 |
| Short name | T380 |
| Test name | |
| Test status | |
| Simulation time | 6410269854 ps |
| CPU time | 544.86 seconds |
| Started | Aug 24 12:50:22 PM UTC 24 |
| Finished | Aug 24 12:59:34 PM UTC 24 |
| Peak memory | 627012 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv + sw_images=data_integrity_escalation_reset_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1124500503 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip _sw_data_integrity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_data_integrity_escalation.1124500503 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/2.chip_sw_data_integrity_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_edn_auto_mode.4129172521 |
| Short name | T1174 |
| Test name | |
| Test status | |
| Simulation time | 7939804520 ps |
| CPU time | 1399.26 seconds |
| Started | Aug 24 01:50:30 PM UTC 24 |
| Finished | Aug 24 02:14:05 PM UTC 24 |
| Peak memory | 627280 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=18_000_000 +rng_srate_value=5 +accelerat e_cold_power_up_time=3 +accelerate_regulators_power_up_time=2 +sw_build_device=sim_dv +sw_images=edn_auto_mode:1:new_rules,test_rom:0 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4129172521 -a ssert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re po/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_edn_auto_mode.4129172521 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/2.chip_sw_edn_auto_mode/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_edn_boot_mode.770576449 |
| Short name | T452 |
| Test name | |
| Test status | |
| Simulation time | 3072465144 ps |
| CPU time | 388.43 seconds |
| Started | Aug 24 01:51:16 PM UTC 24 |
| Finished | Aug 24 01:57:49 PM UTC 24 |
| Peak memory | 624692 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=18_000_000 +rng_srate_value=5 +accelerat e_cold_power_up_time=3 +accelerate_regulators_power_up_time=2 +sw_build_device=sim_dv +sw_images=edn_boot_mode:1:new_rules,test_rom:0 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=770576449 -as sert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/rep o/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_edn_boot_mode.770576449 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/2.chip_sw_edn_boot_mode/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_edn_entropy_reqs.3122199430 |
| Short name | T1169 |
| Test name | |
| Test status | |
| Simulation time | 7232008120 ps |
| CPU time | 935.69 seconds |
| Started | Aug 24 01:54:40 PM UTC 24 |
| Finished | Aug 24 02:10:26 PM UTC 24 |
| Peak memory | 626748 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=15000000 +rng_srate_value_min=15 +rng_sr ate_value_max=30 +sw_build_device=sim_dv +sw_images=entropy_src_edn_reqs_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3122199430 -assert nopostproc +UVM_TESTNAME=ch ip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_ 22/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_edn_entropy_reqs.3122199430 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/2.chip_sw_edn_entropy_reqs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_edn_entropy_reqs_jitter.2267258573 |
| Short name | T1164 |
| Test name | |
| Test status | |
| Simulation time | 6453531094 ps |
| CPU time | 642.97 seconds |
| Started | Aug 24 01:57:13 PM UTC 24 |
| Finished | Aug 24 02:08:04 PM UTC 24 |
| Peak memory | 626748 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=15000000 +rng_srate_value_min=15 +rng_sr ate_value_max=30 +en_jitter=1 +sw_build_device=sim_dv +sw_images=entropy_src_edn_reqs_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2267258573 -assert nopostproc +UV M_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_edn_entropy_reqs_jitter.2267258573 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/2.chip_sw_edn_entropy_reqs_jitter/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_edn_kat.365991402 |
| Short name | T1157 |
| Test name | |
| Test status | |
| Simulation time | 3580678424 ps |
| CPU time | 473.5 seconds |
| Started | Aug 24 01:52:25 PM UTC 24 |
| Finished | Aug 24 02:00:25 PM UTC 24 |
| Peak memory | 630968 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=18_000_000 +rng_srate_value=5 +disable_a ssert_edn_output_diff_from_prev=1 +accelerate_cold_power_up_time=3 +accelerate_regulators_power_up_time=2 +sw_build_device=sim_dv +sw_images=edn_k at:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/ sim.tcl +ntb_random_seed=365991402 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam e 2.chip_sw_edn_kat.365991402 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/2.chip_sw_edn_kat/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_edn_sw_mode.2381369428 |
| Short name | T1179 |
| Test name | |
| Test status | |
| Simulation time | 10098199520 ps |
| CPU time | 1556.32 seconds |
| Started | Aug 24 01:52:27 PM UTC 24 |
| Finished | Aug 24 02:18:41 PM UTC 24 |
| Peak memory | 629596 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_i mages=edn_sw_mode:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/re po/hw/dv/tools/sim.tcl +ntb_random_seed=2381369428 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 2.chip_sw_edn_sw_mode.2381369428 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/2.chip_sw_edn_sw_mode/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_entropy_src_ast_rng_req.3181282233 |
| Short name | T1155 |
| Test name | |
| Test status | |
| Simulation time | 3088483724 ps |
| CPU time | 190.06 seconds |
| Started | Aug 24 01:54:09 PM UTC 24 |
| Finished | Aug 24 01:57:22 PM UTC 24 |
| Peak memory | 626940 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=15_000_000 +sw_build_device=sim_dv +sw_i mages=entropy_src_ast_rng_req_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli - do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3181282233 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/defa ult.vdb -cm_log /dev/null -cm_name 2.chip_sw_entropy_src_ast_rng_req.3181282233 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/2.chip_sw_entropy_src_ast_rng_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_entropy_src_csrng.2485125969 |
| Short name | T365 |
| Test name | |
| Test status | |
| Simulation time | 7425802716 ps |
| CPU time | 1236.97 seconds |
| Started | Aug 24 01:54:29 PM UTC 24 |
| Finished | Aug 24 02:15:20 PM UTC 24 |
| Peak memory | 625204 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=50_000_000 +rng_srate_value_min=15 +rng_ srate_value_max=30 +sw_build_device=sim_dv +sw_images=entropy_src_csrng_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2485125969 -assert nopostproc +UVM_TESTNAME=chi p_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_2 2/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_entropy_src_csrng.2485125969 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/2.chip_sw_entropy_src_csrng/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_entropy_src_kat_test.3173612142 |
| Short name | T1151 |
| Test name | |
| Test status | |
| Simulation time | 3152294920 ps |
| CPU time | 193.07 seconds |
| Started | Aug 24 01:50:28 PM UTC 24 |
| Finished | Aug 24 01:53:45 PM UTC 24 |
| Peak memory | 624572 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_i mages=entropy_src_kat_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3173612142 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_entropy_src_kat_test.3173612142 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/2.chip_sw_entropy_src_kat_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_entropy_src_smoketest.1266827976 |
| Short name | T1239 |
| Test name | |
| Test status | |
| Simulation time | 3156987580 ps |
| CPU time | 288.51 seconds |
| Started | Aug 24 02:54:34 PM UTC 24 |
| Finished | Aug 24 02:59:27 PM UTC 24 |
| Peak memory | 624572 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/default/simv +rng_srate_value_min=15 +rng_srate_value_max=30 +sw_build_de vice=sim_dv +sw_images=entropy_src_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1266827976 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_s w_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_entropy_src_smoketest.1266827976 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/2.chip_sw_entropy_src_smoketest/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_example_concurrency.3289886884 |
| Short name | T1070 |
| Test name | |
| Test status | |
| Simulation time | 2821984660 ps |
| CPU time | 142.72 seconds |
| Started | Aug 24 12:49:19 PM UTC 24 |
| Finished | Aug 24 12:51:44 PM UTC 24 |
| Peak memory | 624556 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=example_concurrency_test: 1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim .tcl +ntb_random_seed=3289886884 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_example_concurrency.3289886884 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/2.chip_sw_example_concurrency/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_example_flash.707771903 |
| Short name | T1064 |
| Test name | |
| Test status | |
| Simulation time | 2600432296 ps |
| CPU time | 132.02 seconds |
| Started | Aug 24 12:47:29 PM UTC 24 |
| Finished | Aug 24 12:49:43 PM UTC 24 |
| Peak memory | 626608 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=example_test_from_flash:1 :new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim. tcl +ntb_random_seed=707771903 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2. chip_sw_example_flash.707771903 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/2.chip_sw_example_flash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_example_manufacturer.3749172108 |
| Short name | T1068 |
| Test name | |
| Test status | |
| Simulation time | 3157576720 ps |
| CPU time | 136.58 seconds |
| Started | Aug 24 12:48:54 PM UTC 24 |
| Finished | Aug 24 12:51:13 PM UTC 24 |
| Peak memory | 624564 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=example_test:1:new_rules, test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=3749172108 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_ex ample_manufacturer.3749172108 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/2.chip_sw_example_manufacturer/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_example_rom.3452004822 |
| Short name | T1063 |
| Test name | |
| Test status | |
| Simulation time | 2387485512 ps |
| CPU time | 102.58 seconds |
| Started | Aug 24 12:47:57 PM UTC 24 |
| Finished | Aug 24 12:49:42 PM UTC 24 |
| Peak memory | 624492 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=example_test_from_rom:0:t est_in_rom:new_rules +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.t cl +ntb_random_seed=3452004822 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2. chip_sw_example_rom.3452004822 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/2.chip_sw_example_rom/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_exit_test_unlocked_bootstrap.3716670402 |
| Short name | T1302 |
| Test name | |
| Test status | |
| Simulation time | 59974351814 ps |
| CPU time | 9981.9 seconds |
| Started | Aug 24 12:56:22 PM UTC 24 |
| Finished | Aug 24 03:44:28 PM UTC 24 |
| Peak memory | 644192 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/default/simv +flash_program_latency=5 +sw_test_timeout_ns=150_000_000 +sw _build_device=sim_dv +sw_images=exit_test_unlocked_bootstrap:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY =UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3716670402 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM _TEST_SEQ=chip_sw_exit_test_unlocked_bootstrap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_exit_test_unlocked_bootstrap.3716670402 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/2.chip_sw_exit_test_unlocked_bootstrap/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_flash_crash_alert.3169974434 |
| Short name | T1222 |
| Test name | |
| Test status | |
| Simulation time | 4480449520 ps |
| CPU time | 457.27 seconds |
| Started | Aug 24 02:36:14 PM UTC 24 |
| Finished | Aug 24 02:43:57 PM UTC 24 |
| Peak memory | 627024 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/default/simv +test_timeout_ns=8_000_000 +bypass_alert_ready_to_end_check= 1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3169974434 -assert nopostproc +UVM_TESTNAME=chip_base_test + UVM_TEST_SEQ=chip_sw_flash_host_gnt_err_inj_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _08_22/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_flash_crash_alert.3169974434 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/2.chip_sw_flash_crash_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_flash_ctrl_access.924865245 |
| Short name | T1097 |
| Test name | |
| Test status | |
| Simulation time | 5936662670 ps |
| CPU time | 694 seconds |
| Started | Aug 24 01:12:33 PM UTC 24 |
| Finished | Aug 24 01:24:16 PM UTC 24 |
| Peak memory | 626616 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=flash_ctrl_test:1:new_rul es,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb _random_seed=924865245 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_ flash_ctrl_access.924865245 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/2.chip_sw_flash_ctrl_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_flash_ctrl_access_jitter_en.3783189662 |
| Short name | T1105 |
| Test name | |
| Test status | |
| Simulation time | 6828880187 ps |
| CPU time | 733.33 seconds |
| Started | Aug 24 01:12:43 PM UTC 24 |
| Finished | Aug 24 01:25:05 PM UTC 24 |
| Peak memory | 626736 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/default/simv +en_jitter=1 +sw_build_device=sim_dv +sw_images=flash_ctrl_t est:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools /sim.tcl +ntb_random_seed=3783189662 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_n ame 2.chip_sw_flash_ctrl_access_jitter_en.3783189662 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/2.chip_sw_flash_ctrl_access_jitter_en/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_flash_ctrl_access_jitter_en_reduced_freq.2283787259 |
| Short name | T1229 |
| Test name | |
| Test status | |
| Simulation time | 8396282751 ps |
| CPU time | 789.89 seconds |
| Started | Aug 24 02:37:32 PM UTC 24 |
| Finished | Aug 24 02:50:51 PM UTC 24 |
| Peak memory | 625616 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/default/simv +en_jitter=1 +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +s w_images=flash_ctrl_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp aces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2283787259 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -c m_log /dev/null -cm_name 2.chip_sw_flash_ctrl_access_jitter_en_reduced_freq.2283787259 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/2.chip_sw_flash_ctrl_access_jitter_en_reduced_freq/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_flash_ctrl_clock_freqs.1168891505 |
| Short name | T1109 |
| Test name | |
| Test status | |
| Simulation time | 6006929648 ps |
| CPU time | 709.88 seconds |
| Started | Aug 24 01:17:04 PM UTC 24 |
| Finished | Aug 24 01:29:02 PM UTC 24 |
| Peak memory | 624560 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=flash_ctrl_clock_freqs_te st:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/ sim.tcl +ntb_random_seed=1168891505 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tg l+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_na me 2.chip_sw_flash_ctrl_clock_freqs.1168891505 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/2.chip_sw_flash_ctrl_clock_freqs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_flash_ctrl_idle_low_power.1599063781 |
| Short name | T1085 |
| Test name | |
| Test status | |
| Simulation time | 2911202596 ps |
| CPU time | 249.53 seconds |
| Started | Aug 24 01:13:02 PM UTC 24 |
| Finished | Aug 24 01:17:14 PM UTC 24 |
| Peak memory | 624788 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=flash_ctrl_idle_low_power _test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/too ls/sim.tcl +ntb_random_seed=1599063781 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm _name 2.chip_sw_flash_ctrl_idle_low_power.1599063781 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/2.chip_sw_flash_ctrl_idle_low_power/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_flash_ctrl_lc_rw_en.1262263627 |
| Short name | T1086 |
| Test name | |
| Test status | |
| Simulation time | 5336865715 ps |
| CPU time | 350.75 seconds |
| Started | Aug 24 01:12:15 PM UTC 24 |
| Finished | Aug 24 01:18:10 PM UTC 24 |
| Peak memory | 626908 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv + sw_images=flash_ctrl_lc_rw_en_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli - do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1262263627 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_flash_ct rl_lc_rw_en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vc s/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_flash_ctrl_lc_rw_en.1262263627 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/2.chip_sw_flash_ctrl_lc_rw_en/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_flash_ctrl_mem_protection.1614087372 |
| Short name | T1232 |
| Test name | |
| Test status | |
| Simulation time | 5500878010 ps |
| CPU time | 758.8 seconds |
| Started | Aug 24 02:41:24 PM UTC 24 |
| Finished | Aug 24 02:54:11 PM UTC 24 |
| Peak memory | 624796 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=flash_ctrl_mem_protection _test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/too ls/sim.tcl +ntb_random_seed=1614087372 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm _name 2.chip_sw_flash_ctrl_mem_protection.1614087372 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/2.chip_sw_flash_ctrl_mem_protection/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_flash_ctrl_ops_jitter_en.364614860 |
| Short name | T1087 |
| Test name | |
| Test status | |
| Simulation time | 3866761095 ps |
| CPU time | 443.22 seconds |
| Started | Aug 24 01:11:27 PM UTC 24 |
| Finished | Aug 24 01:18:57 PM UTC 24 |
| Peak memory | 624820 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=50_000_000 +en_jitter=1 +sw_build_device =sim_dv +sw_images=flash_ctrl_ops_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=364614860 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 2.chip_sw_flash_ctrl_ops_jitter_en.364614860 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/2.chip_sw_flash_ctrl_ops_jitter_en/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_flash_ctrl_ops_jitter_en_reduced_freq.1685902909 |
| Short name | T1225 |
| Test name | |
| Test status | |
| Simulation time | 5165268937 ps |
| CPU time | 488.65 seconds |
| Started | Aug 24 02:37:18 PM UTC 24 |
| Finished | Aug 24 02:45:33 PM UTC 24 |
| Peak memory | 625076 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=50_000_000 +en_jitter=1 +cal_sys_clk_70m hz=1 +sw_build_device=sim_dv +sw_images=flash_ctrl_ops_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1685902909 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_ TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_a sic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_flash_ctrl_ops_jitter_en_reduced_freq.1685902909 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/2.chip_sw_flash_ctrl_ops_jitter_en_reduced_freq/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_flash_ctrl_write_clear.2884664511 |
| Short name | T1215 |
| Test name | |
| Test status | |
| Simulation time | 3613453872 ps |
| CPU time | 234.08 seconds |
| Started | Aug 24 02:36:17 PM UTC 24 |
| Finished | Aug 24 02:40:14 PM UTC 24 |
| Peak memory | 624564 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/default/simv +test_timeout_ns=8_000_000 +sw_build_device=sim_dv +sw_image s=flash_ctrl_write_clear_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2884664511 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 2.chip_sw_flash_ctrl_write_clear.2884664511 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/2.chip_sw_flash_ctrl_write_clear/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_flash_init_reduced_freq.310296174 |
| Short name | T1249 |
| Test name | |
| Test status | |
| Simulation time | 18684672501 ps |
| CPU time | 1506.01 seconds |
| Started | Aug 24 02:39:02 PM UTC 24 |
| Finished | Aug 24 03:04:25 PM UTC 24 |
| Peak memory | 632032 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=25_000_000 +cal_sys_clk_70mhz=1 +sw_buil d_device=sim_dv +sw_images=flash_init_test:0:test_in_rom:new_rules +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu e -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=310296174 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_ flash_init_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_flash_init_reduced_freq.310296174 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/2.chip_sw_flash_init_reduced_freq/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_flash_scrambling_smoketest.2510517233 |
| Short name | T1223 |
| Test name | |
| Test status | |
| Simulation time | 3425617076 ps |
| CPU time | 202.64 seconds |
| Started | Aug 24 02:41:30 PM UTC 24 |
| Finished | Aug 24 02:44:56 PM UTC 24 |
| Peak memory | 627052 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/default/simv +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_ima ges=flash_scrambling_smoketest:1:new_rules,flash_scrambling_smoketest_otp_img_rma:4,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2510517233 -assert nopostproc +UVM_TESTNAME=chip_bas e_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/chi p_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_flash_scrambling_smoketest.2510517233 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/2.chip_sw_flash_scrambling_smoketest/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_gpio_smoketest.3132280904 |
| Short name | T1238 |
| Test name | |
| Test status | |
| Simulation time | 3172182333 ps |
| CPU time | 202.36 seconds |
| Started | Aug 24 02:54:55 PM UTC 24 |
| Finished | Aug 24 02:58:21 PM UTC 24 |
| Peak memory | 624564 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=gpio_smoketest:1:new_rule s,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ random_seed=3132280904 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.ch ip_sw_gpio_smoketest.3132280904 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/2.chip_sw_gpio_smoketest/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_hmac_enc.1111447181 |
| Short name | T1158 |
| Test name | |
| Test status | |
| Simulation time | 2355802820 ps |
| CPU time | 188.2 seconds |
| Started | Aug 24 01:57:47 PM UTC 24 |
| Finished | Aug 24 02:00:58 PM UTC 24 |
| Peak memory | 624568 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=hmac_enc_test:1:new_rules ,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_r andom_seed=1111447181 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_h mac_enc.1111447181 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/2.chip_sw_hmac_enc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_hmac_enc_idle.3571438373 |
| Short name | T1161 |
| Test name | |
| Test status | |
| Simulation time | 2829357028 ps |
| CPU time | 206.99 seconds |
| Started | Aug 24 01:59:31 PM UTC 24 |
| Finished | Aug 24 02:03:02 PM UTC 24 |
| Peak memory | 624572 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=hmac_enc_idle_test:1:new_ rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl + ntb_random_seed=3571438373 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip _sw_hmac_enc_idle.3571438373 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/2.chip_sw_hmac_enc_idle/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_hmac_enc_jitter_en.2510002057 |
| Short name | T1159 |
| Test name | |
| Test status | |
| Simulation time | 2888485526 ps |
| CPU time | 194.87 seconds |
| Started | Aug 24 01:58:13 PM UTC 24 |
| Finished | Aug 24 02:01:31 PM UTC 24 |
| Peak memory | 624568 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/default/simv +en_jitter=1 +sw_build_device=sim_dv +sw_images=hmac_enc_tes t:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/s im.tcl +ntb_random_seed=2510002057 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam e 2.chip_sw_hmac_enc_jitter_en.2510002057 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/2.chip_sw_hmac_enc_jitter_en/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_hmac_enc_jitter_en_reduced_freq.3897247389 |
| Short name | T1218 |
| Test name | |
| Test status | |
| Simulation time | 2810298447 ps |
| CPU time | 170.36 seconds |
| Started | Aug 24 02:38:06 PM UTC 24 |
| Finished | Aug 24 02:40:59 PM UTC 24 |
| Peak memory | 624820 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/default/simv +en_jitter=1 +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +s w_images=hmac_enc_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac es/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3897247389 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_ log /dev/null -cm_name 2.chip_sw_hmac_enc_jitter_en_reduced_freq.3897247389 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/2.chip_sw_hmac_enc_jitter_en_reduced_freq/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_hmac_multistream.82765181 |
| Short name | T1184 |
| Test name | |
| Test status | |
| Simulation time | 8448506950 ps |
| CPU time | 1196.07 seconds |
| Started | Aug 24 02:01:31 PM UTC 24 |
| Finished | Aug 24 02:21:41 PM UTC 24 |
| Peak memory | 624832 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=hmac_multistream_functest :1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/si m.tcl +ntb_random_seed=82765181 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2 .chip_sw_hmac_multistream.82765181 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/2.chip_sw_hmac_multistream/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_hmac_oneshot.295541996 |
| Short name | T1162 |
| Test name | |
| Test status | |
| Simulation time | 3215313380 ps |
| CPU time | 218.21 seconds |
| Started | Aug 24 02:00:49 PM UTC 24 |
| Finished | Aug 24 02:04:31 PM UTC 24 |
| Peak memory | 624568 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=hmac_functest:1:new_rules ,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_r andom_seed=295541996 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_hm ac_oneshot.295541996 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/2.chip_sw_hmac_oneshot/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_hmac_smoketest.3737626488 |
| Short name | T1240 |
| Test name | |
| Test status | |
| Simulation time | 3317260060 ps |
| CPU time | 217.21 seconds |
| Started | Aug 24 02:56:02 PM UTC 24 |
| Finished | Aug 24 02:59:42 PM UTC 24 |
| Peak memory | 624820 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=hmac_smoketest:1:new_rule s,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ random_seed=3737626488 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_ hmac_smoketest.3737626488 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/2.chip_sw_hmac_smoketest/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_i2c_device_tx_rx.592675640 |
| Short name | T366 |
| Test name | |
| Test status | |
| Simulation time | 4317521250 ps |
| CPU time | 453.96 seconds |
| Started | Aug 24 01:03:23 PM UTC 24 |
| Finished | Aug 24 01:11:03 PM UTC 24 |
| Peak memory | 627320 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=i2c_device_tx_rx_test:1:n ew_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc l +ntb_random_seed=592675640 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_i2c_device_tx_rx_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null - cm_name 2.chip_sw_i2c_device_tx_rx.592675640 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/2.chip_sw_i2c_device_tx_rx/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_i2c_host_tx_rx.3801714816 |
| Short name | T374 |
| Test name | |
| Test status | |
| Simulation time | 5127307920 ps |
| CPU time | 507.67 seconds |
| Started | Aug 24 01:00:59 PM UTC 24 |
| Finished | Aug 24 01:09:34 PM UTC 24 |
| Peak memory | 627148 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/default/simv +i2c_idx=0 +sw_build_device=sim_dv +sw_images=i2c_host_tx_rx _test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/too ls/sim.tcl +ntb_random_seed=3801714816 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_i2c_host_tx_rx_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /de v/null -cm_name 2.chip_sw_i2c_host_tx_rx.3801714816 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/2.chip_sw_i2c_host_tx_rx/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_i2c_host_tx_rx_idx1.1208517064 |
| Short name | T1081 |
| Test name | |
| Test status | |
| Simulation time | 5229324906 ps |
| CPU time | 560.8 seconds |
| Started | Aug 24 01:02:23 PM UTC 24 |
| Finished | Aug 24 01:11:51 PM UTC 24 |
| Peak memory | 625012 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/default/simv +i2c_idx=1 +sw_build_device=sim_dv +sw_images=i2c_host_tx_rx _test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/too ls/sim.tcl +ntb_random_seed=1208517064 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_i2c_host_tx_rx_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /de v/null -cm_name 2.chip_sw_i2c_host_tx_rx_idx1.1208517064 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/2.chip_sw_i2c_host_tx_rx_idx1/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_i2c_host_tx_rx_idx2.794140094 |
| Short name | T1083 |
| Test name | |
| Test status | |
| Simulation time | 5344834534 ps |
| CPU time | 560.4 seconds |
| Started | Aug 24 01:03:10 PM UTC 24 |
| Finished | Aug 24 01:12:37 PM UTC 24 |
| Peak memory | 624756 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/default/simv +i2c_idx=2 +sw_build_device=sim_dv +sw_images=i2c_host_tx_rx _test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/too ls/sim.tcl +ntb_random_seed=794140094 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_i2c_host_tx_rx_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev /null -cm_name 2.chip_sw_i2c_host_tx_rx_idx2.794140094 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/2.chip_sw_i2c_host_tx_rx_idx2/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_inject_scramble_seed.2823145329 |
| Short name | T1313 |
| Test name | |
| Test status | |
| Simulation time | 66449687777 ps |
| CPU time | 10845 seconds |
| Started | Aug 24 12:55:50 PM UTC 24 |
| Finished | Aug 24 03:58:28 PM UTC 24 |
| Peak memory | 644192 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/default/simv +lc_at_prod=1 +flash_program_latency=5 +sw_test_timeout_ns=1 50_000_000 +sw_build_device=sim_dv +sw_images=inject_scramble_seed:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2823145329 -assert nopostproc +UVM_TESTNAME=chip_base_tes t +UVM_TEST_SEQ=chip_sw_inject_scramble_seed_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_08_22/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_inject_scramble_seed.2823145329 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/2.chip_sw_inject_scramble_seed/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_keymgr_key_derivation.3096193493 |
| Short name | T1191 |
| Test name | |
| Test status | |
| Simulation time | 9926301800 ps |
| CPU time | 1566.58 seconds |
| Started | Aug 24 02:01:32 PM UTC 24 |
| Finished | Aug 24 02:27:55 PM UTC 24 |
| Peak memory | 636468 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=20_000_000 +sw_build_device=sim_dv +sw_i mages=keymgr_key_derivation_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3096193493 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_keymgr_key _derivation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vc s/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_keymgr_key_derivation.3096193493 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/2.chip_sw_keymgr_key_derivation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_keymgr_key_derivation_jitter_en.2495852411 |
| Short name | T1183 |
| Test name | |
| Test status | |
| Simulation time | 9093601668 ps |
| CPU time | 1107.36 seconds |
| Started | Aug 24 02:02:23 PM UTC 24 |
| Finished | Aug 24 02:21:03 PM UTC 24 |
| Peak memory | 633048 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=20_000_000 +en_jitter=1 +sw_build_device =sim_dv +sw_images=keymgr_key_derivation_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu eue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2495852411 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_ sw_keymgr_key_derivation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgre y_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_keymgr_key_derivation_jitter_en.2495852411 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/2.chip_sw_keymgr_key_derivation_jitter_en/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_keymgr_key_derivation_jitter_en_reduced_freq.1330588147 |
| Short name | T1235 |
| Test name | |
| Test status | |
| Simulation time | 11361870570 ps |
| CPU time | 1124.39 seconds |
| Started | Aug 24 02:38:19 PM UTC 24 |
| Finished | Aug 24 02:57:15 PM UTC 24 |
| Peak memory | 636060 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=20_000_000 +en_jitter=1 +cal_sys_clk_70m hz=1 +sw_build_device=sim_dv +sw_images=keymgr_key_derivation_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1330588147 -assert nopostproc +UVM_TESTNAME=chip_base_tes t +UVM_TEST_SEQ=chip_sw_keymgr_key_derivation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_22/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_keymgr_key_derivation_jitter_en_reduced_freq.1330588147 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/2.chip_sw_keymgr_key_derivation_jitter_en_reduced_freq/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_keymgr_key_derivation_prod.635377193 |
| Short name | T1178 |
| Test name | |
| Test status | |
| Simulation time | 8193089288 ps |
| CPU time | 940.77 seconds |
| Started | Aug 24 02:01:55 PM UTC 24 |
| Finished | Aug 24 02:17:47 PM UTC 24 |
| Peak memory | 633080 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/default/simv +lc_at_prod=1 +sw_test_timeout_ns=20_000_000 +sw_build_devic e=sim_dv +sw_images=keymgr_key_derivation_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=635377193 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_ sw_keymgr_key_derivation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgre y_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_keymgr_key_derivation_prod.635377193 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/2.chip_sw_keymgr_key_derivation_prod/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_keymgr_sideload_aes.3191192015 |
| Short name | T318 |
| Test name | |
| Test status | |
| Simulation time | 10115566520 ps |
| CPU time | 1501.16 seconds |
| Started | Aug 24 02:04:06 PM UTC 24 |
| Finished | Aug 24 02:29:24 PM UTC 24 |
| Peak memory | 629828 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=20_000_000 +sw_build_device=sim_dv +sw_i mages=keymgr_sideload_aes_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3191192015 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_keymgr_sidel oad_aes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_keymgr_sideload_aes.3191192015 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/2.chip_sw_keymgr_sideload_aes/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_keymgr_sideload_kmac.861569127 |
| Short name | T1186 |
| Test name | |
| Test status | |
| Simulation time | 8741186774 ps |
| CPU time | 1216.66 seconds |
| Started | Aug 24 02:03:27 PM UTC 24 |
| Finished | Aug 24 02:23:58 PM UTC 24 |
| Peak memory | 626696 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=20_000_000 +sw_build_device=sim_dv +sw_i mages=keymgr_sideload_kmac_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=861569127 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_keymgr_sidel oad_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_keymgr_sideload_kmac.861569127 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/2.chip_sw_keymgr_sideload_kmac/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_keymgr_sideload_otbn.893544898 |
| Short name | T320 |
| Test name | |
| Test status | |
| Simulation time | 16938248086 ps |
| CPU time | 3630.44 seconds |
| Started | Aug 24 02:05:01 PM UTC 24 |
| Finished | Aug 24 03:06:10 PM UTC 24 |
| Peak memory | 629864 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=20_000_000 +sw_build_device=sim_dv +sw_i mages=keymgr_sideload_otbn_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=893544898 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default. vdb -cm_log /dev/null -cm_name 2.chip_sw_keymgr_sideload_otbn.893544898 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/2.chip_sw_keymgr_sideload_otbn/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_kmac_app_rom.496155695 |
| Short name | T1171 |
| Test name | |
| Test status | |
| Simulation time | 2864738598 ps |
| CPU time | 194.06 seconds |
| Started | Aug 24 02:08:58 PM UTC 24 |
| Finished | Aug 24 02:12:16 PM UTC 24 |
| Peak memory | 624556 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=kmac_app_rom_test:1:new_r ules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +n tb_random_seed=496155695 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as sert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_s w_kmac_app_rom.496155695 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/2.chip_sw_kmac_app_rom/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_kmac_entropy.902534697 |
| Short name | T1090 |
| Test name | |
| Test status | |
| Simulation time | 3282796288 ps |
| CPU time | 208.23 seconds |
| Started | Aug 24 01:17:39 PM UTC 24 |
| Finished | Aug 24 01:21:10 PM UTC 24 |
| Peak memory | 624816 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=kmac_entropy_test:1:new_r ules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +n tb_random_seed=902534697 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as sert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_s w_kmac_entropy.902534697 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/2.chip_sw_kmac_entropy/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_kmac_idle.869174628 |
| Short name | T1173 |
| Test name | |
| Test status | |
| Simulation time | 2772085470 ps |
| CPU time | 190.41 seconds |
| Started | Aug 24 02:10:34 PM UTC 24 |
| Finished | Aug 24 02:13:47 PM UTC 24 |
| Peak memory | 624772 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=kmac_idle_test:1:new_rule s,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ random_seed=869174628 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_k mac_idle.869174628 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/2.chip_sw_kmac_idle/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_kmac_mode_cshake.1720303053 |
| Short name | T1165 |
| Test name | |
| Test status | |
| Simulation time | 2575662448 ps |
| CPU time | 178.5 seconds |
| Started | Aug 24 02:05:04 PM UTC 24 |
| Finished | Aug 24 02:08:05 PM UTC 24 |
| Peak memory | 626612 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=kmac_mode_cshake_test:1:n ew_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc l +ntb_random_seed=1720303053 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.c hip_sw_kmac_mode_cshake.1720303053 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/2.chip_sw_kmac_mode_cshake/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_kmac_mode_kmac.3443794998 |
| Short name | T1172 |
| Test name | |
| Test status | |
| Simulation time | 3613926532 ps |
| CPU time | 267.51 seconds |
| Started | Aug 24 02:08:36 PM UTC 24 |
| Finished | Aug 24 02:13:07 PM UTC 24 |
| Peak memory | 624960 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=kmac_mode_kmac_test:1:new _rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3443794998 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.chi p_sw_kmac_mode_kmac.3443794998 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/2.chip_sw_kmac_mode_kmac/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_kmac_mode_kmac_jitter_en.2023070143 |
| Short name | T1170 |
| Test name | |
| Test status | |
| Simulation time | 2727218161 ps |
| CPU time | 190.39 seconds |
| Started | Aug 24 02:08:36 PM UTC 24 |
| Finished | Aug 24 02:11:49 PM UTC 24 |
| Peak memory | 626848 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/default/simv +en_jitter=1 +sw_build_device=sim_dv +sw_images=kmac_mode_km ac_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/t ools/sim.tcl +ntb_random_seed=2023070143 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null - cm_name 2.chip_sw_kmac_mode_kmac_jitter_en.2023070143 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/2.chip_sw_kmac_mode_kmac_jitter_en/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_kmac_mode_kmac_jitter_en_reduced_freq.3978684972 |
| Short name | T1221 |
| Test name | |
| Test status | |
| Simulation time | 3174206478 ps |
| CPU time | 220.53 seconds |
| Started | Aug 24 02:38:44 PM UTC 24 |
| Finished | Aug 24 02:42:28 PM UTC 24 |
| Peak memory | 625040 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/default/simv +en_jitter=1 +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +s w_images=kmac_mode_kmac_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo rkspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3978684972 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default.vd b -cm_log /dev/null -cm_name 2.chip_sw_kmac_mode_kmac_jitter_en_reduced_freq.3978684972 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/2.chip_sw_kmac_mode_kmac_jitter_en_reduced_freq/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_kmac_smoketest.2898478865 |
| Short name | T1242 |
| Test name | |
| Test status | |
| Simulation time | 2550661120 ps |
| CPU time | 201.06 seconds |
| Started | Aug 24 02:57:39 PM UTC 24 |
| Finished | Aug 24 03:01:03 PM UTC 24 |
| Peak memory | 624564 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=kmac_smoketest:1:new_rule s,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ random_seed=2898478865 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_ kmac_smoketest.2898478865 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/2.chip_sw_kmac_smoketest/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_lc_ctrl_otp_hw_cfg0.371565821 |
| Short name | T1092 |
| Test name | |
| Test status | |
| Simulation time | 3083655632 ps |
| CPU time | 213.24 seconds |
| Started | Aug 24 01:18:14 PM UTC 24 |
| Finished | Aug 24 01:21:51 PM UTC 24 |
| Peak memory | 626612 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=lc_ctrl_otp_hw_cfg0_test: 1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim .tcl +ntb_random_seed=371565821 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2 .chip_sw_lc_ctrl_otp_hw_cfg0.371565821 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/2.chip_sw_lc_ctrl_otp_hw_cfg0/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_lc_ctrl_program_error.1311631791 |
| Short name | T211 |
| Test name | |
| Test status | |
| Simulation time | 4472458614 ps |
| CPU time | 279.27 seconds |
| Started | Aug 24 02:29:56 PM UTC 24 |
| Finished | Aug 24 02:34:39 PM UTC 24 |
| Peak memory | 627116 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/default/simv +en_scb=0 +bypass_alert_ready_to_end_check=1 +sw_build_devic e=sim_dv +sw_images=lc_ctrl_program_error:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1311631791 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_l c_ctrl_program_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_as ic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_lc_ctrl_program_error.1311631791 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/2.chip_sw_lc_ctrl_program_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_lc_ctrl_rand_to_scrap.3027571050 |
| Short name | T1101 |
| Test name | |
| Test status | |
| Simulation time | 3613846509 ps |
| CPU time | 129.02 seconds |
| Started | Aug 24 01:22:18 PM UTC 24 |
| Finished | Aug 24 01:24:29 PM UTC 24 |
| Peak memory | 636604 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv + sw_images=lc_ctrl_scrap_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo rkspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3027571050 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_ctrl_scrap_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 2.chip_sw_lc_ctrl_rand_to_scrap.3027571050 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/2.chip_sw_lc_ctrl_rand_to_scrap/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_lc_ctrl_transition.573273058 |
| Short name | T1113 |
| Test name | |
| Test status | |
| Simulation time | 11706818861 ps |
| CPU time | 600.81 seconds |
| Started | Aug 24 01:21:35 PM UTC 24 |
| Finished | Aug 24 01:31:43 PM UTC 24 |
| Peak memory | 639316 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=lc_ctrl_transition_test:1 :new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim. tcl +ntb_random_seed=573273058 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_ctrl_transition_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/nu ll -cm_name 2.chip_sw_lc_ctrl_transition.573273058 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/2.chip_sw_lc_ctrl_transition/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_lc_ctrl_volatile_raw_unlock.1049589982 |
| Short name | T1102 |
| Test name | |
| Test status | |
| Simulation time | 2280547126 ps |
| CPU time | 81.47 seconds |
| Started | Aug 24 01:23:13 PM UTC 24 |
| Finished | Aug 24 01:24:36 PM UTC 24 |
| Peak memory | 634288 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/default/simv +use_otp_image=OtpTypeLcStRaw +exp_volatile_raw_unlock_en=0 +sw_build_device=sim_dv +sw_images=lc_ctrl_volatile_raw_unlock_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1049589982 -assert nopostproc +UVM_TESTNAME=chip_base_te st +UVM_TEST_SEQ=chip_sw_lc_volatile_raw_unlock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_lc_ctrl_volatile_raw_unlock.1049589982 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/2.chip_sw_lc_ctrl_volatile_raw_unlock/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz.4130493127 |
| Short name | T1103 |
| Test name | |
| Test status | |
| Simulation time | 2365351399 ps |
| CPU time | 86.85 seconds |
| Started | Aug 24 01:23:25 PM UTC 24 |
| Finished | Aug 24 01:24:53 PM UTC 24 |
| Peak memory | 634784 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/default/simv +use_otp_image=OtpTypeLcStRaw +chip_clock_source=ChipClockSo urceExternal48Mhz +exp_volatile_raw_unlock_en=0 +sw_build_device=sim_dv +sw_images=lc_ctrl_volatile_raw_unlock_test:1:new_rules,test_rom:0 +cdc_in strumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=41304931 27 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_volatile_raw_unlock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_lc _ctrl_volatile_raw_unlock_ext_clk_48mhz.4130493127 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/2.chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_lc_walkthrough_dev.136684197 |
| Short name | T1203 |
| Test name | |
| Test status | |
| Simulation time | 47793438545 ps |
| CPU time | 4264.56 seconds |
| Started | Aug 24 01:22:18 PM UTC 24 |
| Finished | Aug 24 02:34:09 PM UTC 24 |
| Peak memory | 644380 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/default/simv +flash_program_latency=5 +use_otp_image=OtpTypeLcStRaw +dest _dec_state=DecLcStDev +sw_test_timeout_ns=200_000_000 +sw_build_device=sim_dv +sw_images=lc_walkthrough_test:1:new_rules,test_rom:0 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=136684197 -asse rt nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_walkthrough_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp aces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_lc_walkthrough_dev.136684197 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/2.chip_sw_lc_walkthrough_dev/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_lc_walkthrough_prod.2926152810 |
| Short name | T1217 |
| Test name | |
| Test status | |
| Simulation time | 51508525255 ps |
| CPU time | 4644.62 seconds |
| Started | Aug 24 01:22:28 PM UTC 24 |
| Finished | Aug 24 02:40:43 PM UTC 24 |
| Peak memory | 644480 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/default/simv +flash_program_latency=5 +use_otp_image=OtpTypeLcStRaw +dest _dec_state=DecLcStProd +sw_test_timeout_ns=200_000_000 +sw_build_device=sim_dv +sw_images=lc_walkthrough_test:1:new_rules,test_rom:0 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2926152810 -as sert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_walkthrough_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work spaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_lc_walkthrough_prod.2926152810 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/2.chip_sw_lc_walkthrough_prod/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_lc_walkthrough_prodend.160342984 |
| Short name | T1116 |
| Test name | |
| Test status | |
| Simulation time | 9983452950 ps |
| CPU time | 624.89 seconds |
| Started | Aug 24 01:22:41 PM UTC 24 |
| Finished | Aug 24 01:33:14 PM UTC 24 |
| Peak memory | 641312 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/default/simv +flash_program_latency=5 +use_otp_image=OtpTypeLcStRaw +dest _dec_state=DecLcStProdEnd +sw_build_device=sim_dv +sw_images=lc_walkthrough_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=160342984 -assert nopostproc +UVM_TESTNAME= chip_base_test +UVM_TEST_SEQ=chip_sw_lc_walkthrough_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_lc_walkthrough_prodend.160342984 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/2.chip_sw_lc_walkthrough_prodend/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_lc_walkthrough_rma.3021485218 |
| Short name | T1214 |
| Test name | |
| Test status | |
| Simulation time | 48914712612 ps |
| CPU time | 4515.86 seconds |
| Started | Aug 24 01:23:55 PM UTC 24 |
| Finished | Aug 24 02:39:59 PM UTC 24 |
| Peak memory | 644260 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/default/simv +use_otp_image=OtpTypeLcStRaw +dest_dec_state=DecLcStRma +fl ash_program_latency=5 +sw_test_timeout_ns=200_000_000 +sw_build_device=sim_dv +sw_images=lc_walkthrough_test:1:new_rules,test_rom:0 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3021485218 -ass ert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_walkthrough_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works paces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_lc_walkthrough_rma.3021485218 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/2.chip_sw_lc_walkthrough_rma/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_lc_walkthrough_testunlocks.472334380 |
| Short name | T1144 |
| Test name | |
| Test status | |
| Simulation time | 23360576704 ps |
| CPU time | 1465.72 seconds |
| Started | Aug 24 01:25:15 PM UTC 24 |
| Finished | Aug 24 01:49:57 PM UTC 24 |
| Peak memory | 641092 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/default/simv +use_otp_image=OtpTypeLcStRaw +dest_dec_state=DecLcStTestUnl ock7 +sw_build_device=sim_dv +sw_images=lc_walkthrough_testunlocks_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=472334380 -assert nopostproc +UVM_TESTNAME=chip_base _test +UVM_TEST_SEQ=chip_sw_lc_walkthrough_testunlocks_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_lc_walkthrough_testunlocks.472334380 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/2.chip_sw_lc_walkthrough_testunlocks/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_otbn_ecdsa_op_irq.985801287 |
| Short name | T1202 |
| Test name | |
| Test status | |
| Simulation time | 17245702700 ps |
| CPU time | 3077.99 seconds |
| Started | Aug 24 01:42:10 PM UTC 24 |
| Finished | Aug 24 02:34:00 PM UTC 24 |
| Peak memory | 629836 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=28_000_000 +rng_srate_value=30 +sw_build _device=sim_dv +sw_images=otbn_ecdsa_op_irq_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=985801287 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chi p_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_otbn_ecdsa_op_irq.985801287 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/2.chip_sw_otbn_ecdsa_op_irq/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_otbn_ecdsa_op_irq_jitter_en.1957493146 |
| Short name | T1208 |
| Test name | |
| Test status | |
| Simulation time | 18972286016 ps |
| CPU time | 3261.31 seconds |
| Started | Aug 24 01:42:11 PM UTC 24 |
| Finished | Aug 24 02:37:08 PM UTC 24 |
| Peak memory | 629796 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=33_000_000 +rng_srate_value=30 +en_jitte r=1 +sw_build_device=sim_dv +sw_images=otbn_ecdsa_op_irq_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1957493146 -assert nopostproc +UVM_TESTNAME=chip_base_test +UV M_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey _asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_otbn_ecdsa_op_irq_jitter_en.1957493146 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/2.chip_sw_otbn_ecdsa_op_irq_jitter_en/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq.752512748 |
| Short name | T1283 |
| Test name | |
| Test status | |
| Simulation time | 24719069992 ps |
| CPU time | 3158.08 seconds |
| Started | Aug 24 02:37:54 PM UTC 24 |
| Finished | Aug 24 03:31:06 PM UTC 24 |
| Peak memory | 629796 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=33_000_000 +rng_srate_value=30 +en_jitte r=1 +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +sw_images=otbn_ecdsa_op_irq_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=752512748 -assert nopostproc +UVM_TESTNAM E=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _08_22/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq.752512748 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/2.chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_otbn_mem_scramble.3767096917 |
| Short name | T1143 |
| Test name | |
| Test status | |
| Simulation time | 3373002008 ps |
| CPU time | 364.36 seconds |
| Started | Aug 24 01:42:11 PM UTC 24 |
| Finished | Aug 24 01:48:20 PM UTC 24 |
| Peak memory | 626856 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=15_000_000 +en_scb_tl_err_chk=0 +bypass_ alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=otbn_mem_scramble_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3767096917 -assert nopostproc +UVM_TEST NAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_otbn_mem_scramble.3767096917 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/2.chip_sw_otbn_mem_scramble/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_otbn_randomness.281471691 |
| Short name | T1146 |
| Test name | |
| Test status | |
| Simulation time | 5700021264 ps |
| CPU time | 631.13 seconds |
| Started | Aug 24 01:40:12 PM UTC 24 |
| Finished | Aug 24 01:50:51 PM UTC 24 |
| Peak memory | 626756 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=18_000_000 +rng_srate_value=30 +sw_build _device=sim_dv +sw_images=otbn_randomness_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=281471691 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_ sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_otbn_randomness.281471691 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/2.chip_sw_otbn_randomness/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_otbn_smoketest.3129379439 |
| Short name | T1260 |
| Test name | |
| Test status | |
| Simulation time | 6649663380 ps |
| CPU time | 950.68 seconds |
| Started | Aug 24 02:57:56 PM UTC 24 |
| Finished | Aug 24 03:13:58 PM UTC 24 |
| Peak memory | 626928 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=otbn_smoketest:1:new_rule s,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ random_seed=3129379439 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_ otbn_smoketest.3129379439 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/2.chip_sw_otbn_smoketest/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_otp_ctrl_ecc_error_vendor_test.2474788619 |
| Short name | T1099 |
| Test name | |
| Test status | |
| Simulation time | 2882311492 ps |
| CPU time | 176.3 seconds |
| Started | Aug 24 01:21:20 PM UTC 24 |
| Finished | Aug 24 01:24:19 PM UTC 24 |
| Peak memory | 624560 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=otp_ctrl_vendor_test_ecc_ error_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/d v/tools/sim.tcl +ntb_random_seed=2474788619 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_otp_ctrl_vendor_test_ecc_error_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/de fault.vdb -cm_log /dev/null -cm_name 2.chip_sw_otp_ctrl_ecc_error_vendor_test.2474788619 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/2.chip_sw_otp_ctrl_ecc_error_vendor_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_otp_ctrl_lc_signals_dev.781440203 |
| Short name | T1115 |
| Test name | |
| Test status | |
| Simulation time | 8160492272 ps |
| CPU time | 809.94 seconds |
| Started | Aug 24 01:18:52 PM UTC 24 |
| Finished | Aug 24 01:32:31 PM UTC 24 |
| Peak memory | 626620 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/default/simv +use_otp_image=OtpTypeLcStDev +otp_clear_secret2=1 +sw_build _device=sim_dv +sw_images=otp_ctrl_lc_signals_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=781440203 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=c hip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vc s/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_otp_ctrl_lc_signals_dev.781440203 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/2.chip_sw_otp_ctrl_lc_signals_dev/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_otp_ctrl_lc_signals_prod.1495542016 |
| Short name | T1118 |
| Test name | |
| Test status | |
| Simulation time | 8536828484 ps |
| CPU time | 923.21 seconds |
| Started | Aug 24 01:19:20 PM UTC 24 |
| Finished | Aug 24 01:34:54 PM UTC 24 |
| Peak memory | 626632 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/default/simv +use_otp_image=OtpTypeLcStProd +otp_clear_secret2=1 +sw_buil d_device=sim_dv +sw_images=otp_ctrl_lc_signals_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1495542016 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ =chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_otp_ctrl_lc_signals_prod.1495542016 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/2.chip_sw_otp_ctrl_lc_signals_prod/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_otp_ctrl_lc_signals_rma.1715661087 |
| Short name | T1117 |
| Test name | |
| Test status | |
| Simulation time | 7442842396 ps |
| CPU time | 733.16 seconds |
| Started | Aug 24 01:21:19 PM UTC 24 |
| Finished | Aug 24 01:33:41 PM UTC 24 |
| Peak memory | 624972 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/default/simv +use_otp_image=OtpTypeLcStRma +otp_clear_secret2=1 +sw_build _device=sim_dv +sw_images=otp_ctrl_lc_signals_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1715661087 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ= chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_otp_ctrl_lc_signals_rma.1715661087 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/2.chip_sw_otp_ctrl_lc_signals_rma/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_otp_ctrl_lc_signals_test_unlocked0.4098783503 |
| Short name | T1107 |
| Test name | |
| Test status | |
| Simulation time | 5055329886 ps |
| CPU time | 512.11 seconds |
| Started | Aug 24 01:18:34 PM UTC 24 |
| Finished | Aug 24 01:27:12 PM UTC 24 |
| Peak memory | 624568 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/default/simv +use_otp_image=OtpTypeLcStTestUnlocked0 +otp_clear_secret2=1 +sw_build_device=sim_dv +sw_images=otp_ctrl_lc_signals_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY =UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4098783503 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM _TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_ asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_otp_ctrl_lc_signals_test_unlocked0.4098783503 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/2.chip_sw_otp_ctrl_lc_signals_test_unlocked0/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_otp_ctrl_smoketest.818125015 |
| Short name | T1243 |
| Test name | |
| Test status | |
| Simulation time | 3692191156 ps |
| CPU time | 186.65 seconds |
| Started | Aug 24 02:58:09 PM UTC 24 |
| Finished | Aug 24 03:01:19 PM UTC 24 |
| Peak memory | 624820 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=otp_ctrl_smoketest:1:new_ rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl + ntb_random_seed=818125015 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a ssert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_ sw_otp_ctrl_smoketest.818125015 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/2.chip_sw_otp_ctrl_smoketest/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_pattgen_ios.2367560991 |
| Short name | T1072 |
| Test name | |
| Test status | |
| Simulation time | 3088765880 ps |
| CPU time | 193.7 seconds |
| Started | Aug 24 12:52:09 PM UTC 24 |
| Finished | Aug 24 12:55:26 PM UTC 24 |
| Peak memory | 624756 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=5_000_000 +sw_build_device=sim_dv +sw_im ages=pattgen_ios_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace s/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2367560991 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_patt_ios_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default.vdb - cm_log /dev/null -cm_name 2.chip_sw_pattgen_ios.2367560991 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/2.chip_sw_pattgen_ios/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_plic_sw_irq.3534058288 |
| Short name | T332 |
| Test name | |
| Test status | |
| Simulation time | 3114240080 ps |
| CPU time | 247.06 seconds |
| Started | Aug 24 02:19:22 PM UTC 24 |
| Finished | Aug 24 02:23:32 PM UTC 24 |
| Peak memory | 624560 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=plic_sw_irq_test:1:new_ru les,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +nt b_random_seed=3534058288 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as sert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_s w_plic_sw_irq.3534058288 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/2.chip_sw_plic_sw_irq/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_power_idle_load.1832082947 |
| Short name | T1226 |
| Test name | |
| Test status | |
| Simulation time | 4580597960 ps |
| CPU time | 481.84 seconds |
| Started | Aug 24 02:39:59 PM UTC 24 |
| Finished | Aug 24 02:48:07 PM UTC 24 |
| Peak memory | 624820 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=chip_power_idle_load:1:ne w_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1832082947 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_power_idle_load_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -c m_name 2.chip_sw_power_idle_load.1832082947 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/2.chip_sw_power_idle_load/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_power_sleep_load.4197728884 |
| Short name | T652 |
| Test name | |
| Test status | |
| Simulation time | 5042517746 ps |
| CPU time | 260.69 seconds |
| Started | Aug 24 02:41:08 PM UTC 24 |
| Finished | Aug 24 02:45:32 PM UTC 24 |
| Peak memory | 624836 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=chip_power_sleep_load:1:n ew_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc l +ntb_random_seed=4197728884 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_power_sleep_load_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_power_sleep_load.4197728884 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/2.chip_sw_power_sleep_load/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_power_virus.3491664178 |
| Short name | T130 |
| Test name | |
| Test status | |
| Simulation time | 5602943300 ps |
| CPU time | 1008.9 seconds |
| Started | Aug 24 02:41:30 PM UTC 24 |
| Finished | Aug 24 02:58:30 PM UTC 24 |
| Peak memory | 641628 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/default/simv +rng_srate_value_min=15 +rng_srate_value_max=20 +sw_test_tim eout_ns=400_000_000 +use_otp_image=OtpTypeCustom +accelerate_cold_power_up_time=3 +accelerate_regulators_power_up_time=2 +sw_build_device=sim_dv + sw_images=power_virus_systemtest:1:new_rules,power_virus_systemtest_otp_img_rma:4,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3491664178 -assert nopostproc +UVM_TESTNAME=chip_base_ test +UVM_TEST_SEQ=chip_sw_power_virus_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_2 2/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_power_virus.3491664178 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/2.chip_sw_power_virus/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_pwrmgr_all_reset_reqs.2142753523 |
| Short name | T1134 |
| Test name | |
| Test status | |
| Simulation time | 12359561286 ps |
| CPU time | 1077.08 seconds |
| Started | Aug 24 01:25:47 PM UTC 24 |
| Finished | Aug 24 01:43:56 PM UTC 24 |
| Peak memory | 626912 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=50_000_000 +sw_build_device=sim_dv +sw_i mages=pwrmgr_all_reset_reqs_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2142753523 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_deep_sleep _all_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_pwrmgr_all_reset_reqs.2142753523 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/2.chip_sw_pwrmgr_all_reset_reqs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_pwrmgr_b2b_sleep_reset_req.1472083201 |
| Short name | T1211 |
| Test name | |
| Test status | |
| Simulation time | 20699421186 ps |
| CPU time | 1304.38 seconds |
| Started | Aug 24 02:16:21 PM UTC 24 |
| Finished | Aug 24 02:38:20 PM UTC 24 |
| Peak memory | 629732 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=35_000_000 +sw_build_device=sim_dv +sw_i mages=pwrmgr_b2b_sleep_reset_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1472083201 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_repeat_re set_wkup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_pwrmgr_b2b_sleep_reset_req.1472083201 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/2.chip_sw_pwrmgr_b2b_sleep_reset_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_pwrmgr_deep_sleep_all_reset_reqs.894194271 |
| Short name | T1131 |
| Test name | |
| Test status | |
| Simulation time | 18223591278 ps |
| CPU time | 911.09 seconds |
| Started | Aug 24 01:27:37 PM UTC 24 |
| Finished | Aug 24 01:42:59 PM UTC 24 |
| Peak memory | 626760 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=50_000_000 +sw_build_device=sim_dv +sw_i mages=pwrmgr_deep_sleep_all_reset_reqs_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu e -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=894194271 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_ deep_sleep_all_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_as ic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_pwrmgr_deep_sleep_all_reset_reqs.894194271 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/2.chip_sw_pwrmgr_deep_sleep_all_reset_reqs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_pwrmgr_deep_sleep_all_wake_ups.1642048100 |
| Short name | T1227 |
| Test name | |
| Test status | |
| Simulation time | 23083765530 ps |
| CPU time | 1021.94 seconds |
| Started | Aug 24 02:31:08 PM UTC 24 |
| Finished | Aug 24 02:48:22 PM UTC 24 |
| Peak memory | 629732 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_i mages=pwrmgr_deep_sleep_all_wake_ups:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1642048100 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_pwrmgr _deep_sleep_all_wake_ups_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgre y_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_pwrmgr_deep_sleep_all_wake_ups.1642048100 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/2.chip_sw_pwrmgr_deep_sleep_all_wake_ups/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_pwrmgr_deep_sleep_por_reset.563120650 |
| Short name | T1119 |
| Test name | |
| Test status | |
| Simulation time | 9783510202 ps |
| CPU time | 318.07 seconds |
| Started | Aug 24 01:29:32 PM UTC 24 |
| Finished | Aug 24 01:34:55 PM UTC 24 |
| Peak memory | 626680 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=pwrmgr_deep_sleep_por_res et_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/t ools/sim.tcl +ntb_random_seed=563120650 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sleep_por_reset_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 2.chip_sw_pwrmgr_deep_sleep_por_reset.563120650 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/2.chip_sw_pwrmgr_deep_sleep_por_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_pwrmgr_deep_sleep_power_glitch_reset.23195036 |
| Short name | T1122 |
| Test name | |
| Test status | |
| Simulation time | 6731036300 ps |
| CPU time | 306.44 seconds |
| Started | Aug 24 01:30:46 PM UTC 24 |
| Finished | Aug 24 01:35:56 PM UTC 24 |
| Peak memory | 633040 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv + sw_images=pwrmgr_deep_sleep_power_glitch_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu eue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=23195036 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw _deep_power_glitch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_pwrmgr_deep_sleep_power_glitch_reset.23195036 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/2.chip_sw_pwrmgr_deep_sleep_power_glitch_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_pwrmgr_full_aon_reset.2517586580 |
| Short name | T1114 |
| Test name | |
| Test status | |
| Simulation time | 5952733800 ps |
| CPU time | 363.1 seconds |
| Started | Aug 24 01:25:44 PM UTC 24 |
| Finished | Aug 24 01:31:52 PM UTC 24 |
| Peak memory | 626748 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=rstmgr_smoketest:1:new_ru les,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +nt b_random_seed=2517586580 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_full_aon_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam e 2.chip_sw_pwrmgr_full_aon_reset.2517586580 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/2.chip_sw_pwrmgr_full_aon_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_pwrmgr_lowpower_cancel.424078254 |
| Short name | T369 |
| Test name | |
| Test status | |
| Simulation time | 4254950768 ps |
| CPU time | 343.11 seconds |
| Started | Aug 24 02:30:54 PM UTC 24 |
| Finished | Aug 24 02:36:41 PM UTC 24 |
| Peak memory | 624632 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=pwrmgr_lowpower_cancel_te st:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/ sim.tcl +ntb_random_seed=424078254 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam e 2.chip_sw_pwrmgr_lowpower_cancel.424078254 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/2.chip_sw_pwrmgr_lowpower_cancel/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_pwrmgr_main_power_glitch_reset.1103380974 |
| Short name | T1111 |
| Test name | |
| Test status | |
| Simulation time | 4535317140 ps |
| CPU time | 241.21 seconds |
| Started | Aug 24 01:25:44 PM UTC 24 |
| Finished | Aug 24 01:29:48 PM UTC 24 |
| Peak memory | 632992 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv + sw_images=pwrmgr_main_power_glitch_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1103380974 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_mai n_power_glitch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_pwrmgr_main_power_glitch_reset.1103380974 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/2.chip_sw_pwrmgr_main_power_glitch_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_pwrmgr_normal_sleep_all_reset_reqs.3371270771 |
| Short name | T1129 |
| Test name | |
| Test status | |
| Simulation time | 10346959382 ps |
| CPU time | 835.33 seconds |
| Started | Aug 24 01:28:07 PM UTC 24 |
| Finished | Aug 24 01:42:13 PM UTC 24 |
| Peak memory | 626748 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=pwrmgr_normal_sleep_all_r eset_reqs_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/ hw/dv/tools/sim.tcl +ntb_random_seed=3371270771 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_deep_sleep_all_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default. vdb -cm_log /dev/null -cm_name 2.chip_sw_pwrmgr_normal_sleep_all_reset_reqs.3371270771 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/2.chip_sw_pwrmgr_normal_sleep_all_reset_reqs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_pwrmgr_normal_sleep_all_wake_ups.2464340077 |
| Short name | T438 |
| Test name | |
| Test status | |
| Simulation time | 7503530150 ps |
| CPU time | 318.35 seconds |
| Started | Aug 24 02:29:56 PM UTC 24 |
| Finished | Aug 24 02:35:18 PM UTC 24 |
| Peak memory | 624636 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=pwrmgr_normal_sleep_all_w ake_ups:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/t ools/sim.tcl +ntb_random_seed=2464340077 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_pwrmgr_deep_sleep_all_wake_ups_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 2.chip_sw_pwrmgr_normal_sleep_all_wake_ups.2464340077 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/2.chip_sw_pwrmgr_normal_sleep_all_wake_ups/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_pwrmgr_normal_sleep_por_reset.4075472916 |
| Short name | T1123 |
| Test name | |
| Test status | |
| Simulation time | 7440285235 ps |
| CPU time | 471.97 seconds |
| Started | Aug 24 01:29:33 PM UTC 24 |
| Finished | Aug 24 01:37:31 PM UTC 24 |
| Peak memory | 626672 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=pwrmgr_normal_sleep_por_r eset_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv /tools/sim.tcl +ntb_random_seed=4075472916 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sleep_por_reset_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_lo g /dev/null -cm_name 2.chip_sw_pwrmgr_normal_sleep_por_reset.4075472916 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/2.chip_sw_pwrmgr_normal_sleep_por_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_pwrmgr_random_sleep_all_reset_reqs.4060753292 |
| Short name | T1153 |
| Test name | |
| Test status | |
| Simulation time | 26129786596 ps |
| CPU time | 1652.91 seconds |
| Started | Aug 24 01:26:24 PM UTC 24 |
| Finished | Aug 24 01:54:15 PM UTC 24 |
| Peak memory | 626764 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=50_000_000 +sw_build_device=sim_dv +sw_i mages=pwrmgr_random_sleep_all_reset_reqs_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu eue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4060753292 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_ sw_deep_sleep_all_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey _asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_pwrmgr_random_sleep_all_reset_reqs.4060753292 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/2.chip_sw_pwrmgr_random_sleep_all_reset_reqs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_pwrmgr_random_sleep_all_wake_ups.3187627176 |
| Short name | T657 |
| Test name | |
| Test status | |
| Simulation time | 23961045864 ps |
| CPU time | 1053.6 seconds |
| Started | Aug 24 02:31:24 PM UTC 24 |
| Finished | Aug 24 02:49:09 PM UTC 24 |
| Peak memory | 629672 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=18_000_000 +do_random=1 +sw_build_device =sim_dv +sw_images=pwrmgr_random_sleep_all_wake_ups:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3187627176 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ =chip_sw_pwrmgr_deep_sleep_all_wake_ups_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_ 22/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_pwrmgr_random_sleep_all_wake_ups.3187627176 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/2.chip_sw_pwrmgr_random_sleep_all_wake_ups/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up.3364487130 |
| Short name | T389 |
| Test name | |
| Test status | |
| Simulation time | 5266730472 ps |
| CPU time | 304.65 seconds |
| Started | Aug 24 02:32:19 PM UTC 24 |
| Finished | Aug 24 02:37:27 PM UTC 24 |
| Peak memory | 626828 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=18_000_000 +do_random=1 +sw_build_device =sim_dv +sw_images=pwrmgr_sensor_ctrl_deep_sleep_wake_up:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3364487130 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TES T_SEQ=chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up.3364487130 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/2.chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_pwrmgr_sleep_disabled.1480827536 |
| Short name | T647 |
| Test name | |
| Test status | |
| Simulation time | 2649351664 ps |
| CPU time | 154.66 seconds |
| Started | Aug 24 01:32:17 PM UTC 24 |
| Finished | Aug 24 01:34:54 PM UTC 24 |
| Peak memory | 625000 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=pwrmgr_sleep_disabled_tes t:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/s im.tcl +ntb_random_seed=1480827536 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam e 2.chip_sw_pwrmgr_sleep_disabled.1480827536 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/2.chip_sw_pwrmgr_sleep_disabled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup.2475325570 |
| Short name | T171 |
| Test name | |
| Test status | |
| Simulation time | 4763845700 ps |
| CPU time | 283.47 seconds |
| Started | Aug 24 02:15:44 PM UTC 24 |
| Finished | Aug 24 02:20:32 PM UTC 24 |
| Peak memory | 624772 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=8_000_000 +sw_build_device=sim_dv +sw_im ages=sensor_ctrl_wakeup_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo rkspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2475325570 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default.vd b -cm_log /dev/null -cm_name 2.chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup.2475325570 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/2.chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_pwrmgr_sleep_wake_5_bug.3944433458 |
| Short name | T1209 |
| Test name | |
| Test status | |
| Simulation time | 5541892160 ps |
| CPU time | 301.08 seconds |
| Started | Aug 24 02:32:17 PM UTC 24 |
| Finished | Aug 24 02:37:22 PM UTC 24 |
| Peak memory | 626752 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=18_000_000 +do_random=1 +sw_build_device =sim_dv +sw_images=pwrmgr_sleep_wake_5_bug_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3944433458 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chi p_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_pwrmgr_sleep_wake_5_bug.3944433458 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/2.chip_sw_pwrmgr_sleep_wake_5_bug/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_pwrmgr_smoketest.218070770 |
| Short name | T1247 |
| Test name | |
| Test status | |
| Simulation time | 5385757640 ps |
| CPU time | 284.74 seconds |
| Started | Aug 24 02:58:52 PM UTC 24 |
| Finished | Aug 24 03:03:40 PM UTC 24 |
| Peak memory | 625172 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=10000000 +sw_build_device=sim_dv +sw_ima ges=pwrmgr_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces /repo/hw/dv/tools/sim.tcl +ntb_random_seed=218070770 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_pwrmgr_smoketest.218070770 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/2.chip_sw_pwrmgr_smoketest/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_pwrmgr_sysrst_ctrl_reset.1120305967 |
| Short name | T1120 |
| Test name | |
| Test status | |
| Simulation time | 7675357840 ps |
| CPU time | 556.59 seconds |
| Started | Aug 24 01:25:43 PM UTC 24 |
| Finished | Aug 24 01:35:06 PM UTC 24 |
| Peak memory | 626624 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=pwrmgr_sysrst_ctrl_test:1 :new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim. tcl +ntb_random_seed=1120305967 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sysrst_ctrl_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm _name 2.chip_sw_pwrmgr_sysrst_ctrl_reset.1120305967 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/2.chip_sw_pwrmgr_sysrst_ctrl_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_pwrmgr_usb_clk_disabled_when_active.158930399 |
| Short name | T1125 |
| Test name | |
| Test status | |
| Simulation time | 4829529140 ps |
| CPU time | 334.4 seconds |
| Started | Aug 24 01:32:55 PM UTC 24 |
| Finished | Aug 24 01:38:34 PM UTC 24 |
| Peak memory | 626616 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=pwrmgr_usb_clk_disabled_w hen_active_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo /hw/dv/tools/sim.tcl +ntb_random_seed=158930399 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev /null -cm_name 2.chip_sw_pwrmgr_usb_clk_disabled_when_active.158930399 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/2.chip_sw_pwrmgr_usb_clk_disabled_when_active/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_pwrmgr_usbdev_smoketest.3732115123 |
| Short name | T1250 |
| Test name | |
| Test status | |
| Simulation time | 5531182020 ps |
| CPU time | 374.38 seconds |
| Started | Aug 24 02:58:54 PM UTC 24 |
| Finished | Aug 24 03:05:13 PM UTC 24 |
| Peak memory | 624632 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=pwrmgr_usbdev_smoketest:1 :new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim. tcl +ntb_random_seed=3732115123 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2 .chip_sw_pwrmgr_usbdev_smoketest.3732115123 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/2.chip_sw_pwrmgr_usbdev_smoketest/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_pwrmgr_wdog_reset.3410177695 |
| Short name | T1132 |
| Test name | |
| Test status | |
| Simulation time | 4911962776 ps |
| CPU time | 332.9 seconds |
| Started | Aug 24 01:38:01 PM UTC 24 |
| Finished | Aug 24 01:43:39 PM UTC 24 |
| Peak memory | 626792 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_i mages=pwrmgr_wdog_reset_reqs_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3410177695 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 2.chip_sw_pwrmgr_wdog_reset.3410177695 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/2.chip_sw_pwrmgr_wdog_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_rom_ctrl_integrity_check.3524900464 |
| Short name | T1176 |
| Test name | |
| Test status | |
| Simulation time | 9565882496 ps |
| CPU time | 299.97 seconds |
| Started | Aug 24 02:10:53 PM UTC 24 |
| Finished | Aug 24 02:15:57 PM UTC 24 |
| Peak memory | 626736 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=rom_ctrl_integrity_check_ test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=3524900464 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rom_ctrl_integrity_check_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -c m_log /dev/null -cm_name 2.chip_sw_rom_ctrl_integrity_check.3524900464 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/2.chip_sw_rom_ctrl_integrity_check/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_rstmgr_alert_info.2786853160 |
| Short name | T364 |
| Test name | |
| Test status | |
| Simulation time | 13009251548 ps |
| CPU time | 1372.97 seconds |
| Started | Aug 24 01:25:32 PM UTC 24 |
| Finished | Aug 24 01:48:40 PM UTC 24 |
| Peak memory | 626616 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=30_000_000 +en_scb_tl_err_chk=0 +sw_buil d_device=sim_dv +sw_images=rstmgr_alert_info_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2786853160 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=c hip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vc s/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_rstmgr_alert_info.2786853160 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/2.chip_sw_rstmgr_alert_info/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_rstmgr_cpu_info.660530314 |
| Short name | T255 |
| Test name | |
| Test status | |
| Simulation time | 6991755700 ps |
| CPU time | 420.56 seconds |
| Started | Aug 24 01:25:45 PM UTC 24 |
| Finished | Aug 24 01:32:51 PM UTC 24 |
| Peak memory | 626880 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=rstmgr_cpu_info_test:1:ne w_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=660530314 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.chi p_sw_rstmgr_cpu_info.660530314 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/2.chip_sw_rstmgr_cpu_info/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_rstmgr_rst_cnsty_escalation.925401104 |
| Short name | T1073 |
| Test name | |
| Test status | |
| Simulation time | 5600777212 ps |
| CPU time | 487.65 seconds |
| Started | Aug 24 12:50:23 PM UTC 24 |
| Finished | Aug 24 12:58:37 PM UTC 24 |
| Peak memory | 669064 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv + sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=925401104 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rstmgr_ cnsty_fault_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vc s/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_rstmgr_rst_cnsty_escalation.925401104 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/2.chip_sw_rstmgr_rst_cnsty_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_rstmgr_smoketest.3633004386 |
| Short name | T1246 |
| Test name | |
| Test status | |
| Simulation time | 2700590116 ps |
| CPU time | 134.14 seconds |
| Started | Aug 24 03:00:54 PM UTC 24 |
| Finished | Aug 24 03:03:11 PM UTC 24 |
| Peak memory | 624568 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=rstmgr_smoketest:1:new_ru les,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +nt b_random_seed=3633004386 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as sert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_s w_rstmgr_smoketest.3633004386 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/2.chip_sw_rstmgr_smoketest/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_rstmgr_sw_req.1476737013 |
| Short name | T1112 |
| Test name | |
| Test status | |
| Simulation time | 3420105400 ps |
| CPU time | 275.66 seconds |
| Started | Aug 24 01:25:42 PM UTC 24 |
| Finished | Aug 24 01:30:22 PM UTC 24 |
| Peak memory | 626616 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=rstmgr_sw_req_test:1:new_ rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl + ntb_random_seed=1476737013 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip _sw_rstmgr_sw_req.1476737013 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/2.chip_sw_rstmgr_sw_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_rstmgr_sw_rst.2745439475 |
| Short name | T1108 |
| Test name | |
| Test status | |
| Simulation time | 2969922768 ps |
| CPU time | 131.33 seconds |
| Started | Aug 24 01:25:29 PM UTC 24 |
| Finished | Aug 24 01:27:43 PM UTC 24 |
| Peak memory | 625084 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=rstmgr_sw_rst_ctrl_test:1 :new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim. tcl +ntb_random_seed=2745439475 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2 .chip_sw_rstmgr_sw_rst.2745439475 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/2.chip_sw_rstmgr_sw_rst/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_rv_core_ibex_address_translation.3021988852 |
| Short name | T257 |
| Test name | |
| Test status | |
| Simulation time | 2896255930 ps |
| CPU time | 202.85 seconds |
| Started | Aug 24 02:35:56 PM UTC 24 |
| Finished | Aug 24 02:39:21 PM UTC 24 |
| Peak memory | 624552 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=7_000_000 +sw_build_device=sim_dv +sw_im ages=rv_core_ibex_address_translation_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3021988852 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_ base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover age/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_rv_core_ibex_address_translation.3021988852 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/2.chip_sw_rv_core_ibex_address_translation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_rv_core_ibex_icache_invalidate.3627654565 |
| Short name | T297 |
| Test name | |
| Test status | |
| Simulation time | 2221561491 ps |
| CPU time | 144.39 seconds |
| Started | Aug 24 02:36:07 PM UTC 24 |
| Finished | Aug 24 02:38:34 PM UTC 24 |
| Peak memory | 626764 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=rv_core_ibex_icache_inval idate_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/d v/tools/sim.tcl +ntb_random_seed=3627654565 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rv_core_ibex_icache_invalidate_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/de fault.vdb -cm_log /dev/null -cm_name 2.chip_sw_rv_core_ibex_icache_invalidate.3627654565 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/2.chip_sw_rv_core_ibex_icache_invalidate/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_rv_core_ibex_lockstep_glitch.1970261168 |
| Short name | T419 |
| Test name | |
| Test status | |
| Simulation time | 2425096700 ps |
| CPU time | 117.32 seconds |
| Started | Aug 24 02:35:55 PM UTC 24 |
| Finished | Aug 24 02:37:55 PM UTC 24 |
| Peak memory | 674844 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/default/simv +disable_assert_final_checks +sw_build_device=sim_dv +sw_ima ges=aes_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/re po/hw/dv/tools/sim.tcl +ntb_random_seed=1970261168 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rv_core_ibex_lockstep_gli tch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/covera ge/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_rv_core_ibex_lockstep_glitch.1970261168 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/2.chip_sw_rv_core_ibex_lockstep_glitch/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_rv_core_ibex_nmi_irq.1443264193 |
| Short name | T658 |
| Test name | |
| Test status | |
| Simulation time | 4602942362 ps |
| CPU time | 573.32 seconds |
| Started | Aug 24 01:43:29 PM UTC 24 |
| Finished | Aug 24 01:53:10 PM UTC 24 |
| Peak memory | 624712 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=10_000_000 +sw_build_device=sim_dv +sw_i mages=rv_core_ibex_nmi_irq_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1443264193 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default .vdb -cm_log /dev/null -cm_name 2.chip_sw_rv_core_ibex_nmi_irq.1443264193 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/2.chip_sw_rv_core_ibex_nmi_irq/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_rv_core_ibex_rnd.1016051151 |
| Short name | T1152 |
| Test name | |
| Test status | |
| Simulation time | 5331389950 ps |
| CPU time | 679.98 seconds |
| Started | Aug 24 01:42:36 PM UTC 24 |
| Finished | Aug 24 01:54:04 PM UTC 24 |
| Peak memory | 624700 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=20_000_000 +rng_srate_value_max=32 +sw_b uild_device=sim_dv +sw_images=rv_core_ibex_rnd_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1016051151 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ =chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_rv_core_ibex_rnd.1016051151 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/2.chip_sw_rv_core_ibex_rnd/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_rv_dm_access_after_escalation_reset.982646603 |
| Short name | T629 |
| Test name | |
| Test status | |
| Simulation time | 5470885563 ps |
| CPU time | 412.05 seconds |
| Started | Aug 24 02:32:57 PM UTC 24 |
| Finished | Aug 24 02:39:54 PM UTC 24 |
| Peak memory | 636916 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/default/simv +use_jtag_dmi=1 +sw_build_device=sim_dv +sw_images=alert_han dler_escalation_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces /repo/hw/dv/tools/sim.tcl +ntb_random_seed=982646603 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rv_dm_access_after_esca lation_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_rv_dm_access_after_escalation_reset.982646603 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/2.chip_sw_rv_dm_access_after_escalation_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_rv_dm_access_after_wakeup.3338828105 |
| Short name | T1210 |
| Test name | |
| Test status | |
| Simulation time | 6663904328 ps |
| CPU time | 296.2 seconds |
| Started | Aug 24 02:32:42 PM UTC 24 |
| Finished | Aug 24 02:37:42 PM UTC 24 |
| Peak memory | 636900 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/default/simv +use_jtag_dmi=1 +sw_build_device=sim_dv +sw_images=rv_dm_acc ess_after_wakeup_rma:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces /repo/hw/dv/tools/sim.tcl +ntb_random_seed=3338828105 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rv_dm_access_after_wak eup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/covera ge/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_rv_dm_access_after_wakeup.3338828105 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/2.chip_sw_rv_dm_access_after_wakeup/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_rv_dm_ndm_reset_req_when_cpu_halted.3483602790 |
| Short name | T361 |
| Test name | |
| Test status | |
| Simulation time | 4880501156 ps |
| CPU time | 378.94 seconds |
| Started | Aug 24 02:32:19 PM UTC 24 |
| Finished | Aug 24 02:38:43 PM UTC 24 |
| Peak memory | 637236 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/default/simv +use_jtag_dmi=1 +sw_build_device=sim_dv +sw_images=rv_dm_ndm _reset_req_when_cpu_halted_rma:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3483602790 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rv_dm_ndm_re set_when_cpu_halted_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asi c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_rv_dm_ndm_reset_req_when_cpu_halted.3483602790 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/2.chip_sw_rv_dm_ndm_reset_req_when_cpu_halted/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_rv_plic_smoketest.754536921 |
| Short name | T1245 |
| Test name | |
| Test status | |
| Simulation time | 2268441600 ps |
| CPU time | 177.54 seconds |
| Started | Aug 24 02:59:50 PM UTC 24 |
| Finished | Aug 24 03:02:50 PM UTC 24 |
| Peak memory | 624568 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=rv_plic_smoketest:1:new_r ules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +n tb_random_seed=754536921 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as sert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_s w_rv_plic_smoketest.754536921 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/2.chip_sw_rv_plic_smoketest/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_rv_timer_irq.1460662188 |
| Short name | T1121 |
| Test name | |
| Test status | |
| Simulation time | 2701132040 ps |
| CPU time | 152.09 seconds |
| Started | Aug 24 01:33:15 PM UTC 24 |
| Finished | Aug 24 01:35:50 PM UTC 24 |
| Peak memory | 624800 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=rv_timer_smoketest:1:new_ rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl + ntb_random_seed=1460662188 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip _sw_rv_timer_irq.1460662188 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/2.chip_sw_rv_timer_irq/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_rv_timer_smoketest.1771758136 |
| Short name | T1244 |
| Test name | |
| Test status | |
| Simulation time | 2378731360 ps |
| CPU time | 158.92 seconds |
| Started | Aug 24 03:00:05 PM UTC 24 |
| Finished | Aug 24 03:02:47 PM UTC 24 |
| Peak memory | 624564 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=rv_timer_smoketest:1:new_ rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl + ntb_random_seed=1771758136 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip _sw_rv_timer_smoketest.1771758136 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/2.chip_sw_rv_timer_smoketest/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_rv_timer_systick_test.4209553391 |
| Short name | T1277 |
| Test name | |
| Test status | |
| Simulation time | 38363573388 ps |
| CPU time | 6804.25 seconds |
| Started | Aug 24 01:33:38 PM UTC 24 |
| Finished | Aug 24 03:28:13 PM UTC 24 |
| Peak memory | 629908 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=50_000_000 +sw_build_device=sim_dv +sw_i mages=rv_timer_systick_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor kspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4209553391 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_rv_timer_systick_test.4209553391 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/2.chip_sw_rv_timer_systick_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_sensor_ctrl_status.1717240998 |
| Short name | T375 |
| Test name | |
| Test status | |
| Simulation time | 2732770643 ps |
| CPU time | 218.75 seconds |
| Started | Aug 24 02:15:32 PM UTC 24 |
| Finished | Aug 24 02:19:14 PM UTC 24 |
| Peak memory | 625012 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=40_000_000 +sw_build_device=sim_dv +sw_i mages=sensor_ctrl_status_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1717240998 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sensor_ctrl_s tatus_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_sensor_ctrl_status.1717240998 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/2.chip_sw_sensor_ctrl_status/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_sleep_pin_retention.531387889 |
| Short name | T72 |
| Test name | |
| Test status | |
| Simulation time | 3902168648 ps |
| CPU time | 222.69 seconds |
| Started | Aug 24 12:50:55 PM UTC 24 |
| Finished | Aug 24 12:54:41 PM UTC 24 |
| Peak memory | 626928 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=sleep_pin_retention_test: 1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim .tcl +ntb_random_seed=531387889 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sleep_pin_retention_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/ null -cm_name 2.chip_sw_sleep_pin_retention.531387889 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/2.chip_sw_sleep_pin_retention/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_sleep_pwm_pulses.2940842626 |
| Short name | T1079 |
| Test name | |
| Test status | |
| Simulation time | 9227347056 ps |
| CPU time | 875.42 seconds |
| Started | Aug 24 12:51:38 PM UTC 24 |
| Finished | Aug 24 01:06:23 PM UTC 24 |
| Peak memory | 624888 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=sleep_pwm_pulses_test:1:n ew_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc l +ntb_random_seed=2940842626 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_pwm_pulses_vseq +en_cov=1 -cm line+cond+fsm+tg l+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_na me 2.chip_sw_sleep_pwm_pulses.2940842626 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/2.chip_sw_sleep_pwm_pulses/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_sleep_sram_ret_contents_no_scramble.276539265 |
| Short name | T1181 |
| Test name | |
| Test status | |
| Simulation time | 7235013800 ps |
| CPU time | 407.32 seconds |
| Started | Aug 24 02:13:31 PM UTC 24 |
| Finished | Aug 24 02:20:24 PM UTC 24 |
| Peak memory | 626672 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=20_000_000 +en_scb_tl_err_chk=0 +bypass_ alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=sram_ctrl_sleep_sram_ret_contents_no_scramble_test:1:new_rules,test_rom:0 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=276539265 - assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r epo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_sleep_sram_ret_contents_ no_scramble.276539265 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/2.chip_sw_sleep_sram_ret_contents_no_scramble/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_sleep_sram_ret_contents_scramble.2150124479 |
| Short name | T1185 |
| Test name | |
| Test status | |
| Simulation time | 7669930604 ps |
| CPU time | 544.67 seconds |
| Started | Aug 24 02:14:13 PM UTC 24 |
| Finished | Aug 24 02:23:24 PM UTC 24 |
| Peak memory | 626944 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=20_000_000 +en_scb_tl_err_chk=0 +bypass_ alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=sram_ctrl_sleep_sram_ret_contents_scramble_test:1:new_rules,test_rom:0 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2150124479 -as sert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/rep o/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_sleep_sram_ret_contents_sc ramble.2150124479 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/2.chip_sw_sleep_sram_ret_contents_scramble/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_spi_device_pass_through.2839833608 |
| Short name | T241 |
| Test name | |
| Test status | |
| Simulation time | 6200687107 ps |
| CPU time | 495.34 seconds |
| Started | Aug 24 01:09:29 PM UTC 24 |
| Finished | Aug 24 01:17:51 PM UTC 24 |
| Peak memory | 641160 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=spi_passthrough_test:1:ne w_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2839833608 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_spi_passthrough_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -c m_name 2.chip_sw_spi_device_pass_through.2839833608 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/2.chip_sw_spi_device_pass_through/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_spi_device_pass_through_collision.4095534847 |
| Short name | T240 |
| Test name | |
| Test status | |
| Simulation time | 4643428665 ps |
| CPU time | 383.17 seconds |
| Started | Aug 24 01:09:58 PM UTC 24 |
| Finished | Aug 24 01:16:27 PM UTC 24 |
| Peak memory | 641416 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=spi_passthrough_test:1:ne w_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4095534847 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_spi_passthrough_collision_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /d ev/null -cm_name 2.chip_sw_spi_device_pass_through_collision.4095534847 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/2.chip_sw_spi_device_pass_through_collision/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_spi_device_pinmux_sleep_retention.1488698194 |
| Short name | T67 |
| Test name | |
| Test status | |
| Simulation time | 3735631821 ps |
| CPU time | 235.12 seconds |
| Started | Aug 24 01:08:10 PM UTC 24 |
| Finished | Aug 24 01:12:09 PM UTC 24 |
| Peak memory | 637108 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=spi_device_sleep_test:1:n ew_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc l +ntb_random_seed=1488698194 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_spi_device_pinmux_sleep_retention_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default.vdb - cm_log /dev/null -cm_name 2.chip_sw_spi_device_pinmux_sleep_retention.1488698194 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/2.chip_sw_spi_device_pinmux_sleep_retention/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_spi_device_tpm.2480927124 |
| Short name | T56 |
| Test name | |
| Test status | |
| Simulation time | 3551181883 ps |
| CPU time | 223.22 seconds |
| Started | Aug 24 01:05:18 PM UTC 24 |
| Finished | Aug 24 01:09:05 PM UTC 24 |
| Peak memory | 637056 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=spi_device_tpm_tx_rx_test :1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/si m.tcl +ntb_random_seed=2480927124 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_spi_device_tpm_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/nul l -cm_name 2.chip_sw_spi_device_tpm.2480927124 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/2.chip_sw_spi_device_tpm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_spi_host_tx_rx.3813467319 |
| Short name | T52 |
| Test name | |
| Test status | |
| Simulation time | 3230464200 ps |
| CPU time | 204.64 seconds |
| Started | Aug 24 01:06:48 PM UTC 24 |
| Finished | Aug 24 01:10:16 PM UTC 24 |
| Peak memory | 624696 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=spi_host_tx_rx_test:1:new _rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3813467319 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_spi_host_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_ name 2.chip_sw_spi_host_tx_rx.3813467319 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/2.chip_sw_spi_host_tx_rx/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_sram_ctrl_execution_main.3229214253 |
| Short name | T306 |
| Test name | |
| Test status | |
| Simulation time | 9481510939 ps |
| CPU time | 703.24 seconds |
| Started | Aug 24 02:12:39 PM UTC 24 |
| Finished | Aug 24 02:24:31 PM UTC 24 |
| Peak memory | 627072 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=sram_ctrl_execution_main_ test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=3229214253 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sram_ctrl_execution_main_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -c m_log /dev/null -cm_name 2.chip_sw_sram_ctrl_execution_main.3229214253 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/2.chip_sw_sram_ctrl_execution_main/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_sram_ctrl_scrambled_access.3437195349 |
| Short name | T1177 |
| Test name | |
| Test status | |
| Simulation time | 4289392630 ps |
| CPU time | 362.88 seconds |
| Started | Aug 24 02:10:53 PM UTC 24 |
| Finished | Aug 24 02:17:01 PM UTC 24 |
| Peak memory | 626880 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=12_000_000 +en_scb_tl_err_chk=0 +bypass_ alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=sram_ctrl_scrambled_access_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled= 1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3437195349 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sram_ctrl_scrambled_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac es/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_sram_ctrl_scrambled_ access.3437195349 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/2.chip_sw_sram_ctrl_scrambled_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_sram_ctrl_scrambled_access_jitter_en.151288880 |
| Short name | T1182 |
| Test name | |
| Test status | |
| Simulation time | 5331767688 ps |
| CPU time | 509.94 seconds |
| Started | Aug 24 02:12:13 PM UTC 24 |
| Finished | Aug 24 02:20:50 PM UTC 24 |
| Peak memory | 627200 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=12_000_000 +bypass_alert_ready_to_end_ch eck=1 +en_jitter=1 +en_scb_tl_err_chk=0 +sw_build_device=sim_dv +sw_images=sram_ctrl_scrambled_access_test:1:new_rules,test_rom:0 +cdc_instrumenta tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=151288880 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sram_ctrl_scrambled_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_sram_ctr l_scrambled_access_jitter_en.151288880 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/2.chip_sw_sram_ctrl_scrambled_access_jitter_en/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq.2770833094 |
| Short name | T1224 |
| Test name | |
| Test status | |
| Simulation time | 5557977120 ps |
| CPU time | 380.75 seconds |
| Started | Aug 24 02:38:57 PM UTC 24 |
| Finished | Aug 24 02:45:23 PM UTC 24 |
| Peak memory | 627136 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/default/simv +mem_sel=main +sw_test_timeout_ns=12_000_000 +bypass_alert_r eady_to_end_check=1 +en_jitter=1 +en_scb_tl_err_chk=0 +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +sw_images=sram_ctrl_scrambled_access_test:1:ne w_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2770833094 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sram_ctrl_scrambled_access_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 2.chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq.2770833094 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/2.chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_sram_ctrl_smoketest.1593408881 |
| Short name | T1248 |
| Test name | |
| Test status | |
| Simulation time | 3205646808 ps |
| CPU time | 175.8 seconds |
| Started | Aug 24 03:01:26 PM UTC 24 |
| Finished | Aug 24 03:04:25 PM UTC 24 |
| Peak memory | 624824 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=sram_ctrl_smoketest:1:new _rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1593408881 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.chi p_sw_sram_ctrl_smoketest.1593408881 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/2.chip_sw_sram_ctrl_smoketest/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_sysrst_ctrl_ec_rst_l.2000505467 |
| Short name | T1180 |
| Test name | |
| Test status | |
| Simulation time | 21142204212 ps |
| CPU time | 2566.47 seconds |
| Started | Aug 24 01:35:43 PM UTC 24 |
| Finished | Aug 24 02:18:57 PM UTC 24 |
| Peak memory | 629984 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=sysrst_ctrl_ec_rst_l_test :1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/si m.tcl +ntb_random_seed=2000505467 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sysrst_ctrl_ec_rst_l_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /d ev/null -cm_name 2.chip_sw_sysrst_ctrl_ec_rst_l.2000505467 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/2.chip_sw_sysrst_ctrl_ec_rst_l/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_sysrst_ctrl_in_irq.2185459361 |
| Short name | T1127 |
| Test name | |
| Test status | |
| Simulation time | 4270250991 ps |
| CPU time | 416.31 seconds |
| Started | Aug 24 01:34:28 PM UTC 24 |
| Finished | Aug 24 01:41:31 PM UTC 24 |
| Peak memory | 629228 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=sysrst_ctrl_in_irq_test:1 :new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim. tcl +ntb_random_seed=2185459361 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sysrst_ctrl_in_irq_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/n ull -cm_name 2.chip_sw_sysrst_ctrl_in_irq.2185459361 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/2.chip_sw_sysrst_ctrl_in_irq/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_sysrst_ctrl_inputs.3120072266 |
| Short name | T1124 |
| Test name | |
| Test status | |
| Simulation time | 2868576682 ps |
| CPU time | 209.34 seconds |
| Started | Aug 24 01:34:05 PM UTC 24 |
| Finished | Aug 24 01:37:38 PM UTC 24 |
| Peak memory | 628976 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=sysrst_ctrl_inputs_test:1 :new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim. tcl +ntb_random_seed=3120072266 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sysrst_ctrl_inputs_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/n ull -cm_name 2.chip_sw_sysrst_ctrl_inputs.3120072266 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/2.chip_sw_sysrst_ctrl_inputs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_sysrst_ctrl_outputs.3731335771 |
| Short name | T1126 |
| Test name | |
| Test status | |
| Simulation time | 3635523598 ps |
| CPU time | 244.27 seconds |
| Started | Aug 24 01:35:40 PM UTC 24 |
| Finished | Aug 24 01:39:48 PM UTC 24 |
| Peak memory | 624812 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=sysrst_ctrl_outputs_test: 1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim .tcl +ntb_random_seed=3731335771 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sysrst_ctrl_outputs_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev /null -cm_name 2.chip_sw_sysrst_ctrl_outputs.3731335771 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/2.chip_sw_sysrst_ctrl_outputs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_sysrst_ctrl_reset.1453395622 |
| Short name | T1150 |
| Test name | |
| Test status | |
| Simulation time | 22111595864 ps |
| CPU time | 1063.18 seconds |
| Started | Aug 24 01:35:40 PM UTC 24 |
| Finished | Aug 24 01:53:36 PM UTC 24 |
| Peak memory | 629492 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=36_000_000 +sw_build_device=sim_dv +sw_i mages=sysrst_ctrl_reset_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo rkspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1453395622 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sysrst_ctrl_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/covera ge/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_sysrst_ctrl_reset.1453395622 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/2.chip_sw_sysrst_ctrl_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_sysrst_ctrl_ulp_z3_wakeup.2497647027 |
| Short name | T54 |
| Test name | |
| Test status | |
| Simulation time | 5504636172 ps |
| CPU time | 344.23 seconds |
| Started | Aug 24 01:35:43 PM UTC 24 |
| Finished | Aug 24 01:41:32 PM UTC 24 |
| Peak memory | 626756 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=sysrst_ctrl_ulp_z3_wakeup _test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/too ls/sim.tcl +ntb_random_seed=2497647027 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sysrst_ctrl_ulp_z3_wakeup_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_sysrst_ctrl_ulp_z3_wakeup.2497647027 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/2.chip_sw_sysrst_ctrl_ulp_z3_wakeup/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_uart_rand_baudrate.743823965 |
| Short name | T1078 |
| Test name | |
| Test status | |
| Simulation time | 4199261620 ps |
| CPU time | 347.12 seconds |
| Started | Aug 24 12:59:02 PM UTC 24 |
| Finished | Aug 24 01:04:54 PM UTC 24 |
| Peak memory | 637128 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=80_000_000 +calibrate_usb_clk=1 +sw_buil d_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=743823965 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_u art_rand_baudrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_uart_rand_baudrate.743823965 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/2.chip_sw_uart_rand_baudrate/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_uart_smoketest.3448366738 |
| Short name | T1251 |
| Test name | |
| Test status | |
| Simulation time | 2875718040 ps |
| CPU time | 224.13 seconds |
| Started | Aug 24 03:01:42 PM UTC 24 |
| Finished | Aug 24 03:05:30 PM UTC 24 |
| Peak memory | 624564 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=uart_smoketest:1:new_rule s,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ random_seed=3448366738 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.ch ip_sw_uart_smoketest.3448366738 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/2.chip_sw_uart_smoketest/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_uart_tx_rx.579530719 |
| Short name | T1074 |
| Test name | |
| Test status | |
| Simulation time | 4221346920 ps |
| CPU time | 433.01 seconds |
| Started | Aug 24 12:52:11 PM UTC 24 |
| Finished | Aug 24 12:59:30 PM UTC 24 |
| Peak memory | 638908 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/default/simv +uart_idx=0 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw _images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=579530719 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_tx_rx_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default.vd b -cm_log /dev/null -cm_name 2.chip_sw_uart_tx_rx.579530719 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/2.chip_sw_uart_tx_rx/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_uart_tx_rx_alt_clk_freq.274121299 |
| Short name | T134 |
| Test name | |
| Test status | |
| Simulation time | 9137088427 ps |
| CPU time | 1220.05 seconds |
| Started | Aug 24 01:00:03 PM UTC 24 |
| Finished | Aug 24 01:20:40 PM UTC 24 |
| Peak memory | 636872 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=80_000_000 +chip_clock_source=ChipClockS ourceExternal96Mhz +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=274121299 -assert nopostproc +UVM _TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_baudrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra tch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_uart_tx_rx_alt_clk_freq.274121299 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/2.chip_sw_uart_tx_rx_alt_clk_freq/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_uart_tx_rx_alt_clk_freq_low_speed.2433426620 |
| Short name | T1082 |
| Test name | |
| Test status | |
| Simulation time | 7763690789 ps |
| CPU time | 722.81 seconds |
| Started | Aug 24 01:00:03 PM UTC 24 |
| Finished | Aug 24 01:12:18 PM UTC 24 |
| Peak memory | 634824 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=80_000_000 +calibrate_usb_clk=1 +chip_cl ock_source=ChipClockSourceExternal48Mhz +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2433426620 -assert nopostproc +UV M_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_baudrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr atch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_uart_tx_rx_alt_clk_freq_low_speed.2433426620 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/2.chip_sw_uart_tx_rx_alt_clk_freq_low_speed/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_uart_tx_rx_bootstrap.3181222662 |
| Short name | T1340 |
| Test name | |
| Test status | |
| Simulation time | 80556567990 ps |
| CPU time | 13736.8 seconds |
| Started | Aug 24 12:55:14 PM UTC 24 |
| Finished | Aug 24 04:46:34 PM UTC 24 |
| Peak memory | 658728 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/default/simv +use_spi_load_bootstrap=1 +calibrate_usb_clk=1 +test_timeout _ns=160_000_000 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3181222662 -assert nopostproc +UVM_TESTNAME=chip_base_tes t +UVM_TEST_SEQ=chip_sw_uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/ch ip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_uart_tx_rx_bootstrap.3181222662 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/2.chip_sw_uart_tx_rx_bootstrap/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_uart_tx_rx_idx1.1752989171 |
| Short name | T133 |
| Test name | |
| Test status | |
| Simulation time | 3966644792 ps |
| CPU time | 446.28 seconds |
| Started | Aug 24 12:53:03 PM UTC 24 |
| Finished | Aug 24 01:00:35 PM UTC 24 |
| Peak memory | 639132 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/default/simv +uart_idx=1 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw _images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1752989171 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_tx_rx_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 2.chip_sw_uart_tx_rx_idx1.1752989171 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/2.chip_sw_uart_tx_rx_idx1/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_uart_tx_rx_idx2.1571541469 |
| Short name | T1075 |
| Test name | |
| Test status | |
| Simulation time | 4846803282 ps |
| CPU time | 442.79 seconds |
| Started | Aug 24 12:54:31 PM UTC 24 |
| Finished | Aug 24 01:01:59 PM UTC 24 |
| Peak memory | 638912 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/default/simv +uart_idx=2 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw _images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1571541469 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_tx_rx_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 2.chip_sw_uart_tx_rx_idx2.1571541469 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/2.chip_sw_uart_tx_rx_idx2/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_uart_tx_rx_idx3.83821527 |
| Short name | T1076 |
| Test name | |
| Test status | |
| Simulation time | 4636997358 ps |
| CPU time | 445.71 seconds |
| Started | Aug 24 12:55:14 PM UTC 24 |
| Finished | Aug 24 01:02:46 PM UTC 24 |
| Peak memory | 639088 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/default/simv +uart_idx=3 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw _images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=83821527 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_tx_rx_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_uart_tx_rx_idx3.83821527 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/2.chip_sw_uart_tx_rx_idx3/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_tap_straps_dev.2020654856 |
| Short name | T1206 |
| Test name | |
| Test status | |
| Simulation time | 2854096796 ps |
| CPU time | 131.74 seconds |
| Started | Aug 24 02:33:38 PM UTC 24 |
| Finished | Aug 24 02:35:52 PM UTC 24 |
| Peak memory | 641208 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/default/simv +use_otp_image=OtpTypeLcStDev +create_jtag_riscv_map=1 +sw_b uild_device=sim_dv +sw_images=example_test_from_rom:0:test_in_rom:new_rules +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2020654856 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SE Q=chip_tap_straps_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_tap_straps_dev.2020654856 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/2.chip_tap_straps_dev/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_tap_straps_prod.2698376277 |
| Short name | T1207 |
| Test name | |
| Test status | |
| Simulation time | 2597103661 ps |
| CPU time | 114.42 seconds |
| Started | Aug 24 02:34:58 PM UTC 24 |
| Finished | Aug 24 02:36:54 PM UTC 24 |
| Peak memory | 640628 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/default/simv +use_otp_image=OtpTypeLcStProd +create_jtag_riscv_map=1 +sw_ build_device=sim_dv +sw_images=example_test_from_rom:0:test_in_rom:new_rules +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2698376277 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_S EQ=chip_tap_straps_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_tap_straps_prod.2698376277 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/2.chip_tap_straps_prod/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_tap_straps_testunlock0.3892192789 |
| Short name | T1220 |
| Test name | |
| Test status | |
| Simulation time | 7608319767 ps |
| CPU time | 478.44 seconds |
| Started | Aug 24 02:34:20 PM UTC 24 |
| Finished | Aug 24 02:42:24 PM UTC 24 |
| Peak memory | 651964 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/default/simv +use_otp_image=OtpTypeLcStTestUnlocked0 +create_jtag_riscv_m ap=1 +sw_build_device=sim_dv +sw_images=example_test_from_rom:0:test_in_rom:new_rules +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3892192789 -assert nopostproc +UVM_TESTNAME=chip_base_test +U VM_TEST_SEQ=chip_tap_straps_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/chip_earl grey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_tap_straps_testunlock0.3892192789 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/2.chip_tap_straps_testunlock0/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/2.rom_e2e_asm_init_dev.2756302732 |
| Short name | T1286 |
| Test name | |
| Test status | |
| Simulation time | 15165030563 ps |
| CPU time | 3075.56 seconds |
| Started | Aug 24 02:43:05 PM UTC 24 |
| Finished | Aug 24 03:34:53 PM UTC 24 |
| Peak memory | 627812 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/default/simv +use_otp_image=OtpTypeCustom +sw_test_timeout_ns=20000000 +s w_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_prod_key_0:1:ot_flash_binary,otp_img_e2e_bootstrap_entry_dev:4,mask_rom:0 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2756302732 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rom_e2e_asm_init_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_e2e_asm_init_dev.2756302732 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/2.rom_e2e_asm_init_dev/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/2.rom_e2e_asm_init_prod.2152567682 |
| Short name | T1289 |
| Test name | |
| Test status | |
| Simulation time | 15466173692 ps |
| CPU time | 3125.83 seconds |
| Started | Aug 24 02:43:05 PM UTC 24 |
| Finished | Aug 24 03:35:44 PM UTC 24 |
| Peak memory | 628044 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/default/simv +use_otp_image=OtpTypeCustom +sw_test_timeout_ns=20000000 +s w_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_prod_key_0:1:ot_flash_binary,otp_img_e2e_bootstrap_entry_prod:4,mask_rom:0 +cdc_inst rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2152567682 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rom_e2e_asm_init_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_e2e_asm_init_prod.2152567682 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/2.rom_e2e_asm_init_prod/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/2.rom_e2e_asm_init_prod_end.3523039764 |
| Short name | T1292 |
| Test name | |
| Test status | |
| Simulation time | 15564850577 ps |
| CPU time | 3149.34 seconds |
| Started | Aug 24 02:44:26 PM UTC 24 |
| Finished | Aug 24 03:37:30 PM UTC 24 |
| Peak memory | 627800 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/default/simv +use_otp_image=OtpTypeCustom +sw_test_timeout_ns=20000000 +s w_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_prod_key_0:1:ot_flash_binary,otp_img_e2e_bootstrap_entry_prod_end:4,mask_rom:0 +cdc_ instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=352303 9764 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rom_e2e_asm_init_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_e2e_asm_in it_prod_end.3523039764 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/2.rom_e2e_asm_init_prod_end/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/2.rom_e2e_asm_init_rma.2381869283 |
| Short name | T1287 |
| Test name | |
| Test status | |
| Simulation time | 14942410100 ps |
| CPU time | 2954.1 seconds |
| Started | Aug 24 02:45:36 PM UTC 24 |
| Finished | Aug 24 03:35:23 PM UTC 24 |
| Peak memory | 628004 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/default/simv +use_otp_image=OtpTypeCustom +sw_test_timeout_ns=20000000 +s w_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_prod_key_0:1:ot_flash_binary,otp_img_e2e_bootstrap_entry_rma:4,mask_rom:0 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2381869283 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rom_e2e_asm_init_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_e2e_asm_init_rma.2381869283 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/2.rom_e2e_asm_init_rma/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/2.rom_e2e_asm_init_test_unlocked0.3874400317 |
| Short name | T1266 |
| Test name | |
| Test status | |
| Simulation time | 11567641821 ps |
| CPU time | 2258.01 seconds |
| Started | Aug 24 02:42:01 PM UTC 24 |
| Finished | Aug 24 03:20:03 PM UTC 24 |
| Peak memory | 629728 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/default/simv +use_otp_image=OtpTypeCustom +sw_test_timeout_ns=410_000_000 +sw_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_prod_key_0:1:ot_flash_binary,otp_img_e2e_bootstrap_entry_test_unlocked0:4,mask_ro m:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_se ed=3874400317 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rom_e2e_asm_init_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a ssert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_e 2e_asm_init_test_unlocked0.3874400317 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/2.rom_e2e_asm_init_test_unlocked0/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/2.rom_e2e_keymgr_init_rom_ext_invalid_meas.2964878149 |
| Short name | T1290 |
| Test name | |
| Test status | |
| Simulation time | 14501558232 ps |
| CPU time | 2955.37 seconds |
| Started | Aug 24 02:46:20 PM UTC 24 |
| Finished | Aug 24 03:36:08 PM UTC 24 |
| Peak memory | 624912 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=40_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=rom_e2e_keymgr_init_otp_invalid_meas:1:new_rules,otp_img_keymgr_otp_invalid_meas:4,mask_rom:0 +cdc_instrumentat ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2964878149 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc ratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_e2e_keymgr_init_rom_ext_invalid_meas.2964878149 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/2.rom_e2e_keymgr_init_rom_ext_invalid_meas/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/2.rom_e2e_keymgr_init_rom_ext_meas.508446968 |
| Short name | T1295 |
| Test name | |
| Test status | |
| Simulation time | 14740288696 ps |
| CPU time | 3078.84 seconds |
| Started | Aug 24 02:46:16 PM UTC 24 |
| Finished | Aug 24 03:38:07 PM UTC 24 |
| Peak memory | 625500 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=40_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=rom_e2e_keymgr_init_otp_meas:1:new_rules,otp_img_keymgr_otp_meas:4,mask_rom:0 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=508446968 -assert nopostproc +UVM_ TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_e2e_keymgr_init_rom_ext_meas.508446968 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/2.rom_e2e_keymgr_init_rom_ext_meas/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/2.rom_e2e_keymgr_init_rom_ext_no_meas.1711246117 |
| Short name | T1285 |
| Test name | |
| Test status | |
| Simulation time | 15667937224 ps |
| CPU time | 2814 seconds |
| Started | Aug 24 02:46:18 PM UTC 24 |
| Finished | Aug 24 03:33:43 PM UTC 24 |
| Peak memory | 624864 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=40_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=rom_e2e_keymgr_init_otp_no_meas:1:new_rules,otp_img_keymgr_otp_no_meas:4,mask_rom:0 +cdc_instrumentation_enable d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1711246117 -assert nopostpro c +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_e2e_keymgr_init_rom_ext_no_meas.1711246117 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/2.rom_e2e_keymgr_init_rom_ext_no_meas/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/2.rom_e2e_self_hash.2833828422 |
| Short name | T1320 |
| Test name | |
| Test status | |
| Simulation time | 26515973240 ps |
| CPU time | 5104.13 seconds |
| Started | Aug 24 02:49:38 PM UTC 24 |
| Finished | Aug 24 04:15:35 PM UTC 24 |
| Peak memory | 627764 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=200_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=rom_e2e_self_hash_test:1:new_rules,otp_img_sigverify_spx_prod:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2833828422 -assert nopostproc +UVM_T ESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_e2e_self_hash.2833828422 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/2.rom_e2e_self_hash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/2.rom_e2e_shutdown_exception_c.3694628802 |
| Short name | T1280 |
| Test name | |
| Test status | |
| Simulation time | 15174871776 ps |
| CPU time | 2835.69 seconds |
| Started | Aug 24 02:41:52 PM UTC 24 |
| Finished | Aug 24 03:29:38 PM UTC 24 |
| Peak memory | 628104 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=40000000 +use_otp_image=OtpTypeCustom +s w_build_device=sim_dv +sw_images=rom_e2e_shutdown_exception_c:1:new_rules,otp_img_secret2_locked_rma:4,mask_rom:0 +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3694628802 -assert nopostproc +UV M_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rom_e2e_shutdown_exception_c_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace s/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_e2e_shutdown_exception_c.3694628802 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/2.rom_e2e_shutdown_exception_c/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/2.rom_e2e_shutdown_output.2144477011 |
| Short name | T1278 |
| Test name | |
| Test status | |
| Simulation time | 27785006355 ps |
| CPU time | 2762 seconds |
| Started | Aug 24 02:42:01 PM UTC 24 |
| Finished | Aug 24 03:28:32 PM UTC 24 |
| Peak memory | 629780 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=20000000 +use_otp_image=OtpTypeCustom +s w_build_device=sim_dv +sw_images=empty_test_slot_a_unsigned:1:ot_flash_binary,otp_img_shutdown_output_test_unlocked0:4,mask_rom:0 +cdc_instrumenta tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2144477011 -asser t nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rom_e2e_shutdown_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_e2e_shutdown_output.2144477011 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/2.rom_e2e_shutdown_output/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/2.rom_e2e_smoke.2952917597 |
| Short name | T1284 |
| Test name | |
| Test status | |
| Simulation time | 14664889940 ps |
| CPU time | 3036.66 seconds |
| Started | Aug 24 02:41:52 PM UTC 24 |
| Finished | Aug 24 03:33:01 PM UTC 24 |
| Peak memory | 627744 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=40000000 +use_otp_image=OtpTypeCustom +s w_build_device=sim_dv +sw_images=rom_e2e_smoke:1:new_rules,otp_img_secret2_locked_rma:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2952917597 -assert nopostproc +UVM_TESTNAME=chip _base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22 /chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_e2e_smoke.2952917597 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/2.rom_e2e_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/2.rom_e2e_static_critical.3373985852 |
| Short name | T1303 |
| Test name | |
| Test status | |
| Simulation time | 17769347960 ps |
| CPU time | 3503.66 seconds |
| Started | Aug 24 02:45:46 PM UTC 24 |
| Finished | Aug 24 03:44:47 PM UTC 24 |
| Peak memory | 629788 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=40000000 +use_otp_image=OtpTypeCustom +s w_build_device=sim_dv +sw_images=rom_e2e_static_critical:1:new_rules,otp_img_secret2_locked_rma:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3373985852 -assert nopostproc +UVM_TES TNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_e2e_static_critical.3373985852 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/2.rom_e2e_static_critical/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/2.rom_keymgr_functest.975440510 |
| Short name | T1237 |
| Test name | |
| Test status | |
| Simulation time | 4551272728 ps |
| CPU time | 424.76 seconds |
| Started | Aug 24 02:50:35 PM UTC 24 |
| Finished | Aug 24 02:57:45 PM UTC 24 |
| Peak memory | 626824 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=10_000_000 +sw_build_device=sim_dv +sw_i mages=keymgr_functest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace s/repo/hw/dv/tools/sim.tcl +ntb_random_seed=975440510 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_lo g /dev/null -cm_name 2.rom_keymgr_functest.975440510 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/2.rom_keymgr_functest/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/2.rom_raw_unlock.2798123881 |
| Short name | T1230 |
| Test name | |
| Test status | |
| Simulation time | 5422733587 ps |
| CPU time | 173.98 seconds |
| Started | Aug 24 02:48:46 PM UTC 24 |
| Finished | Aug 24 02:51:43 PM UTC 24 |
| Peak memory | 638488 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/default/simv +do_creator_sw_cfg_ast_cfg=0 +sw_test_timeout_ns=200_000_000 +use_otp_image=OtpTypeLcStRaw +chip_clock_source=ChipClockSourceExternal48Mhz +rom_prod_mode=1 +use_jtag_dmi=1 +sw_build_device=sim_dv +sw_images =empty_test_slot_a_fake_ecdsa_test_key_0:1:ot_flash_binary,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2798123881 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip _sw_lc_raw_unlock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_raw_unlock.2798123881 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/2.rom_raw_unlock/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/2.rom_volatile_raw_unlock.868265603 |
| Short name | T1228 |
| Test name | |
| Test status | |
| Simulation time | 2580384443 ps |
| CPU time | 90.69 seconds |
| Started | Aug 24 02:48:31 PM UTC 24 |
| Finished | Aug 24 02:50:04 PM UTC 24 |
| Peak memory | 634804 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=200_000_000 +use_otp_image=OtpTypeLcStRa w +chip_clock_source=ChipClockSourceExternal48Mhz +rom_prod_mode=1 +sw_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_test_key_0:1:ot _flash_binary,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/s im.tcl +ntb_random_seed=868265603 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_volatile_raw_unlock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_volatile_raw_unlock.868265603 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/2.rom_volatile_raw_unlock/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/20.chip_sw_alert_handler_lpg_sleep_mode_alerts.592397183 |
| Short name | T767 |
| Test name | |
| Test status | |
| Simulation time | 3680398854 ps |
| CPU time | 280.06 seconds |
| Started | Aug 24 03:54:34 PM UTC 24 |
| Finished | Aug 24 03:59:19 PM UTC 24 |
| Peak memory | 673216 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_rea dy_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv _core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_handler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=592397183 -assert nopost proc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac es/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.chip_sw_alert_handler_lpg_s leep_mode_alerts.592397183 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/20.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/20.chip_sw_all_escalation_resets.1027707118 |
| Short name | T690 |
| Test name | |
| Test status | |
| Simulation time | 4477680848 ps |
| CPU time | 402.52 seconds |
| Started | Aug 24 03:53:55 PM UTC 24 |
| Finished | Aug 24 04:00:43 PM UTC 24 |
| Peak memory | 675208 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv + sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1027707118 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_es calation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.chip_sw_all_escalation_resets.1027707118 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/20.chip_sw_all_escalation_resets/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/21.chip_sw_all_escalation_resets.1032472092 |
| Short name | T1315 |
| Test name | |
| Test status | |
| Simulation time | 5171511200 ps |
| CPU time | 458.28 seconds |
| Started | Aug 24 03:55:32 PM UTC 24 |
| Finished | Aug 24 04:03:16 PM UTC 24 |
| Peak memory | 637128 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv + sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1032472092 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_es calation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.chip_sw_all_escalation_resets.1032472092 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/21.chip_sw_all_escalation_resets/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/22.chip_sw_alert_handler_lpg_sleep_mode_alerts.3818279748 |
| Short name | T712 |
| Test name | |
| Test status | |
| Simulation time | 3749674794 ps |
| CPU time | 258.15 seconds |
| Started | Aug 24 03:56:26 PM UTC 24 |
| Finished | Aug 24 04:00:47 PM UTC 24 |
| Peak memory | 673276 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_rea dy_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv _core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_handler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3818279748 -assert nopos tproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.chip_sw_alert_handler_lpg_ sleep_mode_alerts.3818279748 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/22.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/23.chip_sw_alert_handler_lpg_sleep_mode_alerts.402021901 |
| Short name | T702 |
| Test name | |
| Test status | |
| Simulation time | 3489464256 ps |
| CPU time | 255.04 seconds |
| Started | Aug 24 03:57:50 PM UTC 24 |
| Finished | Aug 24 04:02:08 PM UTC 24 |
| Peak memory | 673276 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_rea dy_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv _core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_handler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=402021901 -assert nopost proc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac es/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.chip_sw_alert_handler_lpg_s leep_mode_alerts.402021901 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/23.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/25.chip_sw_alert_handler_lpg_sleep_mode_alerts.3908453056 |
| Short name | T691 |
| Test name | |
| Test status | |
| Simulation time | 3507780548 ps |
| CPU time | 263.6 seconds |
| Started | Aug 24 03:59:13 PM UTC 24 |
| Finished | Aug 24 04:03:41 PM UTC 24 |
| Peak memory | 673524 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_rea dy_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv _core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_handler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3908453056 -assert nopos tproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.chip_sw_alert_handler_lpg_ sleep_mode_alerts.3908453056 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/25.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/25.chip_sw_all_escalation_resets.2805677465 |
| Short name | T1318 |
| Test name | |
| Test status | |
| Simulation time | 5396658044 ps |
| CPU time | 409.12 seconds |
| Started | Aug 24 03:59:11 PM UTC 24 |
| Finished | Aug 24 04:06:05 PM UTC 24 |
| Peak memory | 637364 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv + sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2805677465 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_es calation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.chip_sw_all_escalation_resets.2805677465 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/25.chip_sw_all_escalation_resets/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/26.chip_sw_all_escalation_resets.3141582058 |
| Short name | T1317 |
| Test name | |
| Test status | |
| Simulation time | 4803608360 ps |
| CPU time | 397.22 seconds |
| Started | Aug 24 03:59:12 PM UTC 24 |
| Finished | Aug 24 04:05:55 PM UTC 24 |
| Peak memory | 675460 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv + sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3141582058 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_es calation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.chip_sw_all_escalation_resets.3141582058 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/26.chip_sw_all_escalation_resets/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/28.chip_sw_alert_handler_lpg_sleep_mode_alerts.2585467461 |
| Short name | T110 |
| Test name | |
| Test status | |
| Simulation time | 3769234856 ps |
| CPU time | 302.26 seconds |
| Started | Aug 24 04:01:15 PM UTC 24 |
| Finished | Aug 24 04:06:22 PM UTC 24 |
| Peak memory | 673676 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_rea dy_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv _core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_handler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2585467461 -assert nopos tproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.chip_sw_alert_handler_lpg_ sleep_mode_alerts.2585467461 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/28.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/3.chip_sw_alert_handler_lpg_sleep_mode_alerts.1109657275 |
| Short name | T704 |
| Test name | |
| Test status | |
| Simulation time | 4179843842 ps |
| CPU time | 308.68 seconds |
| Started | Aug 24 03:10:54 PM UTC 24 |
| Finished | Aug 24 03:16:07 PM UTC 24 |
| Peak memory | 673216 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_rea dy_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv _core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_handler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1109657275 -assert nopos tproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.chip_sw_alert_handler_lpg_s leep_mode_alerts.1109657275 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/3.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/3.chip_sw_all_escalation_resets.3553986886 |
| Short name | T1252 |
| Test name | |
| Test status | |
| Simulation time | 4937111336 ps |
| CPU time | 414.88 seconds |
| Started | Aug 24 03:03:21 PM UTC 24 |
| Finished | Aug 24 03:10:21 PM UTC 24 |
| Peak memory | 637192 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv + sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3553986886 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_es calation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.chip_sw_all_escalation_resets.3553986886 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/3.chip_sw_all_escalation_resets/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/3.chip_sw_aon_timer_sleep_wdog_sleep_pause.3105449655 |
| Short name | T1261 |
| Test name | |
| Test status | |
| Simulation time | 7848600468 ps |
| CPU time | 302.24 seconds |
| Started | Aug 24 03:10:54 PM UTC 24 |
| Finished | Aug 24 03:16:00 PM UTC 24 |
| Peak memory | 624632 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_i mages=aon_timer_sleep_wdog_sleep_pause_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu e -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3105449655 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw _base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cove rage/default.vdb -cm_log /dev/null -cm_name 3.chip_sw_aon_timer_sleep_wdog_sleep_pause.3105449655 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/3.chip_sw_aon_timer_sleep_wdog_sleep_pause/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/3.chip_sw_csrng_edn_concurrency.507371468 |
| Short name | T1339 |
| Test name | |
| Test status | |
| Simulation time | 27320957108 ps |
| CPU time | 5397.09 seconds |
| Started | Aug 24 03:11:55 PM UTC 24 |
| Finished | Aug 24 04:42:49 PM UTC 24 |
| Peak memory | 630116 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=140_000_000 +rng_srate_value_min=15 +rng _srate_value_max=20 +accelerate_cold_power_up_time=3 +accelerate_regulators_power_up_time=2 +sw_build_device=sim_dv +sw_images=csrng_edn_concurren cy_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/t ools/sim.tcl +ntb_random_seed=507371468 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -c m_name 3.chip_sw_csrng_edn_concurrency.507371468 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/3.chip_sw_csrng_edn_concurrency/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/3.chip_sw_data_integrity_escalation.689356265 |
| Short name | T1258 |
| Test name | |
| Test status | |
| Simulation time | 6319277790 ps |
| CPU time | 522.29 seconds |
| Started | Aug 24 03:03:22 PM UTC 24 |
| Finished | Aug 24 03:12:11 PM UTC 24 |
| Peak memory | 626688 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv + sw_images=data_integrity_escalation_reset_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=689356265 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_ sw_data_integrity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.chip_sw_data_integrity_escalation.689356265 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/3.chip_sw_data_integrity_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/3.chip_sw_lc_ctrl_transition.57158416 |
| Short name | T1264 |
| Test name | |
| Test status | |
| Simulation time | 10075420767 ps |
| CPU time | 545.6 seconds |
| Started | Aug 24 03:09:28 PM UTC 24 |
| Finished | Aug 24 03:18:41 PM UTC 24 |
| Peak memory | 639060 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=lc_ctrl_transition_test:1 :new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim. tcl +ntb_random_seed=57158416 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_ctrl_transition_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/nul l -cm_name 3.chip_sw_lc_ctrl_transition.57158416 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/3.chip_sw_lc_ctrl_transition/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/3.chip_sw_sensor_ctrl_alert.3894875149 |
| Short name | T169 |
| Test name | |
| Test status | |
| Simulation time | 6686157714 ps |
| CPU time | 449.18 seconds |
| Started | Aug 24 03:11:54 PM UTC 24 |
| Finished | Aug 24 03:19:29 PM UTC 24 |
| Peak memory | 626764 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=40_000_000 +sw_build_device=sim_dv +sw_i mages=sensor_ctrl_alert_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo rkspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3894875149 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default.vd b -cm_log /dev/null -cm_name 3.chip_sw_sensor_ctrl_alert.3894875149 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/3.chip_sw_sensor_ctrl_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/3.chip_sw_uart_rand_baudrate.2243116572 |
| Short name | T1254 |
| Test name | |
| Test status | |
| Simulation time | 3070218160 ps |
| CPU time | 332.18 seconds |
| Started | Aug 24 03:05:37 PM UTC 24 |
| Finished | Aug 24 03:11:14 PM UTC 24 |
| Peak memory | 637128 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=80_000_000 +calibrate_usb_clk=1 +sw_buil d_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2243116572 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_ uart_rand_baudrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.chip_sw_uart_rand_baudrate.2243116572 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/3.chip_sw_uart_rand_baudrate/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/3.chip_sw_uart_tx_rx.2188841526 |
| Short name | T1253 |
| Test name | |
| Test status | |
| Simulation time | 4860027956 ps |
| CPU time | 405.09 seconds |
| Started | Aug 24 03:03:35 PM UTC 24 |
| Finished | Aug 24 03:10:26 PM UTC 24 |
| Peak memory | 638908 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/default/simv +uart_idx=0 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw _images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2188841526 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_tx_rx_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 3.chip_sw_uart_tx_rx.2188841526 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/3.chip_sw_uart_tx_rx/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/3.chip_sw_uart_tx_rx_alt_clk_freq.2813866838 |
| Short name | T1275 |
| Test name | |
| Test status | |
| Simulation time | 8453642397 ps |
| CPU time | 1249.98 seconds |
| Started | Aug 24 03:05:54 PM UTC 24 |
| Finished | Aug 24 03:26:58 PM UTC 24 |
| Peak memory | 636860 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=80_000_000 +chip_clock_source=ChipClockS ourceExternal96Mhz +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2813866838 -assert nopostproc +UV M_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_baudrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr atch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.chip_sw_uart_tx_rx_alt_clk_freq.2813866838 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/3.chip_sw_uart_tx_rx_alt_clk_freq/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/3.chip_sw_uart_tx_rx_alt_clk_freq_low_speed.3503929916 |
| Short name | T1263 |
| Test name | |
| Test status | |
| Simulation time | 7986519983 ps |
| CPU time | 662.65 seconds |
| Started | Aug 24 03:06:35 PM UTC 24 |
| Finished | Aug 24 03:17:45 PM UTC 24 |
| Peak memory | 635072 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=80_000_000 +calibrate_usb_clk=1 +chip_cl ock_source=ChipClockSourceExternal48Mhz +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3503929916 -assert nopostproc +UV M_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_baudrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr atch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.chip_sw_uart_tx_rx_alt_clk_freq_low_speed.3503929916 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/3.chip_sw_uart_tx_rx_alt_clk_freq_low_speed/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/3.chip_sw_uart_tx_rx_idx1.95162892 |
| Short name | T1257 |
| Test name | |
| Test status | |
| Simulation time | 4497857282 ps |
| CPU time | 441.6 seconds |
| Started | Aug 24 03:04:05 PM UTC 24 |
| Finished | Aug 24 03:11:32 PM UTC 24 |
| Peak memory | 636860 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/default/simv +uart_idx=1 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw _images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=95162892 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_tx_rx_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.chip_sw_uart_tx_rx_idx1.95162892 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/3.chip_sw_uart_tx_rx_idx1/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/3.chip_sw_uart_tx_rx_idx2.1228734774 |
| Short name | T1256 |
| Test name | |
| Test status | |
| Simulation time | 3699901452 ps |
| CPU time | 376.52 seconds |
| Started | Aug 24 03:04:58 PM UTC 24 |
| Finished | Aug 24 03:11:20 PM UTC 24 |
| Peak memory | 637128 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/default/simv +uart_idx=2 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw _images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1228734774 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_tx_rx_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 3.chip_sw_uart_tx_rx_idx2.1228734774 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/3.chip_sw_uart_tx_rx_idx2/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/3.chip_sw_uart_tx_rx_idx3.3454908747 |
| Short name | T1255 |
| Test name | |
| Test status | |
| Simulation time | 4010684412 ps |
| CPU time | 372.39 seconds |
| Started | Aug 24 03:04:58 PM UTC 24 |
| Finished | Aug 24 03:11:16 PM UTC 24 |
| Peak memory | 639392 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/default/simv +uart_idx=3 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw _images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3454908747 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_tx_rx_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 3.chip_sw_uart_tx_rx_idx3.3454908747 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/3.chip_sw_uart_tx_rx_idx3/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/3.chip_tap_straps_dev.2307066571 |
| Short name | T1259 |
| Test name | |
| Test status | |
| Simulation time | 2383526044 ps |
| CPU time | 126.53 seconds |
| Started | Aug 24 03:11:47 PM UTC 24 |
| Finished | Aug 24 03:13:56 PM UTC 24 |
| Peak memory | 640884 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/default/simv +use_otp_image=OtpTypeLcStDev +create_jtag_riscv_map=1 +sw_b uild_device=sim_dv +sw_images=example_test_from_rom:0:test_in_rom:new_rules +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2307066571 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SE Q=chip_tap_straps_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.chip_tap_straps_dev.2307066571 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/3.chip_tap_straps_dev/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/3.chip_tap_straps_prod.500979442 |
| Short name | T1267 |
| Test name | |
| Test status | |
| Simulation time | 8244053670 ps |
| CPU time | 506.96 seconds |
| Started | Aug 24 03:14:24 PM UTC 24 |
| Finished | Aug 24 03:22:57 PM UTC 24 |
| Peak memory | 643964 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/default/simv +use_otp_image=OtpTypeLcStProd +create_jtag_riscv_map=1 +sw_ build_device=sim_dv +sw_images=example_test_from_rom:0:test_in_rom:new_rules +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=500979442 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SE Q=chip_tap_straps_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.chip_tap_straps_prod.500979442 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/3.chip_tap_straps_prod/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/3.chip_tap_straps_rma.509289893 |
| Short name | T1265 |
| Test name | |
| Test status | |
| Simulation time | 6115307303 ps |
| CPU time | 380.62 seconds |
| Started | Aug 24 03:12:30 PM UTC 24 |
| Finished | Aug 24 03:18:56 PM UTC 24 |
| Peak memory | 651900 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/default/simv +create_jtag_riscv_map=1 +sw_build_device=sim_dv +sw_images= example_test_from_rom:0:test_in_rom:new_rules +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac es/repo/hw/dv/tools/sim.tcl +ntb_random_seed=509289893 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_tap_straps_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -c m_log /dev/null -cm_name 3.chip_tap_straps_rma.509289893 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/3.chip_tap_straps_rma/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/3.chip_tap_straps_testunlock0.825123315 |
| Short name | T1262 |
| Test name | |
| Test status | |
| Simulation time | 4350410421 ps |
| CPU time | 284.99 seconds |
| Started | Aug 24 03:11:55 PM UTC 24 |
| Finished | Aug 24 03:16:44 PM UTC 24 |
| Peak memory | 639676 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/default/simv +use_otp_image=OtpTypeLcStTestUnlocked0 +create_jtag_riscv_m ap=1 +sw_build_device=sim_dv +sw_images=example_test_from_rom:0:test_in_rom:new_rules +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=825123315 -assert nopostproc +UVM_TESTNAME=chip_base_test +UV M_TEST_SEQ=chip_tap_straps_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlg rey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.chip_tap_straps_testunlock0.825123315 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/3.chip_tap_straps_testunlock0/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/30.chip_sw_alert_handler_lpg_sleep_mode_alerts.2470701908 |
| Short name | T289 |
| Test name | |
| Test status | |
| Simulation time | 3870537552 ps |
| CPU time | 278.67 seconds |
| Started | Aug 24 04:02:42 PM UTC 24 |
| Finished | Aug 24 04:07:25 PM UTC 24 |
| Peak memory | 673200 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_rea dy_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv _core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_handler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2470701908 -assert nopos tproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.chip_sw_alert_handler_lpg_ sleep_mode_alerts.2470701908 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/30.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/31.chip_sw_alert_handler_lpg_sleep_mode_alerts.2672000132 |
| Short name | T293 |
| Test name | |
| Test status | |
| Simulation time | 3270130584 ps |
| CPU time | 271.06 seconds |
| Started | Aug 24 04:03:41 PM UTC 24 |
| Finished | Aug 24 04:08:16 PM UTC 24 |
| Peak memory | 673380 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_rea dy_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv _core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_handler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2672000132 -assert nopos tproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.chip_sw_alert_handler_lpg_ sleep_mode_alerts.2672000132 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/31.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/34.chip_sw_alert_handler_lpg_sleep_mode_alerts.3441563907 |
| Short name | T708 |
| Test name | |
| Test status | |
| Simulation time | 3842603192 ps |
| CPU time | 232.05 seconds |
| Started | Aug 24 04:05:45 PM UTC 24 |
| Finished | Aug 24 04:09:40 PM UTC 24 |
| Peak memory | 673464 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_rea dy_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv _core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_handler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3441563907 -assert nopos tproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.chip_sw_alert_handler_lpg_ sleep_mode_alerts.3441563907 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/34.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/36.chip_sw_alert_handler_lpg_sleep_mode_alerts.2698080702 |
| Short name | T390 |
| Test name | |
| Test status | |
| Simulation time | 3849973636 ps |
| CPU time | 278.16 seconds |
| Started | Aug 24 04:06:47 PM UTC 24 |
| Finished | Aug 24 04:11:29 PM UTC 24 |
| Peak memory | 673204 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_rea dy_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv _core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_handler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2698080702 -assert nopos tproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.chip_sw_alert_handler_lpg_ sleep_mode_alerts.2698080702 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/36.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/36.chip_sw_all_escalation_resets.1880435650 |
| Short name | T1319 |
| Test name | |
| Test status | |
| Simulation time | 5571421546 ps |
| CPU time | 513.86 seconds |
| Started | Aug 24 04:06:31 PM UTC 24 |
| Finished | Aug 24 04:15:11 PM UTC 24 |
| Peak memory | 675440 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv + sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1880435650 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_es calation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.chip_sw_all_escalation_resets.1880435650 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/36.chip_sw_all_escalation_resets/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/37.chip_sw_alert_handler_lpg_sleep_mode_alerts.2980565882 |
| Short name | T391 |
| Test name | |
| Test status | |
| Simulation time | 3806691212 ps |
| CPU time | 265.47 seconds |
| Started | Aug 24 04:07:27 PM UTC 24 |
| Finished | Aug 24 04:11:56 PM UTC 24 |
| Peak memory | 673284 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_rea dy_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv _core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_handler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2980565882 -assert nopos tproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.chip_sw_alert_handler_lpg_ sleep_mode_alerts.2980565882 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/37.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/38.chip_sw_alert_handler_lpg_sleep_mode_alerts.3380280106 |
| Short name | T398 |
| Test name | |
| Test status | |
| Simulation time | 4225605890 ps |
| CPU time | 319.24 seconds |
| Started | Aug 24 04:08:29 PM UTC 24 |
| Finished | Aug 24 04:13:53 PM UTC 24 |
| Peak memory | 673208 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_rea dy_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv _core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_handler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3380280106 -assert nopos tproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.chip_sw_alert_handler_lpg_ sleep_mode_alerts.3380280106 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/38.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/38.chip_sw_all_escalation_resets.2355852049 |
| Short name | T685 |
| Test name | |
| Test status | |
| Simulation time | 4817528536 ps |
| CPU time | 467.78 seconds |
| Started | Aug 24 04:07:51 PM UTC 24 |
| Finished | Aug 24 04:15:44 PM UTC 24 |
| Peak memory | 675212 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv + sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2355852049 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_es calation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.chip_sw_all_escalation_resets.2355852049 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/38.chip_sw_all_escalation_resets/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/39.chip_sw_all_escalation_resets.960484165 |
| Short name | T265 |
| Test name | |
| Test status | |
| Simulation time | 4557704528 ps |
| CPU time | 388.93 seconds |
| Started | Aug 24 04:08:30 PM UTC 24 |
| Finished | Aug 24 04:15:04 PM UTC 24 |
| Peak memory | 675452 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv + sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=960484165 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_esc alation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.chip_sw_all_escalation_resets.960484165 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/39.chip_sw_all_escalation_resets/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/4.chip_sw_aon_timer_sleep_wdog_sleep_pause.3733761219 |
| Short name | T1279 |
| Test name | |
| Test status | |
| Simulation time | 7086925072 ps |
| CPU time | 314.21 seconds |
| Started | Aug 24 03:23:21 PM UTC 24 |
| Finished | Aug 24 03:28:39 PM UTC 24 |
| Peak memory | 626936 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_i mages=aon_timer_sleep_wdog_sleep_pause_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu e -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3733761219 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw _base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cove rage/default.vdb -cm_log /dev/null -cm_name 4.chip_sw_aon_timer_sleep_wdog_sleep_pause.3733761219 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/4.chip_sw_aon_timer_sleep_wdog_sleep_pause/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/4.chip_sw_csrng_edn_concurrency.4225787017 |
| Short name | T1333 |
| Test name | |
| Test status | |
| Simulation time | 22242419768 ps |
| CPU time | 4270.06 seconds |
| Started | Aug 24 03:24:15 PM UTC 24 |
| Finished | Aug 24 04:36:11 PM UTC 24 |
| Peak memory | 629800 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=140_000_000 +rng_srate_value_min=15 +rng _srate_value_max=20 +accelerate_cold_power_up_time=3 +accelerate_regulators_power_up_time=2 +sw_build_device=sim_dv +sw_images=csrng_edn_concurren cy_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/t ools/sim.tcl +ntb_random_seed=4225787017 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null - cm_name 4.chip_sw_csrng_edn_concurrency.4225787017 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/4.chip_sw_csrng_edn_concurrency/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/4.chip_sw_data_integrity_escalation.3808959780 |
| Short name | T1268 |
| Test name | |
| Test status | |
| Simulation time | 6253427358 ps |
| CPU time | 387.26 seconds |
| Started | Aug 24 03:16:34 PM UTC 24 |
| Finished | Aug 24 03:23:06 PM UTC 24 |
| Peak memory | 626944 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv + sw_images=data_integrity_escalation_reset_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3808959780 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip _sw_data_integrity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.chip_sw_data_integrity_escalation.3808959780 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/4.chip_sw_data_integrity_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/4.chip_sw_lc_ctrl_transition.1813898182 |
| Short name | T1291 |
| Test name | |
| Test status | |
| Simulation time | 10005340114 ps |
| CPU time | 796.47 seconds |
| Started | Aug 24 03:22:47 PM UTC 24 |
| Finished | Aug 24 03:36:13 PM UTC 24 |
| Peak memory | 639048 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=lc_ctrl_transition_test:1 :new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim. tcl +ntb_random_seed=1813898182 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_ctrl_transition_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/n ull -cm_name 4.chip_sw_lc_ctrl_transition.1813898182 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/4.chip_sw_lc_ctrl_transition/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/4.chip_sw_sensor_ctrl_alert.3619797535 |
| Short name | T173 |
| Test name | |
| Test status | |
| Simulation time | 5657815214 ps |
| CPU time | 571.26 seconds |
| Started | Aug 24 03:24:53 PM UTC 24 |
| Finished | Aug 24 03:34:31 PM UTC 24 |
| Peak memory | 626748 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=40_000_000 +sw_build_device=sim_dv +sw_i mages=sensor_ctrl_alert_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo rkspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3619797535 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default.vd b -cm_log /dev/null -cm_name 4.chip_sw_sensor_ctrl_alert.3619797535 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/4.chip_sw_sensor_ctrl_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/4.chip_sw_uart_rand_baudrate.1420801642 |
| Short name | T1294 |
| Test name | |
| Test status | |
| Simulation time | 8370426696 ps |
| CPU time | 1081.66 seconds |
| Started | Aug 24 03:19:21 PM UTC 24 |
| Finished | Aug 24 03:37:34 PM UTC 24 |
| Peak memory | 637044 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=80_000_000 +calibrate_usb_clk=1 +sw_buil d_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1420801642 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_ uart_rand_baudrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.chip_sw_uart_rand_baudrate.1420801642 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/4.chip_sw_uart_rand_baudrate/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/4.chip_sw_uart_tx_rx.2885369335 |
| Short name | T1269 |
| Test name | |
| Test status | |
| Simulation time | 4567696360 ps |
| CPU time | 430.21 seconds |
| Started | Aug 24 03:16:34 PM UTC 24 |
| Finished | Aug 24 03:23:50 PM UTC 24 |
| Peak memory | 639124 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/default/simv +uart_idx=0 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw _images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2885369335 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_tx_rx_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 4.chip_sw_uart_tx_rx.2885369335 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/4.chip_sw_uart_tx_rx/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/4.chip_sw_uart_tx_rx_alt_clk_freq.1069557481 |
| Short name | T1296 |
| Test name | |
| Test status | |
| Simulation time | 8731517814 ps |
| CPU time | 1144.43 seconds |
| Started | Aug 24 03:19:54 PM UTC 24 |
| Finished | Aug 24 03:39:11 PM UTC 24 |
| Peak memory | 634824 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=80_000_000 +chip_clock_source=ChipClockS ourceExternal96Mhz +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1069557481 -assert nopostproc +UV M_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_baudrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr atch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.chip_sw_uart_tx_rx_alt_clk_freq.1069557481 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/4.chip_sw_uart_tx_rx_alt_clk_freq/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/4.chip_sw_uart_tx_rx_alt_clk_freq_low_speed.985118893 |
| Short name | T1274 |
| Test name | |
| Test status | |
| Simulation time | 4379620676 ps |
| CPU time | 374.99 seconds |
| Started | Aug 24 03:20:28 PM UTC 24 |
| Finished | Aug 24 03:26:48 PM UTC 24 |
| Peak memory | 635076 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=80_000_000 +calibrate_usb_clk=1 +chip_cl ock_source=ChipClockSourceExternal48Mhz +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=985118893 -assert nopostproc +UVM _TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_baudrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra tch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.chip_sw_uart_tx_rx_alt_clk_freq_low_speed.985118893 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/4.chip_sw_uart_tx_rx_alt_clk_freq_low_speed/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/4.chip_sw_uart_tx_rx_idx1.231781061 |
| Short name | T1270 |
| Test name | |
| Test status | |
| Simulation time | 4895030304 ps |
| CPU time | 434.47 seconds |
| Started | Aug 24 03:17:09 PM UTC 24 |
| Finished | Aug 24 03:24:29 PM UTC 24 |
| Peak memory | 637124 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/default/simv +uart_idx=1 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw _images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=231781061 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_tx_rx_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default.vd b -cm_log /dev/null -cm_name 4.chip_sw_uart_tx_rx_idx1.231781061 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/4.chip_sw_uart_tx_rx_idx1/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/4.chip_sw_uart_tx_rx_idx2.732665046 |
| Short name | T1272 |
| Test name | |
| Test status | |
| Simulation time | 5121883026 ps |
| CPU time | 423.96 seconds |
| Started | Aug 24 03:18:10 PM UTC 24 |
| Finished | Aug 24 03:25:20 PM UTC 24 |
| Peak memory | 638916 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/default/simv +uart_idx=2 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw _images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=732665046 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_tx_rx_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default.vd b -cm_log /dev/null -cm_name 4.chip_sw_uart_tx_rx_idx2.732665046 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/4.chip_sw_uart_tx_rx_idx2/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/4.chip_sw_uart_tx_rx_idx3.925633508 |
| Short name | T1273 |
| Test name | |
| Test status | |
| Simulation time | 4445543960 ps |
| CPU time | 430.33 seconds |
| Started | Aug 24 03:19:05 PM UTC 24 |
| Finished | Aug 24 03:26:22 PM UTC 24 |
| Peak memory | 637080 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/default/simv +uart_idx=3 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw _images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=925633508 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_tx_rx_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default.vd b -cm_log /dev/null -cm_name 4.chip_sw_uart_tx_rx_idx3.925633508 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/4.chip_sw_uart_tx_rx_idx3/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/4.chip_tap_straps_dev.4225751285 |
| Short name | T1276 |
| Test name | |
| Test status | |
| Simulation time | 2554908299 ps |
| CPU time | 127.26 seconds |
| Started | Aug 24 03:25:23 PM UTC 24 |
| Finished | Aug 24 03:27:32 PM UTC 24 |
| Peak memory | 636796 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/default/simv +use_otp_image=OtpTypeLcStDev +create_jtag_riscv_map=1 +sw_b uild_device=sim_dv +sw_images=example_test_from_rom:0:test_in_rom:new_rules +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4225751285 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SE Q=chip_tap_straps_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.chip_tap_straps_dev.4225751285 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/4.chip_tap_straps_dev/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/4.chip_tap_straps_prod.2989148551 |
| Short name | T1297 |
| Test name | |
| Test status | |
| Simulation time | 11848055180 ps |
| CPU time | 744.17 seconds |
| Started | Aug 24 03:27:07 PM UTC 24 |
| Finished | Aug 24 03:39:40 PM UTC 24 |
| Peak memory | 641724 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/default/simv +use_otp_image=OtpTypeLcStProd +create_jtag_riscv_map=1 +sw_ build_device=sim_dv +sw_images=example_test_from_rom:0:test_in_rom:new_rules +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2989148551 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_S EQ=chip_tap_straps_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.chip_tap_straps_prod.2989148551 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/4.chip_tap_straps_prod/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/4.chip_tap_straps_rma.2584735210 |
| Short name | T1282 |
| Test name | |
| Test status | |
| Simulation time | 4807978191 ps |
| CPU time | 244.11 seconds |
| Started | Aug 24 03:26:41 PM UTC 24 |
| Finished | Aug 24 03:30:49 PM UTC 24 |
| Peak memory | 651900 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/default/simv +create_jtag_riscv_map=1 +sw_build_device=sim_dv +sw_images= example_test_from_rom:0:test_in_rom:new_rules +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac es/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2584735210 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_tap_straps_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default.vdb - cm_log /dev/null -cm_name 4.chip_tap_straps_rma.2584735210 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/4.chip_tap_straps_rma/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/4.chip_tap_straps_testunlock0.3460517440 |
| Short name | T1281 |
| Test name | |
| Test status | |
| Simulation time | 5241469106 ps |
| CPU time | 290.94 seconds |
| Started | Aug 24 03:25:39 PM UTC 24 |
| Finished | Aug 24 03:30:34 PM UTC 24 |
| Peak memory | 643772 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/default/simv +use_otp_image=OtpTypeLcStTestUnlocked0 +create_jtag_riscv_m ap=1 +sw_build_device=sim_dv +sw_images=example_test_from_rom:0:test_in_rom:new_rules +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3460517440 -assert nopostproc +UVM_TESTNAME=chip_base_test +U VM_TEST_SEQ=chip_tap_straps_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/chip_earl grey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.chip_tap_straps_testunlock0.3460517440 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/4.chip_tap_straps_testunlock0/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/40.chip_sw_alert_handler_lpg_sleep_mode_alerts.498213852 |
| Short name | T396 |
| Test name | |
| Test status | |
| Simulation time | 3897189664 ps |
| CPU time | 252.51 seconds |
| Started | Aug 24 04:08:58 PM UTC 24 |
| Finished | Aug 24 04:13:14 PM UTC 24 |
| Peak memory | 673464 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_rea dy_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv _core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_handler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=498213852 -assert nopost proc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac es/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.chip_sw_alert_handler_lpg_s leep_mode_alerts.498213852 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/40.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/40.chip_sw_all_escalation_resets.2807570171 |
| Short name | T1321 |
| Test name | |
| Test status | |
| Simulation time | 5700154828 ps |
| CPU time | 420.06 seconds |
| Started | Aug 24 04:08:57 PM UTC 24 |
| Finished | Aug 24 04:16:03 PM UTC 24 |
| Peak memory | 675196 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv + sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2807570171 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_es calation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.chip_sw_all_escalation_resets.2807570171 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/40.chip_sw_all_escalation_resets/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/41.chip_sw_alert_handler_lpg_sleep_mode_alerts.3029900001 |
| Short name | T745 |
| Test name | |
| Test status | |
| Simulation time | 4224301240 ps |
| CPU time | 274.53 seconds |
| Started | Aug 24 04:10:08 PM UTC 24 |
| Finished | Aug 24 04:14:46 PM UTC 24 |
| Peak memory | 673228 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_rea dy_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv _core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_handler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3029900001 -assert nopos tproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.chip_sw_alert_handler_lpg_ sleep_mode_alerts.3029900001 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/41.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/42.chip_sw_alert_handler_lpg_sleep_mode_alerts.1750909917 |
| Short name | T756 |
| Test name | |
| Test status | |
| Simulation time | 3288979828 ps |
| CPU time | 259.55 seconds |
| Started | Aug 24 04:10:09 PM UTC 24 |
| Finished | Aug 24 04:14:32 PM UTC 24 |
| Peak memory | 673216 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_rea dy_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv _core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_handler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1750909917 -assert nopos tproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.chip_sw_alert_handler_lpg_ sleep_mode_alerts.1750909917 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/42.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/42.chip_sw_all_escalation_resets.1913247280 |
| Short name | T203 |
| Test name | |
| Test status | |
| Simulation time | 5498624372 ps |
| CPU time | 352.47 seconds |
| Started | Aug 24 04:10:09 PM UTC 24 |
| Finished | Aug 24 04:16:06 PM UTC 24 |
| Peak memory | 637376 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv + sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1913247280 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_es calation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.chip_sw_all_escalation_resets.1913247280 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/42.chip_sw_all_escalation_resets/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/46.chip_sw_all_escalation_resets.3679725913 |
| Short name | T778 |
| Test name | |
| Test status | |
| Simulation time | 5898707962 ps |
| CPU time | 467.03 seconds |
| Started | Aug 24 04:13:39 PM UTC 24 |
| Finished | Aug 24 04:21:32 PM UTC 24 |
| Peak memory | 676128 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv + sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3679725913 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_es calation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.chip_sw_all_escalation_resets.3679725913 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/46.chip_sw_all_escalation_resets/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/47.chip_sw_alert_handler_lpg_sleep_mode_alerts.3370175152 |
| Short name | T709 |
| Test name | |
| Test status | |
| Simulation time | 3928613704 ps |
| CPU time | 320.34 seconds |
| Started | Aug 24 04:14:26 PM UTC 24 |
| Finished | Aug 24 04:19:51 PM UTC 24 |
| Peak memory | 673464 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_rea dy_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv _core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_handler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3370175152 -assert nopos tproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.chip_sw_alert_handler_lpg_ sleep_mode_alerts.3370175152 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/47.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/47.chip_sw_all_escalation_resets.4020949942 |
| Short name | T716 |
| Test name | |
| Test status | |
| Simulation time | 4931177850 ps |
| CPU time | 426.71 seconds |
| Started | Aug 24 04:14:26 PM UTC 24 |
| Finished | Aug 24 04:21:38 PM UTC 24 |
| Peak memory | 676088 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv + sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4020949942 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_es calation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.chip_sw_all_escalation_resets.4020949942 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/47.chip_sw_all_escalation_resets/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/49.chip_sw_alert_handler_lpg_sleep_mode_alerts.2380995576 |
| Short name | T744 |
| Test name | |
| Test status | |
| Simulation time | 4025333440 ps |
| CPU time | 336.11 seconds |
| Started | Aug 24 04:15:46 PM UTC 24 |
| Finished | Aug 24 04:21:26 PM UTC 24 |
| Peak memory | 673460 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_rea dy_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv _core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_handler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2380995576 -assert nopos tproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.chip_sw_alert_handler_lpg_ sleep_mode_alerts.2380995576 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/49.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/49.chip_sw_all_escalation_resets.1625904321 |
| Short name | T771 |
| Test name | |
| Test status | |
| Simulation time | 5853887370 ps |
| CPU time | 483.07 seconds |
| Started | Aug 24 04:15:44 PM UTC 24 |
| Finished | Aug 24 04:23:54 PM UTC 24 |
| Peak memory | 676088 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv + sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1625904321 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_es calation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.chip_sw_all_escalation_resets.1625904321 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/49.chip_sw_all_escalation_resets/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/5.chip_sw_all_escalation_resets.2807437099 |
| Short name | T742 |
| Test name | |
| Test status | |
| Simulation time | 5373536872 ps |
| CPU time | 455.94 seconds |
| Started | Aug 24 03:27:23 PM UTC 24 |
| Finished | Aug 24 03:35:05 PM UTC 24 |
| Peak memory | 675192 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv + sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2807437099 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_es calation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.chip_sw_all_escalation_resets.2807437099 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/5.chip_sw_all_escalation_resets/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/5.chip_sw_csrng_edn_concurrency.2268021218 |
| Short name | T1342 |
| Test name | |
| Test status | |
| Simulation time | 28516678932 ps |
| CPU time | 5255.56 seconds |
| Started | Aug 24 03:29:43 PM UTC 24 |
| Finished | Aug 24 04:58:12 PM UTC 24 |
| Peak memory | 629800 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=140_000_000 +rng_srate_value_min=15 +rng _srate_value_max=20 +accelerate_cold_power_up_time=3 +accelerate_regulators_power_up_time=2 +sw_build_device=sim_dv +sw_images=csrng_edn_concurren cy_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/t ools/sim.tcl +ntb_random_seed=2268021218 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null - cm_name 5.chip_sw_csrng_edn_concurrency.2268021218 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/5.chip_sw_csrng_edn_concurrency/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/5.chip_sw_data_integrity_escalation.1638089708 |
| Short name | T378 |
| Test name | |
| Test status | |
| Simulation time | 5887139928 ps |
| CPU time | 453.88 seconds |
| Started | Aug 24 03:27:56 PM UTC 24 |
| Finished | Aug 24 03:35:36 PM UTC 24 |
| Peak memory | 626704 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv + sw_images=data_integrity_escalation_reset_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1638089708 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip _sw_data_integrity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.chip_sw_data_integrity_escalation.1638089708 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/5.chip_sw_data_integrity_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/5.chip_sw_lc_ctrl_transition.3021946882 |
| Short name | T1299 |
| Test name | |
| Test status | |
| Simulation time | 9014745259 ps |
| CPU time | 663.33 seconds |
| Started | Aug 24 03:29:02 PM UTC 24 |
| Finished | Aug 24 03:40:13 PM UTC 24 |
| Peak memory | 639316 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=lc_ctrl_transition_test:1 :new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim. tcl +ntb_random_seed=3021946882 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_ctrl_transition_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/n ull -cm_name 5.chip_sw_lc_ctrl_transition.3021946882 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/5.chip_sw_lc_ctrl_transition/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/5.chip_sw_uart_rand_baudrate.1746153614 |
| Short name | T1288 |
| Test name | |
| Test status | |
| Simulation time | 4355219352 ps |
| CPU time | 408.82 seconds |
| Started | Aug 24 03:28:38 PM UTC 24 |
| Finished | Aug 24 03:35:32 PM UTC 24 |
| Peak memory | 636864 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=80_000_000 +calibrate_usb_clk=1 +sw_buil d_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1746153614 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_ uart_rand_baudrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.chip_sw_uart_rand_baudrate.1746153614 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/5.chip_sw_uart_rand_baudrate/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/51.chip_sw_alert_handler_lpg_sleep_mode_alerts.382879877 |
| Short name | T728 |
| Test name | |
| Test status | |
| Simulation time | 4069202060 ps |
| CPU time | 354.99 seconds |
| Started | Aug 24 04:16:15 PM UTC 24 |
| Finished | Aug 24 04:22:14 PM UTC 24 |
| Peak memory | 673460 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_rea dy_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv _core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_handler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=382879877 -assert nopost proc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac es/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 51.chip_sw_alert_handler_lpg_s leep_mode_alerts.382879877 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/51.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/51.chip_sw_all_escalation_resets.4183666828 |
| Short name | T723 |
| Test name | |
| Test status | |
| Simulation time | 5157150270 ps |
| CPU time | 502.81 seconds |
| Started | Aug 24 04:16:15 PM UTC 24 |
| Finished | Aug 24 04:24:44 PM UTC 24 |
| Peak memory | 676084 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv + sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4183666828 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_es calation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 51.chip_sw_all_escalation_resets.4183666828 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/51.chip_sw_all_escalation_resets/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/52.chip_sw_alert_handler_lpg_sleep_mode_alerts.1422333539 |
| Short name | T701 |
| Test name | |
| Test status | |
| Simulation time | 4391759556 ps |
| CPU time | 298.74 seconds |
| Started | Aug 24 04:16:36 PM UTC 24 |
| Finished | Aug 24 04:21:39 PM UTC 24 |
| Peak memory | 673280 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_rea dy_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv _core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_handler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1422333539 -assert nopos tproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 52.chip_sw_alert_handler_lpg_ sleep_mode_alerts.1422333539 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/52.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/52.chip_sw_all_escalation_resets.146512253 |
| Short name | T775 |
| Test name | |
| Test status | |
| Simulation time | 4929968024 ps |
| CPU time | 461.22 seconds |
| Started | Aug 24 04:16:36 PM UTC 24 |
| Finished | Aug 24 04:24:22 PM UTC 24 |
| Peak memory | 675256 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv + sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=146512253 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_esc alation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 52.chip_sw_all_escalation_resets.146512253 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/52.chip_sw_all_escalation_resets/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/53.chip_sw_alert_handler_lpg_sleep_mode_alerts.1714853902 |
| Short name | T750 |
| Test name | |
| Test status | |
| Simulation time | 3968865872 ps |
| CPU time | 275.59 seconds |
| Started | Aug 24 04:17:32 PM UTC 24 |
| Finished | Aug 24 04:22:11 PM UTC 24 |
| Peak memory | 673208 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_rea dy_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv _core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_handler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1714853902 -assert nopos tproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 53.chip_sw_alert_handler_lpg_ sleep_mode_alerts.1714853902 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/53.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/54.chip_sw_alert_handler_lpg_sleep_mode_alerts.542982684 |
| Short name | T734 |
| Test name | |
| Test status | |
| Simulation time | 3789303628 ps |
| CPU time | 274.23 seconds |
| Started | Aug 24 04:19:06 PM UTC 24 |
| Finished | Aug 24 04:23:44 PM UTC 24 |
| Peak memory | 673284 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_rea dy_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv _core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_handler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=542982684 -assert nopost proc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac es/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 54.chip_sw_alert_handler_lpg_s leep_mode_alerts.542982684 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/54.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/54.chip_sw_all_escalation_resets.410014666 |
| Short name | T1328 |
| Test name | |
| Test status | |
| Simulation time | 4843703514 ps |
| CPU time | 499.08 seconds |
| Started | Aug 24 04:18:45 PM UTC 24 |
| Finished | Aug 24 04:27:10 PM UTC 24 |
| Peak memory | 678360 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv + sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=410014666 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_esc alation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 54.chip_sw_all_escalation_resets.410014666 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/54.chip_sw_all_escalation_resets/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/55.chip_sw_alert_handler_lpg_sleep_mode_alerts.1567220329 |
| Short name | T780 |
| Test name | |
| Test status | |
| Simulation time | 4167191472 ps |
| CPU time | 276.03 seconds |
| Started | Aug 24 04:20:01 PM UTC 24 |
| Finished | Aug 24 04:24:41 PM UTC 24 |
| Peak memory | 673208 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_rea dy_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv _core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_handler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1567220329 -assert nopos tproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 55.chip_sw_alert_handler_lpg_ sleep_mode_alerts.1567220329 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/55.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/55.chip_sw_all_escalation_resets.2189564879 |
| Short name | T112 |
| Test name | |
| Test status | |
| Simulation time | 5524855970 ps |
| CPU time | 449.81 seconds |
| Started | Aug 24 04:19:20 PM UTC 24 |
| Finished | Aug 24 04:26:56 PM UTC 24 |
| Peak memory | 675296 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv + sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2189564879 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_es calation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 55.chip_sw_all_escalation_resets.2189564879 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/55.chip_sw_all_escalation_resets/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/56.chip_sw_alert_handler_lpg_sleep_mode_alerts.1015442570 |
| Short name | T772 |
| Test name | |
| Test status | |
| Simulation time | 4012677660 ps |
| CPU time | 308.12 seconds |
| Started | Aug 24 04:20:21 PM UTC 24 |
| Finished | Aug 24 04:25:33 PM UTC 24 |
| Peak memory | 673212 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_rea dy_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv _core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_handler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1015442570 -assert nopos tproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 56.chip_sw_alert_handler_lpg_ sleep_mode_alerts.1015442570 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/56.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/57.chip_sw_alert_handler_lpg_sleep_mode_alerts.3824512377 |
| Short name | T760 |
| Test name | |
| Test status | |
| Simulation time | 3598511924 ps |
| CPU time | 282.25 seconds |
| Started | Aug 24 04:21:19 PM UTC 24 |
| Finished | Aug 24 04:26:05 PM UTC 24 |
| Peak memory | 673216 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_rea dy_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv _core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_handler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3824512377 -assert nopos tproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 57.chip_sw_alert_handler_lpg_ sleep_mode_alerts.3824512377 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/57.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/58.chip_sw_alert_handler_lpg_sleep_mode_alerts.3979296303 |
| Short name | T724 |
| Test name | |
| Test status | |
| Simulation time | 3388628600 ps |
| CPU time | 260.81 seconds |
| Started | Aug 24 04:22:39 PM UTC 24 |
| Finished | Aug 24 04:27:03 PM UTC 24 |
| Peak memory | 673400 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_rea dy_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv _core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_handler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3979296303 -assert nopos tproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 58.chip_sw_alert_handler_lpg_ sleep_mode_alerts.3979296303 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/58.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/59.chip_sw_alert_handler_lpg_sleep_mode_alerts.393659049 |
| Short name | T1327 |
| Test name | |
| Test status | |
| Simulation time | 3273666600 ps |
| CPU time | 257.17 seconds |
| Started | Aug 24 04:22:41 PM UTC 24 |
| Finished | Aug 24 04:27:02 PM UTC 24 |
| Peak memory | 637508 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_rea dy_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv _core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_handler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=393659049 -assert nopost proc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac es/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 59.chip_sw_alert_handler_lpg_s leep_mode_alerts.393659049 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/59.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/59.chip_sw_all_escalation_resets.219865261 |
| Short name | T355 |
| Test name | |
| Test status | |
| Simulation time | 5542399762 ps |
| CPU time | 468.41 seconds |
| Started | Aug 24 04:22:53 PM UTC 24 |
| Finished | Aug 24 04:30:48 PM UTC 24 |
| Peak memory | 675396 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv + sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=219865261 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_esc alation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 59.chip_sw_all_escalation_resets.219865261 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/59.chip_sw_all_escalation_resets/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/6.chip_sw_alert_handler_lpg_sleep_mode_alerts.3727952174 |
| Short name | T765 |
| Test name | |
| Test status | |
| Simulation time | 3424452404 ps |
| CPU time | 256.14 seconds |
| Started | Aug 24 03:31:31 PM UTC 24 |
| Finished | Aug 24 03:35:51 PM UTC 24 |
| Peak memory | 673216 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_rea dy_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv _core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_handler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3727952174 -assert nopos tproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.chip_sw_alert_handler_lpg_s leep_mode_alerts.3727952174 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/6.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/6.chip_sw_csrng_edn_concurrency.2856008041 |
| Short name | T1325 |
| Test name | |
| Test status | |
| Simulation time | 17410648912 ps |
| CPU time | 3150.71 seconds |
| Started | Aug 24 03:33:25 PM UTC 24 |
| Finished | Aug 24 04:26:30 PM UTC 24 |
| Peak memory | 627752 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=140_000_000 +rng_srate_value_min=15 +rng _srate_value_max=20 +accelerate_cold_power_up_time=3 +accelerate_regulators_power_up_time=2 +sw_build_device=sim_dv +sw_images=csrng_edn_concurren cy_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/t ools/sim.tcl +ntb_random_seed=2856008041 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null - cm_name 6.chip_sw_csrng_edn_concurrency.2856008041 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/6.chip_sw_csrng_edn_concurrency/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/6.chip_sw_lc_ctrl_transition.1027442037 |
| Short name | T1293 |
| Test name | |
| Test status | |
| Simulation time | 5131152322 ps |
| CPU time | 374.95 seconds |
| Started | Aug 24 03:31:12 PM UTC 24 |
| Finished | Aug 24 03:37:32 PM UTC 24 |
| Peak memory | 639192 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=lc_ctrl_transition_test:1 :new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim. tcl +ntb_random_seed=1027442037 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_ctrl_transition_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/n ull -cm_name 6.chip_sw_lc_ctrl_transition.1027442037 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/6.chip_sw_lc_ctrl_transition/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/6.chip_sw_uart_rand_baudrate.3100563874 |
| Short name | T1306 |
| Test name | |
| Test status | |
| Simulation time | 7927503448 ps |
| CPU time | 1224.13 seconds |
| Started | Aug 24 03:30:58 PM UTC 24 |
| Finished | Aug 24 03:51:36 PM UTC 24 |
| Peak memory | 637124 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=80_000_000 +calibrate_usb_clk=1 +sw_buil d_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3100563874 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_ uart_rand_baudrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.chip_sw_uart_rand_baudrate.3100563874 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/6.chip_sw_uart_rand_baudrate/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/60.chip_sw_alert_handler_lpg_sleep_mode_alerts.257299085 |
| Short name | T1326 |
| Test name | |
| Test status | |
| Simulation time | 3681740902 ps |
| CPU time | 241.36 seconds |
| Started | Aug 24 04:22:54 PM UTC 24 |
| Finished | Aug 24 04:26:59 PM UTC 24 |
| Peak memory | 673428 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_rea dy_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv _core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_handler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=257299085 -assert nopost proc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac es/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 60.chip_sw_alert_handler_lpg_s leep_mode_alerts.257299085 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/60.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/60.chip_sw_all_escalation_resets.41396714 |
| Short name | T357 |
| Test name | |
| Test status | |
| Simulation time | 6410548672 ps |
| CPU time | 486.05 seconds |
| Started | Aug 24 04:22:50 PM UTC 24 |
| Finished | Aug 24 04:31:02 PM UTC 24 |
| Peak memory | 675960 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv + sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=41396714 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_esca lation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 60.chip_sw_all_escalation_resets.41396714 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/60.chip_sw_all_escalation_resets/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/62.chip_sw_alert_handler_lpg_sleep_mode_alerts.2045032003 |
| Short name | T714 |
| Test name | |
| Test status | |
| Simulation time | 3633638372 ps |
| CPU time | 305.02 seconds |
| Started | Aug 24 04:24:08 PM UTC 24 |
| Finished | Aug 24 04:29:17 PM UTC 24 |
| Peak memory | 673208 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_rea dy_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv _core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_handler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2045032003 -assert nopos tproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 62.chip_sw_alert_handler_lpg_ sleep_mode_alerts.2045032003 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/62.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/62.chip_sw_all_escalation_resets.628276662 |
| Short name | T356 |
| Test name | |
| Test status | |
| Simulation time | 5326674944 ps |
| CPU time | 466.61 seconds |
| Started | Aug 24 04:22:56 PM UTC 24 |
| Finished | Aug 24 04:30:49 PM UTC 24 |
| Peak memory | 675516 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv + sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=628276662 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_esc alation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 62.chip_sw_all_escalation_resets.628276662 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/62.chip_sw_all_escalation_resets/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/63.chip_sw_alert_handler_lpg_sleep_mode_alerts.738500998 |
| Short name | T668 |
| Test name | |
| Test status | |
| Simulation time | 3645527144 ps |
| CPU time | 254.59 seconds |
| Started | Aug 24 04:24:36 PM UTC 24 |
| Finished | Aug 24 04:28:55 PM UTC 24 |
| Peak memory | 673464 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_rea dy_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv _core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_handler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=738500998 -assert nopost proc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac es/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 63.chip_sw_alert_handler_lpg_s leep_mode_alerts.738500998 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/63.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/63.chip_sw_all_escalation_resets.882374669 |
| Short name | T359 |
| Test name | |
| Test status | |
| Simulation time | 4664065240 ps |
| CPU time | 453.35 seconds |
| Started | Aug 24 04:24:36 PM UTC 24 |
| Finished | Aug 24 04:32:15 PM UTC 24 |
| Peak memory | 676148 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv + sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=882374669 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_esc alation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 63.chip_sw_all_escalation_resets.882374669 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/63.chip_sw_all_escalation_resets/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/64.chip_sw_alert_handler_lpg_sleep_mode_alerts.339639813 |
| Short name | T732 |
| Test name | |
| Test status | |
| Simulation time | 3747566416 ps |
| CPU time | 283.39 seconds |
| Started | Aug 24 04:24:55 PM UTC 24 |
| Finished | Aug 24 04:29:42 PM UTC 24 |
| Peak memory | 673212 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_rea dy_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv _core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_handler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=339639813 -assert nopost proc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac es/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 64.chip_sw_alert_handler_lpg_s leep_mode_alerts.339639813 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/64.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/64.chip_sw_all_escalation_resets.1348638612 |
| Short name | T353 |
| Test name | |
| Test status | |
| Simulation time | 4663517158 ps |
| CPU time | 352.49 seconds |
| Started | Aug 24 04:24:37 PM UTC 24 |
| Finished | Aug 24 04:30:34 PM UTC 24 |
| Peak memory | 675196 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv + sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1348638612 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_es calation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 64.chip_sw_all_escalation_resets.1348638612 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/64.chip_sw_all_escalation_resets/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/65.chip_sw_alert_handler_lpg_sleep_mode_alerts.897368997 |
| Short name | T352 |
| Test name | |
| Test status | |
| Simulation time | 4092786104 ps |
| CPU time | 306.69 seconds |
| Started | Aug 24 04:25:13 PM UTC 24 |
| Finished | Aug 24 04:30:24 PM UTC 24 |
| Peak memory | 673352 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_rea dy_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv _core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_handler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=897368997 -assert nopost proc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac es/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 65.chip_sw_alert_handler_lpg_s leep_mode_alerts.897368997 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/65.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/65.chip_sw_all_escalation_resets.2112622173 |
| Short name | T358 |
| Test name | |
| Test status | |
| Simulation time | 4587273372 ps |
| CPU time | 402.97 seconds |
| Started | Aug 24 04:24:55 PM UTC 24 |
| Finished | Aug 24 04:31:43 PM UTC 24 |
| Peak memory | 675404 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv + sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2112622173 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_es calation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 65.chip_sw_all_escalation_resets.2112622173 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/65.chip_sw_all_escalation_resets/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/66.chip_sw_alert_handler_lpg_sleep_mode_alerts.1853042096 |
| Short name | T351 |
| Test name | |
| Test status | |
| Simulation time | 4155809048 ps |
| CPU time | 260.36 seconds |
| Started | Aug 24 04:25:58 PM UTC 24 |
| Finished | Aug 24 04:30:22 PM UTC 24 |
| Peak memory | 673204 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_rea dy_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv _core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_handler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1853042096 -assert nopos tproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 66.chip_sw_alert_handler_lpg_ sleep_mode_alerts.1853042096 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/66.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/66.chip_sw_all_escalation_resets.1094769222 |
| Short name | T288 |
| Test name | |
| Test status | |
| Simulation time | 5262106838 ps |
| CPU time | 482.75 seconds |
| Started | Aug 24 04:25:14 PM UTC 24 |
| Finished | Aug 24 04:33:22 PM UTC 24 |
| Peak memory | 675836 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv + sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1094769222 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_es calation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 66.chip_sw_all_escalation_resets.1094769222 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/66.chip_sw_all_escalation_resets/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/67.chip_sw_alert_handler_lpg_sleep_mode_alerts.1402208816 |
| Short name | T1330 |
| Test name | |
| Test status | |
| Simulation time | 4215532464 ps |
| CPU time | 336.01 seconds |
| Started | Aug 24 04:26:54 PM UTC 24 |
| Finished | Aug 24 04:32:35 PM UTC 24 |
| Peak memory | 673268 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_rea dy_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv _core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_handler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1402208816 -assert nopos tproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 67.chip_sw_alert_handler_lpg_ sleep_mode_alerts.1402208816 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/67.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/68.chip_sw_alert_handler_lpg_sleep_mode_alerts.167645286 |
| Short name | T1331 |
| Test name | |
| Test status | |
| Simulation time | 4400443200 ps |
| CPU time | 301.01 seconds |
| Started | Aug 24 04:28:12 PM UTC 24 |
| Finished | Aug 24 04:33:17 PM UTC 24 |
| Peak memory | 673216 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_rea dy_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv _core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_handler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=167645286 -assert nopost proc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac es/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 68.chip_sw_alert_handler_lpg_s leep_mode_alerts.167645286 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/68.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/68.chip_sw_all_escalation_resets.4254017977 |
| Short name | T741 |
| Test name | |
| Test status | |
| Simulation time | 5855050124 ps |
| CPU time | 431.72 seconds |
| Started | Aug 24 04:28:10 PM UTC 24 |
| Finished | Aug 24 04:35:27 PM UTC 24 |
| Peak memory | 676052 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv + sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4254017977 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_es calation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 68.chip_sw_all_escalation_resets.4254017977 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/68.chip_sw_all_escalation_resets/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/69.chip_sw_all_escalation_resets.2405148763 |
| Short name | T781 |
| Test name | |
| Test status | |
| Simulation time | 4416572616 ps |
| CPU time | 361.77 seconds |
| Started | Aug 24 04:28:22 PM UTC 24 |
| Finished | Aug 24 04:34:28 PM UTC 24 |
| Peak memory | 675440 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv + sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2405148763 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_es calation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 69.chip_sw_all_escalation_resets.2405148763 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/69.chip_sw_all_escalation_resets/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/7.chip_sw_alert_handler_lpg_sleep_mode_alerts.1243056365 |
| Short name | T757 |
| Test name | |
| Test status | |
| Simulation time | 4059387112 ps |
| CPU time | 313.75 seconds |
| Started | Aug 24 03:35:17 PM UTC 24 |
| Finished | Aug 24 03:40:35 PM UTC 24 |
| Peak memory | 673508 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_rea dy_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv _core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_handler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1243056365 -assert nopos tproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.chip_sw_alert_handler_lpg_s leep_mode_alerts.1243056365 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/7.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/7.chip_sw_all_escalation_resets.1148209441 |
| Short name | T686 |
| Test name | |
| Test status | |
| Simulation time | 5477921856 ps |
| CPU time | 338.55 seconds |
| Started | Aug 24 03:34:07 PM UTC 24 |
| Finished | Aug 24 03:39:50 PM UTC 24 |
| Peak memory | 675204 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv + sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1148209441 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_es calation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.chip_sw_all_escalation_resets.1148209441 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/7.chip_sw_all_escalation_resets/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/7.chip_sw_csrng_edn_concurrency.1342294731 |
| Short name | T1329 |
| Test name | |
| Test status | |
| Simulation time | 16761170810 ps |
| CPU time | 3110.45 seconds |
| Started | Aug 24 03:35:29 PM UTC 24 |
| Finished | Aug 24 04:27:53 PM UTC 24 |
| Peak memory | 629796 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=140_000_000 +rng_srate_value_min=15 +rng _srate_value_max=20 +accelerate_cold_power_up_time=3 +accelerate_regulators_power_up_time=2 +sw_build_device=sim_dv +sw_images=csrng_edn_concurren cy_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/t ools/sim.tcl +ntb_random_seed=1342294731 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null - cm_name 7.chip_sw_csrng_edn_concurrency.1342294731 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/7.chip_sw_csrng_edn_concurrency/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/7.chip_sw_lc_ctrl_transition.36318549 |
| Short name | T1298 |
| Test name | |
| Test status | |
| Simulation time | 5657233794 ps |
| CPU time | 309.99 seconds |
| Started | Aug 24 03:34:54 PM UTC 24 |
| Finished | Aug 24 03:40:09 PM UTC 24 |
| Peak memory | 639316 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=lc_ctrl_transition_test:1 :new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim. tcl +ntb_random_seed=36318549 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_ctrl_transition_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/nul l -cm_name 7.chip_sw_lc_ctrl_transition.36318549 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/7.chip_sw_lc_ctrl_transition/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/7.chip_sw_uart_rand_baudrate.2855354198 |
| Short name | T1307 |
| Test name | |
| Test status | |
| Simulation time | 8306323006 ps |
| CPU time | 1009.68 seconds |
| Started | Aug 24 03:34:45 PM UTC 24 |
| Finished | Aug 24 03:51:46 PM UTC 24 |
| Peak memory | 637048 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=80_000_000 +calibrate_usb_clk=1 +sw_buil d_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2855354198 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_ uart_rand_baudrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.chip_sw_uart_rand_baudrate.2855354198 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/7.chip_sw_uart_rand_baudrate/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/70.chip_sw_alert_handler_lpg_sleep_mode_alerts.715194308 |
| Short name | T747 |
| Test name | |
| Test status | |
| Simulation time | 3684723878 ps |
| CPU time | 294.74 seconds |
| Started | Aug 24 04:28:11 PM UTC 24 |
| Finished | Aug 24 04:33:10 PM UTC 24 |
| Peak memory | 673416 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_rea dy_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv _core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_handler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=715194308 -assert nopost proc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac es/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 70.chip_sw_alert_handler_lpg_s leep_mode_alerts.715194308 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/70.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/70.chip_sw_all_escalation_resets.917100812 |
| Short name | T761 |
| Test name | |
| Test status | |
| Simulation time | 4648469260 ps |
| CPU time | 416.11 seconds |
| Started | Aug 24 04:28:10 PM UTC 24 |
| Finished | Aug 24 04:35:11 PM UTC 24 |
| Peak memory | 676016 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv + sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=917100812 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_esc alation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 70.chip_sw_all_escalation_resets.917100812 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/70.chip_sw_all_escalation_resets/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/71.chip_sw_alert_handler_lpg_sleep_mode_alerts.2470699943 |
| Short name | T287 |
| Test name | |
| Test status | |
| Simulation time | 3716163328 ps |
| CPU time | 277.33 seconds |
| Started | Aug 24 04:28:24 PM UTC 24 |
| Finished | Aug 24 04:33:06 PM UTC 24 |
| Peak memory | 673368 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_rea dy_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv _core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_handler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2470699943 -assert nopos tproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 71.chip_sw_alert_handler_lpg_ sleep_mode_alerts.2470699943 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/71.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/71.chip_sw_all_escalation_resets.2831409722 |
| Short name | T703 |
| Test name | |
| Test status | |
| Simulation time | 6105998768 ps |
| CPU time | 432.5 seconds |
| Started | Aug 24 04:28:25 PM UTC 24 |
| Finished | Aug 24 04:35:43 PM UTC 24 |
| Peak memory | 675916 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv + sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2831409722 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_es calation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 71.chip_sw_all_escalation_resets.2831409722 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/71.chip_sw_all_escalation_resets/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/72.chip_sw_all_escalation_resets.3973612986 |
| Short name | T740 |
| Test name | |
| Test status | |
| Simulation time | 4095544376 ps |
| CPU time | 333.16 seconds |
| Started | Aug 24 04:29:09 PM UTC 24 |
| Finished | Aug 24 04:34:46 PM UTC 24 |
| Peak memory | 675328 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv + sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3973612986 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_es calation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 72.chip_sw_all_escalation_resets.3973612986 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/72.chip_sw_all_escalation_resets/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/73.chip_sw_alert_handler_lpg_sleep_mode_alerts.1749799388 |
| Short name | T683 |
| Test name | |
| Test status | |
| Simulation time | 3700704078 ps |
| CPU time | 318.3 seconds |
| Started | Aug 24 04:30:06 PM UTC 24 |
| Finished | Aug 24 04:35:29 PM UTC 24 |
| Peak memory | 673220 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_rea dy_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv _core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_handler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1749799388 -assert nopos tproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 73.chip_sw_alert_handler_lpg_ sleep_mode_alerts.1749799388 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/73.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/73.chip_sw_all_escalation_resets.903419031 |
| Short name | T671 |
| Test name | |
| Test status | |
| Simulation time | 4219230138 ps |
| CPU time | 383.26 seconds |
| Started | Aug 24 04:29:42 PM UTC 24 |
| Finished | Aug 24 04:36:10 PM UTC 24 |
| Peak memory | 673776 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv + sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=903419031 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_esc alation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 73.chip_sw_all_escalation_resets.903419031 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/73.chip_sw_all_escalation_resets/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/74.chip_sw_all_escalation_resets.604067042 |
| Short name | T718 |
| Test name | |
| Test status | |
| Simulation time | 5221480228 ps |
| CPU time | 382.83 seconds |
| Started | Aug 24 04:30:34 PM UTC 24 |
| Finished | Aug 24 04:37:01 PM UTC 24 |
| Peak memory | 676092 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv + sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=604067042 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_esc alation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 74.chip_sw_all_escalation_resets.604067042 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/74.chip_sw_all_escalation_resets/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/76.chip_sw_alert_handler_lpg_sleep_mode_alerts.716314035 |
| Short name | T693 |
| Test name | |
| Test status | |
| Simulation time | 3119049984 ps |
| CPU time | 270.91 seconds |
| Started | Aug 24 04:31:40 PM UTC 24 |
| Finished | Aug 24 04:36:15 PM UTC 24 |
| Peak memory | 673276 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_rea dy_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv _core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_handler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=716314035 -assert nopost proc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac es/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 76.chip_sw_alert_handler_lpg_s leep_mode_alerts.716314035 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/76.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/76.chip_sw_all_escalation_resets.1647611563 |
| Short name | T753 |
| Test name | |
| Test status | |
| Simulation time | 5667051000 ps |
| CPU time | 455.66 seconds |
| Started | Aug 24 04:31:39 PM UTC 24 |
| Finished | Aug 24 04:39:20 PM UTC 24 |
| Peak memory | 673396 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv + sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1647611563 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_es calation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 76.chip_sw_all_escalation_resets.1647611563 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/76.chip_sw_all_escalation_resets/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/77.chip_sw_alert_handler_lpg_sleep_mode_alerts.2586444577 |
| Short name | T698 |
| Test name | |
| Test status | |
| Simulation time | 3745060494 ps |
| CPU time | 248.94 seconds |
| Started | Aug 24 04:31:38 PM UTC 24 |
| Finished | Aug 24 04:35:50 PM UTC 24 |
| Peak memory | 673208 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_rea dy_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv _core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_handler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2586444577 -assert nopos tproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 77.chip_sw_alert_handler_lpg_ sleep_mode_alerts.2586444577 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/77.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/77.chip_sw_all_escalation_resets.1776247634 |
| Short name | T1335 |
| Test name | |
| Test status | |
| Simulation time | 6069877056 ps |
| CPU time | 438.68 seconds |
| Started | Aug 24 04:31:32 PM UTC 24 |
| Finished | Aug 24 04:38:57 PM UTC 24 |
| Peak memory | 638412 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv + sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1776247634 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_es calation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 77.chip_sw_all_escalation_resets.1776247634 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/77.chip_sw_all_escalation_resets/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/78.chip_sw_alert_handler_lpg_sleep_mode_alerts.3861271096 |
| Short name | T706 |
| Test name | |
| Test status | |
| Simulation time | 4058853496 ps |
| CPU time | 255.07 seconds |
| Started | Aug 24 04:32:40 PM UTC 24 |
| Finished | Aug 24 04:36:58 PM UTC 24 |
| Peak memory | 673208 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_rea dy_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv _core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_handler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3861271096 -assert nopos tproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 78.chip_sw_alert_handler_lpg_ sleep_mode_alerts.3861271096 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/78.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/78.chip_sw_all_escalation_resets.2960461907 |
| Short name | T1336 |
| Test name | |
| Test status | |
| Simulation time | 4399388200 ps |
| CPU time | 407.52 seconds |
| Started | Aug 24 04:32:08 PM UTC 24 |
| Finished | Aug 24 04:39:00 PM UTC 24 |
| Peak memory | 675448 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv + sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2960461907 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_es calation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 78.chip_sw_all_escalation_resets.2960461907 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/78.chip_sw_all_escalation_resets/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/79.chip_sw_alert_handler_lpg_sleep_mode_alerts.4191386502 |
| Short name | T755 |
| Test name | |
| Test status | |
| Simulation time | 3673555176 ps |
| CPU time | 238 seconds |
| Started | Aug 24 04:34:06 PM UTC 24 |
| Finished | Aug 24 04:38:08 PM UTC 24 |
| Peak memory | 673208 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_rea dy_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv _core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_handler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4191386502 -assert nopos tproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 79.chip_sw_alert_handler_lpg_ sleep_mode_alerts.4191386502 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/79.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/79.chip_sw_all_escalation_resets.1825370467 |
| Short name | T276 |
| Test name | |
| Test status | |
| Simulation time | 4270892514 ps |
| CPU time | 334.98 seconds |
| Started | Aug 24 04:33:00 PM UTC 24 |
| Finished | Aug 24 04:38:40 PM UTC 24 |
| Peak memory | 675280 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv + sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1825370467 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_es calation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 79.chip_sw_all_escalation_resets.1825370467 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/79.chip_sw_all_escalation_resets/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/8.chip_sw_all_escalation_resets.3812758255 |
| Short name | T381 |
| Test name | |
| Test status | |
| Simulation time | 5569998380 ps |
| CPU time | 436.77 seconds |
| Started | Aug 24 03:35:55 PM UTC 24 |
| Finished | Aug 24 03:43:18 PM UTC 24 |
| Peak memory | 675216 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv + sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3812758255 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_es calation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.chip_sw_all_escalation_resets.3812758255 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/8.chip_sw_all_escalation_resets/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/8.chip_sw_csrng_edn_concurrency.1607290467 |
| Short name | T1332 |
| Test name | |
| Test status | |
| Simulation time | 20295049720 ps |
| CPU time | 3429.78 seconds |
| Started | Aug 24 03:36:38 PM UTC 24 |
| Finished | Aug 24 04:34:23 PM UTC 24 |
| Peak memory | 629800 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=140_000_000 +rng_srate_value_min=15 +rng _srate_value_max=20 +accelerate_cold_power_up_time=3 +accelerate_regulators_power_up_time=2 +sw_build_device=sim_dv +sw_images=csrng_edn_concurren cy_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/t ools/sim.tcl +ntb_random_seed=1607290467 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null - cm_name 8.chip_sw_csrng_edn_concurrency.1607290467 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/8.chip_sw_csrng_edn_concurrency/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/8.chip_sw_lc_ctrl_transition.1099423496 |
| Short name | T1300 |
| Test name | |
| Test status | |
| Simulation time | 8449589673 ps |
| CPU time | 442.19 seconds |
| Started | Aug 24 03:36:22 PM UTC 24 |
| Finished | Aug 24 03:43:50 PM UTC 24 |
| Peak memory | 639128 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=lc_ctrl_transition_test:1 :new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim. tcl +ntb_random_seed=1099423496 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_ctrl_transition_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/n ull -cm_name 8.chip_sw_lc_ctrl_transition.1099423496 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/8.chip_sw_lc_ctrl_transition/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/8.chip_sw_uart_rand_baudrate.1187139424 |
| Short name | T291 |
| Test name | |
| Test status | |
| Simulation time | 12912094954 ps |
| CPU time | 1875.61 seconds |
| Started | Aug 24 03:36:22 PM UTC 24 |
| Finished | Aug 24 04:07:58 PM UTC 24 |
| Peak memory | 639988 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=80_000_000 +calibrate_usb_clk=1 +sw_buil d_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1187139424 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_ uart_rand_baudrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.chip_sw_uart_rand_baudrate.1187139424 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/8.chip_sw_uart_rand_baudrate/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/80.chip_sw_alert_handler_lpg_sleep_mode_alerts.2151003359 |
| Short name | T684 |
| Test name | |
| Test status | |
| Simulation time | 3938720526 ps |
| CPU time | 267 seconds |
| Started | Aug 24 04:34:04 PM UTC 24 |
| Finished | Aug 24 04:38:34 PM UTC 24 |
| Peak memory | 673472 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_rea dy_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv _core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_handler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2151003359 -assert nopos tproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 80.chip_sw_alert_handler_lpg_ sleep_mode_alerts.2151003359 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/80.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/80.chip_sw_all_escalation_resets.2123021211 |
| Short name | T1337 |
| Test name | |
| Test status | |
| Simulation time | 5762356736 ps |
| CPU time | 459.29 seconds |
| Started | Aug 24 04:34:05 PM UTC 24 |
| Finished | Aug 24 04:41:50 PM UTC 24 |
| Peak memory | 640184 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv + sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2123021211 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_es calation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 80.chip_sw_all_escalation_resets.2123021211 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/80.chip_sw_all_escalation_resets/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/81.chip_sw_alert_handler_lpg_sleep_mode_alerts.176388028 |
| Short name | T715 |
| Test name | |
| Test status | |
| Simulation time | 4056813800 ps |
| CPU time | 260 seconds |
| Started | Aug 24 04:34:07 PM UTC 24 |
| Finished | Aug 24 04:38:30 PM UTC 24 |
| Peak memory | 673280 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_rea dy_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv _core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_handler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=176388028 -assert nopost proc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac es/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 81.chip_sw_alert_handler_lpg_s leep_mode_alerts.176388028 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/81.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/81.chip_sw_all_escalation_resets.925273160 |
| Short name | T726 |
| Test name | |
| Test status | |
| Simulation time | 4310207100 ps |
| CPU time | 353.51 seconds |
| Started | Aug 24 04:34:06 PM UTC 24 |
| Finished | Aug 24 04:40:04 PM UTC 24 |
| Peak memory | 675260 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv + sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=925273160 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_esc alation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 81.chip_sw_all_escalation_resets.925273160 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/81.chip_sw_all_escalation_resets/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/82.chip_sw_alert_handler_lpg_sleep_mode_alerts.852626462 |
| Short name | T699 |
| Test name | |
| Test status | |
| Simulation time | 3968407202 ps |
| CPU time | 250.33 seconds |
| Started | Aug 24 04:34:57 PM UTC 24 |
| Finished | Aug 24 04:39:11 PM UTC 24 |
| Peak memory | 673212 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_rea dy_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv _core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_handler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=852626462 -assert nopost proc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac es/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 82.chip_sw_alert_handler_lpg_s leep_mode_alerts.852626462 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/82.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/82.chip_sw_all_escalation_resets.2772701826 |
| Short name | T666 |
| Test name | |
| Test status | |
| Simulation time | 4907591890 ps |
| CPU time | 494.17 seconds |
| Started | Aug 24 04:34:29 PM UTC 24 |
| Finished | Aug 24 04:42:50 PM UTC 24 |
| Peak memory | 675828 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv + sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2772701826 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_es calation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 82.chip_sw_all_escalation_resets.2772701826 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/82.chip_sw_all_escalation_resets/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/83.chip_sw_alert_handler_lpg_sleep_mode_alerts.3687036068 |
| Short name | T1334 |
| Test name | |
| Test status | |
| Simulation time | 3261102524 ps |
| CPU time | 218.45 seconds |
| Started | Aug 24 04:34:58 PM UTC 24 |
| Finished | Aug 24 04:38:40 PM UTC 24 |
| Peak memory | 673524 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_rea dy_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv _core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_handler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3687036068 -assert nopos tproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 83.chip_sw_alert_handler_lpg_ sleep_mode_alerts.3687036068 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/83.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/84.chip_sw_alert_handler_lpg_sleep_mode_alerts.3982443009 |
| Short name | T737 |
| Test name | |
| Test status | |
| Simulation time | 3497683240 ps |
| CPU time | 249.13 seconds |
| Started | Aug 24 04:35:35 PM UTC 24 |
| Finished | Aug 24 04:39:48 PM UTC 24 |
| Peak memory | 673204 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_rea dy_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv _core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_handler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3982443009 -assert nopos tproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 84.chip_sw_alert_handler_lpg_ sleep_mode_alerts.3982443009 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/84.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/84.chip_sw_all_escalation_resets.3609052144 |
| Short name | T113 |
| Test name | |
| Test status | |
| Simulation time | 4213811344 ps |
| CPU time | 319.46 seconds |
| Started | Aug 24 04:35:12 PM UTC 24 |
| Finished | Aug 24 04:40:35 PM UTC 24 |
| Peak memory | 675300 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv + sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3609052144 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_es calation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 84.chip_sw_all_escalation_resets.3609052144 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/84.chip_sw_all_escalation_resets/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/85.chip_sw_all_escalation_resets.3998610853 |
| Short name | T1338 |
| Test name | |
| Test status | |
| Simulation time | 4841170552 ps |
| CPU time | 363 seconds |
| Started | Aug 24 04:36:36 PM UTC 24 |
| Finished | Aug 24 04:42:44 PM UTC 24 |
| Peak memory | 675444 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv + sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3998610853 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_es calation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 85.chip_sw_all_escalation_resets.3998610853 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/85.chip_sw_all_escalation_resets/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/86.chip_sw_all_escalation_resets.3856535478 |
| Short name | T707 |
| Test name | |
| Test status | |
| Simulation time | 5861608568 ps |
| CPU time | 489.48 seconds |
| Started | Aug 24 04:37:01 PM UTC 24 |
| Finished | Aug 24 04:45:17 PM UTC 24 |
| Peak memory | 675944 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv + sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3856535478 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_es calation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 86.chip_sw_all_escalation_resets.3856535478 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/86.chip_sw_all_escalation_resets/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/87.chip_sw_alert_handler_lpg_sleep_mode_alerts.2063133939 |
| Short name | T694 |
| Test name | |
| Test status | |
| Simulation time | 3308801376 ps |
| CPU time | 255.54 seconds |
| Started | Aug 24 04:37:00 PM UTC 24 |
| Finished | Aug 24 04:41:19 PM UTC 24 |
| Peak memory | 673460 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_rea dy_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv _core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_handler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2063133939 -assert nopos tproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 87.chip_sw_alert_handler_lpg_ sleep_mode_alerts.2063133939 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/87.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/87.chip_sw_all_escalation_resets.2650556735 |
| Short name | T114 |
| Test name | |
| Test status | |
| Simulation time | 4478617228 ps |
| CPU time | 362.36 seconds |
| Started | Aug 24 04:37:01 PM UTC 24 |
| Finished | Aug 24 04:43:07 PM UTC 24 |
| Peak memory | 676184 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv + sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2650556735 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_es calation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 87.chip_sw_all_escalation_resets.2650556735 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/87.chip_sw_all_escalation_resets/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/88.chip_sw_alert_handler_lpg_sleep_mode_alerts.2642279687 |
| Short name | T717 |
| Test name | |
| Test status | |
| Simulation time | 3800422992 ps |
| CPU time | 262.12 seconds |
| Started | Aug 24 04:37:02 PM UTC 24 |
| Finished | Aug 24 04:41:28 PM UTC 24 |
| Peak memory | 673340 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_rea dy_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv _core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_handler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2642279687 -assert nopos tproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 88.chip_sw_alert_handler_lpg_ sleep_mode_alerts.2642279687 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/88.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/89.chip_sw_alert_handler_lpg_sleep_mode_alerts.1522244701 |
| Short name | T727 |
| Test name | |
| Test status | |
| Simulation time | 3885385590 ps |
| CPU time | 284.12 seconds |
| Started | Aug 24 04:37:31 PM UTC 24 |
| Finished | Aug 24 04:42:19 PM UTC 24 |
| Peak memory | 673464 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_rea dy_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv _core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_handler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1522244701 -assert nopos tproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 89.chip_sw_alert_handler_lpg_ sleep_mode_alerts.1522244701 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/89.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/89.chip_sw_all_escalation_resets.397846540 |
| Short name | T751 |
| Test name | |
| Test status | |
| Simulation time | 4856834144 ps |
| CPU time | 439.92 seconds |
| Started | Aug 24 04:37:05 PM UTC 24 |
| Finished | Aug 24 04:44:30 PM UTC 24 |
| Peak memory | 675336 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv + sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=397846540 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_esc alation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 89.chip_sw_all_escalation_resets.397846540 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/89.chip_sw_all_escalation_resets/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/9.chip_sw_alert_handler_lpg_sleep_mode_alerts.3279622681 |
| Short name | T776 |
| Test name | |
| Test status | |
| Simulation time | 4374703168 ps |
| CPU time | 306.08 seconds |
| Started | Aug 24 03:38:11 PM UTC 24 |
| Finished | Aug 24 03:43:21 PM UTC 24 |
| Peak memory | 673212 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_rea dy_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv _core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_handler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3279622681 -assert nopos tproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.chip_sw_alert_handler_lpg_s leep_mode_alerts.3279622681 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/9.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/9.chip_sw_all_escalation_resets.2457006683 |
| Short name | T202 |
| Test name | |
| Test status | |
| Simulation time | 4871250050 ps |
| CPU time | 361.6 seconds |
| Started | Aug 24 03:36:42 PM UTC 24 |
| Finished | Aug 24 03:42:48 PM UTC 24 |
| Peak memory | 637528 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv + sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2457006683 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_es calation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.chip_sw_all_escalation_resets.2457006683 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/9.chip_sw_all_escalation_resets/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/9.chip_sw_csrng_edn_concurrency.2080508563 |
| Short name | T1323 |
| Test name | |
| Test status | |
| Simulation time | 12973872008 ps |
| CPU time | 2604.22 seconds |
| Started | Aug 24 03:38:10 PM UTC 24 |
| Finished | Aug 24 04:22:01 PM UTC 24 |
| Peak memory | 629800 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=140_000_000 +rng_srate_value_min=15 +rng _srate_value_max=20 +accelerate_cold_power_up_time=3 +accelerate_regulators_power_up_time=2 +sw_build_device=sim_dv +sw_images=csrng_edn_concurren cy_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/t ools/sim.tcl +ntb_random_seed=2080508563 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null - cm_name 9.chip_sw_csrng_edn_concurrency.2080508563 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/9.chip_sw_csrng_edn_concurrency/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/9.chip_sw_lc_ctrl_transition.450619995 |
| Short name | T1304 |
| Test name | |
| Test status | |
| Simulation time | 11985981806 ps |
| CPU time | 518.11 seconds |
| Started | Aug 24 03:37:12 PM UTC 24 |
| Finished | Aug 24 03:45:57 PM UTC 24 |
| Peak memory | 639316 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=lc_ctrl_transition_test:1 :new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim. tcl +ntb_random_seed=450619995 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_ctrl_transition_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/nu ll -cm_name 9.chip_sw_lc_ctrl_transition.450619995 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/9.chip_sw_lc_ctrl_transition/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/9.chip_sw_uart_rand_baudrate.2821548902 |
| Short name | T1301 |
| Test name | |
| Test status | |
| Simulation time | 4653034330 ps |
| CPU time | 423.32 seconds |
| Started | Aug 24 03:36:42 PM UTC 24 |
| Finished | Aug 24 03:43:51 PM UTC 24 |
| Peak memory | 636872 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=80_000_000 +calibrate_usb_clk=1 +sw_buil d_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2821548902 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_ uart_rand_baudrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.chip_sw_uart_rand_baudrate.2821548902 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/9.chip_sw_uart_rand_baudrate/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/91.chip_sw_all_escalation_resets.2167387569 |
| Short name | T115 |
| Test name | |
| Test status | |
| Simulation time | 4063919202 ps |
| CPU time | 306.52 seconds |
| Started | Aug 24 04:38:32 PM UTC 24 |
| Finished | Aug 24 04:43:43 PM UTC 24 |
| Peak memory | 675296 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv + sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2167387569 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_es calation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 91.chip_sw_all_escalation_resets.2167387569 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/91.chip_sw_all_escalation_resets/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/92.chip_sw_all_escalation_resets.1623400976 |
| Short name | T667 |
| Test name | |
| Test status | |
| Simulation time | 4243537600 ps |
| CPU time | 327.22 seconds |
| Started | Aug 24 04:39:54 PM UTC 24 |
| Finished | Aug 24 04:45:25 PM UTC 24 |
| Peak memory | 675196 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv + sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1623400976 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_es calation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 92.chip_sw_all_escalation_resets.1623400976 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/92.chip_sw_all_escalation_resets/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/93.chip_sw_all_escalation_resets.1351210041 |
| Short name | T720 |
| Test name | |
| Test status | |
| Simulation time | 5528831576 ps |
| CPU time | 376.06 seconds |
| Started | Aug 24 04:39:51 PM UTC 24 |
| Finished | Aug 24 04:46:11 PM UTC 24 |
| Peak memory | 675372 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv + sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1351210041 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_es calation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 93.chip_sw_all_escalation_resets.1351210041 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/93.chip_sw_all_escalation_resets/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/94.chip_sw_all_escalation_resets.1931622397 |
| Short name | T259 |
| Test name | |
| Test status | |
| Simulation time | 5760588430 ps |
| CPU time | 387.8 seconds |
| Started | Aug 24 04:39:57 PM UTC 24 |
| Finished | Aug 24 04:46:29 PM UTC 24 |
| Peak memory | 626844 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv + sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1931622397 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_es calation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 94.chip_sw_all_escalation_resets.1931622397 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/94.chip_sw_all_escalation_resets/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/95.chip_sw_all_escalation_resets.3803770928 |
| Short name | T350 |
| Test name | |
| Test status | |
| Simulation time | 6157963426 ps |
| CPU time | 435.23 seconds |
| Started | Aug 24 04:39:49 PM UTC 24 |
| Finished | Aug 24 04:47:10 PM UTC 24 |
| Peak memory | 676152 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv + sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3803770928 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_es calation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 95.chip_sw_all_escalation_resets.3803770928 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/95.chip_sw_all_escalation_resets/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/96.chip_sw_all_escalation_resets.2203366466 |
| Short name | T748 |
| Test name | |
| Test status | |
| Simulation time | 5898424232 ps |
| CPU time | 380.1 seconds |
| Started | Aug 24 04:39:56 PM UTC 24 |
| Finished | Aug 24 04:46:21 PM UTC 24 |
| Peak memory | 675200 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv + sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2203366466 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_es calation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 96.chip_sw_all_escalation_resets.2203366466 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/96.chip_sw_all_escalation_resets/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/97.chip_sw_all_escalation_resets.3380248194 |
| Short name | T260 |
| Test name | |
| Test status | |
| Simulation time | 5643153400 ps |
| CPU time | 395.39 seconds |
| Started | Aug 24 04:40:01 PM UTC 24 |
| Finished | Aug 24 04:46:41 PM UTC 24 |
| Peak memory | 627192 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv + sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3380248194 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_es calation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 97.chip_sw_all_escalation_resets.3380248194 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/97.chip_sw_all_escalation_resets/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/98.chip_sw_all_escalation_resets.3686751628 |
| Short name | T764 |
| Test name | |
| Test status | |
| Simulation time | 5361476748 ps |
| CPU time | 327.03 seconds |
| Started | Aug 24 04:40:00 PM UTC 24 |
| Finished | Aug 24 04:45:31 PM UTC 24 |
| Peak memory | 675332 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv + sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3686751628 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_es calation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 98.chip_sw_all_escalation_resets.3686751628 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/98.chip_sw_all_escalation_resets/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/99.chip_sw_all_escalation_resets.1002550756 |
| Short name | T672 |
| Test name | |
| Test status | |
| Simulation time | 5635471538 ps |
| CPU time | 341.09 seconds |
| Started | Aug 24 04:40:01 PM UTC 24 |
| Finished | Aug 24 04:45:46 PM UTC 24 |
| Peak memory | 675504 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv + sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1002550756 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_es calation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 99.chip_sw_all_escalation_resets.1002550756 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/99.chip_sw_all_escalation_resets/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/pad_ctrl_test_mode/2.chip_padctrl_attributes.288283935 |
| Short name | T237 |
| Test name | |
| Test status | |
| Simulation time | 4741959592 ps |
| CPU time | 190.02 seconds |
| Started | Aug 24 07:33:25 AM UTC 24 |
| Finished | Aug 24 07:36:38 AM UTC 24 |
| Peak memory | 657332 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/pad_ctrl_test_mode/simv +use_otp_image=OtpTypeLcStProd +stub_cpu=1 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2882839 35 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_padctrl_attributes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/pad_ctrl_test_mode.vdb -cm_log /dev/null -cm_name 2.chip_p adctrl_attributes.288283935 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/2.chip_padctrl_attributes/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/pad_ctrl_test_mode/3.chip_padctrl_attributes.3607440041 |
| Short name | T234 |
| Test name | |
| Test status | |
| Simulation time | 6109230384 ps |
| CPU time | 260.93 seconds |
| Started | Aug 24 07:33:26 AM UTC 24 |
| Finished | Aug 24 07:37:51 AM UTC 24 |
| Peak memory | 673720 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/pad_ctrl_test_mode/simv +use_otp_image=OtpTypeLcStProd +stub_cpu=1 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3607440 041 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_padctrl_attributes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/pad_ctrl_test_mode.vdb -cm_log /dev/null -cm_name 3.chip_ padctrl_attributes.3607440041 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/3.chip_padctrl_attributes/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/pad_ctrl_test_mode/4.chip_padctrl_attributes.3498004107 |
| Short name | T230 |
| Test name | |
| Test status | |
| Simulation time | 5168816928 ps |
| CPU time | 169.7 seconds |
| Started | Aug 24 07:33:28 AM UTC 24 |
| Finished | Aug 24 07:36:21 AM UTC 24 |
| Peak memory | 659640 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/pad_ctrl_test_mode/simv +use_otp_image=OtpTypeLcStProd +stub_cpu=1 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3498004 107 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_padctrl_attributes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/pad_ctrl_test_mode.vdb -cm_log /dev/null -cm_name 4.chip_ padctrl_attributes.3498004107 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/4.chip_padctrl_attributes/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/pad_ctrl_test_mode/5.chip_padctrl_attributes.1093319605 |
| Short name | T25 |
| Test name | |
| Test status | |
| Simulation time | 5587269352 ps |
| CPU time | 164.42 seconds |
| Started | Aug 24 07:33:30 AM UTC 24 |
| Finished | Aug 24 07:36:18 AM UTC 24 |
| Peak memory | 659384 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/pad_ctrl_test_mode/simv +use_otp_image=OtpTypeLcStProd +stub_cpu=1 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1093319 605 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_padctrl_attributes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/pad_ctrl_test_mode.vdb -cm_log /dev/null -cm_name 5.chip_ padctrl_attributes.1093319605 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/5.chip_padctrl_attributes/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/pad_ctrl_test_mode/6.chip_padctrl_attributes.3418485337 |
| Short name | T231 |
| Test name | |
| Test status | |
| Simulation time | 4821886620 ps |
| CPU time | 140.19 seconds |
| Started | Aug 24 07:34:12 AM UTC 24 |
| Finished | Aug 24 07:36:34 AM UTC 24 |
| Peak memory | 657336 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/pad_ctrl_test_mode/simv +use_otp_image=OtpTypeLcStProd +stub_cpu=1 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3418485 337 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_padctrl_attributes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/pad_ctrl_test_mode.vdb -cm_log /dev/null -cm_name 6.chip_ padctrl_attributes.3418485337 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/6.chip_padctrl_attributes/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/pad_ctrl_test_mode/7.chip_padctrl_attributes.542264375 |
| Short name | T233 |
| Test name | |
| Test status | |
| Simulation time | 5576816220 ps |
| CPU time | 178.25 seconds |
| Started | Aug 24 07:34:15 AM UTC 24 |
| Finished | Aug 24 07:37:16 AM UTC 24 |
| Peak memory | 657588 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/pad_ctrl_test_mode/simv +use_otp_image=OtpTypeLcStProd +stub_cpu=1 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=5422643 75 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_padctrl_attributes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/pad_ctrl_test_mode.vdb -cm_log /dev/null -cm_name 7.chip_p adctrl_attributes.542264375 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/7.chip_padctrl_attributes/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/pad_ctrl_test_mode/8.chip_padctrl_attributes.1581388133 |
| Short name | T232 |
| Test name | |
| Test status | |
| Simulation time | 4957753289 ps |
| CPU time | 153.96 seconds |
| Started | Aug 24 07:34:16 AM UTC 24 |
| Finished | Aug 24 07:36:53 AM UTC 24 |
| Peak memory | 657336 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/pad_ctrl_test_mode/simv +use_otp_image=OtpTypeLcStProd +stub_cpu=1 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1581388 133 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_padctrl_attributes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/pad_ctrl_test_mode.vdb -cm_log /dev/null -cm_name 8.chip_ padctrl_attributes.1581388133 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/8.chip_padctrl_attributes/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/pad_ctrl_test_mode/9.chip_padctrl_attributes.1651310400 |
| Short name | T235 |
| Test name | |
| Test status | |
| Simulation time | 4475184248 ps |
| CPU time | 204.7 seconds |
| Started | Aug 24 07:34:35 AM UTC 24 |
| Finished | Aug 24 07:38:03 AM UTC 24 |
| Peak memory | 673720 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/pad_ctrl_test_mode/simv +use_otp_image=OtpTypeLcStProd +stub_cpu=1 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1651310 400 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_padctrl_attributes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/pad_ctrl_test_mode.vdb -cm_log /dev/null -cm_name 9.chip_ padctrl_attributes.1651310400 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/9.chip_padctrl_attributes/latest |
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