| T809 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/10.xbar_access_same_device.794990715 |
|
|
Aug 24 04:30:27 AM UTC 24 |
Aug 24 04:31:17 AM UTC 24 |
1402057575 ps |
| T1407 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/10.xbar_error_random.1749689207 |
|
|
Aug 24 04:30:45 AM UTC 24 |
Aug 24 04:31:35 AM UTC 24 |
1818378308 ps |
| T508 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/7.xbar_random_large_delays.2609793722 |
|
|
Aug 24 04:19:37 AM UTC 24 |
Aug 24 04:31:36 AM UTC 24 |
89254402489 ps |
| T1408 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/10.xbar_stress_all_with_error.3386627302 |
|
|
Aug 24 04:31:18 AM UTC 24 |
Aug 24 04:31:37 AM UTC 24 |
205573287 ps |
| T478 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/10.xbar_stress_all.2982594612 |
|
|
Aug 24 04:31:12 AM UTC 24 |
Aug 24 04:31:56 AM UTC 24 |
1373074623 ps |
| T1409 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/11.xbar_smoke.3168223104 |
|
|
Aug 24 04:31:51 AM UTC 24 |
Aug 24 04:32:01 AM UTC 24 |
235794005 ps |
| T1410 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/11.xbar_smoke_zero_delays.2647057013 |
|
|
Aug 24 04:32:11 AM UTC 24 |
Aug 24 04:32:17 AM UTC 24 |
50637364 ps |
| T1411 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/8.chip_csr_rw.1616430476 |
|
|
Aug 24 04:24:06 AM UTC 24 |
Aug 24 04:32:32 AM UTC 24 |
5621404985 ps |
| T1412 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/11.xbar_smoke_slow_rsp.4070204691 |
|
|
Aug 24 04:32:31 AM UTC 24 |
Aug 24 04:33:13 AM UTC 24 |
3288697272 ps |
| T854 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/10.xbar_stress_all_with_reset_error.3457829975 |
|
|
Aug 24 04:31:18 AM UTC 24 |
Aug 24 04:33:25 AM UTC 24 |
2677726979 ps |
| T487 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/11.xbar_random.1632846964 |
|
|
Aug 24 04:32:46 AM UTC 24 |
Aug 24 04:33:26 AM UTC 24 |
548414935 ps |
| T574 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/11.chip_tl_errors.1193207417 |
|
|
Aug 24 04:31:50 AM UTC 24 |
Aug 24 04:33:27 AM UTC 24 |
2499950454 ps |
| T529 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/11.xbar_smoke_large_delays.260754209 |
|
|
Aug 24 04:32:15 AM UTC 24 |
Aug 24 04:33:44 AM UTC 24 |
10085189521 ps |
| T1413 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/11.xbar_random_zero_delays.719783743 |
|
|
Aug 24 04:33:27 AM UTC 24 |
Aug 24 04:33:47 AM UTC 24 |
242381635 ps |
| T540 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/11.xbar_same_source.3097456032 |
|
|
Aug 24 04:34:01 AM UTC 24 |
Aug 24 04:34:34 AM UTC 24 |
582674471 ps |
| T785 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/11.xbar_access_same_device.4122257716 |
|
|
Aug 24 04:33:42 AM UTC 24 |
Aug 24 04:34:44 AM UTC 24 |
2174002838 ps |
| T1414 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/11.xbar_error_random.1709272691 |
|
|
Aug 24 04:34:49 AM UTC 24 |
Aug 24 04:34:57 AM UTC 24 |
71510005 ps |
| T1415 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/11.xbar_unmapped_addr.1885232767 |
|
|
Aug 24 04:34:58 AM UTC 24 |
Aug 24 04:35:11 AM UTC 24 |
299943299 ps |
| T1416 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/11.xbar_error_and_unmapped_addr.2720632912 |
|
|
Aug 24 04:35:11 AM UTC 24 |
Aug 24 04:35:30 AM UTC 24 |
199162404 ps |
| T813 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/9.xbar_stress_all_with_error.3469664778 |
|
|
Aug 24 04:27:45 AM UTC 24 |
Aug 24 04:35:39 AM UTC 24 |
16992823545 ps |
| T1417 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/11.xbar_random_slow_rsp.2276377960 |
|
|
Aug 24 04:33:40 AM UTC 24 |
Aug 24 04:35:49 AM UTC 24 |
10644713943 ps |
| T571 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/9.xbar_random_slow_rsp.529564750 |
|
|
Aug 24 04:26:31 AM UTC 24 |
Aug 24 04:36:03 AM UTC 24 |
45480423668 ps |
| T507 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/9.xbar_stress_all_with_rand_reset.3651682337 |
|
|
Aug 24 04:27:40 AM UTC 24 |
Aug 24 04:36:18 AM UTC 24 |
15280801353 ps |
| T526 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/10.xbar_stress_all_with_rand_reset.3295215824 |
|
|
Aug 24 04:31:16 AM UTC 24 |
Aug 24 04:36:19 AM UTC 24 |
2949788850 ps |
| T1418 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/9.chip_csr_rw.3498805748 |
|
|
Aug 24 04:27:50 AM UTC 24 |
Aug 24 04:36:22 AM UTC 24 |
6827348664 ps |
| T1419 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/10.chip_csr_rw.404307805 |
|
|
Aug 24 04:31:20 AM UTC 24 |
Aug 24 04:37:59 AM UTC 24 |
5965474264 ps |
| T1420 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/12.xbar_smoke.448010195 |
|
|
Aug 24 04:38:13 AM UTC 24 |
Aug 24 04:38:22 AM UTC 24 |
229460012 ps |
| T515 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/10.xbar_random_large_delays.301433284 |
|
|
Aug 24 04:30:11 AM UTC 24 |
Aug 24 04:38:31 AM UTC 24 |
61009910940 ps |
| T596 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/11.xbar_stress_all.2868338961 |
|
|
Aug 24 04:35:26 AM UTC 24 |
Aug 24 04:38:39 AM UTC 24 |
7058792502 ps |
| T1421 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/12.xbar_smoke_zero_delays.1031942112 |
|
|
Aug 24 04:38:36 AM UTC 24 |
Aug 24 04:38:43 AM UTC 24 |
56000587 ps |
| T1422 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/9.chip_csr_mem_rw_with_rand_reset.1671915989 |
|
|
Aug 24 04:27:54 AM UTC 24 |
Aug 24 04:39:06 AM UTC 24 |
9108937250 ps |
| T1423 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/12.xbar_random.1588190419 |
|
|
Aug 24 04:38:57 AM UTC 24 |
Aug 24 04:39:13 AM UTC 24 |
197190311 ps |
| T1424 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/11.xbar_stress_all_with_error.620557906 |
|
|
Aug 24 04:35:53 AM UTC 24 |
Aug 24 04:39:17 AM UTC 24 |
8894812704 ps |
| T407 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/8.chip_same_csr_outstanding.2791586889 |
|
|
Aug 24 04:22:03 AM UTC 24 |
Aug 24 04:39:30 AM UTC 24 |
15222259758 ps |
| T832 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/11.xbar_stress_all_with_reset_error.867782161 |
|
|
Aug 24 04:36:03 AM UTC 24 |
Aug 24 04:39:30 AM UTC 24 |
3455174579 ps |
| T476 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/12.xbar_smoke_large_delays.2423068147 |
|
|
Aug 24 04:38:45 AM UTC 24 |
Aug 24 04:39:32 AM UTC 24 |
5332370179 ps |
| T1425 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/12.xbar_smoke_slow_rsp.621499104 |
|
|
Aug 24 04:38:53 AM UTC 24 |
Aug 24 04:39:42 AM UTC 24 |
3839548456 ps |
| T562 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/12.chip_tl_errors.2551946442 |
|
|
Aug 24 04:36:35 AM UTC 24 |
Aug 24 04:39:46 AM UTC 24 |
4373486406 ps |
| T1426 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/11.xbar_random_large_delays.1060008677 |
|
|
Aug 24 04:33:39 AM UTC 24 |
Aug 24 04:40:01 AM UTC 24 |
45487327196 ps |
| T1427 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/12.xbar_random_zero_delays.2900556246 |
|
|
Aug 24 04:39:21 AM UTC 24 |
Aug 24 04:40:01 AM UTC 24 |
591097736 ps |
| T588 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/12.xbar_same_source.3217715455 |
|
|
Aug 24 04:39:45 AM UTC 24 |
Aug 24 04:40:06 AM UTC 24 |
347042528 ps |
| T789 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/12.xbar_access_same_device.951194355 |
|
|
Aug 24 04:39:43 AM UTC 24 |
Aug 24 04:40:14 AM UTC 24 |
1158356115 ps |
| T1428 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/12.xbar_random_slow_rsp.138391158 |
|
|
Aug 24 04:39:31 AM UTC 24 |
Aug 24 04:40:17 AM UTC 24 |
3566957936 ps |
| T1429 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/12.xbar_unmapped_addr.839678609 |
|
|
Aug 24 04:40:01 AM UTC 24 |
Aug 24 04:40:18 AM UTC 24 |
418800407 ps |
| T1430 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/12.xbar_error_random.1770267029 |
|
|
Aug 24 04:39:57 AM UTC 24 |
Aug 24 04:40:31 AM UTC 24 |
1310651667 ps |
| T1431 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/12.xbar_error_and_unmapped_addr.3461891868 |
|
|
Aug 24 04:40:15 AM UTC 24 |
Aug 24 04:40:49 AM UTC 24 |
1080987577 ps |
| T498 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/11.xbar_stress_all_with_rand_reset.671124946 |
|
|
Aug 24 04:35:44 AM UTC 24 |
Aug 24 04:41:00 AM UTC 24 |
3125156452 ps |
| T1432 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/10.chip_csr_mem_rw_with_rand_reset.2959812945 |
|
|
Aug 24 04:31:32 AM UTC 24 |
Aug 24 04:41:06 AM UTC 24 |
9562901365 ps |
| T472 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/10.xbar_random_slow_rsp.722141719 |
|
|
Aug 24 04:30:16 AM UTC 24 |
Aug 24 04:41:15 AM UTC 24 |
55528596740 ps |
| T1433 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/13.xbar_smoke.1962083743 |
|
|
Aug 24 04:41:20 AM UTC 24 |
Aug 24 04:41:28 AM UTC 24 |
178745474 ps |
| T1434 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/13.xbar_smoke_zero_delays.1641150137 |
|
|
Aug 24 04:41:29 AM UTC 24 |
Aug 24 04:41:35 AM UTC 24 |
39927140 ps |
| T1435 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/11.chip_csr_mem_rw_with_rand_reset.424409459 |
|
|
Aug 24 04:36:32 AM UTC 24 |
Aug 24 04:41:41 AM UTC 24 |
7121173100 ps |
| T1436 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/9.xbar_random_large_delays.585478887 |
|
|
Aug 24 04:26:19 AM UTC 24 |
Aug 24 04:41:46 AM UTC 24 |
110539872392 ps |
| T1437 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/13.xbar_random.3057802229 |
|
|
Aug 24 04:41:55 AM UTC 24 |
Aug 24 04:42:13 AM UTC 24 |
546908345 ps |
| T1438 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/13.xbar_random_zero_delays.774469887 |
|
|
Aug 24 04:42:00 AM UTC 24 |
Aug 24 04:42:13 AM UTC 24 |
147673134 ps |
| T1439 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/1.chip_same_csr_outstanding.3941408413 |
|
|
Aug 24 03:50:12 AM UTC 24 |
Aug 24 04:42:20 AM UTC 24 |
29363662110 ps |
| T1440 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/13.xbar_smoke_large_delays.2696159191 |
|
|
Aug 24 04:41:42 AM UTC 24 |
Aug 24 04:42:35 AM UTC 24 |
6485100489 ps |
| T1441 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/13.xbar_smoke_slow_rsp.1212054629 |
|
|
Aug 24 04:41:49 AM UTC 24 |
Aug 24 04:42:49 AM UTC 24 |
5020745227 ps |
| T796 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/12.xbar_stress_all_with_error.1356378612 |
|
|
Aug 24 04:40:29 AM UTC 24 |
Aug 24 04:42:54 AM UTC 24 |
4887763313 ps |
| T814 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/10.xbar_access_same_device_slow_rsp.3338250826 |
|
|
Aug 24 04:30:33 AM UTC 24 |
Aug 24 04:42:55 AM UTC 24 |
59172607661 ps |
| T1442 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/11.chip_csr_rw.3239844137 |
|
|
Aug 24 04:36:17 AM UTC 24 |
Aug 24 04:43:07 AM UTC 24 |
5971827299 ps |
| T1443 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/13.xbar_same_source.520863255 |
|
|
Aug 24 04:43:04 AM UTC 24 |
Aug 24 04:43:18 AM UTC 24 |
471528233 ps |
| T1444 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/13.xbar_error_random.1192524398 |
|
|
Aug 24 04:43:08 AM UTC 24 |
Aug 24 04:43:35 AM UTC 24 |
395017602 ps |
| T1445 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/13.xbar_error_and_unmapped_addr.1256812531 |
|
|
Aug 24 04:43:21 AM UTC 24 |
Aug 24 04:43:43 AM UTC 24 |
639005207 ps |
| T815 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/13.xbar_access_same_device.763738600 |
|
|
Aug 24 04:42:34 AM UTC 24 |
Aug 24 04:43:44 AM UTC 24 |
2137576648 ps |
| T1446 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/13.xbar_unmapped_addr.3361783649 |
|
|
Aug 24 04:43:10 AM UTC 24 |
Aug 24 04:43:46 AM UTC 24 |
1142677471 ps |
| T862 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/12.xbar_stress_all_with_reset_error.313561527 |
|
|
Aug 24 04:40:31 AM UTC 24 |
Aug 24 04:43:47 AM UTC 24 |
5656949094 ps |
| T490 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/12.xbar_stress_all.3712205925 |
|
|
Aug 24 04:40:16 AM UTC 24 |
Aug 24 04:44:04 AM UTC 24 |
7738677095 ps |
| T422 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/3.chip_same_csr_outstanding.1821580421 |
|
|
Aug 24 03:59:47 AM UTC 24 |
Aug 24 04:44:14 AM UTC 24 |
32020961420 ps |
| T575 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/13.chip_tl_errors.4014366007 |
|
|
Aug 24 04:41:14 AM UTC 24 |
Aug 24 04:44:26 AM UTC 24 |
3334329389 ps |
| T1447 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/12.chip_csr_rw.330686206 |
|
|
Aug 24 04:40:32 AM UTC 24 |
Aug 24 04:44:43 AM UTC 24 |
4092897916 ps |
| T1448 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/14.xbar_smoke.3000206761 |
|
|
Aug 24 04:44:41 AM UTC 24 |
Aug 24 04:44:47 AM UTC 24 |
49797498 ps |
| T523 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/13.xbar_stress_all.1454115364 |
|
|
Aug 24 04:43:32 AM UTC 24 |
Aug 24 04:44:49 AM UTC 24 |
1272373034 ps |
| T1449 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/14.xbar_smoke_zero_delays.1319433668 |
|
|
Aug 24 04:44:57 AM UTC 24 |
Aug 24 04:45:03 AM UTC 24 |
38586144 ps |
| T1450 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/13.xbar_random_large_delays.1852812594 |
|
|
Aug 24 04:42:28 AM UTC 24 |
Aug 24 04:45:34 AM UTC 24 |
22115808972 ps |
| T524 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/14.xbar_random.1466097907 |
|
|
Aug 24 04:45:17 AM UTC 24 |
Aug 24 04:45:40 AM UTC 24 |
305721382 ps |
| T1451 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/14.xbar_smoke_slow_rsp.1515951213 |
|
|
Aug 24 04:45:03 AM UTC 24 |
Aug 24 04:46:03 AM UTC 24 |
4842882839 ps |
| T1452 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/14.xbar_random_zero_delays.2371542208 |
|
|
Aug 24 04:45:48 AM UTC 24 |
Aug 24 04:46:12 AM UTC 24 |
316496169 ps |
| T1453 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/14.xbar_smoke_large_delays.2027246841 |
|
|
Aug 24 04:45:02 AM UTC 24 |
Aug 24 04:46:24 AM UTC 24 |
10178073101 ps |
| T1454 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/14.xbar_random_slow_rsp.1272495587 |
|
|
Aug 24 04:46:17 AM UTC 24 |
Aug 24 04:46:52 AM UTC 24 |
2805635069 ps |
| T828 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/13.xbar_stress_all_with_error.4159953657 |
|
|
Aug 24 04:43:57 AM UTC 24 |
Aug 24 04:46:55 AM UTC 24 |
3517586142 ps |
| T855 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/13.xbar_stress_all_with_reset_error.3709259863 |
|
|
Aug 24 04:43:59 AM UTC 24 |
Aug 24 04:47:00 AM UTC 24 |
2524418662 ps |
| T463 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/14.xbar_access_same_device.3276245064 |
|
|
Aug 24 04:46:26 AM UTC 24 |
Aug 24 04:47:19 AM UTC 24 |
840300331 ps |
| T1455 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/14.xbar_error_random.1123862787 |
|
|
Aug 24 04:47:09 AM UTC 24 |
Aug 24 04:47:28 AM UTC 24 |
594889266 ps |
| T1456 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/12.chip_csr_mem_rw_with_rand_reset.1928510841 |
|
|
Aug 24 04:40:45 AM UTC 24 |
Aug 24 04:47:30 AM UTC 24 |
5990021902 ps |
| T1457 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/14.xbar_unmapped_addr.2129711354 |
|
|
Aug 24 04:47:14 AM UTC 24 |
Aug 24 04:47:32 AM UTC 24 |
443163659 ps |
| T1458 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/14.xbar_same_source.1046342688 |
|
|
Aug 24 04:47:06 AM UTC 24 |
Aug 24 04:47:33 AM UTC 24 |
1072335094 ps |
| T572 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/14.chip_tl_errors.4049354142 |
|
|
Aug 24 04:44:28 AM UTC 24 |
Aug 24 04:47:37 AM UTC 24 |
3783701965 ps |
| T1459 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/13.chip_csr_rw.1226126984 |
|
|
Aug 24 04:44:00 AM UTC 24 |
Aug 24 04:47:37 AM UTC 24 |
4377292076 ps |
| T1460 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/14.xbar_error_and_unmapped_addr.3108011409 |
|
|
Aug 24 04:47:33 AM UTC 24 |
Aug 24 04:48:10 AM UTC 24 |
1229972589 ps |
| T1461 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/14.xbar_stress_all_with_reset_error.4152542018 |
|
|
Aug 24 04:47:48 AM UTC 24 |
Aug 24 04:48:33 AM UTC 24 |
107346665 ps |
| T509 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/12.xbar_random_large_delays.3804476429 |
|
|
Aug 24 04:39:27 AM UTC 24 |
Aug 24 04:48:46 AM UTC 24 |
69996650056 ps |
| T818 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/13.xbar_access_same_device_slow_rsp.698534889 |
|
|
Aug 24 04:42:50 AM UTC 24 |
Aug 24 04:48:49 AM UTC 24 |
30820512043 ps |
| T1462 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/15.xbar_smoke.1715645706 |
|
|
Aug 24 04:49:01 AM UTC 24 |
Aug 24 04:49:07 AM UTC 24 |
45268597 ps |
| T1463 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/13.chip_csr_mem_rw_with_rand_reset.1094186474 |
|
|
Aug 24 04:44:01 AM UTC 24 |
Aug 24 04:48:58 AM UTC 24 |
5411222696 ps |
| T1464 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/15.xbar_smoke_zero_delays.80538753 |
|
|
Aug 24 04:49:03 AM UTC 24 |
Aug 24 04:49:09 AM UTC 24 |
47422109 ps |
| T1465 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/5.chip_same_csr_outstanding.1765394251 |
|
|
Aug 24 04:08:22 AM UTC 24 |
Aug 24 04:49:36 AM UTC 24 |
28489470212 ps |
| T621 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/13.xbar_stress_all_with_rand_reset.533052150 |
|
|
Aug 24 04:43:49 AM UTC 24 |
Aug 24 04:49:37 AM UTC 24 |
1579132571 ps |
| T1466 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/15.xbar_random.3681689686 |
|
|
Aug 24 04:49:23 AM UTC 24 |
Aug 24 04:49:42 AM UTC 24 |
237423529 ps |
| T1467 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/14.xbar_stress_all_with_error.2929892349 |
|
|
Aug 24 04:47:46 AM UTC 24 |
Aug 24 04:49:52 AM UTC 24 |
5303542966 ps |
| T1468 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/14.xbar_random_large_delays.3463134000 |
|
|
Aug 24 04:45:55 AM UTC 24 |
Aug 24 04:50:03 AM UTC 24 |
30945608917 ps |
| T1469 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/15.xbar_smoke_large_delays.592864103 |
|
|
Aug 24 04:49:12 AM UTC 24 |
Aug 24 04:50:11 AM UTC 24 |
7204380197 ps |
| T1470 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/15.xbar_random_zero_delays.2040410864 |
|
|
Aug 24 04:49:50 AM UTC 24 |
Aug 24 04:50:24 AM UTC 24 |
485443099 ps |
| T491 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/14.xbar_stress_all.2324884859 |
|
|
Aug 24 04:47:42 AM UTC 24 |
Aug 24 04:50:38 AM UTC 24 |
6083761428 ps |
| T824 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/15.xbar_access_same_device.3465482114 |
|
|
Aug 24 04:50:05 AM UTC 24 |
Aug 24 04:50:38 AM UTC 24 |
877235799 ps |
| T1471 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/15.xbar_smoke_slow_rsp.2948158188 |
|
|
Aug 24 04:49:22 AM UTC 24 |
Aug 24 04:50:38 AM UTC 24 |
5978635663 ps |
| T1472 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/15.xbar_error_random.1553728310 |
|
|
Aug 24 04:50:38 AM UTC 24 |
Aug 24 04:50:48 AM UTC 24 |
254738589 ps |
| T1473 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/15.xbar_same_source.4238523268 |
|
|
Aug 24 04:50:25 AM UTC 24 |
Aug 24 04:50:52 AM UTC 24 |
506040821 ps |
| T530 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/12.xbar_stress_all_with_rand_reset.1247300163 |
|
|
Aug 24 04:40:21 AM UTC 24 |
Aug 24 04:50:55 AM UTC 24 |
6660158617 ps |
| T1474 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/15.xbar_unmapped_addr.3068980370 |
|
|
Aug 24 04:50:53 AM UTC 24 |
Aug 24 04:51:05 AM UTC 24 |
109213381 ps |
| T1475 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/15.xbar_error_and_unmapped_addr.345580731 |
|
|
Aug 24 04:50:53 AM UTC 24 |
Aug 24 04:51:13 AM UTC 24 |
222788023 ps |
| T822 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/14.xbar_stress_all_with_rand_reset.2489159383 |
|
|
Aug 24 04:47:45 AM UTC 24 |
Aug 24 04:51:21 AM UTC 24 |
2057041839 ps |
| T423 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/9.chip_same_csr_outstanding.92890656 |
|
|
Aug 24 04:24:33 AM UTC 24 |
Aug 24 04:53:44 AM UTC 24 |
17824235733 ps |
| T1476 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/14.chip_csr_mem_rw_with_rand_reset.1005698062 |
|
|
Aug 24 04:47:52 AM UTC 24 |
Aug 24 04:53:47 AM UTC 24 |
6177459511 ps |
| T1477 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/16.xbar_smoke.2452993822 |
|
|
Aug 24 04:54:01 AM UTC 24 |
Aug 24 04:54:08 AM UTC 24 |
52812913 ps |
| T492 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/13.xbar_random_slow_rsp.4140387590 |
|
|
Aug 24 04:42:28 AM UTC 24 |
Aug 24 04:54:14 AM UTC 24 |
60340620222 ps |
| T1478 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/7.chip_same_csr_outstanding.2422952038 |
|
|
Aug 24 04:17:17 AM UTC 24 |
Aug 24 04:54:18 AM UTC 24 |
28187069162 ps |
| T858 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/15.xbar_stress_all_with_reset_error.2142478904 |
|
|
Aug 24 04:51:09 AM UTC 24 |
Aug 24 04:54:27 AM UTC 24 |
2068643274 ps |
| T1479 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/16.xbar_smoke_zero_delays.1804034244 |
|
|
Aug 24 04:54:22 AM UTC 24 |
Aug 24 04:54:28 AM UTC 24 |
46217328 ps |
| T445 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/14.chip_csr_rw.4253309340 |
|
|
Aug 24 04:47:52 AM UTC 24 |
Aug 24 04:54:36 AM UTC 24 |
6229064340 ps |
| T473 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/15.xbar_stress_all.1044277653 |
|
|
Aug 24 04:50:53 AM UTC 24 |
Aug 24 04:54:57 AM UTC 24 |
9963346484 ps |
| T559 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/15.chip_tl_errors.3517079733 |
|
|
Aug 24 04:48:47 AM UTC 24 |
Aug 24 04:55:02 AM UTC 24 |
5432110326 ps |
| T1480 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/16.xbar_random.1968950666 |
|
|
Aug 24 04:54:41 AM UTC 24 |
Aug 24 04:55:04 AM UTC 24 |
298385194 ps |
| T1481 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/16.xbar_random_zero_delays.3280068568 |
|
|
Aug 24 04:54:42 AM UTC 24 |
Aug 24 04:55:09 AM UTC 24 |
345116295 ps |
| T1482 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/16.xbar_access_same_device.3844118770 |
|
|
Aug 24 04:55:16 AM UTC 24 |
Aug 24 04:55:28 AM UTC 24 |
288232754 ps |
| T1483 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/16.xbar_smoke_large_delays.2874468496 |
|
|
Aug 24 04:54:28 AM UTC 24 |
Aug 24 04:55:30 AM UTC 24 |
7154229467 ps |
| T1484 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/16.xbar_same_source.3022390001 |
|
|
Aug 24 04:55:23 AM UTC 24 |
Aug 24 04:55:31 AM UTC 24 |
82395919 ps |
| T1485 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/16.xbar_smoke_slow_rsp.1466947008 |
|
|
Aug 24 04:54:32 AM UTC 24 |
Aug 24 04:55:33 AM UTC 24 |
4980102535 ps |
| T1486 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/15.chip_csr_rw.250585826 |
|
|
Aug 24 04:51:19 AM UTC 24 |
Aug 24 04:55:49 AM UTC 24 |
4182940436 ps |
| T1487 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/16.xbar_error_random.4037557338 |
|
|
Aug 24 04:55:43 AM UTC 24 |
Aug 24 04:55:55 AM UTC 24 |
373999165 ps |
| T1488 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/16.xbar_unmapped_addr.2179076124 |
|
|
Aug 24 04:55:44 AM UTC 24 |
Aug 24 04:56:01 AM UTC 24 |
154225434 ps |
| T1489 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/16.xbar_error_and_unmapped_addr.170989445 |
|
|
Aug 24 04:55:46 AM UTC 24 |
Aug 24 04:56:18 AM UTC 24 |
1111909700 ps |
| T1490 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/15.xbar_random_slow_rsp.245689071 |
|
|
Aug 24 04:49:56 AM UTC 24 |
Aug 24 04:56:20 AM UTC 24 |
31316743743 ps |
| T649 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/16.chip_tl_errors.2441792281 |
|
|
Aug 24 04:53:58 AM UTC 24 |
Aug 24 04:56:38 AM UTC 24 |
3460538584 ps |
| T1491 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/0.chip_csr_aliasing.3009762179 |
|
|
Aug 24 03:44:04 AM UTC 24 |
Aug 24 04:56:43 AM UTC 24 |
28782994067 ps |
| T865 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/16.xbar_stress_all_with_reset_error.1011577536 |
|
|
Aug 24 04:56:15 AM UTC 24 |
Aug 24 04:56:45 AM UTC 24 |
157632437 ps |
| T807 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/11.xbar_access_same_device_slow_rsp.3800875793 |
|
|
Aug 24 04:33:58 AM UTC 24 |
Aug 24 04:56:47 AM UTC 24 |
116778780142 ps |
| T826 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/15.xbar_stress_all_with_error.4001808781 |
|
|
Aug 24 04:51:06 AM UTC 24 |
Aug 24 04:57:02 AM UTC 24 |
14244426947 ps |
| T1492 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/6.chip_same_csr_outstanding.3736495499 |
|
|
Aug 24 04:11:59 AM UTC 24 |
Aug 24 04:57:04 AM UTC 24 |
33023519482 ps |
| T1493 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/17.xbar_smoke.1376152525 |
|
|
Aug 24 04:56:59 AM UTC 24 |
Aug 24 04:57:05 AM UTC 24 |
35602284 ps |
| T1494 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/17.xbar_smoke_zero_delays.3286969381 |
|
|
Aug 24 04:57:01 AM UTC 24 |
Aug 24 04:57:07 AM UTC 24 |
39694123 ps |
| T1495 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/16.xbar_stress_all_with_error.3539802363 |
|
|
Aug 24 04:56:10 AM UTC 24 |
Aug 24 04:57:21 AM UTC 24 |
2875474435 ps |
| T1496 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/17.xbar_random_zero_delays.77252647 |
|
|
Aug 24 04:57:22 AM UTC 24 |
Aug 24 04:58:00 AM UTC 24 |
525178583 ps |
| T1497 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/17.xbar_smoke_slow_rsp.1025514229 |
|
|
Aug 24 04:57:18 AM UTC 24 |
Aug 24 04:58:21 AM UTC 24 |
4781614122 ps |
| T1498 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/17.xbar_random.3274843234 |
|
|
Aug 24 04:57:20 AM UTC 24 |
Aug 24 04:58:30 AM UTC 24 |
2511942132 ps |
| T1499 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/17.xbar_smoke_large_delays.2426052476 |
|
|
Aug 24 04:57:15 AM UTC 24 |
Aug 24 04:58:31 AM UTC 24 |
9029073571 ps |
| T1500 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/16.xbar_random_large_delays.3460166931 |
|
|
Aug 24 04:54:50 AM UTC 24 |
Aug 24 04:58:49 AM UTC 24 |
29226182639 ps |
| T1501 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/17.xbar_same_source.698679959 |
|
|
Aug 24 04:58:45 AM UTC 24 |
Aug 24 04:59:08 AM UTC 24 |
932138573 ps |
| T1502 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/17.xbar_access_same_device.2427338670 |
|
|
Aug 24 04:58:36 AM UTC 24 |
Aug 24 04:59:18 AM UTC 24 |
1224364778 ps |
| T1503 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/17.xbar_random_large_delays.854295890 |
|
|
Aug 24 04:57:35 AM UTC 24 |
Aug 24 04:59:19 AM UTC 24 |
12484193666 ps |
| T1504 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/17.xbar_error_random.4223721348 |
|
|
Aug 24 04:59:03 AM UTC 24 |
Aug 24 04:59:37 AM UTC 24 |
1330312001 ps |
| T1505 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/17.xbar_unmapped_addr.3115906633 |
|
|
Aug 24 04:59:22 AM UTC 24 |
Aug 24 04:59:40 AM UTC 24 |
165311716 ps |
| T1506 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/17.xbar_error_and_unmapped_addr.2562055011 |
|
|
Aug 24 04:59:32 AM UTC 24 |
Aug 24 04:59:43 AM UTC 24 |
99849972 ps |
| T479 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/16.xbar_stress_all.60388278 |
|
|
Aug 24 04:55:47 AM UTC 24 |
Aug 24 04:59:52 AM UTC 24 |
8770244900 ps |
| T519 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/12.xbar_access_same_device_slow_rsp.2517632047 |
|
|
Aug 24 04:39:45 AM UTC 24 |
Aug 24 05:01:04 AM UTC 24 |
101543511020 ps |
| T558 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/17.chip_tl_errors.2865073311 |
|
|
Aug 24 04:56:57 AM UTC 24 |
Aug 24 05:01:16 AM UTC 24 |
4206154112 ps |
| T1507 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/13.chip_same_csr_outstanding.910735474 |
|
|
Aug 24 04:41:04 AM UTC 24 |
Aug 24 05:01:19 AM UTC 24 |
17362482334 ps |
| T837 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/16.xbar_stress_all_with_rand_reset.2550831612 |
|
|
Aug 24 04:56:04 AM UTC 24 |
Aug 24 05:01:28 AM UTC 24 |
897779604 ps |
| T846 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/15.xbar_stress_all_with_rand_reset.2309858161 |
|
|
Aug 24 04:51:02 AM UTC 24 |
Aug 24 05:01:38 AM UTC 24 |
16671941713 ps |
| T1508 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/18.xbar_smoke.284354448 |
|
|
Aug 24 05:01:42 AM UTC 24 |
Aug 24 05:01:48 AM UTC 24 |
43866966 ps |
| T1509 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/14.chip_same_csr_outstanding.127187227 |
|
|
Aug 24 04:44:18 AM UTC 24 |
Aug 24 05:01:49 AM UTC 24 |
15941662298 ps |
| T1510 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/18.xbar_smoke_zero_delays.1058167629 |
|
|
Aug 24 05:01:52 AM UTC 24 |
Aug 24 05:01:59 AM UTC 24 |
45443777 ps |
| T520 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/17.xbar_stress_all.2237019149 |
|
|
Aug 24 04:59:34 AM UTC 24 |
Aug 24 05:02:00 AM UTC 24 |
2647416052 ps |
| T446 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/15.chip_csr_mem_rw_with_rand_reset.3600085214 |
|
|
Aug 24 04:51:28 AM UTC 24 |
Aug 24 05:02:33 AM UTC 24 |
8478910631 ps |
| T1511 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/18.xbar_random_zero_delays.678324601 |
|
|
Aug 24 05:02:14 AM UTC 24 |
Aug 24 05:02:37 AM UTC 24 |
341339771 ps |
| T1512 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/18.xbar_smoke_slow_rsp.3747329714 |
|
|
Aug 24 05:02:03 AM UTC 24 |
Aug 24 05:02:56 AM UTC 24 |
4315085176 ps |
| T1513 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/18.xbar_smoke_large_delays.3484896268 |
|
|
Aug 24 05:02:02 AM UTC 24 |
Aug 24 05:03:03 AM UTC 24 |
7317381180 ps |
| T1514 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/16.chip_csr_mem_rw_with_rand_reset.3204844072 |
|
|
Aug 24 04:56:35 AM UTC 24 |
Aug 24 05:03:07 AM UTC 24 |
6733935600 ps |
| T493 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/18.xbar_random.1122950011 |
|
|
Aug 24 05:02:13 AM UTC 24 |
Aug 24 05:03:13 AM UTC 24 |
2002972645 ps |
| T1515 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/16.chip_csr_rw.2109926676 |
|
|
Aug 24 04:56:32 AM UTC 24 |
Aug 24 05:03:23 AM UTC 24 |
5678222576 ps |
| T483 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/18.xbar_access_same_device.3369140949 |
|
|
Aug 24 05:03:11 AM UTC 24 |
Aug 24 05:03:31 AM UTC 24 |
308259569 ps |
| T488 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/16.xbar_random_slow_rsp.4121371441 |
|
|
Aug 24 04:55:11 AM UTC 24 |
Aug 24 05:03:35 AM UTC 24 |
41335950440 ps |
| T1516 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/18.xbar_same_source.3834560244 |
|
|
Aug 24 05:03:22 AM UTC 24 |
Aug 24 05:03:48 AM UTC 24 |
1207434025 ps |
| T1517 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/18.xbar_unmapped_addr.2724148665 |
|
|
Aug 24 05:03:37 AM UTC 24 |
Aug 24 05:04:03 AM UTC 24 |
733870482 ps |
| T1518 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/18.xbar_error_and_unmapped_addr.4056645647 |
|
|
Aug 24 05:03:46 AM UTC 24 |
Aug 24 05:04:09 AM UTC 24 |
282600642 ps |
| T510 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/15.xbar_random_large_delays.3978292823 |
|
|
Aug 24 04:49:52 AM UTC 24 |
Aug 24 05:04:22 AM UTC 24 |
112250605837 ps |
| T1519 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/11.chip_same_csr_outstanding.997390011 |
|
|
Aug 24 04:31:49 AM UTC 24 |
Aug 24 05:04:22 AM UTC 24 |
28219775808 ps |
| T1520 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/18.xbar_error_random.205453491 |
|
|
Aug 24 05:03:28 AM UTC 24 |
Aug 24 05:04:35 AM UTC 24 |
2539767197 ps |
| T1521 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/17.chip_csr_rw.2793703350 |
|
|
Aug 24 05:00:06 AM UTC 24 |
Aug 24 05:05:19 AM UTC 24 |
4568599234 ps |
| T867 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/18.xbar_stress_all_with_rand_reset.3096893441 |
|
|
Aug 24 05:04:02 AM UTC 24 |
Aug 24 05:05:24 AM UTC 24 |
305909007 ps |
| T1522 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/17.xbar_random_slow_rsp.544635302 |
|
|
Aug 24 04:58:14 AM UTC 24 |
Aug 24 05:05:27 AM UTC 24 |
36812957914 ps |
| T808 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/18.xbar_stress_all_with_error.1554264191 |
|
|
Aug 24 05:04:17 AM UTC 24 |
Aug 24 05:05:30 AM UTC 24 |
2862595778 ps |
| T1523 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/19.xbar_smoke.2268906173 |
|
|
Aug 24 05:05:38 AM UTC 24 |
Aug 24 05:05:44 AM UTC 24 |
41865211 ps |
| T1524 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/19.xbar_smoke_zero_delays.1249698651 |
|
|
Aug 24 05:05:41 AM UTC 24 |
Aug 24 05:05:48 AM UTC 24 |
49697587 ps |
| T560 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/18.chip_tl_errors.2709388663 |
|
|
Aug 24 05:01:34 AM UTC 24 |
Aug 24 05:05:50 AM UTC 24 |
4245291437 ps |
| T791 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/17.xbar_stress_all_with_error.3683590924 |
|
|
Aug 24 04:59:54 AM UTC 24 |
Aug 24 05:06:07 AM UTC 24 |
15307311957 ps |
| T810 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/16.xbar_access_same_device_slow_rsp.2645898573 |
|
|
Aug 24 04:55:19 AM UTC 24 |
Aug 24 05:06:23 AM UTC 24 |
57874739362 ps |
| T833 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/17.xbar_stress_all_with_reset_error.630541712 |
|
|
Aug 24 04:59:58 AM UTC 24 |
Aug 24 05:06:31 AM UTC 24 |
10957293711 ps |
| T531 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/19.xbar_random_zero_delays.3735139802 |
|
|
Aug 24 05:06:04 AM UTC 24 |
Aug 24 05:06:32 AM UTC 24 |
423787763 ps |
| T804 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/14.xbar_access_same_device_slow_rsp.3676533839 |
|
|
Aug 24 04:46:38 AM UTC 24 |
Aug 24 05:06:35 AM UTC 24 |
104582783134 ps |
| T522 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/17.xbar_stress_all_with_rand_reset.1700223983 |
|
|
Aug 24 04:59:51 AM UTC 24 |
Aug 24 05:06:37 AM UTC 24 |
3117369654 ps |
| T1525 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/19.xbar_smoke_large_delays.2233163277 |
|
|
Aug 24 05:05:44 AM UTC 24 |
Aug 24 05:06:37 AM UTC 24 |
6589061291 ps |
| T1526 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/19.xbar_random.2555273060 |
|
|
Aug 24 05:06:02 AM UTC 24 |
Aug 24 05:06:38 AM UTC 24 |
1223335091 ps |
| T1527 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/19.xbar_smoke_slow_rsp.1739260605 |
|
|
Aug 24 05:05:59 AM UTC 24 |
Aug 24 05:06:48 AM UTC 24 |
4053670705 ps |
| T1528 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/18.xbar_stress_all.1676657995 |
|
|
Aug 24 05:03:50 AM UTC 24 |
Aug 24 05:06:50 AM UTC 24 |
6421929644 ps |
| T1529 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/19.xbar_unmapped_addr.3250681459 |
|
|
Aug 24 05:06:51 AM UTC 24 |
Aug 24 05:07:00 AM UTC 24 |
157348810 ps |
| T1530 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/19.xbar_same_source.23594150 |
|
|
Aug 24 05:06:49 AM UTC 24 |
Aug 24 05:07:00 AM UTC 24 |
132412649 ps |
| T1531 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/19.xbar_stress_all_with_reset_error.2016195348 |
|
|
Aug 24 05:07:15 AM UTC 24 |
Aug 24 05:07:25 AM UTC 24 |
42138846 ps |
| T1532 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/19.xbar_error_and_unmapped_addr.2102803570 |
|
|
Aug 24 05:06:52 AM UTC 24 |
Aug 24 05:07:31 AM UTC 24 |
1193959343 ps |
| T501 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/19.xbar_access_same_device.1550945396 |
|
|
Aug 24 05:06:45 AM UTC 24 |
Aug 24 05:07:45 AM UTC 24 |
1712598625 ps |
| T1533 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/19.xbar_error_random.3347719540 |
|
|
Aug 24 05:06:51 AM UTC 24 |
Aug 24 05:07:55 AM UTC 24 |
2240852285 ps |
| T581 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/19.chip_tl_errors.1160300669 |
|
|
Aug 24 05:05:33 AM UTC 24 |
Aug 24 05:08:11 AM UTC 24 |
3451274460 ps |
| T1534 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/20.xbar_smoke.2136024859 |
|
|
Aug 24 05:08:09 AM UTC 24 |
Aug 24 05:08:16 AM UTC 24 |
151486412 ps |
| T1535 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/20.xbar_smoke_zero_delays.3266769917 |
|
|
Aug 24 05:08:25 AM UTC 24 |
Aug 24 05:08:32 AM UTC 24 |
49065741 ps |
| T1536 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/18.chip_csr_rw.746629418 |
|
|
Aug 24 05:04:36 AM UTC 24 |
Aug 24 05:08:39 AM UTC 24 |
3871645150 ps |
| T866 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/18.xbar_stress_all_with_reset_error.1022417242 |
|
|
Aug 24 05:04:24 AM UTC 24 |
Aug 24 05:08:53 AM UTC 24 |
3215659672 ps |
| T1537 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/20.xbar_random.1456898235 |
|
|
Aug 24 05:08:53 AM UTC 24 |
Aug 24 05:09:01 AM UTC 24 |
61750657 ps |
| T541 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/19.xbar_stress_all.3332422033 |
|
|
Aug 24 05:07:01 AM UTC 24 |
Aug 24 05:09:15 AM UTC 24 |
5294588299 ps |
| T1538 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/17.chip_csr_mem_rw_with_rand_reset.976416917 |
|
|
Aug 24 05:01:19 AM UTC 24 |
Aug 24 05:09:19 AM UTC 24 |
7804016160 ps |
| T1539 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/20.xbar_random_zero_delays.2448122045 |
|
|
Aug 24 05:09:07 AM UTC 24 |
Aug 24 05:09:33 AM UTC 24 |
364918418 ps |
| T1540 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/20.xbar_smoke_slow_rsp.2002541874 |
|
|
Aug 24 05:08:46 AM UTC 24 |
Aug 24 05:09:41 AM UTC 24 |
4514167800 ps |
| T1541 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/20.xbar_smoke_large_delays.1937818208 |
|
|
Aug 24 05:08:31 AM UTC 24 |
Aug 24 05:09:43 AM UTC 24 |
8784238735 ps |
| T1542 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/19.xbar_random_slow_rsp.952983720 |
|
|
Aug 24 05:06:37 AM UTC 24 |
Aug 24 05:10:07 AM UTC 24 |
17837396900 ps |
| T859 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/19.xbar_stress_all_with_rand_reset.2180173099 |
|
|
Aug 24 05:07:04 AM UTC 24 |
Aug 24 05:10:24 AM UTC 24 |
5129074989 ps |
| T1543 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/18.xbar_random_slow_rsp.1463304617 |
|
|
Aug 24 05:02:52 AM UTC 24 |
Aug 24 05:10:26 AM UTC 24 |
37891495612 ps |
| T1544 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/20.xbar_access_same_device.3086947281 |
|
|
Aug 24 05:09:33 AM UTC 24 |
Aug 24 05:10:33 AM UTC 24 |
1038807949 ps |
| T1545 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/20.xbar_error_random.3514394019 |
|
|
Aug 24 05:09:57 AM UTC 24 |
Aug 24 05:10:34 AM UTC 24 |
581978890 ps |
| T1546 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/20.xbar_unmapped_addr.1142044501 |
|
|
Aug 24 05:10:22 AM UTC 24 |
Aug 24 05:10:39 AM UTC 24 |
458750811 ps |
| T1547 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/20.xbar_same_source.3501627753 |
|
|
Aug 24 05:09:55 AM UTC 24 |
Aug 24 05:10:48 AM UTC 24 |
2288016826 ps |
| T1548 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/20.xbar_error_and_unmapped_addr.2965221945 |
|
|
Aug 24 05:10:38 AM UTC 24 |
Aug 24 05:11:02 AM UTC 24 |
739278346 ps |
| T1549 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/21.xbar_smoke.2715726794 |
|
|
Aug 24 05:11:16 AM UTC 24 |
Aug 24 05:11:24 AM UTC 24 |
214382821 ps |
| T825 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/19.xbar_stress_all_with_error.2782362750 |
|
|
Aug 24 05:07:14 AM UTC 24 |
Aug 24 05:11:33 AM UTC 24 |
10320511492 ps |
| T1550 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/4.chip_csr_bit_bash.3472050173 |
|
|
Aug 24 04:03:38 AM UTC 24 |
Aug 24 05:11:43 AM UTC 24 |
56274406974 ps |
| T1551 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/21.xbar_smoke_zero_delays.1007157863 |
|
|
Aug 24 05:11:39 AM UTC 24 |
Aug 24 05:11:46 AM UTC 24 |
46197649 ps |
| T582 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/20.chip_tl_errors.477315044 |
|
|
Aug 24 05:07:59 AM UTC 24 |
Aug 24 05:12:14 AM UTC 24 |
4354506876 ps |
| T1552 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/21.xbar_random.2791534002 |
|
|
Aug 24 05:11:59 AM UTC 24 |
Aug 24 05:12:33 AM UTC 24 |
1235111084 ps |
| T1553 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/21.xbar_random_zero_delays.1833047827 |
|
|
Aug 24 05:12:29 AM UTC 24 |
Aug 24 05:12:41 AM UTC 24 |
166652108 ps |
| T1554 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/21.xbar_smoke_slow_rsp.517068974 |
|
|
Aug 24 05:11:57 AM UTC 24 |
Aug 24 05:12:54 AM UTC 24 |
4741990834 ps |
| T1555 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/21.xbar_smoke_large_delays.1896901993 |
|
|
Aug 24 05:11:48 AM UTC 24 |
Aug 24 05:12:55 AM UTC 24 |
8059400761 ps |
| T1556 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/18.chip_csr_mem_rw_with_rand_reset.191606424 |
|
|
Aug 24 05:04:36 AM UTC 24 |
Aug 24 05:13:11 AM UTC 24 |
8702828006 ps |
| T648 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/21.chip_tl_errors.501201175 |
|
|
Aug 24 05:11:03 AM UTC 24 |
Aug 24 05:13:19 AM UTC 24 |
2947092660 ps |
| T1557 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/21.xbar_same_source.3868064917 |
|
|
Aug 24 05:13:26 AM UTC 24 |
Aug 24 05:13:33 AM UTC 24 |
71383655 ps |
| T1558 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/19.xbar_random_large_delays.1960579426 |
|
|
Aug 24 05:06:22 AM UTC 24 |
Aug 24 05:13:37 AM UTC 24 |
54488576922 ps |
| T1559 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/21.xbar_error_random.3591062905 |
|
|
Aug 24 05:13:34 AM UTC 24 |
Aug 24 05:13:48 AM UTC 24 |
173860120 ps |
| T1560 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/18.xbar_random_large_delays.747823316 |
|
|
Aug 24 05:02:46 AM UTC 24 |
Aug 24 05:13:58 AM UTC 24 |
80253412352 ps |
| T860 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/20.xbar_stress_all_with_rand_reset.1828819915 |
|
|
Aug 24 05:10:47 AM UTC 24 |
Aug 24 05:14:19 AM UTC 24 |
870951738 ps |
| T1561 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/21.xbar_unmapped_addr.2867650390 |
|
|
Aug 24 05:13:48 AM UTC 24 |
Aug 24 05:14:26 AM UTC 24 |
1104862647 ps |
| T1562 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/20.xbar_stress_all_with_reset_error.1770686305 |
|
|
Aug 24 05:10:54 AM UTC 24 |
Aug 24 05:14:32 AM UTC 24 |
3129515693 ps |
| T1563 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/21.xbar_error_and_unmapped_addr.4267208163 |
|
|
Aug 24 05:13:52 AM UTC 24 |
Aug 24 05:14:37 AM UTC 24 |
1484352099 ps |
| T831 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/21.xbar_access_same_device.1799391809 |
|
|
Aug 24 05:13:09 AM UTC 24 |
Aug 24 05:14:42 AM UTC 24 |
2984634328 ps |
| T1564 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/20.xbar_random_slow_rsp.137289335 |
|
|
Aug 24 05:09:29 AM UTC 24 |
Aug 24 05:14:44 AM UTC 24 |
26759555359 ps |
| T481 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/20.xbar_stress_all.3775486240 |
|
|
Aug 24 05:10:41 AM UTC 24 |
Aug 24 05:14:47 AM UTC 24 |
8750278064 ps |
| T827 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/20.xbar_stress_all_with_error.1241323639 |
|
|
Aug 24 05:10:48 AM UTC 24 |
Aug 24 05:14:50 AM UTC 24 |
9930756260 ps |
| T1565 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/22.xbar_smoke.317352820 |
|
|
Aug 24 05:14:52 AM UTC 24 |
Aug 24 05:14:58 AM UTC 24 |
56769445 ps |
| T1566 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/22.xbar_smoke_zero_delays.2210970842 |
|
|
Aug 24 05:14:57 AM UTC 24 |
Aug 24 05:15:03 AM UTC 24 |
55712047 ps |
| T1567 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/19.chip_csr_rw.3818727401 |
|
|
Aug 24 05:07:40 AM UTC 24 |
Aug 24 05:15:07 AM UTC 24 |
5260381110 ps |
| T1568 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/22.xbar_random.2947334597 |
|
|
Aug 24 05:15:05 AM UTC 24 |
Aug 24 05:15:15 AM UTC 24 |
281583866 ps |
| T1569 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/21.xbar_stress_all_with_rand_reset.3197466228 |
|
|
Aug 24 05:14:12 AM UTC 24 |
Aug 24 05:15:46 AM UTC 24 |
233203776 ps |
| T534 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/22.xbar_random_zero_delays.482264659 |
|
|
Aug 24 05:15:13 AM UTC 24 |
Aug 24 05:15:54 AM UTC 24 |
594823961 ps |
| T1570 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/21.xbar_stress_all_with_reset_error.1672185677 |
|
|
Aug 24 05:14:40 AM UTC 24 |
Aug 24 05:15:58 AM UTC 24 |
232709061 ps |