| T1249 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_flash_init_reduced_freq.310296174 |
|
|
Aug 24 02:39:02 PM UTC 24 |
Aug 24 03:04:25 PM UTC 24 |
18684672501 ps |
| T1250 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_pwrmgr_usbdev_smoketest.3732115123 |
|
|
Aug 24 02:58:54 PM UTC 24 |
Aug 24 03:05:13 PM UTC 24 |
5531182020 ps |
| T1251 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_uart_smoketest.3448366738 |
|
|
Aug 24 03:01:42 PM UTC 24 |
Aug 24 03:05:30 PM UTC 24 |
2875718040 ps |
| T320 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_keymgr_sideload_otbn.893544898 |
|
|
Aug 24 02:05:01 PM UTC 24 |
Aug 24 03:06:10 PM UTC 24 |
16938248086 ps |
| T178 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_ast_clk_rst_inputs.2799780583 |
|
|
Aug 24 02:41:01 PM UTC 24 |
Aug 24 03:09:04 PM UTC 24 |
17981196684 ps |
| T1252 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/3.chip_sw_all_escalation_resets.3553986886 |
|
|
Aug 24 03:03:21 PM UTC 24 |
Aug 24 03:10:21 PM UTC 24 |
4937111336 ps |
| T1253 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/3.chip_sw_uart_tx_rx.2188841526 |
|
|
Aug 24 03:03:35 PM UTC 24 |
Aug 24 03:10:26 PM UTC 24 |
4860027956 ps |
| T1254 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/3.chip_sw_uart_rand_baudrate.2243116572 |
|
|
Aug 24 03:05:37 PM UTC 24 |
Aug 24 03:11:14 PM UTC 24 |
3070218160 ps |
| T1255 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/3.chip_sw_uart_tx_rx_idx3.3454908747 |
|
|
Aug 24 03:04:58 PM UTC 24 |
Aug 24 03:11:16 PM UTC 24 |
4010684412 ps |
| T1256 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/3.chip_sw_uart_tx_rx_idx2.1228734774 |
|
|
Aug 24 03:04:58 PM UTC 24 |
Aug 24 03:11:20 PM UTC 24 |
3699901452 ps |
| T1257 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/3.chip_sw_uart_tx_rx_idx1.95162892 |
|
|
Aug 24 03:04:05 PM UTC 24 |
Aug 24 03:11:32 PM UTC 24 |
4497857282 ps |
| T1258 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/3.chip_sw_data_integrity_escalation.689356265 |
|
|
Aug 24 03:03:22 PM UTC 24 |
Aug 24 03:12:11 PM UTC 24 |
6319277790 ps |
| T1259 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/3.chip_tap_straps_dev.2307066571 |
|
|
Aug 24 03:11:47 PM UTC 24 |
Aug 24 03:13:56 PM UTC 24 |
2383526044 ps |
| T1260 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_otbn_smoketest.3129379439 |
|
|
Aug 24 02:57:56 PM UTC 24 |
Aug 24 03:13:58 PM UTC 24 |
6649663380 ps |
| T1261 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/3.chip_sw_aon_timer_sleep_wdog_sleep_pause.3105449655 |
|
|
Aug 24 03:10:54 PM UTC 24 |
Aug 24 03:16:00 PM UTC 24 |
7848600468 ps |
| T704 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/3.chip_sw_alert_handler_lpg_sleep_mode_alerts.1109657275 |
|
|
Aug 24 03:10:54 PM UTC 24 |
Aug 24 03:16:07 PM UTC 24 |
4179843842 ps |
| T1262 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/3.chip_tap_straps_testunlock0.825123315 |
|
|
Aug 24 03:11:55 PM UTC 24 |
Aug 24 03:16:44 PM UTC 24 |
4350410421 ps |
| T1263 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/3.chip_sw_uart_tx_rx_alt_clk_freq_low_speed.3503929916 |
|
|
Aug 24 03:06:35 PM UTC 24 |
Aug 24 03:17:45 PM UTC 24 |
7986519983 ps |
| T1264 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/3.chip_sw_lc_ctrl_transition.57158416 |
|
|
Aug 24 03:09:28 PM UTC 24 |
Aug 24 03:18:41 PM UTC 24 |
10075420767 ps |
| T1265 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/3.chip_tap_straps_rma.509289893 |
|
|
Aug 24 03:12:30 PM UTC 24 |
Aug 24 03:18:56 PM UTC 24 |
6115307303 ps |
| T169 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/3.chip_sw_sensor_ctrl_alert.3894875149 |
|
|
Aug 24 03:11:54 PM UTC 24 |
Aug 24 03:19:29 PM UTC 24 |
6686157714 ps |
| T1266 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/2.rom_e2e_asm_init_test_unlocked0.3874400317 |
|
|
Aug 24 02:42:01 PM UTC 24 |
Aug 24 03:20:03 PM UTC 24 |
11567641821 ps |
| T770 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/4.chip_sw_all_escalation_resets.3989073627 |
|
|
Aug 24 03:14:26 PM UTC 24 |
Aug 24 03:22:23 PM UTC 24 |
5313266312 ps |
| T1267 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/3.chip_tap_straps_prod.500979442 |
|
|
Aug 24 03:14:24 PM UTC 24 |
Aug 24 03:22:57 PM UTC 24 |
8244053670 ps |
| T1268 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/4.chip_sw_data_integrity_escalation.3808959780 |
|
|
Aug 24 03:16:34 PM UTC 24 |
Aug 24 03:23:06 PM UTC 24 |
6253427358 ps |
| T1269 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/4.chip_sw_uart_tx_rx.2885369335 |
|
|
Aug 24 03:16:34 PM UTC 24 |
Aug 24 03:23:50 PM UTC 24 |
4567696360 ps |
| T1270 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/4.chip_sw_uart_tx_rx_idx1.231781061 |
|
|
Aug 24 03:17:09 PM UTC 24 |
Aug 24 03:24:29 PM UTC 24 |
4895030304 ps |
| T1271 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_csrng_edn_concurrency.1332810235 |
|
|
Aug 24 01:53:03 PM UTC 24 |
Aug 24 03:25:03 PM UTC 24 |
26879685640 ps |
| T1272 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/4.chip_sw_uart_tx_rx_idx2.732665046 |
|
|
Aug 24 03:18:10 PM UTC 24 |
Aug 24 03:25:20 PM UTC 24 |
5121883026 ps |
| T1273 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/4.chip_sw_uart_tx_rx_idx3.925633508 |
|
|
Aug 24 03:19:05 PM UTC 24 |
Aug 24 03:26:22 PM UTC 24 |
4445543960 ps |
| T1274 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/4.chip_sw_uart_tx_rx_alt_clk_freq_low_speed.985118893 |
|
|
Aug 24 03:20:28 PM UTC 24 |
Aug 24 03:26:48 PM UTC 24 |
4379620676 ps |
| T1275 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/3.chip_sw_uart_tx_rx_alt_clk_freq.2813866838 |
|
|
Aug 24 03:05:54 PM UTC 24 |
Aug 24 03:26:58 PM UTC 24 |
8453642397 ps |
| T1276 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/4.chip_tap_straps_dev.4225751285 |
|
|
Aug 24 03:25:23 PM UTC 24 |
Aug 24 03:27:32 PM UTC 24 |
2554908299 ps |
| T1277 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_rv_timer_systick_test.4209553391 |
|
|
Aug 24 01:33:38 PM UTC 24 |
Aug 24 03:28:13 PM UTC 24 |
38363573388 ps |
| T1278 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/2.rom_e2e_shutdown_output.2144477011 |
|
|
Aug 24 02:42:01 PM UTC 24 |
Aug 24 03:28:32 PM UTC 24 |
27785006355 ps |
| T1279 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/4.chip_sw_aon_timer_sleep_wdog_sleep_pause.3733761219 |
|
|
Aug 24 03:23:21 PM UTC 24 |
Aug 24 03:28:39 PM UTC 24 |
7086925072 ps |
| T746 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/4.chip_sw_alert_handler_lpg_sleep_mode_alerts.3510999369 |
|
|
Aug 24 03:23:31 PM UTC 24 |
Aug 24 03:29:18 PM UTC 24 |
4355739584 ps |
| T1280 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/2.rom_e2e_shutdown_exception_c.3694628802 |
|
|
Aug 24 02:41:52 PM UTC 24 |
Aug 24 03:29:38 PM UTC 24 |
15174871776 ps |
| T1281 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/4.chip_tap_straps_testunlock0.3460517440 |
|
|
Aug 24 03:25:39 PM UTC 24 |
Aug 24 03:30:34 PM UTC 24 |
5241469106 ps |
| T1282 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/4.chip_tap_straps_rma.2584735210 |
|
|
Aug 24 03:26:41 PM UTC 24 |
Aug 24 03:30:49 PM UTC 24 |
4807978191 ps |
| T1283 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq.752512748 |
|
|
Aug 24 02:37:54 PM UTC 24 |
Aug 24 03:31:06 PM UTC 24 |
24719069992 ps |
| T1284 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/2.rom_e2e_smoke.2952917597 |
|
|
Aug 24 02:41:52 PM UTC 24 |
Aug 24 03:33:01 PM UTC 24 |
14664889940 ps |
| T1285 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/2.rom_e2e_keymgr_init_rom_ext_no_meas.1711246117 |
|
|
Aug 24 02:46:18 PM UTC 24 |
Aug 24 03:33:43 PM UTC 24 |
15667937224 ps |
| T710 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/5.chip_sw_alert_handler_lpg_sleep_mode_alerts.156383728 |
|
|
Aug 24 03:29:05 PM UTC 24 |
Aug 24 03:34:20 PM UTC 24 |
4008662962 ps |
| T173 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/4.chip_sw_sensor_ctrl_alert.3619797535 |
|
|
Aug 24 03:24:53 PM UTC 24 |
Aug 24 03:34:31 PM UTC 24 |
5657815214 ps |
| T1286 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/2.rom_e2e_asm_init_dev.2756302732 |
|
|
Aug 24 02:43:05 PM UTC 24 |
Aug 24 03:34:53 PM UTC 24 |
15165030563 ps |
| T742 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/5.chip_sw_all_escalation_resets.2807437099 |
|
|
Aug 24 03:27:23 PM UTC 24 |
Aug 24 03:35:05 PM UTC 24 |
5373536872 ps |
| T1287 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/2.rom_e2e_asm_init_rma.2381869283 |
|
|
Aug 24 02:45:36 PM UTC 24 |
Aug 24 03:35:23 PM UTC 24 |
14942410100 ps |
| T1288 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/5.chip_sw_uart_rand_baudrate.1746153614 |
|
|
Aug 24 03:28:38 PM UTC 24 |
Aug 24 03:35:32 PM UTC 24 |
4355219352 ps |
| T378 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/5.chip_sw_data_integrity_escalation.1638089708 |
|
|
Aug 24 03:27:56 PM UTC 24 |
Aug 24 03:35:36 PM UTC 24 |
5887139928 ps |
| T1289 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/2.rom_e2e_asm_init_prod.2152567682 |
|
|
Aug 24 02:43:05 PM UTC 24 |
Aug 24 03:35:44 PM UTC 24 |
15466173692 ps |
| T765 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/6.chip_sw_alert_handler_lpg_sleep_mode_alerts.3727952174 |
|
|
Aug 24 03:31:31 PM UTC 24 |
Aug 24 03:35:51 PM UTC 24 |
3424452404 ps |
| T1290 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/2.rom_e2e_keymgr_init_rom_ext_invalid_meas.2964878149 |
|
|
Aug 24 02:46:20 PM UTC 24 |
Aug 24 03:36:08 PM UTC 24 |
14501558232 ps |
| T1291 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/4.chip_sw_lc_ctrl_transition.1813898182 |
|
|
Aug 24 03:22:47 PM UTC 24 |
Aug 24 03:36:13 PM UTC 24 |
10005340114 ps |
| T379 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/6.chip_sw_all_escalation_resets.429046675 |
|
|
Aug 24 03:30:03 PM UTC 24 |
Aug 24 03:36:49 PM UTC 24 |
6039520208 ps |
| T1292 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/2.rom_e2e_asm_init_prod_end.3523039764 |
|
|
Aug 24 02:44:26 PM UTC 24 |
Aug 24 03:37:30 PM UTC 24 |
15564850577 ps |
| T1293 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/6.chip_sw_lc_ctrl_transition.1027442037 |
|
|
Aug 24 03:31:12 PM UTC 24 |
Aug 24 03:37:32 PM UTC 24 |
5131152322 ps |
| T1294 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/4.chip_sw_uart_rand_baudrate.1420801642 |
|
|
Aug 24 03:19:21 PM UTC 24 |
Aug 24 03:37:34 PM UTC 24 |
8370426696 ps |
| T1295 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/2.rom_e2e_keymgr_init_rom_ext_meas.508446968 |
|
|
Aug 24 02:46:16 PM UTC 24 |
Aug 24 03:38:07 PM UTC 24 |
14740288696 ps |
| T1296 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/4.chip_sw_uart_tx_rx_alt_clk_freq.1069557481 |
|
|
Aug 24 03:19:54 PM UTC 24 |
Aug 24 03:39:11 PM UTC 24 |
8731517814 ps |
| T1297 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/4.chip_tap_straps_prod.2989148551 |
|
|
Aug 24 03:27:07 PM UTC 24 |
Aug 24 03:39:40 PM UTC 24 |
11848055180 ps |
| T686 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/7.chip_sw_all_escalation_resets.1148209441 |
|
|
Aug 24 03:34:07 PM UTC 24 |
Aug 24 03:39:50 PM UTC 24 |
5477921856 ps |
| T1298 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/7.chip_sw_lc_ctrl_transition.36318549 |
|
|
Aug 24 03:34:54 PM UTC 24 |
Aug 24 03:40:09 PM UTC 24 |
5657233794 ps |
| T1299 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/5.chip_sw_lc_ctrl_transition.3021946882 |
|
|
Aug 24 03:29:02 PM UTC 24 |
Aug 24 03:40:13 PM UTC 24 |
9014745259 ps |
| T757 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/7.chip_sw_alert_handler_lpg_sleep_mode_alerts.1243056365 |
|
|
Aug 24 03:35:17 PM UTC 24 |
Aug 24 03:40:35 PM UTC 24 |
4059387112 ps |
| T669 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/8.chip_sw_alert_handler_lpg_sleep_mode_alerts.2801983277 |
|
|
Aug 24 03:36:21 PM UTC 24 |
Aug 24 03:41:18 PM UTC 24 |
3873183460 ps |
| T202 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/9.chip_sw_all_escalation_resets.2457006683 |
|
|
Aug 24 03:36:42 PM UTC 24 |
Aug 24 03:42:48 PM UTC 24 |
4871250050 ps |
| T381 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/8.chip_sw_all_escalation_resets.3812758255 |
|
|
Aug 24 03:35:55 PM UTC 24 |
Aug 24 03:43:18 PM UTC 24 |
5569998380 ps |
| T776 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/9.chip_sw_alert_handler_lpg_sleep_mode_alerts.3279622681 |
|
|
Aug 24 03:38:11 PM UTC 24 |
Aug 24 03:43:21 PM UTC 24 |
4374703168 ps |
| T1300 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/8.chip_sw_lc_ctrl_transition.1099423496 |
|
|
Aug 24 03:36:22 PM UTC 24 |
Aug 24 03:43:50 PM UTC 24 |
8449589673 ps |
| T1301 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/9.chip_sw_uart_rand_baudrate.2821548902 |
|
|
Aug 24 03:36:42 PM UTC 24 |
Aug 24 03:43:51 PM UTC 24 |
4653034330 ps |
| T766 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/10.chip_sw_alert_handler_lpg_sleep_mode_alerts.1832799366 |
|
|
Aug 24 03:40:04 PM UTC 24 |
Aug 24 03:44:28 PM UTC 24 |
3774814150 ps |
| T1302 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_exit_test_unlocked_bootstrap.3716670402 |
|
|
Aug 24 12:56:22 PM UTC 24 |
Aug 24 03:44:28 PM UTC 24 |
59974351814 ps |
| T1303 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/2.rom_e2e_static_critical.3373985852 |
|
|
Aug 24 02:45:46 PM UTC 24 |
Aug 24 03:44:47 PM UTC 24 |
17769347960 ps |
| T711 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/10.chip_sw_all_escalation_resets.2526818020 |
|
|
Aug 24 03:38:11 PM UTC 24 |
Aug 24 03:45:54 PM UTC 24 |
6352260932 ps |
| T1304 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/9.chip_sw_lc_ctrl_transition.450619995 |
|
|
Aug 24 03:37:12 PM UTC 24 |
Aug 24 03:45:57 PM UTC 24 |
11985981806 ps |
| T109 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/11.chip_sw_alert_handler_lpg_sleep_mode_alerts.1990323089 |
|
|
Aug 24 03:41:00 PM UTC 24 |
Aug 24 03:46:24 PM UTC 24 |
3714134288 ps |
| T116 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/11.chip_sw_lc_ctrl_transition.2359346099 |
|
|
Aug 24 03:40:41 PM UTC 24 |
Aug 24 03:46:26 PM UTC 24 |
5175512138 ps |
| T117 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/11.chip_sw_uart_rand_baudrate.1030954723 |
|
|
Aug 24 03:40:41 PM UTC 24 |
Aug 24 03:47:02 PM UTC 24 |
4052683280 ps |
| T118 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/12.chip_sw_all_escalation_resets.3151326193 |
|
|
Aug 24 03:41:43 PM UTC 24 |
Aug 24 03:48:07 PM UTC 24 |
4129988170 ps |
| T119 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/11.chip_sw_all_escalation_resets.1148703892 |
|
|
Aug 24 03:40:16 PM UTC 24 |
Aug 24 03:48:20 PM UTC 24 |
5579561700 ps |
| T120 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/12.chip_sw_alert_handler_lpg_sleep_mode_alerts.1115893414 |
|
|
Aug 24 03:43:50 PM UTC 24 |
Aug 24 03:48:51 PM UTC 24 |
3915823370 ps |
| T121 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/12.chip_sw_lc_ctrl_transition.3843689910 |
|
|
Aug 24 03:43:50 PM UTC 24 |
Aug 24 03:49:47 PM UTC 24 |
6000814556 ps |
| T122 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/13.chip_sw_lc_ctrl_transition.3388832155 |
|
|
Aug 24 03:45:00 PM UTC 24 |
Aug 24 03:49:53 PM UTC 24 |
5590241058 ps |
| T123 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/10.chip_sw_lc_ctrl_transition.2769339345 |
|
|
Aug 24 03:39:35 PM UTC 24 |
Aug 24 03:50:33 PM UTC 24 |
9046599690 ps |
| T124 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/13.chip_sw_alert_handler_lpg_sleep_mode_alerts.584111278 |
|
|
Aug 24 03:45:00 PM UTC 24 |
Aug 24 03:50:33 PM UTC 24 |
4055322716 ps |
| T1305 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/12.chip_sw_uart_rand_baudrate.601530532 |
|
|
Aug 24 03:43:13 PM UTC 24 |
Aug 24 03:51:10 PM UTC 24 |
4211862912 ps |
| T1306 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/6.chip_sw_uart_rand_baudrate.3100563874 |
|
|
Aug 24 03:30:58 PM UTC 24 |
Aug 24 03:51:36 PM UTC 24 |
7927503448 ps |
| T1307 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/7.chip_sw_uart_rand_baudrate.2855354198 |
|
|
Aug 24 03:34:45 PM UTC 24 |
Aug 24 03:51:46 PM UTC 24 |
8306323006 ps |
| T673 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/14.chip_sw_alert_handler_lpg_sleep_mode_alerts.778216331 |
|
|
Aug 24 03:46:57 PM UTC 24 |
Aug 24 03:51:58 PM UTC 24 |
3869363354 ps |
| T759 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/13.chip_sw_all_escalation_resets.2661478892 |
|
|
Aug 24 03:44:23 PM UTC 24 |
Aug 24 03:52:17 PM UTC 24 |
5218271320 ps |
| T733 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/15.chip_sw_alert_handler_lpg_sleep_mode_alerts.1515883749 |
|
|
Aug 24 03:48:31 PM UTC 24 |
Aug 24 03:53:16 PM UTC 24 |
3350129344 ps |
| T687 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/14.chip_sw_all_escalation_resets.1640888514 |
|
|
Aug 24 03:45:13 PM UTC 24 |
Aug 24 03:53:30 PM UTC 24 |
5370751570 ps |
| T1308 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/15.chip_sw_uart_rand_baudrate.2087588302 |
|
|
Aug 24 03:47:26 PM UTC 24 |
Aug 24 03:54:10 PM UTC 24 |
4311316952 ps |
| T779 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/16.chip_sw_alert_handler_lpg_sleep_mode_alerts.1267273550 |
|
|
Aug 24 03:50:21 PM UTC 24 |
Aug 24 03:55:07 PM UTC 24 |
3296597568 ps |
| T682 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/15.chip_sw_all_escalation_resets.2343976130 |
|
|
Aug 24 03:46:57 PM UTC 24 |
Aug 24 03:55:43 PM UTC 24 |
5960558336 ps |
| T758 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/17.chip_sw_alert_handler_lpg_sleep_mode_alerts.3249149433 |
|
|
Aug 24 03:51:06 PM UTC 24 |
Aug 24 03:55:43 PM UTC 24 |
3359685496 ps |
| T688 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/16.chip_sw_all_escalation_resets.217783659 |
|
|
Aug 24 03:48:45 PM UTC 24 |
Aug 24 03:55:52 PM UTC 24 |
5178921148 ps |
| T721 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/18.chip_sw_alert_handler_lpg_sleep_mode_alerts.4038179267 |
|
|
Aug 24 03:52:11 PM UTC 24 |
Aug 24 03:56:25 PM UTC 24 |
3555643770 ps |
| T1309 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/10.chip_sw_uart_rand_baudrate.2161645702 |
|
|
Aug 24 03:38:32 PM UTC 24 |
Aug 24 03:57:16 PM UTC 24 |
8817306736 ps |
| T1310 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/14.chip_sw_lc_ctrl_transition.1153638653 |
|
|
Aug 24 03:46:26 PM UTC 24 |
Aug 24 03:57:17 PM UTC 24 |
12526944444 ps |
| T1311 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/18.chip_sw_all_escalation_resets.237840929 |
|
|
Aug 24 03:51:35 PM UTC 24 |
Aug 24 03:57:39 PM UTC 24 |
4601269600 ps |
| T1312 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/19.chip_sw_uart_rand_baudrate.1538892161 |
|
|
Aug 24 03:52:43 PM UTC 24 |
Aug 24 03:58:21 PM UTC 24 |
3342654124 ps |
| T700 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/19.chip_sw_alert_handler_lpg_sleep_mode_alerts.2547997285 |
|
|
Aug 24 03:53:40 PM UTC 24 |
Aug 24 03:58:23 PM UTC 24 |
3887192554 ps |
| T774 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/17.chip_sw_all_escalation_resets.3634041092 |
|
|
Aug 24 03:50:21 PM UTC 24 |
Aug 24 03:58:28 PM UTC 24 |
5189026720 ps |
| T1313 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_inject_scramble_seed.2823145329 |
|
|
Aug 24 12:55:50 PM UTC 24 |
Aug 24 03:58:28 PM UTC 24 |
66449687777 ps |
| T767 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/20.chip_sw_alert_handler_lpg_sleep_mode_alerts.592397183 |
|
|
Aug 24 03:54:34 PM UTC 24 |
Aug 24 03:59:19 PM UTC 24 |
3680398854 ps |
| T689 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/19.chip_sw_all_escalation_resets.1885449069 |
|
|
Aug 24 03:52:23 PM UTC 24 |
Aug 24 03:59:50 PM UTC 24 |
4846543368 ps |
| T690 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/20.chip_sw_all_escalation_resets.1027707118 |
|
|
Aug 24 03:53:55 PM UTC 24 |
Aug 24 04:00:43 PM UTC 24 |
4477680848 ps |
| T712 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/22.chip_sw_alert_handler_lpg_sleep_mode_alerts.3818279748 |
|
|
Aug 24 03:56:26 PM UTC 24 |
Aug 24 04:00:47 PM UTC 24 |
3749674794 ps |
| T731 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/21.chip_sw_alert_handler_lpg_sleep_mode_alerts.3463480088 |
|
|
Aug 24 03:56:25 PM UTC 24 |
Aug 24 04:01:55 PM UTC 24 |
4254971752 ps |
| T702 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/23.chip_sw_alert_handler_lpg_sleep_mode_alerts.402021901 |
|
|
Aug 24 03:57:50 PM UTC 24 |
Aug 24 04:02:08 PM UTC 24 |
3489464256 ps |
| T1314 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/13.chip_sw_uart_rand_baudrate.314757720 |
|
|
Aug 24 03:44:24 PM UTC 24 |
Aug 24 04:02:14 PM UTC 24 |
8696474512 ps |
| T768 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/24.chip_sw_alert_handler_lpg_sleep_mode_alerts.1805683873 |
|
|
Aug 24 03:58:03 PM UTC 24 |
Aug 24 04:03:05 PM UTC 24 |
4312729016 ps |
| T1315 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/21.chip_sw_all_escalation_resets.1032472092 |
|
|
Aug 24 03:55:32 PM UTC 24 |
Aug 24 04:03:16 PM UTC 24 |
5171511200 ps |
| T665 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/26.chip_sw_alert_handler_lpg_sleep_mode_alerts.4105029732 |
|
|
Aug 24 03:59:13 PM UTC 24 |
Aug 24 04:03:34 PM UTC 24 |
4007495912 ps |
| T691 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/25.chip_sw_alert_handler_lpg_sleep_mode_alerts.3908453056 |
|
|
Aug 24 03:59:13 PM UTC 24 |
Aug 24 04:03:41 PM UTC 24 |
3507780548 ps |
| T705 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/24.chip_sw_all_escalation_resets.1308636880 |
|
|
Aug 24 03:57:49 PM UTC 24 |
Aug 24 04:03:51 PM UTC 24 |
4879998504 ps |
| T738 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/27.chip_sw_alert_handler_lpg_sleep_mode_alerts.3263945183 |
|
|
Aug 24 04:00:14 PM UTC 24 |
Aug 24 04:04:00 PM UTC 24 |
3199744680 ps |
| T1316 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/14.chip_sw_uart_rand_baudrate.3933316929 |
|
|
Aug 24 03:46:26 PM UTC 24 |
Aug 24 04:04:58 PM UTC 24 |
7935659764 ps |
| T680 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/22.chip_sw_all_escalation_resets.3883848882 |
|
|
Aug 24 03:56:24 PM UTC 24 |
Aug 24 04:05:20 PM UTC 24 |
5881295656 ps |
| T1317 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/26.chip_sw_all_escalation_resets.3141582058 |
|
|
Aug 24 03:59:12 PM UTC 24 |
Aug 24 04:05:55 PM UTC 24 |
4803608360 ps |
| T1318 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/25.chip_sw_all_escalation_resets.2805677465 |
|
|
Aug 24 03:59:11 PM UTC 24 |
Aug 24 04:06:05 PM UTC 24 |
5396658044 ps |
| T110 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/28.chip_sw_alert_handler_lpg_sleep_mode_alerts.2585467461 |
|
|
Aug 24 04:01:15 PM UTC 24 |
Aug 24 04:06:22 PM UTC 24 |
3769234856 ps |
| T263 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/29.chip_sw_alert_handler_lpg_sleep_mode_alerts.2426581878 |
|
|
Aug 24 04:02:20 PM UTC 24 |
Aug 24 04:07:01 PM UTC 24 |
4295662288 ps |
| T289 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/30.chip_sw_alert_handler_lpg_sleep_mode_alerts.2470701908 |
|
|
Aug 24 04:02:42 PM UTC 24 |
Aug 24 04:07:25 PM UTC 24 |
3870537552 ps |
| T290 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/28.chip_sw_all_escalation_resets.2614879375 |
|
|
Aug 24 04:00:53 PM UTC 24 |
Aug 24 04:07:57 PM UTC 24 |
4968087380 ps |
| T291 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/8.chip_sw_uart_rand_baudrate.1187139424 |
|
|
Aug 24 03:36:22 PM UTC 24 |
Aug 24 04:07:58 PM UTC 24 |
12912094954 ps |
| T264 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/27.chip_sw_all_escalation_resets.2050183503 |
|
|
Aug 24 03:59:44 PM UTC 24 |
Aug 24 04:08:16 PM UTC 24 |
5798826756 ps |
| T292 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/32.chip_sw_alert_handler_lpg_sleep_mode_alerts.3303378146 |
|
|
Aug 24 04:04:23 PM UTC 24 |
Aug 24 04:08:16 PM UTC 24 |
3869502512 ps |
| T293 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/31.chip_sw_alert_handler_lpg_sleep_mode_alerts.2672000132 |
|
|
Aug 24 04:03:41 PM UTC 24 |
Aug 24 04:08:16 PM UTC 24 |
3270130584 ps |
| T294 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/30.chip_sw_all_escalation_resets.1916372907 |
|
|
Aug 24 04:02:42 PM UTC 24 |
Aug 24 04:08:44 PM UTC 24 |
4236621008 ps |
| T295 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/33.chip_sw_alert_handler_lpg_sleep_mode_alerts.2596330606 |
|
|
Aug 24 04:04:27 PM UTC 24 |
Aug 24 04:09:26 PM UTC 24 |
3770092370 ps |
| T296 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/18.chip_sw_uart_rand_baudrate.2569196489 |
|
|
Aug 24 03:52:01 PM UTC 24 |
Aug 24 04:09:27 PM UTC 24 |
7640135516 ps |
| T708 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/34.chip_sw_alert_handler_lpg_sleep_mode_alerts.3441563907 |
|
|
Aug 24 04:05:45 PM UTC 24 |
Aug 24 04:09:40 PM UTC 24 |
3842603192 ps |
| T390 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/36.chip_sw_alert_handler_lpg_sleep_mode_alerts.2698080702 |
|
|
Aug 24 04:06:47 PM UTC 24 |
Aug 24 04:11:29 PM UTC 24 |
3849973636 ps |
| T393 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/35.chip_sw_alert_handler_lpg_sleep_mode_alerts.3407847820 |
|
|
Aug 24 04:06:19 PM UTC 24 |
Aug 24 04:11:35 PM UTC 24 |
3509405110 ps |
| T391 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/37.chip_sw_alert_handler_lpg_sleep_mode_alerts.2980565882 |
|
|
Aug 24 04:07:27 PM UTC 24 |
Aug 24 04:11:56 PM UTC 24 |
3806691212 ps |
| T394 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/32.chip_sw_all_escalation_resets.3283721906 |
|
|
Aug 24 04:04:15 PM UTC 24 |
Aug 24 04:11:57 PM UTC 24 |
5001941380 ps |
| T395 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/33.chip_sw_all_escalation_resets.2774427857 |
|
|
Aug 24 04:04:27 PM UTC 24 |
Aug 24 04:12:08 PM UTC 24 |
4506049560 ps |
| T111 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/34.chip_sw_all_escalation_resets.4044032290 |
|
|
Aug 24 04:05:23 PM UTC 24 |
Aug 24 04:12:15 PM UTC 24 |
6215988710 ps |
| T396 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/40.chip_sw_alert_handler_lpg_sleep_mode_alerts.498213852 |
|
|
Aug 24 04:08:58 PM UTC 24 |
Aug 24 04:13:14 PM UTC 24 |
3897189664 ps |
| T397 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/35.chip_sw_all_escalation_resets.1616881063 |
|
|
Aug 24 04:05:58 PM UTC 24 |
Aug 24 04:13:30 PM UTC 24 |
5254028032 ps |
| T398 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/38.chip_sw_alert_handler_lpg_sleep_mode_alerts.3380280106 |
|
|
Aug 24 04:08:29 PM UTC 24 |
Aug 24 04:13:53 PM UTC 24 |
4225605890 ps |
| T399 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/39.chip_sw_alert_handler_lpg_sleep_mode_alerts.3343620601 |
|
|
Aug 24 04:08:58 PM UTC 24 |
Aug 24 04:14:00 PM UTC 24 |
4257810840 ps |
| T756 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/42.chip_sw_alert_handler_lpg_sleep_mode_alerts.1750909917 |
|
|
Aug 24 04:10:09 PM UTC 24 |
Aug 24 04:14:32 PM UTC 24 |
3288979828 ps |
| T745 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/41.chip_sw_alert_handler_lpg_sleep_mode_alerts.3029900001 |
|
|
Aug 24 04:10:08 PM UTC 24 |
Aug 24 04:14:46 PM UTC 24 |
4224301240 ps |
| T265 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/39.chip_sw_all_escalation_resets.960484165 |
|
|
Aug 24 04:08:30 PM UTC 24 |
Aug 24 04:15:04 PM UTC 24 |
4557704528 ps |
| T1319 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/36.chip_sw_all_escalation_resets.1880435650 |
|
|
Aug 24 04:06:31 PM UTC 24 |
Aug 24 04:15:11 PM UTC 24 |
5571421546 ps |
| T777 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/37.chip_sw_all_escalation_resets.3427026818 |
|
|
Aug 24 04:07:26 PM UTC 24 |
Aug 24 04:15:21 PM UTC 24 |
5160474832 ps |
| T763 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/41.chip_sw_all_escalation_resets.2583133257 |
|
|
Aug 24 04:09:09 PM UTC 24 |
Aug 24 04:15:25 PM UTC 24 |
5411707928 ps |
| T1320 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/2.rom_e2e_self_hash.2833828422 |
|
|
Aug 24 02:49:38 PM UTC 24 |
Aug 24 04:15:35 PM UTC 24 |
26515973240 ps |
| T685 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/38.chip_sw_all_escalation_resets.2355852049 |
|
|
Aug 24 04:07:51 PM UTC 24 |
Aug 24 04:15:44 PM UTC 24 |
4817528536 ps |
| T1321 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/40.chip_sw_all_escalation_resets.2807570171 |
|
|
Aug 24 04:08:57 PM UTC 24 |
Aug 24 04:16:03 PM UTC 24 |
5700154828 ps |
| T203 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/42.chip_sw_all_escalation_resets.1913247280 |
|
|
Aug 24 04:10:09 PM UTC 24 |
Aug 24 04:16:06 PM UTC 24 |
5498624372 ps |
| T692 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/43.chip_sw_alert_handler_lpg_sleep_mode_alerts.748070643 |
|
|
Aug 24 04:12:03 PM UTC 24 |
Aug 24 04:16:58 PM UTC 24 |
4199885010 ps |
| T749 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/45.chip_sw_alert_handler_lpg_sleep_mode_alerts.3511579083 |
|
|
Aug 24 04:12:50 PM UTC 24 |
Aug 24 04:17:02 PM UTC 24 |
3576109972 ps |
| T735 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/46.chip_sw_alert_handler_lpg_sleep_mode_alerts.879847666 |
|
|
Aug 24 04:13:55 PM UTC 24 |
Aug 24 04:18:42 PM UTC 24 |
3403161876 ps |
| T275 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/44.chip_sw_all_escalation_resets.1498988219 |
|
|
Aug 24 04:12:47 PM UTC 24 |
Aug 24 04:18:55 PM UTC 24 |
4744309960 ps |
| T719 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/45.chip_sw_all_escalation_resets.2317497076 |
|
|
Aug 24 04:12:49 PM UTC 24 |
Aug 24 04:19:36 PM UTC 24 |
5131103384 ps |
| T681 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/43.chip_sw_all_escalation_resets.965446880 |
|
|
Aug 24 04:12:03 PM UTC 24 |
Aug 24 04:19:47 PM UTC 24 |
4882087404 ps |
| T709 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/47.chip_sw_alert_handler_lpg_sleep_mode_alerts.3370175152 |
|
|
Aug 24 04:14:26 PM UTC 24 |
Aug 24 04:19:51 PM UTC 24 |
3928613704 ps |
| T1322 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/16.chip_sw_uart_rand_baudrate.824075081 |
|
|
Aug 24 03:49:16 PM UTC 24 |
Aug 24 04:20:39 PM UTC 24 |
13137136800 ps |
| T743 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/48.chip_sw_alert_handler_lpg_sleep_mode_alerts.1519376 |
|
|
Aug 24 04:15:11 PM UTC 24 |
Aug 24 04:20:54 PM UTC 24 |
4188197580 ps |
| T722 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/48.chip_sw_all_escalation_resets.2157648356 |
|
|
Aug 24 04:14:57 PM UTC 24 |
Aug 24 04:21:18 PM UTC 24 |
4591847100 ps |
| T697 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/50.chip_sw_alert_handler_lpg_sleep_mode_alerts.3867431253 |
|
|
Aug 24 04:16:14 PM UTC 24 |
Aug 24 04:21:24 PM UTC 24 |
3466171280 ps |
| T744 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/49.chip_sw_alert_handler_lpg_sleep_mode_alerts.2380995576 |
|
|
Aug 24 04:15:46 PM UTC 24 |
Aug 24 04:21:26 PM UTC 24 |
4025333440 ps |
| T778 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/46.chip_sw_all_escalation_resets.3679725913 |
|
|
Aug 24 04:13:39 PM UTC 24 |
Aug 24 04:21:32 PM UTC 24 |
5898707962 ps |
| T716 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/47.chip_sw_all_escalation_resets.4020949942 |
|
|
Aug 24 04:14:26 PM UTC 24 |
Aug 24 04:21:38 PM UTC 24 |
4931177850 ps |
| T701 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/52.chip_sw_alert_handler_lpg_sleep_mode_alerts.1422333539 |
|
|
Aug 24 04:16:36 PM UTC 24 |
Aug 24 04:21:39 PM UTC 24 |
4391759556 ps |
| T1323 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/9.chip_sw_csrng_edn_concurrency.2080508563 |
|
|
Aug 24 03:38:10 PM UTC 24 |
Aug 24 04:22:01 PM UTC 24 |
12973872008 ps |
| T750 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/53.chip_sw_alert_handler_lpg_sleep_mode_alerts.1714853902 |
|
|
Aug 24 04:17:32 PM UTC 24 |
Aug 24 04:22:11 PM UTC 24 |
3968865872 ps |
| T728 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/51.chip_sw_alert_handler_lpg_sleep_mode_alerts.382879877 |
|
|
Aug 24 04:16:15 PM UTC 24 |
Aug 24 04:22:14 PM UTC 24 |
4069202060 ps |
| T734 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/54.chip_sw_alert_handler_lpg_sleep_mode_alerts.542982684 |
|
|
Aug 24 04:19:06 PM UTC 24 |
Aug 24 04:23:44 PM UTC 24 |
3789303628 ps |
| T771 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/49.chip_sw_all_escalation_resets.1625904321 |
|
|
Aug 24 04:15:44 PM UTC 24 |
Aug 24 04:23:54 PM UTC 24 |
5853887370 ps |
| T1324 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/17.chip_sw_uart_rand_baudrate.757804236 |
|
|
Aug 24 03:51:05 PM UTC 24 |
Aug 24 04:23:58 PM UTC 24 |
12552975732 ps |
| T762 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/50.chip_sw_all_escalation_resets.3792614152 |
|
|
Aug 24 04:16:10 PM UTC 24 |
Aug 24 04:24:08 PM UTC 24 |
5852784072 ps |
| T775 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/52.chip_sw_all_escalation_resets.146512253 |
|
|
Aug 24 04:16:36 PM UTC 24 |
Aug 24 04:24:22 PM UTC 24 |
4929968024 ps |
| T739 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/53.chip_sw_all_escalation_resets.3653429020 |
|
|
Aug 24 04:17:32 PM UTC 24 |
Aug 24 04:24:26 PM UTC 24 |
5016946392 ps |
| T780 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/55.chip_sw_alert_handler_lpg_sleep_mode_alerts.1567220329 |
|
|
Aug 24 04:20:01 PM UTC 24 |
Aug 24 04:24:41 PM UTC 24 |
4167191472 ps |
| T723 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/51.chip_sw_all_escalation_resets.4183666828 |
|
|
Aug 24 04:16:15 PM UTC 24 |
Aug 24 04:24:44 PM UTC 24 |
5157150270 ps |
| T772 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/56.chip_sw_alert_handler_lpg_sleep_mode_alerts.1015442570 |
|
|
Aug 24 04:20:21 PM UTC 24 |
Aug 24 04:25:33 PM UTC 24 |
4012677660 ps |
| T760 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/57.chip_sw_alert_handler_lpg_sleep_mode_alerts.3824512377 |
|
|
Aug 24 04:21:19 PM UTC 24 |
Aug 24 04:26:05 PM UTC 24 |
3598511924 ps |
| T1325 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/6.chip_sw_csrng_edn_concurrency.2856008041 |
|
|
Aug 24 03:33:25 PM UTC 24 |
Aug 24 04:26:30 PM UTC 24 |
17410648912 ps |
| T112 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/55.chip_sw_all_escalation_resets.2189564879 |
|
|
Aug 24 04:19:20 PM UTC 24 |
Aug 24 04:26:56 PM UTC 24 |
5524855970 ps |
| T1326 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/60.chip_sw_alert_handler_lpg_sleep_mode_alerts.257299085 |
|
|
Aug 24 04:22:54 PM UTC 24 |
Aug 24 04:26:59 PM UTC 24 |
3681740902 ps |
| T1327 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/59.chip_sw_alert_handler_lpg_sleep_mode_alerts.393659049 |
|
|
Aug 24 04:22:41 PM UTC 24 |
Aug 24 04:27:02 PM UTC 24 |
3273666600 ps |
| T724 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/58.chip_sw_alert_handler_lpg_sleep_mode_alerts.3979296303 |
|
|
Aug 24 04:22:39 PM UTC 24 |
Aug 24 04:27:03 PM UTC 24 |
3388628600 ps |
| T1328 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/54.chip_sw_all_escalation_resets.410014666 |
|
|
Aug 24 04:18:45 PM UTC 24 |
Aug 24 04:27:10 PM UTC 24 |
4843703514 ps |
| T670 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/56.chip_sw_all_escalation_resets.2673528612 |
|
|
Aug 24 04:20:21 PM UTC 24 |
Aug 24 04:27:22 PM UTC 24 |
5640697326 ps |
| T713 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/61.chip_sw_alert_handler_lpg_sleep_mode_alerts.480426606 |
|
|
Aug 24 04:22:58 PM UTC 24 |
Aug 24 04:27:41 PM UTC 24 |
3965130284 ps |
| T1329 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/7.chip_sw_csrng_edn_concurrency.1342294731 |
|
|
Aug 24 03:35:29 PM UTC 24 |
Aug 24 04:27:53 PM UTC 24 |
16761170810 ps |
| T736 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/57.chip_sw_all_escalation_resets.3146334477 |
|
|
Aug 24 04:21:03 PM UTC 24 |
Aug 24 04:28:44 PM UTC 24 |
5445201602 ps |
| T668 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/63.chip_sw_alert_handler_lpg_sleep_mode_alerts.738500998 |
|
|
Aug 24 04:24:36 PM UTC 24 |
Aug 24 04:28:55 PM UTC 24 |
3645527144 ps |
| T714 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/62.chip_sw_alert_handler_lpg_sleep_mode_alerts.2045032003 |
|
|
Aug 24 04:24:08 PM UTC 24 |
Aug 24 04:29:17 PM UTC 24 |
3633638372 ps |
| T732 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/64.chip_sw_alert_handler_lpg_sleep_mode_alerts.339639813 |
|
|
Aug 24 04:24:55 PM UTC 24 |
Aug 24 04:29:42 PM UTC 24 |
3747566416 ps |
| T348 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/61.chip_sw_all_escalation_resets.3711193697 |
|
|
Aug 24 04:22:56 PM UTC 24 |
Aug 24 04:30:08 PM UTC 24 |
4306058074 ps |
| T351 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/66.chip_sw_alert_handler_lpg_sleep_mode_alerts.1853042096 |
|
|
Aug 24 04:25:58 PM UTC 24 |
Aug 24 04:30:22 PM UTC 24 |
4155809048 ps |
| T352 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/65.chip_sw_alert_handler_lpg_sleep_mode_alerts.897368997 |
|
|
Aug 24 04:25:13 PM UTC 24 |
Aug 24 04:30:24 PM UTC 24 |
4092786104 ps |
| T353 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/64.chip_sw_all_escalation_resets.1348638612 |
|
|
Aug 24 04:24:37 PM UTC 24 |
Aug 24 04:30:34 PM UTC 24 |
4663517158 ps |
| T354 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/58.chip_sw_all_escalation_resets.3348281141 |
|
|
Aug 24 04:22:40 PM UTC 24 |
Aug 24 04:30:38 PM UTC 24 |
5151265106 ps |
| T355 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/59.chip_sw_all_escalation_resets.219865261 |
|
|
Aug 24 04:22:53 PM UTC 24 |
Aug 24 04:30:48 PM UTC 24 |
5542399762 ps |
| T356 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/62.chip_sw_all_escalation_resets.628276662 |
|
|
Aug 24 04:22:56 PM UTC 24 |
Aug 24 04:30:49 PM UTC 24 |
5326674944 ps |
| T357 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/60.chip_sw_all_escalation_resets.41396714 |
|
|
Aug 24 04:22:50 PM UTC 24 |
Aug 24 04:31:02 PM UTC 24 |
6410548672 ps |
| T358 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/65.chip_sw_all_escalation_resets.2112622173 |
|
|
Aug 24 04:24:55 PM UTC 24 |
Aug 24 04:31:43 PM UTC 24 |
4587273372 ps |
| T359 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/63.chip_sw_all_escalation_resets.882374669 |
|
|
Aug 24 04:24:36 PM UTC 24 |
Aug 24 04:32:15 PM UTC 24 |
4664065240 ps |
| T1330 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/67.chip_sw_alert_handler_lpg_sleep_mode_alerts.1402208816 |
|
|
Aug 24 04:26:54 PM UTC 24 |
Aug 24 04:32:35 PM UTC 24 |
4215532464 ps |
| T287 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/71.chip_sw_alert_handler_lpg_sleep_mode_alerts.2470699943 |
|
|
Aug 24 04:28:24 PM UTC 24 |
Aug 24 04:33:06 PM UTC 24 |
3716163328 ps |
| T747 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/70.chip_sw_alert_handler_lpg_sleep_mode_alerts.715194308 |
|
|
Aug 24 04:28:11 PM UTC 24 |
Aug 24 04:33:10 PM UTC 24 |
3684723878 ps |
| T752 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/69.chip_sw_alert_handler_lpg_sleep_mode_alerts.3599346621 |
|
|
Aug 24 04:28:11 PM UTC 24 |
Aug 24 04:33:14 PM UTC 24 |
3491231732 ps |
| T1331 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/68.chip_sw_alert_handler_lpg_sleep_mode_alerts.167645286 |
|
|
Aug 24 04:28:12 PM UTC 24 |
Aug 24 04:33:17 PM UTC 24 |
4400443200 ps |
| T288 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/66.chip_sw_all_escalation_resets.1094769222 |
|
|
Aug 24 04:25:14 PM UTC 24 |
Aug 24 04:33:22 PM UTC 24 |
5262106838 ps |
| T725 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/72.chip_sw_alert_handler_lpg_sleep_mode_alerts.1563118306 |
|
|
Aug 24 04:29:19 PM UTC 24 |
Aug 24 04:34:04 PM UTC 24 |
3693116298 ps |
| T258 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/67.chip_sw_all_escalation_resets.3131186134 |
|
|
Aug 24 04:26:31 PM UTC 24 |
Aug 24 04:34:15 PM UTC 24 |
5068427730 ps |
| T1332 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/8.chip_sw_csrng_edn_concurrency.1607290467 |
|
|
Aug 24 03:36:38 PM UTC 24 |
Aug 24 04:34:23 PM UTC 24 |
20295049720 ps |
| T781 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/69.chip_sw_all_escalation_resets.2405148763 |
|
|
Aug 24 04:28:22 PM UTC 24 |
Aug 24 04:34:28 PM UTC 24 |
4416572616 ps |
| T740 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/72.chip_sw_all_escalation_resets.3973612986 |
|
|
Aug 24 04:29:09 PM UTC 24 |
Aug 24 04:34:46 PM UTC 24 |
4095544376 ps |
| T761 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/70.chip_sw_all_escalation_resets.917100812 |
|
|
Aug 24 04:28:10 PM UTC 24 |
Aug 24 04:35:11 PM UTC 24 |
4648469260 ps |
| T741 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/68.chip_sw_all_escalation_resets.4254017977 |
|
|
Aug 24 04:28:10 PM UTC 24 |
Aug 24 04:35:27 PM UTC 24 |
5855050124 ps |
| T683 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/73.chip_sw_alert_handler_lpg_sleep_mode_alerts.1749799388 |
|
|
Aug 24 04:30:06 PM UTC 24 |
Aug 24 04:35:29 PM UTC 24 |
3700704078 ps |
| T703 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/71.chip_sw_all_escalation_resets.2831409722 |
|
|
Aug 24 04:28:25 PM UTC 24 |
Aug 24 04:35:43 PM UTC 24 |
6105998768 ps |
| T754 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/74.chip_sw_alert_handler_lpg_sleep_mode_alerts.1323081987 |
|
|
Aug 24 04:31:38 PM UTC 24 |
Aug 24 04:35:47 PM UTC 24 |
3622856664 ps |
| T698 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/77.chip_sw_alert_handler_lpg_sleep_mode_alerts.2586444577 |
|
|
Aug 24 04:31:38 PM UTC 24 |
Aug 24 04:35:50 PM UTC 24 |
3745060494 ps |
| T695 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/75.chip_sw_alert_handler_lpg_sleep_mode_alerts.1672639718 |
|
|
Aug 24 04:31:33 PM UTC 24 |
Aug 24 04:36:06 PM UTC 24 |
3242590112 ps |
| T671 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/73.chip_sw_all_escalation_resets.903419031 |
|
|
Aug 24 04:29:42 PM UTC 24 |
Aug 24 04:36:10 PM UTC 24 |
4219230138 ps |
| T1333 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/4.chip_sw_csrng_edn_concurrency.4225787017 |
|
|
Aug 24 03:24:15 PM UTC 24 |
Aug 24 04:36:11 PM UTC 24 |
22242419768 ps |
| T693 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/76.chip_sw_alert_handler_lpg_sleep_mode_alerts.716314035 |
|
|
Aug 24 04:31:40 PM UTC 24 |
Aug 24 04:36:15 PM UTC 24 |
3119049984 ps |
| T706 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/78.chip_sw_alert_handler_lpg_sleep_mode_alerts.3861271096 |
|
|
Aug 24 04:32:40 PM UTC 24 |
Aug 24 04:36:58 PM UTC 24 |
4058853496 ps |
| T718 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/74.chip_sw_all_escalation_resets.604067042 |
|
|
Aug 24 04:30:34 PM UTC 24 |
Aug 24 04:37:01 PM UTC 24 |
5221480228 ps |
| T755 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/79.chip_sw_alert_handler_lpg_sleep_mode_alerts.4191386502 |
|
|
Aug 24 04:34:06 PM UTC 24 |
Aug 24 04:38:08 PM UTC 24 |
3673555176 ps |
| T715 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/81.chip_sw_alert_handler_lpg_sleep_mode_alerts.176388028 |
|
|
Aug 24 04:34:07 PM UTC 24 |
Aug 24 04:38:30 PM UTC 24 |
4056813800 ps |
| T684 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/80.chip_sw_alert_handler_lpg_sleep_mode_alerts.2151003359 |
|
|
Aug 24 04:34:04 PM UTC 24 |
Aug 24 04:38:34 PM UTC 24 |
3938720526 ps |
| T1334 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/83.chip_sw_alert_handler_lpg_sleep_mode_alerts.3687036068 |
|
|
Aug 24 04:34:58 PM UTC 24 |
Aug 24 04:38:40 PM UTC 24 |
3261102524 ps |
| T276 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/79.chip_sw_all_escalation_resets.1825370467 |
|
|
Aug 24 04:33:00 PM UTC 24 |
Aug 24 04:38:40 PM UTC 24 |
4270892514 ps |
| T1335 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/77.chip_sw_all_escalation_resets.1776247634 |
|
|
Aug 24 04:31:32 PM UTC 24 |
Aug 24 04:38:57 PM UTC 24 |
6069877056 ps |
| T1336 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/78.chip_sw_all_escalation_resets.2960461907 |
|
|
Aug 24 04:32:08 PM UTC 24 |
Aug 24 04:39:00 PM UTC 24 |
4399388200 ps |
| T699 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/82.chip_sw_alert_handler_lpg_sleep_mode_alerts.852626462 |
|
|
Aug 24 04:34:57 PM UTC 24 |
Aug 24 04:39:11 PM UTC 24 |
3968407202 ps |
| T753 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/76.chip_sw_all_escalation_resets.1647611563 |
|
|
Aug 24 04:31:39 PM UTC 24 |
Aug 24 04:39:20 PM UTC 24 |
5667051000 ps |
| T730 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/75.chip_sw_all_escalation_resets.976706224 |
|
|
Aug 24 04:31:38 PM UTC 24 |
Aug 24 04:39:37 PM UTC 24 |
5269390928 ps |
| T737 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/84.chip_sw_alert_handler_lpg_sleep_mode_alerts.3982443009 |
|
|
Aug 24 04:35:35 PM UTC 24 |
Aug 24 04:39:48 PM UTC 24 |
3497683240 ps |
| T726 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/81.chip_sw_all_escalation_resets.925273160 |
|
|
Aug 24 04:34:06 PM UTC 24 |
Aug 24 04:40:04 PM UTC 24 |
4310207100 ps |
| T113 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/84.chip_sw_all_escalation_resets.3609052144 |
|
|
Aug 24 04:35:12 PM UTC 24 |
Aug 24 04:40:35 PM UTC 24 |
4213811344 ps |
| T694 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/87.chip_sw_alert_handler_lpg_sleep_mode_alerts.2063133939 |
|
|
Aug 24 04:37:00 PM UTC 24 |
Aug 24 04:41:19 PM UTC 24 |
3308801376 ps |
| T349 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/85.chip_sw_alert_handler_lpg_sleep_mode_alerts.3214357835 |
|
|
Aug 24 04:36:52 PM UTC 24 |
Aug 24 04:41:22 PM UTC 24 |
4092603694 ps |
| T717 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/88.chip_sw_alert_handler_lpg_sleep_mode_alerts.2642279687 |
|
|
Aug 24 04:37:02 PM UTC 24 |
Aug 24 04:41:28 PM UTC 24 |
3800422992 ps |
| T1337 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/80.chip_sw_all_escalation_resets.2123021211 |
|
|
Aug 24 04:34:05 PM UTC 24 |
Aug 24 04:41:50 PM UTC 24 |
5762356736 ps |
| T729 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/83.chip_sw_all_escalation_resets.4113805896 |
|
|
Aug 24 04:34:58 PM UTC 24 |
Aug 24 04:41:52 PM UTC 24 |
4692146644 ps |
| T769 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/86.chip_sw_alert_handler_lpg_sleep_mode_alerts.2583764149 |
|
|
Aug 24 04:37:02 PM UTC 24 |
Aug 24 04:42:09 PM UTC 24 |
4039979214 ps |
| T727 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/89.chip_sw_alert_handler_lpg_sleep_mode_alerts.1522244701 |
|
|
Aug 24 04:37:31 PM UTC 24 |
Aug 24 04:42:19 PM UTC 24 |
3885385590 ps |
| T1338 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/85.chip_sw_all_escalation_resets.3998610853 |
|
|
Aug 24 04:36:36 PM UTC 24 |
Aug 24 04:42:44 PM UTC 24 |
4841170552 ps |