| T1339 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/3.chip_sw_csrng_edn_concurrency.507371468 |
|
|
Aug 24 03:11:55 PM UTC 24 |
Aug 24 04:42:49 PM UTC 24 |
27320957108 ps |
| T666 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/82.chip_sw_all_escalation_resets.2772701826 |
|
|
Aug 24 04:34:29 PM UTC 24 |
Aug 24 04:42:50 PM UTC 24 |
4907591890 ps |
| T114 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/87.chip_sw_all_escalation_resets.2650556735 |
|
|
Aug 24 04:37:01 PM UTC 24 |
Aug 24 04:43:07 PM UTC 24 |
4478617228 ps |
| T115 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/91.chip_sw_all_escalation_resets.2167387569 |
|
|
Aug 24 04:38:32 PM UTC 24 |
Aug 24 04:43:43 PM UTC 24 |
4063919202 ps |
| T392 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/88.chip_sw_all_escalation_resets.3627686406 |
|
|
Aug 24 04:37:05 PM UTC 24 |
Aug 24 04:43:57 PM UTC 24 |
5735363880 ps |
| T277 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/90.chip_sw_all_escalation_resets.129769987 |
|
|
Aug 24 04:37:32 PM UTC 24 |
Aug 24 04:44:25 PM UTC 24 |
4640553856 ps |
| T751 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/89.chip_sw_all_escalation_resets.397846540 |
|
|
Aug 24 04:37:05 PM UTC 24 |
Aug 24 04:44:30 PM UTC 24 |
4856834144 ps |
| T707 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/86.chip_sw_all_escalation_resets.3856535478 |
|
|
Aug 24 04:37:01 PM UTC 24 |
Aug 24 04:45:17 PM UTC 24 |
5861608568 ps |
| T667 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/92.chip_sw_all_escalation_resets.1623400976 |
|
|
Aug 24 04:39:54 PM UTC 24 |
Aug 24 04:45:25 PM UTC 24 |
4243537600 ps |
| T764 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/98.chip_sw_all_escalation_resets.3686751628 |
|
|
Aug 24 04:40:00 PM UTC 24 |
Aug 24 04:45:31 PM UTC 24 |
5361476748 ps |
| T672 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/99.chip_sw_all_escalation_resets.1002550756 |
|
|
Aug 24 04:40:01 PM UTC 24 |
Aug 24 04:45:46 PM UTC 24 |
5635471538 ps |
| T720 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/93.chip_sw_all_escalation_resets.1351210041 |
|
|
Aug 24 04:39:51 PM UTC 24 |
Aug 24 04:46:11 PM UTC 24 |
5528831576 ps |
| T748 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/96.chip_sw_all_escalation_resets.2203366466 |
|
|
Aug 24 04:39:56 PM UTC 24 |
Aug 24 04:46:21 PM UTC 24 |
5898424232 ps |
| T259 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/94.chip_sw_all_escalation_resets.1931622397 |
|
|
Aug 24 04:39:57 PM UTC 24 |
Aug 24 04:46:29 PM UTC 24 |
5760588430 ps |
| T1340 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_uart_tx_rx_bootstrap.3181222662 |
|
|
Aug 24 12:55:14 PM UTC 24 |
Aug 24 04:46:34 PM UTC 24 |
80556567990 ps |
| T260 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/97.chip_sw_all_escalation_resets.3380248194 |
|
|
Aug 24 04:40:01 PM UTC 24 |
Aug 24 04:46:41 PM UTC 24 |
5643153400 ps |
| T350 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/95.chip_sw_all_escalation_resets.3803770928 |
|
|
Aug 24 04:39:49 PM UTC 24 |
Aug 24 04:47:10 PM UTC 24 |
6157963426 ps |
| T1341 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_alert_handler_reverse_ping_in_deep_sleep.1218252920 |
|
|
Aug 24 01:47:09 PM UTC 24 |
Aug 24 04:47:26 PM UTC 24 |
254909919480 ps |
| T1342 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/5.chip_sw_csrng_edn_concurrency.2268021218 |
|
|
Aug 24 03:29:43 PM UTC 24 |
Aug 24 04:58:12 PM UTC 24 |
28516678932 ps |
| T626 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_csrng_edn_concurrency_reduced_freq.4011335849 |
|
|
Aug 24 02:39:46 PM UTC 24 |
Aug 24 07:37:50 PM UTC 24 |
153178968724 ps |
| T102 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/0.xbar_smoke.820882211 |
|
|
Aug 24 03:45:05 AM UTC 24 |
Aug 24 03:45:13 AM UTC 24 |
190967146 ps |
| T103 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/0.xbar_smoke_zero_delays.3447159086 |
|
|
Aug 24 03:45:27 AM UTC 24 |
Aug 24 03:45:33 AM UTC 24 |
46923107 ps |
| T104 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/0.xbar_random.2419486570 |
|
|
Aug 24 03:45:56 AM UTC 24 |
Aug 24 03:46:12 AM UTC 24 |
470545680 ps |
| T105 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/0.chip_tl_errors.1105115296 |
|
|
Aug 24 03:44:19 AM UTC 24 |
Aug 24 03:46:32 AM UTC 24 |
3362027010 ps |
| T162 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/0.xbar_random_zero_delays.889446056 |
|
|
Aug 24 03:46:26 AM UTC 24 |
Aug 24 03:46:43 AM UTC 24 |
199859383 ps |
| T187 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/0.xbar_smoke_slow_rsp.1854343284 |
|
|
Aug 24 03:45:47 AM UTC 24 |
Aug 24 03:46:47 AM UTC 24 |
4948829455 ps |
| T163 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/0.xbar_smoke_large_delays.2023994591 |
|
|
Aug 24 03:45:46 AM UTC 24 |
Aug 24 03:46:56 AM UTC 24 |
8567449403 ps |
| T1343 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/0.chip_prim_tl_access.1648772879 |
|
|
Aug 24 03:44:43 AM UTC 24 |
Aug 24 03:47:11 AM UTC 24 |
4874970440 ps |
| T411 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/0.xbar_same_source.1364415493 |
|
|
Aug 24 03:47:10 AM UTC 24 |
Aug 24 03:47:21 AM UTC 24 |
363108545 ps |
| T550 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/0.xbar_unmapped_addr.1926929288 |
|
|
Aug 24 03:47:25 AM UTC 24 |
Aug 24 03:47:37 AM UTC 24 |
106179075 ps |
| T548 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/0.xbar_access_same_device.2016445960 |
|
|
Aug 24 03:46:57 AM UTC 24 |
Aug 24 03:47:42 AM UTC 24 |
779499176 ps |
| T266 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/0.xbar_error_and_unmapped_addr.1911675556 |
|
|
Aug 24 03:47:35 AM UTC 24 |
Aug 24 03:47:46 AM UTC 24 |
104499128 ps |
| T267 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/0.xbar_error_random.2841353926 |
|
|
Aug 24 03:47:16 AM UTC 24 |
Aug 24 03:47:52 AM UTC 24 |
598655442 ps |
| T1344 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/0.chip_rv_dm_lc_disabled.3579355922 |
|
|
Aug 24 03:44:58 AM UTC 24 |
Aug 24 03:48:54 AM UTC 24 |
6942579721 ps |
| T551 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/0.xbar_stress_all_with_rand_reset.3291915635 |
|
|
Aug 24 03:47:56 AM UTC 24 |
Aug 24 03:49:22 AM UTC 24 |
356960955 ps |
| T456 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/0.xbar_stress_all_with_error.1838043288 |
|
|
Aug 24 03:48:00 AM UTC 24 |
Aug 24 03:49:57 AM UTC 24 |
2102938518 ps |
| T440 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/0.xbar_stress_all.1005955182 |
|
|
Aug 24 03:47:52 AM UTC 24 |
Aug 24 03:50:05 AM UTC 24 |
1969099976 ps |
| T459 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/0.xbar_random_slow_rsp.4094559806 |
|
|
Aug 24 03:46:56 AM UTC 24 |
Aug 24 03:50:24 AM UTC 24 |
17448357858 ps |
| T642 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/0.chip_csr_bit_bash.4178250222 |
|
|
Aug 24 03:44:02 AM UTC 24 |
Aug 24 03:50:40 AM UTC 24 |
6405161500 ps |
| T546 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/1.xbar_smoke.2866597213 |
|
|
Aug 24 03:50:54 AM UTC 24 |
Aug 24 03:51:01 AM UTC 24 |
183056022 ps |
| T176 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/0.chip_csr_hw_reset.766074429 |
|
|
Aug 24 03:48:06 AM UTC 24 |
Aug 24 03:51:11 AM UTC 24 |
4527769922 ps |
| T552 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/1.xbar_smoke_zero_delays.3018453415 |
|
|
Aug 24 03:51:16 AM UTC 24 |
Aug 24 03:51:22 AM UTC 24 |
44512754 ps |
| T549 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/0.xbar_stress_all_with_reset_error.1993587740 |
|
|
Aug 24 03:48:06 AM UTC 24 |
Aug 24 03:51:27 AM UTC 24 |
5016502657 ps |
| T532 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/1.xbar_random_zero_delays.976995147 |
|
|
Aug 24 03:51:41 AM UTC 24 |
Aug 24 03:52:05 AM UTC 24 |
361440922 ps |
| T553 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/1.xbar_random.54192238 |
|
|
Aug 24 03:51:36 AM UTC 24 |
Aug 24 03:52:06 AM UTC 24 |
1049947042 ps |
| T590 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/1.xbar_smoke_large_delays.2110034444 |
|
|
Aug 24 03:51:25 AM UTC 24 |
Aug 24 03:52:28 AM UTC 24 |
7610270308 ps |
| T409 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/0.chip_csr_rw.3783905774 |
|
|
Aug 24 03:48:15 AM UTC 24 |
Aug 24 03:52:33 AM UTC 24 |
4546272642 ps |
| T678 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/1.xbar_smoke_slow_rsp.3303084635 |
|
|
Aug 24 03:51:32 AM UTC 24 |
Aug 24 03:52:37 AM UTC 24 |
5363531165 ps |
| T593 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/1.xbar_same_source.1508054408 |
|
|
Aug 24 03:52:52 AM UTC 24 |
Aug 24 03:53:01 AM UTC 24 |
297967497 ps |
| T547 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/1.chip_tl_errors.3738959388 |
|
|
Aug 24 03:50:13 AM UTC 24 |
Aug 24 03:53:02 AM UTC 24 |
3933094224 ps |
| T677 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/1.xbar_access_same_device.1916655372 |
|
|
Aug 24 03:52:42 AM UTC 24 |
Aug 24 03:53:18 AM UTC 24 |
1104357270 ps |
| T1345 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/1.xbar_error_and_unmapped_addr.1878943318 |
|
|
Aug 24 03:53:33 AM UTC 24 |
Aug 24 03:53:41 AM UTC 24 |
56930938 ps |
| T1346 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/1.chip_prim_tl_access.1483736334 |
|
|
Aug 24 03:50:19 AM UTC 24 |
Aug 24 03:53:47 AM UTC 24 |
6584472608 ps |
| T538 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/1.xbar_unmapped_addr.127663522 |
|
|
Aug 24 03:53:17 AM UTC 24 |
Aug 24 03:53:49 AM UTC 24 |
994095297 ps |
| T664 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/1.xbar_error_random.1443253371 |
|
|
Aug 24 03:53:16 AM UTC 24 |
Aug 24 03:53:59 AM UTC 24 |
1637400452 ps |
| T643 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/1.xbar_access_same_device_slow_rsp.1615991302 |
|
|
Aug 24 03:52:47 AM UTC 24 |
Aug 24 03:54:05 AM UTC 24 |
6149645001 ps |
| T408 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/0.chip_csr_mem_rw_with_rand_reset.586639129 |
|
|
Aug 24 03:49:09 AM UTC 24 |
Aug 24 03:54:10 AM UTC 24 |
7149891420 ps |
| T836 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/1.xbar_stress_all_with_rand_reset.2871218884 |
|
|
Aug 24 03:53:55 AM UTC 24 |
Aug 24 03:54:10 AM UTC 24 |
87388115 ps |
| T679 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/2.xbar_smoke.2010822239 |
|
|
Aug 24 03:55:47 AM UTC 24 |
Aug 24 03:55:54 AM UTC 24 |
41002113 ps |
| T1347 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/1.chip_rv_dm_lc_disabled.2330588570 |
|
|
Aug 24 03:50:37 AM UTC 24 |
Aug 24 03:56:04 AM UTC 24 |
12527424031 ps |
| T573 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/1.xbar_random_slow_rsp.2353556408 |
|
|
Aug 24 03:52:20 AM UTC 24 |
Aug 24 03:56:08 AM UTC 24 |
18231149257 ps |
| T1348 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/2.xbar_smoke_zero_delays.2037126847 |
|
|
Aug 24 03:56:08 AM UTC 24 |
Aug 24 03:56:15 AM UTC 24 |
45988376 ps |
| T635 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/1.xbar_stress_all_with_error.1708427752 |
|
|
Aug 24 03:54:00 AM UTC 24 |
Aug 24 03:56:36 AM UTC 24 |
6473341659 ps |
| T174 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/1.chip_csr_hw_reset.689190658 |
|
|
Aug 24 03:54:03 AM UTC 24 |
Aug 24 03:56:53 AM UTC 24 |
5228760390 ps |
| T554 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/2.chip_tl_errors.1692974573 |
|
|
Aug 24 03:54:26 AM UTC 24 |
Aug 24 03:57:06 AM UTC 24 |
3839974324 ps |
| T577 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/2.xbar_random_zero_delays.944505671 |
|
|
Aug 24 03:56:50 AM UTC 24 |
Aug 24 03:57:21 AM UTC 24 |
425516185 ps |
| T460 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/2.xbar_random.1549331925 |
|
|
Aug 24 03:56:29 AM UTC 24 |
Aug 24 03:57:21 AM UTC 24 |
1921542459 ps |
| T869 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/2.xbar_smoke_large_delays.449387542 |
|
|
Aug 24 03:56:19 AM UTC 24 |
Aug 24 03:57:24 AM UTC 24 |
7891643028 ps |
| T578 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/2.xbar_smoke_slow_rsp.4182193501 |
|
|
Aug 24 03:56:23 AM UTC 24 |
Aug 24 03:57:38 AM UTC 24 |
6206846987 ps |
| T1349 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/2.xbar_error_random.911018195 |
|
|
Aug 24 03:57:38 AM UTC 24 |
Aug 24 03:57:53 AM UTC 24 |
469664016 ps |
| T489 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/2.xbar_access_same_device.2961393467 |
|
|
Aug 24 03:57:34 AM UTC 24 |
Aug 24 03:58:05 AM UTC 24 |
507713702 ps |
| T567 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/2.xbar_same_source.4114983378 |
|
|
Aug 24 03:57:35 AM UTC 24 |
Aug 24 03:58:20 AM UTC 24 |
1881719204 ps |
| T619 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/2.xbar_unmapped_addr.2251944507 |
|
|
Aug 24 03:57:52 AM UTC 24 |
Aug 24 03:58:34 AM UTC 24 |
1410290254 ps |
| T636 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/2.xbar_error_and_unmapped_addr.928200787 |
|
|
Aug 24 03:58:07 AM UTC 24 |
Aug 24 03:58:45 AM UTC 24 |
1252610463 ps |
| T542 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/1.xbar_stress_all.780769328 |
|
|
Aug 24 03:53:34 AM UTC 24 |
Aug 24 03:58:59 AM UTC 24 |
11008298801 ps |
| T589 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/1.xbar_stress_all_with_reset_error.3858398648 |
|
|
Aug 24 03:54:01 AM UTC 24 |
Aug 24 03:59:17 AM UTC 24 |
6194775583 ps |
| T569 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/0.xbar_random_large_delays.915912013 |
|
|
Aug 24 03:46:46 AM UTC 24 |
Aug 24 03:59:21 AM UTC 24 |
96472418092 ps |
| T640 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/2.xbar_stress_all_with_error.714636208 |
|
|
Aug 24 03:58:47 AM UTC 24 |
Aug 24 03:59:31 AM UTC 24 |
1907527447 ps |
| T1350 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/2.chip_prim_tl_access.1642817120 |
|
|
Aug 24 03:54:29 AM UTC 24 |
Aug 24 03:59:33 AM UTC 24 |
10265044625 ps |
| T1351 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/2.chip_rv_dm_lc_disabled.2480857030 |
|
|
Aug 24 03:55:15 AM UTC 24 |
Aug 24 03:59:55 AM UTC 24 |
12606284081 ps |
| T433 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/1.chip_csr_mem_rw_with_rand_reset.1569555868 |
|
|
Aug 24 03:54:11 AM UTC 24 |
Aug 24 04:00:11 AM UTC 24 |
6302349787 ps |
| T1352 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/3.xbar_smoke.1495076640 |
|
|
Aug 24 04:00:10 AM UTC 24 |
Aug 24 04:00:16 AM UTC 24 |
40562280 ps |
| T482 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/3.xbar_smoke_zero_delays.3421243368 |
|
|
Aug 24 04:00:25 AM UTC 24 |
Aug 24 04:00:32 AM UTC 24 |
51546654 ps |
| T183 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/1.chip_csr_rw.1941665249 |
|
|
Aug 24 03:54:03 AM UTC 24 |
Aug 24 04:00:53 AM UTC 24 |
5431847189 ps |
| T464 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/1.xbar_random_large_delays.2207508112 |
|
|
Aug 24 03:52:19 AM UTC 24 |
Aug 24 04:00:58 AM UTC 24 |
64358089603 ps |
| T579 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/3.xbar_random.2671887899 |
|
|
Aug 24 04:01:08 AM UTC 24 |
Aug 24 04:01:19 AM UTC 24 |
102678513 ps |
| T1353 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/3.xbar_smoke_large_delays.245204802 |
|
|
Aug 24 04:00:30 AM UTC 24 |
Aug 24 04:01:33 AM UTC 24 |
7539436438 ps |
| T617 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/3.xbar_smoke_slow_rsp.3021399479 |
|
|
Aug 24 04:00:47 AM UTC 24 |
Aug 24 04:01:37 AM UTC 24 |
3793105014 ps |
| T465 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/3.xbar_random_zero_delays.244835888 |
|
|
Aug 24 04:01:13 AM UTC 24 |
Aug 24 04:01:53 AM UTC 24 |
572434393 ps |
| T823 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/2.xbar_stress_all_with_reset_error.4031862757 |
|
|
Aug 24 03:59:00 AM UTC 24 |
Aug 24 04:01:58 AM UTC 24 |
581794807 ps |
| T177 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/2.chip_csr_hw_reset.2829690618 |
|
|
Aug 24 03:59:14 AM UTC 24 |
Aug 24 04:02:09 AM UTC 24 |
4028545356 ps |
| T518 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/3.xbar_same_source.2724532800 |
|
|
Aug 24 04:02:00 AM UTC 24 |
Aug 24 04:02:24 AM UTC 24 |
360803832 ps |
| T1354 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/3.xbar_unmapped_addr.1338828056 |
|
|
Aug 24 04:02:13 AM UTC 24 |
Aug 24 04:02:34 AM UTC 24 |
580650806 ps |
| T662 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/3.xbar_error_and_unmapped_addr.2369364876 |
|
|
Aug 24 04:02:24 AM UTC 24 |
Aug 24 04:02:44 AM UTC 24 |
223144837 ps |
| T555 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/3.chip_tl_errors.2517558064 |
|
|
Aug 24 03:59:53 AM UTC 24 |
Aug 24 04:02:45 AM UTC 24 |
3468875738 ps |
| T1355 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/3.xbar_error_random.3005293523 |
|
|
Aug 24 04:02:07 AM UTC 24 |
Aug 24 04:02:47 AM UTC 24 |
1615556117 ps |
| T413 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/1.chip_csr_bit_bash.2455404438 |
|
|
Aug 24 03:49:34 AM UTC 24 |
Aug 24 04:03:13 AM UTC 24 |
11453281632 ps |
| T801 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/3.xbar_access_same_device.1380870630 |
|
|
Aug 24 04:01:51 AM UTC 24 |
Aug 24 04:03:24 AM UTC 24 |
3053750825 ps |
| T864 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/3.xbar_stress_all_with_rand_reset.2588786084 |
|
|
Aug 24 04:02:49 AM UTC 24 |
Aug 24 04:04:06 AM UTC 24 |
89953411 ps |
| T802 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/3.xbar_stress_all_with_error.2700678252 |
|
|
Aug 24 04:02:58 AM UTC 24 |
Aug 24 04:04:27 AM UTC 24 |
1562138572 ps |
| T525 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/2.xbar_stress_all.728254830 |
|
|
Aug 24 03:58:19 AM UTC 24 |
Aug 24 04:04:58 AM UTC 24 |
12815809573 ps |
| T184 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/2.chip_csr_mem_rw_with_rand_reset.433385764 |
|
|
Aug 24 03:59:35 AM UTC 24 |
Aug 24 04:04:59 AM UTC 24 |
6794398072 ps |
| T1356 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/4.xbar_smoke.3189237267 |
|
|
Aug 24 04:05:13 AM UTC 24 |
Aug 24 04:05:20 AM UTC 24 |
45386165 ps |
| T1357 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/4.xbar_smoke_zero_delays.1559567517 |
|
|
Aug 24 04:05:33 AM UTC 24 |
Aug 24 04:05:40 AM UTC 24 |
44030885 ps |
| T424 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/2.chip_csr_rw.1776974933 |
|
|
Aug 24 03:59:31 AM UTC 24 |
Aug 24 04:06:23 AM UTC 24 |
6057712634 ps |
| T461 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/3.xbar_stress_all.2348179175 |
|
|
Aug 24 04:02:39 AM UTC 24 |
Aug 24 04:06:35 AM UTC 24 |
8762135345 ps |
| T404 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/0.chip_same_csr_outstanding.2644814268 |
|
|
Aug 24 03:44:12 AM UTC 24 |
Aug 24 04:06:43 AM UTC 24 |
16576358560 ps |
| T613 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/4.xbar_random.2763164669 |
|
|
Aug 24 04:06:50 AM UTC 24 |
Aug 24 04:06:58 AM UTC 24 |
68134742 ps |
| T817 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/2.xbar_access_same_device_slow_rsp.109681203 |
|
|
Aug 24 03:57:35 AM UTC 24 |
Aug 24 04:07:03 AM UTC 24 |
45423980804 ps |
| T467 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/4.xbar_random_zero_delays.1343882739 |
|
|
Aug 24 04:06:58 AM UTC 24 |
Aug 24 04:07:09 AM UTC 24 |
105740213 ps |
| T663 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/3.xbar_stress_all_with_reset_error.967417000 |
|
|
Aug 24 04:02:59 AM UTC 24 |
Aug 24 04:07:10 AM UTC 24 |
2118650984 ps |
| T570 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/4.xbar_smoke_large_delays.315237731 |
|
|
Aug 24 04:05:54 AM UTC 24 |
Aug 24 04:07:11 AM UTC 24 |
8932748622 ps |
| T434 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/3.chip_csr_rw.172546347 |
|
|
Aug 24 04:03:27 AM UTC 24 |
Aug 24 04:07:19 AM UTC 24 |
3828768976 ps |
| T587 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/3.xbar_random_large_delays.589717646 |
|
|
Aug 24 04:01:34 AM UTC 24 |
Aug 24 04:07:22 AM UTC 24 |
43074191915 ps |
| T580 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/2.xbar_random_large_delays.369893227 |
|
|
Aug 24 03:57:07 AM UTC 24 |
Aug 24 04:07:29 AM UTC 24 |
73351851064 ps |
| T618 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/4.xbar_same_source.3392157112 |
|
|
Aug 24 04:07:25 AM UTC 24 |
Aug 24 04:07:46 AM UTC 24 |
850807986 ps |
| T1358 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/4.xbar_smoke_slow_rsp.2742670787 |
|
|
Aug 24 04:06:37 AM UTC 24 |
Aug 24 04:07:49 AM UTC 24 |
6178233879 ps |
| T599 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/2.xbar_random_slow_rsp.1531235416 |
|
|
Aug 24 03:57:20 AM UTC 24 |
Aug 24 04:07:57 AM UTC 24 |
54095869134 ps |
| T620 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/4.xbar_unmapped_addr.3951109626 |
|
|
Aug 24 04:07:36 AM UTC 24 |
Aug 24 04:07:59 AM UTC 24 |
222582192 ps |
| T782 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/4.xbar_access_same_device.2968096142 |
|
|
Aug 24 04:07:23 AM UTC 24 |
Aug 24 04:08:00 AM UTC 24 |
582623603 ps |
| T1359 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/4.xbar_error_random.4268985336 |
|
|
Aug 24 04:07:33 AM UTC 24 |
Aug 24 04:08:00 AM UTC 24 |
1127841548 ps |
| T565 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/4.chip_tl_errors.3454341950 |
|
|
Aug 24 04:05:12 AM UTC 24 |
Aug 24 04:08:07 AM UTC 24 |
3990371520 ps |
| T1360 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/4.xbar_error_and_unmapped_addr.2878644909 |
|
|
Aug 24 04:07:37 AM UTC 24 |
Aug 24 04:08:10 AM UTC 24 |
1053396906 ps |
| T175 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/3.chip_csr_hw_reset.3471911497 |
|
|
Aug 24 04:03:01 AM UTC 24 |
Aug 24 04:08:21 AM UTC 24 |
7382791446 ps |
| T1361 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/5.xbar_smoke.2076306976 |
|
|
Aug 24 04:08:35 AM UTC 24 |
Aug 24 04:08:44 AM UTC 24 |
235659125 ps |
| T1362 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/4.xbar_stress_all_with_reset_error.1563665665 |
|
|
Aug 24 04:08:11 AM UTC 24 |
Aug 24 04:08:47 AM UTC 24 |
145502300 ps |
| T1363 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/5.xbar_smoke_zero_delays.71647958 |
|
|
Aug 24 04:08:58 AM UTC 24 |
Aug 24 04:09:05 AM UTC 24 |
44286931 ps |
| T474 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/2.xbar_stress_all_with_rand_reset.262489615 |
|
|
Aug 24 03:58:34 AM UTC 24 |
Aug 24 04:09:30 AM UTC 24 |
8167815578 ps |
| T485 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/4.xbar_stress_all.3793331683 |
|
|
Aug 24 04:07:44 AM UTC 24 |
Aug 24 04:09:30 AM UTC 24 |
1519550467 ps |
| T783 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/4.xbar_access_same_device_slow_rsp.2130598676 |
|
|
Aug 24 04:07:25 AM UTC 24 |
Aug 24 04:09:32 AM UTC 24 |
10829404555 ps |
| T1364 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/5.xbar_random_zero_delays.36031804 |
|
|
Aug 24 04:09:45 AM UTC 24 |
Aug 24 04:09:55 AM UTC 24 |
108788518 ps |
| T641 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/4.xbar_stress_all_with_error.4169152487 |
|
|
Aug 24 04:08:04 AM UTC 24 |
Aug 24 04:09:57 AM UTC 24 |
1937619128 ps |
| T521 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/4.xbar_stress_all_with_rand_reset.2747777259 |
|
|
Aug 24 04:08:01 AM UTC 24 |
Aug 24 04:10:11 AM UTC 24 |
397752491 ps |
| T1365 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/5.xbar_smoke_slow_rsp.919711059 |
|
|
Aug 24 04:09:18 AM UTC 24 |
Aug 24 04:10:11 AM UTC 24 |
4103673681 ps |
| T595 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/5.xbar_smoke_large_delays.454996471 |
|
|
Aug 24 04:09:01 AM UTC 24 |
Aug 24 04:10:14 AM UTC 24 |
9056397945 ps |
| T566 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/5.chip_tl_errors.3523100006 |
|
|
Aug 24 04:08:24 AM UTC 24 |
Aug 24 04:10:21 AM UTC 24 |
2745105374 ps |
| T790 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/5.xbar_access_same_device.744720894 |
|
|
Aug 24 04:10:12 AM UTC 24 |
Aug 24 04:10:32 AM UTC 24 |
336214054 ps |
| T608 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/5.xbar_same_source.4101483729 |
|
|
Aug 24 04:10:26 AM UTC 24 |
Aug 24 04:10:44 AM UTC 24 |
752807684 ps |
| T503 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/5.xbar_random.394717002 |
|
|
Aug 24 04:09:44 AM UTC 24 |
Aug 24 04:10:49 AM UTC 24 |
2282486497 ps |
| T499 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/5.xbar_unmapped_addr.326407276 |
|
|
Aug 24 04:10:35 AM UTC 24 |
Aug 24 04:10:55 AM UTC 24 |
199615893 ps |
| T1366 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/5.xbar_error_and_unmapped_addr.2349620184 |
|
|
Aug 24 04:10:47 AM UTC 24 |
Aug 24 04:11:03 AM UTC 24 |
162026017 ps |
| T616 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/5.xbar_error_random.2428696882 |
|
|
Aug 24 04:10:28 AM UTC 24 |
Aug 24 04:11:28 AM UTC 24 |
2266140653 ps |
| T1367 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/3.chip_csr_bit_bash.1828097251 |
|
|
Aug 24 03:59:44 AM UTC 24 |
Aug 24 04:11:39 AM UTC 24 |
9351491860 ps |
| T179 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/4.chip_csr_hw_reset.675543346 |
|
|
Aug 24 04:08:13 AM UTC 24 |
Aug 24 04:11:45 AM UTC 24 |
5318769344 ps |
| T795 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/5.xbar_stress_all_with_error.2202691693 |
|
|
Aug 24 04:11:09 AM UTC 24 |
Aug 24 04:12:11 AM UTC 24 |
1134345934 ps |
| T622 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/5.xbar_stress_all_with_rand_reset.2963294483 |
|
|
Aug 24 04:11:03 AM UTC 24 |
Aug 24 04:12:48 AM UTC 24 |
2561640025 ps |
| T537 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/6.xbar_smoke.855892118 |
|
|
Aug 24 04:13:03 AM UTC 24 |
Aug 24 04:13:09 AM UTC 24 |
49962729 ps |
| T457 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/4.chip_csr_mem_rw_with_rand_reset.1261301652 |
|
|
Aug 24 04:08:14 AM UTC 24 |
Aug 24 04:13:11 AM UTC 24 |
6774283890 ps |
| T468 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/0.xbar_access_same_device_slow_rsp.27533580 |
|
|
Aug 24 03:47:02 AM UTC 24 |
Aug 24 04:13:22 AM UTC 24 |
130208095991 ps |
| T1368 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/6.xbar_smoke_zero_delays.4218546481 |
|
|
Aug 24 04:13:24 AM UTC 24 |
Aug 24 04:13:30 AM UTC 24 |
45077405 ps |
| T564 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/6.chip_tl_errors.1967886456 |
|
|
Aug 24 04:12:26 AM UTC 24 |
Aug 24 04:14:04 AM UTC 24 |
3188305290 ps |
| T563 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/6.xbar_random.1331624975 |
|
|
Aug 24 04:13:44 AM UTC 24 |
Aug 24 04:14:20 AM UTC 24 |
1432673155 ps |
| T1369 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/6.xbar_smoke_large_delays.994946486 |
|
|
Aug 24 04:13:25 AM UTC 24 |
Aug 24 04:14:20 AM UTC 24 |
6720667010 ps |
| T458 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/4.chip_csr_rw.3099576585 |
|
|
Aug 24 04:08:14 AM UTC 24 |
Aug 24 04:14:21 AM UTC 24 |
5492874999 ps |
| T594 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/6.xbar_random_zero_delays.290954341 |
|
|
Aug 24 04:14:18 AM UTC 24 |
Aug 24 04:14:52 AM UTC 24 |
465737849 ps |
| T1370 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/6.xbar_smoke_slow_rsp.2261732080 |
|
|
Aug 24 04:13:36 AM UTC 24 |
Aug 24 04:14:57 AM UTC 24 |
6525150824 ps |
| T494 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/6.xbar_same_source.2926854788 |
|
|
Aug 24 04:15:11 AM UTC 24 |
Aug 24 04:15:43 AM UTC 24 |
1345566129 ps |
| T425 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/3.chip_csr_mem_rw_with_rand_reset.4179016752 |
|
|
Aug 24 04:03:28 AM UTC 24 |
Aug 24 04:15:47 AM UTC 24 |
12116512138 ps |
| T786 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/6.xbar_access_same_device.1315661054 |
|
|
Aug 24 04:14:35 AM UTC 24 |
Aug 24 04:15:49 AM UTC 24 |
2007683060 ps |
| T605 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/4.xbar_random_large_delays.3611451613 |
|
|
Aug 24 04:07:13 AM UTC 24 |
Aug 24 04:15:58 AM UTC 24 |
64232911562 ps |
| T469 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/5.xbar_stress_all.3798481792 |
|
|
Aug 24 04:10:58 AM UTC 24 |
Aug 24 04:16:06 AM UTC 24 |
11802496330 ps |
| T1371 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/6.xbar_error_random.1086516629 |
|
|
Aug 24 04:15:57 AM UTC 24 |
Aug 24 04:16:10 AM UTC 24 |
342122803 ps |
| T477 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/6.xbar_random_large_delays.3696100217 |
|
|
Aug 24 04:14:34 AM UTC 24 |
Aug 24 04:16:11 AM UTC 24 |
11112570303 ps |
| T1372 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/6.xbar_unmapped_addr.601092888 |
|
|
Aug 24 04:16:01 AM UTC 24 |
Aug 24 04:16:16 AM UTC 24 |
150685099 ps |
| T1373 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/6.xbar_error_and_unmapped_addr.2101943403 |
|
|
Aug 24 04:16:03 AM UTC 24 |
Aug 24 04:16:25 AM UTC 24 |
232240378 ps |
| T475 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/3.xbar_random_slow_rsp.60313789 |
|
|
Aug 24 04:01:47 AM UTC 24 |
Aug 24 04:17:03 AM UTC 24 |
69760968451 ps |
| T1374 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/6.xbar_stress_all_with_error.189929403 |
|
|
Aug 24 04:16:24 AM UTC 24 |
Aug 24 04:17:30 AM UTC 24 |
1201141995 ps |
| T480 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/4.xbar_random_slow_rsp.3912668552 |
|
|
Aug 24 04:07:17 AM UTC 24 |
Aug 24 04:17:39 AM UTC 24 |
51921879014 ps |
| T426 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/5.chip_csr_rw.725995353 |
|
|
Aug 24 04:11:42 AM UTC 24 |
Aug 24 04:17:47 AM UTC 24 |
6184569730 ps |
| T1375 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/7.xbar_smoke.480423633 |
|
|
Aug 24 04:17:53 AM UTC 24 |
Aug 24 04:18:00 AM UTC 24 |
122262751 ps |
| T1376 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/7.xbar_smoke_zero_delays.495227333 |
|
|
Aug 24 04:18:01 AM UTC 24 |
Aug 24 04:18:07 AM UTC 24 |
41931748 ps |
| T405 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/2.chip_same_csr_outstanding.2841402199 |
|
|
Aug 24 03:54:24 AM UTC 24 |
Aug 24 04:18:26 AM UTC 24 |
17144172866 ps |
| T811 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/6.xbar_stress_all_with_reset_error.793432494 |
|
|
Aug 24 04:16:26 AM UTC 24 |
Aug 24 04:18:59 AM UTC 24 |
2579743787 ps |
| T576 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/7.xbar_random.3621292680 |
|
|
Aug 24 04:18:40 AM UTC 24 |
Aug 24 04:19:22 AM UTC 24 |
569974223 ps |
| T1377 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/7.xbar_smoke_slow_rsp.641434160 |
|
|
Aug 24 04:18:22 AM UTC 24 |
Aug 24 04:19:25 AM UTC 24 |
5068012149 ps |
| T1378 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/7.xbar_smoke_large_delays.1633544578 |
|
|
Aug 24 04:18:14 AM UTC 24 |
Aug 24 04:19:28 AM UTC 24 |
8533456480 ps |
| T585 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/7.xbar_random_zero_delays.1294191086 |
|
|
Aug 24 04:19:14 AM UTC 24 |
Aug 24 04:19:44 AM UTC 24 |
398349772 ps |
| T1379 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/5.chip_csr_mem_rw_with_rand_reset.4112559314 |
|
|
Aug 24 04:11:52 AM UTC 24 |
Aug 24 04:20:02 AM UTC 24 |
9214398983 ps |
| T805 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/5.xbar_stress_all_with_reset_error.1491801463 |
|
|
Aug 24 04:11:17 AM UTC 24 |
Aug 24 04:20:44 AM UTC 24 |
16239117295 ps |
| T556 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/7.chip_tl_errors.619049630 |
|
|
Aug 24 04:17:44 AM UTC 24 |
Aug 24 04:20:57 AM UTC 24 |
3865891922 ps |
| T495 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/7.xbar_same_source.1406217830 |
|
|
Aug 24 04:20:16 AM UTC 24 |
Aug 24 04:21:01 AM UTC 24 |
2020875486 ps |
| T466 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/7.xbar_access_same_device.264253669 |
|
|
Aug 24 04:19:43 AM UTC 24 |
Aug 24 04:21:27 AM UTC 24 |
3255568204 ps |
| T420 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/6.chip_csr_mem_rw_with_rand_reset.3914937585 |
|
|
Aug 24 04:16:39 AM UTC 24 |
Aug 24 04:21:31 AM UTC 24 |
6920202957 ps |
| T513 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/6.xbar_stress_all_with_rand_reset.416381542 |
|
|
Aug 24 04:16:21 AM UTC 24 |
Aug 24 04:21:32 AM UTC 24 |
5231358966 ps |
| T609 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/7.xbar_error_random.318558926 |
|
|
Aug 24 04:20:59 AM UTC 24 |
Aug 24 04:21:38 AM UTC 24 |
617983093 ps |
| T591 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/6.xbar_random_slow_rsp.1083550438 |
|
|
Aug 24 04:14:34 AM UTC 24 |
Aug 24 04:21:43 AM UTC 24 |
36601748894 ps |
| T1380 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/7.xbar_unmapped_addr.3373790331 |
|
|
Aug 24 04:21:11 AM UTC 24 |
Aug 24 04:21:44 AM UTC 24 |
1047531111 ps |
| T1381 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/7.xbar_error_and_unmapped_addr.71084607 |
|
|
Aug 24 04:21:15 AM UTC 24 |
Aug 24 04:21:50 AM UTC 24 |
1132165575 ps |
| T803 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/3.xbar_access_same_device_slow_rsp.410850659 |
|
|
Aug 24 04:01:52 AM UTC 24 |
Aug 24 04:21:56 AM UTC 24 |
101864865139 ps |
| T462 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/5.xbar_random_slow_rsp.46248157 |
|
|
Aug 24 04:10:10 AM UTC 24 |
Aug 24 04:21:57 AM UTC 24 |
61754761240 ps |
| T470 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/6.xbar_stress_all.462957702 |
|
|
Aug 24 04:16:13 AM UTC 24 |
Aug 24 04:22:03 AM UTC 24 |
4924893250 ps |
| T850 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/7.xbar_stress_all_with_rand_reset.4263459417 |
|
|
Aug 24 04:21:45 AM UTC 24 |
Aug 24 04:22:07 AM UTC 24 |
14708166 ps |
| T1382 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/8.xbar_smoke.2695988410 |
|
|
Aug 24 04:22:12 AM UTC 24 |
Aug 24 04:22:18 AM UTC 24 |
45019773 ps |
| T816 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/6.xbar_access_same_device_slow_rsp.1244399208 |
|
|
Aug 24 04:15:06 AM UTC 24 |
Aug 24 04:22:22 AM UTC 24 |
34684199221 ps |
| T543 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/5.xbar_random_large_delays.1275000474 |
|
|
Aug 24 04:09:46 AM UTC 24 |
Aug 24 04:22:22 AM UTC 24 |
92734027717 ps |
| T1383 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/8.xbar_smoke_zero_delays.3618293140 |
|
|
Aug 24 04:22:18 AM UTC 24 |
Aug 24 04:22:24 AM UTC 24 |
44733013 ps |
| T1384 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/8.xbar_random.3982989356 |
|
|
Aug 24 04:22:36 AM UTC 24 |
Aug 24 04:22:43 AM UTC 24 |
149920863 ps |
| T497 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/7.xbar_stress_all.3911482237 |
|
|
Aug 24 04:21:41 AM UTC 24 |
Aug 24 04:22:45 AM UTC 24 |
2385389422 ps |
| T638 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/7.xbar_stress_all_with_reset_error.1468136840 |
|
|
Aug 24 04:21:51 AM UTC 24 |
Aug 24 04:23:09 AM UTC 24 |
374154146 ps |
| T592 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/8.xbar_random_zero_delays.482614615 |
|
|
Aug 24 04:22:37 AM UTC 24 |
Aug 24 04:23:16 AM UTC 24 |
578342369 ps |
| T784 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/8.xbar_access_same_device.2416923201 |
|
|
Aug 24 04:22:59 AM UTC 24 |
Aug 24 04:23:21 AM UTC 24 |
217607299 ps |
| T615 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/8.xbar_smoke_slow_rsp.1724031335 |
|
|
Aug 24 04:22:32 AM UTC 24 |
Aug 24 04:23:33 AM UTC 24 |
4858913031 ps |
| T1385 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/8.xbar_unmapped_addr.2347854382 |
|
|
Aug 24 04:23:35 AM UTC 24 |
Aug 24 04:23:41 AM UTC 24 |
22554377 ps |
| T787 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/8.xbar_access_same_device_slow_rsp.1813435975 |
|
|
Aug 24 04:23:09 AM UTC 24 |
Aug 24 04:23:42 AM UTC 24 |
2445803415 ps |
| T583 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/8.xbar_same_source.4200030084 |
|
|
Aug 24 04:23:23 AM UTC 24 |
Aug 24 04:23:47 AM UTC 24 |
403397981 ps |
| T406 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/4.chip_same_csr_outstanding.1816302220 |
|
|
Aug 24 04:04:41 AM UTC 24 |
Aug 24 04:23:47 AM UTC 24 |
16852933106 ps |
| T1386 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/8.xbar_smoke_large_delays.1868748955 |
|
|
Aug 24 04:22:22 AM UTC 24 |
Aug 24 04:23:52 AM UTC 24 |
10481257869 ps |
| T1387 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/8.xbar_error_random.2238741110 |
|
|
Aug 24 04:23:30 AM UTC 24 |
Aug 24 04:24:04 AM UTC 24 |
502016967 ps |
| T602 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/8.xbar_error_and_unmapped_addr.633717262 |
|
|
Aug 24 04:23:48 AM UTC 24 |
Aug 24 04:24:18 AM UTC 24 |
1068017406 ps |
| T544 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/6.chip_csr_rw.1748838671 |
|
|
Aug 24 04:16:30 AM UTC 24 |
Aug 24 04:24:24 AM UTC 24 |
5980020920 ps |
| T533 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/8.xbar_random_large_delays.1252239789 |
|
|
Aug 24 04:22:39 AM UTC 24 |
Aug 24 04:24:38 AM UTC 24 |
14218401831 ps |
| T856 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/8.xbar_stress_all_with_rand_reset.3923837350 |
|
|
Aug 24 04:23:56 AM UTC 24 |
Aug 24 04:24:48 AM UTC 24 |
160036852 ps |
| T1388 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/9.xbar_smoke.1310952668 |
|
|
Aug 24 04:24:52 AM UTC 24 |
Aug 24 04:25:00 AM UTC 24 |
149498236 ps |
| T1389 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/9.xbar_smoke_zero_delays.2389087862 |
|
|
Aug 24 04:25:02 AM UTC 24 |
Aug 24 04:25:08 AM UTC 24 |
52040143 ps |
| T1390 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/9.xbar_random.4199205323 |
|
|
Aug 24 04:25:30 AM UTC 24 |
Aug 24 04:25:36 AM UTC 24 |
31762255 ps |
| T1391 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/9.xbar_smoke_large_delays.2126377419 |
|
|
Aug 24 04:25:13 AM UTC 24 |
Aug 24 04:26:05 AM UTC 24 |
5766178561 ps |
| T1392 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/9.xbar_smoke_slow_rsp.4266020054 |
|
|
Aug 24 04:25:23 AM UTC 24 |
Aug 24 04:26:16 AM UTC 24 |
4249834012 ps |
| T584 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/9.xbar_random_zero_delays.1950475750 |
|
|
Aug 24 04:25:50 AM UTC 24 |
Aug 24 04:26:25 AM UTC 24 |
492140322 ps |
| T557 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/8.chip_tl_errors.1820584305 |
|
|
Aug 24 04:22:11 AM UTC 24 |
Aug 24 04:26:36 AM UTC 24 |
4671058916 ps |
| T486 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/5.xbar_access_same_device_slow_rsp.2396620644 |
|
|
Aug 24 04:10:26 AM UTC 24 |
Aug 24 04:26:38 AM UTC 24 |
77740844678 ps |
| T1393 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/7.chip_csr_rw.1109154162 |
|
|
Aug 24 04:21:58 AM UTC 24 |
Aug 24 04:26:50 AM UTC 24 |
4373501244 ps |
| T561 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/9.chip_tl_errors.4151777192 |
|
|
Aug 24 04:24:39 AM UTC 24 |
Aug 24 04:27:03 AM UTC 24 |
3115115000 ps |
| T1394 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/9.xbar_same_source.2011807914 |
|
|
Aug 24 04:26:52 AM UTC 24 |
Aug 24 04:27:07 AM UTC 24 |
233923267 ps |
| T1395 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/9.xbar_error_random.2505045599 |
|
|
Aug 24 04:27:04 AM UTC 24 |
Aug 24 04:27:20 AM UTC 24 |
207058559 ps |
| T812 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/9.xbar_access_same_device.1509822550 |
|
|
Aug 24 04:26:39 AM UTC 24 |
Aug 24 04:27:25 AM UTC 24 |
1575429967 ps |
| T1396 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/8.xbar_stress_all_with_error.2107972837 |
|
|
Aug 24 04:24:01 AM UTC 24 |
Aug 24 04:27:31 AM UTC 24 |
3545473304 ps |
| T1397 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/9.xbar_unmapped_addr.163883932 |
|
|
Aug 24 04:27:18 AM UTC 24 |
Aug 24 04:27:31 AM UTC 24 |
312286248 ps |
| T806 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/7.xbar_access_same_device_slow_rsp.3693847138 |
|
|
Aug 24 04:19:58 AM UTC 24 |
Aug 24 04:27:36 AM UTC 24 |
37374150336 ps |
| T444 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/7.chip_csr_mem_rw_with_rand_reset.1364503026 |
|
|
Aug 24 04:21:58 AM UTC 24 |
Aug 24 04:27:40 AM UTC 24 |
8339369452 ps |
| T484 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/9.xbar_stress_all.2889970830 |
|
|
Aug 24 04:27:34 AM UTC 24 |
Aug 24 04:27:50 AM UTC 24 |
207009368 ps |
| T1398 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/9.xbar_error_and_unmapped_addr.4160635083 |
|
|
Aug 24 04:27:21 AM UTC 24 |
Aug 24 04:27:59 AM UTC 24 |
1389508728 ps |
| T788 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/7.xbar_stress_all_with_error.133026321 |
|
|
Aug 24 04:21:47 AM UTC 24 |
Aug 24 04:28:25 AM UTC 24 |
15470804331 ps |
| T471 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/8.xbar_stress_all.3866074721 |
|
|
Aug 24 04:23:56 AM UTC 24 |
Aug 24 04:28:39 AM UTC 24 |
10291818404 ps |
| T1399 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/10.xbar_smoke.1568728195 |
|
|
Aug 24 04:28:40 AM UTC 24 |
Aug 24 04:28:46 AM UTC 24 |
45515886 ps |
| T625 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/10.xbar_smoke_zero_delays.3173488013 |
|
|
Aug 24 04:28:54 AM UTC 24 |
Aug 24 04:29:00 AM UTC 24 |
44585609 ps |
| T504 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/7.xbar_random_slow_rsp.2898321551 |
|
|
Aug 24 04:19:39 AM UTC 24 |
Aug 24 04:29:06 AM UTC 24 |
49717462872 ps |
| T1400 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/2.chip_csr_bit_bash.782446949 |
|
|
Aug 24 03:54:14 AM UTC 24 |
Aug 24 04:29:21 AM UTC 24 |
31096152407 ps |
| T623 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/10.xbar_random_zero_delays.1183180421 |
|
|
Aug 24 04:29:35 AM UTC 24 |
Aug 24 04:29:57 AM UTC 24 |
306565691 ps |
| T614 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/10.xbar_random.2406130352 |
|
|
Aug 24 04:29:20 AM UTC 24 |
Aug 24 04:30:01 AM UTC 24 |
627150407 ps |
| T1401 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/8.xbar_random_slow_rsp.2086398679 |
|
|
Aug 24 04:22:57 AM UTC 24 |
Aug 24 04:30:12 AM UTC 24 |
36886116802 ps |
| T821 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/9.xbar_access_same_device_slow_rsp.252994335 |
|
|
Aug 24 04:26:51 AM UTC 24 |
Aug 24 04:30:19 AM UTC 24 |
17054004725 ps |
| T1402 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/10.xbar_smoke_slow_rsp.538480285 |
|
|
Aug 24 04:29:14 AM UTC 24 |
Aug 24 04:30:22 AM UTC 24 |
5511783610 ps |
| T845 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/9.xbar_stress_all_with_reset_error.3706752447 |
|
|
Aug 24 04:27:46 AM UTC 24 |
Aug 24 04:30:31 AM UTC 24 |
1484275884 ps |
| T1403 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/10.xbar_smoke_large_delays.1917710666 |
|
|
Aug 24 04:29:00 AM UTC 24 |
Aug 24 04:30:35 AM UTC 24 |
11154334912 ps |
| T639 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/8.xbar_stress_all_with_reset_error.2527562482 |
|
|
Aug 24 04:24:02 AM UTC 24 |
Aug 24 04:30:38 AM UTC 24 |
4952967714 ps |
| T1404 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/10.xbar_error_and_unmapped_addr.773301115 |
|
|
Aug 24 04:30:52 AM UTC 24 |
Aug 24 04:30:58 AM UTC 24 |
20401540 ps |
| T568 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/10.chip_tl_errors.1380413148 |
|
|
Aug 24 04:28:13 AM UTC 24 |
Aug 24 04:31:02 AM UTC 24 |
3566266185 ps |
| T1405 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/10.xbar_same_source.3770407924 |
|
|
Aug 24 04:30:36 AM UTC 24 |
Aug 24 04:31:03 AM UTC 24 |
1229965537 ps |
| T545 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/8.chip_csr_mem_rw_with_rand_reset.3078082234 |
|
|
Aug 24 04:24:18 AM UTC 24 |
Aug 24 04:31:03 AM UTC 24 |
7306169468 ps |
| T1406 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/10.xbar_unmapped_addr.4125974583 |
|
|
Aug 24 04:30:49 AM UTC 24 |
Aug 24 04:31:06 AM UTC 24 |
156537753 ps |