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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
96.27 95.58 94.38 95.46 95.27 97.35 99.58


Total test records in report: 2941
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T1783 /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/36.xbar_smoke.3118915020 Aug 24 05:46:53 AM UTC 24 Aug 24 05:47:00 AM UTC 24 178377266 ps
T1784 /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/36.xbar_smoke_zero_delays.2270056077 Aug 24 05:47:00 AM UTC 24 Aug 24 05:47:06 AM UTC 24 37983356 ps
T1785 /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/35.xbar_stress_all_with_rand_reset.964614115 Aug 24 05:46:25 AM UTC 24 Aug 24 05:47:09 AM UTC 24 106514849 ps
T1786 /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/35.xbar_stress_all.170854376 Aug 24 05:46:15 AM UTC 24 Aug 24 05:47:11 AM UTC 24 1075501081 ps
T1787 /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/36.xbar_random_zero_delays.4007683093 Aug 24 05:47:23 AM UTC 24 Aug 24 05:47:30 AM UTC 24 63934728 ps
T1788 /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/31.xbar_access_same_device_slow_rsp.4190920793 Aug 24 05:37:27 AM UTC 24 Aug 24 05:47:34 AM UTC 24 48175499920 ps
T1789 /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/33.xbar_stress_all_with_error.3610595675 Aug 24 05:42:09 AM UTC 24 Aug 24 05:47:38 AM UTC 24 12269972900 ps
T1790 /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/36.xbar_random.3547672124 Aug 24 05:47:21 AM UTC 24 Aug 24 05:47:54 AM UTC 24 1203990628 ps
T1791 /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/36.xbar_smoke_slow_rsp.3953550558 Aug 24 05:47:14 AM UTC 24 Aug 24 05:48:05 AM UTC 24 4229988866 ps
T1792 /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/33.xbar_stress_all.2454633236 Aug 24 05:42:03 AM UTC 24 Aug 24 05:48:14 AM UTC 24 13991960405 ps
T1793 /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/36.xbar_error_random.2933756870 Aug 24 05:48:19 AM UTC 24 Aug 24 05:48:27 AM UTC 24 183222109 ps
T1794 /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/36.xbar_smoke_large_delays.2692662296 Aug 24 05:47:11 AM UTC 24 Aug 24 05:48:36 AM UTC 24 10370217713 ps
T1795 /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/36.xbar_error_and_unmapped_addr.1859970490 Aug 24 05:48:41 AM UTC 24 Aug 24 05:48:59 AM UTC 24 576981860 ps
T1796 /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/36.xbar_unmapped_addr.1918419025 Aug 24 05:48:28 AM UTC 24 Aug 24 05:48:59 AM UTC 24 917804850 ps
T1797 /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/34.xbar_stress_all.2218025556 Aug 24 05:43:37 AM UTC 24 Aug 24 05:49:02 AM UTC 24 11587498213 ps
T1798 /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/36.xbar_same_source.4267825541 Aug 24 05:48:08 AM UTC 24 Aug 24 05:49:02 AM UTC 24 2488421028 ps
T1799 /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/25.xbar_access_same_device_slow_rsp.3441279604 Aug 24 05:23:31 AM UTC 24 Aug 24 05:49:20 AM UTC 24 124818132124 ps
T1800 /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/36.xbar_access_same_device.3196681674 Aug 24 05:47:48 AM UTC 24 Aug 24 05:49:22 AM UTC 24 3734996447 ps
T1801 /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/37.xbar_smoke.1862108166 Aug 24 05:49:16 AM UTC 24 Aug 24 05:49:24 AM UTC 24 181346677 ps
T1802 /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/37.xbar_smoke_zero_delays.875335031 Aug 24 05:49:34 AM UTC 24 Aug 24 05:49:40 AM UTC 24 45059807 ps
T843 /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/34.xbar_stress_all_with_rand_reset.307227748 Aug 24 05:43:39 AM UTC 24 Aug 24 05:49:49 AM UTC 24 3271370831 ps
T1803 /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/24.xbar_access_same_device_slow_rsp.771404939 Aug 24 05:21:12 AM UTC 24 Aug 24 05:49:52 AM UTC 24 147842258700 ps
T1804 /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/19.chip_same_csr_outstanding.3589254176 Aug 24 05:04:49 AM UTC 24 Aug 24 05:50:05 AM UTC 24 29476587171 ps
T1805 /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/35.xbar_stress_all_with_reset_error.1649174696 Aug 24 05:46:38 AM UTC 24 Aug 24 05:50:20 AM UTC 24 4064180496 ps
T1806 /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/35.xbar_stress_all_with_error.4145257204 Aug 24 05:46:28 AM UTC 24 Aug 24 05:50:24 AM UTC 24 9026749334 ps
T1807 /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/37.xbar_random.3504741165 Aug 24 05:49:55 AM UTC 24 Aug 24 05:50:28 AM UTC 24 1312333699 ps
T1808 /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/37.xbar_random_zero_delays.2133034700 Aug 24 05:50:03 AM UTC 24 Aug 24 05:50:32 AM UTC 24 432659201 ps
T1809 /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/37.xbar_smoke_large_delays.3042956627 Aug 24 05:49:36 AM UTC 24 Aug 24 05:50:37 AM UTC 24 7258660439 ps
T1810 /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/37.xbar_smoke_slow_rsp.4171224641 Aug 24 05:49:39 AM UTC 24 Aug 24 05:50:38 AM UTC 24 4871328707 ps
T1811 /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/1.chip_csr_aliasing.1581441445 Aug 24 03:49:36 AM UTC 24 Aug 24 05:50:44 AM UTC 24 65246888470 ps
T1812 /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/35.xbar_random_slow_rsp.64386484 Aug 24 05:44:57 AM UTC 24 Aug 24 05:50:45 AM UTC 24 28743976143 ps
T1813 /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/37.xbar_error_and_unmapped_addr.2578303700 Aug 24 05:50:52 AM UTC 24 Aug 24 05:51:09 AM UTC 24 475266772 ps
T1814 /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/37.xbar_same_source.1322189026 Aug 24 05:50:42 AM UTC 24 Aug 24 05:51:10 AM UTC 24 476868310 ps
T1815 /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/33.xbar_random_large_delays.1397731373 Aug 24 05:41:03 AM UTC 24 Aug 24 05:51:11 AM UTC 24 75002453163 ps
T1816 /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/37.xbar_unmapped_addr.560961304 Aug 24 05:50:50 AM UTC 24 Aug 24 05:51:21 AM UTC 24 954216875 ps
T1817 /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/2.chip_csr_aliasing.4019734650 Aug 24 03:54:19 AM UTC 24 Aug 24 05:51:21 AM UTC 24 58247954985 ps
T1818 /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/34.xbar_random_slow_rsp.1425405642 Aug 24 05:42:41 AM UTC 24 Aug 24 05:51:28 AM UTC 24 45077274525 ps
T1819 /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/38.xbar_smoke.2694618006 Aug 24 05:51:25 AM UTC 24 Aug 24 05:51:33 AM UTC 24 220397453 ps
T1820 /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/37.xbar_error_random.1182750892 Aug 24 05:50:45 AM UTC 24 Aug 24 05:51:39 AM UTC 24 2202491765 ps
T1821 /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/38.xbar_smoke_zero_delays.2195120221 Aug 24 05:51:35 AM UTC 24 Aug 24 05:51:42 AM UTC 24 57328686 ps
T1822 /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/37.xbar_access_same_device.1159227572 Aug 24 05:50:34 AM UTC 24 Aug 24 05:51:44 AM UTC 24 2228827722 ps
T863 /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/34.xbar_stress_all_with_reset_error.3630314570 Aug 24 05:43:42 AM UTC 24 Aug 24 05:51:49 AM UTC 24 6004371774 ps
T1823 /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/38.xbar_random.4289078285 Aug 24 05:51:47 AM UTC 24 Aug 24 05:52:02 AM UTC 24 202195148 ps
T1824 /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/36.xbar_stress_all_with_rand_reset.2487013423 Aug 24 05:49:12 AM UTC 24 Aug 24 05:52:07 AM UTC 24 430003661 ps
T1825 /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/31.xbar_random_large_delays.1441651705 Aug 24 05:37:12 AM UTC 24 Aug 24 05:52:07 AM UTC 24 103141638913 ps
T1826 /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/35.xbar_access_same_device_slow_rsp.1392082070 Aug 24 05:45:20 AM UTC 24 Aug 24 05:52:09 AM UTC 24 35613229056 ps
T1827 /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/36.xbar_stress_all_with_error.402033968 Aug 24 05:49:13 AM UTC 24 Aug 24 05:52:17 AM UTC 24 3297867646 ps
T1828 /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/38.xbar_random_zero_delays.2158530308 Aug 24 05:51:53 AM UTC 24 Aug 24 05:52:30 AM UTC 24 603230619 ps
T1829 /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/38.xbar_smoke_slow_rsp.1637101483 Aug 24 05:51:43 AM UTC 24 Aug 24 05:52:36 AM UTC 24 4428861716 ps
T1830 /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/38.xbar_same_source.3201375344 Aug 24 05:52:21 AM UTC 24 Aug 24 05:52:39 AM UTC 24 772518412 ps
T1831 /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/38.xbar_unmapped_addr.2744949175 Aug 24 05:52:23 AM UTC 24 Aug 24 05:52:40 AM UTC 24 462630843 ps
T1832 /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/38.xbar_error_and_unmapped_addr.1805665678 Aug 24 05:52:31 AM UTC 24 Aug 24 05:52:56 AM UTC 24 333810592 ps
T1833 /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/38.xbar_smoke_large_delays.3772244572 Aug 24 05:51:36 AM UTC 24 Aug 24 05:53:00 AM UTC 24 9667933219 ps
T1834 /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/38.xbar_access_same_device.1456919850 Aug 24 05:52:04 AM UTC 24 Aug 24 05:53:01 AM UTC 24 1869391105 ps
T868 /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/36.xbar_stress_all_with_reset_error.4020421773 Aug 24 05:49:16 AM UTC 24 Aug 24 05:53:05 AM UTC 24 1391729580 ps
T1835 /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/39.xbar_smoke.3385640195 Aug 24 05:53:10 AM UTC 24 Aug 24 05:53:16 AM UTC 24 38991435 ps
T1836 /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/38.xbar_random_slow_rsp.2415573860 Aug 24 05:51:58 AM UTC 24 Aug 24 05:53:17 AM UTC 24 6567794036 ps
T1837 /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/35.xbar_random_large_delays.3593635765 Aug 24 05:44:16 AM UTC 24 Aug 24 05:53:17 AM UTC 24 65493987584 ps
T539 /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/36.xbar_stress_all.3927825919 Aug 24 05:48:50 AM UTC 24 Aug 24 05:53:18 AM UTC 24 10433875889 ps
T1838 /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/39.xbar_smoke_zero_delays.411744028 Aug 24 05:53:14 AM UTC 24 Aug 24 05:53:20 AM UTC 24 43464580 ps
T1839 /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/33.xbar_random_slow_rsp.3190210162 Aug 24 05:41:15 AM UTC 24 Aug 24 05:53:23 AM UTC 24 62313015841 ps
T597 /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/38.xbar_error_random.2554877462 Aug 24 05:52:22 AM UTC 24 Aug 24 05:53:31 AM UTC 24 2698854041 ps
T1840 /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/39.xbar_random_zero_delays.1453383521 Aug 24 05:53:31 AM UTC 24 Aug 24 05:53:38 AM UTC 24 43533787 ps
T1841 /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/39.xbar_same_source.60845401 Aug 24 05:53:46 AM UTC 24 Aug 24 05:54:02 AM UTC 24 279381118 ps
T1842 /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/39.xbar_random.618083298 Aug 24 05:53:30 AM UTC 24 Aug 24 05:54:06 AM UTC 24 1325891071 ps
T1843 /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/39.xbar_smoke_slow_rsp.1097767880 Aug 24 05:53:19 AM UTC 24 Aug 24 05:54:09 AM UTC 24 4023994543 ps
T1844 /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/37.xbar_stress_all_with_error.1909437928 Aug 24 05:51:23 AM UTC 24 Aug 24 05:54:14 AM UTC 24 3234895056 ps
T1845 /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/39.xbar_error_random.3304800280 Aug 24 05:53:53 AM UTC 24 Aug 24 05:54:18 AM UTC 24 419073979 ps
T1846 /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/39.xbar_smoke_large_delays.152608867 Aug 24 05:53:15 AM UTC 24 Aug 24 05:54:36 AM UTC 24 9379164316 ps
T1847 /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/38.xbar_stress_all_with_error.2696886985 Aug 24 05:52:53 AM UTC 24 Aug 24 05:54:44 AM UTC 24 2159682425 ps
T1848 /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/39.xbar_unmapped_addr.2918005975 Aug 24 05:54:16 AM UTC 24 Aug 24 05:54:52 AM UTC 24 1179856294 ps
T1849 /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/39.xbar_error_and_unmapped_addr.3586154892 Aug 24 05:54:20 AM UTC 24 Aug 24 05:55:00 AM UTC 24 1444553524 ps
T844 /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/37.xbar_stress_all_with_reset_error.4233235598 Aug 24 05:51:25 AM UTC 24 Aug 24 05:55:05 AM UTC 24 2467885222 ps
T1850 /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/40.xbar_smoke.3557665466 Aug 24 05:54:59 AM UTC 24 Aug 24 05:55:07 AM UTC 24 156166327 ps
T1851 /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/40.xbar_smoke_zero_delays.3267217150 Aug 24 05:55:06 AM UTC 24 Aug 24 05:55:12 AM UTC 24 47569824 ps
T1852 /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/39.xbar_access_same_device.2937383574 Aug 24 05:53:35 AM UTC 24 Aug 24 05:55:15 AM UTC 24 3410435475 ps
T1853 /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/39.xbar_stress_all.3441316479 Aug 24 05:54:24 AM UTC 24 Aug 24 05:55:17 AM UTC 24 867159370 ps
T1854 /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/38.xbar_random_large_delays.2988131721 Aug 24 05:51:56 AM UTC 24 Aug 24 05:55:21 AM UTC 24 22727684129 ps
T1855 /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/38.xbar_stress_all_with_rand_reset.2588523434 Aug 24 05:52:50 AM UTC 24 Aug 24 05:55:25 AM UTC 24 1399888627 ps
T1856 /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/40.xbar_random_zero_delays.2595431620 Aug 24 05:55:27 AM UTC 24 Aug 24 05:55:32 AM UTC 24 37826623 ps
T1857 /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/36.xbar_access_same_device_slow_rsp.2475365592 Aug 24 05:47:53 AM UTC 24 Aug 24 05:55:40 AM UTC 24 40777428837 ps
T1858 /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/37.xbar_stress_all.3882074462 Aug 24 05:50:57 AM UTC 24 Aug 24 05:55:42 AM UTC 24 10120686156 ps
T1859 /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/38.xbar_stress_all.2331025567 Aug 24 05:52:45 AM UTC 24 Aug 24 05:55:56 AM UTC 24 3544011046 ps
T1860 /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/39.xbar_stress_all_with_error.180089637 Aug 24 05:54:32 AM UTC 24 Aug 24 05:56:02 AM UTC 24 1642907830 ps
T1861 /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/40.xbar_random_slow_rsp.2828932845 Aug 24 05:55:32 AM UTC 24 Aug 24 05:56:03 AM UTC 24 2438155868 ps
T1862 /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/40.xbar_unmapped_addr.1397623105 Aug 24 05:55:56 AM UTC 24 Aug 24 05:56:03 AM UTC 24 44842679 ps
T1863 /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/40.xbar_smoke_large_delays.3865106613 Aug 24 05:55:14 AM UTC 24 Aug 24 05:56:04 AM UTC 24 5884757170 ps
T1864 /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/39.xbar_random_slow_rsp.3246287550 Aug 24 05:53:32 AM UTC 24 Aug 24 05:56:05 AM UTC 24 13082261905 ps
T1865 /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/40.xbar_same_source.1405287981 Aug 24 05:55:47 AM UTC 24 Aug 24 05:56:17 AM UTC 24 563130771 ps
T1866 /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/40.xbar_random.1286426436 Aug 24 05:55:21 AM UTC 24 Aug 24 05:56:21 AM UTC 24 2462156217 ps
T1867 /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/40.xbar_smoke_slow_rsp.3741161159 Aug 24 05:55:19 AM UTC 24 Aug 24 05:56:22 AM UTC 24 5028945667 ps
T1868 /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/41.xbar_smoke.3719717242 Aug 24 05:56:19 AM UTC 24 Aug 24 05:56:25 AM UTC 24 54092841 ps
T1869 /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/40.xbar_access_same_device.3046883105 Aug 24 05:55:35 AM UTC 24 Aug 24 05:56:27 AM UTC 24 1768536603 ps
T1870 /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/40.xbar_error_random.185850028 Aug 24 05:55:55 AM UTC 24 Aug 24 05:56:27 AM UTC 24 1413405957 ps
T1871 /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/40.xbar_stress_all_with_error.3784429875 Aug 24 05:56:17 AM UTC 24 Aug 24 05:56:29 AM UTC 24 209747970 ps
T1872 /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/40.xbar_error_and_unmapped_addr.932558043 Aug 24 05:56:10 AM UTC 24 Aug 24 05:56:35 AM UTC 24 313647175 ps
T1873 /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/41.xbar_smoke_zero_delays.2109179585 Aug 24 05:56:31 AM UTC 24 Aug 24 05:56:37 AM UTC 24 45515066 ps
T1874 /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/36.xbar_random_large_delays.1130438326 Aug 24 05:47:25 AM UTC 24 Aug 24 05:56:39 AM UTC 24 66793398586 ps
T1875 /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/41.xbar_random_zero_delays.1138939245 Aug 24 05:56:41 AM UTC 24 Aug 24 05:56:51 AM UTC 24 95943807 ps
T1876 /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/41.xbar_access_same_device.2989937202 Aug 24 05:56:49 AM UTC 24 Aug 24 05:57:11 AM UTC 24 673729699 ps
T1877 /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/41.xbar_error_random.4287774830 Aug 24 05:57:05 AM UTC 24 Aug 24 05:57:16 AM UTC 24 158679030 ps
T1878 /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/41.xbar_same_source.375948875 Aug 24 05:56:54 AM UTC 24 Aug 24 05:57:20 AM UTC 24 1095595121 ps
T1879 /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/40.xbar_stress_all.3106912630 Aug 24 05:56:16 AM UTC 24 Aug 24 05:57:23 AM UTC 24 1179633185 ps
T799 /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/30.xbar_access_same_device_slow_rsp.4105883163 Aug 24 05:34:23 AM UTC 24 Aug 24 05:57:23 AM UTC 24 118348682582 ps
T1880 /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/38.xbar_stress_all_with_reset_error.2079445100 Aug 24 05:52:54 AM UTC 24 Aug 24 05:57:26 AM UTC 24 5845237945 ps
T1881 /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/41.xbar_random.605961233 Aug 24 05:56:39 AM UTC 24 Aug 24 05:57:26 AM UTC 24 1958304319 ps
T1882 /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/37.xbar_random_slow_rsp.2731479140 Aug 24 05:50:19 AM UTC 24 Aug 24 05:57:27 AM UTC 24 35137378774 ps
T1883 /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/41.xbar_stress_all.2942145432 Aug 24 05:57:34 AM UTC 24 Aug 24 05:57:38 AM UTC 24 5796635 ps
T1884 /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/34.xbar_random_large_delays.1233378869 Aug 24 05:42:38 AM UTC 24 Aug 24 05:57:38 AM UTC 24 110369009373 ps
T1885 /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/41.xbar_smoke_slow_rsp.1980146619 Aug 24 05:56:35 AM UTC 24 Aug 24 05:57:41 AM UTC 24 5244846558 ps
T1886 /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/41.xbar_error_and_unmapped_addr.1587711894 Aug 24 05:57:31 AM UTC 24 Aug 24 05:57:44 AM UTC 24 355917372 ps
T1887 /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/42.xbar_smoke.3002180004 Aug 24 05:57:40 AM UTC 24 Aug 24 05:57:47 AM UTC 24 174374968 ps
T1888 /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/42.xbar_smoke_zero_delays.2665936260 Aug 24 05:57:41 AM UTC 24 Aug 24 05:57:47 AM UTC 24 37648413 ps
T1889 /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/41.xbar_smoke_large_delays.856688493 Aug 24 05:56:35 AM UTC 24 Aug 24 05:57:49 AM UTC 24 8589908999 ps
T1890 /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/32.xbar_access_same_device_slow_rsp.656480803 Aug 24 05:39:05 AM UTC 24 Aug 24 05:57:55 AM UTC 24 92976986096 ps
T1891 /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/41.xbar_unmapped_addr.2151445324 Aug 24 05:57:26 AM UTC 24 Aug 24 05:57:55 AM UTC 24 332751654 ps
T1892 /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/42.xbar_random.2362768001 Aug 24 05:57:55 AM UTC 24 Aug 24 05:58:10 AM UTC 24 508159325 ps
T1893 /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/42.xbar_access_same_device.214252556 Aug 24 05:58:02 AM UTC 24 Aug 24 05:58:12 AM UTC 24 115160038 ps
T1894 /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/39.xbar_stress_all_with_reset_error.4285968801 Aug 24 05:54:50 AM UTC 24 Aug 24 05:58:18 AM UTC 24 2726029000 ps
T1895 /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/42.xbar_random_zero_delays.1894168131 Aug 24 05:57:59 AM UTC 24 Aug 24 05:58:27 AM UTC 24 438206596 ps
T1896 /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/42.xbar_unmapped_addr.2498503119 Aug 24 05:58:27 AM UTC 24 Aug 24 05:58:37 AM UTC 24 80359459 ps
T1897 /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/42.xbar_same_source.795498125 Aug 24 05:58:09 AM UTC 24 Aug 24 05:58:39 AM UTC 24 1411581033 ps
T1898 /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/42.xbar_smoke_slow_rsp.3657969089 Aug 24 05:57:53 AM UTC 24 Aug 24 05:58:45 AM UTC 24 4210727713 ps
T1899 /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/42.xbar_error_random.2994589212 Aug 24 05:58:25 AM UTC 24 Aug 24 05:58:56 AM UTC 24 1171886632 ps
T1900 /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/40.xbar_random_large_delays.2427764632 Aug 24 05:55:29 AM UTC 24 Aug 24 05:59:00 AM UTC 24 25659728539 ps
T1901 /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/42.xbar_error_and_unmapped_addr.1484428610 Aug 24 05:58:33 AM UTC 24 Aug 24 05:59:02 AM UTC 24 1054624150 ps
T1902 /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/41.xbar_stress_all_with_rand_reset.3470940795 Aug 24 05:57:37 AM UTC 24 Aug 24 05:59:15 AM UTC 24 370927508 ps
T1903 /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/43.xbar_smoke.4106733805 Aug 24 05:59:10 AM UTC 24 Aug 24 05:59:16 AM UTC 24 44577527 ps
T1904 /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/42.xbar_smoke_large_delays.1576987380 Aug 24 05:57:52 AM UTC 24 Aug 24 05:59:17 AM UTC 24 10384051401 ps
T1905 /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/43.xbar_smoke_zero_delays.3574525153 Aug 24 05:59:14 AM UTC 24 Aug 24 05:59:20 AM UTC 24 46465134 ps
T1906 /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/43.xbar_random_zero_delays.4291353268 Aug 24 05:59:31 AM UTC 24 Aug 24 05:59:45 AM UTC 24 172491906 ps
T1907 /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/37.xbar_stress_all_with_rand_reset.321503490 Aug 24 05:50:58 AM UTC 24 Aug 24 06:00:00 AM UTC 24 6315969491 ps
T1908 /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/42.xbar_random_slow_rsp.2936687592 Aug 24 05:58:01 AM UTC 24 Aug 24 06:00:02 AM UTC 24 10481736189 ps
T1909 /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/42.xbar_stress_all_with_error.390514419 Aug 24 05:58:53 AM UTC 24 Aug 24 06:00:08 AM UTC 24 3171828049 ps
T1910 /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/41.xbar_random_large_delays.1036852755 Aug 24 05:56:41 AM UTC 24 Aug 24 06:00:12 AM UTC 24 26122173881 ps
T1911 /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/43.xbar_random.782335162 Aug 24 05:59:30 AM UTC 24 Aug 24 06:00:15 AM UTC 24 1716092009 ps
T1912 /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/41.xbar_stress_all_with_reset_error.2584862833 Aug 24 05:57:40 AM UTC 24 Aug 24 06:00:19 AM UTC 24 3278371153 ps
T1913 /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/43.xbar_smoke_slow_rsp.2135634691 Aug 24 05:59:29 AM UTC 24 Aug 24 06:00:26 AM UTC 24 4609528144 ps
T1914 /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/43.xbar_smoke_large_delays.2641710767 Aug 24 05:59:16 AM UTC 24 Aug 24 06:00:32 AM UTC 24 8844720753 ps
T1915 /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/40.xbar_stress_all_with_reset_error.3487581383 Aug 24 05:56:18 AM UTC 24 Aug 24 06:00:36 AM UTC 24 3050345616 ps
T1916 /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/43.xbar_unmapped_addr.3489127923 Aug 24 06:00:29 AM UTC 24 Aug 24 06:00:39 AM UTC 24 71654833 ps
T1917 /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/43.xbar_error_and_unmapped_addr.1955420437 Aug 24 06:00:33 AM UTC 24 Aug 24 06:00:39 AM UTC 24 63214041 ps
T1918 /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/43.xbar_error_random.3607987249 Aug 24 06:00:27 AM UTC 24 Aug 24 06:00:42 AM UTC 24 545068359 ps
T1919 /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/43.xbar_access_same_device.488556725 Aug 24 06:00:15 AM UTC 24 Aug 24 06:00:52 AM UTC 24 1171430965 ps
T1920 /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/44.xbar_smoke.1672380166 Aug 24 06:00:54 AM UTC 24 Aug 24 06:01:00 AM UTC 24 51688618 ps
T1921 /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/43.xbar_same_source.4105696341 Aug 24 06:00:22 AM UTC 24 Aug 24 06:01:02 AM UTC 24 1993076610 ps
T1922 /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/44.xbar_smoke_zero_delays.1052605971 Aug 24 06:00:56 AM UTC 24 Aug 24 06:01:03 AM UTC 24 58287299 ps
T1923 /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/36.xbar_random_slow_rsp.9461664 Aug 24 05:47:44 AM UTC 24 Aug 24 06:01:21 AM UTC 24 69269744868 ps
T838 /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/40.xbar_stress_all_with_rand_reset.2026341492 Aug 24 05:56:17 AM UTC 24 Aug 24 06:01:23 AM UTC 24 5399791557 ps
T1924 /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/44.xbar_random_zero_delays.1047962906 Aug 24 06:01:17 AM UTC 24 Aug 24 06:01:26 AM UTC 24 95244601 ps
T1925 /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/43.xbar_stress_all_with_error.665425291 Aug 24 06:00:50 AM UTC 24 Aug 24 06:01:29 AM UTC 24 1647030683 ps
T1926 /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/42.xbar_random_large_delays.3066500284 Aug 24 05:58:01 AM UTC 24 Aug 24 06:01:29 AM UTC 24 25183895682 ps
T1927 /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/39.xbar_stress_all_with_rand_reset.3597962753 Aug 24 05:54:29 AM UTC 24 Aug 24 06:01:35 AM UTC 24 8317821088 ps
T1928 /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/44.xbar_random.2390260209 Aug 24 06:01:17 AM UTC 24 Aug 24 06:01:43 AM UTC 24 424283710 ps
T1929 /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/44.xbar_smoke_large_delays.1726165363 Aug 24 06:01:06 AM UTC 24 Aug 24 06:01:52 AM UTC 24 5303024234 ps
T1930 /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/43.xbar_stress_all.2727381638 Aug 24 06:00:40 AM UTC 24 Aug 24 06:01:53 AM UTC 24 1216117251 ps
T1931 /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/44.xbar_same_source.3118650459 Aug 24 06:01:43 AM UTC 24 Aug 24 06:02:05 AM UTC 24 379999391 ps
T1932 /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/44.xbar_unmapped_addr.4282229806 Aug 24 06:01:57 AM UTC 24 Aug 24 06:02:06 AM UTC 24 65055623 ps
T1933 /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/44.xbar_error_and_unmapped_addr.2047514694 Aug 24 06:02:06 AM UTC 24 Aug 24 06:02:18 AM UTC 24 280812480 ps
T1934 /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/44.xbar_smoke_slow_rsp.4277951556 Aug 24 06:01:14 AM UTC 24 Aug 24 06:02:18 AM UTC 24 5395944426 ps
T1935 /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/41.xbar_stress_all_with_error.1132553266 Aug 24 05:57:37 AM UTC 24 Aug 24 06:02:22 AM UTC 24 12087509621 ps
T1936 /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/44.xbar_error_random.4234151082 Aug 24 06:01:49 AM UTC 24 Aug 24 06:02:24 AM UTC 24 1317690621 ps
T1937 /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/34.xbar_access_same_device_slow_rsp.1526659277 Aug 24 05:43:04 AM UTC 24 Aug 24 06:02:26 AM UTC 24 98090761018 ps
T1938 /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/44.xbar_access_same_device.4188571286 Aug 24 06:01:40 AM UTC 24 Aug 24 06:02:30 AM UTC 24 1812011001 ps
T1939 /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/44.xbar_random_large_delays.2931709869 Aug 24 06:01:35 AM UTC 24 Aug 24 06:02:30 AM UTC 24 6521522458 ps
T1940 /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/45.xbar_smoke.4251611506 Aug 24 06:02:32 AM UTC 24 Aug 24 06:02:40 AM UTC 24 213012480 ps
T1941 /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/45.xbar_smoke_zero_delays.649476950 Aug 24 06:02:36 AM UTC 24 Aug 24 06:02:42 AM UTC 24 46323552 ps
T1942 /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/43.xbar_stress_all_with_reset_error.333033072 Aug 24 06:00:53 AM UTC 24 Aug 24 06:02:45 AM UTC 24 420700051 ps
T1943 /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/43.xbar_stress_all_with_rand_reset.734284989 Aug 24 06:00:46 AM UTC 24 Aug 24 06:02:56 AM UTC 24 1291212086 ps
T1944 /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/37.xbar_random_large_delays.711116403 Aug 24 05:50:06 AM UTC 24 Aug 24 06:02:57 AM UTC 24 92223643553 ps
T1945 /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/42.xbar_stress_all.3999875451 Aug 24 05:58:41 AM UTC 24 Aug 24 06:03:00 AM UTC 24 4276718464 ps
T1946 /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/45.xbar_random_zero_delays.1733771292 Aug 24 06:02:44 AM UTC 24 Aug 24 06:03:02 AM UTC 24 272610125 ps
T1947 /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/39.xbar_access_same_device_slow_rsp.3090594251 Aug 24 05:53:38 AM UTC 24 Aug 24 06:03:09 AM UTC 24 45129079612 ps
T1948 /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/45.xbar_error_random.2607032785 Aug 24 06:03:13 AM UTC 24 Aug 24 06:03:30 AM UTC 24 242885331 ps
T1949 /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/44.xbar_stress_all.1837609699 Aug 24 06:02:07 AM UTC 24 Aug 24 06:03:35 AM UTC 24 1291745987 ps
T1950 /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/42.xbar_stress_all_with_reset_error.761882433 Aug 24 05:58:59 AM UTC 24 Aug 24 06:03:38 AM UTC 24 3675548062 ps
T800 /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/37.xbar_access_same_device_slow_rsp.1493299303 Aug 24 05:50:37 AM UTC 24 Aug 24 06:03:39 AM UTC 24 64818023339 ps
T1951 /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/44.xbar_stress_all_with_error.897811272 Aug 24 06:02:21 AM UTC 24 Aug 24 06:03:41 AM UTC 24 1541593262 ps
T1952 /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/45.xbar_access_same_device.3929899690 Aug 24 06:03:00 AM UTC 24 Aug 24 06:03:42 AM UTC 24 1474422793 ps
T1953 /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/45.xbar_smoke_slow_rsp.3876202192 Aug 24 06:02:40 AM UTC 24 Aug 24 06:03:43 AM UTC 24 5041352449 ps
T1954 /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/45.xbar_smoke_large_delays.2712484725 Aug 24 06:02:38 AM UTC 24 Aug 24 06:03:46 AM UTC 24 8146967211 ps
T1955 /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/45.xbar_random.450783908 Aug 24 06:02:44 AM UTC 24 Aug 24 06:03:47 AM UTC 24 2277910026 ps
T1956 /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/45.xbar_unmapped_addr.3490448451 Aug 24 06:03:17 AM UTC 24 Aug 24 06:03:51 AM UTC 24 1179798230 ps
T1957 /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/45.xbar_error_and_unmapped_addr.945464728 Aug 24 06:03:22 AM UTC 24 Aug 24 06:03:55 AM UTC 24 1133758388 ps
T1958 /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/45.xbar_same_source.3763596945 Aug 24 06:03:11 AM UTC 24 Aug 24 06:03:59 AM UTC 24 2261708001 ps
T1959 /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/46.xbar_smoke_zero_delays.1625430033 Aug 24 06:03:56 AM UTC 24 Aug 24 06:04:02 AM UTC 24 45275894 ps
T1960 /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/46.xbar_smoke.297861336 Aug 24 06:03:55 AM UTC 24 Aug 24 06:04:03 AM UTC 24 235047645 ps
T1961 /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/44.xbar_stress_all_with_rand_reset.2947201684 Aug 24 06:02:19 AM UTC 24 Aug 24 06:04:07 AM UTC 24 331985391 ps
T1962 /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/46.xbar_random.3195035509 Aug 24 06:04:01 AM UTC 24 Aug 24 06:04:09 AM UTC 24 208566454 ps
T1963 /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/46.xbar_same_source.676971303 Aug 24 06:04:21 AM UTC 24 Aug 24 06:04:35 AM UTC 24 535127782 ps
T1964 /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/46.xbar_smoke_slow_rsp.4075613741 Aug 24 06:04:00 AM UTC 24 Aug 24 06:04:38 AM UTC 24 2912606424 ps
T1965 /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/46.xbar_random_zero_delays.3847668549 Aug 24 06:04:05 AM UTC 24 Aug 24 06:04:42 AM UTC 24 542191107 ps
T1966 /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/45.xbar_stress_all.2723951102 Aug 24 06:03:45 AM UTC 24 Aug 24 06:04:48 AM UTC 24 1067374988 ps
T1967 /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/46.xbar_smoke_large_delays.158757787 Aug 24 06:03:57 AM UTC 24 Aug 24 06:04:51 AM UTC 24 6004202818 ps
T1968 /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/46.xbar_error_random.2256933211 Aug 24 06:04:23 AM UTC 24 Aug 24 06:04:53 AM UTC 24 531319749 ps
T1969 /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/45.xbar_stress_all_with_rand_reset.3371001627 Aug 24 06:03:50 AM UTC 24 Aug 24 06:04:54 AM UTC 24 255495663 ps
T1970 /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/46.xbar_error_and_unmapped_addr.1244376961 Aug 24 06:04:52 AM UTC 24 Aug 24 06:05:08 AM UTC 24 169257359 ps
T1971 /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/44.xbar_access_same_device_slow_rsp.1813071348 Aug 24 06:01:43 AM UTC 24 Aug 24 06:05:10 AM UTC 24 17903577018 ps
T1972 /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/47.xbar_smoke.955390057 Aug 24 06:05:08 AM UTC 24 Aug 24 06:05:13 AM UTC 24 44202456 ps
T1973 /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/47.xbar_smoke_zero_delays.3665720886 Aug 24 06:05:23 AM UTC 24 Aug 24 06:05:28 AM UTC 24 36875636 ps
T1974 /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/45.xbar_random_large_delays.3602686940 Aug 24 06:02:54 AM UTC 24 Aug 24 06:05:32 AM UTC 24 17845560780 ps
T1975 /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/42.xbar_stress_all_with_rand_reset.646327027 Aug 24 05:58:51 AM UTC 24 Aug 24 06:05:32 AM UTC 24 11157333967 ps
T1976 /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/46.xbar_unmapped_addr.2922619195 Aug 24 06:04:49 AM UTC 24 Aug 24 06:05:36 AM UTC 24 1488075238 ps
T1977 /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/46.xbar_access_same_device.2829146464 Aug 24 06:04:16 AM UTC 24 Aug 24 06:05:38 AM UTC 24 2990480641 ps
T1978 /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/47.xbar_random_zero_delays.1019464577 Aug 24 06:05:46 AM UTC 24 Aug 24 06:05:56 AM UTC 24 105567328 ps
T1979 /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/44.xbar_stress_all_with_reset_error.3832999995 Aug 24 06:02:32 AM UTC 24 Aug 24 06:05:57 AM UTC 24 6394951381 ps
T1980 /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/47.xbar_smoke_slow_rsp.1204968508 Aug 24 06:05:28 AM UTC 24 Aug 24 06:06:22 AM UTC 24 4438337153 ps
T1981 /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/47.xbar_smoke_large_delays.3027690399 Aug 24 06:05:24 AM UTC 24 Aug 24 06:06:29 AM UTC 24 8006575479 ps
T1982 /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/46.xbar_stress_all.2268314040 Aug 24 06:04:55 AM UTC 24 Aug 24 06:06:30 AM UTC 24 3723685290 ps
T1983 /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/47.xbar_random.3475597646 Aug 24 06:05:42 AM UTC 24 Aug 24 06:06:34 AM UTC 24 2015586396 ps
T1984 /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/45.xbar_stress_all_with_error.265377367 Aug 24 06:03:53 AM UTC 24 Aug 24 06:06:35 AM UTC 24 6399953080 ps
T1985 /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/43.xbar_random_large_delays.401043508 Aug 24 05:59:34 AM UTC 24 Aug 24 06:06:37 AM UTC 24 53387740293 ps
T1986 /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/47.xbar_same_source.3804966466 Aug 24 06:06:11 AM UTC 24 Aug 24 06:06:40 AM UTC 24 1252680494 ps
T1987 /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/46.xbar_stress_all_with_reset_error.537635235 Aug 24 06:05:07 AM UTC 24 Aug 24 06:06:46 AM UTC 24 370387604 ps
T1988 /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/47.xbar_access_same_device.171836607 Aug 24 06:05:52 AM UTC 24 Aug 24 06:06:56 AM UTC 24 2080042616 ps
T1989 /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/46.xbar_stress_all_with_error.1697842363 Aug 24 06:05:06 AM UTC 24 Aug 24 06:06:57 AM UTC 24 4404165988 ps
T1990 /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/47.xbar_unmapped_addr.3685633386 Aug 24 06:06:43 AM UTC 24 Aug 24 06:07:02 AM UTC 24 175733093 ps
T1991 /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/48.xbar_smoke.424112707 Aug 24 06:07:00 AM UTC 24 Aug 24 06:07:06 AM UTC 24 48436251 ps
T1992 /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/48.xbar_smoke_zero_delays.3911207399 Aug 24 06:07:10 AM UTC 24 Aug 24 06:07:16 AM UTC 24 46843057 ps
T1993 /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/47.xbar_error_and_unmapped_addr.834899993 Aug 24 06:06:45 AM UTC 24 Aug 24 06:07:19 AM UTC 24 1069559076 ps
T1994 /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/39.xbar_random_large_delays.2954955841 Aug 24 05:53:31 AM UTC 24 Aug 24 06:07:30 AM UTC 24 102517786838 ps
T1995 /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/47.xbar_error_random.754408040 Aug 24 06:06:36 AM UTC 24 Aug 24 06:07:35 AM UTC 24 2254642932 ps
T1996 /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/48.xbar_random_zero_delays.3606603147 Aug 24 06:07:30 AM UTC 24 Aug 24 06:07:45 AM UTC 24 160213203 ps
T1997 /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/46.xbar_stress_all_with_rand_reset.1109996029 Aug 24 06:05:01 AM UTC 24 Aug 24 06:07:45 AM UTC 24 550248027 ps
T1998 /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/43.xbar_random_slow_rsp.875522790 Aug 24 05:59:59 AM UTC 24 Aug 24 06:08:05 AM UTC 24 40904926331 ps
T1999 /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/48.xbar_random.3077149597 Aug 24 06:07:20 AM UTC 24 Aug 24 06:08:11 AM UTC 24 1863082307 ps
T2000 /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/48.xbar_smoke_large_delays.2853155415 Aug 24 06:07:11 AM UTC 24 Aug 24 06:08:15 AM UTC 24 7995535275 ps
T2001 /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/48.xbar_same_source.1196955519 Aug 24 06:07:59 AM UTC 24 Aug 24 06:08:18 AM UTC 24 341821055 ps
T2002 /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/48.xbar_smoke_slow_rsp.1110933074 Aug 24 06:07:16 AM UTC 24 Aug 24 06:08:26 AM UTC 24 5799009363 ps
T2003 /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/48.xbar_access_same_device.1702189713 Aug 24 06:07:50 AM UTC 24 Aug 24 06:08:27 AM UTC 24 533544477 ps
T2004 /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/48.xbar_error_random.1995315124 Aug 24 06:08:20 AM UTC 24 Aug 24 06:08:30 AM UTC 24 137550049 ps
T2005 /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/47.xbar_stress_all_with_reset_error.4180122505 Aug 24 06:06:54 AM UTC 24 Aug 24 06:08:32 AM UTC 24 361262708 ps
T2006 /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/41.xbar_random_slow_rsp.1277412796 Aug 24 05:56:43 AM UTC 24 Aug 24 06:08:35 AM UTC 24 59122089305 ps
T2007 /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/48.xbar_error_and_unmapped_addr.1438363826 Aug 24 06:08:30 AM UTC 24 Aug 24 06:08:36 AM UTC 24 35859102 ps
T2008 /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/47.xbar_stress_all_with_rand_reset.1544812625 Aug 24 06:06:49 AM UTC 24 Aug 24 06:08:42 AM UTC 24 540793412 ps
T2009 /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/49.xbar_smoke_zero_delays.3585518078 Aug 24 06:08:49 AM UTC 24 Aug 24 06:08:55 AM UTC 24 41508579 ps
T2010 /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/49.xbar_smoke.3010917810 Aug 24 06:08:47 AM UTC 24 Aug 24 06:08:55 AM UTC 24 224513392 ps
T2011 /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/48.xbar_unmapped_addr.3836191634 Aug 24 06:08:26 AM UTC 24 Aug 24 06:08:56 AM UTC 24 963065407 ps
T2012 /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/47.xbar_stress_all.2178450073 Aug 24 06:06:48 AM UTC 24 Aug 24 06:09:04 AM UTC 24 5733333150 ps
T2013 /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/48.xbar_stress_all.1764027757 Aug 24 06:08:32 AM UTC 24 Aug 24 06:09:27 AM UTC 24 1899179836 ps
T2014 /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/49.xbar_random_zero_delays.3765209549 Aug 24 06:09:09 AM UTC 24 Aug 24 06:09:35 AM UTC 24 380533985 ps
T2015 /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/48.xbar_stress_all_with_error.3227225928 Aug 24 06:08:42 AM UTC 24 Aug 24 06:09:37 AM UTC 24 974901097 ps
T2016 /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/48.xbar_random_large_delays.1484822679 Aug 24 06:07:33 AM UTC 24 Aug 24 06:09:39 AM UTC 24 14952421038 ps
T2017 /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/49.xbar_random.2530062960 Aug 24 06:09:09 AM UTC 24 Aug 24 06:09:42 AM UTC 24 494092796 ps
T2018 /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/45.xbar_stress_all_with_reset_error.816131483 Aug 24 06:03:54 AM UTC 24 Aug 24 06:09:43 AM UTC 24 5233194154 ps
T2019 /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/41.xbar_access_same_device_slow_rsp.858131178 Aug 24 05:56:52 AM UTC 24 Aug 24 06:09:46 AM UTC 24 67441784700 ps
T2020 /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/49.xbar_smoke_slow_rsp.36171428 Aug 24 06:08:56 AM UTC 24 Aug 24 06:09:54 AM UTC 24 4566225905 ps
T2021 /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/49.xbar_smoke_large_delays.3989847721 Aug 24 06:08:50 AM UTC 24 Aug 24 06:09:58 AM UTC 24 8146252524 ps
T2022 /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/49.xbar_error_and_unmapped_addr.3120720499 Aug 24 06:09:57 AM UTC 24 Aug 24 06:10:05 AM UTC 24 60241496 ps
T2023 /workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/49.xbar_unmapped_addr.3750387682 Aug 24 06:09:57 AM UTC 24 Aug 24 06:10:05 AM UTC 24 155077688 ps
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