| T2515 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/77.xbar_same_source.3809731156 |
|
|
Aug 24 06:57:15 AM UTC 24 |
Aug 24 06:57:25 AM UTC 24 |
119518263 ps |
| T2516 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/77.xbar_smoke_slow_rsp.95998096 |
|
|
Aug 24 06:56:43 AM UTC 24 |
Aug 24 06:57:33 AM UTC 24 |
4167334600 ps |
| T2517 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/76.xbar_stress_all_with_reset_error.4275795646 |
|
|
Aug 24 06:56:27 AM UTC 24 |
Aug 24 06:57:41 AM UTC 24 |
367359889 ps |
| T2518 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/77.xbar_smoke_large_delays.1432048811 |
|
|
Aug 24 06:56:42 AM UTC 24 |
Aug 24 06:57:44 AM UTC 24 |
7442566728 ps |
| T2519 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/77.xbar_access_same_device.3903941352 |
|
|
Aug 24 06:57:01 AM UTC 24 |
Aug 24 06:57:46 AM UTC 24 |
1658525306 ps |
| T2520 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/76.xbar_random_slow_rsp.134453796 |
|
|
Aug 24 06:56:01 AM UTC 24 |
Aug 24 06:57:54 AM UTC 24 |
9083648249 ps |
| T2521 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/77.xbar_error_random.1993284031 |
|
|
Aug 24 06:57:34 AM UTC 24 |
Aug 24 06:57:57 AM UTC 24 |
395039926 ps |
| T2522 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/75.xbar_stress_all_with_error.2231748656 |
|
|
Aug 24 06:54:30 AM UTC 24 |
Aug 24 06:58:05 AM UTC 24 |
9378282385 ps |
| T2523 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/77.xbar_unmapped_addr.815039880 |
|
|
Aug 24 06:57:38 AM UTC 24 |
Aug 24 06:58:12 AM UTC 24 |
1148783533 ps |
| T2524 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/76.xbar_stress_all_with_error.4264106113 |
|
|
Aug 24 06:56:26 AM UTC 24 |
Aug 24 06:58:13 AM UTC 24 |
5175689345 ps |
| T2525 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/77.xbar_error_and_unmapped_addr.2287291539 |
|
|
Aug 24 06:57:40 AM UTC 24 |
Aug 24 06:58:15 AM UTC 24 |
1337310374 ps |
| T2526 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/78.xbar_smoke.3727116056 |
|
|
Aug 24 06:58:08 AM UTC 24 |
Aug 24 06:58:17 AM UTC 24 |
240885210 ps |
| T2527 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/78.xbar_smoke_zero_delays.1612942959 |
|
|
Aug 24 06:58:11 AM UTC 24 |
Aug 24 06:58:17 AM UTC 24 |
45295555 ps |
| T2528 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/71.xbar_random_large_delays.1703885649 |
|
|
Aug 24 06:45:51 AM UTC 24 |
Aug 24 06:58:25 AM UTC 24 |
86946998082 ps |
| T2529 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/78.xbar_random.4063853562 |
|
|
Aug 24 06:58:27 AM UTC 24 |
Aug 24 06:58:40 AM UTC 24 |
393066076 ps |
| T2530 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/76.xbar_stress_all.2715618148 |
|
|
Aug 24 06:56:17 AM UTC 24 |
Aug 24 06:58:51 AM UTC 24 |
2495378529 ps |
| T2531 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/78.xbar_random_zero_delays.2821470273 |
|
|
Aug 24 06:58:29 AM UTC 24 |
Aug 24 06:58:57 AM UTC 24 |
460843309 ps |
| T2532 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/73.xbar_random_slow_rsp.3515208434 |
|
|
Aug 24 06:49:05 AM UTC 24 |
Aug 24 06:58:59 AM UTC 24 |
52385429020 ps |
| T2533 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/78.xbar_access_same_device.2344561716 |
|
|
Aug 24 06:58:40 AM UTC 24 |
Aug 24 06:59:00 AM UTC 24 |
344200903 ps |
| T2534 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/77.xbar_stress_all.480767557 |
|
|
Aug 24 06:57:47 AM UTC 24 |
Aug 24 06:59:05 AM UTC 24 |
1281125537 ps |
| T2535 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/60.xbar_access_same_device_slow_rsp.2984287473 |
|
|
Aug 24 06:28:32 AM UTC 24 |
Aug 24 06:59:05 AM UTC 24 |
155319733048 ps |
| T2536 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/76.xbar_stress_all_with_rand_reset.761563023 |
|
|
Aug 24 06:56:22 AM UTC 24 |
Aug 24 06:59:09 AM UTC 24 |
511673421 ps |
| T2537 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/78.xbar_same_source.3834477558 |
|
|
Aug 24 06:59:05 AM UTC 24 |
Aug 24 06:59:15 AM UTC 24 |
320546415 ps |
| T2538 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/78.xbar_smoke_large_delays.215893182 |
|
|
Aug 24 06:58:19 AM UTC 24 |
Aug 24 06:59:25 AM UTC 24 |
7961153162 ps |
| T2539 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/78.xbar_stress_all.3957710372 |
|
|
Aug 24 06:59:19 AM UTC 24 |
Aug 24 06:59:25 AM UTC 24 |
58053187 ps |
| T2540 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/78.xbar_error_and_unmapped_addr.2166367310 |
|
|
Aug 24 06:59:14 AM UTC 24 |
Aug 24 06:59:26 AM UTC 24 |
283178107 ps |
| T2541 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/78.xbar_smoke_slow_rsp.2220254009 |
|
|
Aug 24 06:58:26 AM UTC 24 |
Aug 24 06:59:35 AM UTC 24 |
5711440478 ps |
| T2542 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/72.xbar_random_slow_rsp.2469849051 |
|
|
Aug 24 06:47:47 AM UTC 24 |
Aug 24 06:59:41 AM UTC 24 |
61563068174 ps |
| T2543 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/78.xbar_error_random.2762900997 |
|
|
Aug 24 06:59:12 AM UTC 24 |
Aug 24 06:59:43 AM UTC 24 |
1346208282 ps |
| T2544 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/79.xbar_smoke_zero_delays.2872045191 |
|
|
Aug 24 06:59:40 AM UTC 24 |
Aug 24 06:59:46 AM UTC 24 |
50994691 ps |
| T2545 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/78.xbar_unmapped_addr.638867187 |
|
|
Aug 24 06:59:14 AM UTC 24 |
Aug 24 06:59:47 AM UTC 24 |
1033668473 ps |
| T2546 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/79.xbar_smoke.568080097 |
|
|
Aug 24 06:59:40 AM UTC 24 |
Aug 24 06:59:48 AM UTC 24 |
220085624 ps |
| T2547 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/79.xbar_random.3441371744 |
|
|
Aug 24 06:59:55 AM UTC 24 |
Aug 24 07:00:06 AM UTC 24 |
224864241 ps |
| T2548 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/79.xbar_random_zero_delays.1251136880 |
|
|
Aug 24 06:59:57 AM UTC 24 |
Aug 24 07:00:09 AM UTC 24 |
140196435 ps |
| T2549 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/77.xbar_stress_all_with_error.606057526 |
|
|
Aug 24 06:57:58 AM UTC 24 |
Aug 24 07:00:15 AM UTC 24 |
5799147913 ps |
| T2550 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/79.xbar_smoke_slow_rsp.4127195793 |
|
|
Aug 24 06:59:49 AM UTC 24 |
Aug 24 07:00:41 AM UTC 24 |
4089957333 ps |
| T2551 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/79.xbar_error_random.874932387 |
|
|
Aug 24 07:00:30 AM UTC 24 |
Aug 24 07:00:45 AM UTC 24 |
509652033 ps |
| T2552 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/79.xbar_access_same_device.971826812 |
|
|
Aug 24 07:00:02 AM UTC 24 |
Aug 24 07:00:45 AM UTC 24 |
672617690 ps |
| T2553 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/77.xbar_stress_all_with_rand_reset.2170331346 |
|
|
Aug 24 06:57:55 AM UTC 24 |
Aug 24 07:00:45 AM UTC 24 |
466832345 ps |
| T2554 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/79.xbar_same_source.3631934027 |
|
|
Aug 24 07:00:24 AM UTC 24 |
Aug 24 07:00:47 AM UTC 24 |
430107922 ps |
| T2555 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/75.xbar_stress_all_with_reset_error.686083350 |
|
|
Aug 24 06:54:32 AM UTC 24 |
Aug 24 07:00:50 AM UTC 24 |
11112577019 ps |
| T2556 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/78.xbar_stress_all_with_rand_reset.231905252 |
|
|
Aug 24 06:59:20 AM UTC 24 |
Aug 24 07:00:56 AM UTC 24 |
2165089685 ps |
| T2557 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/78.xbar_stress_all_with_error.35778558 |
|
|
Aug 24 06:59:23 AM UTC 24 |
Aug 24 07:00:58 AM UTC 24 |
1993788651 ps |
| T2558 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/82.xbar_random.4108126277 |
|
|
Aug 24 07:05:17 AM UTC 24 |
Aug 24 07:05:33 AM UTC 24 |
561476360 ps |
| T2559 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/79.xbar_smoke_large_delays.539939650 |
|
|
Aug 24 06:59:40 AM UTC 24 |
Aug 24 07:01:03 AM UTC 24 |
9840091282 ps |
| T2560 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/80.xbar_smoke.1058078805 |
|
|
Aug 24 07:01:10 AM UTC 24 |
Aug 24 07:01:16 AM UTC 24 |
42467943 ps |
| T2561 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/80.xbar_smoke_zero_delays.3404155585 |
|
|
Aug 24 07:01:12 AM UTC 24 |
Aug 24 07:01:18 AM UTC 24 |
45091021 ps |
| T2562 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/79.xbar_unmapped_addr.873867320 |
|
|
Aug 24 07:00:55 AM UTC 24 |
Aug 24 07:01:21 AM UTC 24 |
728967938 ps |
| T2563 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/79.xbar_error_and_unmapped_addr.3361315190 |
|
|
Aug 24 07:01:00 AM UTC 24 |
Aug 24 07:01:34 AM UTC 24 |
1232059050 ps |
| T2564 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/78.xbar_stress_all_with_reset_error.4100397411 |
|
|
Aug 24 06:59:29 AM UTC 24 |
Aug 24 07:01:35 AM UTC 24 |
385733767 ps |
| T2565 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/70.xbar_access_same_device_slow_rsp.2767060716 |
|
|
Aug 24 06:44:25 AM UTC 24 |
Aug 24 07:01:37 AM UTC 24 |
91201822278 ps |
| T2566 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/75.xbar_random_slow_rsp.3876230596 |
|
|
Aug 24 06:53:24 AM UTC 24 |
Aug 24 07:01:58 AM UTC 24 |
43366671342 ps |
| T2567 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/80.xbar_random_zero_delays.4198017288 |
|
|
Aug 24 07:01:36 AM UTC 24 |
Aug 24 07:02:06 AM UTC 24 |
470200158 ps |
| T2568 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/80.xbar_random.4261211371 |
|
|
Aug 24 07:01:33 AM UTC 24 |
Aug 24 07:02:10 AM UTC 24 |
1542023271 ps |
| T2569 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/79.xbar_stress_all.3315029491 |
|
|
Aug 24 07:01:00 AM UTC 24 |
Aug 24 07:02:17 AM UTC 24 |
1162663769 ps |
| T2570 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/78.xbar_random_slow_rsp.2716906064 |
|
|
Aug 24 06:58:31 AM UTC 24 |
Aug 24 07:02:30 AM UTC 24 |
20385731765 ps |
| T2571 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/80.xbar_smoke_slow_rsp.3322967086 |
|
|
Aug 24 07:01:30 AM UTC 24 |
Aug 24 07:02:30 AM UTC 24 |
4879626394 ps |
| T2572 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/80.xbar_same_source.1910373259 |
|
|
Aug 24 07:02:20 AM UTC 24 |
Aug 24 07:02:32 AM UTC 24 |
417203292 ps |
| T2573 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/80.xbar_smoke_large_delays.1770032060 |
|
|
Aug 24 07:01:17 AM UTC 24 |
Aug 24 07:02:35 AM UTC 24 |
9494661515 ps |
| T2574 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/75.xbar_access_same_device_slow_rsp.4244078752 |
|
|
Aug 24 06:53:35 AM UTC 24 |
Aug 24 07:02:42 AM UTC 24 |
48361698112 ps |
| T2575 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/80.xbar_error_random.2912879545 |
|
|
Aug 24 07:02:24 AM UTC 24 |
Aug 24 07:02:51 AM UTC 24 |
1213121128 ps |
| T2576 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/80.xbar_unmapped_addr.2465495854 |
|
|
Aug 24 07:02:31 AM UTC 24 |
Aug 24 07:02:53 AM UTC 24 |
676388189 ps |
| T2577 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/79.xbar_random_slow_rsp.2310272107 |
|
|
Aug 24 07:00:01 AM UTC 24 |
Aug 24 07:02:55 AM UTC 24 |
14003337737 ps |
| T2578 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/73.xbar_stress_all_with_reset_error.3004294706 |
|
|
Aug 24 06:50:02 AM UTC 24 |
Aug 24 07:02:59 AM UTC 24 |
29062055791 ps |
| T2579 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/80.xbar_error_and_unmapped_addr.1622851188 |
|
|
Aug 24 07:02:44 AM UTC 24 |
Aug 24 07:03:06 AM UTC 24 |
730165755 ps |
| T853 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/79.xbar_stress_all_with_rand_reset.1605490182 |
|
|
Aug 24 07:01:00 AM UTC 24 |
Aug 24 07:03:07 AM UTC 24 |
326093829 ps |
| T2580 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/81.xbar_smoke_zero_delays.45189061 |
|
|
Aug 24 07:03:06 AM UTC 24 |
Aug 24 07:03:12 AM UTC 24 |
47635064 ps |
| T2581 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/81.xbar_smoke.2162438916 |
|
|
Aug 24 07:03:04 AM UTC 24 |
Aug 24 07:03:13 AM UTC 24 |
246863882 ps |
| T2582 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/80.xbar_access_same_device.2617415799 |
|
|
Aug 24 07:01:52 AM UTC 24 |
Aug 24 07:03:14 AM UTC 24 |
3027041104 ps |
| T2583 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/79.xbar_stress_all_with_error.1363309046 |
|
|
Aug 24 07:01:01 AM UTC 24 |
Aug 24 07:03:25 AM UTC 24 |
6192945101 ps |
| T2584 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/79.xbar_stress_all_with_reset_error.879759411 |
|
|
Aug 24 07:01:04 AM UTC 24 |
Aug 24 07:03:53 AM UTC 24 |
534506739 ps |
| T2585 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/81.xbar_random_zero_delays.744073466 |
|
|
Aug 24 07:03:21 AM UTC 24 |
Aug 24 07:03:55 AM UTC 24 |
569501962 ps |
| T2586 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/81.xbar_smoke_slow_rsp.2656613463 |
|
|
Aug 24 07:03:14 AM UTC 24 |
Aug 24 07:04:06 AM UTC 24 |
4438847367 ps |
| T2587 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/81.xbar_error_random.3322070183 |
|
|
Aug 24 07:04:09 AM UTC 24 |
Aug 24 07:04:22 AM UTC 24 |
397701300 ps |
| T2588 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/81.xbar_same_source.64716442 |
|
|
Aug 24 07:04:07 AM UTC 24 |
Aug 24 07:04:26 AM UTC 24 |
300869486 ps |
| T2589 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/81.xbar_random.2519798415 |
|
|
Aug 24 07:03:21 AM UTC 24 |
Aug 24 07:04:26 AM UTC 24 |
2514365066 ps |
| T2590 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/81.xbar_unmapped_addr.104267810 |
|
|
Aug 24 07:04:20 AM UTC 24 |
Aug 24 07:04:34 AM UTC 24 |
364453740 ps |
| T2591 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/81.xbar_smoke_large_delays.483278597 |
|
|
Aug 24 07:03:09 AM UTC 24 |
Aug 24 07:04:35 AM UTC 24 |
9977184334 ps |
| T2592 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/81.xbar_error_and_unmapped_addr.149910977 |
|
|
Aug 24 07:04:36 AM UTC 24 |
Aug 24 07:04:42 AM UTC 24 |
22911036 ps |
| T2593 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/81.xbar_access_same_device.491871505 |
|
|
Aug 24 07:03:29 AM UTC 24 |
Aug 24 07:04:42 AM UTC 24 |
2544225354 ps |
| T2594 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/75.xbar_random_large_delays.1222402343 |
|
|
Aug 24 06:53:12 AM UTC 24 |
Aug 24 07:04:46 AM UTC 24 |
85962718740 ps |
| T2595 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/82.xbar_smoke.3627013546 |
|
|
Aug 24 07:04:55 AM UTC 24 |
Aug 24 07:05:01 AM UTC 24 |
46947247 ps |
| T2596 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/82.xbar_smoke_zero_delays.2867215961 |
|
|
Aug 24 07:04:57 AM UTC 24 |
Aug 24 07:05:03 AM UTC 24 |
50191361 ps |
| T2597 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/77.xbar_random_large_delays.3753131607 |
|
|
Aug 24 06:56:53 AM UTC 24 |
Aug 24 07:05:04 AM UTC 24 |
59506612983 ps |
| T2598 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/81.xbar_random_large_delays.78782471 |
|
|
Aug 24 07:03:27 AM UTC 24 |
Aug 24 07:05:12 AM UTC 24 |
12947940025 ps |
| T2599 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/80.xbar_random_slow_rsp.3979525492 |
|
|
Aug 24 07:01:50 AM UTC 24 |
Aug 24 07:05:23 AM UTC 24 |
17753683308 ps |
| T2600 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/76.xbar_random_large_delays.2811828720 |
|
|
Aug 24 06:56:00 AM UTC 24 |
Aug 24 07:05:23 AM UTC 24 |
64689855342 ps |
| T2601 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/80.xbar_stress_all.2261849223 |
|
|
Aug 24 07:02:44 AM UTC 24 |
Aug 24 07:05:23 AM UTC 24 |
2789768473 ps |
| T2602 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/81.xbar_stress_all_with_error.3319984934 |
|
|
Aug 24 07:04:48 AM UTC 24 |
Aug 24 07:05:45 AM UTC 24 |
1144979014 ps |
| T2603 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/80.xbar_stress_all_with_reset_error.3173112815 |
|
|
Aug 24 07:02:56 AM UTC 24 |
Aug 24 07:05:50 AM UTC 24 |
2155548876 ps |
| T2604 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/81.xbar_stress_all_with_rand_reset.794952542 |
|
|
Aug 24 07:04:41 AM UTC 24 |
Aug 24 07:05:55 AM UTC 24 |
129758728 ps |
| T2605 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/82.xbar_random_zero_delays.3523616768 |
|
|
Aug 24 07:05:19 AM UTC 24 |
Aug 24 07:05:58 AM UTC 24 |
612484116 ps |
| T2606 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/69.xbar_access_same_device_slow_rsp.1867060068 |
|
|
Aug 24 06:42:24 AM UTC 24 |
Aug 24 07:05:59 AM UTC 24 |
121623752062 ps |
| T2607 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/82.xbar_same_source.2265404005 |
|
|
Aug 24 07:05:47 AM UTC 24 |
Aug 24 07:06:10 AM UTC 24 |
416334137 ps |
| T2608 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/82.xbar_smoke_large_delays.3689529272 |
|
|
Aug 24 07:05:00 AM UTC 24 |
Aug 24 07:06:12 AM UTC 24 |
8791622045 ps |
| T2609 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/82.xbar_error_and_unmapped_addr.3343184544 |
|
|
Aug 24 07:06:09 AM UTC 24 |
Aug 24 07:06:16 AM UTC 24 |
42787373 ps |
| T2610 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/82.xbar_unmapped_addr.3292391779 |
|
|
Aug 24 07:06:04 AM UTC 24 |
Aug 24 07:06:17 AM UTC 24 |
110803559 ps |
| T2611 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/82.xbar_smoke_slow_rsp.525959909 |
|
|
Aug 24 07:05:16 AM UTC 24 |
Aug 24 07:06:19 AM UTC 24 |
5125864035 ps |
| T2612 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/82.xbar_error_random.2796086891 |
|
|
Aug 24 07:05:59 AM UTC 24 |
Aug 24 07:06:20 AM UTC 24 |
289877702 ps |
| T2613 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/77.xbar_stress_all_with_reset_error.3498080635 |
|
|
Aug 24 06:58:00 AM UTC 24 |
Aug 24 07:06:37 AM UTC 24 |
7158793673 ps |
| T2614 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/83.xbar_smoke.2212753173 |
|
|
Aug 24 07:06:30 AM UTC 24 |
Aug 24 07:06:38 AM UTC 24 |
161859056 ps |
| T2615 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/83.xbar_smoke_zero_delays.131901445 |
|
|
Aug 24 07:06:32 AM UTC 24 |
Aug 24 07:06:38 AM UTC 24 |
46385300 ps |
| T2616 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/71.xbar_access_same_device_slow_rsp.2001627283 |
|
|
Aug 24 06:46:07 AM UTC 24 |
Aug 24 07:06:50 AM UTC 24 |
103061654516 ps |
| T2617 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/82.xbar_access_same_device.3523574749 |
|
|
Aug 24 07:05:37 AM UTC 24 |
Aug 24 07:06:52 AM UTC 24 |
2969980589 ps |
| T2618 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/78.xbar_random_large_delays.1885656794 |
|
|
Aug 24 06:58:31 AM UTC 24 |
Aug 24 07:07:01 AM UTC 24 |
63688226397 ps |
| T611 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/80.xbar_stress_all_with_error.2818197064 |
|
|
Aug 24 07:02:49 AM UTC 24 |
Aug 24 07:07:04 AM UTC 24 |
5024553424 ps |
| T2619 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/83.xbar_random_zero_delays.341933126 |
|
|
Aug 24 07:06:52 AM UTC 24 |
Aug 24 07:07:21 AM UTC 24 |
459380344 ps |
| T2620 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/82.xbar_stress_all_with_reset_error.3593998388 |
|
|
Aug 24 07:06:25 AM UTC 24 |
Aug 24 07:07:33 AM UTC 24 |
516364835 ps |
| T2621 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/83.xbar_smoke_large_delays.4213366026 |
|
|
Aug 24 07:06:34 AM UTC 24 |
Aug 24 07:07:42 AM UTC 24 |
8483414554 ps |
| T2622 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/83.xbar_access_same_device.2664516141 |
|
|
Aug 24 07:07:06 AM UTC 24 |
Aug 24 07:07:43 AM UTC 24 |
654767354 ps |
| T2623 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/83.xbar_smoke_slow_rsp.1730441755 |
|
|
Aug 24 07:06:34 AM UTC 24 |
Aug 24 07:07:45 AM UTC 24 |
5741487319 ps |
| T2624 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/77.xbar_random_slow_rsp.1956092195 |
|
|
Aug 24 06:56:56 AM UTC 24 |
Aug 24 07:07:49 AM UTC 24 |
56666645226 ps |
| T2625 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/81.xbar_stress_all.2186904105 |
|
|
Aug 24 07:04:40 AM UTC 24 |
Aug 24 07:07:49 AM UTC 24 |
8314188533 ps |
| T2626 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/83.xbar_random.839784298 |
|
|
Aug 24 07:06:52 AM UTC 24 |
Aug 24 07:07:52 AM UTC 24 |
2363217674 ps |
| T2627 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/83.xbar_same_source.1046257736 |
|
|
Aug 24 07:07:18 AM UTC 24 |
Aug 24 07:08:02 AM UTC 24 |
2035684476 ps |
| T2628 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/83.xbar_unmapped_addr.1612361339 |
|
|
Aug 24 07:07:47 AM UTC 24 |
Aug 24 07:08:03 AM UTC 24 |
166957690 ps |
| T2629 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/83.xbar_error_random.308241457 |
|
|
Aug 24 07:07:35 AM UTC 24 |
Aug 24 07:08:04 AM UTC 24 |
472387921 ps |
| T2630 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/84.xbar_smoke.1357880454 |
|
|
Aug 24 07:08:07 AM UTC 24 |
Aug 24 07:08:14 AM UTC 24 |
174276137 ps |
| T2631 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/83.xbar_error_and_unmapped_addr.2795976409 |
|
|
Aug 24 07:07:56 AM UTC 24 |
Aug 24 07:08:17 AM UTC 24 |
249927964 ps |
| T2632 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/66.xbar_access_same_device_slow_rsp.2883666698 |
|
|
Aug 24 06:38:28 AM UTC 24 |
Aug 24 07:08:17 AM UTC 24 |
149523182576 ps |
| T2633 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/84.xbar_smoke_zero_delays.1613744665 |
|
|
Aug 24 07:08:16 AM UTC 24 |
Aug 24 07:08:22 AM UTC 24 |
48051160 ps |
| T2634 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/80.xbar_random_large_delays.2828610613 |
|
|
Aug 24 07:01:49 AM UTC 24 |
Aug 24 07:08:29 AM UTC 24 |
48565228263 ps |
| T2635 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/82.xbar_stress_all_with_error.4252444807 |
|
|
Aug 24 07:06:24 AM UTC 24 |
Aug 24 07:08:39 AM UTC 24 |
2476639970 ps |
| T2636 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/72.xbar_access_same_device_slow_rsp.4212241010 |
|
|
Aug 24 06:47:52 AM UTC 24 |
Aug 24 07:08:44 AM UTC 24 |
101906715608 ps |
| T2637 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/84.xbar_random_zero_delays.3052202299 |
|
|
Aug 24 07:08:31 AM UTC 24 |
Aug 24 07:08:53 AM UTC 24 |
304610131 ps |
| T2638 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/84.xbar_random.2125788290 |
|
|
Aug 24 07:08:29 AM UTC 24 |
Aug 24 07:09:05 AM UTC 24 |
1371466648 ps |
| T2639 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/83.xbar_stress_all.4072634067 |
|
|
Aug 24 07:07:58 AM UTC 24 |
Aug 24 07:09:16 AM UTC 24 |
1315128360 ps |
| T2640 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/84.xbar_random_large_delays.3687861168 |
|
|
Aug 24 07:08:32 AM UTC 24 |
Aug 24 07:09:16 AM UTC 24 |
5261081362 ps |
| T2641 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/84.xbar_same_source.3060631478 |
|
|
Aug 24 07:08:58 AM UTC 24 |
Aug 24 07:09:28 AM UTC 24 |
1283376103 ps |
| T2642 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/84.xbar_smoke_large_delays.1934132459 |
|
|
Aug 24 07:08:18 AM UTC 24 |
Aug 24 07:09:29 AM UTC 24 |
8567749336 ps |
| T2643 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/84.xbar_access_same_device.2801150160 |
|
|
Aug 24 07:08:43 AM UTC 24 |
Aug 24 07:09:33 AM UTC 24 |
1001704415 ps |
| T2644 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/81.xbar_random_slow_rsp.3449910313 |
|
|
Aug 24 07:03:27 AM UTC 24 |
Aug 24 07:09:34 AM UTC 24 |
30759653877 ps |
| T2645 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/84.xbar_error_random.394765854 |
|
|
Aug 24 07:09:07 AM UTC 24 |
Aug 24 07:09:35 AM UTC 24 |
440634633 ps |
| T2646 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/84.xbar_smoke_slow_rsp.518509842 |
|
|
Aug 24 07:08:18 AM UTC 24 |
Aug 24 07:09:37 AM UTC 24 |
6446872756 ps |
| T2647 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/81.xbar_access_same_device_slow_rsp.3295405373 |
|
|
Aug 24 07:03:40 AM UTC 24 |
Aug 24 07:09:38 AM UTC 24 |
31587974100 ps |
| T2648 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/84.xbar_error_and_unmapped_addr.67358463 |
|
|
Aug 24 07:09:30 AM UTC 24 |
Aug 24 07:09:41 AM UTC 24 |
99451425 ps |
| T2649 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/84.xbar_unmapped_addr.3918627942 |
|
|
Aug 24 07:09:19 AM UTC 24 |
Aug 24 07:09:42 AM UTC 24 |
651831282 ps |
| T2650 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/85.xbar_smoke.3252003501 |
|
|
Aug 24 07:09:49 AM UTC 24 |
Aug 24 07:09:55 AM UTC 24 |
49245881 ps |
| T2651 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/85.xbar_smoke_zero_delays.1753668354 |
|
|
Aug 24 07:09:50 AM UTC 24 |
Aug 24 07:09:55 AM UTC 24 |
44556201 ps |
| T2652 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/84.xbar_stress_all_with_reset_error.985983766 |
|
|
Aug 24 07:09:47 AM UTC 24 |
Aug 24 07:09:58 AM UTC 24 |
90764322 ps |
| T2653 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/85.xbar_random.482030021 |
|
|
Aug 24 07:09:55 AM UTC 24 |
Aug 24 07:10:20 AM UTC 24 |
860276568 ps |
| T2654 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/85.xbar_random_zero_delays.530928169 |
|
|
Aug 24 07:09:57 AM UTC 24 |
Aug 24 07:10:22 AM UTC 24 |
402139431 ps |
| T2655 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/84.xbar_stress_all_with_rand_reset.2590567439 |
|
|
Aug 24 07:09:41 AM UTC 24 |
Aug 24 07:10:22 AM UTC 24 |
121913248 ps |
| T2656 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/85.xbar_error_random.4123550071 |
|
|
Aug 24 07:10:36 AM UTC 24 |
Aug 24 07:10:48 AM UTC 24 |
157661228 ps |
| T2657 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/85.xbar_smoke_slow_rsp.3614202551 |
|
|
Aug 24 07:09:53 AM UTC 24 |
Aug 24 07:10:57 AM UTC 24 |
5160801730 ps |
| T2658 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/82.xbar_stress_all.2387442328 |
|
|
Aug 24 07:06:12 AM UTC 24 |
Aug 24 07:11:01 AM UTC 24 |
11756958684 ps |
| T2659 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/83.xbar_stress_all_with_rand_reset.1477594194 |
|
|
Aug 24 07:08:00 AM UTC 24 |
Aug 24 07:11:07 AM UTC 24 |
2980989475 ps |
| T2660 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/84.xbar_stress_all_with_error.456556324 |
|
|
Aug 24 07:09:42 AM UTC 24 |
Aug 24 07:11:09 AM UTC 24 |
1562099293 ps |
| T2661 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/85.xbar_smoke_large_delays.3999955737 |
|
|
Aug 24 07:09:51 AM UTC 24 |
Aug 24 07:11:18 AM UTC 24 |
10360851977 ps |
| T2662 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/85.xbar_unmapped_addr.3357026337 |
|
|
Aug 24 07:11:02 AM UTC 24 |
Aug 24 07:11:22 AM UTC 24 |
198504168 ps |
| T2663 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/74.xbar_access_same_device_slow_rsp.886430233 |
|
|
Aug 24 06:51:23 AM UTC 24 |
Aug 24 07:11:23 AM UTC 24 |
105253205731 ps |
| T2664 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/85.xbar_stress_all_with_rand_reset.1012446572 |
|
|
Aug 24 07:11:21 AM UTC 24 |
Aug 24 07:11:33 AM UTC 24 |
8915417 ps |
| T2665 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/83.xbar_stress_all_with_error.1942229238 |
|
|
Aug 24 07:08:03 AM UTC 24 |
Aug 24 07:11:34 AM UTC 24 |
9141094474 ps |
| T2666 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/85.xbar_same_source.4080381828 |
|
|
Aug 24 07:10:36 AM UTC 24 |
Aug 24 07:11:35 AM UTC 24 |
2715235913 ps |
| T2667 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/85.xbar_error_and_unmapped_addr.3741918522 |
|
|
Aug 24 07:11:11 AM UTC 24 |
Aug 24 07:11:39 AM UTC 24 |
1018148320 ps |
| T2668 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/86.xbar_smoke_zero_delays.3763537081 |
|
|
Aug 24 07:11:38 AM UTC 24 |
Aug 24 07:11:44 AM UTC 24 |
49415480 ps |
| T2669 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/86.xbar_smoke.4168957673 |
|
|
Aug 24 07:11:36 AM UTC 24 |
Aug 24 07:11:45 AM UTC 24 |
225213139 ps |
| T2670 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/85.xbar_access_same_device.3891024770 |
|
|
Aug 24 07:10:13 AM UTC 24 |
Aug 24 07:11:52 AM UTC 24 |
3401001470 ps |
| T2671 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/85.xbar_stress_all_with_reset_error.3312459192 |
|
|
Aug 24 07:11:33 AM UTC 24 |
Aug 24 07:11:53 AM UTC 24 |
171463925 ps |
| T2672 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/82.xbar_stress_all_with_rand_reset.667816890 |
|
|
Aug 24 07:06:13 AM UTC 24 |
Aug 24 07:12:16 AM UTC 24 |
4879386365 ps |
| T2673 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/86.xbar_random_zero_delays.2183888400 |
|
|
Aug 24 07:11:53 AM UTC 24 |
Aug 24 07:12:21 AM UTC 24 |
381788835 ps |
| T2674 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/84.xbar_random_slow_rsp.4246162127 |
|
|
Aug 24 07:08:36 AM UTC 24 |
Aug 24 07:12:23 AM UTC 24 |
19020832740 ps |
| T2675 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/85.xbar_stress_all.2530353285 |
|
|
Aug 24 07:11:15 AM UTC 24 |
Aug 24 07:12:34 AM UTC 24 |
3423106480 ps |
| T2676 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/86.xbar_random.3734128814 |
|
|
Aug 24 07:11:50 AM UTC 24 |
Aug 24 07:12:40 AM UTC 24 |
1944758973 ps |
| T2677 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/86.xbar_random_large_delays.3040094967 |
|
|
Aug 24 07:11:59 AM UTC 24 |
Aug 24 07:12:43 AM UTC 24 |
5093406190 ps |
| T2678 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/86.xbar_error_random.3939414840 |
|
|
Aug 24 07:12:35 AM UTC 24 |
Aug 24 07:12:46 AM UTC 24 |
138854963 ps |
| T2679 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/86.xbar_smoke_slow_rsp.1460100825 |
|
|
Aug 24 07:11:48 AM UTC 24 |
Aug 24 07:12:53 AM UTC 24 |
5512392134 ps |
| T2680 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/85.xbar_access_same_device_slow_rsp.2605691996 |
|
|
Aug 24 07:10:34 AM UTC 24 |
Aug 24 07:13:09 AM UTC 24 |
12875138674 ps |
| T2681 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/86.xbar_access_same_device.1559960340 |
|
|
Aug 24 07:12:06 AM UTC 24 |
Aug 24 07:13:11 AM UTC 24 |
2238781351 ps |
| T2682 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/83.xbar_stress_all_with_reset_error.2709022810 |
|
|
Aug 24 07:08:04 AM UTC 24 |
Aug 24 07:13:11 AM UTC 24 |
7614775056 ps |
| T2683 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/87.xbar_smoke.1690350669 |
|
|
Aug 24 07:13:07 AM UTC 24 |
Aug 24 07:13:14 AM UTC 24 |
176138867 ps |
| T2684 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/86.xbar_error_and_unmapped_addr.3355089101 |
|
|
Aug 24 07:12:48 AM UTC 24 |
Aug 24 07:13:16 AM UTC 24 |
891601997 ps |
| T2685 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/86.xbar_unmapped_addr.2823539654 |
|
|
Aug 24 07:12:37 AM UTC 24 |
Aug 24 07:13:17 AM UTC 24 |
1220005827 ps |
| T2686 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/86.xbar_same_source.1515099052 |
|
|
Aug 24 07:12:30 AM UTC 24 |
Aug 24 07:13:18 AM UTC 24 |
2237043966 ps |
| T2687 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/87.xbar_smoke_zero_delays.3435892930 |
|
|
Aug 24 07:13:24 AM UTC 24 |
Aug 24 07:13:30 AM UTC 24 |
45555774 ps |
| T2688 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/86.xbar_stress_all.2326872109 |
|
|
Aug 24 07:12:54 AM UTC 24 |
Aug 24 07:13:43 AM UTC 24 |
710155461 ps |
| T2689 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/84.xbar_stress_all.2965335518 |
|
|
Aug 24 07:09:30 AM UTC 24 |
Aug 24 07:13:45 AM UTC 24 |
9932569266 ps |
| T2690 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/87.xbar_random_zero_delays.1029148998 |
|
|
Aug 24 07:13:30 AM UTC 24 |
Aug 24 07:14:00 AM UTC 24 |
454858723 ps |
| T2691 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/79.xbar_random_large_delays.284931023 |
|
|
Aug 24 07:00:01 AM UTC 24 |
Aug 24 07:14:02 AM UTC 24 |
100945877312 ps |
| T2692 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/82.xbar_random_slow_rsp.3696850638 |
|
|
Aug 24 07:05:37 AM UTC 24 |
Aug 24 07:14:05 AM UTC 24 |
44233028689 ps |
| T2693 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/87.xbar_random.1806449410 |
|
|
Aug 24 07:13:28 AM UTC 24 |
Aug 24 07:14:09 AM UTC 24 |
1498443988 ps |
| T2694 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/87.xbar_unmapped_addr.586163330 |
|
|
Aug 24 07:14:15 AM UTC 24 |
Aug 24 07:14:21 AM UTC 24 |
19474245 ps |
| T2695 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/87.xbar_smoke_slow_rsp.1443682669 |
|
|
Aug 24 07:13:26 AM UTC 24 |
Aug 24 07:14:22 AM UTC 24 |
4134170319 ps |
| T2696 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/87.xbar_smoke_large_delays.1993854661 |
|
|
Aug 24 07:13:25 AM UTC 24 |
Aug 24 07:14:34 AM UTC 24 |
7708943065 ps |
| T2697 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/83.xbar_random_slow_rsp.1230416905 |
|
|
Aug 24 07:07:04 AM UTC 24 |
Aug 24 07:14:37 AM UTC 24 |
38690619428 ps |
| T2698 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/85.xbar_stress_all_with_error.1281919227 |
|
|
Aug 24 07:11:22 AM UTC 24 |
Aug 24 07:14:42 AM UTC 24 |
8903755765 ps |
| T2699 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/87.xbar_error_and_unmapped_addr.1840100380 |
|
|
Aug 24 07:14:20 AM UTC 24 |
Aug 24 07:14:44 AM UTC 24 |
304452117 ps |
| T2700 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/87.xbar_error_random.600207592 |
|
|
Aug 24 07:14:14 AM UTC 24 |
Aug 24 07:14:44 AM UTC 24 |
536445853 ps |
| T2701 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/87.xbar_access_same_device.2295732638 |
|
|
Aug 24 07:13:44 AM UTC 24 |
Aug 24 07:14:45 AM UTC 24 |
1315390170 ps |
| T2702 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/87.xbar_same_source.1676984383 |
|
|
Aug 24 07:13:59 AM UTC 24 |
Aug 24 07:14:53 AM UTC 24 |
2622653610 ps |
| T2703 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/88.xbar_smoke.957836844 |
|
|
Aug 24 07:14:51 AM UTC 24 |
Aug 24 07:14:58 AM UTC 24 |
185087734 ps |
| T861 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/81.xbar_stress_all_with_reset_error.2080675386 |
|
|
Aug 24 07:04:48 AM UTC 24 |
Aug 24 07:15:00 AM UTC 24 |
17775561188 ps |
| T2704 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/88.xbar_smoke_zero_delays.3616928169 |
|
|
Aug 24 07:14:56 AM UTC 24 |
Aug 24 07:15:01 AM UTC 24 |
37434385 ps |
| T2705 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/87.xbar_stress_all_with_rand_reset.3595515639 |
|
|
Aug 24 07:14:36 AM UTC 24 |
Aug 24 07:15:07 AM UTC 24 |
117282574 ps |
| T2706 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/88.xbar_random_zero_delays.2532227705 |
|
|
Aug 24 07:15:07 AM UTC 24 |
Aug 24 07:15:17 AM UTC 24 |
104348254 ps |
| T2707 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/88.xbar_random.1204241308 |
|
|
Aug 24 07:14:59 AM UTC 24 |
Aug 24 07:15:20 AM UTC 24 |
306344604 ps |
| T2708 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/85.xbar_random_large_delays.2073404135 |
|
|
Aug 24 07:10:10 AM UTC 24 |
Aug 24 07:15:26 AM UTC 24 |
37222236470 ps |
| T2709 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/80.xbar_stress_all_with_rand_reset.2327756725 |
|
|
Aug 24 07:02:46 AM UTC 24 |
Aug 24 07:15:42 AM UTC 24 |
23709318023 ps |
| T2710 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/88.xbar_same_source.3369884864 |
|
|
Aug 24 07:15:31 AM UTC 24 |
Aug 24 07:15:43 AM UTC 24 |
381964673 ps |
| T2711 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/86.xbar_stress_all_with_error.1465112283 |
|
|
Aug 24 07:12:59 AM UTC 24 |
Aug 24 07:15:47 AM UTC 24 |
6585073606 ps |
| T2712 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/86.xbar_stress_all_with_rand_reset.1145884435 |
|
|
Aug 24 07:12:58 AM UTC 24 |
Aug 24 07:15:54 AM UTC 24 |
814478725 ps |
| T2713 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/88.xbar_error_random.3332672682 |
|
|
Aug 24 07:15:34 AM UTC 24 |
Aug 24 07:16:01 AM UTC 24 |
451103039 ps |
| T2714 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/88.xbar_error_and_unmapped_addr.2464180099 |
|
|
Aug 24 07:15:56 AM UTC 24 |
Aug 24 07:16:01 AM UTC 24 |
23857311 ps |
| T2715 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/88.xbar_access_same_device.3638133953 |
|
|
Aug 24 07:15:15 AM UTC 24 |
Aug 24 07:16:04 AM UTC 24 |
671501727 ps |
| T2716 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/88.xbar_smoke_large_delays.3095954913 |
|
|
Aug 24 07:14:58 AM UTC 24 |
Aug 24 07:16:05 AM UTC 24 |
7821346097 ps |
| T2717 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/88.xbar_smoke_slow_rsp.3124470314 |
|
|
Aug 24 07:14:59 AM UTC 24 |
Aug 24 07:16:09 AM UTC 24 |
5876674986 ps |
| T2718 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/87.xbar_stress_all_with_reset_error.2413780850 |
|
|
Aug 24 07:14:49 AM UTC 24 |
Aug 24 07:16:10 AM UTC 24 |
348081674 ps |
| T2719 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/88.xbar_unmapped_addr.874465730 |
|
|
Aug 24 07:15:40 AM UTC 24 |
Aug 24 07:16:18 AM UTC 24 |
1255157104 ps |
| T2720 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/89.xbar_smoke.1373980479 |
|
|
Aug 24 07:16:15 AM UTC 24 |
Aug 24 07:16:23 AM UTC 24 |
237044099 ps |
| T2721 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/89.xbar_smoke_zero_delays.738713832 |
|
|
Aug 24 07:16:18 AM UTC 24 |
Aug 24 07:16:24 AM UTC 24 |
43689957 ps |
| T2722 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/88.xbar_stress_all_with_rand_reset.352634321 |
|
|
Aug 24 07:16:02 AM UTC 24 |
Aug 24 07:16:31 AM UTC 24 |
38748877 ps |
| T2723 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/89.xbar_random_zero_delays.1894613191 |
|
|
Aug 24 07:16:32 AM UTC 24 |
Aug 24 07:16:53 AM UTC 24 |
300097243 ps |
| T2724 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/89.xbar_random.515206022 |
|
|
Aug 24 07:16:25 AM UTC 24 |
Aug 24 07:16:56 AM UTC 24 |
492772808 ps |
| T2725 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/78.xbar_access_same_device_slow_rsp.2106952774 |
|
|
Aug 24 06:58:55 AM UTC 24 |
Aug 24 07:16:59 AM UTC 24 |
93686796236 ps |
| T2726 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/89.xbar_access_same_device.4203630321 |
|
|
Aug 24 07:16:45 AM UTC 24 |
Aug 24 07:17:13 AM UTC 24 |
499653724 ps |
| T2727 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/89.xbar_smoke_large_delays.3042033171 |
|
|
Aug 24 07:16:19 AM UTC 24 |
Aug 24 07:17:18 AM UTC 24 |
7003344852 ps |
| T2728 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/89.xbar_smoke_slow_rsp.660875834 |
|
|
Aug 24 07:16:24 AM UTC 24 |
Aug 24 07:17:31 AM UTC 24 |
5579905738 ps |
| T2729 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/86.xbar_random_slow_rsp.684152577 |
|
|
Aug 24 07:11:59 AM UTC 24 |
Aug 24 07:17:37 AM UTC 24 |
29232105908 ps |
| T2730 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/89.xbar_error_random.2194537386 |
|
|
Aug 24 07:17:14 AM UTC 24 |
Aug 24 07:17:38 AM UTC 24 |
1009402531 ps |
| T2731 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/89.xbar_same_source.2365121308 |
|
|
Aug 24 07:17:10 AM UTC 24 |
Aug 24 07:17:39 AM UTC 24 |
553974855 ps |
| T2732 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/83.xbar_random_large_delays.844527136 |
|
|
Aug 24 07:06:52 AM UTC 24 |
Aug 24 07:17:48 AM UTC 24 |
81898454921 ps |
| T2733 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/87.xbar_random_slow_rsp.2236681550 |
|
|
Aug 24 07:13:32 AM UTC 24 |
Aug 24 07:17:49 AM UTC 24 |
21946100137 ps |
| T2734 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/89.xbar_unmapped_addr.1075932723 |
|
|
Aug 24 07:17:27 AM UTC 24 |
Aug 24 07:17:53 AM UTC 24 |
829724514 ps |
| T2735 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/89.xbar_error_and_unmapped_addr.2593963086 |
|
|
Aug 24 07:17:32 AM UTC 24 |
Aug 24 07:17:55 AM UTC 24 |
786805606 ps |
| T2736 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/87.xbar_random_large_delays.3499478762 |
|
|
Aug 24 07:13:31 AM UTC 24 |
Aug 24 07:17:55 AM UTC 24 |
32436892530 ps |
| T2737 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/90.xbar_smoke_zero_delays.3823237013 |
|
|
Aug 24 07:18:04 AM UTC 24 |
Aug 24 07:18:10 AM UTC 24 |
43604122 ps |
| T2738 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/90.xbar_smoke.201706787 |
|
|
Aug 24 07:18:03 AM UTC 24 |
Aug 24 07:18:12 AM UTC 24 |
227961786 ps |
| T2739 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/88.xbar_stress_all_with_reset_error.1523453622 |
|
|
Aug 24 07:16:15 AM UTC 24 |
Aug 24 07:18:28 AM UTC 24 |
534208767 ps |
| T2740 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/90.xbar_random.1674076622 |
|
|
Aug 24 07:18:10 AM UTC 24 |
Aug 24 07:18:32 AM UTC 24 |
813515853 ps |
| T2741 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/89.xbar_stress_all_with_reset_error.574643949 |
|
|
Aug 24 07:17:53 AM UTC 24 |
Aug 24 07:18:33 AM UTC 24 |
57166357 ps |
| T2742 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/90.xbar_random_zero_delays.934264796 |
|
|
Aug 24 07:18:24 AM UTC 24 |
Aug 24 07:18:35 AM UTC 24 |
129489491 ps |
| T2743 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/88.xbar_stress_all_with_error.279782974 |
|
|
Aug 24 07:16:09 AM UTC 24 |
Aug 24 07:18:45 AM UTC 24 |
6646330140 ps |
| T2744 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/86.xbar_access_same_device_slow_rsp.3575832611 |
|
|
Aug 24 07:12:07 AM UTC 24 |
Aug 24 07:18:50 AM UTC 24 |
32441131650 ps |
| T2745 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/90.xbar_smoke_slow_rsp.3637734151 |
|
|
Aug 24 07:18:09 AM UTC 24 |
Aug 24 07:18:53 AM UTC 24 |
3472980193 ps |
| T2746 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/82.xbar_random_large_delays.3846047215 |
|
|
Aug 24 07:05:27 AM UTC 24 |
Aug 24 07:18:55 AM UTC 24 |
98564605435 ps |
| T2747 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/87.xbar_stress_all_with_error.2088426916 |
|
|
Aug 24 07:14:37 AM UTC 24 |
Aug 24 07:19:01 AM UTC 24 |
10150889305 ps |
| T2748 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/90.xbar_access_same_device.624391278 |
|
|
Aug 24 07:18:47 AM UTC 24 |
Aug 24 07:19:03 AM UTC 24 |
533354350 ps |
| T2749 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/90.xbar_same_source.3963356062 |
|
|
Aug 24 07:18:51 AM UTC 24 |
Aug 24 07:19:03 AM UTC 24 |
427688279 ps |
| T2750 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/90.xbar_smoke_large_delays.390934924 |
|
|
Aug 24 07:18:08 AM UTC 24 |
Aug 24 07:19:07 AM UTC 24 |
7112510920 ps |
| T2751 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/90.xbar_random_slow_rsp.3154120664 |
|
|
Aug 24 07:18:43 AM UTC 24 |
Aug 24 07:19:13 AM UTC 24 |
2379772968 ps |
| T2752 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/90.xbar_unmapped_addr.3331810206 |
|
|
Aug 24 07:19:05 AM UTC 24 |
Aug 24 07:19:17 AM UTC 24 |
272366575 ps |
| T2753 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/87.xbar_stress_all.2033919802 |
|
|
Aug 24 07:14:22 AM UTC 24 |
Aug 24 07:19:18 AM UTC 24 |
11785193135 ps |
| T2754 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/82.xbar_access_same_device_slow_rsp.1244546521 |
|
|
Aug 24 07:05:38 AM UTC 24 |
Aug 24 07:19:22 AM UTC 24 |
68878452576 ps |
| T2755 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/90.xbar_error_and_unmapped_addr.13893530 |
|
|
Aug 24 07:19:08 AM UTC 24 |
Aug 24 07:19:24 AM UTC 24 |
485453758 ps |
| T2756 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/91.xbar_smoke.2003991544 |
|
|
Aug 24 07:19:22 AM UTC 24 |
Aug 24 07:19:32 AM UTC 24 |
174071091 ps |
| T2757 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/91.xbar_smoke_zero_delays.939947340 |
|
|
Aug 24 07:19:27 AM UTC 24 |
Aug 24 07:19:32 AM UTC 24 |
36648143 ps |
| T2758 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/90.xbar_error_random.4229875995 |
|
|
Aug 24 07:19:00 AM UTC 24 |
Aug 24 07:19:38 AM UTC 24 |
1490175684 ps |
| T2759 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/88.xbar_stress_all.3493744224 |
|
|
Aug 24 07:15:57 AM UTC 24 |
Aug 24 07:19:41 AM UTC 24 |
8465139283 ps |
| T2760 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/76.xbar_access_same_device_slow_rsp.1284536176 |
|
|
Aug 24 06:56:09 AM UTC 24 |
Aug 24 07:19:48 AM UTC 24 |
118879467774 ps |
| T2761 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/91.xbar_access_same_device.2972988242 |
|
|
Aug 24 07:19:52 AM UTC 24 |
Aug 24 07:19:58 AM UTC 24 |
15425378 ps |