| T2024 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/49.xbar_same_source.3144387445 |
|
|
Aug 24 06:09:50 AM UTC 24 |
Aug 24 06:10:19 AM UTC 24 |
1409024678 ps |
| T2025 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/49.xbar_error_random.3510614585 |
|
|
Aug 24 06:09:53 AM UTC 24 |
Aug 24 06:10:26 AM UTC 24 |
1354908199 ps |
| T2026 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/49.xbar_access_same_device.1683092371 |
|
|
Aug 24 06:09:40 AM UTC 24 |
Aug 24 06:10:27 AM UTC 24 |
871452725 ps |
| T2027 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/50.xbar_smoke.169480568 |
|
|
Aug 24 06:10:19 AM UTC 24 |
Aug 24 06:10:27 AM UTC 24 |
216309230 ps |
| T2028 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/47.xbar_stress_all_with_error.761514975 |
|
|
Aug 24 06:06:52 AM UTC 24 |
Aug 24 06:10:35 AM UTC 24 |
9422419900 ps |
| T2029 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/50.xbar_smoke_zero_delays.4110656307 |
|
|
Aug 24 06:10:33 AM UTC 24 |
Aug 24 06:10:39 AM UTC 24 |
46329040 ps |
| T2030 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/48.xbar_stress_all_with_reset_error.3851101904 |
|
|
Aug 24 06:08:45 AM UTC 24 |
Aug 24 06:10:44 AM UTC 24 |
1606877186 ps |
| T2031 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/45.xbar_random_slow_rsp.11600442 |
|
|
Aug 24 06:02:56 AM UTC 24 |
Aug 24 06:10:47 AM UTC 24 |
39503334576 ps |
| T2032 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/49.xbar_stress_all_with_error.3652422347 |
|
|
Aug 24 06:10:12 AM UTC 24 |
Aug 24 06:10:52 AM UTC 24 |
725274542 ps |
| T2033 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/44.xbar_random_slow_rsp.1810409069 |
|
|
Aug 24 06:01:37 AM UTC 24 |
Aug 24 06:11:00 AM UTC 24 |
47327517379 ps |
| T2034 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/50.xbar_random_zero_delays.2997835536 |
|
|
Aug 24 06:10:49 AM UTC 24 |
Aug 24 06:11:20 AM UTC 24 |
506617944 ps |
| T2035 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/50.xbar_random.2055886505 |
|
|
Aug 24 06:10:41 AM UTC 24 |
Aug 24 06:11:40 AM UTC 24 |
2321190048 ps |
| T2036 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/50.xbar_smoke_slow_rsp.2307929354 |
|
|
Aug 24 06:10:41 AM UTC 24 |
Aug 24 06:11:42 AM UTC 24 |
5086249172 ps |
| T2037 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/50.xbar_smoke_large_delays.345852184 |
|
|
Aug 24 06:10:40 AM UTC 24 |
Aug 24 06:12:00 AM UTC 24 |
10183870005 ps |
| T2038 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/50.xbar_same_source.1331567942 |
|
|
Aug 24 06:11:14 AM UTC 24 |
Aug 24 06:12:05 AM UTC 24 |
2367975181 ps |
| T2039 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/46.xbar_random_large_delays.2448816528 |
|
|
Aug 24 06:04:09 AM UTC 24 |
Aug 24 06:12:06 AM UTC 24 |
54453337105 ps |
| T2040 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/33.xbar_access_same_device_slow_rsp.3929466371 |
|
|
Aug 24 05:41:36 AM UTC 24 |
Aug 24 06:12:07 AM UTC 24 |
148740663556 ps |
| T2041 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/50.xbar_unmapped_addr.1616468726 |
|
|
Aug 24 06:11:54 AM UTC 24 |
Aug 24 06:12:11 AM UTC 24 |
162963042 ps |
| T2042 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/50.xbar_error_random.757774980 |
|
|
Aug 24 06:11:33 AM UTC 24 |
Aug 24 06:12:12 AM UTC 24 |
1535759996 ps |
| T2043 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/50.xbar_error_and_unmapped_addr.2006034780 |
|
|
Aug 24 06:11:57 AM UTC 24 |
Aug 24 06:12:20 AM UTC 24 |
278775133 ps |
| T2044 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/50.xbar_access_same_device.1306024055 |
|
|
Aug 24 06:11:01 AM UTC 24 |
Aug 24 06:12:29 AM UTC 24 |
3149531079 ps |
| T2045 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/51.xbar_smoke.2370190173 |
|
|
Aug 24 06:12:25 AM UTC 24 |
Aug 24 06:12:31 AM UTC 24 |
39378207 ps |
| T2046 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/48.xbar_random_slow_rsp.123590588 |
|
|
Aug 24 06:07:44 AM UTC 24 |
Aug 24 06:12:31 AM UTC 24 |
24721654431 ps |
| T2047 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/51.xbar_smoke_zero_delays.997812112 |
|
|
Aug 24 06:12:26 AM UTC 24 |
Aug 24 06:12:32 AM UTC 24 |
57383763 ps |
| T2048 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/51.xbar_random_zero_delays.2342251186 |
|
|
Aug 24 06:12:45 AM UTC 24 |
Aug 24 06:12:51 AM UTC 24 |
34001351 ps |
| T2049 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/51.xbar_random.1036498945 |
|
|
Aug 24 06:12:46 AM UTC 24 |
Aug 24 06:12:56 AM UTC 24 |
247457489 ps |
| T2050 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/49.xbar_stress_all.1259700115 |
|
|
Aug 24 06:10:00 AM UTC 24 |
Aug 24 06:13:14 AM UTC 24 |
7971998557 ps |
| T2051 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/48.xbar_stress_all_with_rand_reset.1702554709 |
|
|
Aug 24 06:08:41 AM UTC 24 |
Aug 24 06:13:23 AM UTC 24 |
993843114 ps |
| T2052 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/49.xbar_random_slow_rsp.2687576157 |
|
|
Aug 24 06:09:18 AM UTC 24 |
Aug 24 06:13:28 AM UTC 24 |
21384128892 ps |
| T2053 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/51.xbar_access_same_device.1342267316 |
|
|
Aug 24 06:13:10 AM UTC 24 |
Aug 24 06:13:44 AM UTC 24 |
588503101 ps |
| T2054 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/51.xbar_smoke_large_delays.2108307850 |
|
|
Aug 24 06:12:34 AM UTC 24 |
Aug 24 06:13:48 AM UTC 24 |
8984427925 ps |
| T2055 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/51.xbar_smoke_slow_rsp.3650685887 |
|
|
Aug 24 06:12:44 AM UTC 24 |
Aug 24 06:13:52 AM UTC 24 |
5466048092 ps |
| T2056 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/51.xbar_same_source.2726266256 |
|
|
Aug 24 06:13:37 AM UTC 24 |
Aug 24 06:14:05 AM UTC 24 |
461644132 ps |
| T2057 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/51.xbar_unmapped_addr.1949715454 |
|
|
Aug 24 06:13:59 AM UTC 24 |
Aug 24 06:14:09 AM UTC 24 |
84935621 ps |
| T2058 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/51.xbar_error_random.136986764 |
|
|
Aug 24 06:13:42 AM UTC 24 |
Aug 24 06:14:12 AM UTC 24 |
1210595444 ps |
| T2059 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/49.xbar_stress_all_with_reset_error.2559194213 |
|
|
Aug 24 06:10:19 AM UTC 24 |
Aug 24 06:14:18 AM UTC 24 |
5200933496 ps |
| T2060 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/51.xbar_error_and_unmapped_addr.1274905760 |
|
|
Aug 24 06:14:02 AM UTC 24 |
Aug 24 06:14:24 AM UTC 24 |
724723280 ps |
| T2061 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/47.xbar_random_slow_rsp.3026689292 |
|
|
Aug 24 06:05:50 AM UTC 24 |
Aug 24 06:14:35 AM UTC 24 |
42078233003 ps |
| T2062 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/52.xbar_smoke.3226572990 |
|
|
Aug 24 06:14:32 AM UTC 24 |
Aug 24 06:14:40 AM UTC 24 |
191420919 ps |
| T2063 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/52.xbar_smoke_zero_delays.2480030512 |
|
|
Aug 24 06:14:38 AM UTC 24 |
Aug 24 06:14:44 AM UTC 24 |
59971008 ps |
| T2064 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/50.xbar_stress_all.883869265 |
|
|
Aug 24 06:12:15 AM UTC 24 |
Aug 24 06:14:52 AM UTC 24 |
2843478040 ps |
| T2065 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/52.xbar_random.2976073672 |
|
|
Aug 24 06:14:58 AM UTC 24 |
Aug 24 06:15:06 AM UTC 24 |
71401956 ps |
| T2066 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/3.chip_csr_aliasing.3631963189 |
|
|
Aug 24 03:59:45 AM UTC 24 |
Aug 24 06:15:07 AM UTC 24 |
66361756242 ps |
| T2067 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/50.xbar_stress_all_with_error.840839418 |
|
|
Aug 24 06:12:21 AM UTC 24 |
Aug 24 06:15:21 AM UTC 24 |
3563996976 ps |
| T2068 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/52.xbar_random_zero_delays.1752114987 |
|
|
Aug 24 06:15:06 AM UTC 24 |
Aug 24 06:15:35 AM UTC 24 |
472947848 ps |
| T2069 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/93.xbar_stress_all.126566072 |
|
|
Aug 24 07:23:28 AM UTC 24 |
Aug 24 07:25:29 AM UTC 24 |
4572161267 ps |
| T2070 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/50.xbar_stress_all_with_reset_error.887538532 |
|
|
Aug 24 06:12:21 AM UTC 24 |
Aug 24 06:15:37 AM UTC 24 |
3291592187 ps |
| T2071 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/52.xbar_smoke_large_delays.1545671192 |
|
|
Aug 24 06:14:49 AM UTC 24 |
Aug 24 06:15:49 AM UTC 24 |
6985147957 ps |
| T2072 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/47.xbar_random_large_delays.3384801559 |
|
|
Aug 24 06:05:46 AM UTC 24 |
Aug 24 06:15:49 AM UTC 24 |
73388648416 ps |
| T2073 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/50.xbar_random_slow_rsp.1433625902 |
|
|
Aug 24 06:10:58 AM UTC 24 |
Aug 24 06:15:50 AM UTC 24 |
24932206101 ps |
| T2074 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/46.xbar_random_slow_rsp.817751453 |
|
|
Aug 24 06:04:13 AM UTC 24 |
Aug 24 06:15:57 AM UTC 24 |
56847227138 ps |
| T2075 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/52.xbar_smoke_slow_rsp.3685182602 |
|
|
Aug 24 06:14:54 AM UTC 24 |
Aug 24 06:15:59 AM UTC 24 |
5269429625 ps |
| T2076 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/52.xbar_same_source.1665744071 |
|
|
Aug 24 06:15:52 AM UTC 24 |
Aug 24 06:16:04 AM UTC 24 |
167987960 ps |
| T2077 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/52.xbar_unmapped_addr.4256636677 |
|
|
Aug 24 06:16:04 AM UTC 24 |
Aug 24 06:16:10 AM UTC 24 |
82194659 ps |
| T2078 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/52.xbar_access_same_device.1130617325 |
|
|
Aug 24 06:15:36 AM UTC 24 |
Aug 24 06:16:11 AM UTC 24 |
1318533412 ps |
| T2079 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/52.xbar_error_random.3529791318 |
|
|
Aug 24 06:16:03 AM UTC 24 |
Aug 24 06:16:14 AM UTC 24 |
144328983 ps |
| T2080 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/51.xbar_stress_all_with_rand_reset.4218730456 |
|
|
Aug 24 06:14:19 AM UTC 24 |
Aug 24 06:16:20 AM UTC 24 |
458754020 ps |
| T2081 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/40.xbar_access_same_device_slow_rsp.3749451329 |
|
|
Aug 24 05:55:40 AM UTC 24 |
Aug 24 06:16:27 AM UTC 24 |
107925148473 ps |
| T2082 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/49.xbar_access_same_device_slow_rsp.1184401854 |
|
|
Aug 24 06:09:48 AM UTC 24 |
Aug 24 06:16:30 AM UTC 24 |
31896618213 ps |
| T2083 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/53.xbar_smoke.2082615896 |
|
|
Aug 24 06:16:25 AM UTC 24 |
Aug 24 06:16:33 AM UTC 24 |
183160742 ps |
| T2084 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/53.xbar_smoke_zero_delays.1343328125 |
|
|
Aug 24 06:16:29 AM UTC 24 |
Aug 24 06:16:36 AM UTC 24 |
43927723 ps |
| T2085 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/52.xbar_error_and_unmapped_addr.1577203525 |
|
|
Aug 24 06:16:04 AM UTC 24 |
Aug 24 06:16:38 AM UTC 24 |
1214439979 ps |
| T2086 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/51.xbar_stress_all.1038221164 |
|
|
Aug 24 06:14:07 AM UTC 24 |
Aug 24 06:16:46 AM UTC 24 |
2632910362 ps |
| T2087 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/53.xbar_random.2895289148 |
|
|
Aug 24 06:16:44 AM UTC 24 |
Aug 24 06:17:08 AM UTC 24 |
350158313 ps |
| T2088 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/53.xbar_random_zero_delays.494397540 |
|
|
Aug 24 06:16:47 AM UTC 24 |
Aug 24 06:17:09 AM UTC 24 |
306164731 ps |
| T2089 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/49.xbar_stress_all_with_rand_reset.172025380 |
|
|
Aug 24 06:10:08 AM UTC 24 |
Aug 24 06:17:10 AM UTC 24 |
4798706941 ps |
| T2090 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/53.xbar_access_same_device.1783617034 |
|
|
Aug 24 06:17:00 AM UTC 24 |
Aug 24 06:17:21 AM UTC 24 |
398305687 ps |
| T2091 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/53.xbar_smoke_large_delays.527248595 |
|
|
Aug 24 06:16:34 AM UTC 24 |
Aug 24 06:17:24 AM UTC 24 |
5726166135 ps |
| T2092 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/52.xbar_stress_all.3854857153 |
|
|
Aug 24 06:16:11 AM UTC 24 |
Aug 24 06:17:29 AM UTC 24 |
1291197865 ps |
| T2093 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/53.xbar_smoke_slow_rsp.3273175534 |
|
|
Aug 24 06:16:41 AM UTC 24 |
Aug 24 06:17:37 AM UTC 24 |
4473979211 ps |
| T2094 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/53.xbar_same_source.3061292586 |
|
|
Aug 24 06:17:23 AM UTC 24 |
Aug 24 06:17:38 AM UTC 24 |
621646125 ps |
| T2095 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/53.xbar_random_large_delays.1898975213 |
|
|
Aug 24 06:16:50 AM UTC 24 |
Aug 24 06:17:49 AM UTC 24 |
6906602200 ps |
| T2096 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/53.xbar_error_random.2621914719 |
|
|
Aug 24 06:17:24 AM UTC 24 |
Aug 24 06:17:57 AM UTC 24 |
567274982 ps |
| T2097 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/53.xbar_unmapped_addr.429319216 |
|
|
Aug 24 06:17:35 AM UTC 24 |
Aug 24 06:18:09 AM UTC 24 |
1070846233 ps |
| T2098 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/53.xbar_error_and_unmapped_addr.2922353789 |
|
|
Aug 24 06:17:38 AM UTC 24 |
Aug 24 06:18:17 AM UTC 24 |
1309798290 ps |
| T2099 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/54.xbar_smoke.1459953641 |
|
|
Aug 24 06:18:11 AM UTC 24 |
Aug 24 06:18:18 AM UTC 24 |
51598317 ps |
| T2100 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/54.xbar_smoke_zero_delays.3802205150 |
|
|
Aug 24 06:18:23 AM UTC 24 |
Aug 24 06:18:29 AM UTC 24 |
47210199 ps |
| T2101 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/53.xbar_stress_all_with_reset_error.1371352195 |
|
|
Aug 24 06:18:03 AM UTC 24 |
Aug 24 06:18:50 AM UTC 24 |
235098101 ps |
| T2102 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/52.xbar_stress_all_with_error.3295834014 |
|
|
Aug 24 06:16:18 AM UTC 24 |
Aug 24 06:18:51 AM UTC 24 |
6325899364 ps |
| T2103 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/54.xbar_random.1635829955 |
|
|
Aug 24 06:18:43 AM UTC 24 |
Aug 24 06:19:08 AM UTC 24 |
829374674 ps |
| T2104 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/53.xbar_stress_all.2250463461 |
|
|
Aug 24 06:17:43 AM UTC 24 |
Aug 24 06:19:14 AM UTC 24 |
1426509274 ps |
| T2105 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/48.xbar_access_same_device_slow_rsp.3725291058 |
|
|
Aug 24 06:07:59 AM UTC 24 |
Aug 24 06:19:19 AM UTC 24 |
59518693276 ps |
| T2106 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/53.xbar_stress_all_with_rand_reset.1892977796 |
|
|
Aug 24 06:17:51 AM UTC 24 |
Aug 24 06:19:21 AM UTC 24 |
235648160 ps |
| T2107 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/54.xbar_random_zero_delays.4174462310 |
|
|
Aug 24 06:19:04 AM UTC 24 |
Aug 24 06:19:24 AM UTC 24 |
283355938 ps |
| T2108 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/54.xbar_smoke_slow_rsp.1399362877 |
|
|
Aug 24 06:18:31 AM UTC 24 |
Aug 24 06:19:40 AM UTC 24 |
5697763478 ps |
| T2109 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/54.xbar_access_same_device.1309816417 |
|
|
Aug 24 06:19:29 AM UTC 24 |
Aug 24 06:19:46 AM UTC 24 |
406009106 ps |
| T2110 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/54.xbar_error_random.510560313 |
|
|
Aug 24 06:19:38 AM UTC 24 |
Aug 24 06:19:49 AM UTC 24 |
139864592 ps |
| T2111 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/54.xbar_smoke_large_delays.3045805462 |
|
|
Aug 24 06:18:31 AM UTC 24 |
Aug 24 06:19:55 AM UTC 24 |
10169373721 ps |
| T2112 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/54.xbar_same_source.1548953048 |
|
|
Aug 24 06:19:35 AM UTC 24 |
Aug 24 06:19:55 AM UTC 24 |
333980813 ps |
| T2113 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/54.xbar_unmapped_addr.3521259464 |
|
|
Aug 24 06:19:54 AM UTC 24 |
Aug 24 06:20:07 AM UTC 24 |
125617069 ps |
| T2114 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/54.xbar_error_and_unmapped_addr.508769766 |
|
|
Aug 24 06:20:00 AM UTC 24 |
Aug 24 06:20:17 AM UTC 24 |
190884627 ps |
| T2115 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/49.xbar_random_large_delays.2964471657 |
|
|
Aug 24 06:09:10 AM UTC 24 |
Aug 24 06:20:19 AM UTC 24 |
80838874420 ps |
| T2116 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/55.xbar_smoke_zero_delays.174306571 |
|
|
Aug 24 06:20:33 AM UTC 24 |
Aug 24 06:20:39 AM UTC 24 |
44461134 ps |
| T2117 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/55.xbar_smoke.1882281710 |
|
|
Aug 24 06:20:31 AM UTC 24 |
Aug 24 06:20:40 AM UTC 24 |
261450303 ps |
| T2118 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/54.xbar_stress_all.1533007779 |
|
|
Aug 24 06:20:03 AM UTC 24 |
Aug 24 06:20:41 AM UTC 24 |
601294342 ps |
| T2119 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/51.xbar_random_slow_rsp.227872199 |
|
|
Aug 24 06:13:05 AM UTC 24 |
Aug 24 06:20:44 AM UTC 24 |
39294814298 ps |
| T2120 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/51.xbar_stress_all_with_error.1006725723 |
|
|
Aug 24 06:14:23 AM UTC 24 |
Aug 24 06:20:51 AM UTC 24 |
15277708769 ps |
| T610 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/52.xbar_stress_all_with_reset_error.3365353055 |
|
|
Aug 24 06:16:24 AM UTC 24 |
Aug 24 06:21:00 AM UTC 24 |
4128614880 ps |
| T2121 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/52.xbar_stress_all_with_rand_reset.3297030107 |
|
|
Aug 24 06:16:14 AM UTC 24 |
Aug 24 06:21:10 AM UTC 24 |
2959697183 ps |
| T2122 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/54.xbar_random_slow_rsp.2256978324 |
|
|
Aug 24 06:19:22 AM UTC 24 |
Aug 24 06:21:12 AM UTC 24 |
9210866367 ps |
| T2123 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/55.xbar_random.3128681284 |
|
|
Aug 24 06:20:54 AM UTC 24 |
Aug 24 06:21:19 AM UTC 24 |
346024508 ps |
| T2124 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/51.xbar_stress_all_with_reset_error.1444799384 |
|
|
Aug 24 06:14:26 AM UTC 24 |
Aug 24 06:21:24 AM UTC 24 |
10950859640 ps |
| T2125 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/55.xbar_random_zero_delays.2325190434 |
|
|
Aug 24 06:20:58 AM UTC 24 |
Aug 24 06:21:30 AM UTC 24 |
474923508 ps |
| T2126 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/55.xbar_access_same_device.1294124033 |
|
|
Aug 24 06:21:24 AM UTC 24 |
Aug 24 06:21:43 AM UTC 24 |
285331783 ps |
| T2127 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/55.xbar_smoke_large_delays.1293171468 |
|
|
Aug 24 06:20:53 AM UTC 24 |
Aug 24 06:21:57 AM UTC 24 |
7793670253 ps |
| T2128 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/55.xbar_smoke_slow_rsp.1130685527 |
|
|
Aug 24 06:20:55 AM UTC 24 |
Aug 24 06:22:00 AM UTC 24 |
5497455882 ps |
| T2129 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/55.xbar_unmapped_addr.3132426627 |
|
|
Aug 24 06:21:44 AM UTC 24 |
Aug 24 06:22:01 AM UTC 24 |
499771274 ps |
| T2130 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/55.xbar_error_random.2806829952 |
|
|
Aug 24 06:21:38 AM UTC 24 |
Aug 24 06:22:02 AM UTC 24 |
945585732 ps |
| T2131 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/55.xbar_same_source.4071639202 |
|
|
Aug 24 06:21:33 AM UTC 24 |
Aug 24 06:22:03 AM UTC 24 |
1443352971 ps |
| T2132 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/54.xbar_stress_all_with_rand_reset.914934595 |
|
|
Aug 24 06:20:09 AM UTC 24 |
Aug 24 06:22:04 AM UTC 24 |
278545692 ps |
| T2133 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/53.xbar_stress_all_with_error.2706218800 |
|
|
Aug 24 06:17:52 AM UTC 24 |
Aug 24 06:22:12 AM UTC 24 |
10593156377 ps |
| T2134 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/38.xbar_access_same_device_slow_rsp.2286560161 |
|
|
Aug 24 05:52:16 AM UTC 24 |
Aug 24 06:22:21 AM UTC 24 |
158789739519 ps |
| T2135 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/55.xbar_error_and_unmapped_addr.3757152558 |
|
|
Aug 24 06:21:57 AM UTC 24 |
Aug 24 06:22:21 AM UTC 24 |
320114010 ps |
| T2136 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/56.xbar_smoke.2471680247 |
|
|
Aug 24 06:22:17 AM UTC 24 |
Aug 24 06:22:23 AM UTC 24 |
41442345 ps |
| T2137 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/56.xbar_smoke_zero_delays.467838277 |
|
|
Aug 24 06:22:18 AM UTC 24 |
Aug 24 06:22:25 AM UTC 24 |
47608041 ps |
| T2138 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/50.xbar_stress_all_with_rand_reset.943623084 |
|
|
Aug 24 06:12:20 AM UTC 24 |
Aug 24 06:22:32 AM UTC 24 |
6768025095 ps |
| T2139 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/52.xbar_random_large_delays.3254499072 |
|
|
Aug 24 06:15:19 AM UTC 24 |
Aug 24 06:22:37 AM UTC 24 |
52920732120 ps |
| T2140 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/47.xbar_access_same_device_slow_rsp.970849743 |
|
|
Aug 24 06:06:10 AM UTC 24 |
Aug 24 06:22:43 AM UTC 24 |
83985534049 ps |
| T2141 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/55.xbar_stress_all_with_reset_error.3367456370 |
|
|
Aug 24 06:22:15 AM UTC 24 |
Aug 24 06:22:45 AM UTC 24 |
110399832 ps |
| T2142 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/54.xbar_stress_all_with_reset_error.674077409 |
|
|
Aug 24 06:20:21 AM UTC 24 |
Aug 24 06:22:49 AM UTC 24 |
642156245 ps |
| T2143 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/56.xbar_random_zero_delays.651762073 |
|
|
Aug 24 06:22:38 AM UTC 24 |
Aug 24 06:22:52 AM UTC 24 |
178923111 ps |
| T2144 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/56.xbar_same_source.2274314859 |
|
|
Aug 24 06:22:59 AM UTC 24 |
Aug 24 06:23:05 AM UTC 24 |
39888085 ps |
| T2145 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/53.xbar_access_same_device_slow_rsp.3270544533 |
|
|
Aug 24 06:17:23 AM UTC 24 |
Aug 24 06:23:07 AM UTC 24 |
30663423526 ps |
| T2146 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/56.xbar_random.2265398895 |
|
|
Aug 24 06:22:35 AM UTC 24 |
Aug 24 06:23:15 AM UTC 24 |
1669352267 ps |
| T2147 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/50.xbar_random_large_delays.448333315 |
|
|
Aug 24 06:10:53 AM UTC 24 |
Aug 24 06:23:21 AM UTC 24 |
89892060673 ps |
| T2148 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/56.xbar_unmapped_addr.1601672398 |
|
|
Aug 24 06:23:06 AM UTC 24 |
Aug 24 06:23:25 AM UTC 24 |
177877226 ps |
| T2149 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/56.xbar_smoke_slow_rsp.3795827659 |
|
|
Aug 24 06:22:35 AM UTC 24 |
Aug 24 06:23:27 AM UTC 24 |
4250179354 ps |
| T2150 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/56.xbar_error_random.3034947577 |
|
|
Aug 24 06:23:03 AM UTC 24 |
Aug 24 06:23:38 AM UTC 24 |
605938466 ps |
| T2151 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/55.xbar_random_slow_rsp.3057286631 |
|
|
Aug 24 06:21:15 AM UTC 24 |
Aug 24 06:23:38 AM UTC 24 |
11801115602 ps |
| T2152 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/43.xbar_access_same_device_slow_rsp.2127374121 |
|
|
Aug 24 06:00:21 AM UTC 24 |
Aug 24 06:23:40 AM UTC 24 |
120071635562 ps |
| T2153 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/56.xbar_smoke_large_delays.2038241517 |
|
|
Aug 24 06:22:26 AM UTC 24 |
Aug 24 06:23:40 AM UTC 24 |
9083025188 ps |
| T2154 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/56.xbar_access_same_device.3298444494 |
|
|
Aug 24 06:22:52 AM UTC 24 |
Aug 24 06:23:43 AM UTC 24 |
1105307797 ps |
| T2155 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/56.xbar_error_and_unmapped_addr.1802692749 |
|
|
Aug 24 06:23:19 AM UTC 24 |
Aug 24 06:23:46 AM UTC 24 |
985455797 ps |
| T2156 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/57.xbar_smoke.1188726936 |
|
|
Aug 24 06:23:41 AM UTC 24 |
Aug 24 06:23:47 AM UTC 24 |
55919053 ps |
| T2157 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/56.xbar_stress_all_with_error.2179326672 |
|
|
Aug 24 06:23:34 AM UTC 24 |
Aug 24 06:23:57 AM UTC 24 |
737862853 ps |
| T2158 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/57.xbar_smoke_zero_delays.3815621456 |
|
|
Aug 24 06:23:53 AM UTC 24 |
Aug 24 06:23:59 AM UTC 24 |
45399938 ps |
| T2159 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/4.chip_csr_aliasing.838123487 |
|
|
Aug 24 04:04:21 AM UTC 24 |
Aug 24 06:24:07 AM UTC 24 |
53328838880 ps |
| T2160 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/57.xbar_random.131087288 |
|
|
Aug 24 06:23:55 AM UTC 24 |
Aug 24 06:24:17 AM UTC 24 |
812880988 ps |
| T2161 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/57.xbar_access_same_device.2196828678 |
|
|
Aug 24 06:24:11 AM UTC 24 |
Aug 24 06:24:23 AM UTC 24 |
288675170 ps |
| T2162 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/56.xbar_random_slow_rsp.669867036 |
|
|
Aug 24 06:22:46 AM UTC 24 |
Aug 24 06:24:27 AM UTC 24 |
8259612586 ps |
| T2163 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/57.xbar_random_zero_delays.2940667409 |
|
|
Aug 24 06:23:58 AM UTC 24 |
Aug 24 06:24:27 AM UTC 24 |
441652748 ps |
| T2164 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/57.xbar_error_random.2652178882 |
|
|
Aug 24 06:24:31 AM UTC 24 |
Aug 24 06:24:38 AM UTC 24 |
98327049 ps |
| T2165 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/55.xbar_stress_all.4140803375 |
|
|
Aug 24 06:22:11 AM UTC 24 |
Aug 24 06:24:39 AM UTC 24 |
5729528633 ps |
| T2166 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/56.xbar_stress_all.347300218 |
|
|
Aug 24 06:23:20 AM UTC 24 |
Aug 24 06:24:45 AM UTC 24 |
2933394732 ps |
| T2167 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/57.xbar_error_and_unmapped_addr.1290422556 |
|
|
Aug 24 06:24:41 AM UTC 24 |
Aug 24 06:24:54 AM UTC 24 |
124842564 ps |
| T2168 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/57.xbar_smoke_slow_rsp.3121912839 |
|
|
Aug 24 06:23:54 AM UTC 24 |
Aug 24 06:25:09 AM UTC 24 |
6270136622 ps |
| T2169 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/57.xbar_smoke_large_delays.2758009753 |
|
|
Aug 24 06:23:53 AM UTC 24 |
Aug 24 06:25:10 AM UTC 24 |
9501338335 ps |
| T2170 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/55.xbar_random_large_delays.3456769919 |
|
|
Aug 24 06:21:05 AM UTC 24 |
Aug 24 06:25:13 AM UTC 24 |
29169196823 ps |
| T2171 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/52.xbar_random_slow_rsp.3222564292 |
|
|
Aug 24 06:15:22 AM UTC 24 |
Aug 24 06:25:16 AM UTC 24 |
50602734653 ps |
| T2172 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/57.xbar_same_source.3306142152 |
|
|
Aug 24 06:24:21 AM UTC 24 |
Aug 24 06:25:16 AM UTC 24 |
2690149924 ps |
| T2173 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/58.xbar_smoke.722475061 |
|
|
Aug 24 06:25:08 AM UTC 24 |
Aug 24 06:25:17 AM UTC 24 |
237082595 ps |
| T852 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/55.xbar_stress_all_with_rand_reset.3150226928 |
|
|
Aug 24 06:22:14 AM UTC 24 |
Aug 24 06:25:19 AM UTC 24 |
2122592825 ps |
| T2174 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/57.xbar_unmapped_addr.2226896817 |
|
|
Aug 24 06:24:37 AM UTC 24 |
Aug 24 06:25:20 AM UTC 24 |
1417602299 ps |
| T2175 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/58.xbar_smoke_zero_delays.2533089104 |
|
|
Aug 24 06:25:23 AM UTC 24 |
Aug 24 06:25:29 AM UTC 24 |
33922480 ps |
| T2176 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/58.xbar_random_zero_delays.1774939834 |
|
|
Aug 24 06:25:30 AM UTC 24 |
Aug 24 06:25:44 AM UTC 24 |
175757824 ps |
| T2177 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/56.xbar_stress_all_with_rand_reset.4103447538 |
|
|
Aug 24 06:23:30 AM UTC 24 |
Aug 24 06:25:45 AM UTC 24 |
415471448 ps |
| T2178 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/54.xbar_stress_all_with_error.1979143856 |
|
|
Aug 24 06:20:09 AM UTC 24 |
Aug 24 06:25:50 AM UTC 24 |
14603835884 ps |
| T2179 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/57.xbar_stress_all_with_error.1299639974 |
|
|
Aug 24 06:24:52 AM UTC 24 |
Aug 24 06:26:04 AM UTC 24 |
3457411096 ps |
| T2180 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/58.xbar_random.1614610490 |
|
|
Aug 24 06:25:30 AM UTC 24 |
Aug 24 06:26:06 AM UTC 24 |
567746307 ps |
| T2181 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/58.xbar_access_same_device.1625765501 |
|
|
Aug 24 06:25:35 AM UTC 24 |
Aug 24 06:26:09 AM UTC 24 |
1148957866 ps |
| T2182 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/58.xbar_smoke_slow_rsp.1337025054 |
|
|
Aug 24 06:25:27 AM UTC 24 |
Aug 24 06:26:10 AM UTC 24 |
3522056794 ps |
| T2183 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/58.xbar_error_random.2140854340 |
|
|
Aug 24 06:25:59 AM UTC 24 |
Aug 24 06:26:11 AM UTC 24 |
380848191 ps |
| T2184 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/58.xbar_same_source.2581065054 |
|
|
Aug 24 06:25:58 AM UTC 24 |
Aug 24 06:26:18 AM UTC 24 |
339465161 ps |
| T2185 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/58.xbar_smoke_large_delays.217163358 |
|
|
Aug 24 06:25:24 AM UTC 24 |
Aug 24 06:26:19 AM UTC 24 |
6781903104 ps |
| T2186 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/42.xbar_access_same_device_slow_rsp.1045805751 |
|
|
Aug 24 05:58:09 AM UTC 24 |
Aug 24 06:26:22 AM UTC 24 |
150237371662 ps |
| T2187 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/57.xbar_stress_all.1864021992 |
|
|
Aug 24 06:24:41 AM UTC 24 |
Aug 24 06:26:30 AM UTC 24 |
4062544220 ps |
| T2188 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/58.xbar_error_and_unmapped_addr.3162387632 |
|
|
Aug 24 06:26:18 AM UTC 24 |
Aug 24 06:26:32 AM UTC 24 |
356721255 ps |
| T2189 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/59.xbar_smoke_zero_delays.2566932107 |
|
|
Aug 24 06:26:34 AM UTC 24 |
Aug 24 06:26:40 AM UTC 24 |
47861514 ps |
| T2190 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/59.xbar_smoke.559967196 |
|
|
Aug 24 06:26:32 AM UTC 24 |
Aug 24 06:26:41 AM UTC 24 |
225399946 ps |
| T2191 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/56.xbar_stress_all_with_reset_error.2644019584 |
|
|
Aug 24 06:23:39 AM UTC 24 |
Aug 24 06:26:43 AM UTC 24 |
7107591803 ps |
| T2192 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/58.xbar_unmapped_addr.192796353 |
|
|
Aug 24 06:26:04 AM UTC 24 |
Aug 24 06:26:44 AM UTC 24 |
1279688439 ps |
| T2193 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/58.xbar_stress_all_with_error.2835812857 |
|
|
Aug 24 06:26:25 AM UTC 24 |
Aug 24 06:27:04 AM UTC 24 |
1745795842 ps |
| T2194 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/59.xbar_random_zero_delays.2619358561 |
|
|
Aug 24 06:26:54 AM UTC 24 |
Aug 24 06:27:05 AM UTC 24 |
123552611 ps |
| T2195 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/57.xbar_stress_all_with_reset_error.2132776397 |
|
|
Aug 24 06:24:59 AM UTC 24 |
Aug 24 06:27:14 AM UTC 24 |
304139323 ps |
| T2196 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/59.xbar_same_source.1148802061 |
|
|
Aug 24 06:27:19 AM UTC 24 |
Aug 24 06:27:31 AM UTC 24 |
439284496 ps |
| T2197 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/58.xbar_stress_all_with_reset_error.2617917758 |
|
|
Aug 24 06:26:24 AM UTC 24 |
Aug 24 06:27:38 AM UTC 24 |
285939193 ps |
| T2198 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/59.xbar_random.1857556242 |
|
|
Aug 24 06:26:46 AM UTC 24 |
Aug 24 06:27:39 AM UTC 24 |
2028739892 ps |
| T2199 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/45.xbar_access_same_device_slow_rsp.620871670 |
|
|
Aug 24 06:03:10 AM UTC 24 |
Aug 24 06:27:40 AM UTC 24 |
129063034799 ps |
| T2200 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/59.xbar_smoke_slow_rsp.741766624 |
|
|
Aug 24 06:26:44 AM UTC 24 |
Aug 24 06:27:43 AM UTC 24 |
4791314871 ps |
| T2201 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/51.xbar_random_large_delays.1967813093 |
|
|
Aug 24 06:12:46 AM UTC 24 |
Aug 24 06:27:45 AM UTC 24 |
105960954598 ps |
| T2202 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/59.xbar_smoke_large_delays.1090136979 |
|
|
Aug 24 06:26:36 AM UTC 24 |
Aug 24 06:27:48 AM UTC 24 |
8793460581 ps |
| T2203 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/55.xbar_stress_all_with_error.715301910 |
|
|
Aug 24 06:22:15 AM UTC 24 |
Aug 24 06:27:50 AM UTC 24 |
13933177848 ps |
| T2204 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/59.xbar_access_same_device.129635326 |
|
|
Aug 24 06:26:58 AM UTC 24 |
Aug 24 06:28:00 AM UTC 24 |
2341797471 ps |
| T2205 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/59.xbar_error_random.1271579513 |
|
|
Aug 24 06:27:28 AM UTC 24 |
Aug 24 06:28:04 AM UTC 24 |
1514000731 ps |
| T2206 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/60.xbar_smoke.957947321 |
|
|
Aug 24 06:28:01 AM UTC 24 |
Aug 24 06:28:08 AM UTC 24 |
54481046 ps |
| T2207 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/59.xbar_error_and_unmapped_addr.3575056730 |
|
|
Aug 24 06:27:51 AM UTC 24 |
Aug 24 06:28:09 AM UTC 24 |
534898955 ps |
| T2208 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/59.xbar_unmapped_addr.3398618363 |
|
|
Aug 24 06:27:45 AM UTC 24 |
Aug 24 06:28:09 AM UTC 24 |
749199801 ps |
| T2209 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/60.xbar_smoke_zero_delays.4027483049 |
|
|
Aug 24 06:28:05 AM UTC 24 |
Aug 24 06:28:11 AM UTC 24 |
50031846 ps |
| T2210 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/57.xbar_stress_all_with_rand_reset.1275636333 |
|
|
Aug 24 06:24:51 AM UTC 24 |
Aug 24 06:28:17 AM UTC 24 |
7563192905 ps |
| T2211 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/54.xbar_random_large_delays.1006289138 |
|
|
Aug 24 06:19:06 AM UTC 24 |
Aug 24 06:28:17 AM UTC 24 |
63462131531 ps |
| T2212 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/51.xbar_access_same_device_slow_rsp.2891238981 |
|
|
Aug 24 06:13:28 AM UTC 24 |
Aug 24 06:28:39 AM UTC 24 |
75258162966 ps |
| T2213 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/60.xbar_random_zero_delays.1094718839 |
|
|
Aug 24 06:28:23 AM UTC 24 |
Aug 24 06:28:42 AM UTC 24 |
248895315 ps |
| T2214 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/52.xbar_access_same_device_slow_rsp.2817994237 |
|
|
Aug 24 06:15:50 AM UTC 24 |
Aug 24 06:28:50 AM UTC 24 |
63056420672 ps |
| T2215 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/60.xbar_access_same_device.1026837795 |
|
|
Aug 24 06:28:32 AM UTC 24 |
Aug 24 06:28:54 AM UTC 24 |
248103210 ps |
| T2216 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/59.xbar_stress_all_with_error.1420845892 |
|
|
Aug 24 06:27:57 AM UTC 24 |
Aug 24 06:28:56 AM UTC 24 |
1043640271 ps |
| T2217 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/53.xbar_random_slow_rsp.1477314756 |
|
|
Aug 24 06:16:51 AM UTC 24 |
Aug 24 06:28:59 AM UTC 24 |
63508391443 ps |
| T2218 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/60.xbar_same_source.4056307976 |
|
|
Aug 24 06:28:53 AM UTC 24 |
Aug 24 06:29:04 AM UTC 24 |
359100901 ps |
| T2219 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/60.xbar_error_random.315770770 |
|
|
Aug 24 06:28:56 AM UTC 24 |
Aug 24 06:29:08 AM UTC 24 |
140094131 ps |
| T2220 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/60.xbar_smoke_slow_rsp.4172339631 |
|
|
Aug 24 06:28:18 AM UTC 24 |
Aug 24 06:29:10 AM UTC 24 |
4261647732 ps |
| T2221 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/60.xbar_smoke_large_delays.3583105899 |
|
|
Aug 24 06:28:14 AM UTC 24 |
Aug 24 06:29:17 AM UTC 24 |
7767298451 ps |
| T2222 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/59.xbar_access_same_device_slow_rsp.2627599342 |
|
|
Aug 24 06:27:18 AM UTC 24 |
Aug 24 06:29:23 AM UTC 24 |
10561716278 ps |
| T2223 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/60.xbar_random.3695979147 |
|
|
Aug 24 06:28:22 AM UTC 24 |
Aug 24 06:29:25 AM UTC 24 |
2516039926 ps |
| T2224 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/60.xbar_error_and_unmapped_addr.1934610205 |
|
|
Aug 24 06:29:08 AM UTC 24 |
Aug 24 06:29:27 AM UTC 24 |
243629969 ps |
| T2225 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/61.xbar_smoke.82357864 |
|
|
Aug 24 06:29:23 AM UTC 24 |
Aug 24 06:29:30 AM UTC 24 |
49552731 ps |
| T2226 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/61.xbar_smoke_zero_delays.2515751898 |
|
|
Aug 24 06:29:32 AM UTC 24 |
Aug 24 06:29:38 AM UTC 24 |
46956405 ps |
| T2227 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/60.xbar_unmapped_addr.818044580 |
|
|
Aug 24 06:29:04 AM UTC 24 |
Aug 24 06:29:39 AM UTC 24 |
1133962204 ps |
| T2228 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/61.xbar_random.3482945532 |
|
|
Aug 24 06:29:42 AM UTC 24 |
Aug 24 06:29:56 AM UTC 24 |
181106179 ps |
| T2229 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/61.xbar_random_zero_delays.2462691961 |
|
|
Aug 24 06:29:43 AM UTC 24 |
Aug 24 06:30:14 AM UTC 24 |
499399820 ps |
| T2230 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/58.xbar_stress_all.570186197 |
|
|
Aug 24 06:26:19 AM UTC 24 |
Aug 24 06:30:17 AM UTC 24 |
10278515719 ps |
| T2231 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/59.xbar_stress_all_with_rand_reset.3707057017 |
|
|
Aug 24 06:27:54 AM UTC 24 |
Aug 24 06:30:27 AM UTC 24 |
2349436743 ps |
| T2232 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/61.xbar_smoke_slow_rsp.2240633021 |
|
|
Aug 24 06:29:38 AM UTC 24 |
Aug 24 06:30:30 AM UTC 24 |
4120335756 ps |
| T2233 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/61.xbar_error_random.1365848 |
|
|
Aug 24 06:30:41 AM UTC 24 |
Aug 24 06:30:51 AM UTC 24 |
259507293 ps |
| T2234 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/61.xbar_smoke_large_delays.1787576769 |
|
|
Aug 24 06:29:36 AM UTC 24 |
Aug 24 06:30:53 AM UTC 24 |
8755119800 ps |
| T2235 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/59.xbar_stress_all.2402512260 |
|
|
Aug 24 06:27:53 AM UTC 24 |
Aug 24 06:30:54 AM UTC 24 |
2976817766 ps |
| T2236 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/60.xbar_stress_all_with_error.1630687779 |
|
|
Aug 24 06:29:19 AM UTC 24 |
Aug 24 06:30:56 AM UTC 24 |
1802533171 ps |
| T2237 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/59.xbar_stress_all_with_reset_error.819625283 |
|
|
Aug 24 06:27:58 AM UTC 24 |
Aug 24 06:30:57 AM UTC 24 |
661731239 ps |
| T2238 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/55.xbar_access_same_device_slow_rsp.429220263 |
|
|
Aug 24 06:21:27 AM UTC 24 |
Aug 24 06:30:58 AM UTC 24 |
50261730356 ps |
| T2239 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/61.xbar_same_source.3008529715 |
|
|
Aug 24 06:30:31 AM UTC 24 |
Aug 24 06:31:09 AM UTC 24 |
1730538482 ps |
| T2240 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/61.xbar_unmapped_addr.3491579031 |
|
|
Aug 24 06:30:44 AM UTC 24 |
Aug 24 06:31:10 AM UTC 24 |
818024401 ps |
| T2241 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/61.xbar_error_and_unmapped_addr.2031147796 |
|
|
Aug 24 06:31:05 AM UTC 24 |
Aug 24 06:31:15 AM UTC 24 |
84553144 ps |
| T2242 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/62.xbar_smoke.2477344930 |
|
|
Aug 24 06:31:13 AM UTC 24 |
Aug 24 06:31:19 AM UTC 24 |
56272365 ps |
| T2243 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/62.xbar_smoke_zero_delays.2978038246 |
|
|
Aug 24 06:31:23 AM UTC 24 |
Aug 24 06:31:29 AM UTC 24 |
47496029 ps |
| T2244 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/61.xbar_access_same_device.3550147096 |
|
|
Aug 24 06:30:10 AM UTC 24 |
Aug 24 06:31:36 AM UTC 24 |
3170621259 ps |
| T2245 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/61.xbar_random_large_delays.3350735945 |
|
|
Aug 24 06:29:52 AM UTC 24 |
Aug 24 06:31:45 AM UTC 24 |
13886065660 ps |
| T2246 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/62.xbar_random_zero_delays.2657609209 |
|
|
Aug 24 06:31:43 AM UTC 24 |
Aug 24 06:31:50 AM UTC 24 |
57556376 ps |
| T2247 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/57.xbar_random_slow_rsp.120231673 |
|
|
Aug 24 06:24:01 AM UTC 24 |
Aug 24 06:31:58 AM UTC 24 |
40272327694 ps |
| T2248 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/50.xbar_access_same_device_slow_rsp.175573268 |
|
|
Aug 24 06:11:06 AM UTC 24 |
Aug 24 06:32:02 AM UTC 24 |
101450446966 ps |
| T2249 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/61.xbar_stress_all_with_rand_reset.1013001273 |
|
|
Aug 24 06:31:08 AM UTC 24 |
Aug 24 06:32:04 AM UTC 24 |
315896920 ps |
| T2250 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/62.xbar_random.1068789652 |
|
|
Aug 24 06:31:34 AM UTC 24 |
Aug 24 06:32:04 AM UTC 24 |
453148549 ps |
| T2251 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/60.xbar_stress_all_with_rand_reset.2488880751 |
|
|
Aug 24 06:29:14 AM UTC 24 |
Aug 24 06:32:12 AM UTC 24 |
414270940 ps |
| T2252 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/56.xbar_random_large_delays.3172225581 |
|
|
Aug 24 06:22:39 AM UTC 24 |
Aug 24 06:32:12 AM UTC 24 |
70311554749 ps |
| T2253 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/62.xbar_smoke_large_delays.1634367418 |
|
|
Aug 24 06:31:25 AM UTC 24 |
Aug 24 06:32:27 AM UTC 24 |
7302907774 ps |
| T2254 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/62.xbar_same_source.2032811764 |
|
|
Aug 24 06:32:16 AM UTC 24 |
Aug 24 06:32:30 AM UTC 24 |
490726824 ps |
| T2255 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/62.xbar_stress_all.1527412711 |
|
|
Aug 24 06:32:27 AM UTC 24 |
Aug 24 06:32:34 AM UTC 24 |
79687187 ps |
| T2256 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/62.xbar_access_same_device.2841181500 |
|
|
Aug 24 06:32:05 AM UTC 24 |
Aug 24 06:32:37 AM UTC 24 |
977818174 ps |
| T2257 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/62.xbar_error_random.3237824492 |
|
|
Aug 24 06:32:18 AM UTC 24 |
Aug 24 06:32:45 AM UTC 24 |
1000835684 ps |
| T2258 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/62.xbar_smoke_slow_rsp.1244980706 |
|
|
Aug 24 06:31:29 AM UTC 24 |
Aug 24 06:32:45 AM UTC 24 |
6472967192 ps |
| T2259 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/62.xbar_unmapped_addr.670336928 |
|
|
Aug 24 06:32:18 AM UTC 24 |
Aug 24 06:32:52 AM UTC 24 |
1043261492 ps |
| T2260 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/62.xbar_error_and_unmapped_addr.1967945732 |
|
|
Aug 24 06:32:26 AM UTC 24 |
Aug 24 06:32:52 AM UTC 24 |
332872758 ps |
| T2261 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/63.xbar_smoke.2838949424 |
|
|
Aug 24 06:32:52 AM UTC 24 |
Aug 24 06:32:58 AM UTC 24 |
57811013 ps |
| T2262 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/63.xbar_smoke_zero_delays.4236967364 |
|
|
Aug 24 06:32:59 AM UTC 24 |
Aug 24 06:33:05 AM UTC 24 |
55928432 ps |
| T2263 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/58.xbar_stress_all_with_rand_reset.3300046927 |
|
|
Aug 24 06:26:22 AM UTC 24 |
Aug 24 06:33:09 AM UTC 24 |
10081035028 ps |
| T2264 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/63.xbar_random.2772733957 |
|
|
Aug 24 06:33:07 AM UTC 24 |
Aug 24 06:33:19 AM UTC 24 |
317474144 ps |
| T2265 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/60.xbar_stress_all_with_reset_error.2067272980 |
|
|
Aug 24 06:29:21 AM UTC 24 |
Aug 24 06:33:41 AM UTC 24 |
2043043892 ps |
| T2266 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/62.xbar_stress_all_with_error.2811449602 |
|
|
Aug 24 06:32:45 AM UTC 24 |
Aug 24 06:33:46 AM UTC 24 |
2008960991 ps |
| T2267 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/63.xbar_random_zero_delays.1940719651 |
|
|
Aug 24 06:33:12 AM UTC 24 |
Aug 24 06:33:49 AM UTC 24 |
592813760 ps |
| T2268 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/60.xbar_stress_all.1317800960 |
|
|
Aug 24 06:29:10 AM UTC 24 |
Aug 24 06:34:01 AM UTC 24 |
10547578083 ps |
| T2269 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/63.xbar_smoke_large_delays.338956255 |
|
|
Aug 24 06:33:00 AM UTC 24 |
Aug 24 06:34:04 AM UTC 24 |
8189662364 ps |
| T2270 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/63.xbar_access_same_device.1724400164 |
|
|
Aug 24 06:33:33 AM UTC 24 |
Aug 24 06:34:06 AM UTC 24 |
1080449899 ps |
| T2271 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/61.xbar_stress_all.4100823980 |
|
|
Aug 24 06:31:07 AM UTC 24 |
Aug 24 06:34:07 AM UTC 24 |
3305545178 ps |