| T1055 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_otp_ctrl_smoketest.1773814245 |
|
|
Aug 24 12:42:40 PM UTC 24 |
Aug 24 12:46:03 PM UTC 24 |
2818243124 ps |
| T1056 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_kmac_smoketest.3808913577 |
|
|
Aug 24 12:42:37 PM UTC 24 |
Aug 24 12:46:23 PM UTC 24 |
3481977784 ps |
| T1057 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_entropy_src_smoketest.578741299 |
|
|
Aug 24 12:41:32 PM UTC 24 |
Aug 24 12:46:26 PM UTC 24 |
3447710792 ps |
| T1058 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_hmac_smoketest.1381780796 |
|
|
Aug 24 12:42:36 PM UTC 24 |
Aug 24 12:47:06 PM UTC 24 |
2940195200 ps |
| T328 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_flash_init_reduced_freq.1519242100 |
|
|
Aug 24 12:26:39 PM UTC 24 |
Aug 24 12:47:38 PM UTC 24 |
23683068055 ps |
| T1059 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_rstmgr_smoketest.2881875962 |
|
|
Aug 24 12:46:27 PM UTC 24 |
Aug 24 12:48:31 PM UTC 24 |
2580724744 ps |
| T1060 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_keymgr_key_derivation_jitter_en_reduced_freq.3886339551 |
|
|
Aug 24 12:26:20 PM UTC 24 |
Aug 24 12:48:47 PM UTC 24 |
12317457891 ps |
| T1061 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_rv_timer_smoketest.378286150 |
|
|
Aug 24 12:46:02 PM UTC 24 |
Aug 24 12:48:49 PM UTC 24 |
2815473840 ps |
| T1062 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_rv_plic_smoketest.3470337326 |
|
|
Aug 24 12:45:45 PM UTC 24 |
Aug 24 12:49:13 PM UTC 24 |
2704294272 ps |
| T134 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_uart_tx_rx_alt_clk_freq.274121299 |
|
|
Aug 24 01:00:03 PM UTC 24 |
Aug 24 01:20:40 PM UTC 24 |
9137088427 ps |
| T1063 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_example_rom.3452004822 |
|
|
Aug 24 12:47:57 PM UTC 24 |
Aug 24 12:49:42 PM UTC 24 |
2387485512 ps |
| T1064 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_example_flash.707771903 |
|
|
Aug 24 12:47:29 PM UTC 24 |
Aug 24 12:49:43 PM UTC 24 |
2600432296 ps |
| T1065 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_sram_ctrl_smoketest.68110837 |
|
|
Aug 24 12:46:54 PM UTC 24 |
Aug 24 12:49:56 PM UTC 24 |
3131496862 ps |
| T1066 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_pwrmgr_smoketest.3472668782 |
|
|
Aug 24 12:44:03 PM UTC 24 |
Aug 24 12:50:22 PM UTC 24 |
5723201132 ps |
| T1067 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_uart_smoketest.4156981730 |
|
|
Aug 24 12:46:55 PM UTC 24 |
Aug 24 12:50:27 PM UTC 24 |
2714207000 ps |
| T1068 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_example_manufacturer.3749172108 |
|
|
Aug 24 12:48:54 PM UTC 24 |
Aug 24 12:51:13 PM UTC 24 |
3157576720 ps |
| T1069 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_pwrmgr_usbdev_smoketest.2586455142 |
|
|
Aug 24 12:45:45 PM UTC 24 |
Aug 24 12:51:37 PM UTC 24 |
6213112940 ps |
| T1070 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_example_concurrency.3289886884 |
|
|
Aug 24 12:49:19 PM UTC 24 |
Aug 24 12:51:44 PM UTC 24 |
2821984660 ps |
| T1071 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sival_flash_info_access.360513927 |
|
|
Aug 24 12:49:19 PM UTC 24 |
Aug 24 12:52:38 PM UTC 24 |
2918829132 ps |
| T23 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_sleep_pin_mio_dio_val.1793002838 |
|
|
Aug 24 12:50:24 PM UTC 24 |
Aug 24 12:54:06 PM UTC 24 |
2779280838 ps |
| T72 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_sleep_pin_retention.531387889 |
|
|
Aug 24 12:50:55 PM UTC 24 |
Aug 24 12:54:41 PM UTC 24 |
3902168648 ps |
| T30 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_sleep_pin_wake.2595752544 |
|
|
Aug 24 12:50:54 PM UTC 24 |
Aug 24 12:54:46 PM UTC 24 |
5124031224 ps |
| T1072 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_pattgen_ios.2367560991 |
|
|
Aug 24 12:52:09 PM UTC 24 |
Aug 24 12:55:26 PM UTC 24 |
3088765880 ps |
| T661 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_all_escalation_resets.1238525354 |
|
|
Aug 24 12:49:39 PM UTC 24 |
Aug 24 12:55:58 PM UTC 24 |
4533928792 ps |
| T1073 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_rstmgr_rst_cnsty_escalation.925401104 |
|
|
Aug 24 12:50:23 PM UTC 24 |
Aug 24 12:58:37 PM UTC 24 |
5600777212 ps |
| T1074 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_uart_tx_rx.579530719 |
|
|
Aug 24 12:52:11 PM UTC 24 |
Aug 24 12:59:30 PM UTC 24 |
4221346920 ps |
| T380 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_data_integrity_escalation.1124500503 |
|
|
Aug 24 12:50:22 PM UTC 24 |
Aug 24 12:59:34 PM UTC 24 |
6410269854 ps |
| T133 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_uart_tx_rx_idx1.1752989171 |
|
|
Aug 24 12:53:03 PM UTC 24 |
Aug 24 01:00:35 PM UTC 24 |
3966644792 ps |
| T1075 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_uart_tx_rx_idx2.1571541469 |
|
|
Aug 24 12:54:31 PM UTC 24 |
Aug 24 01:01:59 PM UTC 24 |
4846803282 ps |
| T1076 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_uart_tx_rx_idx3.83821527 |
|
|
Aug 24 12:55:14 PM UTC 24 |
Aug 24 01:02:46 PM UTC 24 |
4636997358 ps |
| T1077 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_otbn_smoketest.883349302 |
|
|
Aug 24 12:42:38 PM UTC 24 |
Aug 24 01:02:58 PM UTC 24 |
8034387548 ps |
| T1078 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_uart_rand_baudrate.743823965 |
|
|
Aug 24 12:59:02 PM UTC 24 |
Aug 24 01:04:54 PM UTC 24 |
4199261620 ps |
| T1079 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_sleep_pwm_pulses.2940842626 |
|
|
Aug 24 12:51:38 PM UTC 24 |
Aug 24 01:06:23 PM UTC 24 |
9227347056 ps |
| T143 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_ast_clk_rst_inputs.171623675 |
|
|
Aug 24 12:27:53 PM UTC 24 |
Aug 24 01:07:46 PM UTC 24 |
20830585044 ps |
| T56 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_spi_device_tpm.2480927124 |
|
|
Aug 24 01:05:18 PM UTC 24 |
Aug 24 01:09:05 PM UTC 24 |
3551181883 ps |
| T374 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_i2c_host_tx_rx.3801714816 |
|
|
Aug 24 01:00:59 PM UTC 24 |
Aug 24 01:09:34 PM UTC 24 |
5127307920 ps |
| T1080 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/1.rom_e2e_asm_init_test_unlocked0.2426962134 |
|
|
Aug 24 12:30:54 PM UTC 24 |
Aug 24 01:10:07 PM UTC 24 |
11576062799 ps |
| T52 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_spi_host_tx_rx.3813467319 |
|
|
Aug 24 01:06:48 PM UTC 24 |
Aug 24 01:10:16 PM UTC 24 |
3230464200 ps |
| T366 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_i2c_device_tx_rx.592675640 |
|
|
Aug 24 01:03:23 PM UTC 24 |
Aug 24 01:11:03 PM UTC 24 |
4317521250 ps |
| T1081 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_i2c_host_tx_rx_idx1.1208517064 |
|
|
Aug 24 01:02:23 PM UTC 24 |
Aug 24 01:11:51 PM UTC 24 |
5229324906 ps |
| T67 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_spi_device_pinmux_sleep_retention.1488698194 |
|
|
Aug 24 01:08:10 PM UTC 24 |
Aug 24 01:12:09 PM UTC 24 |
3735631821 ps |
| T1082 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_uart_tx_rx_alt_clk_freq_low_speed.2433426620 |
|
|
Aug 24 01:00:03 PM UTC 24 |
Aug 24 01:12:18 PM UTC 24 |
7763690789 ps |
| T1083 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_i2c_host_tx_rx_idx2.794140094 |
|
|
Aug 24 01:03:10 PM UTC 24 |
Aug 24 01:12:37 PM UTC 24 |
5344834534 ps |
| T1084 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/1.rom_e2e_shutdown_output.3907444878 |
|
|
Aug 24 12:30:51 PM UTC 24 |
Aug 24 01:15:51 PM UTC 24 |
25322441933 ps |
| T240 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_spi_device_pass_through_collision.4095534847 |
|
|
Aug 24 01:09:58 PM UTC 24 |
Aug 24 01:16:27 PM UTC 24 |
4643428665 ps |
| T47 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_gpio.916658455 |
|
|
Aug 24 01:10:39 PM UTC 24 |
Aug 24 01:16:40 PM UTC 24 |
4587088536 ps |
| T1085 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_flash_ctrl_idle_low_power.1599063781 |
|
|
Aug 24 01:13:02 PM UTC 24 |
Aug 24 01:17:14 PM UTC 24 |
2911202596 ps |
| T241 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_spi_device_pass_through.2839833608 |
|
|
Aug 24 01:09:29 PM UTC 24 |
Aug 24 01:17:51 PM UTC 24 |
6200687107 ps |
| T1086 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_flash_ctrl_lc_rw_en.1262263627 |
|
|
Aug 24 01:12:15 PM UTC 24 |
Aug 24 01:18:10 PM UTC 24 |
5336865715 ps |
| T386 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_flash_ctrl_ops.2548183988 |
|
|
Aug 24 01:10:41 PM UTC 24 |
Aug 24 01:18:27 PM UTC 24 |
4457478244 ps |
| T1087 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_flash_ctrl_ops_jitter_en.364614860 |
|
|
Aug 24 01:11:27 PM UTC 24 |
Aug 24 01:18:57 PM UTC 24 |
3866761095 ps |
| T1088 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/1.rom_e2e_shutdown_exception_c.2342091815 |
|
|
Aug 24 12:30:36 PM UTC 24 |
Aug 24 01:20:45 PM UTC 24 |
14391187124 ps |
| T1089 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/1.rom_e2e_smoke.587669565 |
|
|
Aug 24 12:29:39 PM UTC 24 |
Aug 24 01:20:48 PM UTC 24 |
15121951480 ps |
| T1090 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_kmac_entropy.902534697 |
|
|
Aug 24 01:17:39 PM UTC 24 |
Aug 24 01:21:10 PM UTC 24 |
3282796288 ps |
| T1091 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/1.rom_e2e_keymgr_init_rom_ext_meas.146477394 |
|
|
Aug 24 12:33:39 PM UTC 24 |
Aug 24 01:21:46 PM UTC 24 |
15071135000 ps |
| T1092 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_lc_ctrl_otp_hw_cfg0.371565821 |
|
|
Aug 24 01:18:14 PM UTC 24 |
Aug 24 01:21:51 PM UTC 24 |
3083655632 ps |
| T1093 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq.793301939 |
|
|
Aug 24 12:25:45 PM UTC 24 |
Aug 24 01:22:04 PM UTC 24 |
24701741560 ps |
| T1094 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/1.rom_e2e_asm_init_dev.62748448 |
|
|
Aug 24 12:31:06 PM UTC 24 |
Aug 24 01:22:16 PM UTC 24 |
15933132391 ps |
| T1095 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/1.rom_e2e_asm_init_rma.1812973681 |
|
|
Aug 24 12:32:08 PM UTC 24 |
Aug 24 01:22:49 PM UTC 24 |
14987232010 ps |
| T1096 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_rv_timer_systick_test.1648072015 |
|
|
Aug 24 11:27:30 AM UTC 24 |
Aug 24 01:23:01 PM UTC 24 |
39075442432 ps |
| T201 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_otp_ctrl_vendor_test_csr_access.2954391279 |
|
|
Aug 24 01:21:21 PM UTC 24 |
Aug 24 01:23:31 PM UTC 24 |
3013408825 ps |
| T1097 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_flash_ctrl_access.924865245 |
|
|
Aug 24 01:12:33 PM UTC 24 |
Aug 24 01:24:16 PM UTC 24 |
5936662670 ps |
| T1098 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/1.rom_e2e_keymgr_init_rom_ext_no_meas.2477713390 |
|
|
Aug 24 12:33:39 PM UTC 24 |
Aug 24 01:24:18 PM UTC 24 |
14894848856 ps |
| T1099 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_otp_ctrl_ecc_error_vendor_test.2474788619 |
|
|
Aug 24 01:21:20 PM UTC 24 |
Aug 24 01:24:19 PM UTC 24 |
2882311492 ps |
| T1100 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/1.rom_e2e_asm_init_prod_end.29243301 |
|
|
Aug 24 12:31:21 PM UTC 24 |
Aug 24 01:24:26 PM UTC 24 |
15334724097 ps |
| T1101 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_lc_ctrl_rand_to_scrap.3027571050 |
|
|
Aug 24 01:22:18 PM UTC 24 |
Aug 24 01:24:29 PM UTC 24 |
3613846509 ps |
| T1102 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_lc_ctrl_volatile_raw_unlock.1049589982 |
|
|
Aug 24 01:23:13 PM UTC 24 |
Aug 24 01:24:36 PM UTC 24 |
2280547126 ps |
| T1103 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz.4130493127 |
|
|
Aug 24 01:23:25 PM UTC 24 |
Aug 24 01:24:53 PM UTC 24 |
2365351399 ps |
| T1104 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/1.rom_e2e_asm_init_prod.609385514 |
|
|
Aug 24 12:31:14 PM UTC 24 |
Aug 24 01:24:56 PM UTC 24 |
15639282184 ps |
| T1105 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_flash_ctrl_access_jitter_en.3783189662 |
|
|
Aug 24 01:12:43 PM UTC 24 |
Aug 24 01:25:05 PM UTC 24 |
6828880187 ps |
| T1106 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/1.rom_e2e_keymgr_init_rom_ext_invalid_meas.2055630805 |
|
|
Aug 24 12:35:24 PM UTC 24 |
Aug 24 01:26:00 PM UTC 24 |
15503026310 ps |
| T1107 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_otp_ctrl_lc_signals_test_unlocked0.4098783503 |
|
|
Aug 24 01:18:34 PM UTC 24 |
Aug 24 01:27:12 PM UTC 24 |
5055329886 ps |
| T1108 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_rstmgr_sw_rst.2745439475 |
|
|
Aug 24 01:25:29 PM UTC 24 |
Aug 24 01:27:43 PM UTC 24 |
2969922768 ps |
| T1109 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_flash_ctrl_clock_freqs.1168891505 |
|
|
Aug 24 01:17:04 PM UTC 24 |
Aug 24 01:29:02 PM UTC 24 |
6006929648 ps |
| T1110 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/1.rom_e2e_static_critical.1558305889 |
|
|
Aug 24 12:32:10 PM UTC 24 |
Aug 24 01:29:05 PM UTC 24 |
17858663112 ps |
| T1111 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_pwrmgr_main_power_glitch_reset.1103380974 |
|
|
Aug 24 01:25:44 PM UTC 24 |
Aug 24 01:29:48 PM UTC 24 |
4535317140 ps |
| T1112 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_rstmgr_sw_req.1476737013 |
|
|
Aug 24 01:25:42 PM UTC 24 |
Aug 24 01:30:22 PM UTC 24 |
3420105400 ps |
| T1113 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_lc_ctrl_transition.573273058 |
|
|
Aug 24 01:21:35 PM UTC 24 |
Aug 24 01:31:43 PM UTC 24 |
11706818861 ps |
| T1114 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_pwrmgr_full_aon_reset.2517586580 |
|
|
Aug 24 01:25:44 PM UTC 24 |
Aug 24 01:31:52 PM UTC 24 |
5952733800 ps |
| T1115 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_otp_ctrl_lc_signals_dev.781440203 |
|
|
Aug 24 01:18:52 PM UTC 24 |
Aug 24 01:32:31 PM UTC 24 |
8160492272 ps |
| T255 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_rstmgr_cpu_info.660530314 |
|
|
Aug 24 01:25:45 PM UTC 24 |
Aug 24 01:32:51 PM UTC 24 |
6991755700 ps |
| T1116 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_lc_walkthrough_prodend.160342984 |
|
|
Aug 24 01:22:41 PM UTC 24 |
Aug 24 01:33:14 PM UTC 24 |
9983452950 ps |
| T1117 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_otp_ctrl_lc_signals_rma.1715661087 |
|
|
Aug 24 01:21:19 PM UTC 24 |
Aug 24 01:33:41 PM UTC 24 |
7442842396 ps |
| T1118 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_otp_ctrl_lc_signals_prod.1495542016 |
|
|
Aug 24 01:19:20 PM UTC 24 |
Aug 24 01:34:54 PM UTC 24 |
8536828484 ps |
| T647 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_pwrmgr_sleep_disabled.1480827536 |
|
|
Aug 24 01:32:17 PM UTC 24 |
Aug 24 01:34:54 PM UTC 24 |
2649351664 ps |
| T1119 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_pwrmgr_deep_sleep_por_reset.563120650 |
|
|
Aug 24 01:29:32 PM UTC 24 |
Aug 24 01:34:55 PM UTC 24 |
9783510202 ps |
| T1120 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_pwrmgr_sysrst_ctrl_reset.1120305967 |
|
|
Aug 24 01:25:43 PM UTC 24 |
Aug 24 01:35:06 PM UTC 24 |
7675357840 ps |
| T1121 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_rv_timer_irq.1460662188 |
|
|
Aug 24 01:33:15 PM UTC 24 |
Aug 24 01:35:50 PM UTC 24 |
2701132040 ps |
| T1122 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_pwrmgr_deep_sleep_power_glitch_reset.23195036 |
|
|
Aug 24 01:30:46 PM UTC 24 |
Aug 24 01:35:56 PM UTC 24 |
6731036300 ps |
| T329 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_flash_init.2316195656 |
|
|
Aug 24 01:16:10 PM UTC 24 |
Aug 24 01:37:05 PM UTC 24 |
21190009512 ps |
| T1123 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_pwrmgr_normal_sleep_por_reset.4075472916 |
|
|
Aug 24 01:29:33 PM UTC 24 |
Aug 24 01:37:31 PM UTC 24 |
7440285235 ps |
| T1124 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_sysrst_ctrl_inputs.3120072266 |
|
|
Aug 24 01:34:05 PM UTC 24 |
Aug 24 01:37:38 PM UTC 24 |
2868576682 ps |
| T1125 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_pwrmgr_usb_clk_disabled_when_active.158930399 |
|
|
Aug 24 01:32:55 PM UTC 24 |
Aug 24 01:38:34 PM UTC 24 |
4829529140 ps |
| T1126 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_sysrst_ctrl_outputs.3731335771 |
|
|
Aug 24 01:35:40 PM UTC 24 |
Aug 24 01:39:48 PM UTC 24 |
3635523598 ps |
| T1127 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_sysrst_ctrl_in_irq.2185459361 |
|
|
Aug 24 01:34:28 PM UTC 24 |
Aug 24 01:41:31 PM UTC 24 |
4270250991 ps |
| T1128 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_aon_timer_irq.3498635708 |
|
|
Aug 24 01:36:21 PM UTC 24 |
Aug 24 01:41:32 PM UTC 24 |
4275108664 ps |
| T54 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_sysrst_ctrl_ulp_z3_wakeup.2497647027 |
|
|
Aug 24 01:35:43 PM UTC 24 |
Aug 24 01:41:32 PM UTC 24 |
5504636172 ps |
| T1129 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_pwrmgr_normal_sleep_all_reset_reqs.3371270771 |
|
|
Aug 24 01:28:07 PM UTC 24 |
Aug 24 01:42:13 PM UTC 24 |
10346959382 ps |
| T1130 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_aon_timer_sleep_wdog_sleep_pause.2595310356 |
|
|
Aug 24 01:36:21 PM UTC 24 |
Aug 24 01:42:58 PM UTC 24 |
6806571320 ps |
| T1131 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_pwrmgr_deep_sleep_all_reset_reqs.894194271 |
|
|
Aug 24 01:27:37 PM UTC 24 |
Aug 24 01:42:59 PM UTC 24 |
18223591278 ps |
| T1132 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_pwrmgr_wdog_reset.3410177695 |
|
|
Aug 24 01:38:01 PM UTC 24 |
Aug 24 01:43:39 PM UTC 24 |
4911962776 ps |
| T1133 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_aon_timer_wdog_lc_escalate.3079202693 |
|
|
Aug 24 01:38:03 PM UTC 24 |
Aug 24 01:43:54 PM UTC 24 |
5371593088 ps |
| T1134 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_pwrmgr_all_reset_reqs.2142753523 |
|
|
Aug 24 01:25:47 PM UTC 24 |
Aug 24 01:43:56 PM UTC 24 |
12359561286 ps |
| T1135 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_csrng_edn_concurrency_reduced_freq.1541720035 |
|
|
Aug 24 12:27:35 PM UTC 24 |
Aug 24 01:44:13 PM UTC 24 |
31912503205 ps |
| T1136 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_aon_timer_wdog_bite_reset.3782285191 |
|
|
Aug 24 01:37:28 PM UTC 24 |
Aug 24 01:45:24 PM UTC 24 |
8578636028 ps |
| T1137 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_exit_test_unlocked_bootstrap.3464088595 |
|
|
Aug 24 10:58:10 AM UTC 24 |
Aug 24 01:45:40 PM UTC 24 |
58629726184 ps |
| T1138 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_aes_enc.1926530897 |
|
|
Aug 24 01:43:30 PM UTC 24 |
Aug 24 01:46:24 PM UTC 24 |
3011820906 ps |
| T1139 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_aes_idle.431713156 |
|
|
Aug 24 01:44:25 PM UTC 24 |
Aug 24 01:46:45 PM UTC 24 |
2484553600 ps |
| T1140 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_aes_enc_jitter_en.2986733029 |
|
|
Aug 24 01:44:02 PM UTC 24 |
Aug 24 01:47:25 PM UTC 24 |
3041069106 ps |
| T1141 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_aes_masking_off.4250786895 |
|
|
Aug 24 01:44:25 PM UTC 24 |
Aug 24 01:47:45 PM UTC 24 |
2841132658 ps |
| T89 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_alert_test.305546160 |
|
|
Aug 24 01:44:38 PM UTC 24 |
Aug 24 01:48:08 PM UTC 24 |
2575928016 ps |
| T1142 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_adc_ctrl_sleep_debug_cable_wakeup.513756129 |
|
|
Aug 24 01:38:59 PM UTC 24 |
Aug 24 01:48:12 PM UTC 24 |
19086957032 ps |
| T1143 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_otbn_mem_scramble.3767096917 |
|
|
Aug 24 01:42:11 PM UTC 24 |
Aug 24 01:48:20 PM UTC 24 |
3373002008 ps |
| T364 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_rstmgr_alert_info.2786853160 |
|
|
Aug 24 01:25:32 PM UTC 24 |
Aug 24 01:48:40 PM UTC 24 |
13009251548 ps |
| T1144 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_lc_walkthrough_testunlocks.472334380 |
|
|
Aug 24 01:25:15 PM UTC 24 |
Aug 24 01:49:57 PM UTC 24 |
23360576704 ps |
| T1145 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_alert_handler_ping_timeout.757849651 |
|
|
Aug 24 01:46:04 PM UTC 24 |
Aug 24 01:50:04 PM UTC 24 |
3484913800 ps |
| T1146 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_otbn_randomness.281471691 |
|
|
Aug 24 01:40:12 PM UTC 24 |
Aug 24 01:50:51 PM UTC 24 |
5700021264 ps |
| T1147 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_aes_entropy.1023536042 |
|
|
Aug 24 01:49:04 PM UTC 24 |
Aug 24 01:51:54 PM UTC 24 |
2708478288 ps |
| T1148 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_alert_handler_entropy.1646151973 |
|
|
Aug 24 01:48:48 PM UTC 24 |
Aug 24 01:52:02 PM UTC 24 |
3295921981 ps |
| T696 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_alert_handler_lpg_sleep_mode_alerts.3855713159 |
|
|
Aug 24 01:47:49 PM UTC 24 |
Aug 24 01:52:23 PM UTC 24 |
3314002190 ps |
| T1149 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_alert_handler_escalation.2659333627 |
|
|
Aug 24 01:45:48 PM UTC 24 |
Aug 24 01:52:38 PM UTC 24 |
5671895572 ps |
| T658 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_rv_core_ibex_nmi_irq.1443264193 |
|
|
Aug 24 01:43:29 PM UTC 24 |
Aug 24 01:53:10 PM UTC 24 |
4602942362 ps |
| T1150 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_sysrst_ctrl_reset.1453395622 |
|
|
Aug 24 01:35:40 PM UTC 24 |
Aug 24 01:53:36 PM UTC 24 |
22111595864 ps |
| T1151 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_entropy_src_kat_test.3173612142 |
|
|
Aug 24 01:50:28 PM UTC 24 |
Aug 24 01:53:45 PM UTC 24 |
3152294920 ps |
| T1152 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_rv_core_ibex_rnd.1016051151 |
|
|
Aug 24 01:42:36 PM UTC 24 |
Aug 24 01:54:04 PM UTC 24 |
5331389950 ps |
| T1153 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_pwrmgr_random_sleep_all_reset_reqs.4060753292 |
|
|
Aug 24 01:26:24 PM UTC 24 |
Aug 24 01:54:15 PM UTC 24 |
26129786596 ps |
| T1154 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_csrng_kat_test.463495247 |
|
|
Aug 24 01:53:34 PM UTC 24 |
Aug 24 01:56:47 PM UTC 24 |
3188486504 ps |
| T1155 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_entropy_src_ast_rng_req.3181282233 |
|
|
Aug 24 01:54:09 PM UTC 24 |
Aug 24 01:57:22 PM UTC 24 |
3088483724 ps |
| T452 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_edn_boot_mode.770576449 |
|
|
Aug 24 01:51:16 PM UTC 24 |
Aug 24 01:57:49 PM UTC 24 |
3072465144 ps |
| T1156 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_csrng_fuse_en_sw_app_read_test.3020017803 |
|
|
Aug 24 01:54:06 PM UTC 24 |
Aug 24 01:59:07 PM UTC 24 |
4443842640 ps |
| T1157 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_edn_kat.365991402 |
|
|
Aug 24 01:52:25 PM UTC 24 |
Aug 24 02:00:25 PM UTC 24 |
3580678424 ps |
| T1158 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_hmac_enc.1111447181 |
|
|
Aug 24 01:57:47 PM UTC 24 |
Aug 24 02:00:58 PM UTC 24 |
2355802820 ps |
| T676 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_alert_handler_lpg_sleep_mode_pings.771205034 |
|
|
Aug 24 01:48:10 PM UTC 24 |
Aug 24 02:01:05 PM UTC 24 |
9564589368 ps |
| T1159 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_hmac_enc_jitter_en.2510002057 |
|
|
Aug 24 01:58:13 PM UTC 24 |
Aug 24 02:01:31 PM UTC 24 |
2888485526 ps |
| T1160 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_csrng_lc_hw_debug_en_test.1139467419 |
|
|
Aug 24 01:52:47 PM UTC 24 |
Aug 24 02:01:59 PM UTC 24 |
7492824709 ps |
| T1161 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_hmac_enc_idle.3571438373 |
|
|
Aug 24 01:59:31 PM UTC 24 |
Aug 24 02:03:02 PM UTC 24 |
2829357028 ps |
| T1162 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_hmac_oneshot.295541996 |
|
|
Aug 24 02:00:49 PM UTC 24 |
Aug 24 02:04:31 PM UTC 24 |
3215313380 ps |
| T1163 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_alert_handler_ping_ok.4141740008 |
|
|
Aug 24 01:46:48 PM UTC 24 |
Aug 24 02:04:38 PM UTC 24 |
7917589440 ps |
| T1164 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_edn_entropy_reqs_jitter.2267258573 |
|
|
Aug 24 01:57:13 PM UTC 24 |
Aug 24 02:08:04 PM UTC 24 |
6453531094 ps |
| T1165 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_kmac_mode_cshake.1720303053 |
|
|
Aug 24 02:05:04 PM UTC 24 |
Aug 24 02:08:05 PM UTC 24 |
2575662448 ps |
| T1166 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_alert_handler_lpg_reset_toggle.600796568 |
|
|
Aug 24 01:48:49 PM UTC 24 |
Aug 24 02:08:35 PM UTC 24 |
7555201872 ps |
| T1167 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_alert_handler_lpg_clkoff.736204347 |
|
|
Aug 24 01:48:48 PM UTC 24 |
Aug 24 02:10:10 PM UTC 24 |
7533367544 ps |
| T1168 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/1.rom_e2e_self_hash.3428965044 |
|
|
Aug 24 12:38:32 PM UTC 24 |
Aug 24 02:10:21 PM UTC 24 |
26465435924 ps |
| T1169 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_edn_entropy_reqs.3122199430 |
|
|
Aug 24 01:54:40 PM UTC 24 |
Aug 24 02:10:26 PM UTC 24 |
7232008120 ps |
| T1170 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_kmac_mode_kmac_jitter_en.2023070143 |
|
|
Aug 24 02:08:36 PM UTC 24 |
Aug 24 02:11:49 PM UTC 24 |
2727218161 ps |
| T1171 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_kmac_app_rom.496155695 |
|
|
Aug 24 02:08:58 PM UTC 24 |
Aug 24 02:12:16 PM UTC 24 |
2864738598 ps |
| T1172 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_kmac_mode_kmac.3443794998 |
|
|
Aug 24 02:08:36 PM UTC 24 |
Aug 24 02:13:07 PM UTC 24 |
3613926532 ps |
| T1173 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_kmac_idle.869174628 |
|
|
Aug 24 02:10:34 PM UTC 24 |
Aug 24 02:13:47 PM UTC 24 |
2772085470 ps |
| T1174 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_edn_auto_mode.4129172521 |
|
|
Aug 24 01:50:30 PM UTC 24 |
Aug 24 02:14:05 PM UTC 24 |
7939804520 ps |
| T1175 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_inject_scramble_seed.1192202516 |
|
|
Aug 24 10:58:10 AM UTC 24 |
Aug 24 02:15:08 PM UTC 24 |
64045576971 ps |
| T365 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_entropy_src_csrng.2485125969 |
|
|
Aug 24 01:54:29 PM UTC 24 |
Aug 24 02:15:20 PM UTC 24 |
7425802716 ps |
| T1176 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_rom_ctrl_integrity_check.3524900464 |
|
|
Aug 24 02:10:53 PM UTC 24 |
Aug 24 02:15:57 PM UTC 24 |
9565882496 ps |
| T1177 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_sram_ctrl_scrambled_access.3437195349 |
|
|
Aug 24 02:10:53 PM UTC 24 |
Aug 24 02:17:01 PM UTC 24 |
4289392630 ps |
| T1178 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_keymgr_key_derivation_prod.635377193 |
|
|
Aug 24 02:01:55 PM UTC 24 |
Aug 24 02:17:47 PM UTC 24 |
8193089288 ps |
| T1179 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_edn_sw_mode.2381369428 |
|
|
Aug 24 01:52:27 PM UTC 24 |
Aug 24 02:18:41 PM UTC 24 |
10098199520 ps |
| T1180 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_sysrst_ctrl_ec_rst_l.2000505467 |
|
|
Aug 24 01:35:43 PM UTC 24 |
Aug 24 02:18:57 PM UTC 24 |
21142204212 ps |
| T375 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_sensor_ctrl_status.1717240998 |
|
|
Aug 24 02:15:32 PM UTC 24 |
Aug 24 02:19:14 PM UTC 24 |
2732770643 ps |
| T1181 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_sleep_sram_ret_contents_no_scramble.276539265 |
|
|
Aug 24 02:13:31 PM UTC 24 |
Aug 24 02:20:24 PM UTC 24 |
7235013800 ps |
| T171 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup.2475325570 |
|
|
Aug 24 02:15:44 PM UTC 24 |
Aug 24 02:20:32 PM UTC 24 |
4763845700 ps |
| T1182 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_sram_ctrl_scrambled_access_jitter_en.151288880 |
|
|
Aug 24 02:12:13 PM UTC 24 |
Aug 24 02:20:50 PM UTC 24 |
5331767688 ps |
| T1183 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_keymgr_key_derivation_jitter_en.2495852411 |
|
|
Aug 24 02:02:23 PM UTC 24 |
Aug 24 02:21:03 PM UTC 24 |
9093601668 ps |
| T1184 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_hmac_multistream.82765181 |
|
|
Aug 24 02:01:31 PM UTC 24 |
Aug 24 02:21:41 PM UTC 24 |
8448506950 ps |
| T172 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_sensor_ctrl_alert.4223843829 |
|
|
Aug 24 02:14:29 PM UTC 24 |
Aug 24 02:22:22 PM UTC 24 |
5807434080 ps |
| T1185 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_sleep_sram_ret_contents_scramble.2150124479 |
|
|
Aug 24 02:14:13 PM UTC 24 |
Aug 24 02:23:24 PM UTC 24 |
7669930604 ps |
| T332 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_plic_sw_irq.3534058288 |
|
|
Aug 24 02:19:22 PM UTC 24 |
Aug 24 02:23:32 PM UTC 24 |
3114240080 ps |
| T1186 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_keymgr_sideload_kmac.861569127 |
|
|
Aug 24 02:03:27 PM UTC 24 |
Aug 24 02:23:58 PM UTC 24 |
8741186774 ps |
| T306 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_sram_ctrl_execution_main.3229214253 |
|
|
Aug 24 02:12:39 PM UTC 24 |
Aug 24 02:24:31 PM UTC 24 |
9481510939 ps |
| T194 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_plic_all_irqs_10.635556492 |
|
|
Aug 24 02:18:11 PM UTC 24 |
Aug 24 02:26:14 PM UTC 24 |
3677568552 ps |
| T1187 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_clkmgr_off_hmac_trans.3208032572 |
|
|
Aug 24 02:20:57 PM UTC 24 |
Aug 24 02:26:17 PM UTC 24 |
4873149264 ps |
| T1188 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_clkmgr_off_aes_trans.1886190845 |
|
|
Aug 24 02:20:55 PM UTC 24 |
Aug 24 02:26:49 PM UTC 24 |
5254737428 ps |
| T1189 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_clkmgr_off_otbn_trans.3969771033 |
|
|
Aug 24 02:21:27 PM UTC 24 |
Aug 24 02:27:26 PM UTC 24 |
4508164938 ps |
| T1190 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_clkmgr_off_kmac_trans.3331687344 |
|
|
Aug 24 02:21:14 PM UTC 24 |
Aug 24 02:27:32 PM UTC 24 |
5832804712 ps |
| T1191 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_keymgr_key_derivation.3096193493 |
|
|
Aug 24 02:01:32 PM UTC 24 |
Aug 24 02:27:55 PM UTC 24 |
9926301800 ps |
| T339 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_plic_all_irqs_20.3886849096 |
|
|
Aug 24 02:19:06 PM UTC 24 |
Aug 24 02:28:12 PM UTC 24 |
4887715232 ps |
| T227 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_flash_rma_unlocked.4288649324 |
|
|
Aug 24 01:16:46 PM UTC 24 |
Aug 24 02:28:21 PM UTC 24 |
44753586454 ps |
| T318 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_keymgr_sideload_aes.3191192015 |
|
|
Aug 24 02:04:06 PM UTC 24 |
Aug 24 02:29:24 PM UTC 24 |
10115566520 ps |
| T1192 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0.1651912347 |
|
|
Aug 24 02:22:46 PM UTC 24 |
Aug 24 02:29:26 PM UTC 24 |
3570705320 ps |
| T1193 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_clkmgr_jitter.3313197597 |
|
|
Aug 24 02:27:56 PM UTC 24 |
Aug 24 02:30:29 PM UTC 24 |
2045067121 ps |
| T342 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_plic_all_irqs_0.2412421818 |
|
|
Aug 24 02:17:26 PM UTC 24 |
Aug 24 02:30:44 PM UTC 24 |
6108643806 ps |
| T1194 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_clkmgr_external_clk_src_for_sw_fast_dev.1424691117 |
|
|
Aug 24 02:23:57 PM UTC 24 |
Aug 24 02:30:59 PM UTC 24 |
4244953076 ps |
| T1195 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0.4241733381 |
|
|
Aug 24 02:23:55 PM UTC 24 |
Aug 24 02:31:30 PM UTC 24 |
4574353056 ps |
| T1196 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_clkmgr_external_clk_src_for_lc.3502606723 |
|
|
Aug 24 02:22:05 PM UTC 24 |
Aug 24 02:31:34 PM UTC 24 |
10092491849 ps |
| T1197 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_clkmgr_reset_frequency.3855548330 |
|
|
Aug 24 02:26:46 PM UTC 24 |
Aug 24 02:31:36 PM UTC 24 |
3113756500 ps |
| T1198 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_clkmgr_external_clk_src_for_sw_slow_dev.1786121166 |
|
|
Aug 24 02:24:21 PM UTC 24 |
Aug 24 02:31:46 PM UTC 24 |
4488357480 ps |
| T1199 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_clkmgr_jitter_frequency.3693629625 |
|
|
Aug 24 02:27:13 PM UTC 24 |
Aug 24 02:32:17 PM UTC 24 |
3361267736 ps |
| T1200 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_clkmgr_external_clk_src_for_sw_fast_rma.4088846672 |
|
|
Aug 24 02:24:56 PM UTC 24 |
Aug 24 02:32:34 PM UTC 24 |
4028025580 ps |
| T1201 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_clkmgr_external_clk_src_for_sw_slow_rma.3059370378 |
|
|
Aug 24 02:26:46 PM UTC 24 |
Aug 24 02:33:18 PM UTC 24 |
4708608358 ps |
| T1202 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_otbn_ecdsa_op_irq.985801287 |
|
|
Aug 24 01:42:10 PM UTC 24 |
Aug 24 02:34:00 PM UTC 24 |
17245702700 ps |
| T1203 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_lc_walkthrough_dev.136684197 |
|
|
Aug 24 01:22:18 PM UTC 24 |
Aug 24 02:34:09 PM UTC 24 |
47793438545 ps |
| T211 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_lc_ctrl_program_error.1311631791 |
|
|
Aug 24 02:29:56 PM UTC 24 |
Aug 24 02:34:39 PM UTC 24 |
4472458614 ps |
| T438 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_pwrmgr_normal_sleep_all_wake_ups.2464340077 |
|
|
Aug 24 02:29:56 PM UTC 24 |
Aug 24 02:35:18 PM UTC 24 |
7503530150 ps |
| T1204 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_clkmgr_off_peri.3478105916 |
|
|
Aug 24 02:19:39 PM UTC 24 |
Aug 24 02:35:20 PM UTC 24 |
10936943282 ps |
| T441 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_rv_dm_ndm_reset_req.2960285409 |
|
|
Aug 24 02:32:20 PM UTC 24 |
Aug 24 02:35:33 PM UTC 24 |
4426411160 ps |
| T1205 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_clkmgr_sleep_frequency.547629533 |
|
|
Aug 24 02:27:58 PM UTC 24 |
Aug 24 02:35:39 PM UTC 24 |
5143084290 ps |
| T1206 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_tap_straps_dev.2020654856 |
|
|
Aug 24 02:33:38 PM UTC 24 |
Aug 24 02:35:52 PM UTC 24 |
2854096796 ps |
| T369 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_pwrmgr_lowpower_cancel.424078254 |
|
|
Aug 24 02:30:54 PM UTC 24 |
Aug 24 02:36:41 PM UTC 24 |
4254950768 ps |
| T1207 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_tap_straps_prod.2698376277 |
|
|
Aug 24 02:34:58 PM UTC 24 |
Aug 24 02:36:54 PM UTC 24 |
2597103661 ps |
| T1208 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_otbn_ecdsa_op_irq_jitter_en.1957493146 |
|
|
Aug 24 01:42:11 PM UTC 24 |
Aug 24 02:37:08 PM UTC 24 |
18972286016 ps |
| T1209 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_pwrmgr_sleep_wake_5_bug.3944433458 |
|
|
Aug 24 02:32:17 PM UTC 24 |
Aug 24 02:37:22 PM UTC 24 |
5541892160 ps |
| T389 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up.3364487130 |
|
|
Aug 24 02:32:19 PM UTC 24 |
Aug 24 02:37:27 PM UTC 24 |
5266730472 ps |
| T1210 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_rv_dm_access_after_wakeup.3338828105 |
|
|
Aug 24 02:32:42 PM UTC 24 |
Aug 24 02:37:42 PM UTC 24 |
6663904328 ps |
| T419 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_rv_core_ibex_lockstep_glitch.1970261168 |
|
|
Aug 24 02:35:55 PM UTC 24 |
Aug 24 02:37:55 PM UTC 24 |
2425096700 ps |
| T1211 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_pwrmgr_b2b_sleep_reset_req.1472083201 |
|
|
Aug 24 02:16:21 PM UTC 24 |
Aug 24 02:38:20 PM UTC 24 |
20699421186 ps |
| T297 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_rv_core_ibex_icache_invalidate.3627654565 |
|
|
Aug 24 02:36:07 PM UTC 24 |
Aug 24 02:38:34 PM UTC 24 |
2221561491 ps |
| T361 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_rv_dm_ndm_reset_req_when_cpu_halted.3483602790 |
|
|
Aug 24 02:32:19 PM UTC 24 |
Aug 24 02:38:43 PM UTC 24 |
4880501156 ps |
| T257 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_rv_core_ibex_address_translation.3021988852 |
|
|
Aug 24 02:35:56 PM UTC 24 |
Aug 24 02:39:21 PM UTC 24 |
2896255930 ps |
| T1212 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_ast_clk_outputs.3159289137 |
|
|
Aug 24 02:28:45 PM UTC 24 |
Aug 24 02:39:33 PM UTC 24 |
6636899374 ps |
| T1213 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_clkmgr_jitter_reduced_freq.2950390353 |
|
|
Aug 24 02:37:04 PM UTC 24 |
Aug 24 02:39:53 PM UTC 24 |
2781498917 ps |
| T629 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_rv_dm_access_after_escalation_reset.982646603 |
|
|
Aug 24 02:32:57 PM UTC 24 |
Aug 24 02:39:54 PM UTC 24 |
5470885563 ps |
| T1214 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_lc_walkthrough_rma.3021485218 |
|
|
Aug 24 01:23:55 PM UTC 24 |
Aug 24 02:39:59 PM UTC 24 |
48914712612 ps |
| T1215 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_flash_ctrl_write_clear.2884664511 |
|
|
Aug 24 02:36:17 PM UTC 24 |
Aug 24 02:40:14 PM UTC 24 |
3613453872 ps |
| T1216 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_uart_tx_rx_bootstrap.2842322799 |
|
|
Aug 24 10:58:00 AM UTC 24 |
Aug 24 02:40:38 PM UTC 24 |
78785630288 ps |
| T1217 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_lc_walkthrough_prod.2926152810 |
|
|
Aug 24 01:22:28 PM UTC 24 |
Aug 24 02:40:43 PM UTC 24 |
51508525255 ps |
| T1218 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_hmac_enc_jitter_en_reduced_freq.3897247389 |
|
|
Aug 24 02:38:06 PM UTC 24 |
Aug 24 02:40:59 PM UTC 24 |
2810298447 ps |
| T93 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_tap_straps_rma.3418317404 |
|
|
Aug 24 02:34:28 PM UTC 24 |
Aug 24 02:40:59 PM UTC 24 |
6022785830 ps |
| T1219 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_aes_enc_jitter_en_reduced_freq.2112891183 |
|
|
Aug 24 02:37:54 PM UTC 24 |
Aug 24 02:41:21 PM UTC 24 |
2912961212 ps |
| T1220 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_tap_straps_testunlock0.3892192789 |
|
|
Aug 24 02:34:20 PM UTC 24 |
Aug 24 02:42:24 PM UTC 24 |
7608319767 ps |
| T1221 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_kmac_mode_kmac_jitter_en_reduced_freq.3978684972 |
|
|
Aug 24 02:38:44 PM UTC 24 |
Aug 24 02:42:28 PM UTC 24 |
3174206478 ps |
| T1222 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_flash_crash_alert.3169974434 |
|
|
Aug 24 02:36:14 PM UTC 24 |
Aug 24 02:43:57 PM UTC 24 |
4480449520 ps |
| T1223 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_flash_scrambling_smoketest.2510517233 |
|
|
Aug 24 02:41:30 PM UTC 24 |
Aug 24 02:44:56 PM UTC 24 |
3425617076 ps |
| T243 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_jtag_mem_access.1515699025 |
|
|
Aug 24 02:28:27 PM UTC 24 |
Aug 24 02:45:08 PM UTC 24 |
13585778955 ps |
| T1224 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq.2770833094 |
|
|
Aug 24 02:38:57 PM UTC 24 |
Aug 24 02:45:23 PM UTC 24 |
5557977120 ps |
| T652 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_power_sleep_load.4197728884 |
|
|
Aug 24 02:41:08 PM UTC 24 |
Aug 24 02:45:32 PM UTC 24 |
5042517746 ps |
| T1225 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_flash_ctrl_ops_jitter_en_reduced_freq.1685902909 |
|
|
Aug 24 02:37:18 PM UTC 24 |
Aug 24 02:45:33 PM UTC 24 |
5165268937 ps |
| T1226 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_power_idle_load.1832082947 |
|
|
Aug 24 02:39:59 PM UTC 24 |
Aug 24 02:48:07 PM UTC 24 |
4580597960 ps |
| T1227 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_pwrmgr_deep_sleep_all_wake_ups.1642048100 |
|
|
Aug 24 02:31:08 PM UTC 24 |
Aug 24 02:48:22 PM UTC 24 |
23083765530 ps |
| T657 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_pwrmgr_random_sleep_all_wake_ups.3187627176 |
|
|
Aug 24 02:31:24 PM UTC 24 |
Aug 24 02:49:09 PM UTC 24 |
23961045864 ps |
| T1228 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/2.rom_volatile_raw_unlock.868265603 |
|
|
Aug 24 02:48:31 PM UTC 24 |
Aug 24 02:50:04 PM UTC 24 |
2580384443 ps |
| T81 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_jtag_csr_rw.1618617623 |
|
|
Aug 24 02:28:10 PM UTC 24 |
Aug 24 02:50:05 PM UTC 24 |
18612019124 ps |
| T1229 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_flash_ctrl_access_jitter_en_reduced_freq.2283787259 |
|
|
Aug 24 02:37:32 PM UTC 24 |
Aug 24 02:50:51 PM UTC 24 |
8396282751 ps |
| T1230 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/2.rom_raw_unlock.2798123881 |
|
|
Aug 24 02:48:46 PM UTC 24 |
Aug 24 02:51:43 PM UTC 24 |
5422733587 ps |
| T1231 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_aes_smoketest.2560217481 |
|
|
Aug 24 02:50:36 PM UTC 24 |
Aug 24 02:53:40 PM UTC 24 |
2972556040 ps |
| T1232 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_flash_ctrl_mem_protection.1614087372 |
|
|
Aug 24 02:41:24 PM UTC 24 |
Aug 24 02:54:11 PM UTC 24 |
5500878010 ps |
| T1233 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_clkmgr_smoketest.2341388915 |
|
|
Aug 24 02:52:07 PM UTC 24 |
Aug 24 02:54:31 PM UTC 24 |
3134653720 ps |
| T1234 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_aon_timer_smoketest.3772891332 |
|
|
Aug 24 02:51:15 PM UTC 24 |
Aug 24 02:55:38 PM UTC 24 |
3701098352 ps |
| T1235 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_keymgr_key_derivation_jitter_en_reduced_freq.1330588147 |
|
|
Aug 24 02:38:19 PM UTC 24 |
Aug 24 02:57:15 PM UTC 24 |
11361870570 ps |
| T1236 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_csrng_smoketest.1004530776 |
|
|
Aug 24 02:54:04 PM UTC 24 |
Aug 24 02:57:32 PM UTC 24 |
3402164524 ps |
| T1237 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/2.rom_keymgr_functest.975440510 |
|
|
Aug 24 02:50:35 PM UTC 24 |
Aug 24 02:57:45 PM UTC 24 |
4551272728 ps |
| T1238 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_gpio_smoketest.3132280904 |
|
|
Aug 24 02:54:55 PM UTC 24 |
Aug 24 02:58:21 PM UTC 24 |
3172182333 ps |
| T130 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_power_virus.3491664178 |
|
|
Aug 24 02:41:30 PM UTC 24 |
Aug 24 02:58:30 PM UTC 24 |
5602943300 ps |
| T1239 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_entropy_src_smoketest.1266827976 |
|
|
Aug 24 02:54:34 PM UTC 24 |
Aug 24 02:59:27 PM UTC 24 |
3156987580 ps |
| T1240 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_hmac_smoketest.3737626488 |
|
|
Aug 24 02:56:02 PM UTC 24 |
Aug 24 02:59:42 PM UTC 24 |
3317260060 ps |
| T1241 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_alert_handler_reverse_ping_in_deep_sleep.2293328563 |
|
|
Aug 24 11:40:11 AM UTC 24 |
Aug 24 03:00:31 PM UTC 24 |
254962225056 ps |
| T1242 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_kmac_smoketest.2898478865 |
|
|
Aug 24 02:57:39 PM UTC 24 |
Aug 24 03:01:03 PM UTC 24 |
2550661120 ps |
| T1243 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_otp_ctrl_smoketest.818125015 |
|
|
Aug 24 02:58:09 PM UTC 24 |
Aug 24 03:01:19 PM UTC 24 |
3692191156 ps |
| T1244 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_rv_timer_smoketest.1771758136 |
|
|
Aug 24 03:00:05 PM UTC 24 |
Aug 24 03:02:47 PM UTC 24 |
2378731360 ps |
| T1245 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_rv_plic_smoketest.754536921 |
|
|
Aug 24 02:59:50 PM UTC 24 |
Aug 24 03:02:50 PM UTC 24 |
2268441600 ps |
| T1246 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_rstmgr_smoketest.3633004386 |
|
|
Aug 24 03:00:54 PM UTC 24 |
Aug 24 03:03:11 PM UTC 24 |
2700590116 ps |
| T1247 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_pwrmgr_smoketest.218070770 |
|
|
Aug 24 02:58:52 PM UTC 24 |
Aug 24 03:03:40 PM UTC 24 |
5385757640 ps |
| T1248 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_sram_ctrl_smoketest.1593408881 |
|
|
Aug 24 03:01:26 PM UTC 24 |
Aug 24 03:04:25 PM UTC 24 |
3205646808 ps |