| T2272 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/63.xbar_same_source.4021340833 |
|
|
Aug 24 06:33:59 AM UTC 24 |
Aug 24 06:34:09 AM UTC 24 |
125818475 ps |
| T2273 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/63.xbar_error_random.859559520 |
|
|
Aug 24 06:34:03 AM UTC 24 |
Aug 24 06:34:10 AM UTC 24 |
49681178 ps |
| T2274 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/63.xbar_smoke_slow_rsp.3584156375 |
|
|
Aug 24 06:33:07 AM UTC 24 |
Aug 24 06:34:24 AM UTC 24 |
6379219746 ps |
| T2275 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/59.xbar_random_large_delays.1082318435 |
|
|
Aug 24 06:26:55 AM UTC 24 |
Aug 24 06:34:24 AM UTC 24 |
54724866301 ps |
| T2276 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/63.xbar_error_and_unmapped_addr.952281125 |
|
|
Aug 24 06:34:18 AM UTC 24 |
Aug 24 06:34:26 AM UTC 24 |
140217438 ps |
| T2277 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/63.xbar_unmapped_addr.2162153409 |
|
|
Aug 24 06:34:15 AM UTC 24 |
Aug 24 06:34:29 AM UTC 24 |
346810003 ps |
| T2278 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/58.xbar_random_slow_rsp.1760530390 |
|
|
Aug 24 06:25:34 AM UTC 24 |
Aug 24 06:34:30 AM UTC 24 |
46548381896 ps |
| T2279 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/63.xbar_stress_all_with_rand_reset.403128012 |
|
|
Aug 24 06:34:22 AM UTC 24 |
Aug 24 06:34:42 AM UTC 24 |
50928733 ps |
| T2280 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/64.xbar_smoke.3412403923 |
|
|
Aug 24 06:34:38 AM UTC 24 |
Aug 24 06:34:44 AM UTC 24 |
54405237 ps |
| T2281 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/64.xbar_smoke_zero_delays.3136129557 |
|
|
Aug 24 06:34:39 AM UTC 24 |
Aug 24 06:34:45 AM UTC 24 |
54175121 ps |
| T847 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/62.xbar_stress_all_with_reset_error.152751221 |
|
|
Aug 24 06:32:49 AM UTC 24 |
Aug 24 06:35:05 AM UTC 24 |
922480122 ps |
| T2282 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/46.xbar_access_same_device_slow_rsp.1245408845 |
|
|
Aug 24 06:04:17 AM UTC 24 |
Aug 24 06:35:08 AM UTC 24 |
156530748529 ps |
| T612 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/61.xbar_stress_all_with_reset_error.2102030724 |
|
|
Aug 24 06:31:11 AM UTC 24 |
Aug 24 06:35:16 AM UTC 24 |
6361851753 ps |
| T2283 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/64.xbar_random_zero_delays.588517061 |
|
|
Aug 24 06:34:56 AM UTC 24 |
Aug 24 06:35:17 AM UTC 24 |
319056114 ps |
| T2284 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/54.xbar_access_same_device_slow_rsp.559702340 |
|
|
Aug 24 06:19:34 AM UTC 24 |
Aug 24 06:35:23 AM UTC 24 |
82962300396 ps |
| T2285 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/64.xbar_smoke_slow_rsp.3588390486 |
|
|
Aug 24 06:34:43 AM UTC 24 |
Aug 24 06:35:25 AM UTC 24 |
3371842870 ps |
| T2286 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/59.xbar_random_slow_rsp.3495243975 |
|
|
Aug 24 06:26:58 AM UTC 24 |
Aug 24 06:35:28 AM UTC 24 |
43622368922 ps |
| T2287 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/64.xbar_smoke_large_delays.1209017135 |
|
|
Aug 24 06:34:40 AM UTC 24 |
Aug 24 06:35:39 AM UTC 24 |
7132837563 ps |
| T2288 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/64.xbar_random_slow_rsp.3025211878 |
|
|
Aug 24 06:34:59 AM UTC 24 |
Aug 24 06:35:42 AM UTC 24 |
3451876009 ps |
| T2289 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/64.xbar_error_and_unmapped_addr.396360211 |
|
|
Aug 24 06:35:38 AM UTC 24 |
Aug 24 06:35:44 AM UTC 24 |
37848351 ps |
| T2290 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/64.xbar_same_source.3592065126 |
|
|
Aug 24 06:35:29 AM UTC 24 |
Aug 24 06:35:50 AM UTC 24 |
348913873 ps |
| T2291 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/64.xbar_random.807888840 |
|
|
Aug 24 06:34:45 AM UTC 24 |
Aug 24 06:35:52 AM UTC 24 |
2516076869 ps |
| T2292 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/64.xbar_error_random.3235223865 |
|
|
Aug 24 06:35:31 AM UTC 24 |
Aug 24 06:35:56 AM UTC 24 |
420191256 ps |
| T2293 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/61.xbar_random_slow_rsp.2362871097 |
|
|
Aug 24 06:29:53 AM UTC 24 |
Aug 24 06:35:58 AM UTC 24 |
29810303115 ps |
| T2294 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/64.xbar_unmapped_addr.3407865861 |
|
|
Aug 24 06:35:36 AM UTC 24 |
Aug 24 06:36:07 AM UTC 24 |
1019050504 ps |
| T2295 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/65.xbar_smoke.3164762787 |
|
|
Aug 24 06:36:04 AM UTC 24 |
Aug 24 06:36:12 AM UTC 24 |
194638392 ps |
| T2296 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/65.xbar_smoke_zero_delays.3019563882 |
|
|
Aug 24 06:36:07 AM UTC 24 |
Aug 24 06:36:13 AM UTC 24 |
46476893 ps |
| T2297 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/64.xbar_access_same_device.3620138209 |
|
|
Aug 24 06:35:19 AM UTC 24 |
Aug 24 06:36:16 AM UTC 24 |
1027409727 ps |
| T2298 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/60.xbar_random_slow_rsp.349827295 |
|
|
Aug 24 06:28:25 AM UTC 24 |
Aug 24 06:36:18 AM UTC 24 |
40884857409 ps |
| T2299 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/65.xbar_random.681698351 |
|
|
Aug 24 06:36:21 AM UTC 24 |
Aug 24 06:36:30 AM UTC 24 |
197850152 ps |
| T2300 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/56.xbar_access_same_device_slow_rsp.1951509219 |
|
|
Aug 24 06:22:57 AM UTC 24 |
Aug 24 06:36:31 AM UTC 24 |
67670974717 ps |
| T2301 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/64.xbar_stress_all_with_rand_reset.1322907644 |
|
|
Aug 24 06:35:54 AM UTC 24 |
Aug 24 06:36:36 AM UTC 24 |
26426275 ps |
| T2302 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/61.xbar_stress_all_with_error.2966259611 |
|
|
Aug 24 06:31:10 AM UTC 24 |
Aug 24 06:36:38 AM UTC 24 |
14504213191 ps |
| T2303 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/63.xbar_stress_all.1094845131 |
|
|
Aug 24 06:34:21 AM UTC 24 |
Aug 24 06:36:45 AM UTC 24 |
6055778009 ps |
| T2304 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/65.xbar_error_random.4149720441 |
|
|
Aug 24 06:36:50 AM UTC 24 |
Aug 24 06:36:57 AM UTC 24 |
71074489 ps |
| T2305 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/65.xbar_random_zero_delays.1989031602 |
|
|
Aug 24 06:36:26 AM UTC 24 |
Aug 24 06:37:02 AM UTC 24 |
586408945 ps |
| T2306 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/65.xbar_smoke_slow_rsp.2151275839 |
|
|
Aug 24 06:36:12 AM UTC 24 |
Aug 24 06:37:06 AM UTC 24 |
4187287800 ps |
| T2307 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/65.xbar_error_and_unmapped_addr.889504388 |
|
|
Aug 24 06:36:59 AM UTC 24 |
Aug 24 06:37:08 AM UTC 24 |
184544670 ps |
| T2308 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/65.xbar_unmapped_addr.1307867105 |
|
|
Aug 24 06:36:52 AM UTC 24 |
Aug 24 06:37:11 AM UTC 24 |
520361013 ps |
| T2309 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/65.xbar_same_source.1288846221 |
|
|
Aug 24 06:36:45 AM UTC 24 |
Aug 24 06:37:14 AM UTC 24 |
540594269 ps |
| T2310 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/65.xbar_access_same_device.1573055596 |
|
|
Aug 24 06:36:32 AM UTC 24 |
Aug 24 06:37:17 AM UTC 24 |
1375785973 ps |
| T2311 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/64.xbar_stress_all.2242146153 |
|
|
Aug 24 06:35:42 AM UTC 24 |
Aug 24 06:37:19 AM UTC 24 |
3421735098 ps |
| T2312 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/63.xbar_stress_all_with_reset_error.2327096198 |
|
|
Aug 24 06:34:25 AM UTC 24 |
Aug 24 06:37:20 AM UTC 24 |
1225081590 ps |
| T2313 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/65.xbar_smoke_large_delays.880112934 |
|
|
Aug 24 06:36:11 AM UTC 24 |
Aug 24 06:37:30 AM UTC 24 |
9547337571 ps |
| T2314 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/66.xbar_smoke.3182132355 |
|
|
Aug 24 06:37:25 AM UTC 24 |
Aug 24 06:37:32 AM UTC 24 |
141769260 ps |
| T2315 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/66.xbar_smoke_zero_delays.3661304508 |
|
|
Aug 24 06:37:29 AM UTC 24 |
Aug 24 06:37:35 AM UTC 24 |
40054571 ps |
| T2316 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/66.xbar_random_zero_delays.68683735 |
|
|
Aug 24 06:37:44 AM UTC 24 |
Aug 24 06:38:08 AM UTC 24 |
364175430 ps |
| T2317 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/57.xbar_random_large_delays.1834831733 |
|
|
Aug 24 06:24:00 AM UTC 24 |
Aug 24 06:38:14 AM UTC 24 |
106062282116 ps |
| T2318 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/66.xbar_smoke_large_delays.2857946239 |
|
|
Aug 24 06:37:31 AM UTC 24 |
Aug 24 06:38:28 AM UTC 24 |
6805171988 ps |
| T2319 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/66.xbar_random.2465753744 |
|
|
Aug 24 06:37:34 AM UTC 24 |
Aug 24 06:38:31 AM UTC 24 |
2088173853 ps |
| T2320 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/66.xbar_smoke_slow_rsp.78169756 |
|
|
Aug 24 06:37:33 AM UTC 24 |
Aug 24 06:38:31 AM UTC 24 |
4912641666 ps |
| T2321 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/65.xbar_stress_all_with_error.4262043509 |
|
|
Aug 24 06:37:20 AM UTC 24 |
Aug 24 06:38:43 AM UTC 24 |
3362437298 ps |
| T2322 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/66.xbar_random_large_delays.868546908 |
|
|
Aug 24 06:37:46 AM UTC 24 |
Aug 24 06:38:44 AM UTC 24 |
7049313360 ps |
| T2323 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/66.xbar_error_random.2162895075 |
|
|
Aug 24 06:38:45 AM UTC 24 |
Aug 24 06:38:54 AM UTC 24 |
90099412 ps |
| T2324 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/66.xbar_same_source.2533931678 |
|
|
Aug 24 06:38:42 AM UTC 24 |
Aug 24 06:38:54 AM UTC 24 |
386015078 ps |
| T2325 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/63.xbar_random_slow_rsp.4103434081 |
|
|
Aug 24 06:33:23 AM UTC 24 |
Aug 24 06:38:54 AM UTC 24 |
28803312315 ps |
| T2326 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/66.xbar_unmapped_addr.1113573006 |
|
|
Aug 24 06:38:45 AM UTC 24 |
Aug 24 06:39:04 AM UTC 24 |
520126422 ps |
| T2327 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/66.xbar_error_and_unmapped_addr.2043375705 |
|
|
Aug 24 06:38:56 AM UTC 24 |
Aug 24 06:39:10 AM UTC 24 |
136545478 ps |
| T2328 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/66.xbar_access_same_device.2604529170 |
|
|
Aug 24 06:38:22 AM UTC 24 |
Aug 24 06:39:18 AM UTC 24 |
1714216979 ps |
| T2329 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/58.xbar_random_large_delays.1080869128 |
|
|
Aug 24 06:25:32 AM UTC 24 |
Aug 24 06:39:19 AM UTC 24 |
97425152144 ps |
| T2330 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/66.xbar_stress_all_with_error.1792709496 |
|
|
Aug 24 06:39:09 AM UTC 24 |
Aug 24 06:39:20 AM UTC 24 |
135303544 ps |
| T2331 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/65.xbar_random_large_delays.2358162409 |
|
|
Aug 24 06:36:27 AM UTC 24 |
Aug 24 06:39:22 AM UTC 24 |
21143114511 ps |
| T2332 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/67.xbar_smoke.1699162473 |
|
|
Aug 24 06:39:19 AM UTC 24 |
Aug 24 06:39:25 AM UTC 24 |
53955813 ps |
| T2333 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/67.xbar_smoke_zero_delays.1314238785 |
|
|
Aug 24 06:39:25 AM UTC 24 |
Aug 24 06:39:30 AM UTC 24 |
43321375 ps |
| T2334 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/65.xbar_stress_all_with_reset_error.2117883697 |
|
|
Aug 24 06:37:22 AM UTC 24 |
Aug 24 06:39:38 AM UTC 24 |
1104727532 ps |
| T2335 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/65.xbar_stress_all_with_rand_reset.3028467786 |
|
|
Aug 24 06:37:16 AM UTC 24 |
Aug 24 06:39:55 AM UTC 24 |
363239946 ps |
| T2336 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/65.xbar_stress_all.50391191 |
|
|
Aug 24 06:37:11 AM UTC 24 |
Aug 24 06:39:58 AM UTC 24 |
6670573727 ps |
| T2337 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/67.xbar_random_zero_delays.4273602760 |
|
|
Aug 24 06:39:36 AM UTC 24 |
Aug 24 06:40:01 AM UTC 24 |
357628301 ps |
| T2338 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/67.xbar_access_same_device.2929877315 |
|
|
Aug 24 06:39:52 AM UTC 24 |
Aug 24 06:40:08 AM UTC 24 |
464731540 ps |
| T2339 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/67.xbar_smoke_slow_rsp.2172996137 |
|
|
Aug 24 06:39:34 AM UTC 24 |
Aug 24 06:40:11 AM UTC 24 |
2931603156 ps |
| T2340 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/67.xbar_random.3706912847 |
|
|
Aug 24 06:39:34 AM UTC 24 |
Aug 24 06:40:17 AM UTC 24 |
1690503951 ps |
| T2341 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/67.xbar_error_random.4078842180 |
|
|
Aug 24 06:40:15 AM UTC 24 |
Aug 24 06:40:33 AM UTC 24 |
276850360 ps |
| T2342 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/67.xbar_same_source.1223538180 |
|
|
Aug 24 06:40:12 AM UTC 24 |
Aug 24 06:40:33 AM UTC 24 |
852377645 ps |
| T2343 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/63.xbar_stress_all_with_error.1147134473 |
|
|
Aug 24 06:34:24 AM UTC 24 |
Aug 24 06:40:33 AM UTC 24 |
14835598831 ps |
| T2344 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/58.xbar_access_same_device_slow_rsp.3188444453 |
|
|
Aug 24 06:25:43 AM UTC 24 |
Aug 24 06:40:35 AM UTC 24 |
73089448129 ps |
| T2345 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/66.xbar_stress_all.2795160601 |
|
|
Aug 24 06:38:58 AM UTC 24 |
Aug 24 06:40:39 AM UTC 24 |
3710718961 ps |
| T2346 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/62.xbar_random_slow_rsp.1861943464 |
|
|
Aug 24 06:31:59 AM UTC 24 |
Aug 24 06:40:39 AM UTC 24 |
44294810856 ps |
| T2347 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/67.xbar_unmapped_addr.2555077293 |
|
|
Aug 24 06:40:22 AM UTC 24 |
Aug 24 06:40:40 AM UTC 24 |
189104496 ps |
| T2348 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/67.xbar_error_and_unmapped_addr.3487168747 |
|
|
Aug 24 06:40:25 AM UTC 24 |
Aug 24 06:40:44 AM UTC 24 |
205710876 ps |
| T2349 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/61.xbar_access_same_device_slow_rsp.558350726 |
|
|
Aug 24 06:30:29 AM UTC 24 |
Aug 24 06:40:54 AM UTC 24 |
52183641163 ps |
| T2350 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/64.xbar_stress_all_with_error.10445240 |
|
|
Aug 24 06:35:56 AM UTC 24 |
Aug 24 06:40:57 AM UTC 24 |
12162661311 ps |
| T2351 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/67.xbar_stress_all.283064176 |
|
|
Aug 24 06:40:30 AM UTC 24 |
Aug 24 06:40:57 AM UTC 24 |
438657721 ps |
| T2352 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/68.xbar_smoke.2961581276 |
|
|
Aug 24 06:40:50 AM UTC 24 |
Aug 24 06:40:58 AM UTC 24 |
231407710 ps |
| T2353 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/68.xbar_smoke_zero_delays.2618559619 |
|
|
Aug 24 06:40:53 AM UTC 24 |
Aug 24 06:40:59 AM UTC 24 |
43695739 ps |
| T2354 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/67.xbar_smoke_large_delays.3027001220 |
|
|
Aug 24 06:39:33 AM UTC 24 |
Aug 24 06:40:59 AM UTC 24 |
9911425199 ps |
| T2355 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/62.xbar_random_large_delays.3651901790 |
|
|
Aug 24 06:31:50 AM UTC 24 |
Aug 24 06:41:10 AM UTC 24 |
68061918201 ps |
| T2356 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/65.xbar_random_slow_rsp.1262084153 |
|
|
Aug 24 06:36:30 AM UTC 24 |
Aug 24 06:41:10 AM UTC 24 |
24567280556 ps |
| T2357 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/60.xbar_random_large_delays.2215643125 |
|
|
Aug 24 06:28:24 AM UTC 24 |
Aug 24 06:41:12 AM UTC 24 |
96542663894 ps |
| T2358 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/67.xbar_stress_all_with_error.3955797982 |
|
|
Aug 24 06:40:46 AM UTC 24 |
Aug 24 06:41:19 AM UTC 24 |
1153988607 ps |
| T2359 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/68.xbar_random_zero_delays.2696729528 |
|
|
Aug 24 06:41:09 AM UTC 24 |
Aug 24 06:41:21 AM UTC 24 |
157892935 ps |
| T2360 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/68.xbar_unmapped_addr.23592559 |
|
|
Aug 24 06:41:24 AM UTC 24 |
Aug 24 06:41:32 AM UTC 24 |
54295189 ps |
| T2361 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/68.xbar_same_source.817667575 |
|
|
Aug 24 06:41:13 AM UTC 24 |
Aug 24 06:41:37 AM UTC 24 |
991409154 ps |
| T848 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/67.xbar_stress_all_with_reset_error.1157330188 |
|
|
Aug 24 06:40:47 AM UTC 24 |
Aug 24 06:41:37 AM UTC 24 |
306067058 ps |
| T2362 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/68.xbar_access_same_device.2734061167 |
|
|
Aug 24 06:41:12 AM UTC 24 |
Aug 24 06:41:49 AM UTC 24 |
642824509 ps |
| T2363 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/68.xbar_smoke_slow_rsp.783504891 |
|
|
Aug 24 06:40:54 AM UTC 24 |
Aug 24 06:41:53 AM UTC 24 |
4769467731 ps |
| T2364 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/67.xbar_stress_all_with_rand_reset.2579633031 |
|
|
Aug 24 06:40:46 AM UTC 24 |
Aug 24 06:41:53 AM UTC 24 |
322300894 ps |
| T2365 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/68.xbar_error_random.2569897641 |
|
|
Aug 24 06:41:24 AM UTC 24 |
Aug 24 06:41:57 AM UTC 24 |
581779886 ps |
| T2366 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/69.xbar_smoke.2677379497 |
|
|
Aug 24 06:41:52 AM UTC 24 |
Aug 24 06:41:59 AM UTC 24 |
196578727 ps |
| T2367 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/68.xbar_random.3474548642 |
|
|
Aug 24 06:40:58 AM UTC 24 |
Aug 24 06:42:01 AM UTC 24 |
2385940302 ps |
| T2368 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/68.xbar_error_and_unmapped_addr.697582006 |
|
|
Aug 24 06:41:26 AM UTC 24 |
Aug 24 06:42:05 AM UTC 24 |
1362729591 ps |
| T2369 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/69.xbar_smoke_zero_delays.2141886440 |
|
|
Aug 24 06:42:03 AM UTC 24 |
Aug 24 06:42:09 AM UTC 24 |
41199577 ps |
| T2370 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/68.xbar_smoke_large_delays.974611443 |
|
|
Aug 24 06:40:54 AM UTC 24 |
Aug 24 06:42:10 AM UTC 24 |
8748590505 ps |
| T2371 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/69.xbar_random_zero_delays.4215730353 |
|
|
Aug 24 06:42:14 AM UTC 24 |
Aug 24 06:42:23 AM UTC 24 |
98406589 ps |
| T2372 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/69.xbar_random.2135616087 |
|
|
Aug 24 06:42:12 AM UTC 24 |
Aug 24 06:42:39 AM UTC 24 |
1056072523 ps |
| T2373 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/69.xbar_same_source.2847090944 |
|
|
Aug 24 06:42:38 AM UTC 24 |
Aug 24 06:42:47 AM UTC 24 |
291599432 ps |
| T2374 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/62.xbar_access_same_device_slow_rsp.2287987919 |
|
|
Aug 24 06:32:12 AM UTC 24 |
Aug 24 06:42:48 AM UTC 24 |
55038331593 ps |
| T2375 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/68.xbar_stress_all.1545403852 |
|
|
Aug 24 06:41:33 AM UTC 24 |
Aug 24 06:42:49 AM UTC 24 |
1119450435 ps |
| T2376 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/66.xbar_stress_all_with_rand_reset.3656517215 |
|
|
Aug 24 06:39:08 AM UTC 24 |
Aug 24 06:43:04 AM UTC 24 |
1102854351 ps |
| T2377 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/69.xbar_unmapped_addr.2209213805 |
|
|
Aug 24 06:43:01 AM UTC 24 |
Aug 24 06:43:19 AM UTC 24 |
179669275 ps |
| T2378 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/69.xbar_smoke_slow_rsp.1875490648 |
|
|
Aug 24 06:42:08 AM UTC 24 |
Aug 24 06:43:22 AM UTC 24 |
5878495961 ps |
| T2379 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/69.xbar_smoke_large_delays.2163513582 |
|
|
Aug 24 06:42:07 AM UTC 24 |
Aug 24 06:43:24 AM UTC 24 |
9408100300 ps |
| T2380 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/69.xbar_error_and_unmapped_addr.1320663185 |
|
|
Aug 24 06:43:02 AM UTC 24 |
Aug 24 06:43:24 AM UTC 24 |
694228335 ps |
| T2381 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/66.xbar_stress_all_with_reset_error.3927547072 |
|
|
Aug 24 06:39:08 AM UTC 24 |
Aug 24 06:43:26 AM UTC 24 |
2438141704 ps |
| T2382 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/69.xbar_access_same_device.2609822939 |
|
|
Aug 24 06:42:23 AM UTC 24 |
Aug 24 06:43:30 AM UTC 24 |
2209778029 ps |
| T2383 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/68.xbar_stress_all_with_reset_error.1574665615 |
|
|
Aug 24 06:41:52 AM UTC 24 |
Aug 24 06:43:33 AM UTC 24 |
3713893108 ps |
| T2384 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/70.xbar_smoke.2092996917 |
|
|
Aug 24 06:43:37 AM UTC 24 |
Aug 24 06:43:43 AM UTC 24 |
37349323 ps |
| T2385 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/70.xbar_smoke_zero_delays.834631605 |
|
|
Aug 24 06:43:39 AM UTC 24 |
Aug 24 06:43:45 AM UTC 24 |
48746044 ps |
| T2386 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/69.xbar_error_random.4065242917 |
|
|
Aug 24 06:42:53 AM UTC 24 |
Aug 24 06:43:45 AM UTC 24 |
2160079992 ps |
| T2387 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/70.xbar_random.2958164117 |
|
|
Aug 24 06:43:47 AM UTC 24 |
Aug 24 06:43:53 AM UTC 24 |
31266401 ps |
| T2388 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/70.xbar_random_zero_delays.109856364 |
|
|
Aug 24 06:43:57 AM UTC 24 |
Aug 24 06:44:11 AM UTC 24 |
186831926 ps |
| T2389 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/62.xbar_stress_all_with_rand_reset.3665158443 |
|
|
Aug 24 06:32:42 AM UTC 24 |
Aug 24 06:44:13 AM UTC 24 |
21953261954 ps |
| T2390 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/68.xbar_random_slow_rsp.2293196408 |
|
|
Aug 24 06:41:12 AM UTC 24 |
Aug 24 06:44:14 AM UTC 24 |
15488298966 ps |
| T2391 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/69.xbar_stress_all_with_reset_error.3725915762 |
|
|
Aug 24 06:43:36 AM UTC 24 |
Aug 24 06:44:16 AM UTC 24 |
170663410 ps |
| T2392 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/70.xbar_access_same_device.1223888611 |
|
|
Aug 24 06:44:07 AM UTC 24 |
Aug 24 06:44:21 AM UTC 24 |
236117628 ps |
| T2393 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/70.xbar_smoke_slow_rsp.4151098378 |
|
|
Aug 24 06:43:45 AM UTC 24 |
Aug 24 06:44:34 AM UTC 24 |
4056360295 ps |
| T2394 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/70.xbar_error_random.1368432643 |
|
|
Aug 24 06:44:28 AM UTC 24 |
Aug 24 06:44:41 AM UTC 24 |
151863084 ps |
| T2395 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/70.xbar_error_and_unmapped_addr.2165591044 |
|
|
Aug 24 06:44:35 AM UTC 24 |
Aug 24 06:44:41 AM UTC 24 |
54275097 ps |
| T2396 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/70.xbar_same_source.2367336150 |
|
|
Aug 24 06:44:27 AM UTC 24 |
Aug 24 06:44:44 AM UTC 24 |
691900330 ps |
| T2397 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/70.xbar_smoke_large_delays.2826197798 |
|
|
Aug 24 06:43:40 AM UTC 24 |
Aug 24 06:44:54 AM UTC 24 |
9195907337 ps |
| T2398 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/70.xbar_unmapped_addr.388192310 |
|
|
Aug 24 06:44:30 AM UTC 24 |
Aug 24 06:44:55 AM UTC 24 |
791719058 ps |
| T2399 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/69.xbar_stress_all_with_rand_reset.835843258 |
|
|
Aug 24 06:43:18 AM UTC 24 |
Aug 24 06:45:02 AM UTC 24 |
1735003488 ps |
| T2400 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/71.xbar_smoke_zero_delays.3370096963 |
|
|
Aug 24 06:45:10 AM UTC 24 |
Aug 24 06:45:16 AM UTC 24 |
43906735 ps |
| T2401 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/71.xbar_smoke.4284931845 |
|
|
Aug 24 06:45:08 AM UTC 24 |
Aug 24 06:45:16 AM UTC 24 |
244362460 ps |
| T2402 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/67.xbar_access_same_device_slow_rsp.3546418262 |
|
|
Aug 24 06:40:09 AM UTC 24 |
Aug 24 06:45:29 AM UTC 24 |
26288505734 ps |
| T2403 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/69.xbar_random_large_delays.204892437 |
|
|
Aug 24 06:42:15 AM UTC 24 |
Aug 24 06:45:37 AM UTC 24 |
24830046969 ps |
| T2404 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/68.xbar_stress_all_with_error.376759741 |
|
|
Aug 24 06:41:46 AM UTC 24 |
Aug 24 06:45:42 AM UTC 24 |
10031578420 ps |
| T2405 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/71.xbar_random.1555912212 |
|
|
Aug 24 06:45:31 AM UTC 24 |
Aug 24 06:45:49 AM UTC 24 |
685589184 ps |
| T2406 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/71.xbar_random_zero_delays.1157566162 |
|
|
Aug 24 06:45:43 AM UTC 24 |
Aug 24 06:45:53 AM UTC 24 |
116052224 ps |
| T2407 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/70.xbar_stress_all_with_error.2211459086 |
|
|
Aug 24 06:44:56 AM UTC 24 |
Aug 24 06:45:55 AM UTC 24 |
1061397519 ps |
| T2408 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/70.xbar_stress_all.3746404319 |
|
|
Aug 24 06:44:49 AM UTC 24 |
Aug 24 06:46:09 AM UTC 24 |
1579284265 ps |
| T2409 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/71.xbar_smoke_large_delays.462145273 |
|
|
Aug 24 06:45:16 AM UTC 24 |
Aug 24 06:46:15 AM UTC 24 |
7289318932 ps |
| T2410 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/71.xbar_smoke_slow_rsp.1977690128 |
|
|
Aug 24 06:45:30 AM UTC 24 |
Aug 24 06:46:21 AM UTC 24 |
3910934565 ps |
| T2411 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/64.xbar_stress_all_with_reset_error.3908497919 |
|
|
Aug 24 06:35:58 AM UTC 24 |
Aug 24 06:46:25 AM UTC 24 |
9929945805 ps |
| T2412 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/67.xbar_random_slow_rsp.306105835 |
|
|
Aug 24 06:39:45 AM UTC 24 |
Aug 24 06:46:25 AM UTC 24 |
34014118895 ps |
| T2413 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/69.xbar_stress_all_with_error.1049974550 |
|
|
Aug 24 06:43:32 AM UTC 24 |
Aug 24 06:46:31 AM UTC 24 |
6487356181 ps |
| T2414 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/71.xbar_same_source.3919730416 |
|
|
Aug 24 06:46:09 AM UTC 24 |
Aug 24 06:46:31 AM UTC 24 |
1006096220 ps |
| T2415 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/71.xbar_error_random.3194442302 |
|
|
Aug 24 06:46:23 AM UTC 24 |
Aug 24 06:46:35 AM UTC 24 |
164737944 ps |
| T2416 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/71.xbar_unmapped_addr.3738050290 |
|
|
Aug 24 06:46:29 AM UTC 24 |
Aug 24 06:46:36 AM UTC 24 |
71880822 ps |
| T2417 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/71.xbar_error_and_unmapped_addr.2247382158 |
|
|
Aug 24 06:46:34 AM UTC 24 |
Aug 24 06:46:42 AM UTC 24 |
137186106 ps |
| T2418 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/72.xbar_smoke.4246566043 |
|
|
Aug 24 06:46:49 AM UTC 24 |
Aug 24 06:46:55 AM UTC 24 |
53056566 ps |
| T2419 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/72.xbar_smoke_zero_delays.2112215231 |
|
|
Aug 24 06:46:50 AM UTC 24 |
Aug 24 06:46:56 AM UTC 24 |
54369572 ps |
| T2420 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/57.xbar_access_same_device_slow_rsp.2177396522 |
|
|
Aug 24 06:24:13 AM UTC 24 |
Aug 24 06:47:06 AM UTC 24 |
118841486991 ps |
| T2421 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/63.xbar_random_large_delays.129909678 |
|
|
Aug 24 06:33:19 AM UTC 24 |
Aug 24 06:47:26 AM UTC 24 |
99678149176 ps |
| T2422 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/69.xbar_stress_all.662251364 |
|
|
Aug 24 06:43:03 AM UTC 24 |
Aug 24 06:47:32 AM UTC 24 |
10915041644 ps |
| T2423 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/71.xbar_stress_all_with_error.1602868949 |
|
|
Aug 24 06:46:45 AM UTC 24 |
Aug 24 06:47:36 AM UTC 24 |
901217949 ps |
| T2424 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/70.xbar_stress_all_with_reset_error.3491306368 |
|
|
Aug 24 06:44:58 AM UTC 24 |
Aug 24 06:47:38 AM UTC 24 |
642153375 ps |
| T2425 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/72.xbar_random.992630154 |
|
|
Aug 24 06:47:10 AM UTC 24 |
Aug 24 06:47:39 AM UTC 24 |
1085790419 ps |
| T2426 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/72.xbar_random_zero_delays.3985501418 |
|
|
Aug 24 06:47:20 AM UTC 24 |
Aug 24 06:47:44 AM UTC 24 |
372038259 ps |
| T2427 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/71.xbar_access_same_device.4160961815 |
|
|
Aug 24 06:46:03 AM UTC 24 |
Aug 24 06:47:49 AM UTC 24 |
3978267081 ps |
| T2428 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/72.xbar_access_same_device.1183876422 |
|
|
Aug 24 06:47:50 AM UTC 24 |
Aug 24 06:47:58 AM UTC 24 |
145820334 ps |
| T2429 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/68.xbar_random_large_delays.1931231420 |
|
|
Aug 24 06:41:11 AM UTC 24 |
Aug 24 06:48:03 AM UTC 24 |
51193449869 ps |
| T2430 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/72.xbar_smoke_large_delays.2018801702 |
|
|
Aug 24 06:46:56 AM UTC 24 |
Aug 24 06:48:08 AM UTC 24 |
8827160458 ps |
| T2431 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/71.xbar_stress_all.437247597 |
|
|
Aug 24 06:46:39 AM UTC 24 |
Aug 24 06:48:09 AM UTC 24 |
1607514907 ps |
| T2432 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/72.xbar_unmapped_addr.3503788943 |
|
|
Aug 24 06:48:04 AM UTC 24 |
Aug 24 06:48:16 AM UTC 24 |
112495038 ps |
| T2433 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/71.xbar_stress_all_with_rand_reset.276046638 |
|
|
Aug 24 06:46:40 AM UTC 24 |
Aug 24 06:48:21 AM UTC 24 |
430163492 ps |
| T2434 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/72.xbar_error_random.3771259935 |
|
|
Aug 24 06:47:58 AM UTC 24 |
Aug 24 06:48:28 AM UTC 24 |
544280639 ps |
| T2435 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/72.xbar_smoke_slow_rsp.2043638341 |
|
|
Aug 24 06:47:09 AM UTC 24 |
Aug 24 06:48:31 AM UTC 24 |
6800022520 ps |
| T2436 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/72.xbar_same_source.4127101718 |
|
|
Aug 24 06:47:53 AM UTC 24 |
Aug 24 06:48:33 AM UTC 24 |
1885440818 ps |
| T2437 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/64.xbar_random_large_delays.2010671957 |
|
|
Aug 24 06:34:58 AM UTC 24 |
Aug 24 06:48:39 AM UTC 24 |
102633610521 ps |
| T2438 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/73.xbar_smoke.3387578468 |
|
|
Aug 24 06:48:35 AM UTC 24 |
Aug 24 06:48:43 AM UTC 24 |
196739041 ps |
| T2439 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/73.xbar_smoke_zero_delays.1528947668 |
|
|
Aug 24 06:48:43 AM UTC 24 |
Aug 24 06:48:49 AM UTC 24 |
44683062 ps |
| T2440 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/72.xbar_error_and_unmapped_addr.2121671830 |
|
|
Aug 24 06:48:12 AM UTC 24 |
Aug 24 06:48:51 AM UTC 24 |
1344546182 ps |
| T2441 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/71.xbar_stress_all_with_reset_error.2340243943 |
|
|
Aug 24 06:46:46 AM UTC 24 |
Aug 24 06:48:53 AM UTC 24 |
648923598 ps |
| T2442 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/66.xbar_random_slow_rsp.3055003973 |
|
|
Aug 24 06:37:49 AM UTC 24 |
Aug 24 06:48:58 AM UTC 24 |
58831820007 ps |
| T2443 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/72.xbar_stress_all.2064334925 |
|
|
Aug 24 06:48:17 AM UTC 24 |
Aug 24 06:48:59 AM UTC 24 |
604415238 ps |
| T2444 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/69.xbar_random_slow_rsp.796876506 |
|
|
Aug 24 06:42:19 AM UTC 24 |
Aug 24 06:49:00 AM UTC 24 |
33531966946 ps |
| T2445 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/73.xbar_random_zero_delays.112776961 |
|
|
Aug 24 06:48:57 AM UTC 24 |
Aug 24 06:49:07 AM UTC 24 |
93303364 ps |
| T2446 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/73.xbar_random.4218710013 |
|
|
Aug 24 06:48:53 AM UTC 24 |
Aug 24 06:49:09 AM UTC 24 |
214262355 ps |
| T2447 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/73.xbar_error_random.473728384 |
|
|
Aug 24 06:49:14 AM UTC 24 |
Aug 24 06:49:21 AM UTC 24 |
67996709 ps |
| T2448 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/73.xbar_same_source.2345681917 |
|
|
Aug 24 06:49:12 AM UTC 24 |
Aug 24 06:49:34 AM UTC 24 |
365313121 ps |
| T2449 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/73.xbar_error_and_unmapped_addr.1920486231 |
|
|
Aug 24 06:49:23 AM UTC 24 |
Aug 24 06:49:38 AM UTC 24 |
174097990 ps |
| T2450 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/73.xbar_smoke_slow_rsp.2723119942 |
|
|
Aug 24 06:48:47 AM UTC 24 |
Aug 24 06:49:48 AM UTC 24 |
5125746586 ps |
| T2451 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/86.xbar_smoke_large_delays.643270773 |
|
|
Aug 24 07:11:47 AM UTC 24 |
Aug 24 07:12:44 AM UTC 24 |
6999960842 ps |
| T2452 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/73.xbar_smoke_large_delays.1671527957 |
|
|
Aug 24 06:48:46 AM UTC 24 |
Aug 24 06:50:00 AM UTC 24 |
9295034942 ps |
| T2453 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/73.xbar_unmapped_addr.3300804588 |
|
|
Aug 24 06:49:21 AM UTC 24 |
Aug 24 06:50:05 AM UTC 24 |
1486372379 ps |
| T2454 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/74.xbar_smoke.1938268135 |
|
|
Aug 24 06:50:14 AM UTC 24 |
Aug 24 06:50:21 AM UTC 24 |
182451588 ps |
| T2455 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/74.xbar_smoke_zero_delays.921266462 |
|
|
Aug 24 06:50:19 AM UTC 24 |
Aug 24 06:50:25 AM UTC 24 |
47293304 ps |
| T2456 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/68.xbar_stress_all_with_rand_reset.1395160671 |
|
|
Aug 24 06:41:35 AM UTC 24 |
Aug 24 06:50:37 AM UTC 24 |
5533888887 ps |
| T2457 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/72.xbar_stress_all_with_rand_reset.3020718481 |
|
|
Aug 24 06:48:23 AM UTC 24 |
Aug 24 06:50:39 AM UTC 24 |
426434808 ps |
| T2458 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/73.xbar_access_same_device.870758426 |
|
|
Aug 24 06:49:06 AM UTC 24 |
Aug 24 06:50:40 AM UTC 24 |
3168154555 ps |
| T2459 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/72.xbar_stress_all_with_error.3830654884 |
|
|
Aug 24 06:48:24 AM UTC 24 |
Aug 24 06:50:44 AM UTC 24 |
2773132195 ps |
| T644 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/73.xbar_stress_all_with_error.3415452833 |
|
|
Aug 24 06:49:52 AM UTC 24 |
Aug 24 06:51:01 AM UTC 24 |
1317890951 ps |
| T2460 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/68.xbar_access_same_device_slow_rsp.2907281819 |
|
|
Aug 24 06:41:13 AM UTC 24 |
Aug 24 06:51:08 AM UTC 24 |
49837145413 ps |
| T849 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/73.xbar_stress_all_with_rand_reset.3562238852 |
|
|
Aug 24 06:49:48 AM UTC 24 |
Aug 24 06:51:16 AM UTC 24 |
1090904798 ps |
| T2461 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/74.xbar_random_zero_delays.3777163647 |
|
|
Aug 24 06:50:53 AM UTC 24 |
Aug 24 06:51:28 AM UTC 24 |
574549528 ps |
| T2462 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/74.xbar_random.4130112780 |
|
|
Aug 24 06:50:51 AM UTC 24 |
Aug 24 06:51:30 AM UTC 24 |
620479234 ps |
| T2463 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/70.xbar_random_slow_rsp.1575175938 |
|
|
Aug 24 06:43:59 AM UTC 24 |
Aug 24 06:51:33 AM UTC 24 |
36752299654 ps |
| T2464 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/74.xbar_smoke_slow_rsp.349033570 |
|
|
Aug 24 06:50:39 AM UTC 24 |
Aug 24 06:51:35 AM UTC 24 |
4715693985 ps |
| T2465 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/74.xbar_smoke_large_delays.13647953 |
|
|
Aug 24 06:50:36 AM UTC 24 |
Aug 24 06:51:50 AM UTC 24 |
9340278116 ps |
| T2466 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/74.xbar_error_random.4267829756 |
|
|
Aug 24 06:51:43 AM UTC 24 |
Aug 24 06:51:51 AM UTC 24 |
147127227 ps |
| T2467 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/74.xbar_same_source.2631377249 |
|
|
Aug 24 06:51:31 AM UTC 24 |
Aug 24 06:51:59 AM UTC 24 |
502103151 ps |
| T2468 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/74.xbar_unmapped_addr.10905633 |
|
|
Aug 24 06:51:45 AM UTC 24 |
Aug 24 06:52:03 AM UTC 24 |
179562022 ps |
| T2469 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/74.xbar_access_same_device.4287551499 |
|
|
Aug 24 06:51:14 AM UTC 24 |
Aug 24 06:52:16 AM UTC 24 |
2057258771 ps |
| T2470 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/75.xbar_smoke.4127298476 |
|
|
Aug 24 06:52:17 AM UTC 24 |
Aug 24 06:52:25 AM UTC 24 |
183633560 ps |
| T2471 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/74.xbar_error_and_unmapped_addr.2669535971 |
|
|
Aug 24 06:51:47 AM UTC 24 |
Aug 24 06:52:33 AM UTC 24 |
1429293403 ps |
| T2472 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/73.xbar_stress_all.2987940024 |
|
|
Aug 24 06:49:36 AM UTC 24 |
Aug 24 06:52:33 AM UTC 24 |
7688337772 ps |
| T2473 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/75.xbar_smoke_zero_delays.684639645 |
|
|
Aug 24 06:52:30 AM UTC 24 |
Aug 24 06:52:37 AM UTC 24 |
54234386 ps |
| T2474 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/75.xbar_random.1028548276 |
|
|
Aug 24 06:52:47 AM UTC 24 |
Aug 24 06:52:58 AM UTC 24 |
198540038 ps |
| T2475 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/75.xbar_random_zero_delays.402213002 |
|
|
Aug 24 06:52:51 AM UTC 24 |
Aug 24 06:53:10 AM UTC 24 |
254726785 ps |
| T2476 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/74.xbar_stress_all.85599054 |
|
|
Aug 24 06:51:50 AM UTC 24 |
Aug 24 06:53:13 AM UTC 24 |
3294980649 ps |
| T2477 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/75.xbar_smoke_slow_rsp.3217512887 |
|
|
Aug 24 06:52:47 AM UTC 24 |
Aug 24 06:53:21 AM UTC 24 |
2629699948 ps |
| T2478 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/74.xbar_stress_all_with_error.3071533122 |
|
|
Aug 24 06:52:05 AM UTC 24 |
Aug 24 06:53:27 AM UTC 24 |
3331947913 ps |
| T2479 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/73.xbar_random_large_delays.1458303923 |
|
|
Aug 24 06:49:03 AM UTC 24 |
Aug 24 06:53:43 AM UTC 24 |
33571547835 ps |
| T2480 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/75.xbar_access_same_device.4014062663 |
|
|
Aug 24 06:53:27 AM UTC 24 |
Aug 24 06:53:51 AM UTC 24 |
375027147 ps |
| T2481 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/71.xbar_random_slow_rsp.4096443016 |
|
|
Aug 24 06:45:56 AM UTC 24 |
Aug 24 06:53:54 AM UTC 24 |
40228051691 ps |
| T2482 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/74.xbar_random_slow_rsp.1402230053 |
|
|
Aug 24 06:50:58 AM UTC 24 |
Aug 24 06:54:00 AM UTC 24 |
15213144396 ps |
| T2483 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/75.xbar_smoke_large_delays.1588612579 |
|
|
Aug 24 06:52:39 AM UTC 24 |
Aug 24 06:54:04 AM UTC 24 |
10004634104 ps |
| T598 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/75.xbar_error_random.919250056 |
|
|
Aug 24 06:53:58 AM UTC 24 |
Aug 24 06:54:16 AM UTC 24 |
300222866 ps |
| T2484 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/75.xbar_same_source.4142472806 |
|
|
Aug 24 06:53:41 AM UTC 24 |
Aug 24 06:54:18 AM UTC 24 |
1825865167 ps |
| T2485 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/75.xbar_error_and_unmapped_addr.1599477710 |
|
|
Aug 24 06:54:08 AM UTC 24 |
Aug 24 06:54:19 AM UTC 24 |
265047397 ps |
| T2486 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/75.xbar_unmapped_addr.593351842 |
|
|
Aug 24 06:54:06 AM UTC 24 |
Aug 24 06:54:23 AM UTC 24 |
432031547 ps |
| T2487 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/76.xbar_smoke.2606969111 |
|
|
Aug 24 06:54:33 AM UTC 24 |
Aug 24 06:54:41 AM UTC 24 |
214906122 ps |
| T2488 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/76.xbar_smoke_zero_delays.4259771810 |
|
|
Aug 24 06:54:37 AM UTC 24 |
Aug 24 06:54:43 AM UTC 24 |
42077555 ps |
| T2489 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/63.xbar_access_same_device_slow_rsp.3151534131 |
|
|
Aug 24 06:33:55 AM UTC 24 |
Aug 24 06:55:11 AM UTC 24 |
111119792724 ps |
| T2490 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/75.xbar_stress_all_with_rand_reset.371627290 |
|
|
Aug 24 06:54:18 AM UTC 24 |
Aug 24 06:55:24 AM UTC 24 |
157737955 ps |
| T2491 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/70.xbar_stress_all_with_rand_reset.276664704 |
|
|
Aug 24 06:44:54 AM UTC 24 |
Aug 24 06:55:45 AM UTC 24 |
20906367436 ps |
| T2492 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/76.xbar_random.1327444323 |
|
|
Aug 24 06:55:25 AM UTC 24 |
Aug 24 06:55:48 AM UTC 24 |
766687380 ps |
| T2493 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/76.xbar_random_zero_delays.2406348135 |
|
|
Aug 24 06:55:38 AM UTC 24 |
Aug 24 06:55:52 AM UTC 24 |
170547972 ps |
| T2494 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/65.xbar_access_same_device_slow_rsp.1199833684 |
|
|
Aug 24 06:36:44 AM UTC 24 |
Aug 24 06:55:55 AM UTC 24 |
98567236742 ps |
| T600 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/74.xbar_stress_all_with_reset_error.3923029072 |
|
|
Aug 24 06:52:13 AM UTC 24 |
Aug 24 06:55:55 AM UTC 24 |
6764794456 ps |
| T2495 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/74.xbar_random_large_delays.1288707721 |
|
|
Aug 24 06:50:54 AM UTC 24 |
Aug 24 06:55:56 AM UTC 24 |
34153215187 ps |
| T2496 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/72.xbar_random_large_delays.3497155259 |
|
|
Aug 24 06:47:40 AM UTC 24 |
Aug 24 06:55:57 AM UTC 24 |
58182613109 ps |
| T2497 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/70.xbar_random_large_delays.1897148309 |
|
|
Aug 24 06:43:59 AM UTC 24 |
Aug 24 06:55:58 AM UTC 24 |
88413246841 ps |
| T2498 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/76.xbar_smoke_slow_rsp.3774464654 |
|
|
Aug 24 06:54:57 AM UTC 24 |
Aug 24 06:56:02 AM UTC 24 |
5412546175 ps |
| T2499 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/73.xbar_access_same_device_slow_rsp.2144904844 |
|
|
Aug 24 06:49:12 AM UTC 24 |
Aug 24 06:56:07 AM UTC 24 |
34086933496 ps |
| T2500 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/74.xbar_stress_all_with_rand_reset.3828642705 |
|
|
Aug 24 06:52:05 AM UTC 24 |
Aug 24 06:56:12 AM UTC 24 |
5602219138 ps |
| T2501 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/76.xbar_smoke_large_delays.1323083087 |
|
|
Aug 24 06:54:55 AM UTC 24 |
Aug 24 06:56:13 AM UTC 24 |
8862367938 ps |
| T2502 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/67.xbar_random_large_delays.2791950143 |
|
|
Aug 24 06:39:39 AM UTC 24 |
Aug 24 06:56:18 AM UTC 24 |
120314612546 ps |
| T2503 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/76.xbar_error_and_unmapped_addr.246116654 |
|
|
Aug 24 06:56:12 AM UTC 24 |
Aug 24 06:56:27 AM UTC 24 |
415006063 ps |
| T2504 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/76.xbar_unmapped_addr.1776813961 |
|
|
Aug 24 06:56:12 AM UTC 24 |
Aug 24 06:56:28 AM UTC 24 |
401307361 ps |
| T2505 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/76.xbar_error_random.3685424230 |
|
|
Aug 24 06:56:10 AM UTC 24 |
Aug 24 06:56:29 AM UTC 24 |
311662808 ps |
| T2506 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/76.xbar_same_source.3806225946 |
|
|
Aug 24 06:56:09 AM UTC 24 |
Aug 24 06:56:30 AM UTC 24 |
919727348 ps |
| T2507 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/64.xbar_access_same_device_slow_rsp.1155368445 |
|
|
Aug 24 06:35:22 AM UTC 24 |
Aug 24 06:56:33 AM UTC 24 |
108812179565 ps |
| T2508 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/75.xbar_stress_all.1083650372 |
|
|
Aug 24 06:54:14 AM UTC 24 |
Aug 24 06:56:39 AM UTC 24 |
5875535546 ps |
| T2509 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/77.xbar_smoke.3000385565 |
|
|
Aug 24 06:56:33 AM UTC 24 |
Aug 24 06:56:42 AM UTC 24 |
265512709 ps |
| T2510 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/77.xbar_smoke_zero_delays.2548128527 |
|
|
Aug 24 06:56:41 AM UTC 24 |
Aug 24 06:56:47 AM UTC 24 |
39563486 ps |
| T2511 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/72.xbar_stress_all_with_reset_error.1720268121 |
|
|
Aug 24 06:48:31 AM UTC 24 |
Aug 24 06:56:50 AM UTC 24 |
15644871241 ps |
| T2512 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/77.xbar_random.3525862967 |
|
|
Aug 24 06:56:44 AM UTC 24 |
Aug 24 06:57:00 AM UTC 24 |
224825294 ps |
| T2513 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/77.xbar_random_zero_delays.374247261 |
|
|
Aug 24 06:56:47 AM UTC 24 |
Aug 24 06:57:20 AM UTC 24 |
517342573 ps |
| T2514 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/76.xbar_access_same_device.1449921633 |
|
|
Aug 24 06:56:06 AM UTC 24 |
Aug 24 06:57:23 AM UTC 24 |
2284829794 ps |