| T1571 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/23.xbar_smoke.1395946739 |
|
|
Aug 24 05:17:48 AM UTC 24 |
Aug 24 05:17:56 AM UTC 24 |
198474919 ps |
| T1572 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/22.xbar_same_source.3306233791 |
|
|
Aug 24 05:16:08 AM UTC 24 |
Aug 24 05:16:17 AM UTC 24 |
78995010 ps |
| T1573 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/22.xbar_access_same_device.2897434665 |
|
|
Aug 24 05:15:29 AM UTC 24 |
Aug 24 05:16:17 AM UTC 24 |
749710270 ps |
| T1574 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/22.xbar_smoke_large_delays.4059355286 |
|
|
Aug 24 05:14:59 AM UTC 24 |
Aug 24 05:16:19 AM UTC 24 |
9754877675 ps |
| T1575 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/22.xbar_smoke_slow_rsp.2906734483 |
|
|
Aug 24 05:15:02 AM UTC 24 |
Aug 24 05:16:35 AM UTC 24 |
7832994464 ps |
| T1576 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/22.xbar_error_random.1013729076 |
|
|
Aug 24 05:16:13 AM UTC 24 |
Aug 24 05:16:47 AM UTC 24 |
1347391507 ps |
| T1577 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/22.xbar_error_and_unmapped_addr.2109959829 |
|
|
Aug 24 05:16:31 AM UTC 24 |
Aug 24 05:16:48 AM UTC 24 |
510297241 ps |
| T500 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/22.xbar_unmapped_addr.1145059185 |
|
|
Aug 24 05:16:31 AM UTC 24 |
Aug 24 05:17:18 AM UTC 24 |
1506466308 ps |
| T1578 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/19.chip_csr_mem_rw_with_rand_reset.3555287538 |
|
|
Aug 24 05:07:45 AM UTC 24 |
Aug 24 05:17:33 AM UTC 24 |
8310723498 ps |
| T1579 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/21.xbar_stress_all_with_error.1993712122 |
|
|
Aug 24 05:14:33 AM UTC 24 |
Aug 24 05:17:35 AM UTC 24 |
7310385743 ps |
| T1580 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/10.chip_same_csr_outstanding.1740302673 |
|
|
Aug 24 04:28:05 AM UTC 24 |
Aug 24 05:17:48 AM UTC 24 |
31207165142 ps |
| T1581 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/23.xbar_smoke_zero_delays.3408338145 |
|
|
Aug 24 05:17:50 AM UTC 24 |
Aug 24 05:17:56 AM UTC 24 |
53076748 ps |
| T1582 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/18.chip_same_csr_outstanding.1646046693 |
|
|
Aug 24 05:01:31 AM UTC 24 |
Aug 24 05:18:14 AM UTC 24 |
14766173387 ps |
| T1583 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/23.xbar_random.1604117858 |
|
|
Aug 24 05:18:11 AM UTC 24 |
Aug 24 05:18:19 AM UTC 24 |
65831213 ps |
| T829 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/19.xbar_access_same_device_slow_rsp.2901292923 |
|
|
Aug 24 05:06:46 AM UTC 24 |
Aug 24 05:18:21 AM UTC 24 |
56676472276 ps |
| T496 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/21.xbar_stress_all.3128841474 |
|
|
Aug 24 05:14:02 AM UTC 24 |
Aug 24 05:18:38 AM UTC 24 |
9898251541 ps |
| T1584 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/23.xbar_random_zero_delays.453805179 |
|
|
Aug 24 05:18:28 AM UTC 24 |
Aug 24 05:18:39 AM UTC 24 |
118507687 ps |
| T1585 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/21.xbar_random_slow_rsp.781737466 |
|
|
Aug 24 05:12:55 AM UTC 24 |
Aug 24 05:18:39 AM UTC 24 |
27823394918 ps |
| T637 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/22.chip_tl_errors.2903657465 |
|
|
Aug 24 05:14:46 AM UTC 24 |
Aug 24 05:19:03 AM UTC 24 |
4376826770 ps |
| T1586 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/23.xbar_same_source.357984303 |
|
|
Aug 24 05:18:53 AM UTC 24 |
Aug 24 05:19:07 AM UTC 24 |
186872337 ps |
| T511 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/17.xbar_access_same_device_slow_rsp.48213435 |
|
|
Aug 24 04:58:44 AM UTC 24 |
Aug 24 05:19:11 AM UTC 24 |
103807552623 ps |
| T1587 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/23.xbar_smoke_slow_rsp.1276782786 |
|
|
Aug 24 05:18:10 AM UTC 24 |
Aug 24 05:19:18 AM UTC 24 |
5713507844 ps |
| T1588 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/23.xbar_smoke_large_delays.1159166059 |
|
|
Aug 24 05:18:03 AM UTC 24 |
Aug 24 05:19:20 AM UTC 24 |
9504427551 ps |
| T1589 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/22.xbar_random_large_delays.716922106 |
|
|
Aug 24 05:15:18 AM UTC 24 |
Aug 24 05:19:30 AM UTC 24 |
28159986226 ps |
| T1590 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/23.xbar_error_and_unmapped_addr.3830826278 |
|
|
Aug 24 05:19:26 AM UTC 24 |
Aug 24 05:19:31 AM UTC 24 |
20955088 ps |
| T634 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/23.chip_tl_errors.1150101392 |
|
|
Aug 24 05:17:32 AM UTC 24 |
Aug 24 05:19:32 AM UTC 24 |
3435196104 ps |
| T1591 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/23.xbar_access_same_device.240144733 |
|
|
Aug 24 05:18:52 AM UTC 24 |
Aug 24 05:19:33 AM UTC 24 |
645535718 ps |
| T1592 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/23.xbar_error_random.2125742229 |
|
|
Aug 24 05:19:17 AM UTC 24 |
Aug 24 05:19:39 AM UTC 24 |
374041831 ps |
| T1593 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/23.xbar_unmapped_addr.4260659423 |
|
|
Aug 24 05:19:21 AM UTC 24 |
Aug 24 05:19:40 AM UTC 24 |
577174441 ps |
| T1594 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/24.xbar_smoke.2717896042 |
|
|
Aug 24 05:19:47 AM UTC 24 |
Aug 24 05:19:54 AM UTC 24 |
190814219 ps |
| T1595 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/24.xbar_smoke_zero_delays.3190381163 |
|
|
Aug 24 05:19:53 AM UTC 24 |
Aug 24 05:19:59 AM UTC 24 |
48372632 ps |
| T839 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/23.xbar_stress_all_with_rand_reset.3439165428 |
|
|
Aug 24 05:19:34 AM UTC 24 |
Aug 24 05:20:08 AM UTC 24 |
164286848 ps |
| T1596 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/23.xbar_stress_all_with_error.1133720022 |
|
|
Aug 24 05:19:44 AM UTC 24 |
Aug 24 05:20:20 AM UTC 24 |
1154091356 ps |
| T1597 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/24.xbar_random.3669058479 |
|
|
Aug 24 05:20:13 AM UTC 24 |
Aug 24 05:20:38 AM UTC 24 |
807211286 ps |
| T535 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/24.xbar_random_zero_delays.1457934547 |
|
|
Aug 24 05:20:22 AM UTC 24 |
Aug 24 05:20:57 AM UTC 24 |
563049065 ps |
| T1598 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/24.xbar_smoke_slow_rsp.2193206655 |
|
|
Aug 24 05:20:09 AM UTC 24 |
Aug 24 05:20:58 AM UTC 24 |
4018772021 ps |
| T1599 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/24.xbar_smoke_large_delays.1286878436 |
|
|
Aug 24 05:19:54 AM UTC 24 |
Aug 24 05:21:04 AM UTC 24 |
8096042682 ps |
| T792 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/15.xbar_access_same_device_slow_rsp.59893241 |
|
|
Aug 24 04:50:18 AM UTC 24 |
Aug 24 05:21:05 AM UTC 24 |
160840015194 ps |
| T1600 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/21.xbar_random_large_delays.3191714573 |
|
|
Aug 24 05:12:48 AM UTC 24 |
Aug 24 05:21:08 AM UTC 24 |
59157702447 ps |
| T1601 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/22.xbar_stress_all_with_error.2493436406 |
|
|
Aug 24 05:17:01 AM UTC 24 |
Aug 24 05:21:13 AM UTC 24 |
9881624597 ps |
| T1602 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/23.xbar_random_slow_rsp.3206481140 |
|
|
Aug 24 05:18:35 AM UTC 24 |
Aug 24 05:21:29 AM UTC 24 |
15178460817 ps |
| T1603 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/24.xbar_error_random.4021775368 |
|
|
Aug 24 05:21:20 AM UTC 24 |
Aug 24 05:21:32 AM UTC 24 |
138626106 ps |
| T1604 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/24.xbar_error_and_unmapped_addr.3823949737 |
|
|
Aug 24 05:21:27 AM UTC 24 |
Aug 24 05:21:33 AM UTC 24 |
19376220 ps |
| T1605 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/24.xbar_unmapped_addr.2885207520 |
|
|
Aug 24 05:21:22 AM UTC 24 |
Aug 24 05:21:33 AM UTC 24 |
260468506 ps |
| T1606 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/24.xbar_access_same_device.1700444045 |
|
|
Aug 24 05:21:11 AM UTC 24 |
Aug 24 05:21:38 AM UTC 24 |
777889790 ps |
| T1607 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/23.xbar_stress_all_with_reset_error.44025914 |
|
|
Aug 24 05:19:46 AM UTC 24 |
Aug 24 05:21:39 AM UTC 24 |
389977169 ps |
| T1608 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/25.xbar_smoke.1023799570 |
|
|
Aug 24 05:21:54 AM UTC 24 |
Aug 24 05:22:00 AM UTC 24 |
50703414 ps |
| T1609 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/20.xbar_random_large_delays.679517816 |
|
|
Aug 24 05:09:15 AM UTC 24 |
Aug 24 05:22:02 AM UTC 24 |
92991279299 ps |
| T1610 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/24.xbar_same_source.503657475 |
|
|
Aug 24 05:21:19 AM UTC 24 |
Aug 24 05:22:11 AM UTC 24 |
2455855820 ps |
| T1611 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/25.xbar_smoke_zero_delays.3760945293 |
|
|
Aug 24 05:22:15 AM UTC 24 |
Aug 24 05:22:21 AM UTC 24 |
45428396 ps |
| T1612 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/22.xbar_stress_all.1162085906 |
|
|
Aug 24 05:16:33 AM UTC 24 |
Aug 24 05:22:33 AM UTC 24 |
14261759224 ps |
| T834 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/22.xbar_stress_all_with_rand_reset.55528403 |
|
|
Aug 24 05:16:49 AM UTC 24 |
Aug 24 05:22:47 AM UTC 24 |
1874652235 ps |
| T1613 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/25.xbar_random.2262641234 |
|
|
Aug 24 05:22:35 AM UTC 24 |
Aug 24 05:22:51 AM UTC 24 |
511625179 ps |
| T1614 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/25.xbar_smoke_large_delays.1070375280 |
|
|
Aug 24 05:22:16 AM UTC 24 |
Aug 24 05:23:02 AM UTC 24 |
5373721284 ps |
| T650 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/24.chip_tl_errors.614111280 |
|
|
Aug 24 05:19:46 AM UTC 24 |
Aug 24 05:23:17 AM UTC 24 |
3688285006 ps |
| T1615 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/25.xbar_smoke_slow_rsp.1280312283 |
|
|
Aug 24 05:22:26 AM UTC 24 |
Aug 24 05:23:23 AM UTC 24 |
4622196524 ps |
| T512 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/25.xbar_random_zero_delays.726706160 |
|
|
Aug 24 05:22:47 AM UTC 24 |
Aug 24 05:23:27 AM UTC 24 |
608011524 ps |
| T516 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/23.xbar_stress_all.1404477203 |
|
|
Aug 24 05:19:32 AM UTC 24 |
Aug 24 05:23:53 AM UTC 24 |
9821785957 ps |
| T797 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/22.xbar_stress_all_with_reset_error.324713962 |
|
|
Aug 24 05:17:02 AM UTC 24 |
Aug 24 05:24:00 AM UTC 24 |
9765094841 ps |
| T527 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/25.xbar_same_source.4260187040 |
|
|
Aug 24 05:23:37 AM UTC 24 |
Aug 24 05:24:02 AM UTC 24 |
415225332 ps |
| T1616 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/25.xbar_access_same_device.182757044 |
|
|
Aug 24 05:23:17 AM UTC 24 |
Aug 24 05:24:10 AM UTC 24 |
1737679692 ps |
| T606 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/25.xbar_error_random.2056477398 |
|
|
Aug 24 05:23:42 AM UTC 24 |
Aug 24 05:24:32 AM UTC 24 |
2167254554 ps |
| T1617 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/25.xbar_unmapped_addr.1705954773 |
|
|
Aug 24 05:24:07 AM UTC 24 |
Aug 24 05:24:36 AM UTC 24 |
306049352 ps |
| T1618 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/25.xbar_error_and_unmapped_addr.3544363286 |
|
|
Aug 24 05:24:14 AM UTC 24 |
Aug 24 05:24:44 AM UTC 24 |
1039130901 ps |
| T1619 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/25.chip_tl_errors.60661371 |
|
|
Aug 24 05:21:52 AM UTC 24 |
Aug 24 05:25:13 AM UTC 24 |
4078989752 ps |
| T1620 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/12.chip_same_csr_outstanding.2159204894 |
|
|
Aug 24 04:36:34 AM UTC 24 |
Aug 24 05:25:22 AM UTC 24 |
29584249088 ps |
| T842 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/24.xbar_stress_all_with_rand_reset.3939982260 |
|
|
Aug 24 05:21:46 AM UTC 24 |
Aug 24 05:25:25 AM UTC 24 |
729981991 ps |
| T1621 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/26.xbar_smoke.3351352059 |
|
|
Aug 24 05:25:27 AM UTC 24 |
Aug 24 05:25:34 AM UTC 24 |
134777069 ps |
| T1622 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/26.xbar_smoke_zero_delays.228849982 |
|
|
Aug 24 05:25:36 AM UTC 24 |
Aug 24 05:25:42 AM UTC 24 |
49061528 ps |
| T830 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/22.xbar_access_same_device_slow_rsp.4282879970 |
|
|
Aug 24 05:16:00 AM UTC 24 |
Aug 24 05:25:56 AM UTC 24 |
48388567428 ps |
| T835 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/25.xbar_stress_all_with_reset_error.3930966251 |
|
|
Aug 24 05:24:50 AM UTC 24 |
Aug 24 05:26:13 AM UTC 24 |
328591163 ps |
| T1623 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/23.xbar_random_large_delays.3404373279 |
|
|
Aug 24 05:18:33 AM UTC 24 |
Aug 24 05:26:19 AM UTC 24 |
57316738801 ps |
| T1624 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/26.xbar_random_zero_delays.497580318 |
|
|
Aug 24 05:26:11 AM UTC 24 |
Aug 24 05:26:22 AM UTC 24 |
131037766 ps |
| T505 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/26.xbar_random.429359164 |
|
|
Aug 24 05:25:56 AM UTC 24 |
Aug 24 05:26:26 AM UTC 24 |
465455795 ps |
| T1625 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/26.xbar_smoke_slow_rsp.1933258925 |
|
|
Aug 24 05:25:49 AM UTC 24 |
Aug 24 05:26:47 AM UTC 24 |
4883194435 ps |
| T1626 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/24.xbar_random_large_delays.785251492 |
|
|
Aug 24 05:20:34 AM UTC 24 |
Aug 24 05:26:50 AM UTC 24 |
44720053408 ps |
| T1627 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/25.xbar_stress_all.3700375100 |
|
|
Aug 24 05:24:17 AM UTC 24 |
Aug 24 05:26:55 AM UTC 24 |
5466887188 ps |
| T506 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/24.xbar_stress_all.190040860 |
|
|
Aug 24 05:21:42 AM UTC 24 |
Aug 24 05:27:00 AM UTC 24 |
11096839558 ps |
| T1628 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/26.xbar_smoke_large_delays.2279623560 |
|
|
Aug 24 05:25:40 AM UTC 24 |
Aug 24 05:27:06 AM UTC 24 |
10503968866 ps |
| T1629 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/26.xbar_unmapped_addr.121834206 |
|
|
Aug 24 05:27:09 AM UTC 24 |
Aug 24 05:27:15 AM UTC 24 |
65925207 ps |
| T819 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/24.xbar_stress_all_with_error.424624203 |
|
|
Aug 24 05:21:47 AM UTC 24 |
Aug 24 05:27:16 AM UTC 24 |
12203819406 ps |
| T1630 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/26.xbar_same_source.619908982 |
|
|
Aug 24 05:27:02 AM UTC 24 |
Aug 24 05:27:21 AM UTC 24 |
767594845 ps |
| T1631 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/26.xbar_error_random.770823746 |
|
|
Aug 24 05:27:04 AM UTC 24 |
Aug 24 05:27:34 AM UTC 24 |
1193368082 ps |
| T1632 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/22.xbar_random_slow_rsp.667925017 |
|
|
Aug 24 05:15:21 AM UTC 24 |
Aug 24 05:27:35 AM UTC 24 |
63504663699 ps |
| T1633 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/24.xbar_random_slow_rsp.2701093954 |
|
|
Aug 24 05:20:52 AM UTC 24 |
Aug 24 05:27:49 AM UTC 24 |
35152460523 ps |
| T1634 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/26.xbar_error_and_unmapped_addr.913193670 |
|
|
Aug 24 05:27:14 AM UTC 24 |
Aug 24 05:27:52 AM UTC 24 |
1263660808 ps |
| T1635 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/27.xbar_smoke.4080226300 |
|
|
Aug 24 05:27:48 AM UTC 24 |
Aug 24 05:27:57 AM UTC 24 |
221302965 ps |
| T1636 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/25.xbar_random_large_delays.2193054111 |
|
|
Aug 24 05:23:02 AM UTC 24 |
Aug 24 05:27:57 AM UTC 24 |
36659646562 ps |
| T1637 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/25.xbar_random_slow_rsp.4114825163 |
|
|
Aug 24 05:23:05 AM UTC 24 |
Aug 24 05:27:58 AM UTC 24 |
23449443326 ps |
| T1638 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/27.xbar_smoke_zero_delays.4175731661 |
|
|
Aug 24 05:28:04 AM UTC 24 |
Aug 24 05:28:10 AM UTC 24 |
50488017 ps |
| T1639 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/27.xbar_random.2142821904 |
|
|
Aug 24 05:28:11 AM UTC 24 |
Aug 24 05:28:22 AM UTC 24 |
301529338 ps |
| T1640 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/26.xbar_access_same_device.3524706324 |
|
|
Aug 24 05:26:37 AM UTC 24 |
Aug 24 05:28:24 AM UTC 24 |
3514350267 ps |
| T1641 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/27.xbar_random_zero_delays.2839178628 |
|
|
Aug 24 05:28:12 AM UTC 24 |
Aug 24 05:28:30 AM UTC 24 |
234163546 ps |
| T1642 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/25.xbar_stress_all_with_error.3334631150 |
|
|
Aug 24 05:24:47 AM UTC 24 |
Aug 24 05:28:35 AM UTC 24 |
7922227078 ps |
| T1643 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/26.chip_tl_errors.1404076536 |
|
|
Aug 24 05:24:58 AM UTC 24 |
Aug 24 05:28:38 AM UTC 24 |
4734228496 ps |
| T1644 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/23.xbar_access_same_device_slow_rsp.287568497 |
|
|
Aug 24 05:18:53 AM UTC 24 |
Aug 24 05:28:41 AM UTC 24 |
51347102463 ps |
| T1645 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/18.xbar_access_same_device_slow_rsp.3987524018 |
|
|
Aug 24 05:03:18 AM UTC 24 |
Aug 24 05:28:47 AM UTC 24 |
127451111765 ps |
| T793 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/20.xbar_access_same_device_slow_rsp.3590807141 |
|
|
Aug 24 05:09:47 AM UTC 24 |
Aug 24 05:29:04 AM UTC 24 |
100707171825 ps |
| T502 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/27.xbar_access_same_device.2522390615 |
|
|
Aug 24 05:28:39 AM UTC 24 |
Aug 24 05:29:05 AM UTC 24 |
411897007 ps |
| T1646 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/27.xbar_error_and_unmapped_addr.420121235 |
|
|
Aug 24 05:29:01 AM UTC 24 |
Aug 24 05:29:17 AM UTC 24 |
165627028 ps |
| T1647 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/27.xbar_smoke_slow_rsp.130906140 |
|
|
Aug 24 05:28:11 AM UTC 24 |
Aug 24 05:29:20 AM UTC 24 |
5741736169 ps |
| T1648 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/27.xbar_error_random.2090667717 |
|
|
Aug 24 05:28:53 AM UTC 24 |
Aug 24 05:29:21 AM UTC 24 |
449890990 ps |
| T1649 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/27.xbar_smoke_large_delays.3545729881 |
|
|
Aug 24 05:28:07 AM UTC 24 |
Aug 24 05:29:28 AM UTC 24 |
9382591397 ps |
| T1650 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/27.xbar_unmapped_addr.2010533088 |
|
|
Aug 24 05:28:56 AM UTC 24 |
Aug 24 05:29:39 AM UTC 24 |
1326731524 ps |
| T1651 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/27.xbar_same_source.3728903453 |
|
|
Aug 24 05:28:50 AM UTC 24 |
Aug 24 05:29:44 AM UTC 24 |
2366919077 ps |
| T1652 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/28.xbar_smoke.500965579 |
|
|
Aug 24 05:29:42 AM UTC 24 |
Aug 24 05:29:49 AM UTC 24 |
46423943 ps |
| T1653 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/28.xbar_smoke_zero_delays.613041751 |
|
|
Aug 24 05:29:53 AM UTC 24 |
Aug 24 05:29:59 AM UTC 24 |
49155651 ps |
| T1654 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/27.xbar_stress_all_with_reset_error.4037668352 |
|
|
Aug 24 05:29:34 AM UTC 24 |
Aug 24 05:30:00 AM UTC 24 |
55003595 ps |
| T1655 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/27.xbar_stress_all.2432147271 |
|
|
Aug 24 05:29:19 AM UTC 24 |
Aug 24 05:30:08 AM UTC 24 |
734208498 ps |
| T1656 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/27.chip_tl_errors.3968172459 |
|
|
Aug 24 05:27:48 AM UTC 24 |
Aug 24 05:30:26 AM UTC 24 |
3757513850 ps |
| T1657 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/28.xbar_random_zero_delays.928261320 |
|
|
Aug 24 05:30:13 AM UTC 24 |
Aug 24 05:30:27 AM UTC 24 |
172619729 ps |
| T517 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/25.xbar_stress_all_with_rand_reset.2659859961 |
|
|
Aug 24 05:24:24 AM UTC 24 |
Aug 24 05:30:39 AM UTC 24 |
5909147948 ps |
| T514 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/26.xbar_stress_all.3018570893 |
|
|
Aug 24 05:27:20 AM UTC 24 |
Aug 24 05:30:43 AM UTC 24 |
3372995487 ps |
| T1658 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/26.xbar_stress_all_with_error.1584523669 |
|
|
Aug 24 05:27:30 AM UTC 24 |
Aug 24 05:30:50 AM UTC 24 |
7851017295 ps |
| T528 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/28.xbar_random.1899320684 |
|
|
Aug 24 05:30:13 AM UTC 24 |
Aug 24 05:30:56 AM UTC 24 |
1585039499 ps |
| T1659 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/28.xbar_smoke_large_delays.423844504 |
|
|
Aug 24 05:29:58 AM UTC 24 |
Aug 24 05:31:02 AM UTC 24 |
7404143728 ps |
| T1660 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/28.xbar_smoke_slow_rsp.3784411420 |
|
|
Aug 24 05:30:03 AM UTC 24 |
Aug 24 05:31:04 AM UTC 24 |
5108590860 ps |
| T1661 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/28.xbar_random_large_delays.606410920 |
|
|
Aug 24 05:30:23 AM UTC 24 |
Aug 24 05:31:24 AM UTC 24 |
6801806003 ps |
| T840 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/24.xbar_stress_all_with_reset_error.2816871109 |
|
|
Aug 24 05:21:47 AM UTC 24 |
Aug 24 05:31:29 AM UTC 24 |
16154368208 ps |
| T1662 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/28.xbar_error_random.2998675747 |
|
|
Aug 24 05:31:05 AM UTC 24 |
Aug 24 05:31:32 AM UTC 24 |
441598476 ps |
| T1663 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/28.xbar_error_and_unmapped_addr.3501929717 |
|
|
Aug 24 05:31:16 AM UTC 24 |
Aug 24 05:31:36 AM UTC 24 |
217304111 ps |
| T1664 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/28.xbar_same_source.731202956 |
|
|
Aug 24 05:30:57 AM UTC 24 |
Aug 24 05:31:42 AM UTC 24 |
1986376720 ps |
| T1665 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/28.xbar_unmapped_addr.3946128141 |
|
|
Aug 24 05:31:11 AM UTC 24 |
Aug 24 05:31:55 AM UTC 24 |
1414385346 ps |
| T1666 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/28.xbar_access_same_device.3569671136 |
|
|
Aug 24 05:30:42 AM UTC 24 |
Aug 24 05:31:58 AM UTC 24 |
2218293912 ps |
| T1667 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/28.xbar_stress_all.4064146254 |
|
|
Aug 24 05:31:19 AM UTC 24 |
Aug 24 05:32:00 AM UTC 24 |
601904765 ps |
| T851 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/26.xbar_stress_all_with_reset_error.3802880264 |
|
|
Aug 24 05:27:35 AM UTC 24 |
Aug 24 05:32:02 AM UTC 24 |
2190354910 ps |
| T1668 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/29.xbar_smoke.357731685 |
|
|
Aug 24 05:31:57 AM UTC 24 |
Aug 24 05:32:05 AM UTC 24 |
187878871 ps |
| T1669 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/28.xbar_stress_all_with_rand_reset.1052188168 |
|
|
Aug 24 05:31:38 AM UTC 24 |
Aug 24 05:32:09 AM UTC 24 |
115216209 ps |
| T1670 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/28.xbar_random_slow_rsp.4167125595 |
|
|
Aug 24 05:30:40 AM UTC 24 |
Aug 24 05:32:12 AM UTC 24 |
7225880071 ps |
| T1671 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/29.xbar_smoke_zero_delays.1619811833 |
|
|
Aug 24 05:32:10 AM UTC 24 |
Aug 24 05:32:16 AM UTC 24 |
51811334 ps |
| T1672 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/28.chip_tl_errors.579150548 |
|
|
Aug 24 05:29:35 AM UTC 24 |
Aug 24 05:32:30 AM UTC 24 |
3576250850 ps |
| T1673 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/15.chip_same_csr_outstanding.256940926 |
|
|
Aug 24 04:48:25 AM UTC 24 |
Aug 24 05:32:31 AM UTC 24 |
31220738855 ps |
| T1674 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/26.xbar_stress_all_with_rand_reset.1886987830 |
|
|
Aug 24 05:27:29 AM UTC 24 |
Aug 24 05:32:33 AM UTC 24 |
2250847133 ps |
| T1675 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/29.xbar_random_zero_delays.1397179843 |
|
|
Aug 24 05:32:19 AM UTC 24 |
Aug 24 05:32:38 AM UTC 24 |
236301216 ps |
| T1676 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/29.xbar_random.3638901239 |
|
|
Aug 24 05:32:17 AM UTC 24 |
Aug 24 05:32:51 AM UTC 24 |
562765239 ps |
| T1677 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/28.xbar_stress_all_with_reset_error.413773849 |
|
|
Aug 24 05:31:46 AM UTC 24 |
Aug 24 05:32:55 AM UTC 24 |
258242583 ps |
| T1678 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/29.xbar_access_same_device.2011458790 |
|
|
Aug 24 05:32:30 AM UTC 24 |
Aug 24 05:33:04 AM UTC 24 |
594287798 ps |
| T1679 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/29.xbar_unmapped_addr.2580110186 |
|
|
Aug 24 05:32:52 AM UTC 24 |
Aug 24 05:33:05 AM UTC 24 |
299874923 ps |
| T1680 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/29.xbar_error_random.2359074293 |
|
|
Aug 24 05:32:48 AM UTC 24 |
Aug 24 05:33:06 AM UTC 24 |
568184293 ps |
| T1681 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/29.xbar_smoke_large_delays.1684267677 |
|
|
Aug 24 05:32:13 AM UTC 24 |
Aug 24 05:33:07 AM UTC 24 |
6489612225 ps |
| T1682 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/29.xbar_smoke_slow_rsp.2919649846 |
|
|
Aug 24 05:32:14 AM UTC 24 |
Aug 24 05:33:09 AM UTC 24 |
4494106700 ps |
| T1683 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/29.xbar_same_source.3217138279 |
|
|
Aug 24 05:32:45 AM UTC 24 |
Aug 24 05:33:09 AM UTC 24 |
421232138 ps |
| T1684 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/29.xbar_error_and_unmapped_addr.427233239 |
|
|
Aug 24 05:33:05 AM UTC 24 |
Aug 24 05:33:11 AM UTC 24 |
28621769 ps |
| T1685 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/30.xbar_smoke_zero_delays.2004982766 |
|
|
Aug 24 05:33:23 AM UTC 24 |
Aug 24 05:33:29 AM UTC 24 |
54971608 ps |
| T1686 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/30.xbar_smoke.1247253528 |
|
|
Aug 24 05:33:22 AM UTC 24 |
Aug 24 05:33:30 AM UTC 24 |
163565485 ps |
| T603 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/27.xbar_stress_all_with_error.3396339614 |
|
|
Aug 24 05:29:31 AM UTC 24 |
Aug 24 05:33:34 AM UTC 24 |
9531813920 ps |
| T1687 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/30.xbar_random.2674823759 |
|
|
Aug 24 05:33:44 AM UTC 24 |
Aug 24 05:33:55 AM UTC 24 |
114239839 ps |
| T1688 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/29.xbar_stress_all_with_reset_error.3043935615 |
|
|
Aug 24 05:33:20 AM UTC 24 |
Aug 24 05:34:08 AM UTC 24 |
227001883 ps |
| T1689 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/29.chip_tl_errors.1388777915 |
|
|
Aug 24 05:31:49 AM UTC 24 |
Aug 24 05:34:09 AM UTC 24 |
3989879368 ps |
| T1690 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/28.xbar_stress_all_with_error.2091097634 |
|
|
Aug 24 05:31:43 AM UTC 24 |
Aug 24 05:34:19 AM UTC 24 |
5682189916 ps |
| T1691 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/30.xbar_random_zero_delays.76275830 |
|
|
Aug 24 05:33:44 AM UTC 24 |
Aug 24 05:34:24 AM UTC 24 |
611299417 ps |
| T1692 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/30.xbar_smoke_large_delays.3684304707 |
|
|
Aug 24 05:33:24 AM UTC 24 |
Aug 24 05:34:29 AM UTC 24 |
7679521298 ps |
| T1693 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/30.xbar_smoke_slow_rsp.3355833493 |
|
|
Aug 24 05:33:26 AM UTC 24 |
Aug 24 05:34:30 AM UTC 24 |
5448475910 ps |
| T1694 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/30.xbar_same_source.2758841991 |
|
|
Aug 24 05:34:33 AM UTC 24 |
Aug 24 05:34:51 AM UTC 24 |
243652499 ps |
| T1695 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/26.xbar_random_slow_rsp.75661278 |
|
|
Aug 24 05:26:34 AM UTC 24 |
Aug 24 05:34:53 AM UTC 24 |
43176225369 ps |
| T1696 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/30.xbar_unmapped_addr.3756621445 |
|
|
Aug 24 05:34:43 AM UTC 24 |
Aug 24 05:34:59 AM UTC 24 |
148346834 ps |
| T1697 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/30.xbar_error_and_unmapped_addr.407278094 |
|
|
Aug 24 05:34:44 AM UTC 24 |
Aug 24 05:35:12 AM UTC 24 |
925595318 ps |
| T1698 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/30.xbar_error_random.3714263825 |
|
|
Aug 24 05:34:38 AM UTC 24 |
Aug 24 05:35:12 AM UTC 24 |
581926119 ps |
| T1699 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/31.xbar_smoke.2983869444 |
|
|
Aug 24 05:35:27 AM UTC 24 |
Aug 24 05:35:34 AM UTC 24 |
169767575 ps |
| T1700 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/30.xbar_access_same_device.532227213 |
|
|
Aug 24 05:34:22 AM UTC 24 |
Aug 24 05:35:35 AM UTC 24 |
2265112521 ps |
| T1701 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/31.xbar_smoke_zero_delays.1954224425 |
|
|
Aug 24 05:35:48 AM UTC 24 |
Aug 24 05:35:55 AM UTC 24 |
53540818 ps |
| T1702 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/29.xbar_access_same_device_slow_rsp.1164367505 |
|
|
Aug 24 05:32:44 AM UTC 24 |
Aug 24 05:36:19 AM UTC 24 |
18306760930 ps |
| T1703 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/31.xbar_smoke_large_delays.2999278832 |
|
|
Aug 24 05:35:49 AM UTC 24 |
Aug 24 05:36:56 AM UTC 24 |
8224820201 ps |
| T536 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/30.xbar_stress_all_with_rand_reset.1730762521 |
|
|
Aug 24 05:35:07 AM UTC 24 |
Aug 24 05:36:58 AM UTC 24 |
3619982347 ps |
| T1704 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/30.xbar_random_slow_rsp.1542325265 |
|
|
Aug 24 05:34:09 AM UTC 24 |
Aug 24 05:36:58 AM UTC 24 |
14602103647 ps |
| T1705 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/31.xbar_smoke_slow_rsp.922819410 |
|
|
Aug 24 05:36:10 AM UTC 24 |
Aug 24 05:37:13 AM UTC 24 |
4703759022 ps |
| T1706 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/29.xbar_stress_all.2486978828 |
|
|
Aug 24 05:33:10 AM UTC 24 |
Aug 24 05:37:13 AM UTC 24 |
8136096609 ps |
| T1707 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/31.xbar_random_zero_delays.3509712109 |
|
|
Aug 24 05:37:10 AM UTC 24 |
Aug 24 05:37:18 AM UTC 24 |
62802979 ps |
| T1708 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/29.xbar_stress_all_with_error.3663240699 |
|
|
Aug 24 05:33:19 AM UTC 24 |
Aug 24 05:37:28 AM UTC 24 |
9936236911 ps |
| T1709 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/31.xbar_random.465353602 |
|
|
Aug 24 05:36:34 AM UTC 24 |
Aug 24 05:37:31 AM UTC 24 |
2268411300 ps |
| T1710 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/31.xbar_access_same_device.3019269046 |
|
|
Aug 24 05:37:27 AM UTC 24 |
Aug 24 05:37:42 AM UTC 24 |
166979941 ps |
| T1711 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/27.xbar_random_slow_rsp.2124019469 |
|
|
Aug 24 05:28:37 AM UTC 24 |
Aug 24 05:37:43 AM UTC 24 |
42586339601 ps |
| T1712 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/31.xbar_error_random.1879640584 |
|
|
Aug 24 05:37:42 AM UTC 24 |
Aug 24 05:37:52 AM UTC 24 |
97040590 ps |
| T794 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/21.xbar_access_same_device_slow_rsp.316425591 |
|
|
Aug 24 05:13:10 AM UTC 24 |
Aug 24 05:37:58 AM UTC 24 |
125585707075 ps |
| T1713 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/31.xbar_same_source.3086871789 |
|
|
Aug 24 05:37:32 AM UTC 24 |
Aug 24 05:37:59 AM UTC 24 |
489738633 ps |
| T1714 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/31.xbar_error_and_unmapped_addr.2747518049 |
|
|
Aug 24 05:37:57 AM UTC 24 |
Aug 24 05:38:05 AM UTC 24 |
58814868 ps |
| T1715 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/17.chip_same_csr_outstanding.3974826448 |
|
|
Aug 24 04:56:52 AM UTC 24 |
Aug 24 05:38:06 AM UTC 24 |
27581671419 ps |
| T1716 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/31.xbar_unmapped_addr.2847428332 |
|
|
Aug 24 05:37:44 AM UTC 24 |
Aug 24 05:38:16 AM UTC 24 |
347692931 ps |
| T1717 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/26.xbar_random_large_delays.1547805307 |
|
|
Aug 24 05:26:27 AM UTC 24 |
Aug 24 05:38:21 AM UTC 24 |
91427851915 ps |
| T1718 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/32.xbar_smoke_zero_delays.688345243 |
|
|
Aug 24 05:38:20 AM UTC 24 |
Aug 24 05:38:26 AM UTC 24 |
51122162 ps |
| T1719 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/32.xbar_smoke.3645607524 |
|
|
Aug 24 05:38:19 AM UTC 24 |
Aug 24 05:38:27 AM UTC 24 |
223937849 ps |
| T820 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/26.xbar_access_same_device_slow_rsp.2397008352 |
|
|
Aug 24 05:26:41 AM UTC 24 |
Aug 24 05:38:36 AM UTC 24 |
62149928466 ps |
| T1720 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/27.xbar_random_large_delays.4184737906 |
|
|
Aug 24 05:28:24 AM UTC 24 |
Aug 24 05:38:42 AM UTC 24 |
76287793774 ps |
| T1721 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/29.xbar_stress_all_with_rand_reset.2703358431 |
|
|
Aug 24 05:33:18 AM UTC 24 |
Aug 24 05:38:45 AM UTC 24 |
867060431 ps |
| T1722 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/29.xbar_random_slow_rsp.1503266890 |
|
|
Aug 24 05:32:26 AM UTC 24 |
Aug 24 05:38:51 AM UTC 24 |
32837151330 ps |
| T1723 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/32.xbar_random.4076432075 |
|
|
Aug 24 05:38:41 AM UTC 24 |
Aug 24 05:38:54 AM UTC 24 |
148289433 ps |
| T1724 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/32.xbar_random_zero_delays.881545497 |
|
|
Aug 24 05:38:41 AM UTC 24 |
Aug 24 05:39:21 AM UTC 24 |
598062656 ps |
| T1725 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/32.xbar_smoke_large_delays.4242596103 |
|
|
Aug 24 05:38:30 AM UTC 24 |
Aug 24 05:39:23 AM UTC 24 |
6175493325 ps |
| T1726 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/30.xbar_stress_all.3985131112 |
|
|
Aug 24 05:35:05 AM UTC 24 |
Aug 24 05:39:24 AM UTC 24 |
9664560780 ps |
| T1727 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/32.xbar_smoke_slow_rsp.1510658688 |
|
|
Aug 24 05:38:36 AM UTC 24 |
Aug 24 05:39:36 AM UTC 24 |
4905093679 ps |
| T1728 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/32.xbar_error_random.4190424864 |
|
|
Aug 24 05:39:36 AM UTC 24 |
Aug 24 05:39:56 AM UTC 24 |
732135097 ps |
| T1729 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/32.xbar_access_same_device.2788773204 |
|
|
Aug 24 05:38:59 AM UTC 24 |
Aug 24 05:39:57 AM UTC 24 |
764074196 ps |
| T1730 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/32.xbar_error_and_unmapped_addr.3974265877 |
|
|
Aug 24 05:39:38 AM UTC 24 |
Aug 24 05:39:58 AM UTC 24 |
699804748 ps |
| T1731 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/32.xbar_same_source.3385132350 |
|
|
Aug 24 05:39:08 AM UTC 24 |
Aug 24 05:40:05 AM UTC 24 |
2615414701 ps |
| T601 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/30.xbar_stress_all_with_error.3834201869 |
|
|
Aug 24 05:35:14 AM UTC 24 |
Aug 24 05:40:13 AM UTC 24 |
11725495734 ps |
| T1732 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/32.xbar_unmapped_addr.1345188054 |
|
|
Aug 24 05:39:38 AM UTC 24 |
Aug 24 05:40:16 AM UTC 24 |
1231636262 ps |
| T1733 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/33.xbar_smoke.1416455464 |
|
|
Aug 24 05:40:20 AM UTC 24 |
Aug 24 05:40:28 AM UTC 24 |
188100573 ps |
| T841 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/31.xbar_stress_all_with_rand_reset.1006107532 |
|
|
Aug 24 05:38:07 AM UTC 24 |
Aug 24 05:40:29 AM UTC 24 |
812338641 ps |
| T1734 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/33.xbar_smoke_zero_delays.3774247539 |
|
|
Aug 24 05:40:27 AM UTC 24 |
Aug 24 05:40:33 AM UTC 24 |
43396939 ps |
| T1735 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/31.xbar_stress_all.1287380176 |
|
|
Aug 24 05:37:57 AM UTC 24 |
Aug 24 05:40:49 AM UTC 24 |
6124960569 ps |
| T1736 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/33.xbar_random.490137456 |
|
|
Aug 24 05:40:43 AM UTC 24 |
Aug 24 05:41:01 AM UTC 24 |
561990658 ps |
| T1737 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/31.xbar_stress_all_with_reset_error.974760844 |
|
|
Aug 24 05:38:14 AM UTC 24 |
Aug 24 05:41:07 AM UTC 24 |
2289475870 ps |
| T1738 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/29.xbar_random_large_delays.3421709279 |
|
|
Aug 24 05:32:23 AM UTC 24 |
Aug 24 05:41:21 AM UTC 24 |
62668632301 ps |
| T1739 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/33.xbar_random_zero_delays.2653413703 |
|
|
Aug 24 05:40:47 AM UTC 24 |
Aug 24 05:41:22 AM UTC 24 |
513917973 ps |
| T1740 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/32.xbar_random_large_delays.3878971631 |
|
|
Aug 24 05:38:50 AM UTC 24 |
Aug 24 05:41:28 AM UTC 24 |
19445023870 ps |
| T1741 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/33.xbar_smoke_large_delays.2386346411 |
|
|
Aug 24 05:40:30 AM UTC 24 |
Aug 24 05:41:36 AM UTC 24 |
7794469282 ps |
| T1742 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/16.chip_same_csr_outstanding.1431031827 |
|
|
Aug 24 04:51:35 AM UTC 24 |
Aug 24 05:41:45 AM UTC 24 |
34532335374 ps |
| T1743 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/33.xbar_error_random.1942374980 |
|
|
Aug 24 05:41:43 AM UTC 24 |
Aug 24 05:41:49 AM UTC 24 |
32662464 ps |
| T1744 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/32.xbar_stress_all_with_rand_reset.3940138340 |
|
|
Aug 24 05:40:10 AM UTC 24 |
Aug 24 05:41:52 AM UTC 24 |
331301000 ps |
| T1745 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/33.xbar_smoke_slow_rsp.3134401967 |
|
|
Aug 24 05:40:42 AM UTC 24 |
Aug 24 05:41:55 AM UTC 24 |
5971079750 ps |
| T1746 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/33.xbar_access_same_device.3925988707 |
|
|
Aug 24 05:41:21 AM UTC 24 |
Aug 24 05:41:56 AM UTC 24 |
1213975358 ps |
| T1747 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/33.xbar_unmapped_addr.2101509160 |
|
|
Aug 24 05:41:51 AM UTC 24 |
Aug 24 05:41:57 AM UTC 24 |
82420895 ps |
| T1748 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/33.xbar_same_source.3338205867 |
|
|
Aug 24 05:41:36 AM UTC 24 |
Aug 24 05:41:58 AM UTC 24 |
920707382 ps |
| T1749 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/33.xbar_error_and_unmapped_addr.2163913170 |
|
|
Aug 24 05:42:00 AM UTC 24 |
Aug 24 05:42:08 AM UTC 24 |
68587961 ps |
| T1750 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/34.xbar_smoke_zero_delays.691633288 |
|
|
Aug 24 05:42:12 AM UTC 24 |
Aug 24 05:42:18 AM UTC 24 |
47772646 ps |
| T1751 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/34.xbar_smoke.2709514050 |
|
|
Aug 24 05:42:12 AM UTC 24 |
Aug 24 05:42:18 AM UTC 24 |
53150935 ps |
| T857 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/27.xbar_stress_all_with_rand_reset.2996650848 |
|
|
Aug 24 05:29:19 AM UTC 24 |
Aug 24 05:42:19 AM UTC 24 |
24692802634 ps |
| T1752 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/31.xbar_stress_all_with_error.2999423117 |
|
|
Aug 24 05:38:12 AM UTC 24 |
Aug 24 05:42:24 AM UTC 24 |
10121963787 ps |
| T1753 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/32.xbar_random_slow_rsp.2461888394 |
|
|
Aug 24 05:38:56 AM UTC 24 |
Aug 24 05:42:26 AM UTC 24 |
18116745838 ps |
| T1754 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/33.xbar_stress_all_with_rand_reset.767731161 |
|
|
Aug 24 05:42:07 AM UTC 24 |
Aug 24 05:42:29 AM UTC 24 |
9666160 ps |
| T1755 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/34.xbar_random_zero_delays.1977826930 |
|
|
Aug 24 05:42:33 AM UTC 24 |
Aug 24 05:42:50 AM UTC 24 |
202103697 ps |
| T1756 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/32.xbar_stress_all_with_reset_error.2583408971 |
|
|
Aug 24 05:40:13 AM UTC 24 |
Aug 24 05:42:52 AM UTC 24 |
599084041 ps |
| T1757 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/32.xbar_stress_all_with_error.3533651614 |
|
|
Aug 24 05:40:11 AM UTC 24 |
Aug 24 05:42:56 AM UTC 24 |
6272604439 ps |
| T604 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/30.xbar_stress_all_with_reset_error.4071098672 |
|
|
Aug 24 05:35:27 AM UTC 24 |
Aug 24 05:43:13 AM UTC 24 |
7176858392 ps |
| T1758 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/34.xbar_random.3330219078 |
|
|
Aug 24 05:42:32 AM UTC 24 |
Aug 24 05:43:19 AM UTC 24 |
1864284531 ps |
| T1759 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/30.xbar_random_large_delays.1450393988 |
|
|
Aug 24 05:33:48 AM UTC 24 |
Aug 24 05:43:23 AM UTC 24 |
67298741846 ps |
| T1760 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/34.xbar_smoke_slow_rsp.572841878 |
|
|
Aug 24 05:42:32 AM UTC 24 |
Aug 24 05:43:25 AM UTC 24 |
4346502196 ps |
| T1761 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/34.xbar_access_same_device.1651838647 |
|
|
Aug 24 05:42:44 AM UTC 24 |
Aug 24 05:43:27 AM UTC 24 |
851318695 ps |
| T1762 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/34.xbar_smoke_large_delays.1426741675 |
|
|
Aug 24 05:42:22 AM UTC 24 |
Aug 24 05:43:28 AM UTC 24 |
7543208699 ps |
| T1763 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/31.xbar_random_slow_rsp.1309388966 |
|
|
Aug 24 05:37:12 AM UTC 24 |
Aug 24 05:43:37 AM UTC 24 |
33127129232 ps |
| T1764 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/34.xbar_same_source.1770885048 |
|
|
Aug 24 05:43:06 AM UTC 24 |
Aug 24 05:43:37 AM UTC 24 |
1387481406 ps |
| T1765 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/34.xbar_error_and_unmapped_addr.1665778454 |
|
|
Aug 24 05:43:33 AM UTC 24 |
Aug 24 05:43:41 AM UTC 24 |
149122603 ps |
| T1766 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/35.xbar_smoke.2494917539 |
|
|
Aug 24 05:43:50 AM UTC 24 |
Aug 24 05:43:57 AM UTC 24 |
52935684 ps |
| T1767 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/35.xbar_smoke_zero_delays.1329344220 |
|
|
Aug 24 05:43:51 AM UTC 24 |
Aug 24 05:43:57 AM UTC 24 |
38106890 ps |
| T1768 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/34.xbar_unmapped_addr.2657625928 |
|
|
Aug 24 05:43:28 AM UTC 24 |
Aug 24 05:43:58 AM UTC 24 |
315518594 ps |
| T1769 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/34.xbar_error_random.1695311768 |
|
|
Aug 24 05:43:10 AM UTC 24 |
Aug 24 05:44:01 AM UTC 24 |
2052611749 ps |
| T1770 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/35.xbar_random_zero_delays.36211111 |
|
|
Aug 24 05:44:12 AM UTC 24 |
Aug 24 05:44:42 AM UTC 24 |
497222929 ps |
| T1771 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/35.xbar_random.2050140048 |
|
|
Aug 24 05:44:12 AM UTC 24 |
Aug 24 05:45:01 AM UTC 24 |
1821306286 ps |
| T1772 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/35.xbar_smoke_slow_rsp.329235223 |
|
|
Aug 24 05:44:11 AM UTC 24 |
Aug 24 05:45:06 AM UTC 24 |
4475422671 ps |
| T1773 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/35.xbar_smoke_large_delays.4185393847 |
|
|
Aug 24 05:43:55 AM UTC 24 |
Aug 24 05:45:06 AM UTC 24 |
8570470036 ps |
| T1774 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/33.xbar_stress_all_with_reset_error.3733971936 |
|
|
Aug 24 05:42:10 AM UTC 24 |
Aug 24 05:45:41 AM UTC 24 |
5228439146 ps |
| T1775 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/35.xbar_access_same_device.2884093343 |
|
|
Aug 24 05:45:15 AM UTC 24 |
Aug 24 05:45:56 AM UTC 24 |
1275731594 ps |
| T1776 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/32.xbar_stress_all.1978837111 |
|
|
Aug 24 05:39:51 AM UTC 24 |
Aug 24 05:45:59 AM UTC 24 |
13893981795 ps |
| T1777 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/28.xbar_access_same_device_slow_rsp.2413271267 |
|
|
Aug 24 05:30:54 AM UTC 24 |
Aug 24 05:46:02 AM UTC 24 |
77706334891 ps |
| T1778 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/35.xbar_error_random.847208554 |
|
|
Aug 24 05:45:55 AM UTC 24 |
Aug 24 05:46:11 AM UTC 24 |
203586112 ps |
| T1779 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/35.xbar_same_source.559582882 |
|
|
Aug 24 05:45:20 AM UTC 24 |
Aug 24 05:46:14 AM UTC 24 |
2329025652 ps |
| T1780 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/35.xbar_error_and_unmapped_addr.2436293873 |
|
|
Aug 24 05:46:13 AM UTC 24 |
Aug 24 05:46:24 AM UTC 24 |
101364965 ps |
| T1781 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/35.xbar_unmapped_addr.3938688837 |
|
|
Aug 24 05:46:10 AM UTC 24 |
Aug 24 05:46:39 AM UTC 24 |
313725872 ps |
| T798 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/27.xbar_access_same_device_slow_rsp.3458883261 |
|
|
Aug 24 05:28:44 AM UTC 24 |
Aug 24 05:46:47 AM UTC 24 |
87884094802 ps |
| T1782 |
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/34.xbar_stress_all_with_error.1838662689 |
|
|
Aug 24 05:43:41 AM UTC 24 |
Aug 24 05:46:56 AM UTC 24 |
7516995392 ps |