| T918 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_good_prod.1792177343 |
|
|
Aug 27 11:36:13 PM UTC 24 |
Aug 28 12:44:21 AM UTC 24 |
15545593800 ps |
| T363 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sival_flash_info_access.1936722345 |
|
|
Aug 28 12:39:25 AM UTC 24 |
Aug 28 12:44:26 AM UTC 24 |
2589958396 ps |
| T254 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_lc_walkthrough_prod.3405773357 |
|
|
Aug 27 10:44:18 PM UTC 24 |
Aug 28 12:44:40 AM UTC 24 |
51355802855 ps |
| T919 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_nothing_rma.326471254 |
|
|
Aug 27 11:40:50 PM UTC 24 |
Aug 28 12:45:12 AM UTC 24 |
13311556912 ps |
| T70 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_sleep_pin_retention.3806881817 |
|
|
Aug 28 12:41:25 AM UTC 24 |
Aug 28 12:45:43 AM UTC 24 |
2906830590 ps |
| T136 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_pattgen_ios.147029468 |
|
|
Aug 28 12:41:59 AM UTC 24 |
Aug 28 12:46:03 AM UTC 24 |
3284656856 ps |
| T20 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_sleep_pin_mio_dio_val.1311621734 |
|
|
Aug 28 12:40:56 AM UTC 24 |
Aug 28 12:46:04 AM UTC 24 |
3023302902 ps |
| T632 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq.2777234514 |
|
|
Aug 27 11:27:38 PM UTC 24 |
Aug 28 12:47:33 AM UTC 24 |
24727050212 ps |
| T920 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_bad_rma.3284235692 |
|
|
Aug 27 11:38:37 PM UTC 24 |
Aug 28 12:48:01 AM UTC 24 |
14654888052 ps |
| T921 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_good_dev.3125136615 |
|
|
Aug 27 11:34:11 PM UTC 24 |
Aug 28 12:48:05 AM UTC 24 |
15711190270 ps |
| T922 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_bad_dev.2480185011 |
|
|
Aug 27 11:39:20 PM UTC 24 |
Aug 28 12:48:40 AM UTC 24 |
15336896920 ps |
| T25 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_sleep_pin_wake.1286892557 |
|
|
Aug 28 12:41:01 AM UTC 24 |
Aug 28 12:48:41 AM UTC 24 |
5356664600 ps |
| T923 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_bad_prod_end.1092617380 |
|
|
Aug 27 11:38:48 PM UTC 24 |
Aug 28 12:48:42 AM UTC 24 |
15610969104 ps |
| T663 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/default/0.rom_e2e_sigverify_always_a_nothing_b_bad_prod.1067525839 |
|
|
Aug 27 11:42:43 PM UTC 24 |
Aug 28 12:48:48 AM UTC 24 |
14600770310 ps |
| T924 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_good_prod_end.1747709197 |
|
|
Aug 27 11:36:45 PM UTC 24 |
Aug 28 12:49:19 AM UTC 24 |
15538521880 ps |
| T925 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_nothing_prod_end.2470456751 |
|
|
Aug 27 11:41:05 PM UTC 24 |
Aug 28 12:50:11 AM UTC 24 |
14800328320 ps |
| T360 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_all_escalation_resets.2594309981 |
|
|
Aug 28 12:40:41 AM UTC 24 |
Aug 28 12:50:22 AM UTC 24 |
5161679512 ps |
| T926 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_bad_prod.4099741428 |
|
|
Aug 27 11:38:15 PM UTC 24 |
Aug 28 12:50:36 AM UTC 24 |
15581362860 ps |
| T927 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/default/0.rom_e2e_sigverify_always_a_nothing_b_bad_dev.3721829325 |
|
|
Aug 27 11:42:13 PM UTC 24 |
Aug 28 12:51:40 AM UTC 24 |
14211475092 ps |
| T928 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/default/0.rom_e2e_asm_init_rma.2756407584 |
|
|
Aug 27 11:45:57 PM UTC 24 |
Aug 28 12:52:26 AM UTC 24 |
14922902558 ps |
| T929 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/default/0.rom_e2e_sigverify_always_a_nothing_b_bad_rma.1041466609 |
|
|
Aug 27 11:43:56 PM UTC 24 |
Aug 28 12:52:59 AM UTC 24 |
14291154765 ps |
| T45 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_spi_host_tx_rx.4259267170 |
|
|
Aug 28 12:48:05 AM UTC 24 |
Aug 28 12:53:00 AM UTC 24 |
3013168128 ps |
| T49 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_spi_device_tpm.2426190802 |
|
|
Aug 28 12:46:51 AM UTC 24 |
Aug 28 12:53:36 AM UTC 24 |
3192904616 ps |
| T79 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_spi_device_pinmux_sleep_retention.3509226534 |
|
|
Aug 28 12:49:34 AM UTC 24 |
Aug 28 12:53:44 AM UTC 24 |
3712213343 ps |
| T930 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_good_rma.651325480 |
|
|
Aug 27 11:37:22 PM UTC 24 |
Aug 28 12:53:59 AM UTC 24 |
15157415372 ps |
| T931 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/default/0.rom_e2e_asm_init_prod_end.2910738472 |
|
|
Aug 27 11:45:25 PM UTC 24 |
Aug 28 12:53:59 AM UTC 24 |
16071621770 ps |
| T682 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_rstmgr_rst_cnsty_escalation.2735653067 |
|
|
Aug 28 12:41:01 AM UTC 24 |
Aug 28 12:54:02 AM UTC 24 |
5916407806 ps |
| T291 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_data_integrity_escalation.3803862374 |
|
|
Aug 28 12:40:55 AM UTC 24 |
Aug 28 12:54:07 AM UTC 24 |
6033890220 ps |
| T64 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_uart_tx_rx_idx2.3915395317 |
|
|
Aug 28 12:43:45 AM UTC 24 |
Aug 28 12:54:15 AM UTC 24 |
3716147950 ps |
| T359 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_uart_tx_rx.2948081774 |
|
|
Aug 28 12:42:52 AM UTC 24 |
Aug 28 12:54:33 AM UTC 24 |
4335399628 ps |
| T142 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_ast_clk_rst_inputs.3889441120 |
|
|
Aug 27 11:32:46 PM UTC 24 |
Aug 28 12:54:35 AM UTC 24 |
27799413509 ps |
| T135 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_uart_tx_rx_idx1.3897406185 |
|
|
Aug 28 12:43:22 AM UTC 24 |
Aug 28 12:54:36 AM UTC 24 |
4668519064 ps |
| T345 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_uart_tx_rx_idx3.747586052 |
|
|
Aug 28 12:44:00 AM UTC 24 |
Aug 28 12:54:36 AM UTC 24 |
3887984690 ps |
| T932 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/default/0.rom_e2e_jtag_inject_dev.267290585 |
|
|
Aug 27 11:54:47 PM UTC 24 |
Aug 28 12:55:01 AM UTC 24 |
31770457814 ps |
| T350 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_i2c_device_tx_rx.2611350612 |
|
|
Aug 28 12:46:50 AM UTC 24 |
Aug 28 12:55:07 AM UTC 24 |
3778623252 ps |
| T933 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/default/0.rom_e2e_asm_init_dev.799366886 |
|
|
Aug 27 11:44:07 PM UTC 24 |
Aug 28 12:55:28 AM UTC 24 |
15357484872 ps |
| T934 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/default/0.rom_e2e_asm_init_prod.3652114054 |
|
|
Aug 27 11:45:24 PM UTC 24 |
Aug 28 12:56:54 AM UTC 24 |
15406136642 ps |
| T40 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_gpio.1622161634 |
|
|
Aug 28 12:49:58 AM UTC 24 |
Aug 28 12:57:31 AM UTC 24 |
4156571476 ps |
| T935 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_flash_ctrl_idle_low_power.1097073969 |
|
|
Aug 28 12:51:05 AM UTC 24 |
Aug 28 12:57:34 AM UTC 24 |
3152705604 ps |
| T227 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_spi_device_pass_through_collision.3664542402 |
|
|
Aug 28 12:49:01 AM UTC 24 |
Aug 28 12:58:00 AM UTC 24 |
4539857800 ps |
| T637 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_lc_ctrl_volatile_raw_unlock.1569179599 |
|
|
Aug 28 12:56:40 AM UTC 24 |
Aug 28 12:58:39 AM UTC 24 |
1852153035 ps |
| T936 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_kmac_entropy.1586513534 |
|
|
Aug 28 12:53:45 AM UTC 24 |
Aug 28 12:58:39 AM UTC 24 |
2940764264 ps |
| T638 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz.2761726199 |
|
|
Aug 28 12:56:31 AM UTC 24 |
Aug 28 12:58:45 AM UTC 24 |
2425523099 ps |
| T937 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_lc_ctrl_otp_hw_cfg0.3062112889 |
|
|
Aug 28 12:53:46 AM UTC 24 |
Aug 28 12:59:00 AM UTC 24 |
3005248360 ps |
| T252 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_flash_ctrl_lc_rw_en.806838713 |
|
|
Aug 28 12:49:59 AM UTC 24 |
Aug 28 12:59:12 AM UTC 24 |
5893291580 ps |
| T370 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_flash_ctrl_ops.4108946022 |
|
|
Aug 28 12:49:33 AM UTC 24 |
Aug 28 12:59:14 AM UTC 24 |
4076106328 ps |
| T228 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_spi_device_pass_through.810496451 |
|
|
Aug 28 12:49:12 AM UTC 24 |
Aug 28 12:59:20 AM UTC 24 |
6305229450 ps |
| T139 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_i2c_host_tx_rx.3828801802 |
|
|
Aug 28 12:45:23 AM UTC 24 |
Aug 28 12:59:22 AM UTC 24 |
5674919310 ps |
| T194 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_otp_ctrl_vendor_test_csr_access.3020565209 |
|
|
Aug 28 12:56:32 AM UTC 24 |
Aug 28 12:59:45 AM UTC 24 |
2947081286 ps |
| T60 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_i2c_host_tx_rx_idx1.1735567731 |
|
|
Aug 28 12:45:48 AM UTC 24 |
Aug 28 01:00:00 AM UTC 24 |
5838925304 ps |
| T938 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_otp_ctrl_ecc_error_vendor_test.2118920692 |
|
|
Aug 28 12:56:35 AM UTC 24 |
Aug 28 01:00:00 AM UTC 24 |
2026700718 ps |
| T939 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/default/0.rom_e2e_sigverify_always_a_nothing_b_bad_prod_end.2366640633 |
|
|
Aug 27 11:43:44 PM UTC 24 |
Aug 28 01:00:12 AM UTC 24 |
14618929263 ps |
| T358 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_flash_ctrl_ops_jitter_en.4121266559 |
|
|
Aug 28 12:50:03 AM UTC 24 |
Aug 28 01:00:52 AM UTC 24 |
4511775782 ps |
| T62 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_i2c_host_tx_rx_idx2.1831194747 |
|
|
Aug 28 12:46:19 AM UTC 24 |
Aug 28 01:00:58 AM UTC 24 |
5250202100 ps |
| T639 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_lc_ctrl_rand_to_scrap.2721040928 |
|
|
Aug 28 12:56:28 AM UTC 24 |
Aug 28 01:01:05 AM UTC 24 |
3615948262 ps |
| T940 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_rstmgr_sw_req.1408230885 |
|
|
Aug 28 12:58:16 AM UTC 24 |
Aug 28 01:02:35 AM UTC 24 |
3124320318 ps |
| T941 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_otbn_smoketest.3982932851 |
|
|
Aug 28 12:33:00 AM UTC 24 |
Aug 28 01:03:11 AM UTC 24 |
8527988990 ps |
| T942 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_rstmgr_sw_rst.479131647 |
|
|
Aug 28 12:58:17 AM UTC 24 |
Aug 28 01:03:22 AM UTC 24 |
2399029800 ps |
| T94 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_usbdev_pincfg.3737870188 |
|
|
Aug 27 10:39:47 PM UTC 24 |
Aug 28 01:04:22 AM UTC 24 |
31436440770 ps |
| T943 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_otp_ctrl_lc_signals_test_unlocked0.3489294957 |
|
|
Aug 28 12:55:19 AM UTC 24 |
Aug 28 01:05:16 AM UTC 24 |
4384379748 ps |
| T944 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_bad_test_unlocked0.2495709401 |
|
|
Aug 27 11:37:33 PM UTC 24 |
Aug 28 01:05:18 AM UTC 24 |
18065088996 ps |
| T945 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_sleep_pwm_pulses.715351952 |
|
|
Aug 28 12:41:55 AM UTC 24 |
Aug 28 01:05:36 AM UTC 24 |
9563938252 ps |
| T946 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_rv_timer_irq.1940854253 |
|
|
Aug 28 01:03:11 AM UTC 24 |
Aug 28 01:06:05 AM UTC 24 |
3184056760 ps |
| T651 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_pwrmgr_sleep_disabled.1759503215 |
|
|
Aug 28 01:01:50 AM UTC 24 |
Aug 28 01:06:21 AM UTC 24 |
3222727872 ps |
| T947 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_flash_ctrl_access.2547861028 |
|
|
Aug 28 12:50:06 AM UTC 24 |
Aug 28 01:06:27 AM UTC 24 |
5823221856 ps |
| T948 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/default/0.rom_e2e_jtag_inject_rma.1612566370 |
|
|
Aug 27 11:58:48 PM UTC 24 |
Aug 28 01:06:30 AM UTC 24 |
38172202594 ps |
| T181 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_pwrmgr_full_aon_reset.1861711917 |
|
|
Aug 28 01:00:00 AM UTC 24 |
Aug 28 01:07:15 AM UTC 24 |
7605598208 ps |
| T949 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_pwrmgr_deep_sleep_power_glitch_reset.3102870343 |
|
|
Aug 28 01:01:08 AM UTC 24 |
Aug 28 01:07:58 AM UTC 24 |
6035295938 ps |
| T233 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_sysrst_ctrl_inputs.3083530175 |
|
|
Aug 28 01:04:11 AM UTC 24 |
Aug 28 01:09:16 AM UTC 24 |
2944530120 ps |
| T950 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_flash_ctrl_access_jitter_en.3350653906 |
|
|
Aug 28 12:50:55 AM UTC 24 |
Aug 28 01:09:25 AM UTC 24 |
6030452528 ps |
| T951 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_uart_rand_baudrate.2243874311 |
|
|
Aug 28 12:45:29 AM UTC 24 |
Aug 28 01:10:09 AM UTC 24 |
7649058116 ps |
| T952 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_pwrmgr_usb_clk_disabled_when_active.2820640528 |
|
|
Aug 28 01:01:50 AM UTC 24 |
Aug 28 01:10:19 AM UTC 24 |
4515151096 ps |
| T953 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_pwrmgr_main_power_glitch_reset.3718256505 |
|
|
Aug 28 01:00:01 AM UTC 24 |
Aug 28 01:10:28 AM UTC 24 |
5630868100 ps |
| T954 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_flash_ctrl_clock_freqs.972182889 |
|
|
Aug 28 12:53:02 AM UTC 24 |
Aug 28 01:11:27 AM UTC 24 |
5598702058 ps |
| T47 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_sysrst_ctrl_ulp_z3_wakeup.3595759442 |
|
|
Aug 28 01:04:59 AM UTC 24 |
Aug 28 01:11:37 AM UTC 24 |
5151678458 ps |
| T955 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/default/0.rom_e2e_keymgr_init_rom_ext_meas.493645321 |
|
|
Aug 27 11:59:54 PM UTC 24 |
Aug 28 01:11:55 AM UTC 24 |
15215770800 ps |
| T956 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_aon_timer_irq.2879757779 |
|
|
Aug 28 01:06:40 AM UTC 24 |
Aug 28 01:12:13 AM UTC 24 |
3775009562 ps |
| T234 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_sysrst_ctrl_outputs.3191803928 |
|
|
Aug 28 01:06:15 AM UTC 24 |
Aug 28 01:12:17 AM UTC 24 |
3157225000 ps |
| T957 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/default/0.rom_e2e_keymgr_init_rom_ext_no_meas.36447660 |
|
|
Aug 28 12:01:01 AM UTC 24 |
Aug 28 01:12:30 AM UTC 24 |
14323462004 ps |
| T398 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/default/0.rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0.24649083 |
|
|
Aug 27 11:38:29 PM UTC 24 |
Aug 28 01:12:37 AM UTC 24 |
18032289348 ps |
| T958 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_lc_walkthrough_prodend.2127454765 |
|
|
Aug 28 12:55:59 AM UTC 24 |
Aug 28 01:13:07 AM UTC 24 |
9095902799 ps |
| T261 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_rstmgr_cpu_info.3586080711 |
|
|
Aug 28 01:00:51 AM UTC 24 |
Aug 28 01:13:08 AM UTC 24 |
5293492568 ps |
| T959 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_pwrmgr_deep_sleep_por_reset.1436048744 |
|
|
Aug 28 01:01:12 AM UTC 24 |
Aug 28 01:13:24 AM UTC 24 |
9481732340 ps |
| T960 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_uart_tx_rx_alt_clk_freq_low_speed.26854021 |
|
|
Aug 28 12:45:27 AM UTC 24 |
Aug 28 01:14:40 AM UTC 24 |
13581697493 ps |
| T235 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_sysrst_ctrl_in_irq.2814941613 |
|
|
Aug 28 01:04:14 AM UTC 24 |
Aug 28 01:14:40 AM UTC 24 |
4540205606 ps |
| T961 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_lc_ctrl_transition.1025862774 |
|
|
Aug 28 12:56:35 AM UTC 24 |
Aug 28 01:14:41 AM UTC 24 |
9882900241 ps |
| T962 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_aon_timer_sleep_wdog_sleep_pause.3218063517 |
|
|
Aug 28 01:07:14 AM UTC 24 |
Aug 28 01:15:19 AM UTC 24 |
6409249080 ps |
| T963 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_pwrmgr_normal_sleep_por_reset.2858387244 |
|
|
Aug 28 01:01:44 AM UTC 24 |
Aug 28 01:15:24 AM UTC 24 |
6311892540 ps |
| T964 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_otp_ctrl_lc_signals_dev.812668714 |
|
|
Aug 28 12:55:01 AM UTC 24 |
Aug 28 01:15:53 AM UTC 24 |
8622301800 ps |
| T965 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_otp_ctrl_lc_signals_rma.3783564836 |
|
|
Aug 28 12:56:25 AM UTC 24 |
Aug 28 01:16:02 AM UTC 24 |
8958600292 ps |
| T966 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_pwrmgr_wdog_reset.1402920198 |
|
|
Aug 28 01:07:17 AM UTC 24 |
Aug 28 01:16:39 AM UTC 24 |
4017621770 ps |
| T967 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_aes_enc_jitter_en.3722969562 |
|
|
Aug 28 01:12:30 AM UTC 24 |
Aug 28 01:16:42 AM UTC 24 |
3132658491 ps |
| T968 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_aes_enc.1789222323 |
|
|
Aug 28 01:12:15 AM UTC 24 |
Aug 28 01:17:05 AM UTC 24 |
2488542104 ps |
| T969 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_aes_masking_off.1718944865 |
|
|
Aug 28 01:13:19 AM UTC 24 |
Aug 28 01:18:04 AM UTC 24 |
3362628944 ps |
| T76 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_alert_test.1507203372 |
|
|
Aug 28 01:13:23 AM UTC 24 |
Aug 28 01:18:05 AM UTC 24 |
3151693984 ps |
| T970 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_otp_ctrl_lc_signals_prod.174987811 |
|
|
Aug 28 12:56:36 AM UTC 24 |
Aug 28 01:18:07 AM UTC 24 |
7442353076 ps |
| T971 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/default/0.rom_e2e_keymgr_init_rom_ext_invalid_meas.3205630325 |
|
|
Aug 28 12:05:10 AM UTC 24 |
Aug 28 01:18:36 AM UTC 24 |
15533582360 ps |
| T972 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_aes_idle.3362790566 |
|
|
Aug 28 01:13:18 AM UTC 24 |
Aug 28 01:19:35 AM UTC 24 |
3150084862 ps |
| T973 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_aon_timer_wdog_lc_escalate.312441836 |
|
|
Aug 28 01:07:47 AM UTC 24 |
Aug 28 01:19:50 AM UTC 24 |
5280209254 ps |
| T295 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_otbn_mem_scramble.1258555363 |
|
|
Aug 28 01:11:07 AM UTC 24 |
Aug 28 01:20:01 AM UTC 24 |
3572745336 ps |
| T974 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_entropy_src_kat_test.421854341 |
|
|
Aug 28 01:16:40 AM UTC 24 |
Aug 28 01:20:25 AM UTC 24 |
2906912600 ps |
| T975 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_pwrmgr_sysrst_ctrl_reset.3202124015 |
|
|
Aug 28 01:00:31 AM UTC 24 |
Aug 28 01:20:26 AM UTC 24 |
7126116280 ps |
| T367 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_adc_ctrl_sleep_debug_cable_wakeup.1110111410 |
|
|
Aug 28 01:08:34 AM UTC 24 |
Aug 28 01:20:32 AM UTC 24 |
18794079192 ps |
| T976 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_aon_timer_wdog_bite_reset.1341152088 |
|
|
Aug 28 01:07:16 AM UTC 24 |
Aug 28 01:21:33 AM UTC 24 |
9270149588 ps |
| T977 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_aes_entropy.667517900 |
|
|
Aug 28 01:16:39 AM UTC 24 |
Aug 28 01:21:36 AM UTC 24 |
2605225648 ps |
| T978 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_alert_handler_escalation.2818907961 |
|
|
Aug 28 01:13:24 AM UTC 24 |
Aug 28 01:21:40 AM UTC 24 |
4861379792 ps |
| T346 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_rstmgr_alert_info.328000439 |
|
|
Aug 28 12:58:38 AM UTC 24 |
Aug 28 01:22:25 AM UTC 24 |
9609263254 ps |
| T104 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_alert_handler_entropy.2305822052 |
|
|
Aug 28 01:16:06 AM UTC 24 |
Aug 28 01:22:38 AM UTC 24 |
2812196227 ps |
| T979 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_csrng_kat_test.4093418188 |
|
|
Aug 28 01:19:16 AM UTC 24 |
Aug 28 01:22:44 AM UTC 24 |
2510229112 ps |
| T707 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_alert_handler_lpg_sleep_mode_alerts.1025422455 |
|
|
Aug 28 01:15:41 AM UTC 24 |
Aug 28 01:23:32 AM UTC 24 |
4291434150 ps |
| T980 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_alert_handler_ping_timeout.3348153325 |
|
|
Aug 28 01:14:00 AM UTC 24 |
Aug 28 01:23:45 AM UTC 24 |
4706155448 ps |
| T981 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_pwrmgr_all_reset_reqs.2865729668 |
|
|
Aug 28 01:00:17 AM UTC 24 |
Aug 28 01:24:08 AM UTC 24 |
9863000877 ps |
| T982 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_entropy_src_ast_rng_req.471570625 |
|
|
Aug 28 01:20:32 AM UTC 24 |
Aug 28 01:24:29 AM UTC 24 |
3332633656 ps |
| T983 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_pwrmgr_normal_sleep_all_reset_reqs.862279144 |
|
|
Aug 28 01:00:51 AM UTC 24 |
Aug 28 01:24:30 AM UTC 24 |
11839676776 ps |
| T984 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/default/0.rom_e2e_static_critical.1260048349 |
|
|
Aug 27 11:58:48 PM UTC 24 |
Aug 28 01:24:41 AM UTC 24 |
17758013508 ps |
| T985 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_otbn_randomness.1183129510 |
|
|
Aug 28 01:10:04 AM UTC 24 |
Aug 28 01:24:58 AM UTC 24 |
6547871714 ps |
| T256 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_flash_init.960871695 |
|
|
Aug 28 12:51:05 AM UTC 24 |
Aug 28 01:25:39 AM UTC 24 |
25144082840 ps |
| T371 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_hmac_enc_jitter_en.3076078708 |
|
|
Aug 28 01:22:32 AM UTC 24 |
Aug 28 01:25:54 AM UTC 24 |
2640116038 ps |
| T453 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_rv_core_ibex_nmi_irq.3231364535 |
|
|
Aug 28 01:12:11 AM UTC 24 |
Aug 28 01:26:28 AM UTC 24 |
4933779028 ps |
| T986 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_csrng_fuse_en_sw_app_read_test.1472971261 |
|
|
Aug 28 01:20:18 AM UTC 24 |
Aug 28 01:26:32 AM UTC 24 |
4848787784 ps |
| T987 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_hmac_enc_idle.781601270 |
|
|
Aug 28 01:22:32 AM UTC 24 |
Aug 28 01:26:36 AM UTC 24 |
3229278120 ps |
| T988 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_hmac_enc.1728492462 |
|
|
Aug 28 01:21:26 AM UTC 24 |
Aug 28 01:26:58 AM UTC 24 |
2959516130 ps |
| T989 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_hmac_oneshot.1542495774 |
|
|
Aug 28 01:22:33 AM UTC 24 |
Aug 28 01:27:09 AM UTC 24 |
3206974278 ps |
| T627 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_edn_boot_mode.323024039 |
|
|
Aug 28 01:17:27 AM UTC 24 |
Aug 28 01:27:21 AM UTC 24 |
3158399000 ps |
| T990 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_rv_core_ibex_rnd.1628213817 |
|
|
Aug 28 01:11:06 AM UTC 24 |
Aug 28 01:27:31 AM UTC 24 |
5450023132 ps |
| T991 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_edn_kat.3107746138 |
|
|
Aug 28 01:17:41 AM UTC 24 |
Aug 28 01:29:01 AM UTC 24 |
3369039192 ps |
| T992 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_kmac_mode_cshake.2674483849 |
|
|
Aug 28 01:25:22 AM UTC 24 |
Aug 28 01:29:50 AM UTC 24 |
3204086070 ps |
| T993 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_kmac_mode_kmac.4086051406 |
|
|
Aug 28 01:25:37 AM UTC 24 |
Aug 28 01:30:20 AM UTC 24 |
2697293622 ps |
| T420 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_kmac_app_rom.3482786348 |
|
|
Aug 28 01:26:16 AM UTC 24 |
Aug 28 01:31:18 AM UTC 24 |
2464572540 ps |
| T994 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_pwrmgr_deep_sleep_all_reset_reqs.4118590912 |
|
|
Aug 28 01:00:51 AM UTC 24 |
Aug 28 01:31:20 AM UTC 24 |
17372746260 ps |
| T995 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_kmac_idle.2054985775 |
|
|
Aug 28 01:26:29 AM UTC 24 |
Aug 28 01:31:35 AM UTC 24 |
2703572016 ps |
| T996 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_sysrst_ctrl_reset.284815580 |
|
|
Aug 28 01:06:13 AM UTC 24 |
Aug 28 01:31:40 AM UTC 24 |
25722411588 ps |
| T997 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_kmac_mode_kmac_jitter_en.2288905538 |
|
|
Aug 28 01:25:38 AM UTC 24 |
Aug 28 01:32:15 AM UTC 24 |
3220537674 ps |
| T629 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_edn_auto_mode.1886366546 |
|
|
Aug 28 01:17:26 AM UTC 24 |
Aug 28 01:32:57 AM UTC 24 |
4400427800 ps |
| T998 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_csrng_lc_hw_debug_en_test.2090832797 |
|
|
Aug 28 01:19:16 AM UTC 24 |
Aug 28 01:32:58 AM UTC 24 |
5740598488 ps |
| T343 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_sensor_ctrl_status.366297036 |
|
|
Aug 28 01:29:37 AM UTC 24 |
Aug 28 01:33:50 AM UTC 24 |
3002605942 ps |
| T999 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_uart_tx_rx_alt_clk_freq.865079579 |
|
|
Aug 28 12:45:28 AM UTC 24 |
Aug 28 01:33:59 AM UTC 24 |
12947460336 ps |
| T1000 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_bad_prod.508764542 |
|
|
Aug 27 11:40:33 PM UTC 24 |
Aug 28 01:34:02 AM UTC 24 |
23334788120 ps |
| T175 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_sensor_ctrl_alert.1833322863 |
|
|
Aug 28 01:28:14 AM UTC 24 |
Aug 28 01:35:10 AM UTC 24 |
4072173980 ps |
| T296 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_sram_ctrl_scrambled_access.2837123496 |
|
|
Aug 28 01:27:23 AM UTC 24 |
Aug 28 01:35:43 AM UTC 24 |
4151495016 ps |
| T421 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_rom_ctrl_integrity_check.2519541590 |
|
|
Aug 28 01:27:24 AM UTC 24 |
Aug 28 01:35:57 AM UTC 24 |
9867236824 ps |
| T399 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/default/0.rom_e2e_boot_policy_valid_a_bad_b_good_rma.2766504204 |
|
|
Aug 27 11:38:28 PM UTC 24 |
Aug 28 01:36:15 AM UTC 24 |
23459701880 ps |
| T274 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_plic_sw_irq.791765283 |
|
|
Aug 28 01:32:28 AM UTC 24 |
Aug 28 01:36:50 AM UTC 24 |
3518973520 ps |
| T1001 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_alert_handler_ping_ok.3930631979 |
|
|
Aug 28 01:13:59 AM UTC 24 |
Aug 28 01:36:55 AM UTC 24 |
8315277166 ps |
| T168 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup.2734819154 |
|
|
Aug 28 01:30:26 AM UTC 24 |
Aug 28 01:37:16 AM UTC 24 |
5083174200 ps |
| T297 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_sram_ctrl_scrambled_access_jitter_en.277757633 |
|
|
Aug 28 01:27:45 AM UTC 24 |
Aug 28 01:38:39 AM UTC 24 |
5044759055 ps |
| T1002 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_lc_walkthrough_testunlocks.1846601435 |
|
|
Aug 28 12:57:31 AM UTC 24 |
Aug 28 01:38:54 AM UTC 24 |
27749975936 ps |
| T1003 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_sleep_sram_ret_contents_no_scramble.3501602694 |
|
|
Aug 28 01:28:15 AM UTC 24 |
Aug 28 01:38:57 AM UTC 24 |
6946381430 ps |
| T1004 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_clkmgr_off_aes_trans.3668829590 |
|
|
Aug 28 01:33:44 AM UTC 24 |
Aug 28 01:39:00 AM UTC 24 |
3518627008 ps |
| T1005 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_bad_dev.1792161225 |
|
|
Aug 27 11:41:01 PM UTC 24 |
Aug 28 01:39:21 AM UTC 24 |
24062193019 ps |
| T400 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/default/0.rom_e2e_boot_policy_valid_a_bad_b_good_prod.1542268912 |
|
|
Aug 27 11:37:40 PM UTC 24 |
Aug 28 01:39:39 AM UTC 24 |
24356805540 ps |
| T317 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_sram_ctrl_execution_main.3785488818 |
|
|
Aug 28 01:28:15 AM UTC 24 |
Aug 28 01:40:08 AM UTC 24 |
8246187336 ps |
| T1006 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_clkmgr_off_otbn_trans.2021601133 |
|
|
Aug 28 01:34:47 AM UTC 24 |
Aug 28 01:40:11 AM UTC 24 |
3837645192 ps |
| T245 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_keymgr_sideload_aes.2187700482 |
|
|
Aug 28 01:24:44 AM UTC 24 |
Aug 28 01:40:22 AM UTC 24 |
7079232408 ps |
| T1007 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_edn_entropy_reqs.3583542206 |
|
|
Aug 28 01:21:25 AM UTC 24 |
Aug 28 01:40:58 AM UTC 24 |
6734898704 ps |
| T1008 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_clkmgr_external_clk_src_for_lc.1380980873 |
|
|
Aug 28 01:34:49 AM UTC 24 |
Aug 28 01:41:09 AM UTC 24 |
6048181277 ps |
| T1009 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_clkmgr_off_kmac_trans.3070280311 |
|
|
Aug 28 01:34:46 AM UTC 24 |
Aug 28 01:41:10 AM UTC 24 |
5296656824 ps |
| T1010 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_bad_rma.946508346 |
|
|
Aug 27 11:40:47 PM UTC 24 |
Aug 28 01:41:15 AM UTC 24 |
22671782868 ps |
| T190 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_plic_all_irqs_10.3661500215 |
|
|
Aug 28 01:32:29 AM UTC 24 |
Aug 28 01:42:00 AM UTC 24 |
4255501012 ps |
| T193 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_alert_handler_lpg_sleep_mode_pings.1128485617 |
|
|
Aug 28 01:15:59 AM UTC 24 |
Aug 28 01:42:03 AM UTC 24 |
14133663880 ps |
| T1011 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_edn_entropy_reqs_jitter.4233372392 |
|
|
Aug 28 01:21:24 AM UTC 24 |
Aug 28 01:42:26 AM UTC 24 |
6736982946 ps |
| T1012 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_sleep_sram_ret_contents_scramble.3404812561 |
|
|
Aug 28 01:28:10 AM UTC 24 |
Aug 28 01:42:32 AM UTC 24 |
8227190240 ps |
| T1013 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_bad_prod_end.398215002 |
|
|
Aug 27 11:40:33 PM UTC 24 |
Aug 28 01:42:56 AM UTC 24 |
24104067456 ps |
| T1014 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_clkmgr_off_hmac_trans.1790705377 |
|
|
Aug 28 01:33:44 AM UTC 24 |
Aug 28 01:43:03 AM UTC 24 |
4946731630 ps |
| T1015 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/default/0.rom_e2e_boot_policy_valid_a_bad_b_good_prod_end.1343318556 |
|
|
Aug 27 11:39:06 PM UTC 24 |
Aug 28 01:43:16 AM UTC 24 |
24296528120 ps |
| T1016 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_clkmgr_jitter.3692261059 |
|
|
Aug 28 01:39:41 AM UTC 24 |
Aug 28 01:44:21 AM UTC 24 |
3692067995 ps |
| T1017 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_alert_handler_lpg_reset_toggle.3474708236 |
|
|
Aug 28 01:16:06 AM UTC 24 |
Aug 28 01:45:08 AM UTC 24 |
8177945812 ps |
| T1018 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_clkmgr_reset_frequency.2705322795 |
|
|
Aug 28 01:37:52 AM UTC 24 |
Aug 28 01:45:20 AM UTC 24 |
3202550680 ps |
| T1019 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_tap_straps_dev.2410490929 |
|
|
Aug 28 01:43:31 AM UTC 24 |
Aug 28 01:46:01 AM UTC 24 |
3327294747 ps |
| T1020 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_clkmgr_external_clk_src_for_sw_slow_dev.276450851 |
|
|
Aug 28 01:36:50 AM UTC 24 |
Aug 28 01:46:10 AM UTC 24 |
4223841160 ps |
| T1021 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0.933299296 |
|
|
Aug 28 01:36:17 AM UTC 24 |
Aug 28 01:46:30 AM UTC 24 |
4701279850 ps |
| T1022 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0.2415802956 |
|
|
Aug 28 01:35:46 AM UTC 24 |
Aug 28 01:46:31 AM UTC 24 |
4134895224 ps |
| T329 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_plic_all_irqs_20.2280635851 |
|
|
Aug 28 01:32:26 AM UTC 24 |
Aug 28 01:46:38 AM UTC 24 |
5097062608 ps |
| T1023 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_clkmgr_external_clk_src_for_sw_slow_rma.3175523199 |
|
|
Aug 28 01:37:34 AM UTC 24 |
Aug 28 01:46:50 AM UTC 24 |
4587929080 ps |
| T120 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_pwrmgr_normal_sleep_all_wake_ups.3682348777 |
|
|
Aug 28 01:40:54 AM UTC 24 |
Aug 28 01:47:12 AM UTC 24 |
6542372960 ps |
| T1024 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_clkmgr_external_clk_src_for_sw_fast_dev.3540941144 |
|
|
Aug 28 01:36:33 AM UTC 24 |
Aug 28 01:47:31 AM UTC 24 |
4520226610 ps |
| T1025 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_clkmgr_jitter_frequency.1486166802 |
|
|
Aug 28 01:39:16 AM UTC 24 |
Aug 28 01:47:35 AM UTC 24 |
3931200680 ps |
| T354 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_pwrmgr_lowpower_cancel.3934768208 |
|
|
Aug 28 01:41:06 AM UTC 24 |
Aug 28 01:47:54 AM UTC 24 |
3518495296 ps |
| T386 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_rv_dm_ndm_reset_req.1457829137 |
|
|
Aug 28 01:42:45 AM UTC 24 |
Aug 28 01:47:55 AM UTC 24 |
3503204208 ps |
| T1026 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_pwrmgr_random_sleep_all_reset_reqs.3352420763 |
|
|
Aug 28 01:01:11 AM UTC 24 |
Aug 28 01:48:11 AM UTC 24 |
22949424747 ps |
| T1027 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_tap_straps_prod.763980078 |
|
|
Aug 28 01:44:50 AM UTC 24 |
Aug 28 01:48:15 AM UTC 24 |
2477516411 ps |
| T1028 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_clkmgr_sleep_frequency.2485666723 |
|
|
Aug 28 01:39:41 AM UTC 24 |
Aug 28 01:48:23 AM UTC 24 |
4372903208 ps |
| T1029 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_clkmgr_external_clk_src_for_sw_fast_rma.1585375938 |
|
|
Aug 28 01:37:34 AM UTC 24 |
Aug 28 01:48:26 AM UTC 24 |
4450730854 ps |
| T337 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_entropy_src_csrng.2880729138 |
|
|
Aug 28 01:20:37 AM UTC 24 |
Aug 28 01:49:00 AM UTC 24 |
7212473246 ps |
| T1030 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_hmac_multistream.1730412084 |
|
|
Aug 28 01:23:11 AM UTC 24 |
Aug 28 01:49:14 AM UTC 24 |
7183755722 ps |
| T92 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_tap_straps_rma.3465772358 |
|
|
Aug 28 01:43:45 AM UTC 24 |
Aug 28 01:49:18 AM UTC 24 |
4348458509 ps |
| T402 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_rv_core_ibex_lockstep_glitch.2993801601 |
|
|
Aug 28 01:45:57 AM UTC 24 |
Aug 28 01:49:41 AM UTC 24 |
2743989034 ps |
| T388 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up.4103244343 |
|
|
Aug 28 01:42:11 AM UTC 24 |
Aug 28 01:50:00 AM UTC 24 |
6713538440 ps |
| T1031 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_pwrmgr_sleep_wake_5_bug.957587001 |
|
|
Aug 28 01:42:14 AM UTC 24 |
Aug 28 01:50:06 AM UTC 24 |
5822572360 ps |
| T215 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_rv_core_ibex_address_translation.1540748082 |
|
|
Aug 28 01:45:53 AM UTC 24 |
Aug 28 01:50:18 AM UTC 24 |
2884082836 ps |
| T1032 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_clkmgr_jitter_reduced_freq.2051687990 |
|
|
Aug 28 01:47:34 AM UTC 24 |
Aug 28 01:50:32 AM UTC 24 |
2708035620 ps |
| T323 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_rv_dm_ndm_reset_req_when_cpu_halted.2355125712 |
|
|
Aug 28 01:42:46 AM UTC 24 |
Aug 28 01:50:48 AM UTC 24 |
5062698546 ps |
| T1033 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_rv_dm_access_after_wakeup.850703387 |
|
|
Aug 28 01:43:13 AM UTC 24 |
Aug 28 01:50:53 AM UTC 24 |
5836497480 ps |
| T312 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_rv_core_ibex_icache_invalidate.3025171517 |
|
|
Aug 28 01:46:50 AM UTC 24 |
Aug 28 01:50:56 AM UTC 24 |
3271739755 ps |
| T1034 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_alert_handler_lpg_clkoff.219327912 |
|
|
Aug 28 01:15:41 AM UTC 24 |
Aug 28 01:51:11 AM UTC 24 |
7810565520 ps |
| T1035 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_tap_straps_testunlock0.2971325389 |
|
|
Aug 28 01:43:32 AM UTC 24 |
Aug 28 01:51:21 AM UTC 24 |
5190632610 ps |
| T1036 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/default/0.rom_e2e_boot_policy_valid_a_bad_b_good_dev.150684977 |
|
|
Aug 27 11:37:22 PM UTC 24 |
Aug 28 01:51:34 AM UTC 24 |
24081283160 ps |
| T332 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_plic_all_irqs_0.3137363240 |
|
|
Aug 28 01:32:27 AM UTC 24 |
Aug 28 01:51:38 AM UTC 24 |
5621726868 ps |
| T1037 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_flash_ctrl_write_clear.339350703 |
|
|
Aug 28 01:47:46 AM UTC 24 |
Aug 28 01:51:55 AM UTC 24 |
3399438864 ps |
| T1038 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_hmac_enc_jitter_en_reduced_freq.2656301257 |
|
|
Aug 28 01:48:17 AM UTC 24 |
Aug 28 01:52:23 AM UTC 24 |
3415975094 ps |
| T1039 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_aes_enc_jitter_en_reduced_freq.3759201731 |
|
|
Aug 28 01:48:17 AM UTC 24 |
Aug 28 01:52:30 AM UTC 24 |
3339877474 ps |
| T203 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_lc_ctrl_program_error.3750525636 |
|
|
Aug 28 01:40:53 AM UTC 24 |
Aug 28 01:52:32 AM UTC 24 |
5855115668 ps |
| T1040 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_kmac_mode_kmac_jitter_en_reduced_freq.1485832449 |
|
|
Aug 28 01:49:17 AM UTC 24 |
Aug 28 01:53:57 AM UTC 24 |
3642156983 ps |
| T635 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_rv_dm_access_after_escalation_reset.553148344 |
|
|
Aug 28 01:43:13 AM UTC 24 |
Aug 28 01:54:44 AM UTC 24 |
6516221307 ps |
| T1041 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_ast_clk_outputs.1369905239 |
|
|
Aug 28 01:40:15 AM UTC 24 |
Aug 28 01:55:11 AM UTC 24 |
7250695220 ps |
| T1042 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_flash_scrambling_smoketest.956467851 |
|
|
Aug 28 01:51:52 AM UTC 24 |
Aug 28 01:55:20 AM UTC 24 |
3339640000 ps |
| T1043 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_flash_crash_alert.22979539 |
|
|
Aug 28 01:46:50 AM UTC 24 |
Aug 28 01:56:15 AM UTC 24 |
4762020682 ps |
| T640 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/default/1.rom_volatile_raw_unlock.74084111 |
|
|
Aug 28 01:54:56 AM UTC 24 |
Aug 28 01:57:27 AM UTC 24 |
3134831937 ps |
| T1044 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_clkmgr_off_peri.3430575414 |
|
|
Aug 28 01:32:51 AM UTC 24 |
Aug 28 01:57:59 AM UTC 24 |
12133662520 ps |
| T1045 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_edn_sw_mode.3208556316 |
|
|
Aug 28 01:19:09 AM UTC 24 |
Aug 28 01:58:21 AM UTC 24 |
10716695374 ps |
| T1046 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_power_sleep_load.4150812296 |
|
|
Aug 28 01:49:48 AM UTC 24 |
Aug 28 01:58:44 AM UTC 24 |
10933121480 ps |
| T1047 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_flash_ctrl_ops_jitter_en_reduced_freq.2607356156 |
|
|
Aug 28 01:47:51 AM UTC 24 |
Aug 28 01:58:51 AM UTC 24 |
5173159853 ps |
| T100 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_jtag_csr_rw.1917844808 |
|
|
Aug 28 01:39:22 AM UTC 24 |
Aug 28 01:59:02 AM UTC 24 |
10484716730 ps |
| T185 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/default/1.rom_raw_unlock.3353787831 |
|
|
Aug 28 01:54:23 AM UTC 24 |
Aug 28 01:59:22 AM UTC 24 |
6552337026 ps |
| T298 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq.1336712491 |
|
|
Aug 28 01:49:23 AM UTC 24 |
Aug 28 02:00:05 AM UTC 24 |
4702542551 ps |
| T231 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_jtag_mem_access.3742767189 |
|
|
Aug 28 01:39:44 AM UTC 24 |
Aug 28 02:00:07 AM UTC 24 |
13726103500 ps |
| T1048 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_aes_smoketest.1680559124 |
|
|
Aug 28 01:55:56 AM UTC 24 |
Aug 28 02:00:11 AM UTC 24 |
2733907228 ps |
| T1049 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_power_idle_load.3894820978 |
|
|
Aug 28 01:49:33 AM UTC 24 |
Aug 28 02:01:09 AM UTC 24 |
4499937154 ps |
| T1050 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_clkmgr_smoketest.2047217264 |
|
|
Aug 28 01:56:51 AM UTC 24 |
Aug 28 02:01:15 AM UTC 24 |
2617735420 ps |
| T1051 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_aon_timer_smoketest.934352563 |
|
|
Aug 28 01:55:57 AM UTC 24 |
Aug 28 02:01:31 AM UTC 24 |
2963098748 ps |
| T1052 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_keymgr_key_derivation_jitter_en.3898440567 |
|
|
Aug 28 01:24:19 AM UTC 24 |
Aug 28 02:01:52 AM UTC 24 |
12318329307 ps |
| T1053 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_csrng_smoketest.4283848136 |
|
|
Aug 28 01:58:03 AM UTC 24 |
Aug 28 02:02:33 AM UTC 24 |
2434263320 ps |
| T1054 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_keymgr_sideload_kmac.2654535419 |
|
|
Aug 28 01:24:23 AM UTC 24 |
Aug 28 02:03:31 AM UTC 24 |
13167438520 ps |
| T1055 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_keymgr_key_derivation_jitter_en_reduced_freq.4124027302 |
|
|
Aug 28 01:48:52 AM UTC 24 |
Aug 28 02:04:07 AM UTC 24 |
6584267394 ps |
| T1056 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_gpio_smoketest.2281463707 |
|
|
Aug 28 01:58:56 AM UTC 24 |
Aug 28 02:04:15 AM UTC 24 |
3386885174 ps |
| T1057 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_hmac_smoketest.3035565533 |
|
|
Aug 28 01:59:43 AM UTC 24 |
Aug 28 02:04:15 AM UTC 24 |
3268811696 ps |
| T125 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_pwrmgr_random_sleep_all_wake_ups.1792536811 |
|
|
Aug 28 01:42:12 AM UTC 24 |
Aug 28 02:04:35 AM UTC 24 |
22985880104 ps |
| T1058 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/default/1.rom_keymgr_functest.3287647141 |
|
|
Aug 28 01:55:20 AM UTC 24 |
Aug 28 02:04:49 AM UTC 24 |
4738897880 ps |
| T1059 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_kmac_smoketest.556254737 |
|
|
Aug 28 01:59:41 AM UTC 24 |
Aug 28 02:05:17 AM UTC 24 |
3132249526 ps |
| T1060 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_sram_ctrl_smoketest.1241252755 |
|
|
Aug 28 02:02:09 AM UTC 24 |
Aug 28 02:05:51 AM UTC 24 |
3115153980 ps |
| T1061 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_rv_plic_smoketest.3085409232 |
|
|
Aug 28 02:01:02 AM UTC 24 |
Aug 28 02:06:05 AM UTC 24 |
3509120360 ps |
| T1062 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_example_rom.2788029477 |
|
|
Aug 28 02:04:01 AM UTC 24 |
Aug 28 02:06:06 AM UTC 24 |
2226738830 ps |
| T1063 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_rstmgr_smoketest.1693648137 |
|
|
Aug 28 02:01:56 AM UTC 24 |
Aug 28 02:06:06 AM UTC 24 |
2489734768 ps |
| T1064 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_keymgr_key_derivation_prod.2448190786 |
|
|
Aug 28 01:23:27 AM UTC 24 |
Aug 28 02:06:13 AM UTC 24 |
12214408928 ps |
| T1065 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_rv_timer_smoketest.1190999619 |
|
|
Aug 28 02:01:56 AM UTC 24 |
Aug 28 02:06:15 AM UTC 24 |
3102952016 ps |
| T1066 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_pwrmgr_random_sleep_power_glitch_reset.4185789893 |
|
|
Aug 28 01:01:49 AM UTC 24 |
Aug 28 02:06:16 AM UTC 24 |
44175052274 ps |
| T1067 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_otp_ctrl_smoketest.3340956435 |
|
|
Aug 28 01:59:56 AM UTC 24 |
Aug 28 02:07:10 AM UTC 24 |
2817090134 ps |
| T1068 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_uart_smoketest.637664909 |
|
|
Aug 28 02:02:24 AM UTC 24 |
Aug 28 02:07:14 AM UTC 24 |
3176019224 ps |
| T1069 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_example_flash.3877129465 |
|
|
Aug 28 02:03:09 AM UTC 24 |
Aug 28 02:07:59 AM UTC 24 |
2568184352 ps |
| T1070 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_example_manufacturer.3424285202 |
|
|
Aug 28 02:05:14 AM UTC 24 |
Aug 28 02:08:17 AM UTC 24 |
3405212760 ps |
| T1071 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_entropy_src_smoketest.400301068 |
|
|
Aug 28 01:58:34 AM UTC 24 |
Aug 28 02:08:17 AM UTC 24 |
3952892656 ps |
| T1072 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_pwrmgr_usbdev_smoketest.218050384 |
|
|
Aug 28 02:01:04 AM UTC 24 |
Aug 28 02:08:25 AM UTC 24 |
5386878512 ps |
| T1073 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_flash_ctrl_access_jitter_en_reduced_freq.2004696685 |
|
|
Aug 28 01:47:49 AM UTC 24 |
Aug 28 02:08:26 AM UTC 24 |
7183402725 ps |
| T1074 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_pwrmgr_smoketest.2372919220 |
|
|
Aug 28 02:01:00 AM UTC 24 |
Aug 28 02:08:38 AM UTC 24 |
4936386272 ps |
| T1075 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_flash_ctrl_mem_protection.2692180618 |
|
|
Aug 28 01:53:00 AM UTC 24 |
Aug 28 02:09:16 AM UTC 24 |
5464172200 ps |
| T423 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_pwrmgr_deep_sleep_all_wake_ups.605453510 |
|
|
Aug 28 01:42:06 AM UTC 24 |
Aug 28 02:10:08 AM UTC 24 |
22899831102 ps |
| T1076 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_example_concurrency.563735575 |
|
|
Aug 28 02:05:25 AM UTC 24 |
Aug 28 02:10:14 AM UTC 24 |
3491671372 ps |
| T1077 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_keymgr_key_derivation.1348330036 |
|
|
Aug 28 01:23:26 AM UTC 24 |
Aug 28 02:10:21 AM UTC 24 |
12405376084 ps |
| T1078 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sival_flash_info_access.3633987859 |
|
|
Aug 28 02:05:14 AM UTC 24 |
Aug 28 02:10:25 AM UTC 24 |
2941464600 ps |
| T1079 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_pattgen_ios.2563356927 |
|
|
Aug 28 02:07:54 AM UTC 24 |
Aug 28 02:11:03 AM UTC 24 |
2761091272 ps |