| T1080 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_pwrmgr_b2b_sleep_reset_req.1256446645 |
|
|
Aug 28 01:30:57 AM UTC 24 |
Aug 28 02:11:05 AM UTC 24 |
26039511315 ps |
| T1081 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_sysrst_ctrl_ec_rst_l.374063490 |
|
|
Aug 28 01:06:16 AM UTC 24 |
Aug 28 02:11:26 AM UTC 24 |
20715131281 ps |
| T21 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_sleep_pin_mio_dio_val.2241947700 |
|
|
Aug 28 02:06:36 AM UTC 24 |
Aug 28 02:11:30 AM UTC 24 |
3683336072 ps |
| T78 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_sleep_pin_retention.1534532727 |
|
|
Aug 28 02:08:06 AM UTC 24 |
Aug 28 02:13:15 AM UTC 24 |
3614545016 ps |
| T1082 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_csrng_edn_concurrency.270538339 |
|
|
Aug 28 01:19:14 AM UTC 24 |
Aug 28 02:14:01 AM UTC 24 |
12543803792 ps |
| T684 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_all_escalation_resets.3913796809 |
|
|
Aug 28 02:05:30 AM UTC 24 |
Aug 28 02:14:15 AM UTC 24 |
5458418302 ps |
| T46 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_spi_host_tx_rx.2146384123 |
|
|
Aug 28 02:11:48 AM UTC 24 |
Aug 28 02:16:22 AM UTC 24 |
3046957528 ps |
| T80 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_spi_device_pinmux_sleep_retention.393519777 |
|
|
Aug 28 02:11:49 AM UTC 24 |
Aug 28 02:16:23 AM UTC 24 |
3084710141 ps |
| T71 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_sleep_pin_wake.948145209 |
|
|
Aug 28 02:08:00 AM UTC 24 |
Aug 28 02:16:37 AM UTC 24 |
7219590362 ps |
| T292 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_data_integrity_escalation.1895942279 |
|
|
Aug 28 02:05:54 AM UTC 24 |
Aug 28 02:16:47 AM UTC 24 |
5080441170 ps |
| T435 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_rstmgr_rst_cnsty_escalation.3227725724 |
|
|
Aug 28 02:05:29 AM UTC 24 |
Aug 28 02:17:03 AM UTC 24 |
4682508088 ps |
| T349 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_uart_tx_rx_idx2.1983484531 |
|
|
Aug 28 02:08:07 AM UTC 24 |
Aug 28 02:17:30 AM UTC 24 |
3605689018 ps |
| T365 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_uart_tx_rx_idx1.2951212562 |
|
|
Aug 28 02:07:58 AM UTC 24 |
Aug 28 02:18:12 AM UTC 24 |
4586949936 ps |
| T50 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_spi_device_tpm.1354216927 |
|
|
Aug 28 02:11:16 AM UTC 24 |
Aug 28 02:18:45 AM UTC 24 |
3829737197 ps |
| T436 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_uart_tx_rx.3207008016 |
|
|
Aug 28 02:07:31 AM UTC 24 |
Aug 28 02:19:25 AM UTC 24 |
4523656004 ps |
| T437 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_uart_tx_rx_idx3.3062018130 |
|
|
Aug 28 02:08:10 AM UTC 24 |
Aug 28 02:19:30 AM UTC 24 |
4369403790 ps |
| T129 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_power_virus.1515127036 |
|
|
Aug 28 01:54:01 AM UTC 24 |
Aug 28 02:19:34 AM UTC 24 |
6219539856 ps |
| T438 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_otbn_ecdsa_op_irq_jitter_en.3336544333 |
|
|
Aug 28 01:11:01 AM UTC 24 |
Aug 28 02:19:45 AM UTC 24 |
18997153634 ps |
| T229 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_spi_device_pass_through_collision.2326813005 |
|
|
Aug 28 02:12:14 AM UTC 24 |
Aug 28 02:20:20 AM UTC 24 |
4378688858 ps |
| T253 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_flash_init_reduced_freq.437371467 |
|
|
Aug 28 01:49:11 AM UTC 24 |
Aug 28 02:20:22 AM UTC 24 |
23853343925 ps |
| T41 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_gpio.2423843575 |
|
|
Aug 28 02:13:51 AM UTC 24 |
Aug 28 02:21:04 AM UTC 24 |
3733807915 ps |
| T230 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_spi_device_pass_through.4248417579 |
|
|
Aug 28 02:12:14 AM UTC 24 |
Aug 28 02:21:24 AM UTC 24 |
5996240262 ps |
| T353 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_i2c_device_tx_rx.2123202847 |
|
|
Aug 28 02:11:13 AM UTC 24 |
Aug 28 02:21:30 AM UTC 24 |
3793373490 ps |
| T1083 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_otbn_ecdsa_op_irq.2829412088 |
|
|
Aug 28 01:10:04 AM UTC 24 |
Aug 28 02:21:38 AM UTC 24 |
17606151668 ps |
| T1084 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_flash_rma_unlocked.3206414978 |
|
|
Aug 28 12:52:08 AM UTC 24 |
Aug 28 02:22:19 AM UTC 24 |
44559817531 ps |
| T1085 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_flash_ctrl_idle_low_power.4265568590 |
|
|
Aug 28 02:17:36 AM UTC 24 |
Aug 28 02:22:36 AM UTC 24 |
3244463148 ps |
| T1086 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_i2c_host_tx_rx.3433563807 |
|
|
Aug 28 02:09:55 AM UTC 24 |
Aug 28 02:22:52 AM UTC 24 |
5449875962 ps |
| T1087 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_kmac_entropy.3387613480 |
|
|
Aug 28 02:18:48 AM UTC 24 |
Aug 28 02:23:29 AM UTC 24 |
2996125920 ps |
| T1088 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_lc_ctrl_otp_hw_cfg0.2551504007 |
|
|
Aug 28 02:19:19 AM UTC 24 |
Aug 28 02:24:11 AM UTC 24 |
2793033720 ps |
| T195 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_otp_ctrl_vendor_test_csr_access.2279160703 |
|
|
Aug 28 02:21:05 AM UTC 24 |
Aug 28 02:24:48 AM UTC 24 |
2828690168 ps |
| T352 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_i2c_host_tx_rx_idx2.2133704422 |
|
|
Aug 28 02:11:14 AM UTC 24 |
Aug 28 02:24:55 AM UTC 24 |
5153165112 ps |
| T1089 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_lc_ctrl_volatile_raw_unlock.2215708163 |
|
|
Aug 28 02:23:11 AM UTC 24 |
Aug 28 02:25:07 AM UTC 24 |
2551226947 ps |
| T351 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_i2c_host_tx_rx_idx1.222218232 |
|
|
Aug 28 02:11:10 AM UTC 24 |
Aug 28 02:25:49 AM UTC 24 |
4748964032 ps |
| T255 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_flash_ctrl_lc_rw_en.79029809 |
|
|
Aug 28 02:15:26 AM UTC 24 |
Aug 28 02:25:53 AM UTC 24 |
5350125790 ps |
| T1090 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz.2646464686 |
|
|
Aug 28 02:23:26 AM UTC 24 |
Aug 28 02:26:09 AM UTC 24 |
2539540620 ps |
| T362 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_flash_ctrl_ops_jitter_en.811156665 |
|
|
Aug 28 02:14:53 AM UTC 24 |
Aug 28 02:26:22 AM UTC 24 |
5030843860 ps |
| T1091 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_otp_ctrl_ecc_error_vendor_test.3792171482 |
|
|
Aug 28 02:21:06 AM UTC 24 |
Aug 28 02:26:55 AM UTC 24 |
3016896104 ps |
| T369 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_flash_ctrl_ops.2410448963 |
|
|
Aug 28 02:14:49 AM UTC 24 |
Aug 28 02:26:58 AM UTC 24 |
4054342358 ps |
| T1092 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/default/0.rom_e2e_self_hash.3857803174 |
|
|
Aug 28 12:19:34 AM UTC 24 |
Aug 28 02:27:04 AM UTC 24 |
27028579584 ps |
| T1093 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_lc_ctrl_rand_to_scrap.831902563 |
|
|
Aug 28 02:22:21 AM UTC 24 |
Aug 28 02:27:14 AM UTC 24 |
3427675071 ps |
| T1094 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_rstmgr_sw_rst.685341319 |
|
|
Aug 28 02:25:45 AM UTC 24 |
Aug 28 02:30:09 AM UTC 24 |
3438402992 ps |
| T1095 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_otbn_smoketest.3978660559 |
|
|
Aug 28 01:59:44 AM UTC 24 |
Aug 28 02:30:25 AM UTC 24 |
7630373342 ps |
| T247 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_keymgr_sideload_otbn.3931412006 |
|
|
Aug 28 01:25:22 AM UTC 24 |
Aug 28 02:31:36 AM UTC 24 |
13495736628 ps |
| T1096 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_uart_rand_baudrate.514307002 |
|
|
Aug 28 02:09:33 AM UTC 24 |
Aug 28 02:31:54 AM UTC 24 |
7925713560 ps |
| T1097 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_sleep_pwm_pulses.3245632915 |
|
|
Aug 28 02:08:06 AM UTC 24 |
Aug 28 02:32:02 AM UTC 24 |
8410238680 ps |
| T1098 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_otp_ctrl_lc_signals_test_unlocked0.3951655943 |
|
|
Aug 28 02:20:24 AM UTC 24 |
Aug 28 02:32:38 AM UTC 24 |
4290311192 ps |
| T1099 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_rstmgr_sw_req.1976154492 |
|
|
Aug 28 02:25:42 AM UTC 24 |
Aug 28 02:32:43 AM UTC 24 |
4397896734 ps |
| T1100 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_pwrmgr_main_power_glitch_reset.2966298671 |
|
|
Aug 28 02:26:54 AM UTC 24 |
Aug 28 02:33:11 AM UTC 24 |
3786969650 ps |
| T257 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_lc_walkthrough_prod.2440323243 |
|
|
Aug 28 12:56:22 AM UTC 24 |
Aug 28 02:34:18 AM UTC 24 |
49231758700 ps |
| T1101 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_flash_ctrl_access.2342108488 |
|
|
Aug 28 02:17:24 AM UTC 24 |
Aug 28 02:34:42 AM UTC 24 |
5923974800 ps |
| T1102 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_pwrmgr_full_aon_reset.1359761793 |
|
|
Aug 28 02:26:41 AM UTC 24 |
Aug 28 02:35:20 AM UTC 24 |
9335105420 ps |
| T1103 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_flash_ctrl_clock_freqs.2475634068 |
|
|
Aug 28 02:18:05 AM UTC 24 |
Aug 28 02:35:26 AM UTC 24 |
5456602119 ps |
| T262 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_rstmgr_cpu_info.3234447615 |
|
|
Aug 28 02:26:41 AM UTC 24 |
Aug 28 02:35:31 AM UTC 24 |
4947395544 ps |
| T251 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_lc_walkthrough_rma.829480020 |
|
|
Aug 28 12:56:37 AM UTC 24 |
Aug 28 02:35:51 AM UTC 24 |
44953713556 ps |
| T1104 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_flash_ctrl_access_jitter_en.3613833045 |
|
|
Aug 28 02:17:37 AM UTC 24 |
Aug 28 02:36:12 AM UTC 24 |
5900120548 ps |
| T1105 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_lc_ctrl_transition.3311115257 |
|
|
Aug 28 02:21:39 AM UTC 24 |
Aug 28 02:37:39 AM UTC 24 |
11265992497 ps |
| T1106 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_otp_ctrl_lc_signals_dev.3379773340 |
|
|
Aug 28 02:20:40 AM UTC 24 |
Aug 28 02:38:09 AM UTC 24 |
6789116616 ps |
| T1107 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_rv_timer_irq.453811430 |
|
|
Aug 28 02:33:46 AM UTC 24 |
Aug 28 02:38:18 AM UTC 24 |
2663404350 ps |
| T1108 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_pwrmgr_sleep_disabled.1561761126 |
|
|
Aug 28 02:33:24 AM UTC 24 |
Aug 28 02:38:25 AM UTC 24 |
3291617036 ps |
| T1109 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_pwrmgr_deep_sleep_power_glitch_reset.1452646069 |
|
|
Aug 28 02:32:42 AM UTC 24 |
Aug 28 02:39:36 AM UTC 24 |
6362551580 ps |
| T1110 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_pwrmgr_normal_sleep_por_reset.2204757272 |
|
|
Aug 28 02:30:59 AM UTC 24 |
Aug 28 02:39:50 AM UTC 24 |
7336513592 ps |
| T1111 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_uart_tx_rx_alt_clk_freq_low_speed.3338700158 |
|
|
Aug 28 02:09:41 AM UTC 24 |
Aug 28 02:39:51 AM UTC 24 |
13421370383 ps |
| T1112 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_otp_ctrl_lc_signals_rma.447435575 |
|
|
Aug 28 02:20:24 AM UTC 24 |
Aug 28 02:40:24 AM UTC 24 |
7779939000 ps |
| T1113 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_uart_tx_rx_alt_clk_freq.2802300274 |
|
|
Aug 28 02:09:41 AM UTC 24 |
Aug 28 02:40:34 AM UTC 24 |
8905807756 ps |
| T1114 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_lc_walkthrough_prodend.448755900 |
|
|
Aug 28 02:22:53 AM UTC 24 |
Aug 28 02:41:18 AM UTC 24 |
10229166140 ps |
| T1115 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_sysrst_ctrl_inputs.3443548527 |
|
|
Aug 28 02:35:18 AM UTC 24 |
Aug 28 02:41:46 AM UTC 24 |
2904157714 ps |
| T1116 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_otp_ctrl_lc_signals_prod.753197855 |
|
|
Aug 28 02:20:42 AM UTC 24 |
Aug 28 02:42:12 AM UTC 24 |
8269961886 ps |
| T1117 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_pwrmgr_deep_sleep_por_reset.2150615531 |
|
|
Aug 28 02:30:45 AM UTC 24 |
Aug 28 02:42:20 AM UTC 24 |
8961550316 ps |
| T1118 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_pwrmgr_usb_clk_disabled_when_active.2374105683 |
|
|
Aug 28 02:33:24 AM UTC 24 |
Aug 28 02:42:30 AM UTC 24 |
4773253316 ps |
| T1119 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_pwrmgr_sysrst_ctrl_reset.3162962103 |
|
|
Aug 28 02:26:57 AM UTC 24 |
Aug 28 02:42:50 AM UTC 24 |
7600406813 ps |
| T1120 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_sysrst_ctrl_outputs.2659013230 |
|
|
Aug 28 02:36:32 AM UTC 24 |
Aug 28 02:43:28 AM UTC 24 |
3918368768 ps |
| T368 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_aon_timer_irq.2862899873 |
|
|
Aug 28 02:36:50 AM UTC 24 |
Aug 28 02:44:53 AM UTC 24 |
4280627380 ps |
| T1121 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/default/1.rom_e2e_asm_init_test_unlocked0.961198638 |
|
|
Aug 28 01:53:59 AM UTC 24 |
Aug 28 02:45:57 AM UTC 24 |
10830449742 ps |
| T48 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_sysrst_ctrl_ulp_z3_wakeup.4107616310 |
|
|
Aug 28 02:36:30 AM UTC 24 |
Aug 28 02:47:12 AM UTC 24 |
6910401126 ps |
| T1122 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_aon_timer_wdog_lc_escalate.1750381269 |
|
|
Aug 28 02:39:07 AM UTC 24 |
Aug 28 02:47:12 AM UTC 24 |
4616924208 ps |
| T1123 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_aes_enc.2306769418 |
|
|
Aug 28 02:43:09 AM UTC 24 |
Aug 28 02:47:30 AM UTC 24 |
3124028908 ps |
| T1124 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_aes_idle.2124184647 |
|
|
Aug 28 02:43:11 AM UTC 24 |
Aug 28 02:47:33 AM UTC 24 |
3318272344 ps |
| T1125 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_aon_timer_sleep_wdog_sleep_pause.3269975969 |
|
|
Aug 28 02:38:14 AM UTC 24 |
Aug 28 02:47:49 AM UTC 24 |
7297191520 ps |
| T1126 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_adc_ctrl_sleep_debug_cable_wakeup.1636035474 |
|
|
Aug 28 02:40:12 AM UTC 24 |
Aug 28 02:47:54 AM UTC 24 |
18745141378 ps |
| T1127 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_sysrst_ctrl_in_irq.3388715047 |
|
|
Aug 28 02:36:32 AM UTC 24 |
Aug 28 02:47:58 AM UTC 24 |
4793959127 ps |
| T1128 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_pwrmgr_wdog_reset.1097781889 |
|
|
Aug 28 02:39:08 AM UTC 24 |
Aug 28 02:48:42 AM UTC 24 |
4904502668 ps |
| T1129 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_aes_enc_jitter_en.2155088204 |
|
|
Aug 28 02:43:10 AM UTC 24 |
Aug 28 02:49:14 AM UTC 24 |
3050069768 ps |
| T1130 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_aes_masking_off.3210686228 |
|
|
Aug 28 02:43:24 AM UTC 24 |
Aug 28 02:50:06 AM UTC 24 |
3241111075 ps |
| T299 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_otbn_mem_scramble.2590208131 |
|
|
Aug 28 02:41:11 AM UTC 24 |
Aug 28 02:50:14 AM UTC 24 |
3716733002 ps |
| T1131 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_flash_init.4140917825 |
|
|
Aug 28 02:17:34 AM UTC 24 |
Aug 28 02:50:21 AM UTC 24 |
17616049020 ps |
| T77 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_alert_test.200800846 |
|
|
Aug 28 02:44:06 AM UTC 24 |
Aug 28 02:50:33 AM UTC 24 |
3215783140 ps |
| T1132 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_aon_timer_wdog_bite_reset.1517128431 |
|
|
Aug 28 02:39:06 AM UTC 24 |
Aug 28 02:51:26 AM UTC 24 |
9504166288 ps |
| T1133 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_pwrmgr_normal_sleep_all_reset_reqs.3818437843 |
|
|
Aug 28 02:28:06 AM UTC 24 |
Aug 28 02:52:00 AM UTC 24 |
13538304746 ps |
| T1134 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_otbn_randomness.3824588789 |
|
|
Aug 28 02:40:37 AM UTC 24 |
Aug 28 02:52:48 AM UTC 24 |
5836406908 ps |
| T1135 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_alert_handler_escalation.2850189249 |
|
|
Aug 28 02:45:30 AM UTC 24 |
Aug 28 02:53:39 AM UTC 24 |
4169393062 ps |
| T1136 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_lc_walkthrough_dev.491389267 |
|
|
Aug 28 12:56:30 AM UTC 24 |
Aug 28 02:53:42 AM UTC 24 |
50875551475 ps |
| T1137 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_entropy_src_kat_test.239950108 |
|
|
Aug 28 02:49:49 AM UTC 24 |
Aug 28 02:53:48 AM UTC 24 |
2868484892 ps |
| T1138 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_pwrmgr_all_reset_reqs.674805209 |
|
|
Aug 28 02:27:58 AM UTC 24 |
Aug 28 02:53:55 AM UTC 24 |
12951427023 ps |
| T1139 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_aes_entropy.2843026929 |
|
|
Aug 28 02:49:16 AM UTC 24 |
Aug 28 02:54:17 AM UTC 24 |
3067974336 ps |
| T669 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_rv_core_ibex_nmi_irq.3748608168 |
|
|
Aug 28 02:42:23 AM UTC 24 |
Aug 28 02:54:43 AM UTC 24 |
4950367834 ps |
| T1140 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_pwrmgr_deep_sleep_all_reset_reqs.1140065257 |
|
|
Aug 28 02:28:05 AM UTC 24 |
Aug 28 02:54:54 AM UTC 24 |
15394321923 ps |
| T1141 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_alert_handler_entropy.2690518400 |
|
|
Aug 28 02:49:01 AM UTC 24 |
Aug 28 02:55:03 AM UTC 24 |
3875592857 ps |
| T721 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_alert_handler_lpg_sleep_mode_alerts.3001563500 |
|
|
Aug 28 02:48:32 AM UTC 24 |
Aug 28 02:55:05 AM UTC 24 |
3954411636 ps |
| T1142 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_alert_handler_ping_timeout.3108065142 |
|
|
Aug 28 02:46:33 AM UTC 24 |
Aug 28 02:55:45 AM UTC 24 |
4620006952 ps |
| T1143 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_csrng_kat_test.1919204876 |
|
|
Aug 28 02:53:24 AM UTC 24 |
Aug 28 02:57:19 AM UTC 24 |
2653094268 ps |
| T633 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq.552544579 |
|
|
Aug 28 01:47:52 AM UTC 24 |
Aug 28 02:57:28 AM UTC 24 |
24781918824 ps |
| T1144 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_rv_core_ibex_rnd.3303596589 |
|
|
Aug 28 02:41:51 AM UTC 24 |
Aug 28 02:57:58 AM UTC 24 |
5518489864 ps |
| T347 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_rstmgr_alert_info.742215737 |
|
|
Aug 28 02:25:46 AM UTC 24 |
Aug 28 02:58:00 AM UTC 24 |
14798193206 ps |
| T1145 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_entropy_src_ast_rng_req.2841154829 |
|
|
Aug 28 02:55:05 AM UTC 24 |
Aug 28 02:58:23 AM UTC 24 |
2261047922 ps |
| T1146 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/default/1.rom_e2e_smoke.3348862197 |
|
|
Aug 28 01:53:05 AM UTC 24 |
Aug 28 02:59:40 AM UTC 24 |
15250006950 ps |
| T1147 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_hmac_enc_idle.110478306 |
|
|
Aug 28 02:55:50 AM UTC 24 |
Aug 28 03:00:10 AM UTC 24 |
2762298400 ps |
| T1148 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_hmac_enc_jitter_en.1993348179 |
|
|
Aug 28 02:55:53 AM UTC 24 |
Aug 28 03:00:35 AM UTC 24 |
2490214835 ps |
| T628 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_edn_boot_mode.3214394217 |
|
|
Aug 28 02:51:10 AM UTC 24 |
Aug 28 03:00:45 AM UTC 24 |
2867653628 ps |
| T1149 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_csrng_lc_hw_debug_en_test.2775305751 |
|
|
Aug 28 02:52:03 AM UTC 24 |
Aug 28 03:00:47 AM UTC 24 |
6584828088 ps |
| T1150 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_hmac_oneshot.1936111916 |
|
|
Aug 28 02:55:54 AM UTC 24 |
Aug 28 03:01:15 AM UTC 24 |
3375511352 ps |
| T1151 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_edn_kat.2534963983 |
|
|
Aug 28 02:51:10 AM UTC 24 |
Aug 28 03:01:59 AM UTC 24 |
3137494792 ps |
| T1152 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_hmac_enc.1833926277 |
|
|
Aug 28 02:55:40 AM UTC 24 |
Aug 28 03:02:01 AM UTC 24 |
2877280996 ps |
| T1153 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/default/1.rom_e2e_shutdown_exception_c.399266989 |
|
|
Aug 28 01:54:03 AM UTC 24 |
Aug 28 03:02:16 AM UTC 24 |
14379928734 ps |
| T1154 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_lc_walkthrough_testunlocks.4051323911 |
|
|
Aug 28 02:24:46 AM UTC 24 |
Aug 28 03:02:27 AM UTC 24 |
32728616329 ps |
| T1155 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/default/1.rom_e2e_shutdown_output.3505416283 |
|
|
Aug 28 01:54:22 AM UTC 24 |
Aug 28 03:02:54 AM UTC 24 |
26028864281 ps |
| T1156 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/default/1.rom_e2e_keymgr_init_rom_ext_no_meas.199529072 |
|
|
Aug 28 01:54:43 AM UTC 24 |
Aug 28 03:03:17 AM UTC 24 |
15381407570 ps |
| T1157 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_sysrst_ctrl_reset.3600223715 |
|
|
Aug 28 02:36:44 AM UTC 24 |
Aug 28 03:04:01 AM UTC 24 |
24792933436 ps |
| T1158 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_csrng_fuse_en_sw_app_read_test.2790449708 |
|
|
Aug 28 02:54:58 AM UTC 24 |
Aug 28 03:04:03 AM UTC 24 |
4878354310 ps |
| T1159 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/default/1.rom_e2e_asm_init_prod.108388725 |
|
|
Aug 28 01:54:04 AM UTC 24 |
Aug 28 03:04:24 AM UTC 24 |
14809586991 ps |
| T1160 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_edn_auto_mode.1175478834 |
|
|
Aug 28 02:50:57 AM UTC 24 |
Aug 28 03:04:34 AM UTC 24 |
4666896680 ps |
| T1161 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_kmac_mode_cshake.2548984707 |
|
|
Aug 28 03:00:15 AM UTC 24 |
Aug 28 03:04:50 AM UTC 24 |
3072703864 ps |
| T1162 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/default/1.rom_e2e_keymgr_init_rom_ext_invalid_meas.2807081976 |
|
|
Aug 28 01:54:23 AM UTC 24 |
Aug 28 03:05:19 AM UTC 24 |
14871889416 ps |
| T1163 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_kmac_app_rom.3810864780 |
|
|
Aug 28 03:01:31 AM UTC 24 |
Aug 28 03:05:45 AM UTC 24 |
3009044288 ps |
| T1164 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_kmac_idle.145297681 |
|
|
Aug 28 03:01:31 AM UTC 24 |
Aug 28 03:05:52 AM UTC 24 |
2516907400 ps |
| T1165 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_kmac_mode_kmac.16364486 |
|
|
Aug 28 03:00:44 AM UTC 24 |
Aug 28 03:06:13 AM UTC 24 |
3228700198 ps |
| T1166 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_kmac_mode_kmac_jitter_en.312207845 |
|
|
Aug 28 03:01:34 AM UTC 24 |
Aug 28 03:06:31 AM UTC 24 |
3057623182 ps |
| T1167 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/default/1.rom_e2e_asm_init_prod_end.3920534712 |
|
|
Aug 28 01:55:00 AM UTC 24 |
Aug 28 03:06:41 AM UTC 24 |
15732519173 ps |
| T1168 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/default/1.rom_e2e_asm_init_dev.2916962328 |
|
|
Aug 28 01:53:21 AM UTC 24 |
Aug 28 03:06:41 AM UTC 24 |
15233026276 ps |
| T1169 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/default/1.rom_e2e_asm_init_rma.3076969945 |
|
|
Aug 28 01:54:58 AM UTC 24 |
Aug 28 03:06:55 AM UTC 24 |
14757145924 ps |
| T361 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_sensor_ctrl_status.3400831012 |
|
|
Aug 28 03:03:57 AM UTC 24 |
Aug 28 03:07:35 AM UTC 24 |
3172603437 ps |
| T1170 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_edn_sw_mode.1897998187 |
|
|
Aug 28 02:51:13 AM UTC 24 |
Aug 28 03:08:56 AM UTC 24 |
5744083366 ps |
| T1171 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_pwrmgr_random_sleep_all_reset_reqs.3454184913 |
|
|
Aug 28 02:28:07 AM UTC 24 |
Aug 28 03:09:54 AM UTC 24 |
27362321675 ps |
| T1172 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_sleep_sram_ret_contents_no_scramble.3042882938 |
|
|
Aug 28 03:03:08 AM UTC 24 |
Aug 28 03:10:49 AM UTC 24 |
6155360320 ps |
| T1173 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_alert_handler_lpg_sleep_mode_pings.747514932 |
|
|
Aug 28 02:48:42 AM UTC 24 |
Aug 28 03:10:51 AM UTC 24 |
13247326920 ps |
| T1174 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_edn_entropy_reqs_jitter.808630471 |
|
|
Aug 28 02:55:05 AM UTC 24 |
Aug 28 03:11:23 AM UTC 24 |
5487547247 ps |
| T300 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_sram_ctrl_scrambled_access.1892421113 |
|
|
Aug 28 03:03:03 AM UTC 24 |
Aug 28 03:11:29 AM UTC 24 |
4273970136 ps |
| T1175 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/default/1.rom_e2e_keymgr_init_rom_ext_meas.992158182 |
|
|
Aug 28 01:54:44 AM UTC 24 |
Aug 28 03:11:32 AM UTC 24 |
14957317264 ps |
| T422 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_rom_ctrl_integrity_check.4243272667 |
|
|
Aug 28 03:01:50 AM UTC 24 |
Aug 28 03:11:38 AM UTC 24 |
9804982104 ps |
| T1176 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_alert_handler_ping_ok.3591566817 |
|
|
Aug 28 02:48:33 AM UTC 24 |
Aug 28 03:11:45 AM UTC 24 |
7468416528 ps |
| T275 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_plic_sw_irq.3889928249 |
|
|
Aug 28 03:05:53 AM UTC 24 |
Aug 28 03:12:04 AM UTC 24 |
3031154002 ps |
| T1177 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_clkmgr_off_hmac_trans.2410552935 |
|
|
Aug 28 03:06:49 AM UTC 24 |
Aug 28 03:12:07 AM UTC 24 |
5037900224 ps |
| T615 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_sram_ctrl_scrambled_access_jitter_en.1413194492 |
|
|
Aug 28 03:03:08 AM UTC 24 |
Aug 28 03:12:19 AM UTC 24 |
4840135416 ps |
| T1178 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_clkmgr_off_aes_trans.1137943814 |
|
|
Aug 28 03:06:32 AM UTC 24 |
Aug 28 03:12:45 AM UTC 24 |
4615855000 ps |
| T169 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup.1846183598 |
|
|
Aug 28 03:04:47 AM UTC 24 |
Aug 28 03:13:33 AM UTC 24 |
5348574284 ps |
| T1179 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_keymgr_key_derivation.1733460778 |
|
|
Aug 28 02:56:39 AM UTC 24 |
Aug 28 03:13:48 AM UTC 24 |
7945472794 ps |
| T348 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_entropy_src_csrng.1302226840 |
|
|
Aug 28 02:55:04 AM UTC 24 |
Aug 28 03:13:54 AM UTC 24 |
5825156130 ps |
| T318 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_sram_ctrl_execution_main.568006487 |
|
|
Aug 28 03:03:09 AM UTC 24 |
Aug 28 03:14:01 AM UTC 24 |
7639050919 ps |
| T191 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_plic_all_irqs_10.2252947249 |
|
|
Aug 28 03:05:23 AM UTC 24 |
Aug 28 03:14:47 AM UTC 24 |
3911633474 ps |
| T170 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_sensor_ctrl_alert.2898877125 |
|
|
Aug 28 03:03:57 AM UTC 24 |
Aug 28 03:15:14 AM UTC 24 |
5768271268 ps |
| T1180 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/default/1.rom_e2e_static_critical.44290201 |
|
|
Aug 28 01:54:32 AM UTC 24 |
Aug 28 03:15:31 AM UTC 24 |
17718716680 ps |
| T143 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_csrng_edn_concurrency_reduced_freq.4023483167 |
|
|
Aug 27 11:32:40 PM UTC 24 |
Aug 28 03:15:38 AM UTC 24 |
70522296389 ps |
| T1181 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_alert_handler_lpg_clkoff.684864754 |
|
|
Aug 28 02:48:57 AM UTC 24 |
Aug 28 03:15:44 AM UTC 24 |
7333526748 ps |
| T1182 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_clkmgr_jitter.936742507 |
|
|
Aug 28 03:12:30 AM UTC 24 |
Aug 28 03:15:53 AM UTC 24 |
2795840977 ps |
| T1183 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_clkmgr_off_kmac_trans.3629137399 |
|
|
Aug 28 03:07:35 AM UTC 24 |
Aug 28 03:16:09 AM UTC 24 |
3799678224 ps |
| T1184 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_edn_entropy_reqs.4219263372 |
|
|
Aug 28 02:55:03 AM UTC 24 |
Aug 28 03:16:38 AM UTC 24 |
7397785804 ps |
| T1185 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_sleep_sram_ret_contents_scramble.1963095154 |
|
|
Aug 28 03:03:31 AM UTC 24 |
Aug 28 03:16:38 AM UTC 24 |
8419077580 ps |
| T1186 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_clkmgr_off_otbn_trans.3842320248 |
|
|
Aug 28 03:07:39 AM UTC 24 |
Aug 28 03:16:42 AM UTC 24 |
5182603484 ps |
| T330 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_plic_all_irqs_20.3558422032 |
|
|
Aug 28 03:05:27 AM UTC 24 |
Aug 28 03:17:00 AM UTC 24 |
4635128904 ps |
| T1187 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_pwrmgr_random_sleep_power_glitch_reset.3556433277 |
|
|
Aug 28 02:32:42 AM UTC 24 |
Aug 28 03:18:07 AM UTC 24 |
33144667040 ps |
| T1188 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0.1026208503 |
|
|
Aug 28 03:08:10 AM UTC 24 |
Aug 28 03:18:09 AM UTC 24 |
4820721792 ps |
| T1189 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_clkmgr_external_clk_src_for_lc.123402323 |
|
|
Aug 28 03:07:41 AM UTC 24 |
Aug 28 03:18:09 AM UTC 24 |
12349243568 ps |
| T246 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_keymgr_sideload_aes.2148516314 |
|
|
Aug 28 02:58:41 AM UTC 24 |
Aug 28 03:18:26 AM UTC 24 |
6454508628 ps |
| T144 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_ast_clk_rst_inputs.1257357648 |
|
|
Aug 28 01:51:11 AM UTC 24 |
Aug 28 03:18:44 AM UTC 24 |
26772624012 ps |
| T1190 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_clkmgr_reset_frequency.209609506 |
|
|
Aug 28 03:12:30 AM UTC 24 |
Aug 28 03:18:50 AM UTC 24 |
3005759576 ps |
| T1191 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_tap_straps_dev.583800682 |
|
|
Aug 28 03:16:28 AM UTC 24 |
Aug 28 03:18:51 AM UTC 24 |
3168490983 ps |
| T1192 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0.3556703862 |
|
|
Aug 28 03:07:42 AM UTC 24 |
Aug 28 03:19:12 AM UTC 24 |
4053334142 ps |
| T1193 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_clkmgr_jitter_frequency.2612150079 |
|
|
Aug 28 03:12:29 AM UTC 24 |
Aug 28 03:19:49 AM UTC 24 |
4174864358 ps |
| T1194 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_tap_straps_prod.1071874320 |
|
|
Aug 28 03:17:20 AM UTC 24 |
Aug 28 03:20:00 AM UTC 24 |
2681870000 ps |
| T1195 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_clkmgr_sleep_frequency.603905512 |
|
|
Aug 28 03:12:28 AM UTC 24 |
Aug 28 03:20:35 AM UTC 24 |
5078440468 ps |
| T124 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_rv_dm_ndm_reset_req.1256522868 |
|
|
Aug 28 03:15:50 AM UTC 24 |
Aug 28 03:20:37 AM UTC 24 |
4579407624 ps |
| T664 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_clkmgr_external_clk_src_for_sw_slow_dev.1391874888 |
|
|
Aug 28 03:10:29 AM UTC 24 |
Aug 28 03:20:43 AM UTC 24 |
4409835150 ps |
| T439 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_pwrmgr_normal_sleep_all_wake_ups.2997960224 |
|
|
Aug 28 03:13:22 AM UTC 24 |
Aug 28 03:21:08 AM UTC 24 |
7272751068 ps |
| T665 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_clkmgr_external_clk_src_for_sw_fast_rma.3973887479 |
|
|
Aug 28 03:11:36 AM UTC 24 |
Aug 28 03:21:23 AM UTC 24 |
4086775526 ps |
| T666 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_clkmgr_external_clk_src_for_sw_slow_rma.2389777104 |
|
|
Aug 28 03:11:36 AM UTC 24 |
Aug 28 03:21:36 AM UTC 24 |
4760243456 ps |
| T204 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_lc_ctrl_program_error.2303094871 |
|
|
Aug 28 03:12:57 AM UTC 24 |
Aug 28 03:21:37 AM UTC 24 |
4833435120 ps |
| T667 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_clkmgr_external_clk_src_for_sw_fast_dev.1871122982 |
|
|
Aug 28 03:09:31 AM UTC 24 |
Aug 28 03:21:37 AM UTC 24 |
4340489018 ps |
| T333 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_plic_all_irqs_0.1808436471 |
|
|
Aug 28 03:05:26 AM UTC 24 |
Aug 28 03:22:14 AM UTC 24 |
6259166002 ps |
| T356 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_pwrmgr_lowpower_cancel.4179110089 |
|
|
Aug 28 03:14:09 AM UTC 24 |
Aug 28 03:22:35 AM UTC 24 |
4653752610 ps |
| T668 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_clkmgr_jitter_reduced_freq.4025324739 |
|
|
Aug 28 03:19:24 AM UTC 24 |
Aug 28 03:22:39 AM UTC 24 |
2778601179 ps |
| T263 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_rv_core_ibex_address_translation.2462642605 |
|
|
Aug 28 03:17:33 AM UTC 24 |
Aug 28 03:22:45 AM UTC 24 |
2848249500 ps |
| T1196 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_clkmgr_off_peri.2195429997 |
|
|
Aug 28 03:06:31 AM UTC 24 |
Aug 28 03:22:48 AM UTC 24 |
7948872060 ps |
| T1197 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_rv_dm_access_after_wakeup.2229722653 |
|
|
Aug 28 03:16:43 AM UTC 24 |
Aug 28 03:23:11 AM UTC 24 |
4808640736 ps |
| T313 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_rv_core_ibex_icache_invalidate.1810136527 |
|
|
Aug 28 03:19:10 AM UTC 24 |
Aug 28 03:23:28 AM UTC 24 |
3069285305 ps |
| T1198 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_alert_handler_lpg_reset_toggle.1551631315 |
|
|
Aug 28 02:48:57 AM UTC 24 |
Aug 28 03:23:31 AM UTC 24 |
9893234112 ps |
| T389 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up.62952557 |
|
|
Aug 28 03:15:20 AM UTC 24 |
Aug 28 03:23:47 AM UTC 24 |
6033829958 ps |
| T1199 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_aes_enc_jitter_en_reduced_freq.4216724271 |
|
|
Aug 28 03:20:04 AM UTC 24 |
Aug 28 03:23:57 AM UTC 24 |
2812131899 ps |
| T636 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_rv_dm_access_after_escalation_reset.3687192089 |
|
|
Aug 28 03:16:42 AM UTC 24 |
Aug 28 03:24:00 AM UTC 24 |
5416725031 ps |
| T1200 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_tap_straps_rma.1410251055 |
|
|
Aug 28 03:17:20 AM UTC 24 |
Aug 28 03:24:03 AM UTC 24 |
5706569028 ps |
| T1201 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_pwrmgr_sleep_wake_5_bug.2445354104 |
|
|
Aug 28 03:14:49 AM UTC 24 |
Aug 28 03:24:17 AM UTC 24 |
6975314180 ps |
| T237 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_inject_scramble_seed.3655201797 |
|
|
Aug 27 10:39:58 PM UTC 24 |
Aug 28 03:24:20 AM UTC 24 |
67147547922 ps |
| T1202 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_keymgr_key_derivation_prod.3865849281 |
|
|
Aug 28 02:58:07 AM UTC 24 |
Aug 28 03:24:35 AM UTC 24 |
9322377009 ps |
| T1203 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_flash_ctrl_write_clear.4027501861 |
|
|
Aug 28 03:19:35 AM UTC 24 |
Aug 28 03:25:13 AM UTC 24 |
2401999680 ps |
| T324 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_rv_dm_ndm_reset_req_when_cpu_halted.4004114169 |
|
|
Aug 28 03:16:39 AM UTC 24 |
Aug 28 03:25:20 AM UTC 24 |
4670929914 ps |
| T1204 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_hmac_enc_jitter_en_reduced_freq.3767874729 |
|
|
Aug 28 03:20:35 AM UTC 24 |
Aug 28 03:25:24 AM UTC 24 |
3408015422 ps |
| T1205 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_kmac_mode_kmac_jitter_en_reduced_freq.2547914727 |
|
|
Aug 28 03:20:55 AM UTC 24 |
Aug 28 03:25:38 AM UTC 24 |
3238893583 ps |
| T1206 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_hmac_multistream.1388923878 |
|
|
Aug 28 02:56:20 AM UTC 24 |
Aug 28 03:26:07 AM UTC 24 |
8414886536 ps |
| T657 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_power_sleep_load.2005414950 |
|
|
Aug 28 03:21:56 AM UTC 24 |
Aug 28 03:26:48 AM UTC 24 |
3744390728 ps |
| T1207 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_ast_clk_outputs.3300031398 |
|
|
Aug 28 03:12:54 AM UTC 24 |
Aug 28 03:26:49 AM UTC 24 |
6961118182 ps |
| T1208 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_flash_scrambling_smoketest.520962718 |
|
|
Aug 28 03:25:18 AM UTC 24 |
Aug 28 03:27:48 AM UTC 24 |
2075373524 ps |
| T87 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_tap_straps_testunlock0.689501034 |
|
|
Aug 28 03:16:39 AM UTC 24 |
Aug 28 03:27:56 AM UTC 24 |
7137286713 ps |
| T1209 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq.2512120584 |
|
|
Aug 28 03:21:27 AM UTC 24 |
Aug 28 03:28:21 AM UTC 24 |
4271724429 ps |
| T1210 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_flash_crash_alert.3738417768 |
|
|
Aug 28 03:19:59 AM UTC 24 |
Aug 28 03:29:35 AM UTC 24 |
5168567880 ps |
| T1211 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/default/2.rom_volatile_raw_unlock.3909467128 |
|
|
Aug 28 03:27:24 AM UTC 24 |
Aug 28 03:30:06 AM UTC 24 |
1941207009 ps |
| T1212 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_flash_ctrl_ops_jitter_en_reduced_freq.4188122711 |
|
|
Aug 28 03:20:02 AM UTC 24 |
Aug 28 03:30:59 AM UTC 24 |
4423486360 ps |
| T1213 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_clkmgr_smoketest.3814948886 |
|
|
Aug 28 03:27:42 AM UTC 24 |
Aug 28 03:31:02 AM UTC 24 |
3116640930 ps |
| T1214 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_keymgr_key_derivation_jitter_en.751849251 |
|
|
Aug 28 02:58:08 AM UTC 24 |
Aug 28 03:31:15 AM UTC 24 |
11859532954 ps |
| T1215 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_aon_timer_smoketest.3668416824 |
|
|
Aug 28 03:27:26 AM UTC 24 |
Aug 28 03:31:45 AM UTC 24 |
3716632396 ps |
| T186 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/default/2.rom_raw_unlock.1596338708 |
|
|
Aug 28 03:27:25 AM UTC 24 |
Aug 28 03:31:55 AM UTC 24 |
5808273128 ps |
| T1216 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_aes_smoketest.1168455583 |
|
|
Aug 28 03:27:08 AM UTC 24 |
Aug 28 03:32:08 AM UTC 24 |
2349749168 ps |
| T1217 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_csrng_smoketest.2349652452 |
|
|
Aug 28 03:27:47 AM UTC 24 |
Aug 28 03:32:49 AM UTC 24 |
2785505624 ps |
| T1218 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_power_idle_load.1345833620 |
|
|
Aug 28 03:21:43 AM UTC 24 |
Aug 28 03:33:23 AM UTC 24 |
5167149260 ps |
| T1219 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_gpio_smoketest.1598459054 |
|
|
Aug 28 03:28:34 AM UTC 24 |
Aug 28 03:33:32 AM UTC 24 |
2685196779 ps |
| T1220 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_hmac_smoketest.2171510607 |
|
|
Aug 28 03:28:35 AM UTC 24 |
Aug 28 03:34:02 AM UTC 24 |
2956544200 ps |
| T1221 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_kmac_smoketest.3688441335 |
|
|
Aug 28 03:28:57 AM UTC 24 |
Aug 28 03:34:08 AM UTC 24 |
3358910574 ps |
| T1222 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_otp_ctrl_smoketest.3596171165 |
|
|
Aug 28 03:30:41 AM UTC 24 |
Aug 28 03:34:53 AM UTC 24 |
2554830312 ps |
| T232 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_jtag_mem_access.1436959744 |
|
|
Aug 28 03:12:25 AM UTC 24 |
Aug 28 03:35:17 AM UTC 24 |
13525500716 ps |
| T440 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_pwrmgr_random_sleep_all_wake_ups.789753796 |
|
|
Aug 28 03:14:44 AM UTC 24 |
Aug 28 03:36:10 AM UTC 24 |
23414238284 ps |
| T1223 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_rv_timer_smoketest.3830641996 |
|
|
Aug 28 03:32:30 AM UTC 24 |
Aug 28 03:36:19 AM UTC 24 |
2169247312 ps |
| T1224 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_sysrst_ctrl_ec_rst_l.3451655729 |
|
|
Aug 28 02:36:49 AM UTC 24 |
Aug 28 03:36:41 AM UTC 24 |
20989372809 ps |
| T1225 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_entropy_src_smoketest.1696452272 |
|
|
Aug 28 03:27:50 AM UTC 24 |
Aug 28 03:36:55 AM UTC 24 |
3694640520 ps |
| T1226 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_sram_ctrl_smoketest.76736847 |
|
|
Aug 28 03:32:46 AM UTC 24 |
Aug 28 03:37:14 AM UTC 24 |
3061971480 ps |
| T1227 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/default/2.rom_keymgr_functest.943014042 |
|
|
Aug 28 03:26:57 AM UTC 24 |
Aug 28 03:37:21 AM UTC 24 |
4242862660 ps |
| T1228 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_uart_smoketest.786136246 |
|
|
Aug 28 03:33:24 AM UTC 24 |
Aug 28 03:37:58 AM UTC 24 |
2812669680 ps |
| T1229 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_rv_plic_smoketest.3280198291 |
|
|
Aug 28 03:31:57 AM UTC 24 |
Aug 28 03:38:00 AM UTC 24 |
2932282696 ps |
| T1230 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_rstmgr_smoketest.3618891751 |
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|
Aug 28 03:32:42 AM UTC 24 |
Aug 28 03:38:19 AM UTC 24 |
2889819302 ps |
| T1231 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_flash_ctrl_access_jitter_en_reduced_freq.92113514 |
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|
Aug 28 03:20:07 AM UTC 24 |
Aug 28 03:39:07 AM UTC 24 |
7847018975 ps |
| T1232 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_pwrmgr_smoketest.859096259 |
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|
Aug 28 03:31:53 AM UTC 24 |
Aug 28 03:39:07 AM UTC 24 |
5427328390 ps |
| T441 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_pwrmgr_deep_sleep_all_wake_ups.2094180846 |
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|
Aug 28 03:14:48 AM UTC 24 |
Aug 28 03:40:27 AM UTC 24 |
22765211736 ps |
| T1233 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_pwrmgr_usbdev_smoketest.489042195 |
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|
Aug 28 03:31:56 AM UTC 24 |
Aug 28 03:41:18 AM UTC 24 |
6225072960 ps |
| T1234 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/default/3.chip_sw_uart_rand_baudrate.872607258 |
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|
Aug 28 03:37:00 AM UTC 24 |
Aug 28 03:44:15 AM UTC 24 |
3868448056 ps |
| T1235 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/default/3.chip_sw_uart_tx_rx_idx2.731927129 |
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|
Aug 28 03:35:30 AM UTC 24 |
Aug 28 03:44:19 AM UTC 24 |
4477689304 ps |
| T1236 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/default/3.chip_tap_straps_rma.402806082 |
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|
Aug 28 03:39:41 AM UTC 24 |
Aug 28 03:44:25 AM UTC 24 |
4213566312 ps |
| T1237 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_flash_rma_unlocked.2291949076 |
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|
Aug 28 02:17:36 AM UTC 24 |
Aug 28 03:44:27 AM UTC 24 |
44396948464 ps |
| T1238 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_keymgr_key_derivation_jitter_en_reduced_freq.3132428905 |
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|
Aug 28 03:20:38 AM UTC 24 |
Aug 28 03:44:44 AM UTC 24 |
9970964489 ps |
| T1239 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/default/3.chip_tap_straps_testunlock0.4166610236 |
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|
Aug 28 03:39:42 AM UTC 24 |
Aug 28 03:44:51 AM UTC 24 |
3258948152 ps |
| T1240 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_flash_ctrl_mem_protection.1073877934 |
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|
Aug 28 03:26:29 AM UTC 24 |
Aug 28 03:44:57 AM UTC 24 |
5087804518 ps |
| T1241 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_keymgr_sideload_kmac.4131503370 |
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|
Aug 28 02:58:41 AM UTC 24 |
Aug 28 03:45:12 AM UTC 24 |
13216221690 ps |
| T366 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/default/3.chip_sw_all_escalation_resets.249752355 |
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|
Aug 28 03:34:12 AM UTC 24 |
Aug 28 03:45:20 AM UTC 24 |
4894898024 ps |
| T1242 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/default/3.chip_sw_uart_tx_rx_idx1.73799246 |
|
|
Aug 28 03:34:51 AM UTC 24 |
Aug 28 03:45:22 AM UTC 24 |
4320517560 ps |
| T1243 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/default/3.chip_sw_aon_timer_sleep_wdog_sleep_pause.2517420934 |
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|
Aug 28 03:38:03 AM UTC 24 |
Aug 28 03:45:24 AM UTC 24 |
6893652984 ps |
| T1244 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/default/3.chip_sw_uart_tx_rx.3327378340 |
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|
Aug 28 03:34:51 AM UTC 24 |
Aug 28 03:45:34 AM UTC 24 |
4464246052 ps |
| T1245 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/default/3.chip_sw_uart_tx_rx_idx3.2086293848 |
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|
Aug 28 03:35:54 AM UTC 24 |
Aug 28 03:45:48 AM UTC 24 |
4921005930 ps |
| T1246 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_pwrmgr_b2b_sleep_reset_req.1822629669 |
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|
Aug 28 03:04:47 AM UTC 24 |
Aug 28 03:45:52 AM UTC 24 |
26025533492 ps |
| T1247 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_otbn_ecdsa_op_irq_jitter_en.3165616663 |
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|
Aug 28 02:41:07 AM UTC 24 |
Aug 28 03:46:24 AM UTC 24 |
18492126380 ps |
| T1248 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/default/3.chip_sw_data_integrity_escalation.3716592288 |
|
|
Aug 28 03:34:13 AM UTC 24 |
Aug 28 03:47:47 AM UTC 24 |
6318828520 ps |
| T130 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_power_virus.2573255377 |
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|
Aug 28 03:24:12 AM UTC 24 |
Aug 28 03:48:35 AM UTC 24 |
6068387610 ps |
| T372 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_uart_tx_rx_bootstrap.157366231 |
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|
Aug 27 10:37:32 PM UTC 24 |
Aug 28 03:49:10 AM UTC 24 |
80031244125 ps |
| T1249 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/default/4.chip_tap_straps_dev.2267022352 |
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|
Aug 28 03:46:52 AM UTC 24 |
Aug 28 03:49:22 AM UTC 24 |
3084020973 ps |
| T1250 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/default/4.chip_tap_straps_rma.1836547978 |
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|
Aug 28 03:47:24 AM UTC 24 |
Aug 28 03:50:26 AM UTC 24 |
3298218688 ps |
| T171 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/default/3.chip_sw_sensor_ctrl_alert.3970261485 |
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|
Aug 28 03:38:50 AM UTC 24 |
Aug 28 03:50:39 AM UTC 24 |
6232870066 ps |