| T2020 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/51.xbar_random_zero_delays.984468153 |
|
|
Aug 27 09:37:18 PM UTC 24 |
Aug 27 09:37:46 PM UTC 24 |
286537116 ps |
| T2021 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/51.xbar_access_same_device.3513470165 |
|
|
Aug 27 09:37:25 PM UTC 24 |
Aug 27 09:37:58 PM UTC 24 |
448146046 ps |
| T2022 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/51.xbar_error_and_unmapped_addr.2918667376 |
|
|
Aug 27 09:37:41 PM UTC 24 |
Aug 27 09:38:02 PM UTC 24 |
126486509 ps |
| T2023 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/47.xbar_stress_all_with_reset_error.1883721095 |
|
|
Aug 27 09:33:10 PM UTC 24 |
Aug 27 09:38:08 PM UTC 24 |
7402384603 ps |
| T2024 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/52.xbar_smoke.1191480281 |
|
|
Aug 27 09:37:59 PM UTC 24 |
Aug 27 09:38:09 PM UTC 24 |
57183829 ps |
| T2025 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/51.xbar_unmapped_addr.157517893 |
|
|
Aug 27 09:37:31 PM UTC 24 |
Aug 27 09:38:14 PM UTC 24 |
240973908 ps |
| T2026 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/52.xbar_smoke_zero_delays.2179600274 |
|
|
Aug 27 09:38:08 PM UTC 24 |
Aug 27 09:38:18 PM UTC 24 |
49104142 ps |
| T2027 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/43.xbar_access_same_device_slow_rsp.3530829920 |
|
|
Aug 27 09:27:22 PM UTC 24 |
Aug 27 09:38:24 PM UTC 24 |
48646326960 ps |
| T2028 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/50.xbar_stress_all_with_reset_error.181461822 |
|
|
Aug 27 09:36:52 PM UTC 24 |
Aug 27 09:38:27 PM UTC 24 |
399550647 ps |
| T2029 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/51.xbar_smoke_large_delays.1376937845 |
|
|
Aug 27 09:37:05 PM UTC 24 |
Aug 27 09:38:27 PM UTC 24 |
8649722205 ps |
| T2030 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/51.xbar_stress_all.3874499568 |
|
|
Aug 27 09:37:40 PM UTC 24 |
Aug 27 09:38:27 PM UTC 24 |
588605920 ps |
| T2031 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/41.xbar_random_large_delays.3335941000 |
|
|
Aug 27 09:24:11 PM UTC 24 |
Aug 27 09:38:30 PM UTC 24 |
80741583900 ps |
| T2032 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/51.xbar_smoke_slow_rsp.2431736656 |
|
|
Aug 27 09:37:10 PM UTC 24 |
Aug 27 09:38:40 PM UTC 24 |
4366378966 ps |
| T2033 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/50.xbar_stress_all.3760568193 |
|
|
Aug 27 09:36:46 PM UTC 24 |
Aug 27 09:38:44 PM UTC 24 |
3756537839 ps |
| T2034 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/52.xbar_random.2694311135 |
|
|
Aug 27 09:38:23 PM UTC 24 |
Aug 27 09:38:44 PM UTC 24 |
532891146 ps |
| T2035 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/46.xbar_stress_all_with_reset_error.3162813390 |
|
|
Aug 27 09:31:46 PM UTC 24 |
Aug 27 09:38:49 PM UTC 24 |
10370264623 ps |
| T2036 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/51.xbar_random_slow_rsp.2853210593 |
|
|
Aug 27 09:37:21 PM UTC 24 |
Aug 27 09:38:50 PM UTC 24 |
3869132337 ps |
| T519 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/40.xbar_stress_all_with_rand_reset.767611282 |
|
|
Aug 27 09:23:44 PM UTC 24 |
Aug 27 09:38:53 PM UTC 24 |
7835412940 ps |
| T2037 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/52.xbar_random_zero_delays.1103611744 |
|
|
Aug 27 09:38:31 PM UTC 24 |
Aug 27 09:38:55 PM UTC 24 |
260211683 ps |
| T2038 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/52.xbar_unmapped_addr.2469313988 |
|
|
Aug 27 09:38:50 PM UTC 24 |
Aug 27 09:39:04 PM UTC 24 |
156738138 ps |
| T2039 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/51.xbar_same_source.2477854808 |
|
|
Aug 27 09:37:31 PM UTC 24 |
Aug 27 09:39:05 PM UTC 24 |
2367548125 ps |
| T2040 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/42.xbar_random_slow_rsp.982745509 |
|
|
Aug 27 09:25:52 PM UTC 24 |
Aug 27 09:39:06 PM UTC 24 |
52563671788 ps |
| T2041 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/51.xbar_error_random.3776170419 |
|
|
Aug 27 09:37:30 PM UTC 24 |
Aug 27 09:39:08 PM UTC 24 |
2419421418 ps |
| T2042 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/46.xbar_random_large_delays.805983019 |
|
|
Aug 27 09:30:44 PM UTC 24 |
Aug 27 09:39:14 PM UTC 24 |
44061210311 ps |
| T2043 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/52.xbar_access_same_device.3533336119 |
|
|
Aug 27 09:38:42 PM UTC 24 |
Aug 27 09:39:15 PM UTC 24 |
406248071 ps |
| T854 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/48.xbar_stress_all_with_rand_reset.1487570870 |
|
|
Aug 27 09:34:16 PM UTC 24 |
Aug 27 09:39:21 PM UTC 24 |
488539238 ps |
| T2044 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/53.xbar_smoke.2609844980 |
|
|
Aug 27 09:39:12 PM UTC 24 |
Aug 27 09:39:22 PM UTC 24 |
218830156 ps |
| T2045 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/53.xbar_smoke_zero_delays.3565558197 |
|
|
Aug 27 09:39:15 PM UTC 24 |
Aug 27 09:39:24 PM UTC 24 |
33673678 ps |
| T2046 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/52.xbar_error_random.488193798 |
|
|
Aug 27 09:38:49 PM UTC 24 |
Aug 27 09:39:29 PM UTC 24 |
530948135 ps |
| T2047 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/51.xbar_stress_all_with_reset_error.1816390310 |
|
|
Aug 27 09:37:58 PM UTC 24 |
Aug 27 09:39:30 PM UTC 24 |
154511409 ps |
| T2048 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/52.xbar_error_and_unmapped_addr.1135530351 |
|
|
Aug 27 09:38:53 PM UTC 24 |
Aug 27 09:39:32 PM UTC 24 |
285418347 ps |
| T2049 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/51.xbar_stress_all_with_error.1508087213 |
|
|
Aug 27 09:37:53 PM UTC 24 |
Aug 27 09:39:36 PM UTC 24 |
3511965694 ps |
| T2050 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/52.xbar_stress_all_with_rand_reset.1802987041 |
|
|
Aug 27 09:39:06 PM UTC 24 |
Aug 27 09:39:46 PM UTC 24 |
133504682 ps |
| T2051 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/3.chip_csr_aliasing.1907233473 |
|
|
Aug 27 08:10:33 PM UTC 24 |
Aug 27 09:39:53 PM UTC 24 |
37022678906 ps |
| T2052 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/46.xbar_random_slow_rsp.1011558030 |
|
|
Aug 27 09:30:48 PM UTC 24 |
Aug 27 09:39:54 PM UTC 24 |
35058197079 ps |
| T2053 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/52.xbar_same_source.2499282477 |
|
|
Aug 27 09:38:47 PM UTC 24 |
Aug 27 09:39:56 PM UTC 24 |
2549425047 ps |
| T2054 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/53.xbar_same_source.2590536576 |
|
|
Aug 27 09:39:41 PM UTC 24 |
Aug 27 09:39:58 PM UTC 24 |
107798917 ps |
| T2055 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/52.xbar_smoke_large_delays.1178481278 |
|
|
Aug 27 09:38:06 PM UTC 24 |
Aug 27 09:39:58 PM UTC 24 |
9646296212 ps |
| T2056 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/52.xbar_smoke_slow_rsp.109833220 |
|
|
Aug 27 09:38:18 PM UTC 24 |
Aug 27 09:40:01 PM UTC 24 |
6538167440 ps |
| T2057 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/53.xbar_error_random.3464021577 |
|
|
Aug 27 09:39:46 PM UTC 24 |
Aug 27 09:40:03 PM UTC 24 |
154060998 ps |
| T2058 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/53.xbar_random_zero_delays.4085082093 |
|
|
Aug 27 09:39:29 PM UTC 24 |
Aug 27 09:40:08 PM UTC 24 |
319665200 ps |
| T2059 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/38.xbar_access_same_device_slow_rsp.1807890910 |
|
|
Aug 27 09:19:30 PM UTC 24 |
Aug 27 09:40:16 PM UTC 24 |
77393758569 ps |
| T2060 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/53.xbar_unmapped_addr.1887593855 |
|
|
Aug 27 09:39:53 PM UTC 24 |
Aug 27 09:40:18 PM UTC 24 |
658898246 ps |
| T2061 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/53.xbar_error_and_unmapped_addr.113392356 |
|
|
Aug 27 09:39:53 PM UTC 24 |
Aug 27 09:40:21 PM UTC 24 |
564511990 ps |
| T2062 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/53.xbar_random_large_delays.3521726570 |
|
|
Aug 27 09:39:28 PM UTC 24 |
Aug 27 09:40:21 PM UTC 24 |
5189334898 ps |
| T2063 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/53.xbar_random.690685022 |
|
|
Aug 27 09:39:27 PM UTC 24 |
Aug 27 09:40:23 PM UTC 24 |
1410463613 ps |
| T2064 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/53.xbar_smoke_slow_rsp.3091242718 |
|
|
Aug 27 09:39:24 PM UTC 24 |
Aug 27 09:40:27 PM UTC 24 |
4193033427 ps |
| T2065 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/54.xbar_smoke.832326480 |
|
|
Aug 27 09:40:18 PM UTC 24 |
Aug 27 09:40:28 PM UTC 24 |
198387818 ps |
| T2066 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/54.xbar_smoke_zero_delays.1161744625 |
|
|
Aug 27 09:40:18 PM UTC 24 |
Aug 27 09:40:28 PM UTC 24 |
52929230 ps |
| T2067 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/54.xbar_random.1115270845 |
|
|
Aug 27 09:40:25 PM UTC 24 |
Aug 27 09:40:35 PM UTC 24 |
42990312 ps |
| T2068 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/43.xbar_random_slow_rsp.3434657086 |
|
|
Aug 27 09:27:19 PM UTC 24 |
Aug 27 09:40:40 PM UTC 24 |
64359128582 ps |
| T2069 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/53.xbar_stress_all_with_error.1029981146 |
|
|
Aug 27 09:40:09 PM UTC 24 |
Aug 27 09:40:43 PM UTC 24 |
325766503 ps |
| T2070 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/31.xbar_access_same_device_slow_rsp.876747340 |
|
|
Aug 27 09:10:14 PM UTC 24 |
Aug 27 09:40:44 PM UTC 24 |
121241470336 ps |
| T2071 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/54.xbar_access_same_device.3996436366 |
|
|
Aug 27 09:40:39 PM UTC 24 |
Aug 27 09:40:50 PM UTC 24 |
63338586 ps |
| T2072 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/52.xbar_stress_all_with_reset_error.3844935865 |
|
|
Aug 27 09:39:11 PM UTC 24 |
Aug 27 09:40:57 PM UTC 24 |
509603693 ps |
| T2073 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/47.xbar_random_slow_rsp.1952343546 |
|
|
Aug 27 09:32:11 PM UTC 24 |
Aug 27 09:41:08 PM UTC 24 |
35413993557 ps |
| T2074 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/53.xbar_smoke_large_delays.1447947713 |
|
|
Aug 27 09:39:19 PM UTC 24 |
Aug 27 09:41:14 PM UTC 24 |
9924627344 ps |
| T2075 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/54.xbar_random_zero_delays.3771431153 |
|
|
Aug 27 09:40:26 PM UTC 24 |
Aug 27 09:41:16 PM UTC 24 |
593284456 ps |
| T2076 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/55.xbar_smoke.2829478663 |
|
|
Aug 27 09:41:06 PM UTC 24 |
Aug 27 09:41:21 PM UTC 24 |
234691313 ps |
| T2077 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/55.xbar_smoke_zero_delays.3230276181 |
|
|
Aug 27 09:41:13 PM UTC 24 |
Aug 27 09:41:25 PM UTC 24 |
52354074 ps |
| T2078 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/44.xbar_random_large_delays.769828296 |
|
|
Aug 27 09:28:18 PM UTC 24 |
Aug 27 09:41:25 PM UTC 24 |
83770105166 ps |
| T2079 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/54.xbar_smoke_large_delays.721727531 |
|
|
Aug 27 09:40:20 PM UTC 24 |
Aug 27 09:41:29 PM UTC 24 |
7027476570 ps |
| T2080 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/54.xbar_unmapped_addr.2023567632 |
|
|
Aug 27 09:40:48 PM UTC 24 |
Aug 27 09:41:35 PM UTC 24 |
993936141 ps |
| T2081 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/1.chip_csr_bit_bash.1671497023 |
|
|
Aug 27 08:07:55 PM UTC 24 |
Aug 27 09:41:36 PM UTC 24 |
56555215212 ps |
| T2082 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/1.chip_csr_aliasing.1689688769 |
|
|
Aug 27 08:07:53 PM UTC 24 |
Aug 27 09:41:36 PM UTC 24 |
36165572864 ps |
| T2083 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/52.xbar_stress_all_with_error.2324470740 |
|
|
Aug 27 09:39:04 PM UTC 24 |
Aug 27 09:41:40 PM UTC 24 |
2107240224 ps |
| T2084 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/53.xbar_access_same_device.4292612823 |
|
|
Aug 27 09:39:37 PM UTC 24 |
Aug 27 09:41:45 PM UTC 24 |
2579833162 ps |
| T2085 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/50.xbar_stress_all_with_error.322763666 |
|
|
Aug 27 09:36:49 PM UTC 24 |
Aug 27 09:41:51 PM UTC 24 |
10004439002 ps |
| T2086 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/50.xbar_random_large_delays.1296867609 |
|
|
Aug 27 09:36:27 PM UTC 24 |
Aug 27 09:41:51 PM UTC 24 |
29821135792 ps |
| T2087 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/54.xbar_error_and_unmapped_addr.2284542575 |
|
|
Aug 27 09:40:50 PM UTC 24 |
Aug 27 09:41:54 PM UTC 24 |
1361321429 ps |
| T2088 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/39.xbar_access_same_device_slow_rsp.3632862526 |
|
|
Aug 27 09:21:27 PM UTC 24 |
Aug 27 09:41:56 PM UTC 24 |
81235634061 ps |
| T2089 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/55.xbar_random_zero_delays.1389383983 |
|
|
Aug 27 09:41:38 PM UTC 24 |
Aug 27 09:41:59 PM UTC 24 |
251938948 ps |
| T2090 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/54.xbar_error_random.639916687 |
|
|
Aug 27 09:40:46 PM UTC 24 |
Aug 27 09:42:01 PM UTC 24 |
2277067910 ps |
| T2091 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/54.xbar_same_source.1595902027 |
|
|
Aug 27 09:40:43 PM UTC 24 |
Aug 27 09:42:02 PM UTC 24 |
2006476012 ps |
| T2092 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/54.xbar_stress_all_with_error.738080613 |
|
|
Aug 27 09:41:03 PM UTC 24 |
Aug 27 09:42:05 PM UTC 24 |
822900249 ps |
| T2093 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/54.xbar_smoke_slow_rsp.4189962723 |
|
|
Aug 27 09:40:22 PM UTC 24 |
Aug 27 09:42:14 PM UTC 24 |
6045703458 ps |
| T2094 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/55.xbar_unmapped_addr.1350344034 |
|
|
Aug 27 09:41:58 PM UTC 24 |
Aug 27 09:42:15 PM UTC 24 |
95740478 ps |
| T2095 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/56.xbar_smoke_zero_delays.242523547 |
|
|
Aug 27 09:42:18 PM UTC 24 |
Aug 27 09:42:29 PM UTC 24 |
49265430 ps |
| T2096 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/56.xbar_smoke.3023280237 |
|
|
Aug 27 09:42:20 PM UTC 24 |
Aug 27 09:42:30 PM UTC 24 |
44795041 ps |
| T873 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/53.xbar_stress_all_with_reset_error.3907880236 |
|
|
Aug 27 09:40:17 PM UTC 24 |
Aug 27 09:42:40 PM UTC 24 |
1134082897 ps |
| T2097 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/55.xbar_error_and_unmapped_addr.1209765466 |
|
|
Aug 27 09:42:00 PM UTC 24 |
Aug 27 09:42:44 PM UTC 24 |
298866471 ps |
| T2098 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/45.xbar_random_large_delays.1567918705 |
|
|
Aug 27 09:29:31 PM UTC 24 |
Aug 27 09:42:46 PM UTC 24 |
86802298442 ps |
| T2099 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/55.xbar_smoke_slow_rsp.4171506092 |
|
|
Aug 27 09:41:31 PM UTC 24 |
Aug 27 09:42:48 PM UTC 24 |
4820502684 ps |
| T2100 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/55.xbar_random.3455639295 |
|
|
Aug 27 09:41:36 PM UTC 24 |
Aug 27 09:42:51 PM UTC 24 |
2051667916 ps |
| T2101 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/55.xbar_same_source.1439728973 |
|
|
Aug 27 09:41:56 PM UTC 24 |
Aug 27 09:42:54 PM UTC 24 |
1463806692 ps |
| T2102 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/26.xbar_access_same_device_slow_rsp.3853282953 |
|
|
Aug 27 09:01:17 PM UTC 24 |
Aug 27 09:42:56 PM UTC 24 |
136981491697 ps |
| T2103 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/56.xbar_random.1854609152 |
|
|
Aug 27 09:42:28 PM UTC 24 |
Aug 27 09:42:58 PM UTC 24 |
282612305 ps |
| T2104 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/55.xbar_stress_all_with_reset_error.1129934214 |
|
|
Aug 27 09:42:17 PM UTC 24 |
Aug 27 09:43:02 PM UTC 24 |
97806284 ps |
| T2105 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/56.xbar_random_zero_delays.3707260283 |
|
|
Aug 27 09:42:37 PM UTC 24 |
Aug 27 09:43:07 PM UTC 24 |
229232510 ps |
| T2106 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/55.xbar_smoke_large_delays.4082481722 |
|
|
Aug 27 09:41:20 PM UTC 24 |
Aug 27 09:43:08 PM UTC 24 |
8199965160 ps |
| T2107 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/43.xbar_random_large_delays.3801022450 |
|
|
Aug 27 09:27:17 PM UTC 24 |
Aug 27 09:43:12 PM UTC 24 |
91323579650 ps |
| T2108 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/55.xbar_error_random.530370769 |
|
|
Aug 27 09:41:56 PM UTC 24 |
Aug 27 09:43:13 PM UTC 24 |
2125031146 ps |
| T2109 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/55.xbar_access_same_device.960656596 |
|
|
Aug 27 09:41:47 PM UTC 24 |
Aug 27 09:43:21 PM UTC 24 |
2220751069 ps |
| T2110 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/56.xbar_error_and_unmapped_addr.1484339858 |
|
|
Aug 27 09:43:11 PM UTC 24 |
Aug 27 09:43:24 PM UTC 24 |
64461421 ps |
| T2111 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/45.xbar_stress_all_with_reset_error.1814602363 |
|
|
Aug 27 09:30:03 PM UTC 24 |
Aug 27 09:43:30 PM UTC 24 |
17191519889 ps |
| T2112 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/56.xbar_error_random.3665918896 |
|
|
Aug 27 09:43:08 PM UTC 24 |
Aug 27 09:43:31 PM UTC 24 |
186983438 ps |
| T2113 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/55.xbar_stress_all_with_error.3668116257 |
|
|
Aug 27 09:42:13 PM UTC 24 |
Aug 27 09:43:31 PM UTC 24 |
1630875126 ps |
| T2114 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/56.xbar_access_same_device.4023292100 |
|
|
Aug 27 09:42:53 PM UTC 24 |
Aug 27 09:43:41 PM UTC 24 |
1222026347 ps |
| T2115 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/57.xbar_smoke_zero_delays.2142256042 |
|
|
Aug 27 09:43:31 PM UTC 24 |
Aug 27 09:43:41 PM UTC 24 |
48200530 ps |
| T2116 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/57.xbar_smoke.2849626026 |
|
|
Aug 27 09:43:28 PM UTC 24 |
Aug 27 09:43:43 PM UTC 24 |
238015755 ps |
| T2117 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/56.xbar_same_source.1899965043 |
|
|
Aug 27 09:43:06 PM UTC 24 |
Aug 27 09:43:46 PM UTC 24 |
418642517 ps |
| T2118 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/56.xbar_smoke_slow_rsp.1121925262 |
|
|
Aug 27 09:42:25 PM UTC 24 |
Aug 27 09:43:53 PM UTC 24 |
5336435407 ps |
| T2119 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/53.xbar_stress_all_with_rand_reset.2523919570 |
|
|
Aug 27 09:39:59 PM UTC 24 |
Aug 27 09:43:54 PM UTC 24 |
1421313753 ps |
| T2120 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/52.xbar_random_slow_rsp.2345705564 |
|
|
Aug 27 09:38:33 PM UTC 24 |
Aug 27 09:44:00 PM UTC 24 |
20112457702 ps |
| T2121 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/52.xbar_access_same_device_slow_rsp.3783717930 |
|
|
Aug 27 09:38:44 PM UTC 24 |
Aug 27 09:44:00 PM UTC 24 |
21716854880 ps |
| T2122 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/57.xbar_access_same_device.3028949224 |
|
|
Aug 27 09:43:55 PM UTC 24 |
Aug 27 09:44:10 PM UTC 24 |
109746538 ps |
| T2123 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/56.xbar_smoke_large_delays.134622642 |
|
|
Aug 27 09:42:24 PM UTC 24 |
Aug 27 09:44:22 PM UTC 24 |
8840921925 ps |
| T2124 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/50.xbar_access_same_device_slow_rsp.1473380451 |
|
|
Aug 27 09:36:34 PM UTC 24 |
Aug 27 09:44:22 PM UTC 24 |
31990962180 ps |
| T2125 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/56.xbar_unmapped_addr.239401306 |
|
|
Aug 27 09:43:11 PM UTC 24 |
Aug 27 09:44:23 PM UTC 24 |
1434573336 ps |
| T2126 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/49.xbar_stress_all.3036037238 |
|
|
Aug 27 09:35:44 PM UTC 24 |
Aug 27 09:44:27 PM UTC 24 |
14835568785 ps |
| T2127 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/57.xbar_error_and_unmapped_addr.3136961540 |
|
|
Aug 27 09:44:14 PM UTC 24 |
Aug 27 09:44:28 PM UTC 24 |
70474939 ps |
| T2128 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/53.xbar_stress_all.4165262825 |
|
|
Aug 27 09:39:56 PM UTC 24 |
Aug 27 09:44:29 PM UTC 24 |
3796825890 ps |
| T2129 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/57.xbar_unmapped_addr.3941420672 |
|
|
Aug 27 09:44:07 PM UTC 24 |
Aug 27 09:44:29 PM UTC 24 |
308791417 ps |
| T2130 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/57.xbar_smoke_large_delays.752710962 |
|
|
Aug 27 09:43:35 PM UTC 24 |
Aug 27 09:44:30 PM UTC 24 |
4811155233 ps |
| T2131 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/57.xbar_random_zero_delays.2572233882 |
|
|
Aug 27 09:43:47 PM UTC 24 |
Aug 27 09:44:32 PM UTC 24 |
605820287 ps |
| T2132 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/49.xbar_stress_all_with_reset_error.115185944 |
|
|
Aug 27 09:35:52 PM UTC 24 |
Aug 27 09:44:34 PM UTC 24 |
5952894550 ps |
| T2133 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/57.xbar_same_source.2388265829 |
|
|
Aug 27 09:44:03 PM UTC 24 |
Aug 27 09:44:41 PM UTC 24 |
1330756157 ps |
| T2134 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/58.xbar_smoke.3977062522 |
|
|
Aug 27 09:44:38 PM UTC 24 |
Aug 27 09:44:48 PM UTC 24 |
261412627 ps |
| T2135 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/57.xbar_error_random.1394565782 |
|
|
Aug 27 09:44:06 PM UTC 24 |
Aug 27 09:44:54 PM UTC 24 |
609103511 ps |
| T2136 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/58.xbar_smoke_zero_delays.2212106242 |
|
|
Aug 27 09:44:46 PM UTC 24 |
Aug 27 09:44:54 PM UTC 24 |
47476763 ps |
| T2137 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/57.xbar_smoke_slow_rsp.42304887 |
|
|
Aug 27 09:43:36 PM UTC 24 |
Aug 27 09:44:55 PM UTC 24 |
5145439952 ps |
| T2138 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/58.xbar_random_zero_delays.850444746 |
|
|
Aug 27 09:44:49 PM UTC 24 |
Aug 27 09:44:59 PM UTC 24 |
67903465 ps |
| T2139 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/56.xbar_stress_all.889868438 |
|
|
Aug 27 09:43:17 PM UTC 24 |
Aug 27 09:45:04 PM UTC 24 |
1166016067 ps |
| T2140 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/40.xbar_access_same_device_slow_rsp.2178615983 |
|
|
Aug 27 09:23:08 PM UTC 24 |
Aug 27 09:45:14 PM UTC 24 |
80988870689 ps |
| T2141 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/58.xbar_random.1827808488 |
|
|
Aug 27 09:44:49 PM UTC 24 |
Aug 27 09:45:22 PM UTC 24 |
623897813 ps |
| T2142 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/57.xbar_random.1102750919 |
|
|
Aug 27 09:43:44 PM UTC 24 |
Aug 27 09:45:25 PM UTC 24 |
2240596066 ps |
| T2143 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/52.xbar_random_large_delays.1665152169 |
|
|
Aug 27 09:38:31 PM UTC 24 |
Aug 27 09:45:27 PM UTC 24 |
42339962866 ps |
| T2144 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/44.xbar_access_same_device_slow_rsp.1361463443 |
|
|
Aug 27 09:28:28 PM UTC 24 |
Aug 27 09:45:28 PM UTC 24 |
61576268226 ps |
| T2145 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/58.xbar_same_source.505897369 |
|
|
Aug 27 09:45:01 PM UTC 24 |
Aug 27 09:45:31 PM UTC 24 |
444213212 ps |
| T2146 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/58.xbar_unmapped_addr.344003665 |
|
|
Aug 27 09:45:15 PM UTC 24 |
Aug 27 09:45:31 PM UTC 24 |
214896932 ps |
| T2147 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/41.xbar_access_same_device_slow_rsp.430751564 |
|
|
Aug 27 09:24:30 PM UTC 24 |
Aug 27 09:45:33 PM UTC 24 |
87629934925 ps |
| T2148 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/57.xbar_stress_all_with_error.1496899497 |
|
|
Aug 27 09:44:24 PM UTC 24 |
Aug 27 09:45:34 PM UTC 24 |
2594990431 ps |
| T2149 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/55.xbar_stress_all_with_rand_reset.4084842424 |
|
|
Aug 27 09:42:09 PM UTC 24 |
Aug 27 09:45:47 PM UTC 24 |
1903272807 ps |
| T2150 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/59.xbar_smoke.2397782032 |
|
|
Aug 27 09:45:45 PM UTC 24 |
Aug 27 09:45:54 PM UTC 24 |
43636061 ps |
| T2151 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/58.xbar_error_and_unmapped_addr.4064616478 |
|
|
Aug 27 09:45:16 PM UTC 24 |
Aug 27 09:45:54 PM UTC 24 |
283184302 ps |
| T2152 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/59.xbar_smoke_zero_delays.3866139813 |
|
|
Aug 27 09:45:48 PM UTC 24 |
Aug 27 09:45:57 PM UTC 24 |
45162274 ps |
| T2153 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/58.xbar_error_random.2432725347 |
|
|
Aug 27 09:45:11 PM UTC 24 |
Aug 27 09:46:05 PM UTC 24 |
1698888526 ps |
| T2154 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/59.xbar_random_zero_delays.1728632350 |
|
|
Aug 27 09:45:55 PM UTC 24 |
Aug 27 09:46:07 PM UTC 24 |
63977155 ps |
| T2155 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/59.xbar_random.1499080282 |
|
|
Aug 27 09:45:53 PM UTC 24 |
Aug 27 09:46:08 PM UTC 24 |
89755363 ps |
| T861 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/57.xbar_stress_all_with_rand_reset.1823504115 |
|
|
Aug 27 09:44:22 PM UTC 24 |
Aug 27 09:46:14 PM UTC 24 |
338398253 ps |
| T2156 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/58.xbar_smoke_slow_rsp.4020463874 |
|
|
Aug 27 09:44:50 PM UTC 24 |
Aug 27 09:46:16 PM UTC 24 |
6029566210 ps |
| T2157 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/53.xbar_random_slow_rsp.376203418 |
|
|
Aug 27 09:39:36 PM UTC 24 |
Aug 27 09:46:17 PM UTC 24 |
25924032879 ps |
| T2158 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/58.xbar_smoke_large_delays.2856822081 |
|
|
Aug 27 09:44:45 PM UTC 24 |
Aug 27 09:46:17 PM UTC 24 |
7922862509 ps |
| T2159 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/54.xbar_stress_all.3398321812 |
|
|
Aug 27 09:40:51 PM UTC 24 |
Aug 27 09:46:18 PM UTC 24 |
8334491050 ps |
| T2160 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/49.xbar_random_large_delays.136040318 |
|
|
Aug 27 09:35:22 PM UTC 24 |
Aug 27 09:46:18 PM UTC 24 |
64563034106 ps |
| T2161 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/55.xbar_stress_all.2615859693 |
|
|
Aug 27 09:42:05 PM UTC 24 |
Aug 27 09:46:20 PM UTC 24 |
7982643558 ps |
| T2162 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/59.xbar_smoke_large_delays.3082996513 |
|
|
Aug 27 09:45:48 PM UTC 24 |
Aug 27 09:46:34 PM UTC 24 |
4582021419 ps |
| T2163 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/58.xbar_stress_all_with_rand_reset.1284774717 |
|
|
Aug 27 09:45:20 PM UTC 24 |
Aug 27 09:46:44 PM UTC 24 |
168831274 ps |
| T2164 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/52.xbar_stress_all.1276416236 |
|
|
Aug 27 09:39:03 PM UTC 24 |
Aug 27 09:46:47 PM UTC 24 |
13770119603 ps |
| T2165 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/60.xbar_smoke_zero_delays.3945467314 |
|
|
Aug 27 09:46:39 PM UTC 24 |
Aug 27 09:46:48 PM UTC 24 |
57662798 ps |
| T2166 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/60.xbar_smoke.4099943872 |
|
|
Aug 27 09:46:38 PM UTC 24 |
Aug 27 09:46:51 PM UTC 24 |
175800034 ps |
| T2167 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/58.xbar_access_same_device.871032473 |
|
|
Aug 27 09:44:53 PM UTC 24 |
Aug 27 09:46:52 PM UTC 24 |
3123143023 ps |
| T2168 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/59.xbar_unmapped_addr.2175084883 |
|
|
Aug 27 09:46:25 PM UTC 24 |
Aug 27 09:46:56 PM UTC 24 |
176376194 ps |
| T2169 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/59.xbar_error_and_unmapped_addr.3351842422 |
|
|
Aug 27 09:46:29 PM UTC 24 |
Aug 27 09:46:56 PM UTC 24 |
424819806 ps |
| T2170 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/59.xbar_access_same_device.3802733125 |
|
|
Aug 27 09:46:08 PM UTC 24 |
Aug 27 09:46:58 PM UTC 24 |
1153223038 ps |
| T2171 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/59.xbar_error_random.1644428799 |
|
|
Aug 27 09:46:19 PM UTC 24 |
Aug 27 09:47:21 PM UTC 24 |
602837951 ps |
| T2172 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/56.xbar_access_same_device_slow_rsp.1462573007 |
|
|
Aug 27 09:43:01 PM UTC 24 |
Aug 27 09:47:22 PM UTC 24 |
16651031032 ps |
| T2173 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/54.xbar_stress_all_with_reset_error.2867034913 |
|
|
Aug 27 09:41:05 PM UTC 24 |
Aug 27 09:47:22 PM UTC 24 |
3120806635 ps |
| T2174 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/48.xbar_random_slow_rsp.1275236615 |
|
|
Aug 27 09:33:51 PM UTC 24 |
Aug 27 09:47:22 PM UTC 24 |
51220768991 ps |
| T2175 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/60.xbar_access_same_device.3519512461 |
|
|
Aug 27 09:47:13 PM UTC 24 |
Aug 27 09:47:31 PM UTC 24 |
272613628 ps |
| T2176 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/59.xbar_same_source.9898489 |
|
|
Aug 27 09:46:17 PM UTC 24 |
Aug 27 09:47:31 PM UTC 24 |
2631035574 ps |
| T2177 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/60.xbar_error_random.611838012 |
|
|
Aug 27 09:47:18 PM UTC 24 |
Aug 27 09:47:35 PM UTC 24 |
252973583 ps |
| T2178 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/58.xbar_stress_all_with_error.2857930976 |
|
|
Aug 27 09:45:27 PM UTC 24 |
Aug 27 09:47:46 PM UTC 24 |
1747074925 ps |
| T2179 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/60.xbar_random_zero_delays.994948061 |
|
|
Aug 27 09:47:06 PM UTC 24 |
Aug 27 09:47:58 PM UTC 24 |
434050896 ps |
| T2180 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/57.xbar_stress_all.3388118442 |
|
|
Aug 27 09:44:16 PM UTC 24 |
Aug 27 09:48:00 PM UTC 24 |
2031979889 ps |
| T2181 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/60.xbar_same_source.2500656358 |
|
|
Aug 27 09:47:18 PM UTC 24 |
Aug 27 09:48:03 PM UTC 24 |
1581327731 ps |
| T2182 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/61.xbar_smoke.181476428 |
|
|
Aug 27 09:47:55 PM UTC 24 |
Aug 27 09:48:07 PM UTC 24 |
162647720 ps |
| T2183 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/61.xbar_smoke_zero_delays.3842777160 |
|
|
Aug 27 09:47:58 PM UTC 24 |
Aug 27 09:48:08 PM UTC 24 |
43958476 ps |
| T2184 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/51.xbar_random_large_delays.2160708803 |
|
|
Aug 27 09:37:19 PM UTC 24 |
Aug 27 09:48:08 PM UTC 24 |
71424354517 ps |
| T2185 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/60.xbar_smoke_large_delays.243576041 |
|
|
Aug 27 09:46:39 PM UTC 24 |
Aug 27 09:48:16 PM UTC 24 |
6046081286 ps |
| T2186 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/54.xbar_random_slow_rsp.2341670030 |
|
|
Aug 27 09:40:39 PM UTC 24 |
Aug 27 09:48:19 PM UTC 24 |
33683491078 ps |
| T2187 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/60.xbar_random.333282184 |
|
|
Aug 27 09:46:52 PM UTC 24 |
Aug 27 09:48:22 PM UTC 24 |
1980124501 ps |
| T2188 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/16.chip_same_csr_outstanding.178423187 |
|
|
Aug 27 08:38:46 PM UTC 24 |
Aug 27 09:48:22 PM UTC 24 |
29197177423 ps |
| T2189 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/58.xbar_stress_all.2660874962 |
|
|
Aug 27 09:45:16 PM UTC 24 |
Aug 27 09:48:23 PM UTC 24 |
4170389731 ps |
| T2190 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/59.xbar_smoke_slow_rsp.2477920109 |
|
|
Aug 27 09:45:51 PM UTC 24 |
Aug 27 09:48:24 PM UTC 24 |
7358878244 ps |
| T2191 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/50.xbar_random_slow_rsp.214363632 |
|
|
Aug 27 09:36:28 PM UTC 24 |
Aug 27 09:48:24 PM UTC 24 |
50580187788 ps |
| T2192 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/60.xbar_error_and_unmapped_addr.4081343307 |
|
|
Aug 27 09:47:44 PM UTC 24 |
Aug 27 09:48:26 PM UTC 24 |
309192769 ps |
| T2193 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/60.xbar_smoke_slow_rsp.1823887876 |
|
|
Aug 27 09:46:41 PM UTC 24 |
Aug 27 09:48:27 PM UTC 24 |
5386695252 ps |
| T2194 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/60.xbar_unmapped_addr.2562493424 |
|
|
Aug 27 09:47:21 PM UTC 24 |
Aug 27 09:48:28 PM UTC 24 |
1284609247 ps |
| T2195 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/60.xbar_random_large_delays.575949571 |
|
|
Aug 27 09:47:06 PM UTC 24 |
Aug 27 09:48:33 PM UTC 24 |
5614144391 ps |
| T2196 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/59.xbar_stress_all.1086451509 |
|
|
Aug 27 09:46:29 PM UTC 24 |
Aug 27 09:48:41 PM UTC 24 |
1673621320 ps |
| T2197 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/61.xbar_random.1417237533 |
|
|
Aug 27 09:48:23 PM UTC 24 |
Aug 27 09:48:45 PM UTC 24 |
671630005 ps |
| T2198 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/56.xbar_random_slow_rsp.145491330 |
|
|
Aug 27 09:42:52 PM UTC 24 |
Aug 27 09:48:46 PM UTC 24 |
25185315212 ps |
| T2199 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/60.xbar_stress_all_with_rand_reset.3697050345 |
|
|
Aug 27 09:47:46 PM UTC 24 |
Aug 27 09:48:52 PM UTC 24 |
148069316 ps |
| T2200 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/57.xbar_stress_all_with_reset_error.2142288732 |
|
|
Aug 27 09:44:32 PM UTC 24 |
Aug 27 09:48:57 PM UTC 24 |
5082627866 ps |
| T2201 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/61.xbar_unmapped_addr.3205217265 |
|
|
Aug 27 09:48:44 PM UTC 24 |
Aug 27 09:48:58 PM UTC 24 |
51921436 ps |
| T2202 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/62.xbar_smoke.1600897079 |
|
|
Aug 27 09:48:49 PM UTC 24 |
Aug 27 09:49:02 PM UTC 24 |
170689206 ps |
| T2203 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/61.xbar_error_random.3235916069 |
|
|
Aug 27 09:48:44 PM UTC 24 |
Aug 27 09:49:05 PM UTC 24 |
294014558 ps |
| T2204 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/61.xbar_random_zero_delays.1851893250 |
|
|
Aug 27 09:48:23 PM UTC 24 |
Aug 27 09:49:05 PM UTC 24 |
552122018 ps |
| T2205 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/62.xbar_smoke_zero_delays.1751146149 |
|
|
Aug 27 09:48:56 PM UTC 24 |
Aug 27 09:49:06 PM UTC 24 |
48422581 ps |
| T2206 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/61.xbar_error_and_unmapped_addr.1501816220 |
|
|
Aug 27 09:48:46 PM UTC 24 |
Aug 27 09:49:08 PM UTC 24 |
145600636 ps |
| T2207 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/49.xbar_random_slow_rsp.4189765956 |
|
|
Aug 27 09:35:27 PM UTC 24 |
Aug 27 09:49:21 PM UTC 24 |
52631738237 ps |
| T2208 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/61.xbar_smoke_slow_rsp.1448440605 |
|
|
Aug 27 09:48:21 PM UTC 24 |
Aug 27 09:49:22 PM UTC 24 |
4585656506 ps |
| T2209 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/56.xbar_stress_all_with_reset_error.1544239816 |
|
|
Aug 27 09:43:23 PM UTC 24 |
Aug 27 09:49:29 PM UTC 24 |
2852629876 ps |
| T2210 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/56.xbar_stress_all_with_error.2061118721 |
|
|
Aug 27 09:43:20 PM UTC 24 |
Aug 27 09:49:35 PM UTC 24 |
11741415843 ps |
| T2211 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/61.xbar_smoke_large_delays.1974423647 |
|
|
Aug 27 09:48:10 PM UTC 24 |
Aug 27 09:49:44 PM UTC 24 |
9068068822 ps |
| T2212 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/62.xbar_unmapped_addr.2890688115 |
|
|
Aug 27 09:49:31 PM UTC 24 |
Aug 27 09:49:46 PM UTC 24 |
118770672 ps |
| T2213 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/61.xbar_same_source.1921945984 |
|
|
Aug 27 09:48:42 PM UTC 24 |
Aug 27 09:49:46 PM UTC 24 |
2543432421 ps |
| T2214 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/62.xbar_random.3851486945 |
|
|
Aug 27 09:49:09 PM UTC 24 |
Aug 27 09:49:50 PM UTC 24 |
839112053 ps |
| T2215 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/62.xbar_access_same_device.658680535 |
|
|
Aug 27 09:49:25 PM UTC 24 |
Aug 27 09:49:50 PM UTC 24 |
134855451 ps |
| T2216 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/62.xbar_same_source.4159834037 |
|
|
Aug 27 09:49:29 PM UTC 24 |
Aug 27 09:49:54 PM UTC 24 |
652506946 ps |
| T2217 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/62.xbar_random_zero_delays.607951656 |
|
|
Aug 27 09:49:15 PM UTC 24 |
Aug 27 09:50:04 PM UTC 24 |
439347172 ps |
| T2218 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/19.chip_same_csr_outstanding.158287333 |
|
|
Aug 27 08:45:31 PM UTC 24 |
Aug 27 09:50:09 PM UTC 24 |
29184304567 ps |
| T2219 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/42.xbar_access_same_device_slow_rsp.1276701072 |
|
|
Aug 27 09:26:04 PM UTC 24 |
Aug 27 09:50:13 PM UTC 24 |
98773891028 ps |
| T2220 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/62.xbar_smoke_large_delays.3313061140 |
|
|
Aug 27 09:49:04 PM UTC 24 |
Aug 27 09:50:18 PM UTC 24 |
8168093789 ps |
| T2221 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/63.xbar_smoke_zero_delays.3379903502 |
|
|
Aug 27 09:50:08 PM UTC 24 |
Aug 27 09:50:18 PM UTC 24 |
49127692 ps |
| T2222 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/62.xbar_error_and_unmapped_addr.3939986562 |
|
|
Aug 27 09:49:44 PM UTC 24 |
Aug 27 09:50:19 PM UTC 24 |
301889856 ps |
| T2223 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/59.xbar_stress_all_with_error.3471625853 |
|
|
Aug 27 09:46:37 PM UTC 24 |
Aug 27 09:50:21 PM UTC 24 |
7275063714 ps |
| T2224 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/63.xbar_smoke.2977990170 |
|
|
Aug 27 09:50:09 PM UTC 24 |
Aug 27 09:50:22 PM UTC 24 |
188983623 ps |
| T2225 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/61.xbar_access_same_device.2718110337 |
|
|
Aug 27 09:48:29 PM UTC 24 |
Aug 27 09:50:24 PM UTC 24 |
2406320524 ps |
| T2226 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/63.xbar_random.513395995 |
|
|
Aug 27 09:50:13 PM UTC 24 |
Aug 27 09:50:29 PM UTC 24 |
153024236 ps |
| T2227 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/62.xbar_error_random.3760169859 |
|
|
Aug 27 09:49:30 PM UTC 24 |
Aug 27 09:50:33 PM UTC 24 |
1639978777 ps |
| T2228 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/60.xbar_stress_all_with_error.3785110438 |
|
|
Aug 27 09:47:46 PM UTC 24 |
Aug 27 09:50:39 PM UTC 24 |
3644695835 ps |
| T2229 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/55.xbar_random_slow_rsp.4286565227 |
|
|
Aug 27 09:41:44 PM UTC 24 |
Aug 27 09:50:40 PM UTC 24 |
34120802022 ps |
| T2230 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/59.xbar_access_same_device_slow_rsp.2670794304 |
|
|
Aug 27 09:46:16 PM UTC 24 |
Aug 27 09:50:46 PM UTC 24 |
19270209077 ps |
| T2231 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/58.xbar_access_same_device_slow_rsp.1568815943 |
|
|
Aug 27 09:44:55 PM UTC 24 |
Aug 27 09:50:50 PM UTC 24 |
22607189988 ps |
| T2232 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/62.xbar_smoke_slow_rsp.1286440100 |
|
|
Aug 27 09:49:07 PM UTC 24 |
Aug 27 09:50:51 PM UTC 24 |
5027602944 ps |
| T2233 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/63.xbar_unmapped_addr.1823480724 |
|
|
Aug 27 09:50:44 PM UTC 24 |
Aug 27 09:50:54 PM UTC 24 |
92856326 ps |
| T2234 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/63.xbar_random_zero_delays.4089249988 |
|
|
Aug 27 09:50:27 PM UTC 24 |
Aug 27 09:50:54 PM UTC 24 |
348490348 ps |
| T2235 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/63.xbar_error_random.3404295309 |
|
|
Aug 27 09:50:45 PM UTC 24 |
Aug 27 09:51:05 PM UTC 24 |
244373241 ps |
| T2236 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/54.xbar_stress_all_with_rand_reset.3627346188 |
|
|
Aug 27 09:40:57 PM UTC 24 |
Aug 27 09:51:06 PM UTC 24 |
12770253912 ps |
| T2237 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/63.xbar_stress_all_with_error.3359757247 |
|
|
Aug 27 09:50:59 PM UTC 24 |
Aug 27 09:51:06 PM UTC 24 |
5533204 ps |
| T2238 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/60.xbar_stress_all.1589674716 |
|
|
Aug 27 09:47:46 PM UTC 24 |
Aug 27 09:51:10 PM UTC 24 |
2389977604 ps |
| T2239 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/62.xbar_stress_all_with_error.4108640004 |
|
|
Aug 27 09:49:57 PM UTC 24 |
Aug 27 09:51:14 PM UTC 24 |
968800084 ps |
| T2240 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/64.xbar_smoke.825588272 |
|
|
Aug 27 09:51:07 PM UTC 24 |
Aug 27 09:51:20 PM UTC 24 |
241936076 ps |
| T2241 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/63.xbar_error_and_unmapped_addr.419795191 |
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|
Aug 27 09:50:46 PM UTC 24 |
Aug 27 09:51:20 PM UTC 24 |
282120940 ps |
| T2242 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/63.xbar_access_same_device.1920687339 |
|
|
Aug 27 09:50:41 PM UTC 24 |
Aug 27 09:51:21 PM UTC 24 |
879971070 ps |
| T2243 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/64.xbar_smoke_zero_delays.1135673171 |
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|
Aug 27 09:51:11 PM UTC 24 |
Aug 27 09:51:22 PM UTC 24 |
53929214 ps |
| T2244 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/51.xbar_stress_all_with_rand_reset.1006096274 |
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|
Aug 27 09:37:44 PM UTC 24 |
Aug 27 09:51:27 PM UTC 24 |
7627722323 ps |
| T2245 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/63.xbar_stress_all.1804880778 |
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|
Aug 27 09:50:52 PM UTC 24 |
Aug 27 09:51:28 PM UTC 24 |
920033203 ps |
| T2246 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/63.xbar_same_source.3347043207 |
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|
Aug 27 09:50:41 PM UTC 24 |
Aug 27 09:51:35 PM UTC 24 |
583751204 ps |
| T2247 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/63.xbar_random_slow_rsp.1713714449 |
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|
Aug 27 09:50:35 PM UTC 24 |
Aug 27 09:51:41 PM UTC 24 |
3665003647 ps |
| T2248 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/64.xbar_random_zero_delays.758096987 |
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|
Aug 27 09:51:26 PM UTC 24 |
Aug 27 09:51:50 PM UTC 24 |
191173209 ps |
| T2249 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/64.xbar_error_random.55366493 |
|
|
Aug 27 09:51:41 PM UTC 24 |
Aug 27 09:51:51 PM UTC 24 |
144142381 ps |
| T2250 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/60.xbar_stress_all_with_reset_error.4290119191 |
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|
Aug 27 09:47:54 PM UTC 24 |
Aug 27 09:51:52 PM UTC 24 |
2671984945 ps |
| T2251 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/64.xbar_access_same_device.374339953 |
|
|
Aug 27 09:51:33 PM UTC 24 |
Aug 27 09:51:56 PM UTC 24 |
588253289 ps |
| T2252 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/64.xbar_unmapped_addr.4172973455 |
|
|
Aug 27 09:51:42 PM UTC 24 |
Aug 27 09:51:58 PM UTC 24 |
70574842 ps |
| T2253 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/63.xbar_smoke_slow_rsp.118477985 |
|
|
Aug 27 09:50:13 PM UTC 24 |
Aug 27 09:51:59 PM UTC 24 |
5709748779 ps |
| T2254 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/63.xbar_smoke_large_delays.3187029788 |
|
|
Aug 27 09:50:12 PM UTC 24 |
Aug 27 09:52:01 PM UTC 24 |
7736949036 ps |
| T2255 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/64.xbar_random.3453512153 |
|
|
Aug 27 09:51:17 PM UTC 24 |
Aug 27 09:52:07 PM UTC 24 |
1164672281 ps |
| T2256 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/64.xbar_error_and_unmapped_addr.212178125 |
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|
Aug 27 09:51:42 PM UTC 24 |
Aug 27 09:52:07 PM UTC 24 |
229934487 ps |
| T2257 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/56.xbar_stress_all_with_rand_reset.4097337841 |
|
|
Aug 27 09:43:16 PM UTC 24 |
Aug 27 09:52:16 PM UTC 24 |
5152090101 ps |
| T2258 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/63.xbar_stress_all_with_rand_reset.3281443599 |
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|
Aug 27 09:50:54 PM UTC 24 |
Aug 27 09:52:20 PM UTC 24 |
225253981 ps |
| T2259 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/65.xbar_smoke_zero_delays.65453371 |
|
|
Aug 27 09:52:14 PM UTC 24 |
Aug 27 09:52:22 PM UTC 24 |
49905509 ps |
| T2260 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/65.xbar_smoke.3402922072 |
|
|
Aug 27 09:52:12 PM UTC 24 |
Aug 27 09:52:23 PM UTC 24 |
184484149 ps |
| T2261 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/64.xbar_smoke_slow_rsp.3042534836 |
|
|
Aug 27 09:51:16 PM UTC 24 |
Aug 27 09:52:30 PM UTC 24 |
5236114630 ps |
| T2262 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/61.xbar_stress_all_with_reset_error.2522338863 |
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|
Aug 27 09:48:48 PM UTC 24 |
Aug 27 09:52:30 PM UTC 24 |
2304610771 ps |
| T2263 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/65.xbar_random.3266059562 |
|
|
Aug 27 09:52:21 PM UTC 24 |
Aug 27 09:52:37 PM UTC 24 |
124938814 ps |
| T2264 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/61.xbar_stress_all_with_error.201201413 |
|
|
Aug 27 09:48:48 PM UTC 24 |
Aug 27 09:52:37 PM UTC 24 |
6583160751 ps |
| T2265 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/64.xbar_same_source.427305661 |
|
|
Aug 27 09:51:37 PM UTC 24 |
Aug 27 09:52:52 PM UTC 24 |
1908302342 ps |