| T1251 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_otbn_smoketest.4068964000 |
|
|
Aug 28 03:30:10 AM UTC 24 |
Aug 28 03:50:50 AM UTC 24 |
6598136032 ps |
| T1252 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/default/3.chip_tap_straps_dev.3922935298 |
|
|
Aug 28 03:38:49 AM UTC 24 |
Aug 28 03:52:37 AM UTC 24 |
9023671167 ps |
| T1253 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_flash_init_reduced_freq.2155588009 |
|
|
Aug 28 03:21:22 AM UTC 24 |
Aug 28 03:52:51 AM UTC 24 |
24075860231 ps |
| T1254 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/default/3.chip_tap_straps_prod.620716319 |
|
|
Aug 28 03:40:56 AM UTC 24 |
Aug 28 03:53:09 AM UTC 24 |
8322632435 ps |
| T1255 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_otbn_ecdsa_op_irq.2870777740 |
|
|
Aug 28 02:40:36 AM UTC 24 |
Aug 28 03:53:44 AM UTC 24 |
17929348816 ps |
| T1256 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/default/4.chip_tap_straps_testunlock0.3346731658 |
|
|
Aug 28 03:47:00 AM UTC 24 |
Aug 28 03:53:46 AM UTC 24 |
5316778239 ps |
| T697 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/default/4.chip_sw_all_escalation_resets.3087516019 |
|
|
Aug 28 03:41:55 AM UTC 24 |
Aug 28 03:53:48 AM UTC 24 |
4344369588 ps |
| T780 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/default/4.chip_sw_alert_handler_lpg_sleep_mode_alerts.3222281566 |
|
|
Aug 28 03:47:33 AM UTC 24 |
Aug 28 03:54:28 AM UTC 24 |
3978840270 ps |
| T1257 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/default/4.chip_sw_uart_tx_rx.1872061666 |
|
|
Aug 28 03:45:33 AM UTC 24 |
Aug 28 03:54:56 AM UTC 24 |
4288348640 ps |
| T1258 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/default/4.chip_sw_aon_timer_sleep_wdog_sleep_pause.3766743234 |
|
|
Aug 28 03:47:11 AM UTC 24 |
Aug 28 03:55:03 AM UTC 24 |
6727887968 ps |
| T1259 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/default/3.chip_sw_uart_tx_rx_alt_clk_freq_low_speed.3020839318 |
|
|
Aug 28 03:37:15 AM UTC 24 |
Aug 28 03:55:28 AM UTC 24 |
8553133902 ps |
| T1260 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/default/4.chip_sw_uart_tx_rx_alt_clk_freq.1341772658 |
|
|
Aug 28 03:46:58 AM UTC 24 |
Aug 28 03:56:09 AM UTC 24 |
4650596322 ps |
| T1261 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/default/4.chip_sw_uart_tx_rx_idx2.1635465727 |
|
|
Aug 28 03:45:34 AM UTC 24 |
Aug 28 03:56:42 AM UTC 24 |
4311497366 ps |
| T1262 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/default/4.chip_sw_uart_tx_rx_alt_clk_freq_low_speed.1147694538 |
|
|
Aug 28 03:47:04 AM UTC 24 |
Aug 28 03:56:56 AM UTC 24 |
5045858731 ps |
| T1263 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/default/4.chip_sw_uart_tx_rx_idx1.2201511432 |
|
|
Aug 28 03:47:29 AM UTC 24 |
Aug 28 03:57:23 AM UTC 24 |
4369050144 ps |
| T1264 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/default/4.chip_sw_uart_tx_rx_idx3.491660357 |
|
|
Aug 28 03:47:21 AM UTC 24 |
Aug 28 03:57:57 AM UTC 24 |
4330138380 ps |
| T293 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/default/4.chip_sw_data_integrity_escalation.2848932635 |
|
|
Aug 28 03:47:31 AM UTC 24 |
Aug 28 03:57:59 AM UTC 24 |
4756245812 ps |
| T719 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/default/5.chip_sw_alert_handler_lpg_sleep_mode_alerts.4033813305 |
|
|
Aug 28 03:51:26 AM UTC 24 |
Aug 28 03:58:28 AM UTC 24 |
3727559682 ps |
| T1265 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/default/5.chip_sw_uart_rand_baudrate.2257484935 |
|
|
Aug 28 03:50:02 AM UTC 24 |
Aug 28 03:58:43 AM UTC 24 |
3653927660 ps |
| T68 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_jtag_csr_rw.3432428634 |
|
|
Aug 28 03:12:07 AM UTC 24 |
Aug 28 03:59:00 AM UTC 24 |
22460803368 ps |
| T429 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/default/5.chip_sw_data_integrity_escalation.2417722234 |
|
|
Aug 28 03:49:58 AM UTC 24 |
Aug 28 03:59:08 AM UTC 24 |
5316855690 ps |
| T430 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/default/4.chip_tap_straps_prod.2485096506 |
|
|
Aug 28 03:48:17 AM UTC 24 |
Aug 28 03:59:10 AM UTC 24 |
7470887105 ps |
| T431 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/default/3.chip_sw_lc_ctrl_transition.3130197019 |
|
|
Aug 28 03:37:29 AM UTC 24 |
Aug 28 03:59:42 AM UTC 24 |
13802487273 ps |
| T432 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/default/6.chip_sw_alert_handler_lpg_sleep_mode_alerts.345332805 |
|
|
Aug 28 03:54:44 AM UTC 24 |
Aug 28 04:01:33 AM UTC 24 |
3059291440 ps |
| T197 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/default/5.chip_sw_all_escalation_resets.1954796927 |
|
|
Aug 28 03:49:13 AM UTC 24 |
Aug 28 04:01:34 AM UTC 24 |
4700984040 ps |
| T338 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/default/7.chip_sw_alert_handler_lpg_sleep_mode_alerts.3301131987 |
|
|
Aug 28 03:55:41 AM UTC 24 |
Aug 28 04:02:35 AM UTC 24 |
3840222680 ps |
| T264 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/default/6.chip_sw_all_escalation_resets.818325393 |
|
|
Aug 28 03:53:27 AM UTC 24 |
Aug 28 04:04:05 AM UTC 24 |
4835677480 ps |
| T342 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/default/1.rom_e2e_self_hash.24728498 |
|
|
Aug 28 01:55:00 AM UTC 24 |
Aug 28 04:04:20 AM UTC 24 |
26326881530 ps |
| T269 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/default/8.chip_sw_alert_handler_lpg_sleep_mode_alerts.920019276 |
|
|
Aug 28 03:58:00 AM UTC 24 |
Aug 28 04:04:23 AM UTC 24 |
3395218982 ps |
| T173 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/default/4.chip_sw_sensor_ctrl_alert.1783270779 |
|
|
Aug 28 03:47:37 AM UTC 24 |
Aug 28 04:05:24 AM UTC 24 |
7885170488 ps |
| T278 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/default/8.chip_sw_all_escalation_resets.2712330857 |
|
|
Aug 28 03:56:47 AM UTC 24 |
Aug 28 04:05:27 AM UTC 24 |
6019318242 ps |
| T305 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/default/7.chip_sw_all_escalation_resets.2552545283 |
|
|
Aug 28 03:54:45 AM UTC 24 |
Aug 28 04:05:49 AM UTC 24 |
5866777136 ps |
| T306 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_lc_walkthrough_dev.3873136743 |
|
|
Aug 28 02:22:22 AM UTC 24 |
Aug 28 04:05:50 AM UTC 24 |
47409954496 ps |
| T307 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/default/8.chip_sw_lc_ctrl_transition.514626455 |
|
|
Aug 28 03:57:31 AM UTC 24 |
Aug 28 04:06:44 AM UTC 24 |
4857821600 ps |
| T308 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/default/9.chip_sw_uart_rand_baudrate.234934387 |
|
|
Aug 28 03:59:14 AM UTC 24 |
Aug 28 04:07:52 AM UTC 24 |
3801905444 ps |
| T309 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/default/9.chip_sw_alert_handler_lpg_sleep_mode_alerts.1717954095 |
|
|
Aug 28 04:00:03 AM UTC 24 |
Aug 28 04:08:55 AM UTC 24 |
3103695500 ps |
| T310 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/default/4.chip_sw_lc_ctrl_transition.3976937242 |
|
|
Aug 28 03:47:32 AM UTC 24 |
Aug 28 04:09:19 AM UTC 24 |
11154353037 ps |
| T311 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/default/5.chip_sw_lc_ctrl_transition.948038749 |
|
|
Aug 28 03:51:02 AM UTC 24 |
Aug 28 04:09:43 AM UTC 24 |
10365381591 ps |
| T107 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/default/10.chip_sw_alert_handler_lpg_sleep_mode_alerts.1834946609 |
|
|
Aug 28 04:02:21 AM UTC 24 |
Aug 28 04:10:06 AM UTC 24 |
3989623790 ps |
| T111 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_lc_walkthrough_rma.3923160894 |
|
|
Aug 28 02:24:04 AM UTC 24 |
Aug 28 04:10:46 AM UTC 24 |
46119242474 ps |
| T112 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/default/9.chip_sw_all_escalation_resets.2507319346 |
|
|
Aug 28 03:58:47 AM UTC 24 |
Aug 28 04:12:23 AM UTC 24 |
6018660956 ps |
| T113 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/default/12.chip_sw_alert_handler_lpg_sleep_mode_alerts.2424651235 |
|
|
Aug 28 04:06:38 AM UTC 24 |
Aug 28 04:12:51 AM UTC 24 |
4036248964 ps |
| T114 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/default/11.chip_sw_all_escalation_resets.2114232266 |
|
|
Aug 28 04:03:12 AM UTC 24 |
Aug 28 04:12:59 AM UTC 24 |
4202039294 ps |
| T115 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/default/10.chip_sw_all_escalation_resets.342093976 |
|
|
Aug 28 04:00:04 AM UTC 24 |
Aug 28 04:13:06 AM UTC 24 |
5461242876 ps |
| T116 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/default/11.chip_sw_alert_handler_lpg_sleep_mode_alerts.3388295964 |
|
|
Aug 28 04:05:07 AM UTC 24 |
Aug 28 04:13:31 AM UTC 24 |
3883958910 ps |
| T117 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_csrng_edn_concurrency.2448671402 |
|
|
Aug 28 02:52:37 AM UTC 24 |
Aug 28 04:13:38 AM UTC 24 |
16564476706 ps |
| T118 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/default/6.chip_sw_lc_ctrl_transition.938530407 |
|
|
Aug 28 03:53:45 AM UTC 24 |
Aug 28 04:14:02 AM UTC 24 |
13021114032 ps |
| T119 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/default/11.chip_sw_lc_ctrl_transition.2459925746 |
|
|
Aug 28 04:05:06 AM UTC 24 |
Aug 28 04:14:56 AM UTC 24 |
7130753532 ps |
| T1266 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/default/9.chip_sw_lc_ctrl_transition.2788905261 |
|
|
Aug 28 03:59:18 AM UTC 24 |
Aug 28 04:15:59 AM UTC 24 |
10157650159 ps |
| T1267 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/default/7.chip_sw_lc_ctrl_transition.2315751402 |
|
|
Aug 28 03:55:41 AM UTC 24 |
Aug 28 04:16:07 AM UTC 24 |
10630040758 ps |
| T774 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/default/13.chip_sw_alert_handler_lpg_sleep_mode_alerts.948702967 |
|
|
Aug 28 04:09:34 AM UTC 24 |
Aug 28 04:16:36 AM UTC 24 |
3942604084 ps |
| T1268 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/default/4.chip_sw_uart_rand_baudrate.1955429035 |
|
|
Aug 28 03:47:09 AM UTC 24 |
Aug 28 04:16:55 AM UTC 24 |
8533866088 ps |
| T1269 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/default/13.chip_sw_lc_ctrl_transition.2326902297 |
|
|
Aug 28 04:09:30 AM UTC 24 |
Aug 28 04:18:05 AM UTC 24 |
4996109640 ps |
| T374 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/default/12.chip_sw_all_escalation_resets.2445071752 |
|
|
Aug 28 04:06:13 AM UTC 24 |
Aug 28 04:18:21 AM UTC 24 |
5516205340 ps |
| T391 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/default/13.chip_sw_all_escalation_resets.3853077714 |
|
|
Aug 28 04:07:18 AM UTC 24 |
Aug 28 04:19:33 AM UTC 24 |
5235601640 ps |
| T392 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/default/6.chip_sw_uart_rand_baudrate.2564250338 |
|
|
Aug 28 03:53:31 AM UTC 24 |
Aug 28 04:20:03 AM UTC 24 |
9245958760 ps |
| T393 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/default/14.chip_sw_lc_ctrl_transition.1069015510 |
|
|
Aug 28 04:10:43 AM UTC 24 |
Aug 28 04:20:10 AM UTC 24 |
6594201230 ps |
| T179 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_ast_clk_rst_inputs.1313872702 |
|
|
Aug 28 03:22:43 AM UTC 24 |
Aug 28 04:20:15 AM UTC 24 |
23383501987 ps |
| T394 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/default/14.chip_sw_alert_handler_lpg_sleep_mode_alerts.42549669 |
|
|
Aug 28 04:11:24 AM UTC 24 |
Aug 28 04:20:27 AM UTC 24 |
4574120940 ps |
| T198 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/default/14.chip_sw_all_escalation_resets.3235023361 |
|
|
Aug 28 04:09:57 AM UTC 24 |
Aug 28 04:20:35 AM UTC 24 |
5923316360 ps |
| T395 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/default/16.chip_sw_alert_handler_lpg_sleep_mode_alerts.2178897216 |
|
|
Aug 28 04:14:24 AM UTC 24 |
Aug 28 04:20:38 AM UTC 24 |
3547972148 ps |
| T396 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/default/2.rom_e2e_asm_init_test_unlocked0.4156869253 |
|
|
Aug 28 03:26:36 AM UTC 24 |
Aug 28 04:20:51 AM UTC 24 |
11572996697 ps |
| T248 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_keymgr_sideload_otbn.3987152599 |
|
|
Aug 28 02:58:57 AM UTC 24 |
Aug 28 04:20:53 AM UTC 24 |
17166290264 ps |
| T1270 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/default/7.chip_sw_uart_rand_baudrate.2122806590 |
|
|
Aug 28 03:55:06 AM UTC 24 |
Aug 28 04:21:45 AM UTC 24 |
8667076960 ps |
| T753 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/default/15.chip_sw_alert_handler_lpg_sleep_mode_alerts.3105575689 |
|
|
Aug 28 04:13:52 AM UTC 24 |
Aug 28 04:21:57 AM UTC 24 |
4208630600 ps |
| T1271 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/default/10.chip_sw_lc_ctrl_transition.4170728207 |
|
|
Aug 28 04:02:20 AM UTC 24 |
Aug 28 04:22:49 AM UTC 24 |
11331803138 ps |
| T1272 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_lc_walkthrough_prod.346259652 |
|
|
Aug 28 02:22:22 AM UTC 24 |
Aug 28 04:23:10 AM UTC 24 |
50910868597 ps |
| T1273 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/default/12.chip_sw_lc_ctrl_transition.1168886588 |
|
|
Aug 28 04:06:37 AM UTC 24 |
Aug 28 04:24:25 AM UTC 24 |
10092240866 ps |
| T755 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/default/18.chip_sw_alert_handler_lpg_sleep_mode_alerts.2124367693 |
|
|
Aug 28 04:17:32 AM UTC 24 |
Aug 28 04:24:37 AM UTC 24 |
3918040694 ps |
| T720 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/default/17.chip_sw_alert_handler_lpg_sleep_mode_alerts.2345282913 |
|
|
Aug 28 04:16:50 AM UTC 24 |
Aug 28 04:24:51 AM UTC 24 |
3969898260 ps |
| T1274 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/default/17.chip_sw_uart_rand_baudrate.2207059260 |
|
|
Aug 28 04:15:32 AM UTC 24 |
Aug 28 04:25:32 AM UTC 24 |
4204205320 ps |
| T1275 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/default/16.chip_sw_all_escalation_resets.1441566486 |
|
|
Aug 28 04:14:06 AM UTC 24 |
Aug 28 04:25:37 AM UTC 24 |
6441084042 ps |
| T279 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/default/17.chip_sw_all_escalation_resets.386151312 |
|
|
Aug 28 04:14:41 AM UTC 24 |
Aug 28 04:25:39 AM UTC 24 |
4903500366 ps |
| T280 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/default/15.chip_sw_all_escalation_resets.3768972916 |
|
|
Aug 28 04:12:55 AM UTC 24 |
Aug 28 04:26:01 AM UTC 24 |
5607445488 ps |
| T1276 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/default/8.chip_sw_uart_rand_baudrate.3641764236 |
|
|
Aug 28 03:57:27 AM UTC 24 |
Aug 28 04:26:40 AM UTC 24 |
8586696360 ps |
| T1277 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/default/3.chip_sw_uart_tx_rx_alt_clk_freq.654976357 |
|
|
Aug 28 03:37:01 AM UTC 24 |
Aug 28 04:26:55 AM UTC 24 |
13486812032 ps |
| T1278 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/default/2.rom_e2e_asm_init_dev.1912813614 |
|
|
Aug 28 03:27:43 AM UTC 24 |
Aug 28 04:42:22 AM UTC 24 |
15844375460 ps |
| T1279 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/default/18.chip_sw_uart_rand_baudrate.155540171 |
|
|
Aug 28 04:17:14 AM UTC 24 |
Aug 28 04:27:31 AM UTC 24 |
4632913250 ps |
| T783 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/default/19.chip_sw_alert_handler_lpg_sleep_mode_alerts.496348993 |
|
|
Aug 28 04:20:10 AM UTC 24 |
Aug 28 04:27:46 AM UTC 24 |
4199265384 ps |
| T727 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/default/20.chip_sw_alert_handler_lpg_sleep_mode_alerts.1995625222 |
|
|
Aug 28 04:21:21 AM UTC 24 |
Aug 28 04:27:56 AM UTC 24 |
3472009410 ps |
| T1280 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/default/19.chip_sw_uart_rand_baudrate.2012575332 |
|
|
Aug 28 04:18:57 AM UTC 24 |
Aug 28 04:28:00 AM UTC 24 |
4491408488 ps |
| T768 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/default/18.chip_sw_all_escalation_resets.713495843 |
|
|
Aug 28 04:16:51 AM UTC 24 |
Aug 28 04:28:03 AM UTC 24 |
5322505176 ps |
| T743 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/default/24.chip_sw_alert_handler_lpg_sleep_mode_alerts.1481369926 |
|
|
Aug 28 04:22:39 AM UTC 24 |
Aug 28 04:29:02 AM UTC 24 |
3551715760 ps |
| T1281 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/default/10.chip_sw_uart_rand_baudrate.2271920721 |
|
|
Aug 28 04:00:18 AM UTC 24 |
Aug 28 04:29:06 AM UTC 24 |
8918991806 ps |
| T724 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/default/22.chip_sw_alert_handler_lpg_sleep_mode_alerts.3338283762 |
|
|
Aug 28 04:22:09 AM UTC 24 |
Aug 28 04:29:18 AM UTC 24 |
3033629466 ps |
| T1282 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/default/21.chip_sw_alert_handler_lpg_sleep_mode_alerts.2990849780 |
|
|
Aug 28 04:22:05 AM UTC 24 |
Aug 28 04:30:02 AM UTC 24 |
3433939016 ps |
| T705 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/default/22.chip_sw_all_escalation_resets.280022549 |
|
|
Aug 28 04:22:02 AM UTC 24 |
Aug 28 04:30:38 AM UTC 24 |
5504456000 ps |
| T725 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/default/23.chip_sw_alert_handler_lpg_sleep_mode_alerts.105841900 |
|
|
Aug 28 04:22:07 AM UTC 24 |
Aug 28 04:30:46 AM UTC 24 |
4552156584 ps |
| T786 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/default/25.chip_sw_alert_handler_lpg_sleep_mode_alerts.2087858436 |
|
|
Aug 28 04:23:47 AM UTC 24 |
Aug 28 04:31:23 AM UTC 24 |
3572989170 ps |
| T688 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/default/19.chip_sw_all_escalation_resets.1889293535 |
|
|
Aug 28 04:18:40 AM UTC 24 |
Aug 28 04:32:07 AM UTC 24 |
5775788890 ps |
| T1283 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/default/2.rom_e2e_shutdown_output.2040569225 |
|
|
Aug 28 03:27:07 AM UTC 24 |
Aug 28 04:32:16 AM UTC 24 |
25553350680 ps |
| T1284 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/default/5.chip_sw_csrng_edn_concurrency.2555455772 |
|
|
Aug 28 03:51:29 AM UTC 24 |
Aug 28 04:32:21 AM UTC 24 |
9676441800 ps |
| T696 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/default/27.chip_sw_alert_handler_lpg_sleep_mode_alerts.2191061304 |
|
|
Aug 28 04:25:31 AM UTC 24 |
Aug 28 04:32:25 AM UTC 24 |
3699986978 ps |
| T1285 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/default/2.rom_e2e_shutdown_exception_c.3789305126 |
|
|
Aug 28 03:25:58 AM UTC 24 |
Aug 28 04:32:30 AM UTC 24 |
14114345220 ps |
| T770 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/default/20.chip_sw_all_escalation_resets.695725599 |
|
|
Aug 28 04:22:05 AM UTC 24 |
Aug 28 04:32:46 AM UTC 24 |
6398297936 ps |
| T677 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/default/21.chip_sw_all_escalation_resets.954160173 |
|
|
Aug 28 04:21:55 AM UTC 24 |
Aug 28 04:32:52 AM UTC 24 |
5699819576 ps |
| T784 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/default/29.chip_sw_alert_handler_lpg_sleep_mode_alerts.2593718063 |
|
|
Aug 28 04:26:50 AM UTC 24 |
Aug 28 04:33:04 AM UTC 24 |
3635847592 ps |
| T713 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/default/23.chip_sw_all_escalation_resets.1917480008 |
|
|
Aug 28 04:22:21 AM UTC 24 |
Aug 28 04:33:55 AM UTC 24 |
4493179000 ps |
| T738 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/default/28.chip_sw_alert_handler_lpg_sleep_mode_alerts.525091607 |
|
|
Aug 28 04:26:43 AM UTC 24 |
Aug 28 04:33:59 AM UTC 24 |
3868377166 ps |
| T270 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/default/26.chip_sw_alert_handler_lpg_sleep_mode_alerts.1815290283 |
|
|
Aug 28 04:25:14 AM UTC 24 |
Aug 28 04:34:01 AM UTC 24 |
3917774158 ps |
| T744 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/default/30.chip_sw_alert_handler_lpg_sleep_mode_alerts.1754138903 |
|
|
Aug 28 04:27:32 AM UTC 24 |
Aug 28 04:34:05 AM UTC 24 |
3200084086 ps |
| T747 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/default/25.chip_sw_all_escalation_resets.2066709743 |
|
|
Aug 28 04:23:27 AM UTC 24 |
Aug 28 04:34:28 AM UTC 24 |
5673847940 ps |
| T742 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/default/24.chip_sw_all_escalation_resets.741596122 |
|
|
Aug 28 04:22:37 AM UTC 24 |
Aug 28 04:34:36 AM UTC 24 |
5547775024 ps |
| T1286 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq.1079485735 |
|
|
Aug 28 03:20:08 AM UTC 24 |
Aug 28 04:35:32 AM UTC 24 |
24581571981 ps |
| T759 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/default/30.chip_sw_all_escalation_resets.327392281 |
|
|
Aug 28 04:27:28 AM UTC 24 |
Aug 28 04:35:45 AM UTC 24 |
4189746104 ps |
| T745 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/default/29.chip_sw_all_escalation_resets.4214378010 |
|
|
Aug 28 04:26:47 AM UTC 24 |
Aug 28 04:35:46 AM UTC 24 |
4604718520 ps |
| T722 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/default/31.chip_sw_alert_handler_lpg_sleep_mode_alerts.731500099 |
|
|
Aug 28 04:29:04 AM UTC 24 |
Aug 28 04:35:50 AM UTC 24 |
4045439812 ps |
| T758 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/default/34.chip_sw_alert_handler_lpg_sleep_mode_alerts.1980337655 |
|
|
Aug 28 04:30:06 AM UTC 24 |
Aug 28 04:35:57 AM UTC 24 |
4084717982 ps |
| T1287 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/default/12.chip_sw_uart_rand_baudrate.1570990480 |
|
|
Aug 28 04:06:21 AM UTC 24 |
Aug 28 04:36:01 AM UTC 24 |
9083977140 ps |
| T1288 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/default/2.rom_e2e_asm_init_prod_end.1336301153 |
|
|
Aug 28 03:26:03 AM UTC 24 |
Aug 28 04:36:04 AM UTC 24 |
15658324871 ps |
| T1289 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/default/2.rom_e2e_smoke.2063877467 |
|
|
Aug 28 03:26:47 AM UTC 24 |
Aug 28 04:36:12 AM UTC 24 |
14954856504 ps |
| T703 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/default/26.chip_sw_all_escalation_resets.73087742 |
|
|
Aug 28 04:24:13 AM UTC 24 |
Aug 28 04:36:13 AM UTC 24 |
5667230000 ps |
| T772 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/default/32.chip_sw_alert_handler_lpg_sleep_mode_alerts.1817192940 |
|
|
Aug 28 04:29:05 AM UTC 24 |
Aug 28 04:36:29 AM UTC 24 |
3363519000 ps |
| T1290 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/default/2.rom_e2e_asm_init_rma.371084240 |
|
|
Aug 28 03:27:09 AM UTC 24 |
Aug 28 04:36:35 AM UTC 24 |
14380362224 ps |
| T1291 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/default/13.chip_sw_uart_rand_baudrate.1037452488 |
|
|
Aug 28 04:08:30 AM UTC 24 |
Aug 28 04:36:50 AM UTC 24 |
8327274152 ps |
| T1292 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/default/33.chip_sw_alert_handler_lpg_sleep_mode_alerts.3282946518 |
|
|
Aug 28 04:30:02 AM UTC 24 |
Aug 28 04:36:51 AM UTC 24 |
3495322624 ps |
| T751 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/default/31.chip_sw_all_escalation_resets.2923086230 |
|
|
Aug 28 04:28:09 AM UTC 24 |
Aug 28 04:37:04 AM UTC 24 |
5120085956 ps |
| T281 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/default/27.chip_sw_all_escalation_resets.629927586 |
|
|
Aug 28 04:25:28 AM UTC 24 |
Aug 28 04:37:06 AM UTC 24 |
6547257000 ps |
| T728 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/default/33.chip_sw_all_escalation_resets.571113013 |
|
|
Aug 28 04:29:01 AM UTC 24 |
Aug 28 04:37:08 AM UTC 24 |
5118945944 ps |
| T1293 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/default/2.rom_e2e_keymgr_init_rom_ext_no_meas.1010237217 |
|
|
Aug 28 03:27:06 AM UTC 24 |
Aug 28 04:37:15 AM UTC 24 |
15283327058 ps |
| T735 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/default/35.chip_sw_alert_handler_lpg_sleep_mode_alerts.561370017 |
|
|
Aug 28 04:31:29 AM UTC 24 |
Aug 28 04:37:23 AM UTC 24 |
4022970204 ps |
| T777 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/default/36.chip_sw_alert_handler_lpg_sleep_mode_alerts.3872307853 |
|
|
Aug 28 04:32:00 AM UTC 24 |
Aug 28 04:38:12 AM UTC 24 |
3638553994 ps |
| T698 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/default/28.chip_sw_all_escalation_resets.2744764454 |
|
|
Aug 28 04:26:46 AM UTC 24 |
Aug 28 04:38:15 AM UTC 24 |
5257275296 ps |
| T1294 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/default/2.rom_e2e_keymgr_init_rom_ext_meas.4001028605 |
|
|
Aug 28 03:27:04 AM UTC 24 |
Aug 28 04:38:30 AM UTC 24 |
15454055640 ps |
| T1295 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/default/15.chip_sw_uart_rand_baudrate.4188340698 |
|
|
Aug 28 04:13:51 AM UTC 24 |
Aug 28 04:38:44 AM UTC 24 |
8929780210 ps |
| T1296 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/default/9.chip_sw_csrng_edn_concurrency.4009358841 |
|
|
Aug 28 04:00:03 AM UTC 24 |
Aug 28 04:39:19 AM UTC 24 |
9412368234 ps |
| T769 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/default/35.chip_sw_all_escalation_resets.2621060325 |
|
|
Aug 28 04:30:41 AM UTC 24 |
Aug 28 04:39:22 AM UTC 24 |
4826414760 ps |
| T1297 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/default/2.rom_e2e_keymgr_init_rom_ext_invalid_meas.1580683024 |
|
|
Aug 28 03:27:08 AM UTC 24 |
Aug 28 04:39:22 AM UTC 24 |
14989581128 ps |
| T740 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/default/40.chip_sw_alert_handler_lpg_sleep_mode_alerts.312837302 |
|
|
Aug 28 04:34:16 AM UTC 24 |
Aug 28 04:39:42 AM UTC 24 |
4352829728 ps |
| T726 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/default/39.chip_sw_alert_handler_lpg_sleep_mode_alerts.640704569 |
|
|
Aug 28 04:34:15 AM UTC 24 |
Aug 28 04:39:55 AM UTC 24 |
3548201130 ps |
| T693 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/default/37.chip_sw_alert_handler_lpg_sleep_mode_alerts.4227728228 |
|
|
Aug 28 04:33:26 AM UTC 24 |
Aug 28 04:40:08 AM UTC 24 |
3320627334 ps |
| T1298 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/default/2.rom_e2e_asm_init_prod.2433504529 |
|
|
Aug 28 03:27:47 AM UTC 24 |
Aug 28 04:40:10 AM UTC 24 |
15302395106 ps |
| T723 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/default/32.chip_sw_all_escalation_resets.2559618546 |
|
|
Aug 28 04:29:00 AM UTC 24 |
Aug 28 04:40:11 AM UTC 24 |
5923346900 ps |
| T765 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/default/42.chip_sw_alert_handler_lpg_sleep_mode_alerts.3058649199 |
|
|
Aug 28 04:35:41 AM UTC 24 |
Aug 28 04:40:18 AM UTC 24 |
3632892400 ps |
| T301 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/default/38.chip_sw_alert_handler_lpg_sleep_mode_alerts.3804638213 |
|
|
Aug 28 04:34:17 AM UTC 24 |
Aug 28 04:40:36 AM UTC 24 |
3891735124 ps |
| T1299 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/default/34.chip_sw_all_escalation_resets.393031573 |
|
|
Aug 28 04:30:05 AM UTC 24 |
Aug 28 04:40:40 AM UTC 24 |
5450680250 ps |
| T773 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/default/41.chip_sw_alert_handler_lpg_sleep_mode_alerts.1165919756 |
|
|
Aug 28 04:35:48 AM UTC 24 |
Aug 28 04:40:53 AM UTC 24 |
3213110630 ps |
| T1300 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/default/36.chip_sw_all_escalation_resets.451430348 |
|
|
Aug 28 04:31:30 AM UTC 24 |
Aug 28 04:41:00 AM UTC 24 |
5903040434 ps |
| T714 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/default/37.chip_sw_all_escalation_resets.3965318878 |
|
|
Aug 28 04:34:06 AM UTC 24 |
Aug 28 04:41:13 AM UTC 24 |
4400727496 ps |
| T1301 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/default/2.rom_e2e_static_critical.1958865657 |
|
|
Aug 28 03:27:01 AM UTC 24 |
Aug 28 04:41:36 AM UTC 24 |
17192451450 ps |
| T711 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/default/38.chip_sw_all_escalation_resets.2809278404 |
|
|
Aug 28 04:34:18 AM UTC 24 |
Aug 28 04:41:38 AM UTC 24 |
4581784088 ps |
| T1302 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/default/16.chip_sw_uart_rand_baudrate.3908908423 |
|
|
Aug 28 04:14:23 AM UTC 24 |
Aug 28 04:42:14 AM UTC 24 |
7978010900 ps |
| T689 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/default/39.chip_sw_all_escalation_resets.1175487284 |
|
|
Aug 28 04:34:05 AM UTC 24 |
Aug 28 04:42:39 AM UTC 24 |
6199613040 ps |
| T1303 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/default/40.chip_sw_all_escalation_resets.171003370 |
|
|
Aug 28 04:34:17 AM UTC 24 |
Aug 28 04:42:41 AM UTC 24 |
4564471360 ps |
| T746 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/default/43.chip_sw_alert_handler_lpg_sleep_mode_alerts.2881953152 |
|
|
Aug 28 04:35:50 AM UTC 24 |
Aug 28 04:42:49 AM UTC 24 |
3557776392 ps |
| T108 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/default/42.chip_sw_all_escalation_resets.1756272671 |
|
|
Aug 28 04:35:47 AM UTC 24 |
Aug 28 04:43:44 AM UTC 24 |
4762305800 ps |
| T687 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/default/52.chip_sw_alert_handler_lpg_sleep_mode_alerts.2958238282 |
|
|
Aug 28 04:39:15 AM UTC 24 |
Aug 28 04:43:46 AM UTC 24 |
3107506272 ps |
| T1304 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/default/44.chip_sw_all_escalation_resets.3049695405 |
|
|
Aug 28 04:35:52 AM UTC 24 |
Aug 28 04:44:08 AM UTC 24 |
4100085318 ps |
| T715 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/default/48.chip_sw_alert_handler_lpg_sleep_mode_alerts.2842097791 |
|
|
Aug 28 04:40:10 AM UTC 24 |
Aug 28 04:44:24 AM UTC 24 |
3412830568 ps |
| T375 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/default/43.chip_sw_all_escalation_resets.2587042585 |
|
|
Aug 28 04:35:48 AM UTC 24 |
Aug 28 04:44:29 AM UTC 24 |
4095828712 ps |
| T282 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/default/41.chip_sw_all_escalation_resets.2810511982 |
|
|
Aug 28 04:35:37 AM UTC 24 |
Aug 28 04:45:06 AM UTC 24 |
5639378104 ps |
| T781 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/default/47.chip_sw_alert_handler_lpg_sleep_mode_alerts.483538209 |
|
|
Aug 28 04:39:06 AM UTC 24 |
Aug 28 04:45:18 AM UTC 24 |
3929971240 ps |
| T704 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/default/49.chip_sw_alert_handler_lpg_sleep_mode_alerts.901077733 |
|
|
Aug 28 04:39:33 AM UTC 24 |
Aug 28 04:45:34 AM UTC 24 |
3673977904 ps |
| T673 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/default/45.chip_sw_alert_handler_lpg_sleep_mode_alerts.842443713 |
|
|
Aug 28 04:39:04 AM UTC 24 |
Aug 28 04:45:40 AM UTC 24 |
3617038184 ps |
| T376 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/default/55.chip_sw_alert_handler_lpg_sleep_mode_alerts.382443078 |
|
|
Aug 28 04:40:40 AM UTC 24 |
Aug 28 04:45:52 AM UTC 24 |
4601030440 ps |
| T109 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/default/51.chip_sw_alert_handler_lpg_sleep_mode_alerts.2713566181 |
|
|
Aug 28 04:39:44 AM UTC 24 |
Aug 28 04:45:53 AM UTC 24 |
4107429808 ps |
| T729 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/default/46.chip_sw_alert_handler_lpg_sleep_mode_alerts.3396579378 |
|
|
Aug 28 04:39:35 AM UTC 24 |
Aug 28 04:46:41 AM UTC 24 |
3662757424 ps |
| T737 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/default/45.chip_sw_all_escalation_resets.355215530 |
|
|
Aug 28 04:37:38 AM UTC 24 |
Aug 28 04:46:56 AM UTC 24 |
5561412560 ps |
| T785 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/default/50.chip_sw_alert_handler_lpg_sleep_mode_alerts.469651405 |
|
|
Aug 28 04:40:42 AM UTC 24 |
Aug 28 04:47:11 AM UTC 24 |
4323445528 ps |
| T302 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/default/53.chip_sw_alert_handler_lpg_sleep_mode_alerts.313076622 |
|
|
Aug 28 04:40:40 AM UTC 24 |
Aug 28 04:47:32 AM UTC 24 |
4120039800 ps |
| T1305 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/default/54.chip_sw_alert_handler_lpg_sleep_mode_alerts.4020780094 |
|
|
Aug 28 04:42:04 AM UTC 24 |
Aug 28 04:48:05 AM UTC 24 |
3473299748 ps |
| T1306 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/default/57.chip_sw_alert_handler_lpg_sleep_mode_alerts.1366787967 |
|
|
Aug 28 04:42:58 AM UTC 24 |
Aug 28 04:48:06 AM UTC 24 |
3236504308 ps |
| T674 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/default/56.chip_sw_alert_handler_lpg_sleep_mode_alerts.4203471216 |
|
|
Aug 28 04:42:02 AM UTC 24 |
Aug 28 04:48:23 AM UTC 24 |
3459897384 ps |
| T110 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/default/50.chip_sw_all_escalation_resets.2329303166 |
|
|
Aug 28 04:39:30 AM UTC 24 |
Aug 28 04:48:26 AM UTC 24 |
5836586982 ps |
| T760 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/default/61.chip_sw_alert_handler_lpg_sleep_mode_alerts.2441842724 |
|
|
Aug 28 04:43:08 AM UTC 24 |
Aug 28 04:48:52 AM UTC 24 |
3738223260 ps |
| T339 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/default/59.chip_sw_alert_handler_lpg_sleep_mode_alerts.3872413107 |
|
|
Aug 28 04:43:55 AM UTC 24 |
Aug 28 04:49:13 AM UTC 24 |
3891728680 ps |
| T730 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/default/58.chip_sw_alert_handler_lpg_sleep_mode_alerts.3887794075 |
|
|
Aug 28 04:42:31 AM UTC 24 |
Aug 28 04:49:44 AM UTC 24 |
4417972472 ps |
| T731 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/default/52.chip_sw_all_escalation_resets.3519851356 |
|
|
Aug 28 04:39:54 AM UTC 24 |
Aug 28 04:49:46 AM UTC 24 |
4578722202 ps |
| T699 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/default/53.chip_sw_all_escalation_resets.3256458196 |
|
|
Aug 28 04:40:30 AM UTC 24 |
Aug 28 04:49:51 AM UTC 24 |
4826141640 ps |
| T303 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/default/64.chip_sw_alert_handler_lpg_sleep_mode_alerts.2613848248 |
|
|
Aug 28 04:43:52 AM UTC 24 |
Aug 28 04:49:56 AM UTC 24 |
3548987372 ps |
| T762 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/default/60.chip_sw_alert_handler_lpg_sleep_mode_alerts.1700439504 |
|
|
Aug 28 04:43:28 AM UTC 24 |
Aug 28 04:50:01 AM UTC 24 |
3578755424 ps |
| T692 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/default/47.chip_sw_all_escalation_resets.3572045823 |
|
|
Aug 28 04:40:47 AM UTC 24 |
Aug 28 04:50:11 AM UTC 24 |
5763642572 ps |
| T733 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/default/65.chip_sw_alert_handler_lpg_sleep_mode_alerts.3011973072 |
|
|
Aug 28 04:43:54 AM UTC 24 |
Aug 28 04:50:12 AM UTC 24 |
2913222916 ps |
| T672 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/default/54.chip_sw_all_escalation_resets.3288548379 |
|
|
Aug 28 04:40:47 AM UTC 24 |
Aug 28 04:50:24 AM UTC 24 |
6002797744 ps |
| T1307 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/default/8.chip_sw_csrng_edn_concurrency.2663146999 |
|
|
Aug 28 03:58:47 AM UTC 24 |
Aug 28 04:50:35 AM UTC 24 |
12335988784 ps |
| T708 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/default/63.chip_sw_alert_handler_lpg_sleep_mode_alerts.2564396731 |
|
|
Aug 28 04:43:28 AM UTC 24 |
Aug 28 04:50:36 AM UTC 24 |
3716984920 ps |
| T1308 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/default/66.chip_sw_alert_handler_lpg_sleep_mode_alerts.1051005265 |
|
|
Aug 28 04:44:32 AM UTC 24 |
Aug 28 04:50:51 AM UTC 24 |
3119152570 ps |
| T1309 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/default/62.chip_sw_alert_handler_lpg_sleep_mode_alerts.3531476688 |
|
|
Aug 28 04:43:30 AM UTC 24 |
Aug 28 04:50:53 AM UTC 24 |
3830961464 ps |
| T766 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/default/48.chip_sw_all_escalation_resets.2134994145 |
|
|
Aug 28 04:40:02 AM UTC 24 |
Aug 28 04:50:55 AM UTC 24 |
5439801638 ps |
| T757 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/default/62.chip_sw_all_escalation_resets.404815774 |
|
|
Aug 28 04:42:59 AM UTC 24 |
Aug 28 04:51:04 AM UTC 24 |
5487542892 ps |
| T304 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/default/61.chip_sw_all_escalation_resets.701101425 |
|
|
Aug 28 04:43:00 AM UTC 24 |
Aug 28 04:51:25 AM UTC 24 |
4695567800 ps |
| T1310 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/default/11.chip_sw_uart_rand_baudrate.881729641 |
|
|
Aug 28 04:05:00 AM UTC 24 |
Aug 28 04:51:29 AM UTC 24 |
13564823768 ps |
| T700 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/default/46.chip_sw_all_escalation_resets.1106958787 |
|
|
Aug 28 04:39:30 AM UTC 24 |
Aug 28 04:51:33 AM UTC 24 |
6366695576 ps |
| T390 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/default/51.chip_sw_all_escalation_resets.2475741083 |
|
|
Aug 28 04:40:29 AM UTC 24 |
Aug 28 04:51:47 AM UTC 24 |
5521324900 ps |
| T767 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/default/57.chip_sw_all_escalation_resets.2077260477 |
|
|
Aug 28 04:41:32 AM UTC 24 |
Aug 28 04:51:55 AM UTC 24 |
6209942280 ps |
| T1311 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/default/58.chip_sw_all_escalation_resets.1871464454 |
|
|
Aug 28 04:42:31 AM UTC 24 |
Aug 28 04:52:08 AM UTC 24 |
4897063260 ps |
| T283 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/default/65.chip_sw_all_escalation_resets.3520111043 |
|
|
Aug 28 04:43:49 AM UTC 24 |
Aug 28 04:52:11 AM UTC 24 |
4915615820 ps |
| T775 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/default/49.chip_sw_all_escalation_resets.272392747 |
|
|
Aug 28 04:39:33 AM UTC 24 |
Aug 28 04:52:18 AM UTC 24 |
5540061608 ps |
| T763 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/default/69.chip_sw_alert_handler_lpg_sleep_mode_alerts.4199581954 |
|
|
Aug 28 04:46:06 AM UTC 24 |
Aug 28 04:52:21 AM UTC 24 |
3891512132 ps |
| T1312 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/default/55.chip_sw_all_escalation_resets.2449218913 |
|
|
Aug 28 04:42:27 AM UTC 24 |
Aug 28 04:52:29 AM UTC 24 |
5252706422 ps |
| T340 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/default/67.chip_sw_alert_handler_lpg_sleep_mode_alerts.3665982573 |
|
|
Aug 28 04:44:46 AM UTC 24 |
Aug 28 04:52:44 AM UTC 24 |
4443592080 ps |
| T1313 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/default/67.chip_sw_all_escalation_resets.842010782 |
|
|
Aug 28 04:44:32 AM UTC 24 |
Aug 28 04:52:53 AM UTC 24 |
5232876092 ps |
| T778 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/default/68.chip_sw_alert_handler_lpg_sleep_mode_alerts.1762971214 |
|
|
Aug 28 04:45:14 AM UTC 24 |
Aug 28 04:53:10 AM UTC 24 |
3961503848 ps |
| T681 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/default/72.chip_sw_alert_handler_lpg_sleep_mode_alerts.1955227482 |
|
|
Aug 28 04:47:45 AM UTC 24 |
Aug 28 04:53:15 AM UTC 24 |
3284705504 ps |
| T752 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/default/59.chip_sw_all_escalation_resets.1858984363 |
|
|
Aug 28 04:42:58 AM UTC 24 |
Aug 28 04:53:24 AM UTC 24 |
5962676480 ps |
| T756 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/default/70.chip_sw_alert_handler_lpg_sleep_mode_alerts.3105152440 |
|
|
Aug 28 04:46:45 AM UTC 24 |
Aug 28 04:53:26 AM UTC 24 |
4056370072 ps |
| T709 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/default/71.chip_sw_alert_handler_lpg_sleep_mode_alerts.2953970526 |
|
|
Aug 28 04:46:49 AM UTC 24 |
Aug 28 04:53:28 AM UTC 24 |
4493432264 ps |
| T1314 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/default/63.chip_sw_all_escalation_resets.3319653298 |
|
|
Aug 28 04:43:33 AM UTC 24 |
Aug 28 04:53:32 AM UTC 24 |
6279214344 ps |
| T1315 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/default/73.chip_sw_alert_handler_lpg_sleep_mode_alerts.3871638909 |
|
|
Aug 28 04:48:09 AM UTC 24 |
Aug 28 04:53:50 AM UTC 24 |
4056909312 ps |
| T691 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/default/60.chip_sw_all_escalation_resets.4277578556 |
|
|
Aug 28 04:43:34 AM UTC 24 |
Aug 28 04:53:51 AM UTC 24 |
5615402870 ps |
| T1316 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/default/14.chip_sw_uart_rand_baudrate.1406859848 |
|
|
Aug 28 04:10:21 AM UTC 24 |
Aug 28 04:53:59 AM UTC 24 |
12739828952 ps |
| T1317 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/default/66.chip_sw_all_escalation_resets.4192867959 |
|
|
Aug 28 04:43:52 AM UTC 24 |
Aug 28 04:54:03 AM UTC 24 |
5193120856 ps |
| T764 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/default/64.chip_sw_all_escalation_resets.4128227260 |
|
|
Aug 28 04:43:54 AM UTC 24 |
Aug 28 04:54:22 AM UTC 24 |
5896439248 ps |
| T678 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/default/71.chip_sw_all_escalation_resets.1969525058 |
|
|
Aug 28 04:46:49 AM UTC 24 |
Aug 28 04:54:27 AM UTC 24 |
4825308712 ps |
| T1318 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/default/74.chip_sw_alert_handler_lpg_sleep_mode_alerts.3098562850 |
|
|
Aug 28 04:49:50 AM UTC 24 |
Aug 28 04:54:41 AM UTC 24 |
2975001952 ps |
| T706 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/default/75.chip_sw_alert_handler_lpg_sleep_mode_alerts.1284321988 |
|
|
Aug 28 04:49:32 AM UTC 24 |
Aug 28 04:54:42 AM UTC 24 |
3291772154 ps |
| T690 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/default/56.chip_sw_all_escalation_resets.1538279926 |
|
|
Aug 28 04:43:55 AM UTC 24 |
Aug 28 04:54:57 AM UTC 24 |
6015978192 ps |
| T732 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/default/70.chip_sw_all_escalation_resets.4107617177 |
|
|
Aug 28 04:46:43 AM UTC 24 |
Aug 28 04:55:05 AM UTC 24 |
4862184456 ps |
| T679 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/default/76.chip_sw_alert_handler_lpg_sleep_mode_alerts.457239067 |
|
|
Aug 28 04:49:52 AM UTC 24 |
Aug 28 04:55:12 AM UTC 24 |
3886161044 ps |
| T284 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/default/69.chip_sw_all_escalation_resets.4141408797 |
|
|
Aug 28 04:45:55 AM UTC 24 |
Aug 28 04:55:23 AM UTC 24 |
4902311738 ps |
| T694 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/default/72.chip_sw_all_escalation_resets.1393163820 |
|
|
Aug 28 04:47:19 AM UTC 24 |
Aug 28 04:55:30 AM UTC 24 |
4924132000 ps |
| T734 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/default/68.chip_sw_all_escalation_resets.938746218 |
|
|
Aug 28 04:45:13 AM UTC 24 |
Aug 28 04:55:41 AM UTC 24 |
5212192888 ps |
| T1319 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/default/7.chip_sw_csrng_edn_concurrency.2772211535 |
|
|
Aug 28 03:56:04 AM UTC 24 |
Aug 28 04:55:59 AM UTC 24 |
14312229714 ps |
| T1320 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/default/76.chip_sw_all_escalation_resets.1692905648 |
|
|
Aug 28 04:49:36 AM UTC 24 |
Aug 28 04:56:48 AM UTC 24 |
4536128910 ps |
| T695 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/default/77.chip_sw_alert_handler_lpg_sleep_mode_alerts.1205688335 |
|
|
Aug 28 04:51:29 AM UTC 24 |
Aug 28 04:56:54 AM UTC 24 |
3933865898 ps |
| T701 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/default/74.chip_sw_all_escalation_resets.2783736375 |
|
|
Aug 28 04:49:29 AM UTC 24 |
Aug 28 04:56:56 AM UTC 24 |
4843664688 ps |
| T716 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/default/73.chip_sw_all_escalation_resets.2325014558 |
|
|
Aug 28 04:47:50 AM UTC 24 |
Aug 28 04:57:42 AM UTC 24 |
4873623704 ps |
| T1321 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/default/75.chip_sw_all_escalation_resets.3455574734 |
|
|
Aug 28 04:49:35 AM UTC 24 |
Aug 28 04:57:44 AM UTC 24 |
5869801200 ps |
| T341 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/default/87.chip_sw_alert_handler_lpg_sleep_mode_alerts.1736707756 |
|
|
Aug 28 04:53:39 AM UTC 24 |
Aug 28 04:58:18 AM UTC 24 |
3602733812 ps |
| T717 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/default/78.chip_sw_alert_handler_lpg_sleep_mode_alerts.24789072 |
|
|
Aug 28 04:54:13 AM UTC 24 |
Aug 28 04:59:36 AM UTC 24 |
4302917012 ps |
| T739 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/default/80.chip_sw_all_escalation_resets.2048142801 |
|
|
Aug 28 04:52:40 AM UTC 24 |
Aug 28 04:59:40 AM UTC 24 |
4769000352 ps |
| T710 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/default/85.chip_sw_alert_handler_lpg_sleep_mode_alerts.3492816973 |
|
|
Aug 28 04:54:22 AM UTC 24 |
Aug 28 04:59:46 AM UTC 24 |
3813012680 ps |
| T736 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/default/83.chip_sw_alert_handler_lpg_sleep_mode_alerts.569954600 |
|
|
Aug 28 04:54:15 AM UTC 24 |
Aug 28 04:59:58 AM UTC 24 |
4091625962 ps |
| T675 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/default/86.chip_sw_alert_handler_lpg_sleep_mode_alerts.3405042879 |
|
|
Aug 28 04:55:05 AM UTC 24 |
Aug 28 05:00:03 AM UTC 24 |
3211179762 ps |
| T779 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/default/86.chip_sw_all_escalation_resets.2115590397 |
|
|
Aug 28 04:53:48 AM UTC 24 |
Aug 28 05:00:05 AM UTC 24 |
5803072448 ps |
| T776 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/default/84.chip_sw_alert_handler_lpg_sleep_mode_alerts.326655623 |
|
|
Aug 28 04:55:38 AM UTC 24 |
Aug 28 05:00:27 AM UTC 24 |
3691390628 ps |
| T718 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/default/81.chip_sw_alert_handler_lpg_sleep_mode_alerts.4147676340 |
|
|
Aug 28 04:55:03 AM UTC 24 |
Aug 28 05:00:36 AM UTC 24 |
4245708488 ps |
| T676 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/default/89.chip_sw_alert_handler_lpg_sleep_mode_alerts.376055040 |
|
|
Aug 28 04:55:51 AM UTC 24 |
Aug 28 05:00:43 AM UTC 24 |
3244910660 ps |
| T1322 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/default/88.chip_sw_alert_handler_lpg_sleep_mode_alerts.1635369161 |
|
|
Aug 28 04:55:09 AM UTC 24 |
Aug 28 05:00:48 AM UTC 24 |
4133044520 ps |
| T1323 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/default/84.chip_sw_all_escalation_resets.1715669252 |
|
|
Aug 28 04:53:16 AM UTC 24 |
Aug 28 05:01:28 AM UTC 24 |
5083520980 ps |
| T754 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/default/87.chip_sw_all_escalation_resets.2789298 |
|
|
Aug 28 04:55:19 AM UTC 24 |
Aug 28 05:01:28 AM UTC 24 |
4675987460 ps |
| T1324 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/default/77.chip_sw_all_escalation_resets.4127448175 |
|
|
Aug 28 04:52:38 AM UTC 24 |
Aug 28 05:01:30 AM UTC 24 |
5182924700 ps |
| T373 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_inject_scramble_seed.3780506721 |
|
|
Aug 28 12:44:13 AM UTC 24 |
Aug 28 05:01:44 AM UTC 24 |
65537779333 ps |
| T1325 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/default/82.chip_sw_alert_handler_lpg_sleep_mode_alerts.2407961720 |
|
|
Aug 28 04:55:02 AM UTC 24 |
Aug 28 05:01:48 AM UTC 24 |
4118677400 ps |
| T1326 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/default/80.chip_sw_alert_handler_lpg_sleep_mode_alerts.732772159 |
|
|
Aug 28 04:55:30 AM UTC 24 |
Aug 28 05:01:51 AM UTC 24 |
4144011840 ps |
| T1327 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/default/78.chip_sw_all_escalation_resets.1401566545 |
|
|
Aug 28 04:53:14 AM UTC 24 |
Aug 28 05:01:56 AM UTC 24 |
6416345482 ps |
| T741 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/default/79.chip_sw_alert_handler_lpg_sleep_mode_alerts.2603367093 |
|
|
Aug 28 04:55:50 AM UTC 24 |
Aug 28 05:02:00 AM UTC 24 |
3618182090 ps |
| T749 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/default/91.chip_sw_all_escalation_resets.446839683 |
|
|
Aug 28 04:55:16 AM UTC 24 |
Aug 28 05:02:07 AM UTC 24 |
5345912184 ps |
| T761 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/default/81.chip_sw_all_escalation_resets.975810517 |
|
|
Aug 28 04:55:30 AM UTC 24 |
Aug 28 05:02:09 AM UTC 24 |
4055404752 ps |
| T680 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/default/94.chip_sw_all_escalation_resets.2051595883 |
|
|
Aug 28 04:55:50 AM UTC 24 |
Aug 28 05:02:13 AM UTC 24 |
3983285194 ps |
| T750 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/default/79.chip_sw_all_escalation_resets.475363814 |
|
|
Aug 28 04:55:30 AM UTC 24 |
Aug 28 05:03:03 AM UTC 24 |
4026847848 ps |
| T712 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/default/99.chip_sw_all_escalation_resets.3812130420 |
|
|
Aug 28 04:55:40 AM UTC 24 |
Aug 28 05:03:12 AM UTC 24 |
4267808934 ps |
| T702 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/default/98.chip_sw_all_escalation_resets.643630427 |
|
|
Aug 28 04:55:28 AM UTC 24 |
Aug 28 05:03:28 AM UTC 24 |
5184308536 ps |
| T1328 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/default/89.chip_sw_all_escalation_resets.1534231812 |
|
|
Aug 28 04:55:52 AM UTC 24 |
Aug 28 05:03:30 AM UTC 24 |
5531621400 ps |
| T748 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/default/88.chip_sw_all_escalation_resets.1880200865 |
|
|
Aug 28 04:55:30 AM UTC 24 |
Aug 28 05:03:32 AM UTC 24 |
4499866146 ps |
| T1329 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/default/90.chip_sw_all_escalation_resets.2213861495 |
|
|
Aug 28 04:55:17 AM UTC 24 |
Aug 28 05:03:36 AM UTC 24 |
6423460168 ps |
| T771 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/default/92.chip_sw_all_escalation_resets.1793409768 |
|
|
Aug 28 04:55:46 AM UTC 24 |
Aug 28 05:03:47 AM UTC 24 |
4342308520 ps |
| T1330 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/default/83.chip_sw_all_escalation_resets.2770765703 |
|
|
Aug 28 04:55:02 AM UTC 24 |
Aug 28 05:03:49 AM UTC 24 |
4916229038 ps |
| T782 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/default/97.chip_sw_all_escalation_resets.3506909193 |
|
|
Aug 28 04:55:48 AM UTC 24 |
Aug 28 05:03:49 AM UTC 24 |
6377167244 ps |
| T1331 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/default/95.chip_sw_all_escalation_resets.1679279116 |
|
|
Aug 28 04:55:52 AM UTC 24 |
Aug 28 05:03:52 AM UTC 24 |
6491692920 ps |