| T2514 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/57.xbar_access_same_device_slow_rsp.3119116945 |
|
|
Aug 27 09:44:04 PM UTC 24 |
Aug 27 10:08:46 PM UTC 24 |
98384740801 ps |
| T2515 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/78.xbar_access_same_device.2157374227 |
|
|
Aug 27 10:07:48 PM UTC 24 |
Aug 27 10:08:49 PM UTC 24 |
1838417289 ps |
| T2516 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/78.xbar_stress_all_with_error.1645520578 |
|
|
Aug 27 10:08:04 PM UTC 24 |
Aug 27 10:08:52 PM UTC 24 |
486114910 ps |
| T2517 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/78.xbar_same_source.2714176147 |
|
|
Aug 27 10:07:48 PM UTC 24 |
Aug 27 10:08:55 PM UTC 24 |
1869005852 ps |
| T2518 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/78.xbar_stress_all.2267033280 |
|
|
Aug 27 10:08:01 PM UTC 24 |
Aug 27 10:09:12 PM UTC 24 |
810113904 ps |
| T2519 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/75.xbar_stress_all_with_rand_reset.1018235513 |
|
|
Aug 27 10:04:33 PM UTC 24 |
Aug 27 10:09:13 PM UTC 24 |
1087056132 ps |
| T2520 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/78.xbar_smoke_slow_rsp.3084267489 |
|
|
Aug 27 10:07:32 PM UTC 24 |
Aug 27 10:09:18 PM UTC 24 |
6528568374 ps |
| T2521 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/79.xbar_random_zero_delays.2548560280 |
|
|
Aug 27 10:08:37 PM UTC 24 |
Aug 27 10:09:19 PM UTC 24 |
544833313 ps |
| T2522 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/80.xbar_smoke_zero_delays.920312215 |
|
|
Aug 27 10:09:10 PM UTC 24 |
Aug 27 10:09:20 PM UTC 24 |
48628703 ps |
| T2523 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/80.xbar_smoke.4290804322 |
|
|
Aug 27 10:09:14 PM UTC 24 |
Aug 27 10:09:25 PM UTC 24 |
110481194 ps |
| T2524 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/79.xbar_error_random.2741636342 |
|
|
Aug 27 10:08:49 PM UTC 24 |
Aug 27 10:09:32 PM UTC 24 |
1274320212 ps |
| T2525 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/76.xbar_stress_all_with_reset_error.2322456699 |
|
|
Aug 27 10:05:40 PM UTC 24 |
Aug 27 10:09:32 PM UTC 24 |
1817571729 ps |
| T2526 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/72.xbar_stress_all_with_rand_reset.4039153456 |
|
|
Aug 27 10:01:35 PM UTC 24 |
Aug 27 10:09:35 PM UTC 24 |
3665450378 ps |
| T2527 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/79.xbar_error_and_unmapped_addr.1578239592 |
|
|
Aug 27 10:08:58 PM UTC 24 |
Aug 27 10:09:37 PM UTC 24 |
1049068210 ps |
| T2528 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/79.xbar_same_source.2913637455 |
|
|
Aug 27 10:08:47 PM UTC 24 |
Aug 27 10:09:39 PM UTC 24 |
1305290059 ps |
| T2529 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/79.xbar_smoke_large_delays.1919146716 |
|
|
Aug 27 10:08:29 PM UTC 24 |
Aug 27 10:09:41 PM UTC 24 |
6716191001 ps |
| T2530 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/74.xbar_access_same_device_slow_rsp.532003171 |
|
|
Aug 27 10:03:17 PM UTC 24 |
Aug 27 10:09:43 PM UTC 24 |
24896788445 ps |
| T2531 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/79.xbar_unmapped_addr.3672746934 |
|
|
Aug 27 10:08:56 PM UTC 24 |
Aug 27 10:09:45 PM UTC 24 |
1050755359 ps |
| T2532 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/79.xbar_smoke_slow_rsp.759512084 |
|
|
Aug 27 10:08:32 PM UTC 24 |
Aug 27 10:09:56 PM UTC 24 |
5928481682 ps |
| T2533 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/65.xbar_random_large_delays.518916855 |
|
|
Aug 27 09:52:22 PM UTC 24 |
Aug 27 10:09:58 PM UTC 24 |
110506927238 ps |
| T2534 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/79.xbar_stress_all_with_error.2254728729 |
|
|
Aug 27 10:09:08 PM UTC 24 |
Aug 27 10:09:59 PM UTC 24 |
1821104038 ps |
| T2535 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/80.xbar_random.3824931523 |
|
|
Aug 27 10:09:39 PM UTC 24 |
Aug 27 10:10:03 PM UTC 24 |
692764580 ps |
| T2536 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/79.xbar_random_large_delays.1135814750 |
|
|
Aug 27 10:08:38 PM UTC 24 |
Aug 27 10:10:03 PM UTC 24 |
6940158481 ps |
| T2537 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/76.xbar_stress_all.1631702062 |
|
|
Aug 27 10:05:37 PM UTC 24 |
Aug 27 10:10:06 PM UTC 24 |
6590180683 ps |
| T866 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/77.xbar_stress_all_with_reset_error.3046125589 |
|
|
Aug 27 10:07:16 PM UTC 24 |
Aug 27 10:10:06 PM UTC 24 |
547369604 ps |
| T2538 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/79.xbar_stress_all_with_reset_error.1578627217 |
|
|
Aug 27 10:09:09 PM UTC 24 |
Aug 27 10:10:11 PM UTC 24 |
104459077 ps |
| T2539 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/79.xbar_random.4172842149 |
|
|
Aug 27 10:08:34 PM UTC 24 |
Aug 27 10:10:14 PM UTC 24 |
2533856451 ps |
| T2540 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/79.xbar_access_same_device.3619534584 |
|
|
Aug 27 10:08:44 PM UTC 24 |
Aug 27 10:10:20 PM UTC 24 |
1922242338 ps |
| T2541 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/80.xbar_error_random.3875166033 |
|
|
Aug 27 10:10:01 PM UTC 24 |
Aug 27 10:10:20 PM UTC 24 |
619882699 ps |
| T2542 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/80.xbar_random_zero_delays.1084510152 |
|
|
Aug 27 10:09:41 PM UTC 24 |
Aug 27 10:10:28 PM UTC 24 |
544744859 ps |
| T2543 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/69.xbar_random_slow_rsp.838056451 |
|
|
Aug 27 09:57:47 PM UTC 24 |
Aug 27 10:10:29 PM UTC 24 |
47924242315 ps |
| T2544 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/80.xbar_unmapped_addr.2625444933 |
|
|
Aug 27 10:10:02 PM UTC 24 |
Aug 27 10:10:30 PM UTC 24 |
430665027 ps |
| T2545 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/80.xbar_error_and_unmapped_addr.917448708 |
|
|
Aug 27 10:10:02 PM UTC 24 |
Aug 27 10:10:31 PM UTC 24 |
499012132 ps |
| T2546 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/81.xbar_smoke_zero_delays.378805689 |
|
|
Aug 27 10:10:24 PM UTC 24 |
Aug 27 10:10:34 PM UTC 24 |
56202314 ps |
| T2547 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/81.xbar_smoke.1189866645 |
|
|
Aug 27 10:10:22 PM UTC 24 |
Aug 27 10:10:35 PM UTC 24 |
188648031 ps |
| T2548 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/76.xbar_random_slow_rsp.909562670 |
|
|
Aug 27 10:05:16 PM UTC 24 |
Aug 27 10:10:41 PM UTC 24 |
22364893126 ps |
| T2549 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/80.xbar_same_source.2461108833 |
|
|
Aug 27 10:09:58 PM UTC 24 |
Aug 27 10:10:50 PM UTC 24 |
1699253689 ps |
| T2550 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/81.xbar_access_same_device.1429367430 |
|
|
Aug 27 10:10:38 PM UTC 24 |
Aug 27 10:10:54 PM UTC 24 |
102235835 ps |
| T2551 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/80.xbar_smoke_large_delays.1154662326 |
|
|
Aug 27 10:09:35 PM UTC 24 |
Aug 27 10:11:00 PM UTC 24 |
7977605442 ps |
| T2552 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/81.xbar_random.774164054 |
|
|
Aug 27 10:10:30 PM UTC 24 |
Aug 27 10:11:05 PM UTC 24 |
1089221748 ps |
| T2553 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/80.xbar_smoke_slow_rsp.314463306 |
|
|
Aug 27 10:09:37 PM UTC 24 |
Aug 27 10:11:11 PM UTC 24 |
6256696375 ps |
| T2554 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/80.xbar_stress_all_with_error.1680418939 |
|
|
Aug 27 10:10:17 PM UTC 24 |
Aug 27 10:11:16 PM UTC 24 |
1565800604 ps |
| T2555 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/74.xbar_stress_all_with_rand_reset.2213280912 |
|
|
Aug 27 10:03:24 PM UTC 24 |
Aug 27 10:11:16 PM UTC 24 |
4562006408 ps |
| T2556 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/81.xbar_same_source.2806062158 |
|
|
Aug 27 10:10:53 PM UTC 24 |
Aug 27 10:11:17 PM UTC 24 |
522791190 ps |
| T2557 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/81.xbar_random_zero_delays.3034048864 |
|
|
Aug 27 10:10:35 PM UTC 24 |
Aug 27 10:11:20 PM UTC 24 |
363456997 ps |
| T2558 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/81.xbar_error_random.182498180 |
|
|
Aug 27 10:10:52 PM UTC 24 |
Aug 27 10:11:23 PM UTC 24 |
336114476 ps |
| T2559 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/81.xbar_error_and_unmapped_addr.2032316085 |
|
|
Aug 27 10:10:55 PM UTC 24 |
Aug 27 10:11:30 PM UTC 24 |
622526059 ps |
| T2560 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/80.xbar_access_same_device.2714129308 |
|
|
Aug 27 10:09:54 PM UTC 24 |
Aug 27 10:11:33 PM UTC 24 |
2237006092 ps |
| T2561 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/82.xbar_smoke_zero_delays.2752843582 |
|
|
Aug 27 10:11:25 PM UTC 24 |
Aug 27 10:11:35 PM UTC 24 |
41194258 ps |
| T2562 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/81.xbar_smoke_slow_rsp.486632831 |
|
|
Aug 27 10:10:29 PM UTC 24 |
Aug 27 10:11:36 PM UTC 24 |
5223543736 ps |
| T2563 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/82.xbar_smoke.230593935 |
|
|
Aug 27 10:11:23 PM UTC 24 |
Aug 27 10:11:36 PM UTC 24 |
212852070 ps |
| T2564 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/77.xbar_stress_all_with_error.1371504103 |
|
|
Aug 27 10:07:07 PM UTC 24 |
Aug 27 10:11:41 PM UTC 24 |
3880433486 ps |
| T2565 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/81.xbar_unmapped_addr.1146782110 |
|
|
Aug 27 10:10:53 PM UTC 24 |
Aug 27 10:11:46 PM UTC 24 |
1321264017 ps |
| T2566 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/70.xbar_access_same_device_slow_rsp.3030587321 |
|
|
Aug 27 09:59:13 PM UTC 24 |
Aug 27 10:11:47 PM UTC 24 |
43170982788 ps |
| T2567 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/79.xbar_access_same_device_slow_rsp.2018298740 |
|
|
Aug 27 10:08:43 PM UTC 24 |
Aug 27 10:11:55 PM UTC 24 |
12967416793 ps |
| T2568 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/82.xbar_random_zero_delays.2829011816 |
|
|
Aug 27 10:11:38 PM UTC 24 |
Aug 27 10:11:55 PM UTC 24 |
170999655 ps |
| T2569 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/75.xbar_random_large_delays.2747122611 |
|
|
Aug 27 10:03:55 PM UTC 24 |
Aug 27 10:11:55 PM UTC 24 |
42459733028 ps |
| T2570 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/78.xbar_random_slow_rsp.2928225897 |
|
|
Aug 27 10:07:46 PM UTC 24 |
Aug 27 10:11:59 PM UTC 24 |
13248189106 ps |
| T2571 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/67.xbar_random_slow_rsp.3863196018 |
|
|
Aug 27 09:54:43 PM UTC 24 |
Aug 27 10:11:59 PM UTC 24 |
71476399382 ps |
| T2572 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/75.xbar_stress_all.1252799464 |
|
|
Aug 27 10:04:31 PM UTC 24 |
Aug 27 10:12:02 PM UTC 24 |
13032642138 ps |
| T2573 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/82.xbar_error_random.2035182810 |
|
|
Aug 27 10:11:55 PM UTC 24 |
Aug 27 10:12:07 PM UTC 24 |
114898961 ps |
| T2574 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/82.xbar_unmapped_addr.4261144904 |
|
|
Aug 27 10:11:57 PM UTC 24 |
Aug 27 10:12:11 PM UTC 24 |
154370224 ps |
| T2575 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/81.xbar_smoke_large_delays.3143010277 |
|
|
Aug 27 10:10:26 PM UTC 24 |
Aug 27 10:12:13 PM UTC 24 |
7743807599 ps |
| T2576 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/82.xbar_error_and_unmapped_addr.2840985373 |
|
|
Aug 27 10:12:01 PM UTC 24 |
Aug 27 10:12:19 PM UTC 24 |
268927673 ps |
| T2577 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/78.xbar_stress_all_with_reset_error.2181892257 |
|
|
Aug 27 10:08:09 PM UTC 24 |
Aug 27 10:12:20 PM UTC 24 |
696651943 ps |
| T2578 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/82.xbar_same_source.2736385713 |
|
|
Aug 27 10:11:58 PM UTC 24 |
Aug 27 10:12:23 PM UTC 24 |
243800898 ps |
| T2579 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/83.xbar_smoke_zero_delays.3068109971 |
|
|
Aug 27 10:12:18 PM UTC 24 |
Aug 27 10:12:25 PM UTC 24 |
39928863 ps |
| T2580 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/83.xbar_smoke.755264865 |
|
|
Aug 27 10:12:15 PM UTC 24 |
Aug 27 10:12:27 PM UTC 24 |
181458136 ps |
| T2581 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/82.xbar_random.1444933212 |
|
|
Aug 27 10:11:38 PM UTC 24 |
Aug 27 10:12:28 PM UTC 24 |
532444570 ps |
| T2582 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/81.xbar_stress_all_with_reset_error.2884203876 |
|
|
Aug 27 10:11:17 PM UTC 24 |
Aug 27 10:12:50 PM UTC 24 |
826285866 ps |
| T2583 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/74.xbar_random_slow_rsp.1623978590 |
|
|
Aug 27 10:03:13 PM UTC 24 |
Aug 27 10:12:54 PM UTC 24 |
38456717949 ps |
| T2584 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/83.xbar_same_source.1077351947 |
|
|
Aug 27 10:12:45 PM UTC 24 |
Aug 27 10:12:57 PM UTC 24 |
63663338 ps |
| T2585 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/83.xbar_random_zero_delays.3505991096 |
|
|
Aug 27 10:12:33 PM UTC 24 |
Aug 27 10:13:00 PM UTC 24 |
207055710 ps |
| T2586 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/80.xbar_stress_all.387251034 |
|
|
Aug 27 10:10:05 PM UTC 24 |
Aug 27 10:13:00 PM UTC 24 |
2321133599 ps |
| T2587 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/82.xbar_access_same_device.716053705 |
|
|
Aug 27 10:11:52 PM UTC 24 |
Aug 27 10:13:07 PM UTC 24 |
1299531606 ps |
| T2588 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/78.xbar_stress_all_with_rand_reset.208935972 |
|
|
Aug 27 10:08:05 PM UTC 24 |
Aug 27 10:13:09 PM UTC 24 |
6253472294 ps |
| T2589 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/83.xbar_unmapped_addr.1363409706 |
|
|
Aug 27 10:12:50 PM UTC 24 |
Aug 27 10:13:14 PM UTC 24 |
426732877 ps |
| T2590 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/82.xbar_smoke_slow_rsp.3504949821 |
|
|
Aug 27 10:11:38 PM UTC 24 |
Aug 27 10:13:17 PM UTC 24 |
5626762051 ps |
| T2591 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/76.xbar_random_large_delays.1472554281 |
|
|
Aug 27 10:05:12 PM UTC 24 |
Aug 27 10:13:19 PM UTC 24 |
41692128414 ps |
| T2592 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/83.xbar_error_random.1402311145 |
|
|
Aug 27 10:12:48 PM UTC 24 |
Aug 27 10:13:23 PM UTC 24 |
775290614 ps |
| T2593 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/83.xbar_random.444075869 |
|
|
Aug 27 10:12:29 PM UTC 24 |
Aug 27 10:13:26 PM UTC 24 |
2089143112 ps |
| T2594 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/84.xbar_smoke.3393047395 |
|
|
Aug 27 10:13:30 PM UTC 24 |
Aug 27 10:13:39 PM UTC 24 |
45833725 ps |
| T2595 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/82.xbar_stress_all.3479966527 |
|
|
Aug 27 10:12:08 PM UTC 24 |
Aug 27 10:13:40 PM UTC 24 |
2419733749 ps |
| T2596 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/82.xbar_smoke_large_delays.1092541009 |
|
|
Aug 27 10:11:34 PM UTC 24 |
Aug 27 10:13:40 PM UTC 24 |
9221082238 ps |
| T2597 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/84.xbar_smoke_zero_delays.1821789185 |
|
|
Aug 27 10:13:32 PM UTC 24 |
Aug 27 10:13:41 PM UTC 24 |
55129115 ps |
| T2598 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/84.xbar_random_zero_delays.2603024990 |
|
|
Aug 27 10:13:45 PM UTC 24 |
Aug 27 10:13:53 PM UTC 24 |
41229167 ps |
| T2599 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/71.xbar_access_same_device_slow_rsp.3669360543 |
|
|
Aug 27 10:00:19 PM UTC 24 |
Aug 27 10:13:53 PM UTC 24 |
54181537052 ps |
| T2600 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/80.xbar_random_large_delays.4015818746 |
|
|
Aug 27 10:09:42 PM UTC 24 |
Aug 27 10:13:59 PM UTC 24 |
30160518284 ps |
| T2601 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/83.xbar_smoke_slow_rsp.3824703965 |
|
|
Aug 27 10:12:23 PM UTC 24 |
Aug 27 10:14:08 PM UTC 24 |
5734655162 ps |
| T2602 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/71.xbar_random_large_delays.2168000071 |
|
|
Aug 27 10:00:10 PM UTC 24 |
Aug 27 10:14:08 PM UTC 24 |
94553111005 ps |
| T2603 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/83.xbar_error_and_unmapped_addr.4267931643 |
|
|
Aug 27 10:13:12 PM UTC 24 |
Aug 27 10:14:10 PM UTC 24 |
1234598970 ps |
| T2604 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/76.xbar_stress_all_with_rand_reset.2864692423 |
|
|
Aug 27 10:05:40 PM UTC 24 |
Aug 27 10:14:13 PM UTC 24 |
3708811884 ps |
| T2605 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/83.xbar_smoke_large_delays.2766907262 |
|
|
Aug 27 10:12:22 PM UTC 24 |
Aug 27 10:14:13 PM UTC 24 |
9903717251 ps |
| T2606 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/82.xbar_stress_all_with_error.2516643018 |
|
|
Aug 27 10:12:18 PM UTC 24 |
Aug 27 10:14:17 PM UTC 24 |
1370686519 ps |
| T2607 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/82.xbar_stress_all_with_rand_reset.269168012 |
|
|
Aug 27 10:12:07 PM UTC 24 |
Aug 27 10:14:20 PM UTC 24 |
852335798 ps |
| T2608 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/55.xbar_access_same_device_slow_rsp.865967424 |
|
|
Aug 27 09:41:50 PM UTC 24 |
Aug 27 10:14:21 PM UTC 24 |
137754785412 ps |
| T2609 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/70.xbar_stress_all_with_rand_reset.93656203 |
|
|
Aug 27 09:59:31 PM UTC 24 |
Aug 27 10:14:25 PM UTC 24 |
8848442517 ps |
| T2610 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/84.xbar_unmapped_addr.4021299090 |
|
|
Aug 27 10:14:16 PM UTC 24 |
Aug 27 10:14:27 PM UTC 24 |
78347516 ps |
| T2611 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/84.xbar_random.538529361 |
|
|
Aug 27 10:13:40 PM UTC 24 |
Aug 27 10:14:30 PM UTC 24 |
1436426514 ps |
| T2612 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/84.xbar_error_and_unmapped_addr.3815103446 |
|
|
Aug 27 10:14:18 PM UTC 24 |
Aug 27 10:14:38 PM UTC 24 |
144183803 ps |
| T2613 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/85.xbar_smoke.3232717907 |
|
|
Aug 27 10:14:36 PM UTC 24 |
Aug 27 10:14:47 PM UTC 24 |
177344856 ps |
| T2614 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/85.xbar_smoke_zero_delays.1334402049 |
|
|
Aug 27 10:14:40 PM UTC 24 |
Aug 27 10:14:51 PM UTC 24 |
50224979 ps |
| T2615 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/83.xbar_access_same_device.1956260499 |
|
|
Aug 27 10:12:40 PM UTC 24 |
Aug 27 10:14:55 PM UTC 24 |
3324686021 ps |
| T2616 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/84.xbar_error_random.1331259659 |
|
|
Aug 27 10:14:14 PM UTC 24 |
Aug 27 10:14:56 PM UTC 24 |
976357019 ps |
| T2617 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/85.xbar_random_zero_delays.3066771608 |
|
|
Aug 27 10:14:48 PM UTC 24 |
Aug 27 10:15:01 PM UTC 24 |
64692060 ps |
| T2618 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/75.xbar_access_same_device_slow_rsp.3118012620 |
|
|
Aug 27 10:04:14 PM UTC 24 |
Aug 27 10:15:03 PM UTC 24 |
42382269077 ps |
| T2619 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/85.xbar_random.2381034681 |
|
|
Aug 27 10:14:49 PM UTC 24 |
Aug 27 10:15:05 PM UTC 24 |
104688958 ps |
| T2620 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/71.xbar_random_slow_rsp.2357447783 |
|
|
Aug 27 10:00:11 PM UTC 24 |
Aug 27 10:15:05 PM UTC 24 |
63657751534 ps |
| T2621 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/84.xbar_same_source.2550487626 |
|
|
Aug 27 10:14:04 PM UTC 24 |
Aug 27 10:15:08 PM UTC 24 |
1694750021 ps |
| T2622 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/83.xbar_stress_all_with_rand_reset.2547677579 |
|
|
Aug 27 10:13:17 PM UTC 24 |
Aug 27 10:15:12 PM UTC 24 |
434537682 ps |
| T2623 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/67.xbar_access_same_device_slow_rsp.843653379 |
|
|
Aug 27 09:54:50 PM UTC 24 |
Aug 27 10:15:31 PM UTC 24 |
78720829664 ps |
| T2624 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/85.xbar_same_source.441698317 |
|
|
Aug 27 10:15:17 PM UTC 24 |
Aug 27 10:15:33 PM UTC 24 |
247628587 ps |
| T2625 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/83.xbar_stress_all_with_error.3614163478 |
|
|
Aug 27 10:13:22 PM UTC 24 |
Aug 27 10:15:41 PM UTC 24 |
4718530446 ps |
| T2626 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/85.xbar_stress_all.1403935318 |
|
|
Aug 27 10:15:28 PM UTC 24 |
Aug 27 10:15:44 PM UTC 24 |
103497442 ps |
| T2627 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/85.xbar_access_same_device.3569932295 |
|
|
Aug 27 10:15:10 PM UTC 24 |
Aug 27 10:15:45 PM UTC 24 |
334759440 ps |
| T858 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/80.xbar_stress_all_with_reset_error.2851260986 |
|
|
Aug 27 10:10:20 PM UTC 24 |
Aug 27 10:15:46 PM UTC 24 |
2446297455 ps |
| T2628 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/84.xbar_smoke_large_delays.2542652508 |
|
|
Aug 27 10:13:36 PM UTC 24 |
Aug 27 10:15:46 PM UTC 24 |
10477644143 ps |
| T2629 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/84.xbar_access_same_device.234117854 |
|
|
Aug 27 10:14:03 PM UTC 24 |
Aug 27 10:15:50 PM UTC 24 |
2873498166 ps |
| T2630 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/85.xbar_smoke_slow_rsp.881084022 |
|
|
Aug 27 10:14:40 PM UTC 24 |
Aug 27 10:15:52 PM UTC 24 |
3980883628 ps |
| T2631 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/84.xbar_smoke_slow_rsp.762366823 |
|
|
Aug 27 10:13:40 PM UTC 24 |
Aug 27 10:15:52 PM UTC 24 |
6986643414 ps |
| T2632 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/75.xbar_random_slow_rsp.3058361657 |
|
|
Aug 27 10:04:02 PM UTC 24 |
Aug 27 10:15:53 PM UTC 24 |
52255167278 ps |
| T2633 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/86.xbar_smoke_zero_delays.2611819036 |
|
|
Aug 27 10:15:55 PM UTC 24 |
Aug 27 10:16:03 PM UTC 24 |
42424079 ps |
| T2634 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/85.xbar_error_and_unmapped_addr.3283839824 |
|
|
Aug 27 10:15:26 PM UTC 24 |
Aug 27 10:16:05 PM UTC 24 |
885805850 ps |
| T2635 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/86.xbar_smoke.1715551166 |
|
|
Aug 27 10:15:51 PM UTC 24 |
Aug 27 10:16:05 PM UTC 24 |
197435203 ps |
| T2636 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/85.xbar_smoke_large_delays.1161585957 |
|
|
Aug 27 10:14:41 PM UTC 24 |
Aug 27 10:16:06 PM UTC 24 |
9120225485 ps |
| T2637 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/85.xbar_unmapped_addr.528893713 |
|
|
Aug 27 10:15:22 PM UTC 24 |
Aug 27 10:16:13 PM UTC 24 |
1001040923 ps |
| T2638 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/85.xbar_error_random.3475048737 |
|
|
Aug 27 10:15:17 PM UTC 24 |
Aug 27 10:16:16 PM UTC 24 |
1732373205 ps |
| T2639 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/86.xbar_same_source.1245643503 |
|
|
Aug 27 10:16:13 PM UTC 24 |
Aug 27 10:16:39 PM UTC 24 |
287192297 ps |
| T2640 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/86.xbar_unmapped_addr.2962827096 |
|
|
Aug 27 10:16:24 PM UTC 24 |
Aug 27 10:16:41 PM UTC 24 |
211933508 ps |
| T2641 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/85.xbar_stress_all_with_rand_reset.2450120164 |
|
|
Aug 27 10:15:28 PM UTC 24 |
Aug 27 10:16:41 PM UTC 24 |
197672880 ps |
| T2642 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/86.xbar_random_zero_delays.3638893081 |
|
|
Aug 27 10:16:07 PM UTC 24 |
Aug 27 10:16:43 PM UTC 24 |
415957268 ps |
| T2643 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/80.xbar_stress_all_with_rand_reset.1379323117 |
|
|
Aug 27 10:10:07 PM UTC 24 |
Aug 27 10:16:49 PM UTC 24 |
3927722485 ps |
| T2644 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/86.xbar_error_and_unmapped_addr.3454553067 |
|
|
Aug 27 10:16:27 PM UTC 24 |
Aug 27 10:16:50 PM UTC 24 |
187991489 ps |
| T2645 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/86.xbar_error_random.1292353857 |
|
|
Aug 27 10:16:23 PM UTC 24 |
Aug 27 10:16:53 PM UTC 24 |
327466512 ps |
| T2646 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/86.xbar_random.246213789 |
|
|
Aug 27 10:16:06 PM UTC 24 |
Aug 27 10:17:03 PM UTC 24 |
1817946970 ps |
| T2647 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/86.xbar_smoke_large_delays.1712334883 |
|
|
Aug 27 10:16:00 PM UTC 24 |
Aug 27 10:17:08 PM UTC 24 |
4717096416 ps |
| T2648 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/79.xbar_stress_all_with_rand_reset.1205748388 |
|
|
Aug 27 10:09:03 PM UTC 24 |
Aug 27 10:17:09 PM UTC 24 |
2577623567 ps |
| T2649 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/87.xbar_smoke_zero_delays.2031672212 |
|
|
Aug 27 10:17:03 PM UTC 24 |
Aug 27 10:17:10 PM UTC 24 |
46432423 ps |
| T2650 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/87.xbar_smoke.3333272890 |
|
|
Aug 27 10:17:03 PM UTC 24 |
Aug 27 10:17:13 PM UTC 24 |
164626281 ps |
| T2651 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/81.xbar_stress_all_with_error.1719362808 |
|
|
Aug 27 10:11:10 PM UTC 24 |
Aug 27 10:17:17 PM UTC 24 |
8405877718 ps |
| T2652 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/87.xbar_random.1147453940 |
|
|
Aug 27 10:17:10 PM UTC 24 |
Aug 27 10:17:19 PM UTC 24 |
153205615 ps |
| T2653 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/85.xbar_random_slow_rsp.2848438404 |
|
|
Aug 27 10:14:58 PM UTC 24 |
Aug 27 10:17:23 PM UTC 24 |
10941193003 ps |
| T2654 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/81.xbar_stress_all_with_rand_reset.1287935347 |
|
|
Aug 27 10:11:02 PM UTC 24 |
Aug 27 10:17:23 PM UTC 24 |
6733176496 ps |
| T2655 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/83.xbar_random_slow_rsp.4001217393 |
|
|
Aug 27 10:12:41 PM UTC 24 |
Aug 27 10:17:31 PM UTC 24 |
18619937925 ps |
| T2656 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/73.xbar_random_slow_rsp.3705475027 |
|
|
Aug 27 10:02:05 PM UTC 24 |
Aug 27 10:17:34 PM UTC 24 |
65270500782 ps |
| T2657 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/85.xbar_random_large_delays.2515771952 |
|
|
Aug 27 10:14:48 PM UTC 24 |
Aug 27 10:17:37 PM UTC 24 |
17499329801 ps |
| T2658 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/87.xbar_random_zero_delays.2573771444 |
|
|
Aug 27 10:17:14 PM UTC 24 |
Aug 27 10:17:38 PM UTC 24 |
188060066 ps |
| T2659 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/79.xbar_stress_all.1610245285 |
|
|
Aug 27 10:08:59 PM UTC 24 |
Aug 27 10:17:41 PM UTC 24 |
15776278030 ps |
| T2660 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/86.xbar_access_same_device.2348684782 |
|
|
Aug 27 10:16:12 PM UTC 24 |
Aug 27 10:17:45 PM UTC 24 |
897583368 ps |
| T2661 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/77.xbar_random_slow_rsp.4010253736 |
|
|
Aug 27 10:06:24 PM UTC 24 |
Aug 27 10:17:52 PM UTC 24 |
45389439152 ps |
| T2662 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/86.xbar_stress_all_with_reset_error.433445629 |
|
|
Aug 27 10:17:03 PM UTC 24 |
Aug 27 10:17:57 PM UTC 24 |
121434514 ps |
| T2663 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/86.xbar_smoke_slow_rsp.2564205287 |
|
|
Aug 27 10:16:05 PM UTC 24 |
Aug 27 10:18:01 PM UTC 24 |
5793834801 ps |
| T2664 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/87.xbar_error_and_unmapped_addr.3249469700 |
|
|
Aug 27 10:17:44 PM UTC 24 |
Aug 27 10:18:08 PM UTC 24 |
157252261 ps |
| T2665 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/88.xbar_smoke.4149704018 |
|
|
Aug 27 10:17:58 PM UTC 24 |
Aug 27 10:18:08 PM UTC 24 |
57337063 ps |
| T2666 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/87.xbar_error_random.3354693466 |
|
|
Aug 27 10:17:39 PM UTC 24 |
Aug 27 10:18:10 PM UTC 24 |
936385497 ps |
| T2667 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/84.xbar_random_slow_rsp.2509102992 |
|
|
Aug 27 10:13:57 PM UTC 24 |
Aug 27 10:18:12 PM UTC 24 |
16304499822 ps |
| T2668 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/88.xbar_smoke_zero_delays.1525812820 |
|
|
Aug 27 10:18:03 PM UTC 24 |
Aug 27 10:18:12 PM UTC 24 |
42194634 ps |
| T2669 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/87.xbar_same_source.2684917808 |
|
|
Aug 27 10:17:30 PM UTC 24 |
Aug 27 10:18:19 PM UTC 24 |
1579765651 ps |
| T2670 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/73.xbar_random_large_delays.812408450 |
|
|
Aug 27 10:02:06 PM UTC 24 |
Aug 27 10:18:31 PM UTC 24 |
91265914480 ps |
| T2671 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/87.xbar_unmapped_addr.1603941149 |
|
|
Aug 27 10:17:42 PM UTC 24 |
Aug 27 10:18:37 PM UTC 24 |
1045713156 ps |
| T2672 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/87.xbar_smoke_slow_rsp.3971362708 |
|
|
Aug 27 10:17:11 PM UTC 24 |
Aug 27 10:18:33 PM UTC 24 |
4975143073 ps |
| T2673 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/86.xbar_access_same_device_slow_rsp.1367310814 |
|
|
Aug 27 10:16:12 PM UTC 24 |
Aug 27 10:18:42 PM UTC 24 |
10433148446 ps |
| T2674 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/88.xbar_random.717053579 |
|
|
Aug 27 10:18:20 PM UTC 24 |
Aug 27 10:18:44 PM UTC 24 |
411856082 ps |
| T2675 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/87.xbar_smoke_large_delays.1342569466 |
|
|
Aug 27 10:17:02 PM UTC 24 |
Aug 27 10:18:46 PM UTC 24 |
9855723556 ps |
| T2676 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/82.xbar_random_slow_rsp.2960340269 |
|
|
Aug 27 10:11:45 PM UTC 24 |
Aug 27 10:18:49 PM UTC 24 |
30505309201 ps |
| T2677 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/80.xbar_random_slow_rsp.3473932117 |
|
|
Aug 27 10:09:45 PM UTC 24 |
Aug 27 10:18:50 PM UTC 24 |
33548920335 ps |
| T2678 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/85.xbar_stress_all_with_error.4109523317 |
|
|
Aug 27 10:15:28 PM UTC 24 |
Aug 27 10:18:53 PM UTC 24 |
5059203857 ps |
| T2679 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/84.xbar_stress_all_with_reset_error.1238746956 |
|
|
Aug 27 10:14:33 PM UTC 24 |
Aug 27 10:18:53 PM UTC 24 |
6084438482 ps |
| T2680 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/88.xbar_error_random.4177067718 |
|
|
Aug 27 10:18:41 PM UTC 24 |
Aug 27 10:18:53 PM UTC 24 |
146561399 ps |
| T2681 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/85.xbar_access_same_device_slow_rsp.530913320 |
|
|
Aug 27 10:15:14 PM UTC 24 |
Aug 27 10:18:55 PM UTC 24 |
14826072790 ps |
| T2682 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/82.xbar_access_same_device_slow_rsp.2645889006 |
|
|
Aug 27 10:11:55 PM UTC 24 |
Aug 27 10:18:59 PM UTC 24 |
31102220055 ps |
| T2683 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/88.xbar_access_same_device.3620457145 |
|
|
Aug 27 10:18:32 PM UTC 24 |
Aug 27 10:19:03 PM UTC 24 |
370583961 ps |
| T2684 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/87.xbar_stress_all_with_rand_reset.2389567107 |
|
|
Aug 27 10:17:49 PM UTC 24 |
Aug 27 10:19:04 PM UTC 24 |
240099921 ps |
| T2685 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/83.xbar_stress_all.1780577003 |
|
|
Aug 27 10:13:16 PM UTC 24 |
Aug 27 10:19:09 PM UTC 24 |
4394971489 ps |
| T2686 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/88.xbar_random_zero_delays.2744194083 |
|
|
Aug 27 10:18:23 PM UTC 24 |
Aug 27 10:19:09 PM UTC 24 |
410415504 ps |
| T2687 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/87.xbar_access_same_device.1325435867 |
|
|
Aug 27 10:17:28 PM UTC 24 |
Aug 27 10:19:16 PM UTC 24 |
1897442353 ps |
| T2688 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/89.xbar_smoke_zero_delays.1903067981 |
|
|
Aug 27 10:19:09 PM UTC 24 |
Aug 27 10:19:18 PM UTC 24 |
48716236 ps |
| T2689 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/88.xbar_error_and_unmapped_addr.4107333698 |
|
|
Aug 27 10:18:53 PM UTC 24 |
Aug 27 10:19:23 PM UTC 24 |
749948462 ps |
| T2690 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/89.xbar_smoke.865473699 |
|
|
Aug 27 10:19:10 PM UTC 24 |
Aug 27 10:19:25 PM UTC 24 |
224304572 ps |
| T2691 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/89.xbar_random_zero_delays.111540455 |
|
|
Aug 27 10:19:16 PM UTC 24 |
Aug 27 10:19:31 PM UTC 24 |
149100031 ps |
| T2692 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/88.xbar_same_source.2093977632 |
|
|
Aug 27 10:18:35 PM UTC 24 |
Aug 27 10:19:46 PM UTC 24 |
2625577618 ps |
| T2693 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/86.xbar_random_slow_rsp.220663081 |
|
|
Aug 27 10:16:10 PM UTC 24 |
Aug 27 10:20:03 PM UTC 24 |
15956752117 ps |
| T2694 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/88.xbar_smoke_large_delays.272415090 |
|
|
Aug 27 10:18:08 PM UTC 24 |
Aug 27 10:20:03 PM UTC 24 |
7246643120 ps |
| T2695 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/88.xbar_unmapped_addr.2655582388 |
|
|
Aug 27 10:18:53 PM UTC 24 |
Aug 27 10:20:04 PM UTC 24 |
1478024884 ps |
| T2696 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/89.xbar_unmapped_addr.2497407699 |
|
|
Aug 27 10:19:38 PM UTC 24 |
Aug 27 10:20:05 PM UTC 24 |
407644696 ps |
| T2697 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/88.xbar_smoke_slow_rsp.3554197691 |
|
|
Aug 27 10:18:14 PM UTC 24 |
Aug 27 10:20:10 PM UTC 24 |
5469895279 ps |
| T2698 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/86.xbar_stress_all_with_rand_reset.1516882567 |
|
|
Aug 27 10:16:32 PM UTC 24 |
Aug 27 10:20:23 PM UTC 24 |
1249506220 ps |
| T2699 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/89.xbar_error_and_unmapped_addr.2868741513 |
|
|
Aug 27 10:19:46 PM UTC 24 |
Aug 27 10:20:26 PM UTC 24 |
342207309 ps |
| T2700 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/82.xbar_stress_all_with_reset_error.2281241064 |
|
|
Aug 27 10:12:17 PM UTC 24 |
Aug 27 10:20:27 PM UTC 24 |
11229376132 ps |
| T2701 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/84.xbar_stress_all.2177338603 |
|
|
Aug 27 10:14:30 PM UTC 24 |
Aug 27 10:20:30 PM UTC 24 |
8789996655 ps |
| T2702 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/83.xbar_stress_all_with_reset_error.692809153 |
|
|
Aug 27 10:13:19 PM UTC 24 |
Aug 27 10:20:32 PM UTC 24 |
7040788084 ps |
| T2703 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/89.xbar_smoke_slow_rsp.3905223658 |
|
|
Aug 27 10:19:15 PM UTC 24 |
Aug 27 10:20:34 PM UTC 24 |
5327399458 ps |
| T2704 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/90.xbar_smoke.3462623279 |
|
|
Aug 27 10:20:26 PM UTC 24 |
Aug 27 10:20:35 PM UTC 24 |
206124208 ps |
| T2705 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/74.xbar_random_large_delays.430507399 |
|
|
Aug 27 10:02:58 PM UTC 24 |
Aug 27 10:20:35 PM UTC 24 |
96017783051 ps |
| T2706 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/90.xbar_smoke_zero_delays.187099814 |
|
|
Aug 27 10:20:27 PM UTC 24 |
Aug 27 10:20:37 PM UTC 24 |
51057582 ps |
| T2707 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/89.xbar_smoke_large_delays.3652868780 |
|
|
Aug 27 10:19:15 PM UTC 24 |
Aug 27 10:20:43 PM UTC 24 |
8040594915 ps |
| T2708 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/81.xbar_stress_all.4022985676 |
|
|
Aug 27 10:10:58 PM UTC 24 |
Aug 27 10:20:48 PM UTC 24 |
18784436735 ps |
| T2709 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/86.xbar_stress_all.3564147898 |
|
|
Aug 27 10:16:26 PM UTC 24 |
Aug 27 10:20:51 PM UTC 24 |
3100733743 ps |
| T2710 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/87.xbar_stress_all_with_reset_error.931014852 |
|
|
Aug 27 10:17:59 PM UTC 24 |
Aug 27 10:20:53 PM UTC 24 |
2764610113 ps |
| T2711 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/60.xbar_access_same_device_slow_rsp.1279503423 |
|
|
Aug 27 09:47:09 PM UTC 24 |
Aug 27 10:20:55 PM UTC 24 |
137883229191 ps |
| T2712 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/89.xbar_same_source.2253398464 |
|
|
Aug 27 10:19:32 PM UTC 24 |
Aug 27 10:20:56 PM UTC 24 |
2321434227 ps |
| T2713 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/89.xbar_random.4072501886 |
|
|
Aug 27 10:19:14 PM UTC 24 |
Aug 27 10:20:57 PM UTC 24 |
2598416279 ps |
| T2714 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/89.xbar_error_random.1943817807 |
|
|
Aug 27 10:19:39 PM UTC 24 |
Aug 27 10:20:59 PM UTC 24 |
2069318975 ps |
| T2715 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/88.xbar_random_slow_rsp.745102942 |
|
|
Aug 27 10:18:31 PM UTC 24 |
Aug 27 10:21:04 PM UTC 24 |
10426591563 ps |
| T2716 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/90.xbar_random.3549100154 |
|
|
Aug 27 10:20:46 PM UTC 24 |
Aug 27 10:21:06 PM UTC 24 |
439427794 ps |
| T2717 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/89.xbar_access_same_device.2593049681 |
|
|
Aug 27 10:19:27 PM UTC 24 |
Aug 27 10:21:06 PM UTC 24 |
973191377 ps |
| T2718 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/90.xbar_error_random.4120891696 |
|
|
Aug 27 10:20:57 PM UTC 24 |
Aug 27 10:21:09 PM UTC 24 |
67609541 ps |
| T2719 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/90.xbar_unmapped_addr.736004240 |
|
|
Aug 27 10:21:00 PM UTC 24 |
Aug 27 10:21:10 PM UTC 24 |
74292439 ps |
| T2720 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/90.xbar_error_and_unmapped_addr.4176979236 |
|
|
Aug 27 10:21:05 PM UTC 24 |
Aug 27 10:21:23 PM UTC 24 |
317380113 ps |
| T2721 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/91.xbar_smoke_zero_delays.2646149518 |
|
|
Aug 27 10:21:17 PM UTC 24 |
Aug 27 10:21:25 PM UTC 24 |
53147233 ps |
| T2722 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/91.xbar_smoke.3863366856 |
|
|
Aug 27 10:21:18 PM UTC 24 |
Aug 27 10:21:28 PM UTC 24 |
48515560 ps |
| T2723 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/90.xbar_stress_all_with_reset_error.2606319594 |
|
|
Aug 27 10:21:14 PM UTC 24 |
Aug 27 10:21:28 PM UTC 24 |
85668128 ps |
| T2724 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/89.xbar_stress_all.2972728333 |
|
|
Aug 27 10:19:45 PM UTC 24 |
Aug 27 10:21:30 PM UTC 24 |
1493611690 ps |
| T2725 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/90.xbar_random_zero_delays.564231718 |
|
|
Aug 27 10:20:49 PM UTC 24 |
Aug 27 10:21:34 PM UTC 24 |
389052508 ps |
| T2726 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/91.xbar_random_zero_delays.2047909427 |
|
|
Aug 27 10:21:25 PM UTC 24 |
Aug 27 10:21:40 PM UTC 24 |
146678376 ps |
| T2727 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/90.xbar_same_source.239733039 |
|
|
Aug 27 10:20:55 PM UTC 24 |
Aug 27 10:21:47 PM UTC 24 |
1811412386 ps |
| T2728 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/88.xbar_stress_all_with_rand_reset.2608279755 |
|
|
Aug 27 10:19:05 PM UTC 24 |
Aug 27 10:21:54 PM UTC 24 |
386181051 ps |
| T2729 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/87.xbar_random_large_delays.3980555423 |
|
|
Aug 27 10:17:25 PM UTC 24 |
Aug 27 10:22:03 PM UTC 24 |
26523334216 ps |
| T2730 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/85.xbar_stress_all_with_reset_error.3490583004 |
|
|
Aug 27 10:15:32 PM UTC 24 |
Aug 27 10:22:03 PM UTC 24 |
7149661920 ps |
| T2731 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/90.xbar_smoke_large_delays.2163772103 |
|
|
Aug 27 10:20:26 PM UTC 24 |
Aug 27 10:22:04 PM UTC 24 |
8490426323 ps |
| T2732 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/91.xbar_error_random.2136214264 |
|
|
Aug 27 10:21:45 PM UTC 24 |
Aug 27 10:22:06 PM UTC 24 |
534836409 ps |
| T2733 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/90.xbar_access_same_device.4235527407 |
|
|
Aug 27 10:20:53 PM UTC 24 |
Aug 27 10:22:07 PM UTC 24 |
985100071 ps |
| T2734 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/91.xbar_unmapped_addr.1713047043 |
|
|
Aug 27 10:21:51 PM UTC 24 |
Aug 27 10:22:10 PM UTC 24 |
329033642 ps |
| T2735 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/86.xbar_stress_all_with_error.2759410321 |
|
|
Aug 27 10:16:38 PM UTC 24 |
Aug 27 10:22:12 PM UTC 24 |
11304818838 ps |
| T2736 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/90.xbar_smoke_slow_rsp.1639147688 |
|
|
Aug 27 10:20:33 PM UTC 24 |
Aug 27 10:22:24 PM UTC 24 |
4571971616 ps |
| T2737 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/91.xbar_same_source.3477035950 |
|
|
Aug 27 10:21:50 PM UTC 24 |
Aug 27 10:22:30 PM UTC 24 |
427112747 ps |
| T2738 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/91.xbar_smoke_slow_rsp.4082063803 |
|
|
Aug 27 10:21:23 PM UTC 24 |
Aug 27 10:22:33 PM UTC 24 |
4483586141 ps |
| T2739 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/92.xbar_smoke_zero_delays.1515969304 |
|
|
Aug 27 10:22:28 PM UTC 24 |
Aug 27 10:22:38 PM UTC 24 |
41179858 ps |
| T2740 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/84.xbar_stress_all_with_error.375913246 |
|
|
Aug 27 10:14:30 PM UTC 24 |
Aug 27 10:22:42 PM UTC 24 |
14271704119 ps |
| T2741 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/92.xbar_smoke.749438433 |
|
|
Aug 27 10:22:27 PM UTC 24 |
Aug 27 10:22:42 PM UTC 24 |
228734994 ps |
| T2742 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/90.xbar_stress_all.4008562895 |
|
|
Aug 27 10:21:06 PM UTC 24 |
Aug 27 10:22:42 PM UTC 24 |
930120531 ps |
| T2743 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/88.xbar_stress_all_with_error.1974818476 |
|
|
Aug 27 10:19:08 PM UTC 24 |
Aug 27 10:22:43 PM UTC 24 |
5129778931 ps |
| T2744 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/91.xbar_random.4203356308 |
|
|
Aug 27 10:21:29 PM UTC 24 |
Aug 27 10:22:48 PM UTC 24 |
2355614875 ps |
| T2745 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/77.xbar_random_large_delays.1284380205 |
|
|
Aug 27 10:06:20 PM UTC 24 |
Aug 27 10:23:05 PM UTC 24 |
95806717718 ps |
| T2746 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/91.xbar_error_and_unmapped_addr.3278135402 |
|
|
Aug 27 10:21:56 PM UTC 24 |
Aug 27 10:23:07 PM UTC 24 |
1415680637 ps |
| T2747 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/92.xbar_random.426176467 |
|
|
Aug 27 10:22:33 PM UTC 24 |
Aug 27 10:23:07 PM UTC 24 |
282007613 ps |
| T2748 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/91.xbar_access_same_device.208037455 |
|
|
Aug 27 10:21:43 PM UTC 24 |
Aug 27 10:23:08 PM UTC 24 |
1957598898 ps |
| T2749 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/92.xbar_random_zero_delays.2864064977 |
|
|
Aug 27 10:22:35 PM UTC 24 |
Aug 27 10:23:09 PM UTC 24 |
394155868 ps |
| T2750 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/91.xbar_smoke_large_delays.3138186294 |
|
|
Aug 27 10:21:22 PM UTC 24 |
Aug 27 10:23:12 PM UTC 24 |
8658145659 ps |
| T2751 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/92.xbar_error_random.2185000199 |
|
|
Aug 27 10:23:04 PM UTC 24 |
Aug 27 10:23:17 PM UTC 24 |
127904209 ps |
| T2752 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/92.xbar_error_and_unmapped_addr.1665441298 |
|
|
Aug 27 10:23:05 PM UTC 24 |
Aug 27 10:23:18 PM UTC 24 |
58440566 ps |
| T2753 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/87.xbar_stress_all_with_error.433733178 |
|
|
Aug 27 10:17:56 PM UTC 24 |
Aug 27 10:23:26 PM UTC 24 |
11311204484 ps |
| T2754 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/84.xbar_stress_all_with_rand_reset.790732406 |
|
|
Aug 27 10:14:29 PM UTC 24 |
Aug 27 10:23:28 PM UTC 24 |
5144782871 ps |
| T2755 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/90.xbar_stress_all_with_error.1618110780 |
|
|
Aug 27 10:21:12 PM UTC 24 |
Aug 27 10:23:38 PM UTC 24 |
4824121683 ps |
| T2756 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/93.xbar_smoke.2722121471 |
|
|
Aug 27 10:23:28 PM UTC 24 |
Aug 27 10:23:39 PM UTC 24 |
44438032 ps |
| T2757 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/91.xbar_stress_all.1166692269 |
|
|
Aug 27 10:22:04 PM UTC 24 |
Aug 27 10:23:40 PM UTC 24 |
1397821302 ps |
| T2758 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/93.xbar_smoke_zero_delays.3637550534 |
|
|
Aug 27 10:23:32 PM UTC 24 |
Aug 27 10:23:42 PM UTC 24 |
37956127 ps |
| T2759 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/78.xbar_random_large_delays.2766543782 |
|
|
Aug 27 10:07:44 PM UTC 24 |
Aug 27 10:23:46 PM UTC 24 |
94335062196 ps |
| T2760 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/87.xbar_access_same_device_slow_rsp.363474944 |
|
|
Aug 27 10:17:31 PM UTC 24 |
Aug 27 10:23:47 PM UTC 24 |
26351451895 ps |
| T2761 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/92.xbar_same_source.3574930302 |
|
|
Aug 27 10:23:05 PM UTC 24 |
Aug 27 10:23:48 PM UTC 24 |
581047281 ps |