| T2266 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/65.xbar_error_random.3334266464 |
|
|
Aug 27 09:52:44 PM UTC 24 |
Aug 27 09:53:06 PM UTC 24 |
252129819 ps |
| T2267 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/65.xbar_stress_all_with_rand_reset.2856122863 |
|
|
Aug 27 09:52:58 PM UTC 24 |
Aug 27 09:53:07 PM UTC 24 |
30166546 ps |
| T2268 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/65.xbar_smoke_large_delays.557877093 |
|
|
Aug 27 09:52:13 PM UTC 24 |
Aug 27 09:53:08 PM UTC 24 |
6609467901 ps |
| T2269 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/65.xbar_access_same_device.4033277379 |
|
|
Aug 27 09:52:28 PM UTC 24 |
Aug 27 09:53:09 PM UTC 24 |
645399694 ps |
| T2270 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/65.xbar_random_zero_delays.307733722 |
|
|
Aug 27 09:52:22 PM UTC 24 |
Aug 27 09:53:12 PM UTC 24 |
596218471 ps |
| T2271 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/59.xbar_stress_all_with_rand_reset.3860111249 |
|
|
Aug 27 09:46:36 PM UTC 24 |
Aug 27 09:53:12 PM UTC 24 |
8658134068 ps |
| T2272 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/59.xbar_stress_all_with_reset_error.965987576 |
|
|
Aug 27 09:46:37 PM UTC 24 |
Aug 27 09:53:18 PM UTC 24 |
5894653703 ps |
| T2273 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/62.xbar_stress_all_with_reset_error.1388310472 |
|
|
Aug 27 09:50:08 PM UTC 24 |
Aug 27 09:53:20 PM UTC 24 |
525051201 ps |
| T2274 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/46.xbar_access_same_device_slow_rsp.3272134298 |
|
|
Aug 27 09:31:02 PM UTC 24 |
Aug 27 09:53:24 PM UTC 24 |
79113312605 ps |
| T2275 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/59.xbar_random_slow_rsp.1949138842 |
|
|
Aug 27 09:45:54 PM UTC 24 |
Aug 27 09:53:29 PM UTC 24 |
30712082824 ps |
| T2276 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/64.xbar_smoke_large_delays.3051060382 |
|
|
Aug 27 09:51:12 PM UTC 24 |
Aug 27 09:53:31 PM UTC 24 |
8233127087 ps |
| T2277 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/66.xbar_smoke_zero_delays.1213314320 |
|
|
Aug 27 09:53:28 PM UTC 24 |
Aug 27 09:53:38 PM UTC 24 |
38312348 ps |
| T2278 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/66.xbar_smoke.4202437104 |
|
|
Aug 27 09:53:25 PM UTC 24 |
Aug 27 09:53:39 PM UTC 24 |
210682319 ps |
| T2279 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/64.xbar_stress_all_with_rand_reset.3012277377 |
|
|
Aug 27 09:51:48 PM UTC 24 |
Aug 27 09:53:40 PM UTC 24 |
128918309 ps |
| T2280 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/45.xbar_access_same_device_slow_rsp.848824872 |
|
|
Aug 27 09:29:40 PM UTC 24 |
Aug 27 09:53:42 PM UTC 24 |
96758119503 ps |
| T2281 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/65.xbar_smoke_slow_rsp.21516102 |
|
|
Aug 27 09:52:16 PM UTC 24 |
Aug 27 09:53:42 PM UTC 24 |
4717522670 ps |
| T2282 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/65.xbar_unmapped_addr.760632942 |
|
|
Aug 27 09:52:46 PM UTC 24 |
Aug 27 09:53:44 PM UTC 24 |
1263553479 ps |
| T2283 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/65.xbar_same_source.1153399732 |
|
|
Aug 27 09:52:40 PM UTC 24 |
Aug 27 09:53:46 PM UTC 24 |
2383283539 ps |
| T2284 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/66.xbar_random_zero_delays.1858148881 |
|
|
Aug 27 09:53:35 PM UTC 24 |
Aug 27 09:53:48 PM UTC 24 |
120010102 ps |
| T2285 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/65.xbar_error_and_unmapped_addr.3068904608 |
|
|
Aug 27 09:52:52 PM UTC 24 |
Aug 27 09:53:48 PM UTC 24 |
1430791555 ps |
| T2286 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/65.xbar_access_same_device_slow_rsp.2297508001 |
|
|
Aug 27 09:52:37 PM UTC 24 |
Aug 27 09:53:51 PM UTC 24 |
4837158527 ps |
| T2287 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/66.xbar_random.846478106 |
|
|
Aug 27 09:53:36 PM UTC 24 |
Aug 27 09:54:12 PM UTC 24 |
809474635 ps |
| T2288 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/66.xbar_unmapped_addr.3561570530 |
|
|
Aug 27 09:54:01 PM UTC 24 |
Aug 27 09:54:14 PM UTC 24 |
119850474 ps |
| T2289 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/65.xbar_stress_all_with_error.1404497130 |
|
|
Aug 27 09:52:58 PM UTC 24 |
Aug 27 09:54:15 PM UTC 24 |
1013168111 ps |
| T2290 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/67.xbar_smoke_zero_delays.1330982168 |
|
|
Aug 27 09:54:09 PM UTC 24 |
Aug 27 09:54:18 PM UTC 24 |
40826340 ps |
| T2291 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/64.xbar_access_same_device_slow_rsp.2276324744 |
|
|
Aug 27 09:51:32 PM UTC 24 |
Aug 27 09:54:20 PM UTC 24 |
11078955845 ps |
| T2292 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/67.xbar_smoke.3425454876 |
|
|
Aug 27 09:54:07 PM UTC 24 |
Aug 27 09:54:22 PM UTC 24 |
209499700 ps |
| T2293 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/66.xbar_same_source.3697582903 |
|
|
Aug 27 09:53:52 PM UTC 24 |
Aug 27 09:54:26 PM UTC 24 |
338326083 ps |
| T2294 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/65.xbar_stress_all_with_reset_error.953819459 |
|
|
Aug 27 09:53:12 PM UTC 24 |
Aug 27 09:54:40 PM UTC 24 |
332602620 ps |
| T2295 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/66.xbar_error_and_unmapped_addr.402417213 |
|
|
Aug 27 09:54:03 PM UTC 24 |
Aug 27 09:54:54 PM UTC 24 |
863971741 ps |
| T2296 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/65.xbar_stress_all.1378751541 |
|
|
Aug 27 09:52:50 PM UTC 24 |
Aug 27 09:54:54 PM UTC 24 |
1533321192 ps |
| T2297 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/66.xbar_access_same_device.840823800 |
|
|
Aug 27 09:53:47 PM UTC 24 |
Aug 27 09:54:55 PM UTC 24 |
921369141 ps |
| T2298 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/66.xbar_stress_all_with_rand_reset.1574804628 |
|
|
Aug 27 09:54:06 PM UTC 24 |
Aug 27 09:55:04 PM UTC 24 |
162552086 ps |
| T2299 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/66.xbar_smoke_slow_rsp.2665507029 |
|
|
Aug 27 09:53:32 PM UTC 24 |
Aug 27 09:55:08 PM UTC 24 |
4419772796 ps |
| T2300 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/66.xbar_error_random.140671042 |
|
|
Aug 27 09:53:59 PM UTC 24 |
Aug 27 09:55:17 PM UTC 24 |
1885496088 ps |
| T2301 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/67.xbar_random_zero_delays.3103010486 |
|
|
Aug 27 09:54:39 PM UTC 24 |
Aug 27 09:55:19 PM UTC 24 |
351507766 ps |
| T2302 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/66.xbar_smoke_large_delays.972735536 |
|
|
Aug 27 09:53:31 PM UTC 24 |
Aug 27 09:55:28 PM UTC 24 |
10377758281 ps |
| T2303 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/67.xbar_error_and_unmapped_addr.3483747501 |
|
|
Aug 27 09:55:18 PM UTC 24 |
Aug 27 09:55:37 PM UTC 24 |
120978556 ps |
| T2304 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/67.xbar_random.1099792109 |
|
|
Aug 27 09:54:36 PM UTC 24 |
Aug 27 09:55:39 PM UTC 24 |
1818189296 ps |
| T2305 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/67.xbar_same_source.1562436834 |
|
|
Aug 27 09:55:03 PM UTC 24 |
Aug 27 09:55:45 PM UTC 24 |
407613911 ps |
| T2306 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/61.xbar_stress_all.2595073979 |
|
|
Aug 27 09:48:45 PM UTC 24 |
Aug 27 09:55:56 PM UTC 24 |
12803595603 ps |
| T2307 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/62.xbar_stress_all.1673840443 |
|
|
Aug 27 09:49:45 PM UTC 24 |
Aug 27 09:55:56 PM UTC 24 |
12278636517 ps |
| T2308 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/68.xbar_smoke.500757878 |
|
|
Aug 27 09:55:51 PM UTC 24 |
Aug 27 09:56:01 PM UTC 24 |
46235939 ps |
| T2309 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/67.xbar_error_random.3924712848 |
|
|
Aug 27 09:55:15 PM UTC 24 |
Aug 27 09:56:03 PM UTC 24 |
1246140832 ps |
| T2310 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/55.xbar_random_large_delays.829571894 |
|
|
Aug 27 09:41:41 PM UTC 24 |
Aug 27 09:56:05 PM UTC 24 |
78222019089 ps |
| T2311 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/67.xbar_unmapped_addr.1559306961 |
|
|
Aug 27 09:55:17 PM UTC 24 |
Aug 27 09:56:06 PM UTC 24 |
1208269258 ps |
| T2312 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/58.xbar_random_slow_rsp.3733127284 |
|
|
Aug 27 09:44:52 PM UTC 24 |
Aug 27 09:56:08 PM UTC 24 |
46545004314 ps |
| T2313 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/61.xbar_random_large_delays.2754704453 |
|
|
Aug 27 09:48:31 PM UTC 24 |
Aug 27 09:56:08 PM UTC 24 |
44230773338 ps |
| T2314 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/68.xbar_smoke_zero_delays.2063643741 |
|
|
Aug 27 09:56:00 PM UTC 24 |
Aug 27 09:56:11 PM UTC 24 |
58391439 ps |
| T2315 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/53.xbar_access_same_device_slow_rsp.845855917 |
|
|
Aug 27 09:39:44 PM UTC 24 |
Aug 27 09:56:13 PM UTC 24 |
62368997193 ps |
| T2316 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/67.xbar_smoke_slow_rsp.1415828658 |
|
|
Aug 27 09:54:34 PM UTC 24 |
Aug 27 09:56:15 PM UTC 24 |
5090097437 ps |
| T2317 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/54.xbar_random_large_delays.1861179261 |
|
|
Aug 27 09:40:30 PM UTC 24 |
Aug 27 09:56:19 PM UTC 24 |
92262261840 ps |
| T2318 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/56.xbar_random_large_delays.1490685748 |
|
|
Aug 27 09:42:38 PM UTC 24 |
Aug 27 09:56:25 PM UTC 24 |
86633179518 ps |
| T2319 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/67.xbar_smoke_large_delays.3206140069 |
|
|
Aug 27 09:54:13 PM UTC 24 |
Aug 27 09:56:43 PM UTC 24 |
9279964262 ps |
| T2320 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/68.xbar_random_zero_delays.740927987 |
|
|
Aug 27 09:56:18 PM UTC 24 |
Aug 27 09:56:46 PM UTC 24 |
334650788 ps |
| T2321 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/68.xbar_error_and_unmapped_addr.3187812945 |
|
|
Aug 27 09:56:36 PM UTC 24 |
Aug 27 09:56:51 PM UTC 24 |
194996128 ps |
| T2322 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/68.xbar_random.3809611114 |
|
|
Aug 27 09:56:16 PM UTC 24 |
Aug 27 09:57:04 PM UTC 24 |
1002181930 ps |
| T2323 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/68.xbar_unmapped_addr.1052830974 |
|
|
Aug 27 09:56:33 PM UTC 24 |
Aug 27 09:57:11 PM UTC 24 |
220878109 ps |
| T2324 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/68.xbar_same_source.239535749 |
|
|
Aug 27 09:56:29 PM UTC 24 |
Aug 27 09:57:14 PM UTC 24 |
477127077 ps |
| T2325 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/69.xbar_smoke.1290765463 |
|
|
Aug 27 09:57:07 PM UTC 24 |
Aug 27 09:57:17 PM UTC 24 |
39542771 ps |
| T2326 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/68.xbar_smoke_slow_rsp.4220123956 |
|
|
Aug 27 09:56:05 PM UTC 24 |
Aug 27 09:57:17 PM UTC 24 |
3641214348 ps |
| T2327 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/69.xbar_smoke_zero_delays.1624991847 |
|
|
Aug 27 09:57:13 PM UTC 24 |
Aug 27 09:57:24 PM UTC 24 |
55804366 ps |
| T2328 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/68.xbar_error_random.3322321196 |
|
|
Aug 27 09:56:31 PM UTC 24 |
Aug 27 09:57:30 PM UTC 24 |
576659454 ps |
| T2329 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/67.xbar_access_same_device.2877602604 |
|
|
Aug 27 09:54:45 PM UTC 24 |
Aug 27 09:57:31 PM UTC 24 |
3052247425 ps |
| T2330 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/63.xbar_stress_all_with_reset_error.3801763364 |
|
|
Aug 27 09:51:01 PM UTC 24 |
Aug 27 09:57:35 PM UTC 24 |
7782779339 ps |
| T2331 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/64.xbar_stress_all.2157579725 |
|
|
Aug 27 09:51:45 PM UTC 24 |
Aug 27 09:57:38 PM UTC 24 |
8621938408 ps |
| T2332 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/61.xbar_stress_all_with_rand_reset.1292318662 |
|
|
Aug 27 09:48:48 PM UTC 24 |
Aug 27 09:57:48 PM UTC 24 |
10354225860 ps |
| T2333 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/67.xbar_random_large_delays.355334582 |
|
|
Aug 27 09:54:41 PM UTC 24 |
Aug 27 09:57:49 PM UTC 24 |
19669017408 ps |
| T2334 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/68.xbar_smoke_large_delays.206617924 |
|
|
Aug 27 09:56:01 PM UTC 24 |
Aug 27 09:57:54 PM UTC 24 |
9969550786 ps |
| T2335 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/68.xbar_access_same_device.323488677 |
|
|
Aug 27 09:56:26 PM UTC 24 |
Aug 27 09:57:57 PM UTC 24 |
1935584374 ps |
| T2336 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/69.xbar_random_zero_delays.2429583972 |
|
|
Aug 27 09:57:39 PM UTC 24 |
Aug 27 09:58:08 PM UTC 24 |
247447527 ps |
| T2337 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/54.xbar_access_same_device_slow_rsp.3902772046 |
|
|
Aug 27 09:40:43 PM UTC 24 |
Aug 27 09:58:11 PM UTC 24 |
59623065032 ps |
| T2338 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/69.xbar_random.236670858 |
|
|
Aug 27 09:57:37 PM UTC 24 |
Aug 27 09:58:12 PM UTC 24 |
873217194 ps |
| T2339 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/66.xbar_stress_all_with_reset_error.1568635718 |
|
|
Aug 27 09:54:07 PM UTC 24 |
Aug 27 09:58:23 PM UTC 24 |
1382887881 ps |
| T2340 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/58.xbar_random_large_delays.1461379164 |
|
|
Aug 27 09:44:50 PM UTC 24 |
Aug 27 09:58:24 PM UTC 24 |
81640965130 ps |
| T2341 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/69.xbar_unmapped_addr.4123269775 |
|
|
Aug 27 09:58:07 PM UTC 24 |
Aug 27 09:58:24 PM UTC 24 |
110252066 ps |
| T2342 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/62.xbar_stress_all_with_rand_reset.4216106603 |
|
|
Aug 27 09:49:52 PM UTC 24 |
Aug 27 09:58:25 PM UTC 24 |
10753163180 ps |
| T2343 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/69.xbar_access_same_device.2916614867 |
|
|
Aug 27 09:57:52 PM UTC 24 |
Aug 27 09:58:44 PM UTC 24 |
678101765 ps |
| T2344 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/70.xbar_smoke.2617400955 |
|
|
Aug 27 09:58:35 PM UTC 24 |
Aug 27 09:58:46 PM UTC 24 |
58538949 ps |
| T2345 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/57.xbar_random_large_delays.4162351004 |
|
|
Aug 27 09:43:52 PM UTC 24 |
Aug 27 09:58:46 PM UTC 24 |
85929465159 ps |
| T2346 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/69.xbar_smoke_slow_rsp.1605331898 |
|
|
Aug 27 09:57:35 PM UTC 24 |
Aug 27 09:58:47 PM UTC 24 |
4885090912 ps |
| T2347 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/69.xbar_error_and_unmapped_addr.1626964630 |
|
|
Aug 27 09:58:09 PM UTC 24 |
Aug 27 09:58:50 PM UTC 24 |
768476024 ps |
| T2348 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/69.xbar_error_random.454978465 |
|
|
Aug 27 09:57:58 PM UTC 24 |
Aug 27 09:58:51 PM UTC 24 |
2059213755 ps |
| T2349 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/57.xbar_random_slow_rsp.1182619252 |
|
|
Aug 27 09:43:54 PM UTC 24 |
Aug 27 09:58:53 PM UTC 24 |
55633912364 ps |
| T2350 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/70.xbar_smoke_zero_delays.302507702 |
|
|
Aug 27 09:58:47 PM UTC 24 |
Aug 27 09:58:56 PM UTC 24 |
53154582 ps |
| T2351 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/69.xbar_smoke_large_delays.1992095676 |
|
|
Aug 27 09:57:27 PM UTC 24 |
Aug 27 09:59:03 PM UTC 24 |
8154332735 ps |
| T2352 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/66.xbar_stress_all_with_error.3273848321 |
|
|
Aug 27 09:54:07 PM UTC 24 |
Aug 27 09:59:05 PM UTC 24 |
10573260806 ps |
| T2353 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/64.xbar_stress_all_with_reset_error.3344823237 |
|
|
Aug 27 09:52:03 PM UTC 24 |
Aug 27 09:59:08 PM UTC 24 |
9678993733 ps |
| T2354 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/70.xbar_random.1316157862 |
|
|
Aug 27 09:58:48 PM UTC 24 |
Aug 27 09:59:10 PM UTC 24 |
404207357 ps |
| T2355 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/68.xbar_random_large_delays.41872370 |
|
|
Aug 27 09:56:21 PM UTC 24 |
Aug 27 09:59:14 PM UTC 24 |
17053193265 ps |
| T2356 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/70.xbar_random_zero_delays.2789676985 |
|
|
Aug 27 09:59:05 PM UTC 24 |
Aug 27 09:59:15 PM UTC 24 |
87107059 ps |
| T2357 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/69.xbar_same_source.3002926518 |
|
|
Aug 27 09:57:58 PM UTC 24 |
Aug 27 09:59:23 PM UTC 24 |
2489667216 ps |
| T2358 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/70.xbar_same_source.1312509442 |
|
|
Aug 27 09:59:13 PM UTC 24 |
Aug 27 09:59:30 PM UTC 24 |
118320138 ps |
| T2359 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/61.xbar_access_same_device_slow_rsp.1582425600 |
|
|
Aug 27 09:48:39 PM UTC 24 |
Aug 27 09:59:37 PM UTC 24 |
49814356203 ps |
| T2360 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/70.xbar_error_random.3937443401 |
|
|
Aug 27 09:59:15 PM UTC 24 |
Aug 27 09:59:40 PM UTC 24 |
581646591 ps |
| T2361 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/69.xbar_stress_all.1316970862 |
|
|
Aug 27 09:58:16 PM UTC 24 |
Aug 27 09:59:48 PM UTC 24 |
2448427946 ps |
| T2362 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/71.xbar_smoke.379496522 |
|
|
Aug 27 09:59:38 PM UTC 24 |
Aug 27 09:59:48 PM UTC 24 |
54611145 ps |
| T2363 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/70.xbar_smoke_large_delays.2627547910 |
|
|
Aug 27 09:58:47 PM UTC 24 |
Aug 27 09:59:50 PM UTC 24 |
6217125334 ps |
| T2364 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/67.xbar_stress_all.70883061 |
|
|
Aug 27 09:55:25 PM UTC 24 |
Aug 27 09:59:53 PM UTC 24 |
2963100918 ps |
| T2365 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/71.xbar_smoke_zero_delays.2044404522 |
|
|
Aug 27 09:59:46 PM UTC 24 |
Aug 27 09:59:56 PM UTC 24 |
46484799 ps |
| T2366 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/70.xbar_stress_all_with_reset_error.3153657561 |
|
|
Aug 27 09:59:37 PM UTC 24 |
Aug 27 09:59:57 PM UTC 24 |
90382123 ps |
| T2367 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/70.xbar_error_and_unmapped_addr.2705657023 |
|
|
Aug 27 09:59:25 PM UTC 24 |
Aug 27 09:59:59 PM UTC 24 |
311357930 ps |
| T2368 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/70.xbar_unmapped_addr.890285639 |
|
|
Aug 27 09:59:16 PM UTC 24 |
Aug 27 10:00:06 PM UTC 24 |
1164408689 ps |
| T2369 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/68.xbar_stress_all.3156555780 |
|
|
Aug 27 09:56:34 PM UTC 24 |
Aug 27 10:00:07 PM UTC 24 |
2440545116 ps |
| T2370 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/68.xbar_stress_all_with_error.1525967849 |
|
|
Aug 27 09:56:47 PM UTC 24 |
Aug 27 10:00:13 PM UTC 24 |
2477268472 ps |
| T2371 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/68.xbar_stress_all_with_rand_reset.2388734439 |
|
|
Aug 27 09:56:43 PM UTC 24 |
Aug 27 10:00:15 PM UTC 24 |
561730030 ps |
| T2372 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/70.xbar_access_same_device.10410754 |
|
|
Aug 27 09:59:09 PM UTC 24 |
Aug 27 10:00:25 PM UTC 24 |
1438523767 ps |
| T2373 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/70.xbar_smoke_slow_rsp.3636126160 |
|
|
Aug 27 09:58:46 PM UTC 24 |
Aug 27 10:00:25 PM UTC 24 |
4816582942 ps |
| T2374 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/68.xbar_stress_all_with_reset_error.4243345846 |
|
|
Aug 27 09:57:03 PM UTC 24 |
Aug 27 10:00:26 PM UTC 24 |
618472647 ps |
| T2375 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/48.xbar_access_same_device_slow_rsp.2415591209 |
|
|
Aug 27 09:34:02 PM UTC 24 |
Aug 27 10:00:28 PM UTC 24 |
102151143726 ps |
| T2376 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/71.xbar_random_zero_delays.644946297 |
|
|
Aug 27 10:00:10 PM UTC 24 |
Aug 27 10:00:32 PM UTC 24 |
215802546 ps |
| T2377 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/47.xbar_access_same_device_slow_rsp.4108724511 |
|
|
Aug 27 09:32:19 PM UTC 24 |
Aug 27 10:00:35 PM UTC 24 |
109112779576 ps |
| T2378 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/71.xbar_error_and_unmapped_addr.1438410902 |
|
|
Aug 27 10:00:27 PM UTC 24 |
Aug 27 10:00:37 PM UTC 24 |
139833619 ps |
| T2379 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/64.xbar_stress_all_with_error.1783545487 |
|
|
Aug 27 09:51:53 PM UTC 24 |
Aug 27 10:00:41 PM UTC 24 |
11689306909 ps |
| T2380 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/71.xbar_unmapped_addr.662859180 |
|
|
Aug 27 10:00:26 PM UTC 24 |
Aug 27 10:00:46 PM UTC 24 |
346833832 ps |
| T2381 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/72.xbar_smoke_zero_delays.1219201819 |
|
|
Aug 27 10:00:47 PM UTC 24 |
Aug 27 10:00:54 PM UTC 24 |
48009622 ps |
| T2382 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/71.xbar_random.3943420199 |
|
|
Aug 27 10:00:01 PM UTC 24 |
Aug 27 10:00:54 PM UTC 24 |
464446415 ps |
| T2383 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/71.xbar_stress_all_with_rand_reset.1051493522 |
|
|
Aug 27 10:00:35 PM UTC 24 |
Aug 27 10:00:56 PM UTC 24 |
50677482 ps |
| T2384 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/72.xbar_smoke.2854190862 |
|
|
Aug 27 10:00:47 PM UTC 24 |
Aug 27 10:00:56 PM UTC 24 |
45474724 ps |
| T2385 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/59.xbar_random_large_delays.3446126216 |
|
|
Aug 27 09:45:53 PM UTC 24 |
Aug 27 10:00:58 PM UTC 24 |
93622666254 ps |
| T2386 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/63.xbar_random_large_delays.3146986813 |
|
|
Aug 27 09:50:32 PM UTC 24 |
Aug 27 10:00:58 PM UTC 24 |
66263551781 ps |
| T2387 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/71.xbar_error_random.2267702027 |
|
|
Aug 27 10:00:20 PM UTC 24 |
Aug 27 10:01:11 PM UTC 24 |
614816967 ps |
| T2388 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/72.xbar_random_zero_delays.3893558383 |
|
|
Aug 27 10:01:00 PM UTC 24 |
Aug 27 10:01:13 PM UTC 24 |
102049617 ps |
| T2389 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/71.xbar_smoke_large_delays.1145182861 |
|
|
Aug 27 09:59:51 PM UTC 24 |
Aug 27 10:01:14 PM UTC 24 |
9371944379 ps |
| T2390 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/69.xbar_stress_all_with_error.3469425765 |
|
|
Aug 27 09:58:29 PM UTC 24 |
Aug 27 10:01:22 PM UTC 24 |
4292599802 ps |
| T2391 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/69.xbar_stress_all_with_reset_error.2361453412 |
|
|
Aug 27 09:58:35 PM UTC 24 |
Aug 27 10:01:26 PM UTC 24 |
497657188 ps |
| T2392 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/67.xbar_stress_all_with_error.4031749033 |
|
|
Aug 27 09:55:40 PM UTC 24 |
Aug 27 10:01:27 PM UTC 24 |
4320423760 ps |
| T2393 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/49.xbar_access_same_device_slow_rsp.1271629613 |
|
|
Aug 27 09:35:28 PM UTC 24 |
Aug 27 10:01:28 PM UTC 24 |
107615272626 ps |
| T2394 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/69.xbar_random_large_delays.2059346014 |
|
|
Aug 27 09:57:39 PM UTC 24 |
Aug 27 10:01:30 PM UTC 24 |
22395408317 ps |
| T2395 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/66.xbar_random_slow_rsp.1360593335 |
|
|
Aug 27 09:53:43 PM UTC 24 |
Aug 27 10:01:30 PM UTC 24 |
32884935721 ps |
| T2396 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/72.xbar_unmapped_addr.2783917799 |
|
|
Aug 27 10:01:21 PM UTC 24 |
Aug 27 10:01:35 PM UTC 24 |
66919032 ps |
| T2397 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/71.xbar_access_same_device.376650632 |
|
|
Aug 27 10:00:13 PM UTC 24 |
Aug 27 10:01:43 PM UTC 24 |
1380364069 ps |
| T2398 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/71.xbar_smoke_slow_rsp.1698269232 |
|
|
Aug 27 09:59:58 PM UTC 24 |
Aug 27 10:01:44 PM UTC 24 |
5395729367 ps |
| T2399 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/71.xbar_same_source.22920200 |
|
|
Aug 27 10:00:19 PM UTC 24 |
Aug 27 10:01:45 PM UTC 24 |
2735176328 ps |
| T2400 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/62.xbar_random_large_delays.2558801222 |
|
|
Aug 27 09:49:20 PM UTC 24 |
Aug 27 10:01:46 PM UTC 24 |
84936679599 ps |
| T2401 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/72.xbar_error_and_unmapped_addr.3156212534 |
|
|
Aug 27 10:01:33 PM UTC 24 |
Aug 27 10:01:50 PM UTC 24 |
104802900 ps |
| T2402 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/73.xbar_smoke.3482346643 |
|
|
Aug 27 10:01:47 PM UTC 24 |
Aug 27 10:01:59 PM UTC 24 |
162096471 ps |
| T2403 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/73.xbar_smoke_zero_delays.2974540793 |
|
|
Aug 27 10:01:50 PM UTC 24 |
Aug 27 10:01:59 PM UTC 24 |
35263115 ps |
| T2404 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/72.xbar_same_source.97084773 |
|
|
Aug 27 10:01:19 PM UTC 24 |
Aug 27 10:01:59 PM UTC 24 |
376912192 ps |
| T2405 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/72.xbar_random.2660927198 |
|
|
Aug 27 10:00:57 PM UTC 24 |
Aug 27 10:01:59 PM UTC 24 |
1809408748 ps |
| T2406 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/60.xbar_random_slow_rsp.1673455129 |
|
|
Aug 27 09:47:11 PM UTC 24 |
Aug 27 10:02:07 PM UTC 24 |
64422734632 ps |
| T2407 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/72.xbar_error_random.1132923294 |
|
|
Aug 27 10:01:21 PM UTC 24 |
Aug 27 10:02:08 PM UTC 24 |
1512691911 ps |
| T2408 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/72.xbar_access_same_device.3055619167 |
|
|
Aug 27 10:01:17 PM UTC 24 |
Aug 27 10:02:21 PM UTC 24 |
1364577263 ps |
| T2409 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/69.xbar_stress_all_with_rand_reset.939393645 |
|
|
Aug 27 09:58:20 PM UTC 24 |
Aug 27 10:02:21 PM UTC 24 |
2445707464 ps |
| T2410 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/73.xbar_random_zero_delays.2502659069 |
|
|
Aug 27 10:02:05 PM UTC 24 |
Aug 27 10:02:22 PM UTC 24 |
188710744 ps |
| T2411 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/72.xbar_smoke_slow_rsp.68096961 |
|
|
Aug 27 10:00:57 PM UTC 24 |
Aug 27 10:02:23 PM UTC 24 |
3794791439 ps |
| T2412 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/72.xbar_smoke_large_delays.2045259056 |
|
|
Aug 27 10:00:53 PM UTC 24 |
Aug 27 10:02:28 PM UTC 24 |
7444543735 ps |
| T2413 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/73.xbar_same_source.4077416444 |
|
|
Aug 27 10:02:19 PM UTC 24 |
Aug 27 10:02:31 PM UTC 24 |
77275382 ps |
| T2414 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/71.xbar_stress_all_with_error.2505767667 |
|
|
Aug 27 10:00:45 PM UTC 24 |
Aug 27 10:02:34 PM UTC 24 |
1457658298 ps |
| T2415 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/61.xbar_random_slow_rsp.1816254754 |
|
|
Aug 27 09:48:29 PM UTC 24 |
Aug 27 10:02:35 PM UTC 24 |
58158412333 ps |
| T2416 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/67.xbar_stress_all_with_reset_error.1012858713 |
|
|
Aug 27 09:55:42 PM UTC 24 |
Aug 27 10:02:37 PM UTC 24 |
7933221800 ps |
| T2417 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/74.xbar_smoke.1340657753 |
|
|
Aug 27 10:02:43 PM UTC 24 |
Aug 27 10:02:53 PM UTC 24 |
36098622 ps |
| T2418 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/74.xbar_smoke_zero_delays.3639212948 |
|
|
Aug 27 10:02:44 PM UTC 24 |
Aug 27 10:02:53 PM UTC 24 |
58579562 ps |
| T2419 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/72.xbar_stress_all_with_error.3515470310 |
|
|
Aug 27 10:01:43 PM UTC 24 |
Aug 27 10:02:54 PM UTC 24 |
719182926 ps |
| T2420 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/58.xbar_stress_all_with_reset_error.3386157416 |
|
|
Aug 27 09:45:36 PM UTC 24 |
Aug 27 10:02:59 PM UTC 24 |
12584920215 ps |
| T2421 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/73.xbar_unmapped_addr.1541238661 |
|
|
Aug 27 10:02:20 PM UTC 24 |
Aug 27 10:02:59 PM UTC 24 |
264203388 ps |
| T2422 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/73.xbar_error_random.1442014715 |
|
|
Aug 27 10:02:18 PM UTC 24 |
Aug 27 10:02:59 PM UTC 24 |
1172148327 ps |
| T2423 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/73.xbar_error_and_unmapped_addr.1132065087 |
|
|
Aug 27 10:02:20 PM UTC 24 |
Aug 27 10:03:01 PM UTC 24 |
1134308085 ps |
| T2424 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/73.xbar_random.1783160176 |
|
|
Aug 27 10:01:54 PM UTC 24 |
Aug 27 10:03:03 PM UTC 24 |
1716016624 ps |
| T2425 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/73.xbar_smoke_slow_rsp.1430076759 |
|
|
Aug 27 10:01:51 PM UTC 24 |
Aug 27 10:03:04 PM UTC 24 |
4892085600 ps |
| T2426 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/70.xbar_stress_all.4024128192 |
|
|
Aug 27 09:59:28 PM UTC 24 |
Aug 27 10:03:07 PM UTC 24 |
2506146936 ps |
| T2427 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/70.xbar_random_slow_rsp.3259620363 |
|
|
Aug 27 09:59:08 PM UTC 24 |
Aug 27 10:03:13 PM UTC 24 |
14945690113 ps |
| T2428 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/73.xbar_smoke_large_delays.1198579049 |
|
|
Aug 27 10:01:49 PM UTC 24 |
Aug 27 10:03:14 PM UTC 24 |
7747913781 ps |
| T2429 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/72.xbar_stress_all_with_reset_error.3985466307 |
|
|
Aug 27 10:01:47 PM UTC 24 |
Aug 27 10:03:15 PM UTC 24 |
214391294 ps |
| T2430 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/73.xbar_access_same_device.1334597877 |
|
|
Aug 27 10:02:09 PM UTC 24 |
Aug 27 10:03:16 PM UTC 24 |
1441808094 ps |
| T2431 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/74.xbar_random.3109923208 |
|
|
Aug 27 10:02:57 PM UTC 24 |
Aug 27 10:03:25 PM UTC 24 |
259279994 ps |
| T2432 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/66.xbar_stress_all.3001044032 |
|
|
Aug 27 09:54:00 PM UTC 24 |
Aug 27 10:03:28 PM UTC 24 |
14569578329 ps |
| T2433 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/74.xbar_random_zero_delays.2072678749 |
|
|
Aug 27 10:02:59 PM UTC 24 |
Aug 27 10:03:31 PM UTC 24 |
288656133 ps |
| T2434 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/64.xbar_random_large_delays.1575240845 |
|
|
Aug 27 09:51:28 PM UTC 24 |
Aug 27 10:03:32 PM UTC 24 |
73709061886 ps |
| T2435 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/74.xbar_error_random.3697417584 |
|
|
Aug 27 10:03:16 PM UTC 24 |
Aug 27 10:03:39 PM UTC 24 |
536421059 ps |
| T2436 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/75.xbar_smoke_zero_delays.3375676665 |
|
|
Aug 27 10:03:38 PM UTC 24 |
Aug 27 10:03:48 PM UTC 24 |
51944438 ps |
| T2437 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/75.xbar_smoke.1197483806 |
|
|
Aug 27 10:03:37 PM UTC 24 |
Aug 27 10:03:50 PM UTC 24 |
197319029 ps |
| T2438 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/70.xbar_random_large_delays.4054700190 |
|
|
Aug 27 09:59:09 PM UTC 24 |
Aug 27 10:03:55 PM UTC 24 |
25146409514 ps |
| T2439 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/75.xbar_random.70551857 |
|
|
Aug 27 10:03:51 PM UTC 24 |
Aug 27 10:04:05 PM UTC 24 |
106630978 ps |
| T2440 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/72.xbar_random_large_delays.3955842623 |
|
|
Aug 27 10:01:06 PM UTC 24 |
Aug 27 10:04:07 PM UTC 24 |
18691170688 ps |
| T2441 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/62.xbar_random_slow_rsp.1661824244 |
|
|
Aug 27 09:49:21 PM UTC 24 |
Aug 27 10:04:07 PM UTC 24 |
57610227311 ps |
| T2442 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/74.xbar_unmapped_addr.1158033207 |
|
|
Aug 27 10:03:19 PM UTC 24 |
Aug 27 10:04:08 PM UTC 24 |
334877758 ps |
| T2443 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/65.xbar_random_slow_rsp.1492785300 |
|
|
Aug 27 09:52:30 PM UTC 24 |
Aug 27 10:04:12 PM UTC 24 |
42046422886 ps |
| T2444 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/62.xbar_access_same_device_slow_rsp.2024904191 |
|
|
Aug 27 09:49:28 PM UTC 24 |
Aug 27 10:04:18 PM UTC 24 |
50083516145 ps |
| T2445 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/75.xbar_random_zero_delays.3639865136 |
|
|
Aug 27 10:03:52 PM UTC 24 |
Aug 27 10:04:19 PM UTC 24 |
265408478 ps |
| T2446 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/74.xbar_smoke_slow_rsp.3406160292 |
|
|
Aug 27 10:02:50 PM UTC 24 |
Aug 27 10:04:23 PM UTC 24 |
4465276868 ps |
| T2447 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/74.xbar_stress_all_with_reset_error.944967660 |
|
|
Aug 27 10:03:31 PM UTC 24 |
Aug 27 10:04:30 PM UTC 24 |
270520193 ps |
| T2448 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/75.xbar_access_same_device.3345757369 |
|
|
Aug 27 10:04:09 PM UTC 24 |
Aug 27 10:04:32 PM UTC 24 |
197774503 ps |
| T2449 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/74.xbar_smoke_large_delays.500573077 |
|
|
Aug 27 10:02:49 PM UTC 24 |
Aug 27 10:04:33 PM UTC 24 |
10995938068 ps |
| T2450 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/74.xbar_error_and_unmapped_addr.3682099620 |
|
|
Aug 27 10:03:24 PM UTC 24 |
Aug 27 10:04:37 PM UTC 24 |
1402730806 ps |
| T2451 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/74.xbar_same_source.940646335 |
|
|
Aug 27 10:03:18 PM UTC 24 |
Aug 27 10:04:39 PM UTC 24 |
2064731587 ps |
| T2452 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/75.xbar_stress_all_with_reset_error.3911474468 |
|
|
Aug 27 10:04:42 PM UTC 24 |
Aug 27 10:04:49 PM UTC 24 |
7229236 ps |
| T2453 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/76.xbar_smoke.1362739694 |
|
|
Aug 27 10:04:45 PM UTC 24 |
Aug 27 10:04:55 PM UTC 24 |
51251970 ps |
| T2454 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/71.xbar_stress_all.4027901689 |
|
|
Aug 27 10:00:35 PM UTC 24 |
Aug 27 10:04:55 PM UTC 24 |
9196963492 ps |
| T2455 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/67.xbar_stress_all_with_rand_reset.1431121492 |
|
|
Aug 27 09:55:31 PM UTC 24 |
Aug 27 10:04:58 PM UTC 24 |
7969930923 ps |
| T2456 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/75.xbar_smoke_large_delays.4107694351 |
|
|
Aug 27 10:03:35 PM UTC 24 |
Aug 27 10:04:59 PM UTC 24 |
7720305809 ps |
| T2457 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/76.xbar_smoke_zero_delays.27329390 |
|
|
Aug 27 10:04:53 PM UTC 24 |
Aug 27 10:05:02 PM UTC 24 |
44636210 ps |
| T2458 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/75.xbar_error_and_unmapped_addr.1935677701 |
|
|
Aug 27 10:04:29 PM UTC 24 |
Aug 27 10:05:04 PM UTC 24 |
1031941048 ps |
| T2459 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/74.xbar_access_same_device.2312342643 |
|
|
Aug 27 10:03:14 PM UTC 24 |
Aug 27 10:05:15 PM UTC 24 |
3112585186 ps |
| T2460 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/75.xbar_same_source.22714426 |
|
|
Aug 27 10:04:18 PM UTC 24 |
Aug 27 10:05:16 PM UTC 24 |
2475850543 ps |
| T859 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/71.xbar_stress_all_with_reset_error.200964330 |
|
|
Aug 27 10:00:48 PM UTC 24 |
Aug 27 10:05:18 PM UTC 24 |
987224776 ps |
| T2461 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/75.xbar_smoke_slow_rsp.2935570550 |
|
|
Aug 27 10:03:48 PM UTC 24 |
Aug 27 10:05:19 PM UTC 24 |
6512811466 ps |
| T2462 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/75.xbar_unmapped_addr.1995762756 |
|
|
Aug 27 10:04:30 PM UTC 24 |
Aug 27 10:05:21 PM UTC 24 |
1421984339 ps |
| T2463 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/76.xbar_random.1120992677 |
|
|
Aug 27 10:04:58 PM UTC 24 |
Aug 27 10:05:24 PM UTC 24 |
234300131 ps |
| T2464 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/76.xbar_random_zero_delays.522745992 |
|
|
Aug 27 10:05:02 PM UTC 24 |
Aug 27 10:05:31 PM UTC 24 |
296198268 ps |
| T2465 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/76.xbar_access_same_device.3087157750 |
|
|
Aug 27 10:05:18 PM UTC 24 |
Aug 27 10:05:32 PM UTC 24 |
110648735 ps |
| T2466 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/75.xbar_error_random.2772987786 |
|
|
Aug 27 10:04:27 PM UTC 24 |
Aug 27 10:05:32 PM UTC 24 |
1916412256 ps |
| T2467 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/73.xbar_stress_all_with_error.3664625550 |
|
|
Aug 27 10:02:41 PM UTC 24 |
Aug 27 10:05:37 PM UTC 24 |
2797423171 ps |
| T2468 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/76.xbar_same_source.766984147 |
|
|
Aug 27 10:05:20 PM UTC 24 |
Aug 27 10:05:39 PM UTC 24 |
190528659 ps |
| T2469 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/77.xbar_smoke.2774689658 |
|
|
Aug 27 10:05:46 PM UTC 24 |
Aug 27 10:05:56 PM UTC 24 |
56442805 ps |
| T2470 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/68.xbar_access_same_device_slow_rsp.4061960596 |
|
|
Aug 27 09:56:29 PM UTC 24 |
Aug 27 10:06:01 PM UTC 24 |
40156394946 ps |
| T2471 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/77.xbar_smoke_zero_delays.2058827243 |
|
|
Aug 27 10:05:54 PM UTC 24 |
Aug 27 10:06:03 PM UTC 24 |
46814572 ps |
| T2472 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/76.xbar_unmapped_addr.1513231764 |
|
|
Aug 27 10:05:26 PM UTC 24 |
Aug 27 10:06:10 PM UTC 24 |
1040336147 ps |
| T2473 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/76.xbar_smoke_large_delays.2456807864 |
|
|
Aug 27 10:04:56 PM UTC 24 |
Aug 27 10:06:10 PM UTC 24 |
7655616492 ps |
| T614 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/73.xbar_stress_all_with_reset_error.3308060127 |
|
|
Aug 27 10:02:44 PM UTC 24 |
Aug 27 10:06:10 PM UTC 24 |
2393660992 ps |
| T2474 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/68.xbar_random_slow_rsp.4246078174 |
|
|
Aug 27 09:56:25 PM UTC 24 |
Aug 27 10:06:13 PM UTC 24 |
32960999093 ps |
| T2475 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/77.xbar_random_zero_delays.3747062814 |
|
|
Aug 27 10:06:02 PM UTC 24 |
Aug 27 10:06:15 PM UTC 24 |
68560870 ps |
| T2476 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/76.xbar_error_and_unmapped_addr.2907780786 |
|
|
Aug 27 10:05:37 PM UTC 24 |
Aug 27 10:06:26 PM UTC 24 |
979374602 ps |
| T2477 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/77.xbar_random.3268548570 |
|
|
Aug 27 10:06:00 PM UTC 24 |
Aug 27 10:06:32 PM UTC 24 |
267871050 ps |
| T2478 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/74.xbar_stress_all_with_error.3426224773 |
|
|
Aug 27 10:03:28 PM UTC 24 |
Aug 27 10:06:43 PM UTC 24 |
2833255722 ps |
| T2479 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/76.xbar_smoke_slow_rsp.556694080 |
|
|
Aug 27 10:04:56 PM UTC 24 |
Aug 27 10:06:54 PM UTC 24 |
5344783017 ps |
| T2480 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/76.xbar_error_random.696479506 |
|
|
Aug 27 10:05:25 PM UTC 24 |
Aug 27 10:06:55 PM UTC 24 |
1942452767 ps |
| T2481 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/64.xbar_random_slow_rsp.3953493883 |
|
|
Aug 27 09:51:25 PM UTC 24 |
Aug 27 10:07:05 PM UTC 24 |
61626509258 ps |
| T2482 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/77.xbar_access_same_device.1930315 |
|
|
Aug 27 10:06:26 PM UTC 24 |
Aug 27 10:07:07 PM UTC 24 |
382479008 ps |
| T2483 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/77.xbar_same_source.3579208447 |
|
|
Aug 27 10:06:33 PM UTC 24 |
Aug 27 10:07:09 PM UTC 24 |
308955935 ps |
| T2484 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/77.xbar_error_and_unmapped_addr.3181779048 |
|
|
Aug 27 10:06:38 PM UTC 24 |
Aug 27 10:07:11 PM UTC 24 |
287310321 ps |
| T2485 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/77.xbar_smoke_slow_rsp.1045672111 |
|
|
Aug 27 10:05:55 PM UTC 24 |
Aug 27 10:07:13 PM UTC 24 |
4259203979 ps |
| T2486 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/77.xbar_smoke_large_delays.23682749 |
|
|
Aug 27 10:05:55 PM UTC 24 |
Aug 27 10:07:21 PM UTC 24 |
8679892484 ps |
| T2487 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/77.xbar_unmapped_addr.3012745464 |
|
|
Aug 27 10:06:36 PM UTC 24 |
Aug 27 10:07:23 PM UTC 24 |
796503447 ps |
| T2488 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/77.xbar_error_random.1176764697 |
|
|
Aug 27 10:06:33 PM UTC 24 |
Aug 27 10:07:28 PM UTC 24 |
1612662710 ps |
| T2489 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/78.xbar_smoke.3308226855 |
|
|
Aug 27 10:07:18 PM UTC 24 |
Aug 27 10:07:29 PM UTC 24 |
49602360 ps |
| T2490 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/66.xbar_random_large_delays.3776748521 |
|
|
Aug 27 09:53:42 PM UTC 24 |
Aug 27 10:07:29 PM UTC 24 |
75947878396 ps |
| T2491 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/63.xbar_access_same_device_slow_rsp.2816707271 |
|
|
Aug 27 09:50:40 PM UTC 24 |
Aug 27 10:07:33 PM UTC 24 |
67091630269 ps |
| T2492 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/70.xbar_stress_all_with_error.563698325 |
|
|
Aug 27 09:59:33 PM UTC 24 |
Aug 27 10:07:37 PM UTC 24 |
12252983405 ps |
| T2493 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/77.xbar_stress_all_with_rand_reset.638209318 |
|
|
Aug 27 10:06:54 PM UTC 24 |
Aug 27 10:07:38 PM UTC 24 |
64596940 ps |
| T2494 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/78.xbar_smoke_zero_delays.838869659 |
|
|
Aug 27 10:07:28 PM UTC 24 |
Aug 27 10:07:38 PM UTC 24 |
47146101 ps |
| T2495 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/66.xbar_access_same_device_slow_rsp.1251285938 |
|
|
Aug 27 09:53:51 PM UTC 24 |
Aug 27 10:07:45 PM UTC 24 |
53870871512 ps |
| T2496 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/76.xbar_stress_all_with_error.1601630625 |
|
|
Aug 27 10:05:41 PM UTC 24 |
Aug 27 10:07:45 PM UTC 24 |
1701163578 ps |
| T2497 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/78.xbar_random_zero_delays.4273920325 |
|
|
Aug 27 10:07:34 PM UTC 24 |
Aug 27 10:07:47 PM UTC 24 |
71807617 ps |
| T2498 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/72.xbar_stress_all.502602823 |
|
|
Aug 27 10:01:35 PM UTC 24 |
Aug 27 10:07:52 PM UTC 24 |
10956064591 ps |
| T2499 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/2.chip_csr_aliasing.25362836 |
|
|
Aug 27 08:08:45 PM UTC 24 |
Aug 27 10:08:02 PM UTC 24 |
39209945976 ps |
| T2500 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/78.xbar_random.988446091 |
|
|
Aug 27 10:07:31 PM UTC 24 |
Aug 27 10:08:08 PM UTC 24 |
968931956 ps |
| T2501 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/78.xbar_unmapped_addr.2538024740 |
|
|
Aug 27 10:07:59 PM UTC 24 |
Aug 27 10:08:08 PM UTC 24 |
41926189 ps |
| T2502 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/77.xbar_stress_all.1447912492 |
|
|
Aug 27 10:06:49 PM UTC 24 |
Aug 27 10:08:11 PM UTC 24 |
2298701018 ps |
| T2503 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/73.xbar_stress_all_with_rand_reset.2978887954 |
|
|
Aug 27 10:02:30 PM UTC 24 |
Aug 27 10:08:13 PM UTC 24 |
830803459 ps |
| T2504 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/74.xbar_stress_all.2829448972 |
|
|
Aug 27 10:03:22 PM UTC 24 |
Aug 27 10:08:14 PM UTC 24 |
7500562501 ps |
| T2505 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/73.xbar_stress_all.1872607108 |
|
|
Aug 27 10:02:29 PM UTC 24 |
Aug 27 10:08:21 PM UTC 24 |
4751469055 ps |
| T2506 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/72.xbar_random_slow_rsp.1420340103 |
|
|
Aug 27 10:01:12 PM UTC 24 |
Aug 27 10:08:21 PM UTC 24 |
27962158752 ps |
| T2507 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/78.xbar_error_random.3677877112 |
|
|
Aug 27 10:07:51 PM UTC 24 |
Aug 27 10:08:22 PM UTC 24 |
348790758 ps |
| T2508 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/75.xbar_stress_all_with_error.1260507222 |
|
|
Aug 27 10:04:40 PM UTC 24 |
Aug 27 10:08:26 PM UTC 24 |
2834572143 ps |
| T2509 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/79.xbar_smoke.4115402682 |
|
|
Aug 27 10:08:14 PM UTC 24 |
Aug 27 10:08:28 PM UTC 24 |
203570957 ps |
| T2510 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/79.xbar_smoke_zero_delays.3108784644 |
|
|
Aug 27 10:08:25 PM UTC 24 |
Aug 27 10:08:35 PM UTC 24 |
48312657 ps |
| T2511 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/51.xbar_access_same_device_slow_rsp.3149762886 |
|
|
Aug 27 09:37:27 PM UTC 24 |
Aug 27 10:08:36 PM UTC 24 |
120486487091 ps |
| T2512 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/78.xbar_error_and_unmapped_addr.198018982 |
|
|
Aug 27 10:07:59 PM UTC 24 |
Aug 27 10:08:39 PM UTC 24 |
980603866 ps |
| T2513 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/78.xbar_smoke_large_delays.3990931668 |
|
|
Aug 27 10:07:28 PM UTC 24 |
Aug 27 10:08:44 PM UTC 24 |
6032682750 ps |