| T1576 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/23.xbar_smoke_slow_rsp.1412069710 |
|
|
Aug 27 08:56:18 PM UTC 24 |
Aug 27 08:57:59 PM UTC 24 |
5698787386 ps |
| T1577 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/23.xbar_same_source.2275846875 |
|
|
Aug 27 08:56:28 PM UTC 24 |
Aug 27 08:58:00 PM UTC 24 |
2500146110 ps |
| T822 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/20.xbar_stress_all.4039710321 |
|
|
Aug 27 08:50:58 PM UTC 24 |
Aug 27 08:58:13 PM UTC 24 |
11629003113 ps |
| T1578 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/23.xbar_stress_all.3393908554 |
|
|
Aug 27 08:57:03 PM UTC 24 |
Aug 27 08:58:20 PM UTC 24 |
2272717175 ps |
| T1579 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/24.xbar_error_random.3100978121 |
|
|
Aug 27 08:58:17 PM UTC 24 |
Aug 27 08:58:37 PM UTC 24 |
150445862 ps |
| T1580 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/24.xbar_unmapped_addr.104301957 |
|
|
Aug 27 08:58:22 PM UTC 24 |
Aug 27 08:58:38 PM UTC 24 |
62756892 ps |
| T1581 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/14.chip_same_csr_outstanding.1566419214 |
|
|
Aug 27 08:32:55 PM UTC 24 |
Aug 27 08:58:42 PM UTC 24 |
13992089928 ps |
| T1582 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/24.xbar_random.1057950546 |
|
|
Aug 27 08:57:48 PM UTC 24 |
Aug 27 08:58:46 PM UTC 24 |
439269065 ps |
| T1583 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/24.xbar_error_and_unmapped_addr.837040827 |
|
|
Aug 27 08:58:34 PM UTC 24 |
Aug 27 08:58:49 PM UTC 24 |
80115383 ps |
| T1584 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/24.xbar_random_zero_delays.4261658951 |
|
|
Aug 27 08:57:58 PM UTC 24 |
Aug 27 08:58:50 PM UTC 24 |
476896120 ps |
| T1585 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/24.xbar_same_source.649763714 |
|
|
Aug 27 08:58:11 PM UTC 24 |
Aug 27 08:58:57 PM UTC 24 |
1203414829 ps |
| T1586 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/24.xbar_smoke_large_delays.4078694690 |
|
|
Aug 27 08:57:37 PM UTC 24 |
Aug 27 08:59:03 PM UTC 24 |
8317586325 ps |
| T1587 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/23.xbar_stress_all_with_error.4077375094 |
|
|
Aug 27 08:57:16 PM UTC 24 |
Aug 27 08:59:12 PM UTC 24 |
1530620928 ps |
| T1588 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/24.xbar_access_same_device.1435446237 |
|
|
Aug 27 08:58:03 PM UTC 24 |
Aug 27 08:59:16 PM UTC 24 |
986187780 ps |
| T1589 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/24.chip_tl_errors.1939179845 |
|
|
Aug 27 08:57:24 PM UTC 24 |
Aug 27 08:59:22 PM UTC 24 |
2685276648 ps |
| T1590 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/25.xbar_smoke_zero_delays.2216055446 |
|
|
Aug 27 08:59:13 PM UTC 24 |
Aug 27 08:59:23 PM UTC 24 |
52828195 ps |
| T1591 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/24.xbar_smoke_slow_rsp.4011696454 |
|
|
Aug 27 08:57:42 PM UTC 24 |
Aug 27 08:59:26 PM UTC 24 |
4351684623 ps |
| T1592 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/25.xbar_smoke.2259082799 |
|
|
Aug 27 08:59:12 PM UTC 24 |
Aug 27 08:59:27 PM UTC 24 |
240787873 ps |
| T1593 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/24.xbar_stress_all_with_reset_error.1634213702 |
|
|
Aug 27 08:59:03 PM UTC 24 |
Aug 27 08:59:31 PM UTC 24 |
70082421 ps |
| T1594 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/18.chip_csr_mem_rw_with_rand_reset.691766374 |
|
|
Aug 27 08:45:29 PM UTC 24 |
Aug 27 08:59:45 PM UTC 24 |
10035201830 ps |
| T655 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/21.chip_tl_errors.1092168049 |
|
|
Aug 27 08:51:22 PM UTC 24 |
Aug 27 08:59:46 PM UTC 24 |
4732530195 ps |
| T1595 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/25.xbar_random.77854253 |
|
|
Aug 27 08:59:33 PM UTC 24 |
Aug 27 08:59:47 PM UTC 24 |
80843991 ps |
| T808 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/16.xbar_access_same_device_slow_rsp.2061242990 |
|
|
Aug 27 08:40:00 PM UTC 24 |
Aug 27 08:59:54 PM UTC 24 |
88105822980 ps |
| T1596 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/25.xbar_random_zero_delays.1693546748 |
|
|
Aug 27 08:59:38 PM UTC 24 |
Aug 27 08:59:55 PM UTC 24 |
90830116 ps |
| T1597 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/23.chip_tl_errors.2375056221 |
|
|
Aug 27 08:55:52 PM UTC 24 |
Aug 27 09:00:01 PM UTC 24 |
3905468080 ps |
| T1598 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/20.xbar_random_large_delays.2255363544 |
|
|
Aug 27 08:49:41 PM UTC 24 |
Aug 27 09:00:07 PM UTC 24 |
45877784457 ps |
| T1599 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/25.xbar_same_source.2235073089 |
|
|
Aug 27 08:59:51 PM UTC 24 |
Aug 27 09:00:12 PM UTC 24 |
169215420 ps |
| T1600 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/19.chip_csr_rw.3569220569 |
|
|
Aug 27 08:48:49 PM UTC 24 |
Aug 27 09:00:12 PM UTC 24 |
5868471542 ps |
| T1601 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/24.xbar_stress_all_with_error.3532818864 |
|
|
Aug 27 08:58:59 PM UTC 24 |
Aug 27 09:00:18 PM UTC 24 |
880630930 ps |
| T1602 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/23.xbar_random_slow_rsp.2061584126 |
|
|
Aug 27 08:56:26 PM UTC 24 |
Aug 27 09:00:25 PM UTC 24 |
14736710503 ps |
| T1603 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/25.xbar_unmapped_addr.2902016041 |
|
|
Aug 27 09:00:07 PM UTC 24 |
Aug 27 09:00:40 PM UTC 24 |
779731533 ps |
| T1604 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/26.xbar_smoke.4042038034 |
|
|
Aug 27 09:00:34 PM UTC 24 |
Aug 27 09:00:47 PM UTC 24 |
146090218 ps |
| T1605 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/25.xbar_smoke_large_delays.1960593876 |
|
|
Aug 27 08:59:20 PM UTC 24 |
Aug 27 09:00:46 PM UTC 24 |
8879094948 ps |
| T1606 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/22.xbar_stress_all_with_error.534685669 |
|
|
Aug 27 08:55:43 PM UTC 24 |
Aug 27 09:00:48 PM UTC 24 |
4060809179 ps |
| T1607 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/26.xbar_smoke_zero_delays.2946348849 |
|
|
Aug 27 09:00:41 PM UTC 24 |
Aug 27 09:00:49 PM UTC 24 |
40566424 ps |
| T815 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/25.xbar_access_same_device.2610135125 |
|
|
Aug 27 08:59:47 PM UTC 24 |
Aug 27 09:00:51 PM UTC 24 |
1609457642 ps |
| T1608 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/25.xbar_smoke_slow_rsp.852424417 |
|
|
Aug 27 08:59:26 PM UTC 24 |
Aug 27 09:00:59 PM UTC 24 |
4693658554 ps |
| T1609 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/25.xbar_error_and_unmapped_addr.2971521567 |
|
|
Aug 27 09:00:09 PM UTC 24 |
Aug 27 09:01:09 PM UTC 24 |
1057975407 ps |
| T499 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/24.xbar_stress_all.81644993 |
|
|
Aug 27 08:58:43 PM UTC 24 |
Aug 27 09:01:10 PM UTC 24 |
1552566800 ps |
| T1610 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/25.xbar_error_random.1506508925 |
|
|
Aug 27 09:00:05 PM UTC 24 |
Aug 27 09:01:20 PM UTC 24 |
1961940790 ps |
| T1611 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/24.xbar_random_slow_rsp.3053918145 |
|
|
Aug 27 08:58:01 PM UTC 24 |
Aug 27 09:01:29 PM UTC 24 |
11230193305 ps |
| T817 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/11.xbar_access_same_device_slow_rsp.3724484150 |
|
|
Aug 27 08:27:58 PM UTC 24 |
Aug 27 09:01:32 PM UTC 24 |
137875950640 ps |
| T837 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/26.xbar_access_same_device.3202415502 |
|
|
Aug 27 09:01:10 PM UTC 24 |
Aug 27 09:01:33 PM UTC 24 |
451165440 ps |
| T518 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/26.xbar_random_zero_delays.3596664487 |
|
|
Aug 27 09:01:09 PM UTC 24 |
Aug 27 09:01:38 PM UTC 24 |
339679964 ps |
| T1612 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/4.chip_csr_bit_bash.699172515 |
|
|
Aug 27 08:12:21 PM UTC 24 |
Aug 27 09:01:43 PM UTC 24 |
31860770696 ps |
| T1613 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/25.xbar_stress_all.2233137947 |
|
|
Aug 27 09:00:15 PM UTC 24 |
Aug 27 09:01:48 PM UTC 24 |
2278760859 ps |
| T1614 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/26.xbar_random_large_delays.3049808829 |
|
|
Aug 27 09:01:10 PM UTC 24 |
Aug 27 09:01:48 PM UTC 24 |
4186842288 ps |
| T1615 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/18.xbar_random_slow_rsp.3764021987 |
|
|
Aug 27 08:44:28 PM UTC 24 |
Aug 27 09:01:53 PM UTC 24 |
62371478825 ps |
| T1616 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/26.xbar_same_source.2418863979 |
|
|
Aug 27 09:01:31 PM UTC 24 |
Aug 27 09:01:56 PM UTC 24 |
324244162 ps |
| T1617 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/26.xbar_unmapped_addr.343097131 |
|
|
Aug 27 09:01:43 PM UTC 24 |
Aug 27 09:01:57 PM UTC 24 |
247584142 ps |
| T1618 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/21.xbar_random_slow_rsp.3036167644 |
|
|
Aug 27 08:51:58 PM UTC 24 |
Aug 27 09:02:01 PM UTC 24 |
29909246594 ps |
| T1619 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/25.xbar_stress_all_with_error.1822592833 |
|
|
Aug 27 09:00:23 PM UTC 24 |
Aug 27 09:02:01 PM UTC 24 |
1920313576 ps |
| T495 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/22.xbar_stress_all.1618557201 |
|
|
Aug 27 08:55:38 PM UTC 24 |
Aug 27 09:02:03 PM UTC 24 |
10042034402 ps |
| T500 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/26.xbar_random.1106390485 |
|
|
Aug 27 09:01:10 PM UTC 24 |
Aug 27 09:02:12 PM UTC 24 |
1668955389 ps |
| T1620 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/23.xbar_stress_all_with_reset_error.3011530943 |
|
|
Aug 27 08:57:22 PM UTC 24 |
Aug 27 09:02:14 PM UTC 24 |
6579308024 ps |
| T1621 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/27.xbar_smoke.630625201 |
|
|
Aug 27 09:02:11 PM UTC 24 |
Aug 27 09:02:18 PM UTC 24 |
41724926 ps |
| T1622 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/26.xbar_error_and_unmapped_addr.2338897478 |
|
|
Aug 27 09:01:52 PM UTC 24 |
Aug 27 09:02:18 PM UTC 24 |
202059865 ps |
| T656 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/25.chip_tl_errors.3570702721 |
|
|
Aug 27 08:59:08 PM UTC 24 |
Aug 27 09:02:19 PM UTC 24 |
3271586856 ps |
| T1623 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/27.xbar_smoke_zero_delays.1430010366 |
|
|
Aug 27 09:02:15 PM UTC 24 |
Aug 27 09:02:22 PM UTC 24 |
43834871 ps |
| T525 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/24.xbar_stress_all_with_rand_reset.3084854617 |
|
|
Aug 27 08:59:01 PM UTC 24 |
Aug 27 09:02:36 PM UTC 24 |
1691768442 ps |
| T1624 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/26.xbar_smoke_large_delays.3275300647 |
|
|
Aug 27 09:00:48 PM UTC 24 |
Aug 27 09:02:44 PM UTC 24 |
8402002312 ps |
| T1625 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/25.xbar_random_slow_rsp.3804667385 |
|
|
Aug 27 08:59:46 PM UTC 24 |
Aug 27 09:02:50 PM UTC 24 |
10061741046 ps |
| T1626 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/27.xbar_random.48375195 |
|
|
Aug 27 09:02:23 PM UTC 24 |
Aug 27 09:02:51 PM UTC 24 |
499895367 ps |
| T879 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/26.xbar_stress_all_with_rand_reset.1395431480 |
|
|
Aug 27 09:01:56 PM UTC 24 |
Aug 27 09:02:51 PM UTC 24 |
81925284 ps |
| T1627 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/26.xbar_smoke_slow_rsp.1804598054 |
|
|
Aug 27 09:01:00 PM UTC 24 |
Aug 27 09:02:52 PM UTC 24 |
4646421962 ps |
| T809 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/14.xbar_access_same_device_slow_rsp.600250279 |
|
|
Aug 27 08:34:48 PM UTC 24 |
Aug 27 09:02:54 PM UTC 24 |
108747157482 ps |
| T1628 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/26.xbar_error_random.2751462665 |
|
|
Aug 27 09:01:32 PM UTC 24 |
Aug 27 09:03:05 PM UTC 24 |
2283412754 ps |
| T1629 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/27.xbar_random_zero_delays.1183715565 |
|
|
Aug 27 09:02:22 PM UTC 24 |
Aug 27 09:03:11 PM UTC 24 |
485855383 ps |
| T1630 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/27.xbar_unmapped_addr.1303947872 |
|
|
Aug 27 09:02:45 PM UTC 24 |
Aug 27 09:03:14 PM UTC 24 |
537565409 ps |
| T1631 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/28.xbar_smoke.1460185557 |
|
|
Aug 27 09:03:16 PM UTC 24 |
Aug 27 09:03:30 PM UTC 24 |
192476721 ps |
| T1632 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/18.xbar_random_large_delays.122666604 |
|
|
Aug 27 08:44:08 PM UTC 24 |
Aug 27 09:03:33 PM UTC 24 |
110587664638 ps |
| T1633 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/28.xbar_smoke_zero_delays.2706653839 |
|
|
Aug 27 09:03:27 PM UTC 24 |
Aug 27 09:03:36 PM UTC 24 |
44886179 ps |
| T1634 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/27.xbar_error_and_unmapped_addr.1213762651 |
|
|
Aug 27 09:03:00 PM UTC 24 |
Aug 27 09:03:43 PM UTC 24 |
1038136751 ps |
| T1635 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/27.xbar_smoke_large_delays.812764242 |
|
|
Aug 27 09:02:20 PM UTC 24 |
Aug 27 09:03:45 PM UTC 24 |
7311310414 ps |
| T1636 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/26.chip_tl_errors.493114601 |
|
|
Aug 27 09:00:35 PM UTC 24 |
Aug 27 09:03:45 PM UTC 24 |
3229415380 ps |
| T1637 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/26.xbar_stress_all.2775029105 |
|
|
Aug 27 09:01:55 PM UTC 24 |
Aug 27 09:03:48 PM UTC 24 |
3375919899 ps |
| T1638 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/27.xbar_access_same_device.4256563091 |
|
|
Aug 27 09:02:38 PM UTC 24 |
Aug 27 09:03:54 PM UTC 24 |
739099397 ps |
| T1639 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/27.xbar_error_random.4067758674 |
|
|
Aug 27 09:02:39 PM UTC 24 |
Aug 27 09:03:57 PM UTC 24 |
2179471624 ps |
| T1640 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/28.xbar_random.1024110211 |
|
|
Aug 27 09:03:50 PM UTC 24 |
Aug 27 09:04:02 PM UTC 24 |
244947618 ps |
| T865 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/25.xbar_stress_all_with_reset_error.2234584546 |
|
|
Aug 27 09:00:29 PM UTC 24 |
Aug 27 09:04:08 PM UTC 24 |
767500177 ps |
| T1641 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/20.xbar_random_slow_rsp.3865855104 |
|
|
Aug 27 08:49:54 PM UTC 24 |
Aug 27 09:04:09 PM UTC 24 |
45190352347 ps |
| T1642 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/27.xbar_same_source.120782315 |
|
|
Aug 27 09:02:41 PM UTC 24 |
Aug 27 09:04:15 PM UTC 24 |
2303396367 ps |
| T1643 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/28.xbar_random_zero_delays.3268202864 |
|
|
Aug 27 09:03:55 PM UTC 24 |
Aug 27 09:04:22 PM UTC 24 |
205698023 ps |
| T1644 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/28.xbar_unmapped_addr.1037624696 |
|
|
Aug 27 09:04:18 PM UTC 24 |
Aug 27 09:04:35 PM UTC 24 |
206137826 ps |
| T1645 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/28.xbar_error_and_unmapped_addr.2288683688 |
|
|
Aug 27 09:04:24 PM UTC 24 |
Aug 27 09:04:56 PM UTC 24 |
225491739 ps |
| T1646 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/27.xbar_stress_all.1621756385 |
|
|
Aug 27 09:03:07 PM UTC 24 |
Aug 27 09:05:01 PM UTC 24 |
3381375647 ps |
| T1647 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/28.xbar_smoke_slow_rsp.733707870 |
|
|
Aug 27 09:03:35 PM UTC 24 |
Aug 27 09:05:07 PM UTC 24 |
4759061005 ps |
| T1648 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/27.xbar_smoke_slow_rsp.2377861334 |
|
|
Aug 27 09:02:20 PM UTC 24 |
Aug 27 09:05:09 PM UTC 24 |
7615131586 ps |
| T1649 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/28.xbar_smoke_large_delays.3784770027 |
|
|
Aug 27 09:03:33 PM UTC 24 |
Aug 27 09:05:25 PM UTC 24 |
8043726273 ps |
| T1650 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/29.xbar_smoke.463951993 |
|
|
Aug 27 09:05:19 PM UTC 24 |
Aug 27 09:05:28 PM UTC 24 |
36394002 ps |
| T1651 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/28.xbar_error_random.944964851 |
|
|
Aug 27 09:04:14 PM UTC 24 |
Aug 27 09:05:28 PM UTC 24 |
2145305570 ps |
| T1652 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/29.xbar_smoke_zero_delays.2289564457 |
|
|
Aug 27 09:05:22 PM UTC 24 |
Aug 27 09:05:32 PM UTC 24 |
46543382 ps |
| T1653 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/27.chip_tl_errors.1545300558 |
|
|
Aug 27 09:02:09 PM UTC 24 |
Aug 27 09:05:33 PM UTC 24 |
3292948178 ps |
| T1654 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/28.xbar_same_source.2675433310 |
|
|
Aug 27 09:04:10 PM UTC 24 |
Aug 27 09:05:41 PM UTC 24 |
2332289120 ps |
| T498 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/28.xbar_access_same_device.4249661214 |
|
|
Aug 27 09:04:07 PM UTC 24 |
Aug 27 09:05:52 PM UTC 24 |
1353268002 ps |
| T1655 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/27.xbar_stress_all_with_error.1667846247 |
|
|
Aug 27 09:03:13 PM UTC 24 |
Aug 27 09:05:54 PM UTC 24 |
4518543156 ps |
| T1656 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/28.xbar_stress_all_with_reset_error.2344736284 |
|
|
Aug 27 09:04:44 PM UTC 24 |
Aug 27 09:06:00 PM UTC 24 |
181599171 ps |
| T1657 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/29.xbar_random_zero_delays.1658257490 |
|
|
Aug 27 09:05:49 PM UTC 24 |
Aug 27 09:06:05 PM UTC 24 |
88309541 ps |
| T867 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/23.xbar_stress_all_with_rand_reset.408308953 |
|
|
Aug 27 08:57:05 PM UTC 24 |
Aug 27 09:06:05 PM UTC 24 |
7423416145 ps |
| T864 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/26.xbar_stress_all_with_reset_error.2346261454 |
|
|
Aug 27 09:02:03 PM UTC 24 |
Aug 27 09:06:19 PM UTC 24 |
2184426077 ps |
| T1658 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/25.xbar_stress_all_with_rand_reset.3273254037 |
|
|
Aug 27 09:00:16 PM UTC 24 |
Aug 27 09:06:19 PM UTC 24 |
2495297116 ps |
| T524 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/27.xbar_stress_all_with_rand_reset.2689321193 |
|
|
Aug 27 09:03:12 PM UTC 24 |
Aug 27 09:06:28 PM UTC 24 |
2665261122 ps |
| T1659 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/29.xbar_same_source.3243726711 |
|
|
Aug 27 09:06:15 PM UTC 24 |
Aug 27 09:06:30 PM UTC 24 |
249338906 ps |
| T1660 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/29.xbar_error_random.2333428858 |
|
|
Aug 27 09:06:17 PM UTC 24 |
Aug 27 09:06:46 PM UTC 24 |
339946666 ps |
| T1661 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/24.xbar_random_large_delays.1722276665 |
|
|
Aug 27 08:57:57 PM UTC 24 |
Aug 27 09:06:47 PM UTC 24 |
53921727665 ps |
| T1662 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/29.xbar_random.2981242622 |
|
|
Aug 27 09:05:48 PM UTC 24 |
Aug 27 09:06:49 PM UTC 24 |
1426353962 ps |
| T1663 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/29.xbar_access_same_device.2297650150 |
|
|
Aug 27 09:05:56 PM UTC 24 |
Aug 27 09:06:59 PM UTC 24 |
465398564 ps |
| T1664 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/30.xbar_smoke.320498322 |
|
|
Aug 27 09:06:53 PM UTC 24 |
Aug 27 09:07:02 PM UTC 24 |
46424543 ps |
| T1665 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/29.xbar_smoke_slow_rsp.1595535560 |
|
|
Aug 27 09:05:31 PM UTC 24 |
Aug 27 09:07:03 PM UTC 24 |
6133213486 ps |
| T1666 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/29.xbar_unmapped_addr.1426039678 |
|
|
Aug 27 09:06:24 PM UTC 24 |
Aug 27 09:07:04 PM UTC 24 |
678431707 ps |
| T503 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/29.xbar_smoke_large_delays.2962841084 |
|
|
Aug 27 09:05:29 PM UTC 24 |
Aug 27 09:07:11 PM UTC 24 |
7860813290 ps |
| T1667 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/30.xbar_smoke_zero_delays.3829305432 |
|
|
Aug 27 09:07:07 PM UTC 24 |
Aug 27 09:07:14 PM UTC 24 |
46880194 ps |
| T1668 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/30.xbar_random.4087403956 |
|
|
Aug 27 09:07:21 PM UTC 24 |
Aug 27 09:07:41 PM UTC 24 |
300035007 ps |
| T1669 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/22.xbar_random_slow_rsp.4218627771 |
|
|
Aug 27 08:54:37 PM UTC 24 |
Aug 27 09:07:47 PM UTC 24 |
55590340002 ps |
| T1670 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/29.xbar_error_and_unmapped_addr.4223769482 |
|
|
Aug 27 09:06:27 PM UTC 24 |
Aug 27 09:07:48 PM UTC 24 |
1471302937 ps |
| T408 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/12.chip_same_csr_outstanding.70713701 |
|
|
Aug 27 08:29:16 PM UTC 24 |
Aug 27 09:08:01 PM UTC 24 |
18127598590 ps |
| T1671 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/30.xbar_same_source.2900893578 |
|
|
Aug 27 09:08:04 PM UTC 24 |
Aug 27 09:08:21 PM UTC 24 |
262828920 ps |
| T1672 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/30.xbar_random_zero_delays.2886711278 |
|
|
Aug 27 09:07:22 PM UTC 24 |
Aug 27 09:08:36 PM UTC 24 |
598117525 ps |
| T1673 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/29.xbar_stress_all_with_error.3596606568 |
|
|
Aug 27 09:06:42 PM UTC 24 |
Aug 27 09:08:37 PM UTC 24 |
1766229733 ps |
| T1674 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/30.xbar_error_and_unmapped_addr.2715680800 |
|
|
Aug 27 09:08:24 PM UTC 24 |
Aug 27 09:08:44 PM UTC 24 |
301558768 ps |
| T1675 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/30.xbar_smoke_slow_rsp.3368930015 |
|
|
Aug 27 09:07:12 PM UTC 24 |
Aug 27 09:08:48 PM UTC 24 |
4383745708 ps |
| T1676 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/30.xbar_smoke_large_delays.2914603299 |
|
|
Aug 27 09:07:10 PM UTC 24 |
Aug 27 09:08:51 PM UTC 24 |
6549729785 ps |
| T642 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/29.chip_tl_errors.3859540940 |
|
|
Aug 27 09:04:58 PM UTC 24 |
Aug 27 09:09:03 PM UTC 24 |
3606360529 ps |
| T1677 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/31.xbar_smoke.2660692214 |
|
|
Aug 27 09:09:11 PM UTC 24 |
Aug 27 09:09:23 PM UTC 24 |
255024318 ps |
| T1678 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/30.xbar_access_same_device.3364215915 |
|
|
Aug 27 09:07:32 PM UTC 24 |
Aug 27 09:09:23 PM UTC 24 |
2601850909 ps |
| T1679 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/31.xbar_smoke_zero_delays.999904199 |
|
|
Aug 27 09:09:13 PM UTC 24 |
Aug 27 09:09:24 PM UTC 24 |
51752461 ps |
| T1680 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/30.xbar_unmapped_addr.2924705470 |
|
|
Aug 27 09:08:11 PM UTC 24 |
Aug 27 09:09:34 PM UTC 24 |
1309295588 ps |
| T1681 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/15.chip_same_csr_outstanding.589564224 |
|
|
Aug 27 08:36:00 PM UTC 24 |
Aug 27 09:09:36 PM UTC 24 |
15734188322 ps |
| T1682 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/28.xbar_stress_all_with_error.4231107190 |
|
|
Aug 27 09:04:38 PM UTC 24 |
Aug 27 09:09:42 PM UTC 24 |
9003881194 ps |
| T1683 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/30.xbar_error_random.334587166 |
|
|
Aug 27 09:08:10 PM UTC 24 |
Aug 27 09:09:51 PM UTC 24 |
2451057540 ps |
| T536 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/31.xbar_random.2987389738 |
|
|
Aug 27 09:09:46 PM UTC 24 |
Aug 27 09:09:57 PM UTC 24 |
79859932 ps |
| T501 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/30.xbar_stress_all.1187799804 |
|
|
Aug 27 09:08:43 PM UTC 24 |
Aug 27 09:09:58 PM UTC 24 |
913484609 ps |
| T830 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/26.xbar_stress_all_with_error.3977362693 |
|
|
Aug 27 09:02:00 PM UTC 24 |
Aug 27 09:09:58 PM UTC 24 |
12800390061 ps |
| T1684 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/31.xbar_random_zero_delays.776253664 |
|
|
Aug 27 09:09:48 PM UTC 24 |
Aug 27 09:09:59 PM UTC 24 |
50875021 ps |
| T489 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/23.xbar_random_large_delays.2897412591 |
|
|
Aug 27 08:56:29 PM UTC 24 |
Aug 27 09:10:10 PM UTC 24 |
79041429039 ps |
| T1685 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/31.xbar_smoke_slow_rsp.4006331814 |
|
|
Aug 27 09:09:44 PM UTC 24 |
Aug 27 09:10:34 PM UTC 24 |
3164941287 ps |
| T1686 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/22.xbar_random_large_delays.376221353 |
|
|
Aug 27 08:54:27 PM UTC 24 |
Aug 27 09:10:36 PM UTC 24 |
90251228440 ps |
| T1687 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/30.xbar_random_slow_rsp.923059801 |
|
|
Aug 27 09:07:22 PM UTC 24 |
Aug 27 09:10:39 PM UTC 24 |
10325063570 ps |
| T1688 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/31.xbar_unmapped_addr.2510388784 |
|
|
Aug 27 09:10:21 PM UTC 24 |
Aug 27 09:10:55 PM UTC 24 |
227593874 ps |
| T1689 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/31.xbar_error_and_unmapped_addr.3080670384 |
|
|
Aug 27 09:10:23 PM UTC 24 |
Aug 27 09:11:02 PM UTC 24 |
772584936 ps |
| T1690 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/29.xbar_stress_all_with_rand_reset.2659511225 |
|
|
Aug 27 09:06:42 PM UTC 24 |
Aug 27 09:11:04 PM UTC 24 |
507970992 ps |
| T1691 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/31.xbar_smoke_large_delays.804690316 |
|
|
Aug 27 09:09:24 PM UTC 24 |
Aug 27 09:11:07 PM UTC 24 |
9330167840 ps |
| T1692 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/31.xbar_same_source.705706620 |
|
|
Aug 27 09:10:20 PM UTC 24 |
Aug 27 09:11:14 PM UTC 24 |
1857445484 ps |
| T1693 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/27.xbar_random_slow_rsp.3729605955 |
|
|
Aug 27 09:02:34 PM UTC 24 |
Aug 27 09:11:15 PM UTC 24 |
35157837015 ps |
| T1694 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/28.xbar_stress_all_with_rand_reset.1136775062 |
|
|
Aug 27 09:04:31 PM UTC 24 |
Aug 27 09:11:19 PM UTC 24 |
2110418544 ps |
| T1695 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/28.chip_tl_errors.2942234177 |
|
|
Aug 27 09:03:13 PM UTC 24 |
Aug 27 09:11:20 PM UTC 24 |
4649272170 ps |
| T1696 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/32.xbar_smoke.4157417696 |
|
|
Aug 27 09:11:18 PM UTC 24 |
Aug 27 09:11:27 PM UTC 24 |
40530687 ps |
| T1697 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/31.xbar_access_same_device.472609116 |
|
|
Aug 27 09:10:05 PM UTC 24 |
Aug 27 09:11:30 PM UTC 24 |
2334743979 ps |
| T1698 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/31.xbar_error_random.2830232930 |
|
|
Aug 27 09:10:20 PM UTC 24 |
Aug 27 09:11:31 PM UTC 24 |
1633237345 ps |
| T1699 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/32.xbar_smoke_zero_delays.1324524646 |
|
|
Aug 27 09:11:25 PM UTC 24 |
Aug 27 09:11:33 PM UTC 24 |
49492960 ps |
| T878 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/30.xbar_stress_all_with_rand_reset.3194578826 |
|
|
Aug 27 09:08:59 PM UTC 24 |
Aug 27 09:11:35 PM UTC 24 |
1591695629 ps |
| T1700 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/30.xbar_stress_all_with_reset_error.2622441858 |
|
|
Aug 27 09:09:06 PM UTC 24 |
Aug 27 09:11:36 PM UTC 24 |
359416558 ps |
| T1701 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/18.chip_same_csr_outstanding.110282131 |
|
|
Aug 27 08:43:11 PM UTC 24 |
Aug 27 09:11:40 PM UTC 24 |
14495475918 ps |
| T1702 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/29.xbar_random_large_delays.1901552157 |
|
|
Aug 27 09:05:51 PM UTC 24 |
Aug 27 09:11:42 PM UTC 24 |
34861934471 ps |
| T1703 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/28.xbar_random_large_delays.1593484644 |
|
|
Aug 27 09:03:58 PM UTC 24 |
Aug 27 09:11:46 PM UTC 24 |
51897371201 ps |
| T1704 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/29.xbar_stress_all.899634176 |
|
|
Aug 27 09:06:28 PM UTC 24 |
Aug 27 09:11:52 PM UTC 24 |
10018560255 ps |
| T1705 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/32.xbar_random_zero_delays.4233873179 |
|
|
Aug 27 09:11:35 PM UTC 24 |
Aug 27 09:11:52 PM UTC 24 |
126135957 ps |
| T1706 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/32.xbar_random.989499347 |
|
|
Aug 27 09:11:32 PM UTC 24 |
Aug 27 09:12:04 PM UTC 24 |
309748117 ps |
| T1707 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/32.xbar_unmapped_addr.2144158467 |
|
|
Aug 27 09:11:56 PM UTC 24 |
Aug 27 09:12:16 PM UTC 24 |
244629241 ps |
| T1708 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/31.xbar_stress_all_with_error.712695959 |
|
|
Aug 27 09:10:58 PM UTC 24 |
Aug 27 09:12:18 PM UTC 24 |
2595732993 ps |
| T1709 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/32.xbar_stress_all_with_reset_error.3581668723 |
|
|
Aug 27 09:12:14 PM UTC 24 |
Aug 27 09:12:21 PM UTC 24 |
7746587 ps |
| T1710 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/33.xbar_smoke.2576177384 |
|
|
Aug 27 09:12:15 PM UTC 24 |
Aug 27 09:12:27 PM UTC 24 |
157308994 ps |
| T1711 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/30.xbar_stress_all_with_error.1686873236 |
|
|
Aug 27 09:08:59 PM UTC 24 |
Aug 27 09:12:30 PM UTC 24 |
6685117068 ps |
| T1712 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/32.xbar_same_source.1661757856 |
|
|
Aug 27 09:11:53 PM UTC 24 |
Aug 27 09:12:34 PM UTC 24 |
1476985495 ps |
| T1713 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/33.xbar_smoke_zero_delays.3815651333 |
|
|
Aug 27 09:12:25 PM UTC 24 |
Aug 27 09:12:35 PM UTC 24 |
41683250 ps |
| T1714 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/32.xbar_error_and_unmapped_addr.3659842056 |
|
|
Aug 27 09:11:57 PM UTC 24 |
Aug 27 09:12:35 PM UTC 24 |
303334024 ps |
| T1715 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/29.xbar_stress_all_with_reset_error.3434025833 |
|
|
Aug 27 09:06:51 PM UTC 24 |
Aug 27 09:12:41 PM UTC 24 |
1989519471 ps |
| T1716 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/27.xbar_stress_all_with_reset_error.593594117 |
|
|
Aug 27 09:03:14 PM UTC 24 |
Aug 27 09:12:44 PM UTC 24 |
4663106969 ps |
| T409 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/17.chip_same_csr_outstanding.4207044581 |
|
|
Aug 27 08:40:59 PM UTC 24 |
Aug 27 09:12:47 PM UTC 24 |
17365120441 ps |
| T1717 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/33.xbar_random_zero_delays.2681697171 |
|
|
Aug 27 09:12:50 PM UTC 24 |
Aug 27 09:12:57 PM UTC 24 |
35122490 ps |
| T1718 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/32.xbar_smoke_large_delays.3784394331 |
|
|
Aug 27 09:11:26 PM UTC 24 |
Aug 27 09:13:06 PM UTC 24 |
7390660020 ps |
| T1719 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/32.xbar_smoke_slow_rsp.4100683906 |
|
|
Aug 27 09:11:30 PM UTC 24 |
Aug 27 09:13:14 PM UTC 24 |
6040651295 ps |
| T1720 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/32.xbar_stress_all.3734078599 |
|
|
Aug 27 09:12:02 PM UTC 24 |
Aug 27 09:13:15 PM UTC 24 |
1203175414 ps |
| T410 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/8.chip_same_csr_outstanding.496981984 |
|
|
Aug 27 08:20:02 PM UTC 24 |
Aug 27 09:13:18 PM UTC 24 |
27828262423 ps |
| T1721 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/32.xbar_error_random.968456789 |
|
|
Aug 27 09:11:56 PM UTC 24 |
Aug 27 09:13:20 PM UTC 24 |
2210746181 ps |
| T1722 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/32.xbar_access_same_device.241608380 |
|
|
Aug 27 09:11:48 PM UTC 24 |
Aug 27 09:13:23 PM UTC 24 |
2879407379 ps |
| T1723 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/33.xbar_error_random.1854231571 |
|
|
Aug 27 09:13:03 PM UTC 24 |
Aug 27 09:13:23 PM UTC 24 |
155191764 ps |
| T530 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/17.xbar_access_same_device_slow_rsp.1492383647 |
|
|
Aug 27 08:41:52 PM UTC 24 |
Aug 27 09:13:24 PM UTC 24 |
121649154103 ps |
| T1724 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/33.xbar_error_and_unmapped_addr.1884874596 |
|
|
Aug 27 09:13:20 PM UTC 24 |
Aug 27 09:13:40 PM UTC 24 |
193097422 ps |
| T1725 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/27.xbar_random_large_delays.3540815634 |
|
|
Aug 27 09:02:23 PM UTC 24 |
Aug 27 09:13:40 PM UTC 24 |
75778934705 ps |
| T1726 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/33.xbar_random_slow_rsp.815471775 |
|
|
Aug 27 09:12:55 PM UTC 24 |
Aug 27 09:13:49 PM UTC 24 |
2977689833 ps |
| T1727 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/33.xbar_smoke_slow_rsp.2123642395 |
|
|
Aug 27 09:12:42 PM UTC 24 |
Aug 27 09:13:54 PM UTC 24 |
5562523532 ps |
| T1728 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/34.xbar_smoke_zero_delays.1133512838 |
|
|
Aug 27 09:13:45 PM UTC 24 |
Aug 27 09:13:55 PM UTC 24 |
49179622 ps |
| T1729 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/34.xbar_smoke.4270205468 |
|
|
Aug 27 09:13:43 PM UTC 24 |
Aug 27 09:13:57 PM UTC 24 |
192137254 ps |
| T827 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/33.xbar_access_same_device.3168640410 |
|
|
Aug 27 09:12:58 PM UTC 24 |
Aug 27 09:13:58 PM UTC 24 |
1695732168 ps |
| T1730 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/33.xbar_stress_all_with_rand_reset.995721388 |
|
|
Aug 27 09:13:37 PM UTC 24 |
Aug 27 09:14:02 PM UTC 24 |
96416447 ps |
| T1731 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/33.xbar_unmapped_addr.2188811589 |
|
|
Aug 27 09:13:09 PM UTC 24 |
Aug 27 09:14:03 PM UTC 24 |
1184270707 ps |
| T1732 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/30.xbar_random_large_delays.822392517 |
|
|
Aug 27 09:07:25 PM UTC 24 |
Aug 27 09:14:05 PM UTC 24 |
35215781828 ps |
| T821 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/28.xbar_stress_all.3508283436 |
|
|
Aug 27 09:04:29 PM UTC 24 |
Aug 27 09:14:09 PM UTC 24 |
14113542060 ps |
| T1733 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/33.xbar_random.1013690944 |
|
|
Aug 27 09:12:43 PM UTC 24 |
Aug 27 09:14:12 PM UTC 24 |
1910670163 ps |
| T544 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/31.xbar_random_large_delays.22900671 |
|
|
Aug 27 09:09:57 PM UTC 24 |
Aug 27 09:14:14 PM UTC 24 |
23014099311 ps |
| T1734 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/33.xbar_same_source.2581153397 |
|
|
Aug 27 09:13:02 PM UTC 24 |
Aug 27 09:14:15 PM UTC 24 |
1877626139 ps |
| T1735 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/34.xbar_random.110472196 |
|
|
Aug 27 09:14:02 PM UTC 24 |
Aug 27 09:14:18 PM UTC 24 |
208012512 ps |
| T843 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/21.xbar_access_same_device_slow_rsp.1735137791 |
|
|
Aug 27 08:52:06 PM UTC 24 |
Aug 27 09:14:28 PM UTC 24 |
93413177277 ps |
| T1736 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/33.xbar_smoke_large_delays.2923384750 |
|
|
Aug 27 09:12:39 PM UTC 24 |
Aug 27 09:14:30 PM UTC 24 |
8615724112 ps |
| T1737 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/34.xbar_random_zero_delays.4275942024 |
|
|
Aug 27 09:14:04 PM UTC 24 |
Aug 27 09:14:32 PM UTC 24 |
227952461 ps |
| T1738 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/34.xbar_unmapped_addr.3919147406 |
|
|
Aug 27 09:14:23 PM UTC 24 |
Aug 27 09:14:35 PM UTC 24 |
37303234 ps |
| T1739 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/34.xbar_stress_all.2482560905 |
|
|
Aug 27 09:14:30 PM UTC 24 |
Aug 27 09:14:39 PM UTC 24 |
50269943 ps |
| T1740 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/34.xbar_same_source.1783490613 |
|
|
Aug 27 09:14:18 PM UTC 24 |
Aug 27 09:14:40 PM UTC 24 |
272304692 ps |
| T1741 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/35.xbar_smoke.2209703379 |
|
|
Aug 27 09:14:41 PM UTC 24 |
Aug 27 09:14:52 PM UTC 24 |
141954278 ps |
| T1742 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/33.xbar_stress_all_with_reset_error.2186755593 |
|
|
Aug 27 09:13:40 PM UTC 24 |
Aug 27 09:14:52 PM UTC 24 |
226781345 ps |
| T1743 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/34.xbar_smoke_slow_rsp.3746338614 |
|
|
Aug 27 09:13:47 PM UTC 24 |
Aug 27 09:14:53 PM UTC 24 |
4228787695 ps |
| T1744 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/35.xbar_smoke_zero_delays.2766659203 |
|
|
Aug 27 09:14:50 PM UTC 24 |
Aug 27 09:14:58 PM UTC 24 |
44865798 ps |
| T1745 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/34.xbar_smoke_large_delays.3853581494 |
|
|
Aug 27 09:13:47 PM UTC 24 |
Aug 27 09:15:01 PM UTC 24 |
7104068383 ps |
| T1746 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/32.xbar_random_slow_rsp.3193636441 |
|
|
Aug 27 09:11:43 PM UTC 24 |
Aug 27 09:15:02 PM UTC 24 |
14300176849 ps |
| T490 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/26.xbar_random_slow_rsp.762842098 |
|
|
Aug 27 09:01:08 PM UTC 24 |
Aug 27 09:15:04 PM UTC 24 |
59233332675 ps |
| T1747 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/34.xbar_error_and_unmapped_addr.2190920156 |
|
|
Aug 27 09:14:24 PM UTC 24 |
Aug 27 09:15:06 PM UTC 24 |
747261685 ps |
| T1748 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/35.xbar_random.1043560636 |
|
|
Aug 27 09:14:55 PM UTC 24 |
Aug 27 09:15:12 PM UTC 24 |
137798574 ps |
| T1749 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/34.xbar_stress_all_with_reset_error.2878524864 |
|
|
Aug 27 09:14:36 PM UTC 24 |
Aug 27 09:15:32 PM UTC 24 |
212983649 ps |
| T1750 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/34.xbar_access_same_device.3525251013 |
|
|
Aug 27 09:14:14 PM UTC 24 |
Aug 27 09:15:34 PM UTC 24 |
1953277916 ps |
| T1751 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/35.xbar_random_zero_delays.2306613927 |
|
|
Aug 27 09:15:00 PM UTC 24 |
Aug 27 09:15:35 PM UTC 24 |
292447583 ps |
| T1752 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/34.xbar_error_random.3906142236 |
|
|
Aug 27 09:14:22 PM UTC 24 |
Aug 27 09:15:36 PM UTC 24 |
2454766188 ps |
| T1753 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/31.xbar_stress_all.3355393812 |
|
|
Aug 27 09:10:33 PM UTC 24 |
Aug 27 09:15:40 PM UTC 24 |
9143740403 ps |
| T1754 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/35.xbar_unmapped_addr.2146545512 |
|
|
Aug 27 09:15:23 PM UTC 24 |
Aug 27 09:15:44 PM UTC 24 |
328829581 ps |
| T1755 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/33.xbar_stress_all_with_error.2527957743 |
|
|
Aug 27 09:13:37 PM UTC 24 |
Aug 27 09:15:44 PM UTC 24 |
3333060580 ps |
| T1756 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/32.xbar_stress_all_with_error.3657568362 |
|
|
Aug 27 09:12:07 PM UTC 24 |
Aug 27 09:15:45 PM UTC 24 |
2497896905 ps |
| T1757 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/29.xbar_random_slow_rsp.128611156 |
|
|
Aug 27 09:05:53 PM UTC 24 |
Aug 27 09:15:49 PM UTC 24 |
37276624060 ps |
| T1758 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/25.xbar_random_large_delays.3124118083 |
|
|
Aug 27 08:59:40 PM UTC 24 |
Aug 27 09:16:06 PM UTC 24 |
79770262632 ps |
| T1759 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/36.xbar_smoke_zero_delays.921960537 |
|
|
Aug 27 09:15:59 PM UTC 24 |
Aug 27 09:16:07 PM UTC 24 |
47693978 ps |
| T1760 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/36.xbar_smoke.2259824338 |
|
|
Aug 27 09:15:57 PM UTC 24 |
Aug 27 09:16:11 PM UTC 24 |
195906863 ps |
| T1761 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/35.xbar_error_and_unmapped_addr.2528629852 |
|
|
Aug 27 09:15:26 PM UTC 24 |
Aug 27 09:16:14 PM UTC 24 |
1349728284 ps |
| T1762 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/35.xbar_same_source.1125669690 |
|
|
Aug 27 09:15:18 PM UTC 24 |
Aug 27 09:16:18 PM UTC 24 |
580096288 ps |
| T1763 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/35.xbar_smoke_slow_rsp.2280222187 |
|
|
Aug 27 09:14:56 PM UTC 24 |
Aug 27 09:16:21 PM UTC 24 |
5372696247 ps |
| T1764 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/36.xbar_random.3710895998 |
|
|
Aug 27 09:16:06 PM UTC 24 |
Aug 27 09:16:25 PM UTC 24 |
268292068 ps |
| T1765 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/31.xbar_stress_all_with_reset_error.2127793216 |
|
|
Aug 27 09:11:02 PM UTC 24 |
Aug 27 09:16:28 PM UTC 24 |
6239623460 ps |
| T1766 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/36.xbar_random_zero_delays.978039758 |
|
|
Aug 27 09:16:04 PM UTC 24 |
Aug 27 09:16:28 PM UTC 24 |
166481686 ps |
| T1767 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/35.xbar_smoke_large_delays.3428220041 |
|
|
Aug 27 09:14:52 PM UTC 24 |
Aug 27 09:16:44 PM UTC 24 |
8123173826 ps |
| T1768 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/35.xbar_error_random.2026686164 |
|
|
Aug 27 09:15:23 PM UTC 24 |
Aug 27 09:16:46 PM UTC 24 |
2169169833 ps |
| T1769 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/36.xbar_access_same_device.3502614592 |
|
|
Aug 27 09:16:30 PM UTC 24 |
Aug 27 09:16:51 PM UTC 24 |
327022081 ps |
| T1770 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/34.xbar_access_same_device_slow_rsp.3502647835 |
|
|
Aug 27 09:14:19 PM UTC 24 |
Aug 27 09:17:02 PM UTC 24 |
8644055881 ps |
| T1771 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/34.xbar_stress_all_with_error.108457167 |
|
|
Aug 27 09:14:34 PM UTC 24 |
Aug 27 09:17:07 PM UTC 24 |
1645364467 ps |
| T1772 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/36.xbar_error_random.4257844745 |
|
|
Aug 27 09:16:42 PM UTC 24 |
Aug 27 09:17:08 PM UTC 24 |
216575318 ps |
| T1773 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/36.xbar_error_and_unmapped_addr.2818533205 |
|
|
Aug 27 09:16:48 PM UTC 24 |
Aug 27 09:17:12 PM UTC 24 |
457496802 ps |
| T1774 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/41.xbar_smoke_zero_delays.3951544824 |
|
|
Aug 27 09:23:58 PM UTC 24 |
Aug 27 09:24:10 PM UTC 24 |
54605896 ps |
| T1775 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/3.chip_same_csr_outstanding.3287195941 |
|
|
Aug 27 08:10:47 PM UTC 24 |
Aug 27 09:17:16 PM UTC 24 |
32852711843 ps |
| T1776 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/37.xbar_smoke.4109340550 |
|
|
Aug 27 09:17:14 PM UTC 24 |
Aug 27 09:17:24 PM UTC 24 |
47870385 ps |
| T1777 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/37.xbar_smoke_zero_delays.3896817346 |
|
|
Aug 27 09:17:21 PM UTC 24 |
Aug 27 09:17:32 PM UTC 24 |
56743501 ps |
| T816 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/24.xbar_access_same_device_slow_rsp.3667213345 |
|
|
Aug 27 08:58:05 PM UTC 24 |
Aug 27 09:17:36 PM UTC 24 |
66229152499 ps |
| T1778 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/33.xbar_random_large_delays.4171161586 |
|
|
Aug 27 09:12:53 PM UTC 24 |
Aug 27 09:17:40 PM UTC 24 |
23805158062 ps |
| T1779 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/36.xbar_same_source.2825351237 |
|
|
Aug 27 09:16:37 PM UTC 24 |
Aug 27 09:17:43 PM UTC 24 |
1957798182 ps |
| T1780 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/36.xbar_unmapped_addr.592537267 |
|
|
Aug 27 09:16:44 PM UTC 24 |
Aug 27 09:17:51 PM UTC 24 |
1312829214 ps |
| T1781 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/36.xbar_smoke_slow_rsp.2211435747 |
|
|
Aug 27 09:16:04 PM UTC 24 |
Aug 27 09:17:57 PM UTC 24 |
4600734893 ps |
| T1782 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/37.xbar_random_zero_delays.2404279119 |
|
|
Aug 27 09:17:39 PM UTC 24 |
Aug 27 09:18:00 PM UTC 24 |
152829450 ps |
| T1783 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/35.xbar_access_same_device.2083450068 |
|
|
Aug 27 09:15:15 PM UTC 24 |
Aug 27 09:18:03 PM UTC 24 |
3576036209 ps |
| T1784 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/36.xbar_smoke_large_delays.3381702730 |
|
|
Aug 27 09:16:01 PM UTC 24 |
Aug 27 09:18:04 PM UTC 24 |
8713255435 ps |
| T1785 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/37.xbar_access_same_device.3523834979 |
|
|
Aug 27 09:17:58 PM UTC 24 |
Aug 27 09:18:10 PM UTC 24 |
113398159 ps |
| T1786 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/31.xbar_stress_all_with_rand_reset.954654230 |
|
|
Aug 27 09:10:57 PM UTC 24 |
Aug 27 09:18:21 PM UTC 24 |
3518312396 ps |
| T1787 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/32.xbar_random_large_delays.599963740 |
|
|
Aug 27 09:11:42 PM UTC 24 |
Aug 27 09:18:33 PM UTC 24 |
44079141784 ps |
| T1788 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/37.xbar_same_source.1860413825 |
|
|
Aug 27 09:18:05 PM UTC 24 |
Aug 27 09:18:34 PM UTC 24 |
598721769 ps |
| T1789 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/37.xbar_smoke_slow_rsp.839929145 |
|
|
Aug 27 09:17:31 PM UTC 24 |
Aug 27 09:18:40 PM UTC 24 |
4366942035 ps |