| T846 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/34.xbar_stress_all_with_rand_reset.2221189520 |
|
|
Aug 27 09:14:33 PM UTC 24 |
Aug 27 09:18:44 PM UTC 24 |
545243405 ps |
| T1790 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/37.xbar_unmapped_addr.3385344237 |
|
|
Aug 27 09:18:21 PM UTC 24 |
Aug 27 09:18:46 PM UTC 24 |
570069479 ps |
| T1791 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/35.xbar_stress_all.2581334764 |
|
|
Aug 27 09:15:28 PM UTC 24 |
Aug 27 09:18:48 PM UTC 24 |
1959647033 ps |
| T1792 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/37.xbar_error_and_unmapped_addr.1527583610 |
|
|
Aug 27 09:18:22 PM UTC 24 |
Aug 27 09:18:49 PM UTC 24 |
212830548 ps |
| T1793 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/23.xbar_access_same_device_slow_rsp.3073334637 |
|
|
Aug 27 08:56:31 PM UTC 24 |
Aug 27 09:18:55 PM UTC 24 |
82930349027 ps |
| T1794 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/36.xbar_random_large_delays.1369524074 |
|
|
Aug 27 09:16:09 PM UTC 24 |
Aug 27 09:19:03 PM UTC 24 |
19659718440 ps |
| T1795 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/38.xbar_smoke.3086343456 |
|
|
Aug 27 09:18:56 PM UTC 24 |
Aug 27 09:19:07 PM UTC 24 |
119567734 ps |
| T1796 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/38.xbar_smoke_zero_delays.2447879804 |
|
|
Aug 27 09:18:57 PM UTC 24 |
Aug 27 09:19:08 PM UTC 24 |
59046611 ps |
| T1797 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/37.xbar_smoke_large_delays.1594457967 |
|
|
Aug 27 09:17:29 PM UTC 24 |
Aug 27 09:19:16 PM UTC 24 |
8972275527 ps |
| T1798 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/38.xbar_random.1475628296 |
|
|
Aug 27 09:19:08 PM UTC 24 |
Aug 27 09:19:21 PM UTC 24 |
150584419 ps |
| T1799 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/34.xbar_random_slow_rsp.3558937400 |
|
|
Aug 27 09:14:14 PM UTC 24 |
Aug 27 09:19:26 PM UTC 24 |
20938966957 ps |
| T1800 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/37.xbar_error_random.961635330 |
|
|
Aug 27 09:18:15 PM UTC 24 |
Aug 27 09:19:31 PM UTC 24 |
1937915482 ps |
| T1801 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/37.xbar_random.688887739 |
|
|
Aug 27 09:17:35 PM UTC 24 |
Aug 27 09:19:33 PM UTC 24 |
2223062696 ps |
| T1802 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/38.xbar_random_zero_delays.1358130078 |
|
|
Aug 27 09:19:11 PM UTC 24 |
Aug 27 09:19:53 PM UTC 24 |
495410836 ps |
| T1803 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/38.xbar_same_source.4280725630 |
|
|
Aug 27 09:19:29 PM UTC 24 |
Aug 27 09:20:06 PM UTC 24 |
1169855795 ps |
| T1804 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/38.xbar_unmapped_addr.2230502130 |
|
|
Aug 27 09:19:44 PM UTC 24 |
Aug 27 09:20:16 PM UTC 24 |
297384666 ps |
| T1805 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/38.xbar_error_and_unmapped_addr.222160613 |
|
|
Aug 27 09:19:49 PM UTC 24 |
Aug 27 09:20:23 PM UTC 24 |
908133739 ps |
| T1806 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/38.xbar_access_same_device.2186553725 |
|
|
Aug 27 09:19:23 PM UTC 24 |
Aug 27 09:20:35 PM UTC 24 |
779541578 ps |
| T847 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/36.xbar_stress_all_with_reset_error.157545008 |
|
|
Aug 27 09:17:08 PM UTC 24 |
Aug 27 09:20:41 PM UTC 24 |
619857461 ps |
| T1807 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/39.xbar_smoke.3292556892 |
|
|
Aug 27 09:20:36 PM UTC 24 |
Aug 27 09:20:47 PM UTC 24 |
46319845 ps |
| T1808 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/38.xbar_smoke_large_delays.1771577208 |
|
|
Aug 27 09:19:01 PM UTC 24 |
Aug 27 09:20:48 PM UTC 24 |
6691637883 ps |
| T1809 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/38.xbar_smoke_slow_rsp.2665359703 |
|
|
Aug 27 09:19:07 PM UTC 24 |
Aug 27 09:20:52 PM UTC 24 |
4392981960 ps |
| T1810 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/39.xbar_smoke_zero_delays.3561672805 |
|
|
Aug 27 09:20:47 PM UTC 24 |
Aug 27 09:20:56 PM UTC 24 |
56013753 ps |
| T1811 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/37.xbar_stress_all_with_rand_reset.796051858 |
|
|
Aug 27 09:18:23 PM UTC 24 |
Aug 27 09:21:01 PM UTC 24 |
588300320 ps |
| T1812 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/28.xbar_random_slow_rsp.1061655701 |
|
|
Aug 27 09:04:04 PM UTC 24 |
Aug 27 09:21:05 PM UTC 24 |
57985108265 ps |
| T1813 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/36.xbar_random_slow_rsp.922239367 |
|
|
Aug 27 09:16:29 PM UTC 24 |
Aug 27 09:21:06 PM UTC 24 |
16259435032 ps |
| T1814 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/38.xbar_error_random.482153133 |
|
|
Aug 27 09:19:38 PM UTC 24 |
Aug 27 09:21:08 PM UTC 24 |
1880554638 ps |
| T1815 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/38.xbar_random_slow_rsp.3918641308 |
|
|
Aug 27 09:19:17 PM UTC 24 |
Aug 27 09:21:12 PM UTC 24 |
6426454158 ps |
| T1816 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/36.xbar_stress_all_with_error.2752342903 |
|
|
Aug 27 09:17:07 PM UTC 24 |
Aug 27 09:21:20 PM UTC 24 |
2829360007 ps |
| T831 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/18.xbar_access_same_device_slow_rsp.3357859021 |
|
|
Aug 27 08:44:40 PM UTC 24 |
Aug 27 09:21:26 PM UTC 24 |
153073998359 ps |
| T832 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/35.xbar_access_same_device_slow_rsp.3377600583 |
|
|
Aug 27 09:15:15 PM UTC 24 |
Aug 27 09:21:32 PM UTC 24 |
20460522144 ps |
| T1817 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/39.xbar_unmapped_addr.467887395 |
|
|
Aug 27 09:21:35 PM UTC 24 |
Aug 27 09:21:45 PM UTC 24 |
33403904 ps |
| T1818 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/39.xbar_random.2253374782 |
|
|
Aug 27 09:21:09 PM UTC 24 |
Aug 27 09:21:53 PM UTC 24 |
1240097253 ps |
| T1819 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/39.xbar_random_zero_delays.2326953762 |
|
|
Aug 27 09:21:11 PM UTC 24 |
Aug 27 09:21:58 PM UTC 24 |
514219288 ps |
| T1820 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/38.xbar_stress_all_with_error.1993991361 |
|
|
Aug 27 09:20:16 PM UTC 24 |
Aug 27 09:22:01 PM UTC 24 |
2447433086 ps |
| T1821 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/37.xbar_stress_all_with_error.3975570261 |
|
|
Aug 27 09:18:30 PM UTC 24 |
Aug 27 09:22:08 PM UTC 24 |
5642761229 ps |
| T1822 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/39.xbar_error_random.1496121237 |
|
|
Aug 27 09:21:28 PM UTC 24 |
Aug 27 09:22:15 PM UTC 24 |
444358349 ps |
| T1823 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/39.xbar_same_source.3036272514 |
|
|
Aug 27 09:21:28 PM UTC 24 |
Aug 27 09:22:16 PM UTC 24 |
1085351888 ps |
| T1824 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/39.xbar_error_and_unmapped_addr.2630483430 |
|
|
Aug 27 09:21:43 PM UTC 24 |
Aug 27 09:22:16 PM UTC 24 |
533814841 ps |
| T1825 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/40.xbar_smoke.2333460502 |
|
|
Aug 27 09:22:20 PM UTC 24 |
Aug 27 09:22:30 PM UTC 24 |
39655561 ps |
| T1826 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/40.xbar_smoke_zero_delays.3765432329 |
|
|
Aug 27 09:22:25 PM UTC 24 |
Aug 27 09:22:34 PM UTC 24 |
41924595 ps |
| T1827 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/39.xbar_smoke_large_delays.912591662 |
|
|
Aug 27 09:20:57 PM UTC 24 |
Aug 27 09:22:38 PM UTC 24 |
8923474549 ps |
| T1828 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/39.xbar_stress_all_with_error.2815967416 |
|
|
Aug 27 09:22:07 PM UTC 24 |
Aug 27 09:22:45 PM UTC 24 |
842588306 ps |
| T1829 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/39.xbar_random_large_delays.2594155807 |
|
|
Aug 27 09:21:14 PM UTC 24 |
Aug 27 09:22:48 PM UTC 24 |
5720321083 ps |
| T1830 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/33.xbar_stress_all.1995248772 |
|
|
Aug 27 09:13:26 PM UTC 24 |
Aug 27 09:22:49 PM UTC 24 |
16058728912 ps |
| T1831 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/39.xbar_smoke_slow_rsp.3305309348 |
|
|
Aug 27 09:21:04 PM UTC 24 |
Aug 27 09:23:07 PM UTC 24 |
5694994477 ps |
| T1832 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/40.xbar_random.231870176 |
|
|
Aug 27 09:22:39 PM UTC 24 |
Aug 27 09:23:07 PM UTC 24 |
202713602 ps |
| T1833 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/39.xbar_access_same_device.1077145205 |
|
|
Aug 27 09:21:23 PM UTC 24 |
Aug 27 09:23:22 PM UTC 24 |
2260390097 ps |
| T1834 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/40.xbar_error_random.2138224127 |
|
|
Aug 27 09:23:12 PM UTC 24 |
Aug 27 09:23:23 PM UTC 24 |
145954697 ps |
| T504 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/32.xbar_stress_all_with_rand_reset.3069155750 |
|
|
Aug 27 09:12:04 PM UTC 24 |
Aug 27 09:23:24 PM UTC 24 |
11390799467 ps |
| T1835 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/36.xbar_access_same_device_slow_rsp.3509920212 |
|
|
Aug 27 09:16:34 PM UTC 24 |
Aug 27 09:23:32 PM UTC 24 |
25818817185 ps |
| T1836 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/1.chip_same_csr_outstanding.291521971 |
|
|
Aug 27 08:07:53 PM UTC 24 |
Aug 27 09:23:33 PM UTC 24 |
29002385320 ps |
| T876 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/35.xbar_stress_all_with_rand_reset.3413189614 |
|
|
Aug 27 09:15:33 PM UTC 24 |
Aug 27 09:23:35 PM UTC 24 |
8713517660 ps |
| T1837 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/36.xbar_stress_all.361067763 |
|
|
Aug 27 09:16:51 PM UTC 24 |
Aug 27 09:23:36 PM UTC 24 |
10650106529 ps |
| T1838 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/40.xbar_same_source.1845837629 |
|
|
Aug 27 09:23:10 PM UTC 24 |
Aug 27 09:23:45 PM UTC 24 |
1187619411 ps |
| T1839 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/40.xbar_random_zero_delays.3404419803 |
|
|
Aug 27 09:22:39 PM UTC 24 |
Aug 27 09:23:47 PM UTC 24 |
626302818 ps |
| T1840 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/40.xbar_error_and_unmapped_addr.1771803245 |
|
|
Aug 27 09:23:31 PM UTC 24 |
Aug 27 09:23:48 PM UTC 24 |
205219251 ps |
| T610 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/35.xbar_stress_all_with_error.3114351353 |
|
|
Aug 27 09:15:55 PM UTC 24 |
Aug 27 09:23:49 PM UTC 24 |
10811584864 ps |
| T1841 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/41.xbar_smoke.4273212595 |
|
|
Aug 27 09:23:53 PM UTC 24 |
Aug 27 09:24:02 PM UTC 24 |
47063952 ps |
| T1842 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/40.xbar_smoke_large_delays.2879447244 |
|
|
Aug 27 09:22:31 PM UTC 24 |
Aug 27 09:24:08 PM UTC 24 |
7396234179 ps |
| T1843 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/40.xbar_unmapped_addr.431775536 |
|
|
Aug 27 09:23:30 PM UTC 24 |
Aug 27 09:24:09 PM UTC 24 |
231468717 ps |
| T1844 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/33.xbar_access_same_device_slow_rsp.2708549414 |
|
|
Aug 27 09:12:58 PM UTC 24 |
Aug 27 09:24:15 PM UTC 24 |
45617118598 ps |
| T1845 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/39.xbar_random_slow_rsp.3071099017 |
|
|
Aug 27 09:21:20 PM UTC 24 |
Aug 27 09:24:16 PM UTC 24 |
13732589625 ps |
| T1846 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/31.xbar_random_slow_rsp.1810525873 |
|
|
Aug 27 09:09:58 PM UTC 24 |
Aug 27 09:24:17 PM UTC 24 |
61026483389 ps |
| T1847 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/40.xbar_smoke_slow_rsp.3148661103 |
|
|
Aug 27 09:22:38 PM UTC 24 |
Aug 27 09:24:27 PM UTC 24 |
5257644686 ps |
| T1848 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/40.xbar_access_same_device.4211371541 |
|
|
Aug 27 09:23:01 PM UTC 24 |
Aug 27 09:24:30 PM UTC 24 |
1840913111 ps |
| T1849 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/41.xbar_error_and_unmapped_addr.3122733084 |
|
|
Aug 27 09:24:38 PM UTC 24 |
Aug 27 09:24:47 PM UTC 24 |
32558905 ps |
| T1850 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/41.xbar_random.2578207781 |
|
|
Aug 27 09:24:09 PM UTC 24 |
Aug 27 09:24:52 PM UTC 24 |
461102130 ps |
| T1851 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/27.xbar_access_same_device_slow_rsp.2003961511 |
|
|
Aug 27 09:02:39 PM UTC 24 |
Aug 27 09:24:53 PM UTC 24 |
78012266675 ps |
| T487 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/38.xbar_stress_all.3269683840 |
|
|
Aug 27 09:19:54 PM UTC 24 |
Aug 27 09:24:58 PM UTC 24 |
7126759952 ps |
| T1852 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/41.xbar_error_random.216582996 |
|
|
Aug 27 09:24:34 PM UTC 24 |
Aug 27 09:25:01 PM UTC 24 |
538729651 ps |
| T1853 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/41.xbar_random_zero_delays.3082361181 |
|
|
Aug 27 09:24:09 PM UTC 24 |
Aug 27 09:25:04 PM UTC 24 |
578779529 ps |
| T1854 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/41.xbar_unmapped_addr.3741946936 |
|
|
Aug 27 09:24:38 PM UTC 24 |
Aug 27 09:25:05 PM UTC 24 |
156951142 ps |
| T1855 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/41.xbar_same_source.3490585595 |
|
|
Aug 27 09:24:28 PM UTC 24 |
Aug 27 09:25:16 PM UTC 24 |
541051369 ps |
| T1856 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/39.xbar_stress_all_with_rand_reset.1324961953 |
|
|
Aug 27 09:21:56 PM UTC 24 |
Aug 27 09:25:25 PM UTC 24 |
779972487 ps |
| T1857 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/42.xbar_smoke.1279303524 |
|
|
Aug 27 09:25:16 PM UTC 24 |
Aug 27 09:25:29 PM UTC 24 |
198204470 ps |
| T1858 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/42.xbar_smoke_zero_delays.3050311415 |
|
|
Aug 27 09:25:21 PM UTC 24 |
Aug 27 09:25:30 PM UTC 24 |
47099189 ps |
| T1859 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/41.xbar_smoke_slow_rsp.3187929107 |
|
|
Aug 27 09:24:09 PM UTC 24 |
Aug 27 09:25:41 PM UTC 24 |
5832716360 ps |
| T532 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/42.xbar_random.929343140 |
|
|
Aug 27 09:25:27 PM UTC 24 |
Aug 27 09:25:44 PM UTC 24 |
116918552 ps |
| T1860 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/41.xbar_smoke_large_delays.435446819 |
|
|
Aug 27 09:23:58 PM UTC 24 |
Aug 27 09:25:58 PM UTC 24 |
9317988036 ps |
| T1861 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/41.xbar_stress_all_with_reset_error.4129841260 |
|
|
Aug 27 09:25:15 PM UTC 24 |
Aug 27 09:25:58 PM UTC 24 |
88009324 ps |
| T1862 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/7.chip_same_csr_outstanding.24030263 |
|
|
Aug 27 08:18:17 PM UTC 24 |
Aug 27 09:26:02 PM UTC 24 |
30906513992 ps |
| T1863 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/40.xbar_stress_all.3923630528 |
|
|
Aug 27 09:23:45 PM UTC 24 |
Aug 27 09:26:02 PM UTC 24 |
1436621614 ps |
| T1864 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/38.xbar_stress_all_with_rand_reset.1661871122 |
|
|
Aug 27 09:19:56 PM UTC 24 |
Aug 27 09:26:07 PM UTC 24 |
1184116581 ps |
| T856 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/39.xbar_stress_all_with_reset_error.3687173481 |
|
|
Aug 27 09:22:16 PM UTC 24 |
Aug 27 09:26:13 PM UTC 24 |
1308573603 ps |
| T833 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/41.xbar_access_same_device.298403520 |
|
|
Aug 27 09:24:27 PM UTC 24 |
Aug 27 09:26:14 PM UTC 24 |
2410478841 ps |
| T1865 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/34.xbar_random_large_delays.3059011624 |
|
|
Aug 27 09:14:09 PM UTC 24 |
Aug 27 09:26:27 PM UTC 24 |
82453913674 ps |
| T1866 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/42.xbar_random_zero_delays.46724893 |
|
|
Aug 27 09:25:37 PM UTC 24 |
Aug 27 09:26:27 PM UTC 24 |
456916207 ps |
| T1867 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/5.chip_same_csr_outstanding.29264295 |
|
|
Aug 27 08:14:22 PM UTC 24 |
Aug 27 09:26:30 PM UTC 24 |
28341546671 ps |
| T1868 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/38.xbar_random_large_delays.2256355790 |
|
|
Aug 27 09:19:12 PM UTC 24 |
Aug 27 09:26:34 PM UTC 24 |
42497044015 ps |
| T1869 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/42.xbar_error_and_unmapped_addr.2284762981 |
|
|
Aug 27 09:26:19 PM UTC 24 |
Aug 27 09:26:42 PM UTC 24 |
623622297 ps |
| T1870 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/39.xbar_stress_all.3150041671 |
|
|
Aug 27 09:21:50 PM UTC 24 |
Aug 27 09:26:49 PM UTC 24 |
7499252934 ps |
| T1871 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/37.xbar_stress_all_with_reset_error.2485433858 |
|
|
Aug 27 09:18:44 PM UTC 24 |
Aug 27 09:26:53 PM UTC 24 |
3746047327 ps |
| T1872 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/43.xbar_smoke_zero_delays.1375784654 |
|
|
Aug 27 09:26:45 PM UTC 24 |
Aug 27 09:26:56 PM UTC 24 |
57988717 ps |
| T1873 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/42.xbar_unmapped_addr.1017214391 |
|
|
Aug 27 09:26:20 PM UTC 24 |
Aug 27 09:26:57 PM UTC 24 |
228505174 ps |
| T516 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/37.xbar_stress_all.2382919620 |
|
|
Aug 27 09:18:23 PM UTC 24 |
Aug 27 09:26:59 PM UTC 24 |
15479751314 ps |
| T1874 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/43.xbar_smoke.3413047422 |
|
|
Aug 27 09:26:49 PM UTC 24 |
Aug 27 09:26:59 PM UTC 24 |
123821725 ps |
| T1875 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/37.xbar_random_slow_rsp.947887807 |
|
|
Aug 27 09:17:52 PM UTC 24 |
Aug 27 09:27:05 PM UTC 24 |
37245442636 ps |
| T1876 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/42.xbar_smoke_large_delays.928179203 |
|
|
Aug 27 09:25:25 PM UTC 24 |
Aug 27 09:27:11 PM UTC 24 |
8746644241 ps |
| T1877 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/10.chip_same_csr_outstanding.1218276788 |
|
|
Aug 27 08:25:02 PM UTC 24 |
Aug 27 09:27:13 PM UTC 24 |
31792524719 ps |
| T1878 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/13.chip_same_csr_outstanding.1480358946 |
|
|
Aug 27 08:31:05 PM UTC 24 |
Aug 27 09:27:21 PM UTC 24 |
31975301929 ps |
| T1879 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/43.xbar_random_zero_delays.3967836631 |
|
|
Aug 27 09:27:12 PM UTC 24 |
Aug 27 09:27:27 PM UTC 24 |
91294272 ps |
| T1880 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/42.xbar_error_random.4036733921 |
|
|
Aug 27 09:26:17 PM UTC 24 |
Aug 27 09:27:31 PM UTC 24 |
1662640293 ps |
| T1881 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/41.xbar_stress_all_with_error.154770560 |
|
|
Aug 27 09:25:08 PM UTC 24 |
Aug 27 09:27:33 PM UTC 24 |
1646878104 ps |
| T1882 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/43.xbar_random.1487397249 |
|
|
Aug 27 09:27:04 PM UTC 24 |
Aug 27 09:27:36 PM UTC 24 |
392665982 ps |
| T1883 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/42.xbar_same_source.270056250 |
|
|
Aug 27 09:26:05 PM UTC 24 |
Aug 27 09:27:37 PM UTC 24 |
2578916791 ps |
| T1884 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/42.xbar_access_same_device.2464547686 |
|
|
Aug 27 09:25:53 PM UTC 24 |
Aug 27 09:27:38 PM UTC 24 |
1890654745 ps |
| T857 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/38.xbar_stress_all_with_reset_error.2692667261 |
|
|
Aug 27 09:20:29 PM UTC 24 |
Aug 27 09:27:39 PM UTC 24 |
7738005100 ps |
| T1885 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/42.xbar_smoke_slow_rsp.3898534182 |
|
|
Aug 27 09:25:28 PM UTC 24 |
Aug 27 09:27:55 PM UTC 24 |
6079577972 ps |
| T1886 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/42.xbar_stress_all.1014698183 |
|
|
Aug 27 09:26:24 PM UTC 24 |
Aug 27 09:27:56 PM UTC 24 |
1109373757 ps |
| T1887 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/11.chip_same_csr_outstanding.4188037822 |
|
|
Aug 27 08:26:46 PM UTC 24 |
Aug 27 09:27:57 PM UTC 24 |
31569587449 ps |
| T1888 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/43.xbar_error_random.1264696033 |
|
|
Aug 27 09:27:25 PM UTC 24 |
Aug 27 09:27:59 PM UTC 24 |
710830227 ps |
| T1889 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/43.xbar_unmapped_addr.1196661178 |
|
|
Aug 27 09:27:30 PM UTC 24 |
Aug 27 09:28:02 PM UTC 24 |
218960958 ps |
| T1890 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/43.xbar_error_and_unmapped_addr.2634546133 |
|
|
Aug 27 09:27:34 PM UTC 24 |
Aug 27 09:28:04 PM UTC 24 |
199879325 ps |
| T1891 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/43.xbar_smoke_large_delays.362008855 |
|
|
Aug 27 09:26:53 PM UTC 24 |
Aug 27 09:28:04 PM UTC 24 |
7185500779 ps |
| T1892 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/44.xbar_smoke.1057407395 |
|
|
Aug 27 09:27:59 PM UTC 24 |
Aug 27 09:28:08 PM UTC 24 |
43028911 ps |
| T1893 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/44.xbar_smoke_zero_delays.2909558801 |
|
|
Aug 27 09:28:01 PM UTC 24 |
Aug 27 09:28:09 PM UTC 24 |
47603246 ps |
| T834 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/25.xbar_access_same_device_slow_rsp.2665377509 |
|
|
Aug 27 08:59:47 PM UTC 24 |
Aug 27 09:28:25 PM UTC 24 |
109324316756 ps |
| T1894 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/43.xbar_smoke_slow_rsp.1860920810 |
|
|
Aug 27 09:26:57 PM UTC 24 |
Aug 27 09:28:28 PM UTC 24 |
5690538143 ps |
| T1895 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/43.xbar_same_source.2591722942 |
|
|
Aug 27 09:27:21 PM UTC 24 |
Aug 27 09:28:30 PM UTC 24 |
1974176360 ps |
| T1896 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/44.xbar_random.898461047 |
|
|
Aug 27 09:28:17 PM UTC 24 |
Aug 27 09:28:32 PM UTC 24 |
194505457 ps |
| T1897 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/44.xbar_random_zero_delays.2682536894 |
|
|
Aug 27 09:28:18 PM UTC 24 |
Aug 27 09:28:32 PM UTC 24 |
70903792 ps |
| T1898 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/30.xbar_access_same_device_slow_rsp.32411157 |
|
|
Aug 27 09:07:37 PM UTC 24 |
Aug 27 09:28:34 PM UTC 24 |
83455801512 ps |
| T1899 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/40.xbar_stress_all_with_reset_error.2646503560 |
|
|
Aug 27 09:23:55 PM UTC 24 |
Aug 27 09:28:35 PM UTC 24 |
3937016821 ps |
| T1900 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/43.xbar_access_same_device.1460424493 |
|
|
Aug 27 09:27:19 PM UTC 24 |
Aug 27 09:28:52 PM UTC 24 |
2871829210 ps |
| T1901 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/20.xbar_access_same_device_slow_rsp.859525959 |
|
|
Aug 27 08:50:28 PM UTC 24 |
Aug 27 09:29:04 PM UTC 24 |
148009235875 ps |
| T1902 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/45.xbar_smoke.3397593497 |
|
|
Aug 27 09:28:57 PM UTC 24 |
Aug 27 09:29:08 PM UTC 24 |
48369948 ps |
| T531 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/44.xbar_unmapped_addr.1515734810 |
|
|
Aug 27 09:28:33 PM UTC 24 |
Aug 27 09:29:08 PM UTC 24 |
581026699 ps |
| T1903 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/45.xbar_smoke_zero_delays.750175278 |
|
|
Aug 27 09:28:58 PM UTC 24 |
Aug 27 09:29:09 PM UTC 24 |
55993371 ps |
| T1904 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/44.xbar_access_same_device.4054805085 |
|
|
Aug 27 09:28:26 PM UTC 24 |
Aug 27 09:29:14 PM UTC 24 |
1058568481 ps |
| T1905 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/44.xbar_smoke_slow_rsp.2278837720 |
|
|
Aug 27 09:28:02 PM UTC 24 |
Aug 27 09:29:15 PM UTC 24 |
4882510461 ps |
| T1906 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/41.xbar_stress_all.2884649276 |
|
|
Aug 27 09:24:49 PM UTC 24 |
Aug 27 09:29:21 PM UTC 24 |
8586354471 ps |
| T1907 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/44.xbar_error_random.3732076018 |
|
|
Aug 27 09:28:31 PM UTC 24 |
Aug 27 09:29:23 PM UTC 24 |
1163889622 ps |
| T1908 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/44.xbar_same_source.3892094012 |
|
|
Aug 27 09:28:26 PM UTC 24 |
Aug 27 09:29:25 PM UTC 24 |
1773140653 ps |
| T1909 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/44.xbar_stress_all_with_rand_reset.2261828451 |
|
|
Aug 27 09:28:51 PM UTC 24 |
Aug 27 09:29:31 PM UTC 24 |
109634154 ps |
| T1910 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/44.xbar_smoke_large_delays.318669176 |
|
|
Aug 27 09:27:59 PM UTC 24 |
Aug 27 09:29:32 PM UTC 24 |
8933439070 ps |
| T1911 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/36.xbar_stress_all_with_rand_reset.3169470749 |
|
|
Aug 27 09:16:50 PM UTC 24 |
Aug 27 09:29:36 PM UTC 24 |
12735523645 ps |
| T1912 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/43.xbar_stress_all.1347765841 |
|
|
Aug 27 09:27:44 PM UTC 24 |
Aug 27 09:29:39 PM UTC 24 |
1026182749 ps |
| T1913 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/44.xbar_error_and_unmapped_addr.3611056054 |
|
|
Aug 27 09:28:47 PM UTC 24 |
Aug 27 09:29:40 PM UTC 24 |
1063188118 ps |
| T1914 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/44.xbar_stress_all_with_error.63782978 |
|
|
Aug 27 09:28:52 PM UTC 24 |
Aug 27 09:29:41 PM UTC 24 |
500238308 ps |
| T1915 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/40.xbar_stress_all_with_error.149654839 |
|
|
Aug 27 09:23:42 PM UTC 24 |
Aug 27 09:29:45 PM UTC 24 |
10980223626 ps |
| T1916 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/45.xbar_random_zero_delays.3566543918 |
|
|
Aug 27 09:29:30 PM UTC 24 |
Aug 27 09:29:47 PM UTC 24 |
174727363 ps |
| T1917 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/45.xbar_error_random.2188796713 |
|
|
Aug 27 09:29:46 PM UTC 24 |
Aug 27 09:30:03 PM UTC 24 |
114640039 ps |
| T1918 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/46.xbar_smoke.3961278639 |
|
|
Aug 27 09:30:08 PM UTC 24 |
Aug 27 09:30:18 PM UTC 24 |
50567355 ps |
| T1919 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/46.xbar_smoke_zero_delays.2490448739 |
|
|
Aug 27 09:30:10 PM UTC 24 |
Aug 27 09:30:20 PM UTC 24 |
44393364 ps |
| T1920 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/40.xbar_random_large_delays.4187194062 |
|
|
Aug 27 09:22:53 PM UTC 24 |
Aug 27 09:30:20 PM UTC 24 |
39778234321 ps |
| T1921 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/45.xbar_unmapped_addr.2895083628 |
|
|
Aug 27 09:29:53 PM UTC 24 |
Aug 27 09:30:21 PM UTC 24 |
160605516 ps |
| T1922 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/45.xbar_error_and_unmapped_addr.3958323391 |
|
|
Aug 27 09:29:55 PM UTC 24 |
Aug 27 09:30:25 PM UTC 24 |
195737904 ps |
| T1923 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/45.xbar_same_source.3658005471 |
|
|
Aug 27 09:29:46 PM UTC 24 |
Aug 27 09:30:26 PM UTC 24 |
1117091304 ps |
| T853 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/42.xbar_stress_all_with_reset_error.1799086434 |
|
|
Aug 27 09:26:36 PM UTC 24 |
Aug 27 09:30:39 PM UTC 24 |
482184835 ps |
| T1924 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/45.xbar_smoke_large_delays.1161154140 |
|
|
Aug 27 09:29:14 PM UTC 24 |
Aug 27 09:30:40 PM UTC 24 |
8579362035 ps |
| T1925 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/43.xbar_stress_all_with_reset_error.2757553797 |
|
|
Aug 27 09:27:56 PM UTC 24 |
Aug 27 09:30:42 PM UTC 24 |
509832906 ps |
| T1926 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/43.xbar_stress_all_with_error.2720682226 |
|
|
Aug 27 09:27:55 PM UTC 24 |
Aug 27 09:30:45 PM UTC 24 |
5259552268 ps |
| T1927 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/46.xbar_random.88070921 |
|
|
Aug 27 09:30:43 PM UTC 24 |
Aug 27 09:31:01 PM UTC 24 |
125383680 ps |
| T1928 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/45.xbar_random.300924070 |
|
|
Aug 27 09:29:29 PM UTC 24 |
Aug 27 09:31:03 PM UTC 24 |
2426848979 ps |
| T1929 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/46.xbar_unmapped_addr.3874261644 |
|
|
Aug 27 09:31:08 PM UTC 24 |
Aug 27 09:31:20 PM UTC 24 |
55534992 ps |
| T1930 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/46.xbar_access_same_device.3885423007 |
|
|
Aug 27 09:30:48 PM UTC 24 |
Aug 27 09:31:22 PM UTC 24 |
530313809 ps |
| T1931 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/37.xbar_random_large_delays.220017660 |
|
|
Aug 27 09:17:47 PM UTC 24 |
Aug 27 09:31:23 PM UTC 24 |
76316510326 ps |
| T1932 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/45.xbar_access_same_device.319119316 |
|
|
Aug 27 09:29:36 PM UTC 24 |
Aug 27 09:31:25 PM UTC 24 |
3168400136 ps |
| T1933 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/9.chip_same_csr_outstanding.2242258186 |
|
|
Aug 27 08:22:25 PM UTC 24 |
Aug 27 09:31:26 PM UTC 24 |
28545787108 ps |
| T1934 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/46.xbar_same_source.823551387 |
|
|
Aug 27 09:31:02 PM UTC 24 |
Aug 27 09:31:32 PM UTC 24 |
690654435 ps |
| T1935 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/46.xbar_error_random.2880421839 |
|
|
Aug 27 09:31:04 PM UTC 24 |
Aug 27 09:31:32 PM UTC 24 |
225731080 ps |
| T1936 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/35.xbar_random_slow_rsp.797441491 |
|
|
Aug 27 09:15:15 PM UTC 24 |
Aug 27 09:31:32 PM UTC 24 |
64615833259 ps |
| T1937 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/46.xbar_random_zero_delays.407253 |
|
|
Aug 27 09:30:41 PM UTC 24 |
Aug 27 09:31:32 PM UTC 24 |
460196970 ps |
| T1938 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/45.xbar_smoke_slow_rsp.1363686145 |
|
|
Aug 27 09:29:27 PM UTC 24 |
Aug 27 09:31:42 PM UTC 24 |
5751150204 ps |
| T1939 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/46.xbar_error_and_unmapped_addr.1825712180 |
|
|
Aug 27 09:31:23 PM UTC 24 |
Aug 27 09:31:48 PM UTC 24 |
626543763 ps |
| T848 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/44.xbar_stress_all_with_reset_error.2946114508 |
|
|
Aug 27 09:28:50 PM UTC 24 |
Aug 27 09:31:54 PM UTC 24 |
3726246896 ps |
| T1940 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/47.xbar_smoke_zero_delays.3529299002 |
|
|
Aug 27 09:31:48 PM UTC 24 |
Aug 27 09:31:58 PM UTC 24 |
47742224 ps |
| T1941 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/47.xbar_smoke.4162554467 |
|
|
Aug 27 09:31:49 PM UTC 24 |
Aug 27 09:31:59 PM UTC 24 |
180768360 ps |
| T1942 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/45.xbar_stress_all.1736642751 |
|
|
Aug 27 09:29:59 PM UTC 24 |
Aug 27 09:31:59 PM UTC 24 |
2399684145 ps |
| T1943 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/46.xbar_smoke_large_delays.996521397 |
|
|
Aug 27 09:30:25 PM UTC 24 |
Aug 27 09:32:16 PM UTC 24 |
9220259583 ps |
| T1944 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/46.xbar_stress_all_with_rand_reset.246548140 |
|
|
Aug 27 09:31:42 PM UTC 24 |
Aug 27 09:32:26 PM UTC 24 |
76963135 ps |
| T1945 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/47.xbar_random_zero_delays.1640542062 |
|
|
Aug 27 09:31:55 PM UTC 24 |
Aug 27 09:32:30 PM UTC 24 |
300287876 ps |
| T1946 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/46.xbar_smoke_slow_rsp.602257891 |
|
|
Aug 27 09:30:41 PM UTC 24 |
Aug 27 09:32:38 PM UTC 24 |
5242139048 ps |
| T1947 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/41.xbar_stress_all_with_rand_reset.279151989 |
|
|
Aug 27 09:24:52 PM UTC 24 |
Aug 27 09:32:38 PM UTC 24 |
5393190964 ps |
| T1948 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/47.xbar_smoke_large_delays.3966108412 |
|
|
Aug 27 09:31:55 PM UTC 24 |
Aug 27 09:32:46 PM UTC 24 |
5287856476 ps |
| T1949 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/47.xbar_random.1890621010 |
|
|
Aug 27 09:31:54 PM UTC 24 |
Aug 27 09:32:54 PM UTC 24 |
2180385664 ps |
| T803 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/22.xbar_access_same_device_slow_rsp.292428087 |
|
|
Aug 27 08:54:54 PM UTC 24 |
Aug 27 09:32:56 PM UTC 24 |
157848203999 ps |
| T1950 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/47.xbar_unmapped_addr.1965615788 |
|
|
Aug 27 09:32:39 PM UTC 24 |
Aug 27 09:33:05 PM UTC 24 |
149426639 ps |
| T1951 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/47.xbar_error_and_unmapped_addr.3806219292 |
|
|
Aug 27 09:32:49 PM UTC 24 |
Aug 27 09:33:11 PM UTC 24 |
144179527 ps |
| T1952 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/47.xbar_error_random.2078368584 |
|
|
Aug 27 09:32:23 PM UTC 24 |
Aug 27 09:33:13 PM UTC 24 |
423831605 ps |
| T1953 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/48.xbar_smoke.1768732314 |
|
|
Aug 27 09:33:17 PM UTC 24 |
Aug 27 09:33:26 PM UTC 24 |
42184013 ps |
| T1954 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/47.xbar_stress_all_with_rand_reset.2634468333 |
|
|
Aug 27 09:33:01 PM UTC 24 |
Aug 27 09:33:28 PM UTC 24 |
153067103 ps |
| T1955 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/48.xbar_smoke_zero_delays.1709967151 |
|
|
Aug 27 09:33:19 PM UTC 24 |
Aug 27 09:33:29 PM UTC 24 |
44661118 ps |
| T1956 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/45.xbar_stress_all_with_error.2032961867 |
|
|
Aug 27 09:30:03 PM UTC 24 |
Aug 27 09:33:29 PM UTC 24 |
6925684671 ps |
| T1957 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/47.xbar_same_source.2760680432 |
|
|
Aug 27 09:32:20 PM UTC 24 |
Aug 27 09:33:39 PM UTC 24 |
2253519693 ps |
| T1958 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/43.xbar_stress_all_with_rand_reset.3485979131 |
|
|
Aug 27 09:27:50 PM UTC 24 |
Aug 27 09:33:40 PM UTC 24 |
1422987844 ps |
| T1959 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/47.xbar_stress_all_with_error.2428411928 |
|
|
Aug 27 09:33:01 PM UTC 24 |
Aug 27 09:33:40 PM UTC 24 |
416189617 ps |
| T1960 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/44.xbar_stress_all.2092826727 |
|
|
Aug 27 09:28:49 PM UTC 24 |
Aug 27 09:33:41 PM UTC 24 |
7713981219 ps |
| T1961 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/47.xbar_smoke_slow_rsp.1205405412 |
|
|
Aug 27 09:31:55 PM UTC 24 |
Aug 27 09:33:43 PM UTC 24 |
5277389104 ps |
| T1962 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/32.xbar_access_same_device_slow_rsp.1085645016 |
|
|
Aug 27 09:11:53 PM UTC 24 |
Aug 27 09:33:57 PM UTC 24 |
84992861377 ps |
| T1963 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/47.xbar_access_same_device.2700675572 |
|
|
Aug 27 09:32:16 PM UTC 24 |
Aug 27 09:33:57 PM UTC 24 |
1838510417 ps |
| T1964 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/46.xbar_stress_all_with_error.1252741462 |
|
|
Aug 27 09:31:44 PM UTC 24 |
Aug 27 09:34:19 PM UTC 24 |
3898375061 ps |
| T1965 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/48.xbar_unmapped_addr.797038292 |
|
|
Aug 27 09:34:04 PM UTC 24 |
Aug 27 09:34:27 PM UTC 24 |
128758116 ps |
| T1966 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/48.xbar_access_same_device.3815879974 |
|
|
Aug 27 09:33:51 PM UTC 24 |
Aug 27 09:34:33 PM UTC 24 |
598708075 ps |
| T1967 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/40.xbar_random_slow_rsp.2471453554 |
|
|
Aug 27 09:22:55 PM UTC 24 |
Aug 27 09:34:34 PM UTC 24 |
46865099874 ps |
| T1968 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/48.xbar_error_and_unmapped_addr.3621749290 |
|
|
Aug 27 09:34:01 PM UTC 24 |
Aug 27 09:34:40 PM UTC 24 |
279851464 ps |
| T1969 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/48.xbar_smoke_slow_rsp.3693633783 |
|
|
Aug 27 09:33:32 PM UTC 24 |
Aug 27 09:34:44 PM UTC 24 |
3975129940 ps |
| T1970 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/48.xbar_random_zero_delays.4165059185 |
|
|
Aug 27 09:33:49 PM UTC 24 |
Aug 27 09:34:46 PM UTC 24 |
519065912 ps |
| T1971 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/48.xbar_random.6933068 |
|
|
Aug 27 09:33:35 PM UTC 24 |
Aug 27 09:34:47 PM UTC 24 |
1464728684 ps |
| T1972 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/42.xbar_random_large_delays.1485998142 |
|
|
Aug 27 09:25:49 PM UTC 24 |
Aug 27 09:34:59 PM UTC 24 |
50333186092 ps |
| T1973 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/48.xbar_same_source.2541897404 |
|
|
Aug 27 09:34:03 PM UTC 24 |
Aug 27 09:35:04 PM UTC 24 |
565619523 ps |
| T1974 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/49.xbar_smoke.4036512501 |
|
|
Aug 27 09:34:55 PM UTC 24 |
Aug 27 09:35:05 PM UTC 24 |
43439798 ps |
| T1975 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/44.xbar_random_slow_rsp.1602555093 |
|
|
Aug 27 09:28:19 PM UTC 24 |
Aug 27 09:35:06 PM UTC 24 |
31229287595 ps |
| T1976 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/49.xbar_smoke_zero_delays.1892557122 |
|
|
Aug 27 09:34:57 PM UTC 24 |
Aug 27 09:35:07 PM UTC 24 |
49356486 ps |
| T1977 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/35.xbar_stress_all_with_reset_error.3674814651 |
|
|
Aug 27 09:15:56 PM UTC 24 |
Aug 27 09:35:07 PM UTC 24 |
28609675786 ps |
| T1978 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/35.xbar_random_large_delays.3189512416 |
|
|
Aug 27 09:15:02 PM UTC 24 |
Aug 27 09:35:08 PM UTC 24 |
101428822982 ps |
| T868 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/45.xbar_stress_all_with_rand_reset.1902644049 |
|
|
Aug 27 09:30:01 PM UTC 24 |
Aug 27 09:35:19 PM UTC 24 |
1119292089 ps |
| T1979 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/47.xbar_random_large_delays.1407960984 |
|
|
Aug 27 09:32:06 PM UTC 24 |
Aug 27 09:35:22 PM UTC 24 |
18527466472 ps |
| T1980 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/48.xbar_stress_all.3856424726 |
|
|
Aug 27 09:34:17 PM UTC 24 |
Aug 27 09:35:25 PM UTC 24 |
705704249 ps |
| T1981 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/48.xbar_stress_all_with_error.4121857774 |
|
|
Aug 27 09:34:43 PM UTC 24 |
Aug 27 09:35:25 PM UTC 24 |
1342519514 ps |
| T1982 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/48.xbar_smoke_large_delays.4002156278 |
|
|
Aug 27 09:33:27 PM UTC 24 |
Aug 27 09:35:29 PM UTC 24 |
10042212004 ps |
| T1983 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/48.xbar_error_random.2362740896 |
|
|
Aug 27 09:34:01 PM UTC 24 |
Aug 27 09:35:40 PM UTC 24 |
2413040834 ps |
| T1984 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/47.xbar_stress_all.1833930521 |
|
|
Aug 27 09:32:53 PM UTC 24 |
Aug 27 09:35:42 PM UTC 24 |
4883493403 ps |
| T1985 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/49.xbar_random_zero_delays.3816436881 |
|
|
Aug 27 09:35:10 PM UTC 24 |
Aug 27 09:35:43 PM UTC 24 |
256350148 ps |
| T1986 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/42.xbar_stress_all_with_error.3607910212 |
|
|
Aug 27 09:26:35 PM UTC 24 |
Aug 27 09:35:49 PM UTC 24 |
18377744423 ps |
| T1987 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/49.xbar_error_random.3701608890 |
|
|
Aug 27 09:35:29 PM UTC 24 |
Aug 27 09:35:55 PM UTC 24 |
657059257 ps |
| T1988 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/37.xbar_access_same_device_slow_rsp.2329157021 |
|
|
Aug 27 09:18:02 PM UTC 24 |
Aug 27 09:35:59 PM UTC 24 |
65259055378 ps |
| T1989 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/29.xbar_access_same_device_slow_rsp.2235187405 |
|
|
Aug 27 09:06:03 PM UTC 24 |
Aug 27 09:36:03 PM UTC 24 |
117167346693 ps |
| T1990 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/49.xbar_random.2936336005 |
|
|
Aug 27 09:35:09 PM UTC 24 |
Aug 27 09:36:07 PM UTC 24 |
1296173016 ps |
| T1991 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/49.xbar_error_and_unmapped_addr.4140584287 |
|
|
Aug 27 09:35:40 PM UTC 24 |
Aug 27 09:36:07 PM UTC 24 |
261471435 ps |
| T1992 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/50.xbar_smoke.2978082807 |
|
|
Aug 27 09:36:03 PM UTC 24 |
Aug 27 09:36:13 PM UTC 24 |
46014764 ps |
| T1993 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/50.xbar_smoke_zero_delays.3659921864 |
|
|
Aug 27 09:36:05 PM UTC 24 |
Aug 27 09:36:16 PM UTC 24 |
51713230 ps |
| T1994 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/49.xbar_stress_all_with_rand_reset.2123856529 |
|
|
Aug 27 09:35:48 PM UTC 24 |
Aug 27 09:36:18 PM UTC 24 |
95751714 ps |
| T1995 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/41.xbar_random_slow_rsp.2605360720 |
|
|
Aug 27 09:24:25 PM UTC 24 |
Aug 27 09:36:19 PM UTC 24 |
51017987798 ps |
| T1996 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/49.xbar_same_source.2836403597 |
|
|
Aug 27 09:35:28 PM UTC 24 |
Aug 27 09:36:20 PM UTC 24 |
2037574728 ps |
| T1997 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/48.xbar_stress_all_with_reset_error.758982455 |
|
|
Aug 27 09:34:47 PM UTC 24 |
Aug 27 09:36:24 PM UTC 24 |
635128960 ps |
| T1998 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/49.xbar_smoke_large_delays.1589335164 |
|
|
Aug 27 09:35:04 PM UTC 24 |
Aug 27 09:36:24 PM UTC 24 |
9199027671 ps |
| T1999 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/49.xbar_unmapped_addr.2871308152 |
|
|
Aug 27 09:35:31 PM UTC 24 |
Aug 27 09:36:27 PM UTC 24 |
1006370421 ps |
| T2000 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/49.xbar_smoke_slow_rsp.418909247 |
|
|
Aug 27 09:35:07 PM UTC 24 |
Aug 27 09:36:28 PM UTC 24 |
4991693482 ps |
| T2001 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/49.xbar_access_same_device.1420544585 |
|
|
Aug 27 09:35:28 PM UTC 24 |
Aug 27 09:36:35 PM UTC 24 |
1925798951 ps |
| T2002 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/49.xbar_stress_all_with_error.88867439 |
|
|
Aug 27 09:35:48 PM UTC 24 |
Aug 27 09:36:37 PM UTC 24 |
1200521485 ps |
| T2003 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/46.xbar_stress_all.2578814481 |
|
|
Aug 27 09:31:27 PM UTC 24 |
Aug 27 09:36:42 PM UTC 24 |
10432661057 ps |
| T2004 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/50.xbar_access_same_device.4097837242 |
|
|
Aug 27 09:36:27 PM UTC 24 |
Aug 27 09:36:47 PM UTC 24 |
345041268 ps |
| T2005 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/50.xbar_error_and_unmapped_addr.2489690404 |
|
|
Aug 27 09:36:42 PM UTC 24 |
Aug 27 09:36:54 PM UTC 24 |
87869067 ps |
| T860 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/42.xbar_stress_all_with_rand_reset.3680538150 |
|
|
Aug 27 09:26:28 PM UTC 24 |
Aug 27 09:36:54 PM UTC 24 |
11312216394 ps |
| T2006 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/50.xbar_random_zero_delays.1463535603 |
|
|
Aug 27 09:36:22 PM UTC 24 |
Aug 27 09:36:55 PM UTC 24 |
334562980 ps |
| T2007 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/45.xbar_random_slow_rsp.170429991 |
|
|
Aug 27 09:29:35 PM UTC 24 |
Aug 27 09:37:00 PM UTC 24 |
31276712679 ps |
| T2008 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/50.xbar_unmapped_addr.3563887608 |
|
|
Aug 27 09:36:42 PM UTC 24 |
Aug 27 09:37:04 PM UTC 24 |
103729984 ps |
| T2009 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/50.xbar_same_source.2893034398 |
|
|
Aug 27 09:36:37 PM UTC 24 |
Aug 27 09:37:04 PM UTC 24 |
557224592 ps |
| T2010 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/51.xbar_smoke_zero_delays.3381249313 |
|
|
Aug 27 09:37:00 PM UTC 24 |
Aug 27 09:37:10 PM UTC 24 |
37939299 ps |
| T2011 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/50.xbar_random.4188005650 |
|
|
Aug 27 09:36:18 PM UTC 24 |
Aug 27 09:37:10 PM UTC 24 |
1606433318 ps |
| T2012 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/51.xbar_smoke.1984155391 |
|
|
Aug 27 09:36:58 PM UTC 24 |
Aug 27 09:37:12 PM UTC 24 |
244454162 ps |
| T2013 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/48.xbar_random_large_delays.3421554686 |
|
|
Aug 27 09:33:50 PM UTC 24 |
Aug 27 09:37:17 PM UTC 24 |
20386010630 ps |
| T2014 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/50.xbar_stress_all_with_rand_reset.2670880396 |
|
|
Aug 27 09:36:45 PM UTC 24 |
Aug 27 09:37:19 PM UTC 24 |
88638439 ps |
| T2015 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/50.xbar_smoke_large_delays.834522415 |
|
|
Aug 27 09:36:06 PM UTC 24 |
Aug 27 09:37:20 PM UTC 24 |
6745126554 ps |
| T2016 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/51.xbar_random.1369168759 |
|
|
Aug 27 09:37:16 PM UTC 24 |
Aug 27 09:37:29 PM UTC 24 |
70898657 ps |
| T2017 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/50.xbar_smoke_slow_rsp.193928563 |
|
|
Aug 27 09:36:13 PM UTC 24 |
Aug 27 09:37:34 PM UTC 24 |
5179154723 ps |
| T2018 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/50.xbar_error_random.3740787875 |
|
|
Aug 27 09:36:41 PM UTC 24 |
Aug 27 09:37:42 PM UTC 24 |
1475142984 ps |
| T2019 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/28.xbar_access_same_device_slow_rsp.3747468373 |
|
|
Aug 27 09:04:04 PM UTC 24 |
Aug 27 09:37:46 PM UTC 24 |
137056335277 ps |