| T265 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/default/82.chip_sw_all_escalation_resets.944132739 |
|
|
Aug 28 04:55:38 AM UTC 24 |
Aug 28 05:03:57 AM UTC 24 |
4763375490 ps |
| T1332 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/default/93.chip_sw_all_escalation_resets.40154832 |
|
|
Aug 28 04:55:51 AM UTC 24 |
Aug 28 05:04:02 AM UTC 24 |
5402785824 ps |
| T1333 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/default/85.chip_sw_all_escalation_resets.3531414161 |
|
|
Aug 28 04:55:53 AM UTC 24 |
Aug 28 05:04:16 AM UTC 24 |
5218883804 ps |
| T266 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/default/96.chip_sw_all_escalation_resets.386560636 |
|
|
Aug 28 04:55:46 AM UTC 24 |
Aug 28 05:05:17 AM UTC 24 |
6826373884 ps |
| T1334 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/default/2.rom_e2e_self_hash.2501478773 |
|
|
Aug 28 03:27:46 AM UTC 24 |
Aug 28 05:14:07 AM UTC 24 |
25822089650 ps |
| T1335 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/default/3.chip_sw_csrng_edn_concurrency.3952276318 |
|
|
Aug 28 03:38:51 AM UTC 24 |
Aug 28 05:21:22 AM UTC 24 |
24572599008 ps |
| T1336 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_uart_tx_rx_bootstrap.4208794093 |
|
|
Aug 28 12:44:00 AM UTC 24 |
Aug 28 05:25:13 AM UTC 24 |
80198811480 ps |
| T1337 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_exit_test_unlocked_bootstrap.1758686993 |
|
|
Aug 28 02:09:38 AM UTC 24 |
Aug 28 05:36:42 AM UTC 24 |
60571820960 ps |
| T1338 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_inject_scramble_seed.1898510027 |
|
|
Aug 28 02:09:40 AM UTC 24 |
Aug 28 05:44:35 AM UTC 24 |
67728364866 ps |
| T630 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_csrng_edn_concurrency_reduced_freq.1917294482 |
|
|
Aug 28 01:49:22 AM UTC 24 |
Aug 28 05:57:50 AM UTC 24 |
83740311979 ps |
| T1339 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/default/6.chip_sw_csrng_edn_concurrency.2598819325 |
|
|
Aug 28 03:54:45 AM UTC 24 |
Aug 28 05:59:13 AM UTC 24 |
33913469696 ps |
| T1340 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/default/4.chip_sw_csrng_edn_concurrency.1480865555 |
|
|
Aug 28 03:47:37 AM UTC 24 |
Aug 28 06:02:46 AM UTC 24 |
38077891630 ps |
| T1341 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_uart_tx_rx_bootstrap.2684535848 |
|
|
Aug 28 02:08:35 AM UTC 24 |
Aug 28 06:08:24 AM UTC 24 |
79035255416 ps |
| T1342 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_alert_handler_reverse_ping_in_deep_sleep.151354270 |
|
|
Aug 28 02:48:19 AM UTC 24 |
Aug 28 06:15:24 AM UTC 24 |
254457753136 ps |
| T631 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_csrng_edn_concurrency_reduced_freq.2004916694 |
|
|
Aug 28 03:21:26 AM UTC 24 |
Aug 28 06:48:53 AM UTC 24 |
95009558356 ps |
| T95 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/0.xbar_smoke_zero_delays.1307794740 |
|
|
Aug 27 08:07:48 PM UTC 24 |
Aug 27 08:07:54 PM UTC 24 |
42934146 ps |
| T96 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/0.xbar_smoke.3760590675 |
|
|
Aug 27 08:07:47 PM UTC 24 |
Aug 27 08:07:54 PM UTC 24 |
39457550 ps |
| T97 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/0.xbar_unmapped_addr.2326681955 |
|
|
Aug 27 08:07:54 PM UTC 24 |
Aug 27 08:08:02 PM UTC 24 |
25758321 ps |
| T101 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/1.xbar_smoke_zero_delays.1202705101 |
|
|
Aug 27 08:07:57 PM UTC 24 |
Aug 27 08:08:05 PM UTC 24 |
46202554 ps |
| T162 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/1.xbar_smoke.2834297892 |
|
|
Aug 27 08:07:55 PM UTC 24 |
Aug 27 08:08:05 PM UTC 24 |
193996999 ps |
| T163 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/0.xbar_error_and_unmapped_addr.3786136531 |
|
|
Aug 27 08:07:53 PM UTC 24 |
Aug 27 08:08:14 PM UTC 24 |
209549381 ps |
| T188 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/0.xbar_random_zero_delays.4016204886 |
|
|
Aug 27 08:07:47 PM UTC 24 |
Aug 27 08:08:14 PM UTC 24 |
333250764 ps |
| T189 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/0.xbar_error_random.2369646960 |
|
|
Aug 27 08:07:52 PM UTC 24 |
Aug 27 08:08:15 PM UTC 24 |
315245277 ps |
| T456 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/0.xbar_random.1903900534 |
|
|
Aug 27 08:07:47 PM UTC 24 |
Aug 27 08:08:23 PM UTC 24 |
489477739 ps |
| T551 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/1.xbar_random_zero_delays.1938538868 |
|
|
Aug 27 08:08:01 PM UTC 24 |
Aug 27 08:08:30 PM UTC 24 |
242405473 ps |
| T561 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/1.xbar_unmapped_addr.1462291614 |
|
|
Aug 27 08:08:24 PM UTC 24 |
Aug 27 08:08:36 PM UTC 24 |
71584165 ps |
| T548 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/1.xbar_random.419179621 |
|
|
Aug 27 08:08:02 PM UTC 24 |
Aug 27 08:08:39 PM UTC 24 |
412120139 ps |
| T271 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/0.xbar_same_source.3605929757 |
|
|
Aug 27 08:07:53 PM UTC 24 |
Aug 27 08:08:43 PM UTC 24 |
1714973648 ps |
| T549 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/1.xbar_same_source.2999643474 |
|
|
Aug 27 08:08:14 PM UTC 24 |
Aug 27 08:08:58 PM UTC 24 |
509065030 ps |
| T272 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/0.xbar_stress_all_with_rand_reset.4026469050 |
|
|
Aug 27 08:07:52 PM UTC 24 |
Aug 27 08:09:03 PM UTC 24 |
264510132 ps |
| T478 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/0.xbar_smoke_slow_rsp.3273111747 |
|
|
Aug 27 08:07:46 PM UTC 24 |
Aug 27 08:09:05 PM UTC 24 |
4837366082 ps |
| T457 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/1.xbar_access_same_device.2476452915 |
|
|
Aug 27 08:08:07 PM UTC 24 |
Aug 27 08:09:05 PM UTC 24 |
969485138 ps |
| T562 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/0.xbar_smoke_large_delays.1255167786 |
|
|
Aug 27 08:07:47 PM UTC 24 |
Aug 27 08:09:13 PM UTC 24 |
8617093137 ps |
| T559 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/1.xbar_smoke_slow_rsp.878508089 |
|
|
Aug 27 08:08:01 PM UTC 24 |
Aug 27 08:09:14 PM UTC 24 |
4746195866 ps |
| T460 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/1.xbar_error_and_unmapped_addr.3852860136 |
|
|
Aug 27 08:08:26 PM UTC 24 |
Aug 27 08:09:17 PM UTC 24 |
956789117 ps |
| T568 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/1.xbar_stress_all_with_reset_error.464561713 |
|
|
Aug 27 08:08:37 PM UTC 24 |
Aug 27 08:09:26 PM UTC 24 |
129749149 ps |
| T566 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/2.xbar_smoke_zero_delays.2291198278 |
|
|
Aug 27 08:09:20 PM UTC 24 |
Aug 27 08:09:28 PM UTC 24 |
56174009 ps |
| T565 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/2.xbar_smoke.1822939220 |
|
|
Aug 27 08:09:20 PM UTC 24 |
Aug 27 08:09:34 PM UTC 24 |
227020966 ps |
| T564 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/1.xbar_smoke_large_delays.1101540656 |
|
|
Aug 27 08:07:58 PM UTC 24 |
Aug 27 08:09:45 PM UTC 24 |
9594203239 ps |
| T458 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/1.xbar_error_random.742381550 |
|
|
Aug 27 08:08:16 PM UTC 24 |
Aug 27 08:09:52 PM UTC 24 |
2439611393 ps |
| T555 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/2.xbar_random.321482360 |
|
|
Aug 27 08:09:28 PM UTC 24 |
Aug 27 08:09:54 PM UTC 24 |
646537634 ps |
| T528 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/2.xbar_random_zero_delays.216654898 |
|
|
Aug 27 08:09:33 PM UTC 24 |
Aug 27 08:10:02 PM UTC 24 |
288785538 ps |
| T552 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/2.xbar_error_and_unmapped_addr.972111687 |
|
|
Aug 27 08:09:52 PM UTC 24 |
Aug 27 08:10:10 PM UTC 24 |
91922455 ps |
| T406 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/1.chip_tl_errors.4256600642 |
|
|
Aug 27 08:07:56 PM UTC 24 |
Aug 27 08:10:24 PM UTC 24 |
3212284245 ps |
| T553 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/2.xbar_error_random.2302718326 |
|
|
Aug 27 08:09:50 PM UTC 24 |
Aug 27 08:10:26 PM UTC 24 |
479267555 ps |
| T550 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/0.xbar_access_same_device.3442421851 |
|
|
Aug 27 08:07:47 PM UTC 24 |
Aug 27 08:10:28 PM UTC 24 |
4070186655 ps |
| T554 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/2.xbar_unmapped_addr.5598196 |
|
|
Aug 27 08:09:52 PM UTC 24 |
Aug 27 08:10:30 PM UTC 24 |
621875742 ps |
| T685 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/2.xbar_smoke_slow_rsp.1278731706 |
|
|
Aug 27 08:09:27 PM UTC 24 |
Aug 27 08:10:33 PM UTC 24 |
4007850919 ps |
| T563 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/1.xbar_random_large_delays.3432382513 |
|
|
Aug 27 08:08:03 PM UTC 24 |
Aug 27 08:10:43 PM UTC 24 |
16828478699 ps |
| T558 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/1.xbar_stress_all_with_error.3830545409 |
|
|
Aug 27 08:08:36 PM UTC 24 |
Aug 27 08:10:43 PM UTC 24 |
1883501769 ps |
| T612 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/2.xbar_smoke_large_delays.1798218066 |
|
|
Aug 27 08:09:26 PM UTC 24 |
Aug 27 08:10:57 PM UTC 24 |
7503713371 ps |
| T597 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/3.xbar_smoke_zero_delays.2450109874 |
|
|
Aug 27 08:10:49 PM UTC 24 |
Aug 27 08:10:59 PM UTC 24 |
49691891 ps |
| T1343 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/3.xbar_smoke.3217830554 |
|
|
Aug 27 08:10:50 PM UTC 24 |
Aug 27 08:11:00 PM UTC 24 |
42156703 ps |
| T686 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/2.xbar_access_same_device.3464052010 |
|
|
Aug 27 08:09:43 PM UTC 24 |
Aug 27 08:11:00 PM UTC 24 |
1274805470 ps |
| T446 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/2.xbar_same_source.761311206 |
|
|
Aug 27 08:09:49 PM UTC 24 |
Aug 27 08:11:08 PM UTC 24 |
2444050009 ps |
| T569 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/2.xbar_stress_all_with_error.2239262746 |
|
|
Aug 27 08:10:06 PM UTC 24 |
Aug 27 08:11:15 PM UTC 24 |
938744237 ps |
| T880 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/1.chip_prim_tl_access.4093927278 |
|
|
Aug 27 08:07:57 PM UTC 24 |
Aug 27 08:11:20 PM UTC 24 |
4884973420 ps |
| T567 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/1.xbar_random_slow_rsp.2387581322 |
|
|
Aug 27 08:08:03 PM UTC 24 |
Aug 27 08:11:21 PM UTC 24 |
11363321869 ps |
| T604 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/3.xbar_random.1351436378 |
|
|
Aug 27 08:11:07 PM UTC 24 |
Aug 27 08:11:25 PM UTC 24 |
132288441 ps |
| T874 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/2.xbar_stress_all_with_rand_reset.2043658827 |
|
|
Aug 27 08:10:09 PM UTC 24 |
Aug 27 08:11:28 PM UTC 24 |
17386767 ps |
| T1344 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/3.xbar_random_zero_delays.603433271 |
|
|
Aug 27 08:11:20 PM UTC 24 |
Aug 27 08:11:29 PM UTC 24 |
33985544 ps |
| T556 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/3.xbar_error_random.271205241 |
|
|
Aug 27 08:11:44 PM UTC 24 |
Aug 27 08:11:56 PM UTC 24 |
147578493 ps |
| T560 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/0.xbar_stress_all_with_reset_error.303772585 |
|
|
Aug 27 08:07:52 PM UTC 24 |
Aug 27 08:11:58 PM UTC 24 |
1494613830 ps |
| T545 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/3.xbar_unmapped_addr.4160529418 |
|
|
Aug 27 08:11:44 PM UTC 24 |
Aug 27 08:11:58 PM UTC 24 |
57075334 ps |
| T407 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/0.chip_csr_bit_bash.3514795657 |
|
|
Aug 27 08:07:47 PM UTC 24 |
Aug 27 08:12:09 PM UTC 24 |
3586167223 ps |
| T547 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/3.xbar_same_source.3029157133 |
|
|
Aug 27 08:11:37 PM UTC 24 |
Aug 27 08:12:14 PM UTC 24 |
409463960 ps |
| T1345 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/3.xbar_smoke_large_delays.2920397516 |
|
|
Aug 27 08:10:56 PM UTC 24 |
Aug 27 08:12:15 PM UTC 24 |
7795664388 ps |
| T557 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/0.chip_tl_errors.3809140087 |
|
|
Aug 27 08:07:48 PM UTC 24 |
Aug 27 08:12:17 PM UTC 24 |
3795982286 ps |
| T641 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/3.xbar_error_and_unmapped_addr.2355308933 |
|
|
Aug 27 08:11:43 PM UTC 24 |
Aug 27 08:12:18 PM UTC 24 |
251774032 ps |
| T433 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/0.xbar_stress_all.4210451640 |
|
|
Aug 27 08:07:52 PM UTC 24 |
Aug 27 08:12:21 PM UTC 24 |
6298303151 ps |
| T842 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/3.xbar_smoke_slow_rsp.387609808 |
|
|
Aug 27 08:11:07 PM UTC 24 |
Aug 27 08:12:22 PM UTC 24 |
4658486132 ps |
| T174 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/1.chip_csr_hw_reset.2634006721 |
|
|
Aug 27 08:08:35 PM UTC 24 |
Aug 27 08:12:33 PM UTC 24 |
4135319250 ps |
| T621 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/4.xbar_smoke.152750243 |
|
|
Aug 27 08:12:37 PM UTC 24 |
Aug 27 08:12:47 PM UTC 24 |
43941277 ps |
| T385 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/0.chip_csr_rw.107226107 |
|
|
Aug 27 08:07:52 PM UTC 24 |
Aug 27 08:12:48 PM UTC 24 |
3670827016 ps |
| T1346 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/4.xbar_smoke_zero_delays.1639069317 |
|
|
Aug 27 08:12:41 PM UTC 24 |
Aug 27 08:12:50 PM UTC 24 |
49990055 ps |
| T576 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/3.xbar_random_slow_rsp.3056177406 |
|
|
Aug 27 08:11:22 PM UTC 24 |
Aug 27 08:12:58 PM UTC 24 |
5861870116 ps |
| T1347 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/4.xbar_random_zero_delays.3866130975 |
|
|
Aug 27 08:12:51 PM UTC 24 |
Aug 27 08:13:00 PM UTC 24 |
34740783 ps |
| T474 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/2.xbar_stress_all.3572538076 |
|
|
Aug 27 08:09:56 PM UTC 24 |
Aug 27 08:13:03 PM UTC 24 |
5851730223 ps |
| T826 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/4.xbar_access_same_device.3102069029 |
|
|
Aug 27 08:13:08 PM UTC 24 |
Aug 27 08:13:18 PM UTC 24 |
61350919 ps |
| T482 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/3.xbar_access_same_device.394640801 |
|
|
Aug 27 08:11:21 PM UTC 24 |
Aug 27 08:13:25 PM UTC 24 |
2618110845 ps |
| T178 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/0.chip_csr_hw_reset.1609158662 |
|
|
Aug 27 08:07:51 PM UTC 24 |
Aug 27 08:13:28 PM UTC 24 |
6212203747 ps |
| T1348 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/4.xbar_error_and_unmapped_addr.858135808 |
|
|
Aug 27 08:13:25 PM UTC 24 |
Aug 27 08:13:36 PM UTC 24 |
95859973 ps |
| T579 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/4.xbar_same_source.2658532969 |
|
|
Aug 27 08:13:10 PM UTC 24 |
Aug 27 08:13:36 PM UTC 24 |
250857080 ps |
| T573 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/2.chip_tl_errors.3434448230 |
|
|
Aug 27 08:08:58 PM UTC 24 |
Aug 27 08:13:37 PM UTC 24 |
3930695336 ps |
| T800 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/3.xbar_stress_all_with_error.3189558467 |
|
|
Aug 27 08:11:48 PM UTC 24 |
Aug 27 08:13:43 PM UTC 24 |
2491907390 ps |
| T1349 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/0.chip_prim_tl_access.2047870877 |
|
|
Aug 27 08:07:48 PM UTC 24 |
Aug 27 08:14:01 PM UTC 24 |
6983577623 ps |
| T793 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/2.xbar_access_same_device_slow_rsp.1387137099 |
|
|
Aug 27 08:09:47 PM UTC 24 |
Aug 27 08:14:06 PM UTC 24 |
20549404114 ps |
| T483 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/4.xbar_unmapped_addr.2918622656 |
|
|
Aug 27 08:13:22 PM UTC 24 |
Aug 27 08:14:11 PM UTC 24 |
804663066 ps |
| T1350 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/4.xbar_smoke_large_delays.2942148885 |
|
|
Aug 27 08:12:40 PM UTC 24 |
Aug 27 08:14:15 PM UTC 24 |
5893417218 ps |
| T182 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/2.chip_csr_rw.293428827 |
|
|
Aug 27 08:10:17 PM UTC 24 |
Aug 27 08:14:15 PM UTC 24 |
3739074684 ps |
| T794 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/3.xbar_stress_all_with_reset_error.4273342302 |
|
|
Aug 27 08:11:50 PM UTC 24 |
Aug 27 08:14:16 PM UTC 24 |
554812571 ps |
| T643 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/4.xbar_error_random.1786376396 |
|
|
Aug 27 08:13:21 PM UTC 24 |
Aug 27 08:14:22 PM UTC 24 |
596653066 ps |
| T590 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/4.xbar_random.4123862823 |
|
|
Aug 27 08:12:44 PM UTC 24 |
Aug 27 08:14:27 PM UTC 24 |
2337465573 ps |
| T479 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/4.xbar_smoke_slow_rsp.802102213 |
|
|
Aug 27 08:12:45 PM UTC 24 |
Aug 27 08:14:32 PM UTC 24 |
4678611996 ps |
| T824 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/0.xbar_access_same_device_slow_rsp.2607886495 |
|
|
Aug 27 08:07:50 PM UTC 24 |
Aug 27 08:14:34 PM UTC 24 |
26020813456 ps |
| T593 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/5.xbar_smoke.4139076593 |
|
|
Aug 27 08:14:33 PM UTC 24 |
Aug 27 08:14:47 PM UTC 24 |
193639794 ps |
| T625 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/5.xbar_smoke_zero_delays.1093030630 |
|
|
Aug 27 08:14:37 PM UTC 24 |
Aug 27 08:14:48 PM UTC 24 |
48912054 ps |
| T644 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/0.xbar_stress_all_with_error.1057537221 |
|
|
Aug 27 08:07:51 PM UTC 24 |
Aug 27 08:15:06 PM UTC 24 |
13665573801 ps |
| T645 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/2.xbar_stress_all_with_reset_error.2228974023 |
|
|
Aug 27 08:10:09 PM UTC 24 |
Aug 27 08:15:18 PM UTC 24 |
2345267195 ps |
| T841 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/5.xbar_access_same_device.322416768 |
|
|
Aug 27 08:15:09 PM UTC 24 |
Aug 27 08:15:24 PM UTC 24 |
60805574 ps |
| T1351 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/2.chip_prim_tl_access.944338809 |
|
|
Aug 27 08:08:59 PM UTC 24 |
Aug 27 08:15:25 PM UTC 24 |
9688993554 ps |
| T646 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/4.xbar_stress_all_with_error.3803893498 |
|
|
Aug 27 08:13:47 PM UTC 24 |
Aug 27 08:15:30 PM UTC 24 |
2341808699 ps |
| T172 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/2.chip_csr_hw_reset.3996587366 |
|
|
Aug 27 08:10:15 PM UTC 24 |
Aug 27 08:15:37 PM UTC 24 |
4957904522 ps |
| T476 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/1.xbar_stress_all_with_rand_reset.3791456401 |
|
|
Aug 27 08:08:31 PM UTC 24 |
Aug 27 08:15:41 PM UTC 24 |
8075935829 ps |
| T513 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/5.xbar_random.80246234 |
|
|
Aug 27 08:14:45 PM UTC 24 |
Aug 27 08:15:44 PM UTC 24 |
570207697 ps |
| T1352 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/0.chip_rv_dm_lc_disabled.1054460870 |
|
|
Aug 27 08:07:47 PM UTC 24 |
Aug 27 08:15:49 PM UTC 24 |
10770330780 ps |
| T411 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/0.chip_csr_mem_rw_with_rand_reset.3103753933 |
|
|
Aug 27 08:07:53 PM UTC 24 |
Aug 27 08:15:51 PM UTC 24 |
6621355716 ps |
| T1353 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/5.xbar_error_and_unmapped_addr.3890500640 |
|
|
Aug 27 08:15:47 PM UTC 24 |
Aug 27 08:15:53 PM UTC 24 |
18624184 ps |
| T575 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/4.chip_tl_errors.3537364096 |
|
|
Aug 27 08:12:34 PM UTC 24 |
Aug 27 08:15:56 PM UTC 24 |
3445797679 ps |
| T523 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/5.xbar_random_zero_delays.3372030566 |
|
|
Aug 27 08:14:51 PM UTC 24 |
Aug 27 08:15:57 PM UTC 24 |
573602080 ps |
| T589 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/5.xbar_same_source.3053116035 |
|
|
Aug 27 08:15:29 PM UTC 24 |
Aug 27 08:16:06 PM UTC 24 |
432214803 ps |
| T839 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/5.xbar_smoke_slow_rsp.1061137586 |
|
|
Aug 27 08:14:39 PM UTC 24 |
Aug 27 08:16:16 PM UTC 24 |
5035655041 ps |
| T1354 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/6.xbar_smoke.4280129458 |
|
|
Aug 27 08:16:20 PM UTC 24 |
Aug 27 08:16:30 PM UTC 24 |
46103762 ps |
| T587 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/4.xbar_stress_all.1416668984 |
|
|
Aug 27 08:13:40 PM UTC 24 |
Aug 27 08:16:36 PM UTC 24 |
4645762183 ps |
| T1355 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/6.xbar_smoke_zero_delays.35773565 |
|
|
Aug 27 08:16:28 PM UTC 24 |
Aug 27 08:16:38 PM UTC 24 |
44079428 ps |
| T850 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/4.xbar_stress_all_with_rand_reset.632279559 |
|
|
Aug 27 08:13:47 PM UTC 24 |
Aug 27 08:16:40 PM UTC 24 |
302496623 ps |
| T1356 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/2.chip_rv_dm_lc_disabled.2830600038 |
|
|
Aug 27 08:09:05 PM UTC 24 |
Aug 27 08:16:42 PM UTC 24 |
17197635809 ps |
| T608 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/5.xbar_unmapped_addr.1029919432 |
|
|
Aug 27 08:15:43 PM UTC 24 |
Aug 27 08:16:42 PM UTC 24 |
1098947741 ps |
| T1357 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/5.xbar_stress_all_with_reset_error.925513993 |
|
|
Aug 27 08:16:06 PM UTC 24 |
Aug 27 08:16:43 PM UTC 24 |
60821093 ps |
| T1358 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/5.xbar_smoke_large_delays.79429853 |
|
|
Aug 27 08:14:38 PM UTC 24 |
Aug 27 08:16:47 PM UTC 24 |
8774396801 ps |
| T424 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/3.chip_csr_rw.999680923 |
|
|
Aug 27 08:11:59 PM UTC 24 |
Aug 27 08:16:49 PM UTC 24 |
4283759556 ps |
| T1359 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/5.xbar_error_random.97848093 |
|
|
Aug 27 08:15:40 PM UTC 24 |
Aug 27 08:16:57 PM UTC 24 |
1837246893 ps |
| T425 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/1.chip_csr_rw.220401124 |
|
|
Aug 27 08:08:36 PM UTC 24 |
Aug 27 08:17:00 PM UTC 24 |
5550779220 ps |
| T1360 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/4.xbar_random_large_delays.4013756754 |
|
|
Aug 27 08:12:57 PM UTC 24 |
Aug 27 08:17:04 PM UTC 24 |
19042569431 ps |
| T836 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/6.xbar_access_same_device.3668897375 |
|
|
Aug 27 08:17:03 PM UTC 24 |
Aug 27 08:17:14 PM UTC 24 |
66560654 ps |
| T1361 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/6.xbar_error_and_unmapped_addr.1876904171 |
|
|
Aug 27 08:17:20 PM UTC 24 |
Aug 27 08:17:35 PM UTC 24 |
172628941 ps |
| T522 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/6.xbar_same_source.583351240 |
|
|
Aug 27 08:17:09 PM UTC 24 |
Aug 27 08:17:39 PM UTC 24 |
1046572407 ps |
| T647 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/6.xbar_error_random.3914023565 |
|
|
Aug 27 08:17:10 PM UTC 24 |
Aug 27 08:17:43 PM UTC 24 |
273763593 ps |
| T611 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/6.xbar_unmapped_addr.4146003715 |
|
|
Aug 27 08:17:18 PM UTC 24 |
Aug 27 08:17:48 PM UTC 24 |
525813752 ps |
| T477 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/1.xbar_stress_all.1460737829 |
|
|
Aug 27 08:08:25 PM UTC 24 |
Aug 27 08:17:55 PM UTC 24 |
16146151104 ps |
| T176 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/3.chip_csr_hw_reset.2301565284 |
|
|
Aug 27 08:11:51 PM UTC 24 |
Aug 27 08:18:01 PM UTC 24 |
5692661120 ps |
| T588 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/6.xbar_random_zero_delays.1370010127 |
|
|
Aug 27 08:16:58 PM UTC 24 |
Aug 27 08:18:07 PM UTC 24 |
540975522 ps |
| T574 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/5.chip_tl_errors.653961098 |
|
|
Aug 27 08:14:28 PM UTC 24 |
Aug 27 08:18:09 PM UTC 24 |
3769183134 ps |
| T1362 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/6.xbar_stress_all_with_error.1453534768 |
|
|
Aug 27 08:17:54 PM UTC 24 |
Aug 27 08:18:16 PM UTC 24 |
217781444 ps |
| T606 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/6.xbar_random.3093796264 |
|
|
Aug 27 08:16:58 PM UTC 24 |
Aug 27 08:18:18 PM UTC 24 |
1713384060 ps |
| T177 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/4.chip_csr_hw_reset.2103918615 |
|
|
Aug 27 08:13:59 PM UTC 24 |
Aug 27 08:18:20 PM UTC 24 |
5119494415 ps |
| T412 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/3.chip_tl_errors.2813018504 |
|
|
Aug 27 08:10:49 PM UTC 24 |
Aug 27 08:18:20 PM UTC 24 |
4490986595 ps |
| T471 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/6.xbar_smoke_large_delays.3889661163 |
|
|
Aug 27 08:16:38 PM UTC 24 |
Aug 27 08:18:36 PM UTC 24 |
7126547592 ps |
| T1363 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/7.xbar_smoke_zero_delays.879999826 |
|
|
Aug 27 08:18:32 PM UTC 24 |
Aug 27 08:18:42 PM UTC 24 |
47321519 ps |
| T1364 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/7.xbar_smoke.2468176268 |
|
|
Aug 27 08:18:30 PM UTC 24 |
Aug 27 08:18:42 PM UTC 24 |
157697331 ps |
| T1365 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/1.chip_rv_dm_lc_disabled.1486154005 |
|
|
Aug 27 08:07:54 PM UTC 24 |
Aug 27 08:18:47 PM UTC 24 |
15404725465 ps |
| T790 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/5.xbar_stress_all_with_error.685221214 |
|
|
Aug 27 08:16:04 PM UTC 24 |
Aug 27 08:18:54 PM UTC 24 |
2148687504 ps |
| T1366 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/6.xbar_smoke_slow_rsp.2217039241 |
|
|
Aug 27 08:16:52 PM UTC 24 |
Aug 27 08:18:54 PM UTC 24 |
5715779904 ps |
| T480 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/3.xbar_stress_all.2370881635 |
|
|
Aug 27 08:11:44 PM UTC 24 |
Aug 27 08:19:05 PM UTC 24 |
11544153162 ps |
| T670 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/7.xbar_random.4017252594 |
|
|
Aug 27 08:18:40 PM UTC 24 |
Aug 27 08:19:11 PM UTC 24 |
877782599 ps |
| T1367 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/2.chip_csr_bit_bash.231147178 |
|
|
Aug 27 08:08:33 PM UTC 24 |
Aug 27 08:19:12 PM UTC 24 |
7389606208 ps |
| T426 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/3.chip_csr_mem_rw_with_rand_reset.3313865975 |
|
|
Aug 27 08:12:19 PM UTC 24 |
Aug 27 08:19:18 PM UTC 24 |
5777520362 ps |
| T502 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/7.xbar_same_source.254713029 |
|
|
Aug 27 08:19:07 PM UTC 24 |
Aug 27 08:19:21 PM UTC 24 |
68371764 ps |
| T540 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/3.xbar_stress_all_with_rand_reset.701721603 |
|
|
Aug 27 08:11:47 PM UTC 24 |
Aug 27 08:19:23 PM UTC 24 |
8649098750 ps |
| T591 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/7.xbar_random_zero_delays.3279773883 |
|
|
Aug 27 08:18:43 PM UTC 24 |
Aug 27 08:19:38 PM UTC 24 |
597619261 ps |
| T605 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/7.xbar_smoke_large_delays.3558129106 |
|
|
Aug 27 08:18:37 PM UTC 24 |
Aug 27 08:19:40 PM UTC 24 |
6013545627 ps |
| T1368 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/7.xbar_error_and_unmapped_addr.4110470086 |
|
|
Aug 27 08:19:26 PM UTC 24 |
Aug 27 08:19:43 PM UTC 24 |
246581070 ps |
| T1369 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/7.xbar_error_random.3054871698 |
|
|
Aug 27 08:19:17 PM UTC 24 |
Aug 27 08:19:51 PM UTC 24 |
650305721 ps |
| T1370 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/7.xbar_unmapped_addr.3565474127 |
|
|
Aug 27 08:19:16 PM UTC 24 |
Aug 27 08:19:52 PM UTC 24 |
702712811 ps |
| T1371 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/7.xbar_smoke_slow_rsp.158068254 |
|
|
Aug 27 08:18:40 PM UTC 24 |
Aug 27 08:19:54 PM UTC 24 |
4713811259 ps |
| T618 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/7.xbar_stress_all.3915666002 |
|
|
Aug 27 08:19:33 PM UTC 24 |
Aug 27 08:19:59 PM UTC 24 |
253717520 ps |
| T1372 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/5.xbar_random_slow_rsp.1735951344 |
|
|
Aug 27 08:14:57 PM UTC 24 |
Aug 27 08:20:08 PM UTC 24 |
21274309281 ps |
| T1373 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/8.xbar_smoke.2683572594 |
|
|
Aug 27 08:20:13 PM UTC 24 |
Aug 27 08:20:23 PM UTC 24 |
202296171 ps |
| T624 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/8.xbar_smoke_zero_delays.2385670405 |
|
|
Aug 27 08:20:14 PM UTC 24 |
Aug 27 08:20:24 PM UTC 24 |
52301741 ps |
| T580 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/9.xbar_random.2956892761 |
|
|
Aug 27 08:23:01 PM UTC 24 |
Aug 27 08:23:31 PM UTC 24 |
346501308 ps |
| T1374 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/7.xbar_random_large_delays.1362627666 |
|
|
Aug 27 08:18:43 PM UTC 24 |
Aug 27 08:20:25 PM UTC 24 |
7364660802 ps |
| T534 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/6.xbar_stress_all.2421631050 |
|
|
Aug 27 08:17:23 PM UTC 24 |
Aug 27 08:20:40 PM UTC 24 |
5263218880 ps |
| T542 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/5.xbar_stress_all_with_rand_reset.254772936 |
|
|
Aug 27 08:15:59 PM UTC 24 |
Aug 27 08:20:52 PM UTC 24 |
5866668249 ps |
| T472 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/7.xbar_access_same_device.3915287388 |
|
|
Aug 27 08:19:04 PM UTC 24 |
Aug 27 08:20:53 PM UTC 24 |
2387601067 ps |
| T592 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/5.xbar_stress_all.1102310894 |
|
|
Aug 27 08:15:53 PM UTC 24 |
Aug 27 08:21:10 PM UTC 24 |
8262151413 ps |
| T823 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/8.xbar_access_same_device.1501677401 |
|
|
Aug 27 08:21:02 PM UTC 24 |
Aug 27 08:21:24 PM UTC 24 |
522493232 ps |
| T602 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/8.xbar_random.2928162089 |
|
|
Aug 27 08:20:31 PM UTC 24 |
Aug 27 08:21:27 PM UTC 24 |
1656938492 ps |
| T648 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/4.xbar_stress_all_with_reset_error.699838627 |
|
|
Aug 27 08:13:57 PM UTC 24 |
Aug 27 08:21:34 PM UTC 24 |
4552045131 ps |
| T616 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/8.xbar_random_zero_delays.165507967 |
|
|
Aug 27 08:20:45 PM UTC 24 |
Aug 27 08:21:38 PM UTC 24 |
448813581 ps |
| T577 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/6.chip_tl_errors.4279660198 |
|
|
Aug 27 08:16:17 PM UTC 24 |
Aug 27 08:21:40 PM UTC 24 |
3579484696 ps |
| T599 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/8.xbar_same_source.1641444781 |
|
|
Aug 27 08:21:12 PM UTC 24 |
Aug 27 08:21:50 PM UTC 24 |
380985658 ps |
| T1375 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/8.xbar_smoke_slow_rsp.3531876861 |
|
|
Aug 27 08:20:21 PM UTC 24 |
Aug 27 08:22:02 PM UTC 24 |
4674146047 ps |
| T795 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/7.xbar_stress_all_with_reset_error.2762113218 |
|
|
Aug 27 08:19:43 PM UTC 24 |
Aug 27 08:22:02 PM UTC 24 |
2153870861 ps |
| T473 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/6.xbar_stress_all_with_rand_reset.1953497147 |
|
|
Aug 27 08:17:36 PM UTC 24 |
Aug 27 08:22:04 PM UTC 24 |
3466456855 ps |
| T584 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/7.chip_tl_errors.3464938999 |
|
|
Aug 27 08:18:21 PM UTC 24 |
Aug 27 08:22:05 PM UTC 24 |
3262294277 ps |
| T1376 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/8.xbar_error_and_unmapped_addr.493156656 |
|
|
Aug 27 08:21:47 PM UTC 24 |
Aug 27 08:22:05 PM UTC 24 |
300996770 ps |
| T1377 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/8.xbar_smoke_large_delays.268741630 |
|
|
Aug 27 08:20:15 PM UTC 24 |
Aug 27 08:22:12 PM UTC 24 |
7584644084 ps |
| T1378 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/8.xbar_error_random.2118274497 |
|
|
Aug 27 08:21:31 PM UTC 24 |
Aug 27 08:22:20 PM UTC 24 |
1000723578 ps |
| T1379 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/8.xbar_unmapped_addr.1544452795 |
|
|
Aug 27 08:21:47 PM UTC 24 |
Aug 27 08:22:34 PM UTC 24 |
1076194162 ps |
| T600 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/0.xbar_random_slow_rsp.1964106195 |
|
|
Aug 27 08:07:47 PM UTC 24 |
Aug 27 08:22:39 PM UTC 24 |
63324084167 ps |
| T601 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/9.xbar_smoke.3617062013 |
|
|
Aug 27 08:22:28 PM UTC 24 |
Aug 27 08:22:40 PM UTC 24 |
174292509 ps |
| T1380 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/9.xbar_smoke_zero_delays.2638531305 |
|
|
Aug 27 08:22:34 PM UTC 24 |
Aug 27 08:22:44 PM UTC 24 |
44437338 ps |
| T520 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/0.xbar_random_large_delays.3525576107 |
|
|
Aug 27 08:07:49 PM UTC 24 |
Aug 27 08:23:02 PM UTC 24 |
83590313994 ps |
| T869 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/6.xbar_stress_all_with_reset_error.1344675863 |
|
|
Aug 27 08:18:02 PM UTC 24 |
Aug 27 08:23:07 PM UTC 24 |
2639769948 ps |
| T427 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/1.chip_csr_mem_rw_with_rand_reset.1845174938 |
|
|
Aug 27 08:08:33 PM UTC 24 |
Aug 27 08:23:09 PM UTC 24 |
9750826515 ps |
| T1381 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/2.xbar_random_large_delays.2744490094 |
|
|
Aug 27 08:09:35 PM UTC 24 |
Aug 27 08:23:13 PM UTC 24 |
80434417051 ps |
| T849 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/8.xbar_stress_all_with_reset_error.2821518150 |
|
|
Aug 27 08:22:11 PM UTC 24 |
Aug 27 08:23:26 PM UTC 24 |
158722625 ps |
| T428 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/5.chip_csr_rw.102387864 |
|
|
Aug 27 08:16:11 PM UTC 24 |
Aug 27 08:23:34 PM UTC 24 |
6060163981 ps |
| T1382 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/9.xbar_error_random.2990849103 |
|
|
Aug 27 08:23:49 PM UTC 24 |
Aug 27 08:24:01 PM UTC 24 |
61978492 ps |
| T491 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/9.xbar_random_zero_delays.1939572946 |
|
|
Aug 27 08:23:03 PM UTC 24 |
Aug 27 08:24:04 PM UTC 24 |
503579204 ps |
| T613 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/9.xbar_unmapped_addr.1538606067 |
|
|
Aug 27 08:23:54 PM UTC 24 |
Aug 27 08:24:12 PM UTC 24 |
201479808 ps |
| T851 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/8.xbar_stress_all_with_rand_reset.1469751353 |
|
|
Aug 27 08:22:00 PM UTC 24 |
Aug 27 08:24:21 PM UTC 24 |
358086198 ps |
| T1383 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/9.xbar_error_and_unmapped_addr.77969510 |
|
|
Aug 27 08:23:56 PM UTC 24 |
Aug 27 08:24:30 PM UTC 24 |
638966590 ps |
| T1384 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/9.xbar_same_source.374127614 |
|
|
Aug 27 08:23:36 PM UTC 24 |
Aug 27 08:24:34 PM UTC 24 |
1444994692 ps |
| T434 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/2.chip_csr_mem_rw_with_rand_reset.91786403 |
|
|
Aug 27 08:10:25 PM UTC 24 |
Aug 27 08:24:38 PM UTC 24 |
12218773879 ps |
| T807 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/5.xbar_access_same_device_slow_rsp.2081549206 |
|
|
Aug 27 08:15:10 PM UTC 24 |
Aug 27 08:24:46 PM UTC 24 |
38675762019 ps |
| T578 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/9.xbar_smoke_large_delays.1669902097 |
|
|
Aug 27 08:22:43 PM UTC 24 |
Aug 27 08:24:52 PM UTC 24 |
8539438832 ps |
| T461 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/6.chip_csr_rw.1439055557 |
|
|
Aug 27 08:18:03 PM UTC 24 |
Aug 27 08:24:54 PM UTC 24 |
3848522646 ps |
| T514 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/9.xbar_access_same_device.1681728925 |
|
|
Aug 27 08:23:29 PM UTC 24 |
Aug 27 08:24:56 PM UTC 24 |
1135403122 ps |
| T796 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/1.xbar_access_same_device_slow_rsp.477827703 |
|
|
Aug 27 08:08:10 PM UTC 24 |
Aug 27 08:25:02 PM UTC 24 |
67281254537 ps |
| T810 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/7.xbar_stress_all_with_error.1044130488 |
|
|
Aug 27 08:19:41 PM UTC 24 |
Aug 27 08:25:04 PM UTC 24 |
8680399364 ps |
| T852 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/9.xbar_stress_all_with_rand_reset.1563249887 |
|
|
Aug 27 08:24:26 PM UTC 24 |
Aug 27 08:25:07 PM UTC 24 |
70900020 ps |
| T1385 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/9.xbar_smoke_slow_rsp.4080668664 |
|
|
Aug 27 08:22:57 PM UTC 24 |
Aug 27 08:25:18 PM UTC 24 |
6285441225 ps |
| T581 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/8.chip_tl_errors.4215626448 |
|
|
Aug 27 08:20:05 PM UTC 24 |
Aug 27 08:25:20 PM UTC 24 |
3803924672 ps |
| T1386 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/9.xbar_stress_all.3328312136 |
|
|
Aug 27 08:24:23 PM UTC 24 |
Aug 27 08:25:20 PM UTC 24 |
497029093 ps |
| T526 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/4.xbar_random_slow_rsp.2205118592 |
|
|
Aug 27 08:13:03 PM UTC 24 |
Aug 27 08:25:20 PM UTC 24 |
54289053392 ps |
| T1387 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/10.xbar_smoke.1477439122 |
|
|
Aug 27 08:25:15 PM UTC 24 |
Aug 27 08:25:21 PM UTC 24 |
42080211 ps |
| T1388 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/10.xbar_smoke_zero_delays.775387867 |
|
|
Aug 27 08:25:16 PM UTC 24 |
Aug 27 08:25:26 PM UTC 24 |
59749172 ps |
| T463 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/4.chip_csr_rw.210101783 |
|
|
Aug 27 08:13:58 PM UTC 24 |
Aug 27 08:25:41 PM UTC 24 |
5322245787 ps |
| T537 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/10.xbar_random.1036592197 |
|
|
Aug 27 08:25:24 PM UTC 24 |
Aug 27 08:25:44 PM UTC 24 |
420127328 ps |
| T1389 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/7.xbar_random_slow_rsp.1476875576 |
|
|
Aug 27 08:19:00 PM UTC 24 |
Aug 27 08:25:44 PM UTC 24 |
18146889234 ps |
| T1390 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/10.xbar_error_random.642943534 |
|
|
Aug 27 08:25:46 PM UTC 24 |
Aug 27 08:26:02 PM UTC 24 |
100165971 ps |
| T521 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/10.xbar_random_zero_delays.275277077 |
|
|
Aug 27 08:25:28 PM UTC 24 |
Aug 27 08:26:12 PM UTC 24 |
452852149 ps |
| T1391 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/10.xbar_unmapped_addr.2674326532 |
|
|
Aug 27 08:26:05 PM UTC 24 |
Aug 27 08:26:12 PM UTC 24 |
36585428 ps |
| T1392 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/7.chip_csr_rw.92415346 |
|
|
Aug 27 08:19:45 PM UTC 24 |
Aug 27 08:26:23 PM UTC 24 |
4195151630 ps |
| T1393 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/10.xbar_error_and_unmapped_addr.38633725 |
|
|
Aug 27 08:26:07 PM UTC 24 |
Aug 27 08:26:23 PM UTC 24 |
230666507 ps |
| T1394 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/10.xbar_smoke_slow_rsp.1972931337 |
|
|
Aug 27 08:25:24 PM UTC 24 |
Aug 27 08:26:35 PM UTC 24 |
4685426745 ps |
| T607 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/8.xbar_stress_all_with_error.3896095772 |
|
|
Aug 27 08:22:04 PM UTC 24 |
Aug 27 08:26:38 PM UTC 24 |
7515763388 ps |
| T1395 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/10.xbar_same_source.1505601370 |
|
|
Aug 27 08:25:41 PM UTC 24 |
Aug 27 08:26:39 PM UTC 24 |
1753827645 ps |
| T583 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/2.xbar_random_slow_rsp.757756334 |
|
|
Aug 27 08:09:38 PM UTC 24 |
Aug 27 08:26:55 PM UTC 24 |
69433519437 ps |
| T871 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/10.xbar_stress_all_with_reset_error.2428237309 |
|
|
Aug 27 08:26:34 PM UTC 24 |
Aug 27 08:26:59 PM UTC 24 |
45422156 ps |
| T1396 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/10.xbar_smoke_large_delays.2901058900 |
|
|
Aug 27 08:25:19 PM UTC 24 |
Aug 27 08:27:00 PM UTC 24 |
8258751958 ps |
| T1397 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/11.xbar_smoke.743014719 |
|
|
Aug 27 08:27:00 PM UTC 24 |
Aug 27 08:27:09 PM UTC 24 |
48885292 ps |
| T1398 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/11.xbar_smoke_zero_delays.1387556797 |
|
|
Aug 27 08:27:01 PM UTC 24 |
Aug 27 08:27:11 PM UTC 24 |
43864820 ps |
| T507 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/3.xbar_random_large_delays.4203079130 |
|
|
Aug 27 08:11:20 PM UTC 24 |
Aug 27 08:27:19 PM UTC 24 |
86220765294 ps |
| T797 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/10.xbar_access_same_device.3624140726 |
|
|
Aug 27 08:25:38 PM UTC 24 |
Aug 27 08:27:22 PM UTC 24 |
2124847900 ps |
| T622 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/9.xbar_stress_all_with_error.1492592892 |
|
|
Aug 27 08:24:35 PM UTC 24 |
Aug 27 08:27:36 PM UTC 24 |
6518581940 ps |
| T466 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/9.xbar_access_same_device_slow_rsp.1244409366 |
|
|
Aug 27 08:23:32 PM UTC 24 |
Aug 27 08:27:39 PM UTC 24 |
16081213871 ps |
| T798 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/11.xbar_access_same_device.4252350750 |
|
|
Aug 27 08:27:45 PM UTC 24 |
Aug 27 08:28:20 PM UTC 24 |
800790769 ps |
| T492 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/5.xbar_random_large_delays.67883197 |
|
|
Aug 27 08:14:54 PM UTC 24 |
Aug 27 08:28:22 PM UTC 24 |
79617571254 ps |
| T1399 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/11.xbar_random.1277688557 |
|
|
Aug 27 08:27:21 PM UTC 24 |
Aug 27 08:28:22 PM UTC 24 |
1317171481 ps |
| T462 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/6.chip_csr_mem_rw_with_rand_reset.1538536834 |
|
|
Aug 27 08:18:11 PM UTC 24 |
Aug 27 08:28:22 PM UTC 24 |
6397423485 ps |
| T595 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/11.xbar_random_zero_delays.2467193431 |
|
|
Aug 27 08:27:32 PM UTC 24 |
Aug 27 08:28:26 PM UTC 24 |
467831787 ps |
| T469 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/8.xbar_stress_all.1034142571 |
|
|
Aug 27 08:21:57 PM UTC 24 |
Aug 27 08:28:26 PM UTC 24 |
12084558002 ps |
| T596 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/11.xbar_same_source.1802159889 |
|
|
Aug 27 08:28:02 PM UTC 24 |
Aug 27 08:28:47 PM UTC 24 |
391293562 ps |
| T449 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/8.chip_csr_rw.297892982 |
|
|
Aug 27 08:22:25 PM UTC 24 |
Aug 27 08:28:48 PM UTC 24 |
4841309592 ps |
| T594 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/7.xbar_stress_all_with_rand_reset.2650325651 |
|
|
Aug 27 08:19:35 PM UTC 24 |
Aug 27 08:28:49 PM UTC 24 |
8168267081 ps |
| T620 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/11.xbar_random_large_delays.3786286328 |
|
|
Aug 27 08:27:34 PM UTC 24 |
Aug 27 08:28:54 PM UTC 24 |
5293256544 ps |
| T1400 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/11.xbar_smoke_large_delays.629445906 |
|
|
Aug 27 08:27:16 PM UTC 24 |
Aug 27 08:28:56 PM UTC 24 |
10504575328 ps |
| T1401 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/11.xbar_unmapped_addr.1954966019 |
|
|
Aug 27 08:28:41 PM UTC 24 |
Aug 27 08:29:10 PM UTC 24 |
247200777 ps |
| T623 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/10.xbar_random_slow_rsp.4225486787 |
|
|
Aug 27 08:25:36 PM UTC 24 |
Aug 27 08:29:11 PM UTC 24 |
12096852007 ps |
| T510 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/6.xbar_random_slow_rsp.3821699193 |
|
|
Aug 27 08:17:03 PM UTC 24 |
Aug 27 08:29:22 PM UTC 24 |
51715889858 ps |
| T570 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/9.chip_tl_errors.52485170 |
|
|
Aug 27 08:22:27 PM UTC 24 |
Aug 27 08:29:23 PM UTC 24 |
4893561396 ps |
| T1402 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/11.xbar_smoke_slow_rsp.2911466041 |
|
|
Aug 27 08:27:16 PM UTC 24 |
Aug 27 08:29:25 PM UTC 24 |
6041853779 ps |
| T508 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/10.xbar_stress_all.1178686574 |
|
|
Aug 27 08:26:07 PM UTC 24 |
Aug 27 08:29:28 PM UTC 24 |
2102871581 ps |
| T1403 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/11.xbar_error_and_unmapped_addr.2134552582 |
|
|
Aug 27 08:28:44 PM UTC 24 |
Aug 27 08:29:32 PM UTC 24 |
1366922020 ps |
| T1404 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/11.xbar_error_random.3514608806 |
|
|
Aug 27 08:28:39 PM UTC 24 |
Aug 27 08:29:33 PM UTC 24 |
1810025703 ps |
| T413 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/5.chip_csr_mem_rw_with_rand_reset.4181623258 |
|
|
Aug 27 08:16:14 PM UTC 24 |
Aug 27 08:29:34 PM UTC 24 |
11822274614 ps |
| T1405 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/12.xbar_smoke_zero_delays.1346120259 |
|
|
Aug 27 08:29:34 PM UTC 24 |
Aug 27 08:29:45 PM UTC 24 |
57347281 ps |
| T1406 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/12.xbar_smoke.1968557967 |
|
|
Aug 27 08:29:33 PM UTC 24 |
Aug 27 08:29:47 PM UTC 24 |
224180359 ps |