| T1407 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/11.xbar_stress_all_with_reset_error.1855878548 |
|
|
Aug 27 08:29:09 PM UTC 24 |
Aug 27 08:30:09 PM UTC 24 |
142579206 ps |
| T464 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/4.chip_csr_mem_rw_with_rand_reset.1602149361 |
|
|
Aug 27 08:14:05 PM UTC 24 |
Aug 27 08:30:19 PM UTC 24 |
12395112020 ps |
| T838 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/10.xbar_access_same_device_slow_rsp.458851271 |
|
|
Aug 27 08:25:41 PM UTC 24 |
Aug 27 08:30:19 PM UTC 24 |
15371458164 ps |
| T1408 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/11.xbar_stress_all_with_error.3209905157 |
|
|
Aug 27 08:28:48 PM UTC 24 |
Aug 27 08:30:24 PM UTC 24 |
2368534515 ps |
| T1409 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/12.xbar_random_zero_delays.3468896891 |
|
|
Aug 27 08:29:51 PM UTC 24 |
Aug 27 08:30:25 PM UTC 24 |
247291777 ps |
| T1410 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/12.xbar_same_source.3537803281 |
|
|
Aug 27 08:30:12 PM UTC 24 |
Aug 27 08:30:28 PM UTC 24 |
118084506 ps |
| T582 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/10.chip_tl_errors.3057705476 |
|
|
Aug 27 08:25:07 PM UTC 24 |
Aug 27 08:30:36 PM UTC 24 |
3203905214 ps |
| T572 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/11.chip_tl_errors.3573981857 |
|
|
Aug 27 08:26:57 PM UTC 24 |
Aug 27 08:30:37 PM UTC 24 |
3099146558 ps |
| T1411 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/12.xbar_error_random.1314463121 |
|
|
Aug 27 08:30:32 PM UTC 24 |
Aug 27 08:30:44 PM UTC 24 |
115116348 ps |
| T511 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/12.xbar_random.1700005033 |
|
|
Aug 27 08:29:48 PM UTC 24 |
Aug 27 08:30:46 PM UTC 24 |
1112426629 ps |
| T787 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/12.xbar_access_same_device.1076385054 |
|
|
Aug 27 08:29:56 PM UTC 24 |
Aug 27 08:30:48 PM UTC 24 |
747285825 ps |
| T1412 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/12.xbar_smoke_slow_rsp.837004886 |
|
|
Aug 27 08:29:45 PM UTC 24 |
Aug 27 08:31:02 PM UTC 24 |
5710400729 ps |
| T1413 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/11.xbar_random_slow_rsp.4117425479 |
|
|
Aug 27 08:27:41 PM UTC 24 |
Aug 27 08:31:14 PM UTC 24 |
15254958947 ps |
| T1414 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/12.xbar_random_large_delays.3307491632 |
|
|
Aug 27 08:29:54 PM UTC 24 |
Aug 27 08:31:16 PM UTC 24 |
5662111297 ps |
| T1415 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/12.xbar_smoke_large_delays.2245913325 |
|
|
Aug 27 08:29:45 PM UTC 24 |
Aug 27 08:31:23 PM UTC 24 |
8390175871 ps |
| T1416 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/13.xbar_smoke.3253142127 |
|
|
Aug 27 08:31:11 PM UTC 24 |
Aug 27 08:31:23 PM UTC 24 |
235691475 ps |
| T1417 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/6.xbar_random_large_delays.417571983 |
|
|
Aug 27 08:17:03 PM UTC 24 |
Aug 27 08:31:25 PM UTC 24 |
82647802238 ps |
| T804 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/10.xbar_stress_all_with_rand_reset.4080105842 |
|
|
Aug 27 08:26:19 PM UTC 24 |
Aug 27 08:31:28 PM UTC 24 |
3937360127 ps |
| T465 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/9.chip_csr_mem_rw_with_rand_reset.2113515539 |
|
|
Aug 27 08:24:56 PM UTC 24 |
Aug 27 08:31:29 PM UTC 24 |
6761684830 ps |
| T1418 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/12.xbar_unmapped_addr.2377869415 |
|
|
Aug 27 08:30:42 PM UTC 24 |
Aug 27 08:31:30 PM UTC 24 |
785497785 ps |
| T1419 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/13.xbar_smoke_zero_delays.2691384927 |
|
|
Aug 27 08:31:24 PM UTC 24 |
Aug 27 08:31:33 PM UTC 24 |
56131159 ps |
| T1420 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/12.xbar_error_and_unmapped_addr.3245200162 |
|
|
Aug 27 08:30:43 PM UTC 24 |
Aug 27 08:31:37 PM UTC 24 |
1003695211 ps |
| T467 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/12.xbar_stress_all_with_rand_reset.254879703 |
|
|
Aug 27 08:30:46 PM UTC 24 |
Aug 27 08:31:56 PM UTC 24 |
256824158 ps |
| T818 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/13.xbar_access_same_device.4183001818 |
|
|
Aug 27 08:31:50 PM UTC 24 |
Aug 27 08:32:09 PM UTC 24 |
140330172 ps |
| T403 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/10.chip_csr_rw.1544816138 |
|
|
Aug 27 08:26:34 PM UTC 24 |
Aug 27 08:32:09 PM UTC 24 |
4131485074 ps |
| T1421 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/13.xbar_error_random.3242357612 |
|
|
Aug 27 08:31:58 PM UTC 24 |
Aug 27 08:32:17 PM UTC 24 |
311107786 ps |
| T1422 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/13.xbar_random.3107442387 |
|
|
Aug 27 08:31:44 PM UTC 24 |
Aug 27 08:32:23 PM UTC 24 |
291155611 ps |
| T585 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/12.chip_tl_errors.3386661835 |
|
|
Aug 27 08:29:18 PM UTC 24 |
Aug 27 08:32:27 PM UTC 24 |
2956485720 ps |
| T1423 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/7.chip_csr_mem_rw_with_rand_reset.1682197874 |
|
|
Aug 27 08:20:01 PM UTC 24 |
Aug 27 08:32:28 PM UTC 24 |
8857263971 ps |
| T538 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/13.xbar_random_zero_delays.3374191702 |
|
|
Aug 27 08:31:45 PM UTC 24 |
Aug 27 08:32:32 PM UTC 24 |
533876960 ps |
| T1424 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/13.xbar_smoke_slow_rsp.743644553 |
|
|
Aug 27 08:31:37 PM UTC 24 |
Aug 27 08:32:32 PM UTC 24 |
3692383355 ps |
| T541 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/11.xbar_stress_all.3422987734 |
|
|
Aug 27 08:28:45 PM UTC 24 |
Aug 27 08:32:33 PM UTC 24 |
2399003600 ps |
| T1425 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/13.xbar_stress_all_with_error.592503831 |
|
|
Aug 27 08:32:45 PM UTC 24 |
Aug 27 08:32:55 PM UTC 24 |
44280906 ps |
| T1426 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/13.xbar_error_and_unmapped_addr.16850111 |
|
|
Aug 27 08:32:32 PM UTC 24 |
Aug 27 08:32:57 PM UTC 24 |
663235108 ps |
| T844 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/12.xbar_stress_all_with_reset_error.2538569695 |
|
|
Aug 27 08:30:49 PM UTC 24 |
Aug 27 08:33:01 PM UTC 24 |
334543703 ps |
| T485 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/13.xbar_same_source.828855821 |
|
|
Aug 27 08:31:53 PM UTC 24 |
Aug 27 08:33:10 PM UTC 24 |
2535608872 ps |
| T1427 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/13.xbar_unmapped_addr.1227911176 |
|
|
Aug 27 08:32:18 PM UTC 24 |
Aug 27 08:33:21 PM UTC 24 |
1171441986 ps |
| T1428 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/13.xbar_smoke_large_delays.2077108952 |
|
|
Aug 27 08:31:35 PM UTC 24 |
Aug 27 08:33:25 PM UTC 24 |
7336507751 ps |
| T1429 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/14.xbar_smoke.3143012536 |
|
|
Aug 27 08:33:18 PM UTC 24 |
Aug 27 08:33:29 PM UTC 24 |
51033249 ps |
| T1430 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/14.xbar_smoke_zero_delays.1194697812 |
|
|
Aug 27 08:33:19 PM UTC 24 |
Aug 27 08:33:29 PM UTC 24 |
53598991 ps |
| T1431 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/14.xbar_random.1067841482 |
|
|
Aug 27 08:33:43 PM UTC 24 |
Aug 27 08:34:17 PM UTC 24 |
616529843 ps |
| T1432 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/14.xbar_smoke_large_delays.1365717837 |
|
|
Aug 27 08:33:24 PM UTC 24 |
Aug 27 08:34:27 PM UTC 24 |
5819479476 ps |
| T603 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/14.xbar_random_zero_delays.1603638014 |
|
|
Aug 27 08:33:47 PM UTC 24 |
Aug 27 08:34:36 PM UTC 24 |
426642632 ps |
| T481 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/12.xbar_stress_all.1089740246 |
|
|
Aug 27 08:30:45 PM UTC 24 |
Aug 27 08:34:47 PM UTC 24 |
6688363814 ps |
| T1433 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/13.xbar_random_large_delays.2400294098 |
|
|
Aug 27 08:31:47 PM UTC 24 |
Aug 27 08:34:52 PM UTC 24 |
19660411910 ps |
| T811 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/10.xbar_stress_all_with_error.4214365141 |
|
|
Aug 27 08:26:25 PM UTC 24 |
Aug 27 08:35:00 PM UTC 24 |
15122777623 ps |
| T543 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/14.xbar_smoke_slow_rsp.3686461895 |
|
|
Aug 27 08:33:33 PM UTC 24 |
Aug 27 08:35:18 PM UTC 24 |
5683465885 ps |
| T1434 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/14.xbar_unmapped_addr.792269959 |
|
|
Aug 27 08:35:08 PM UTC 24 |
Aug 27 08:35:22 PM UTC 24 |
57261541 ps |
| T1435 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/3.chip_csr_bit_bash.3554804269 |
|
|
Aug 27 08:10:33 PM UTC 24 |
Aug 27 08:35:25 PM UTC 24 |
14949056787 ps |
| T791 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/8.xbar_access_same_device_slow_rsp.484182914 |
|
|
Aug 27 08:21:13 PM UTC 24 |
Aug 27 08:35:31 PM UTC 24 |
57959689783 ps |
| T1436 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/8.xbar_random_large_delays.2385061885 |
|
|
Aug 27 08:20:44 PM UTC 24 |
Aug 27 08:35:32 PM UTC 24 |
86631553972 ps |
| T1437 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/14.xbar_same_source.44243658 |
|
|
Aug 27 08:34:58 PM UTC 24 |
Aug 27 08:35:33 PM UTC 24 |
307268324 ps |
| T1438 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/14.xbar_error_random.26783745 |
|
|
Aug 27 08:35:06 PM UTC 24 |
Aug 27 08:35:38 PM UTC 24 |
396594745 ps |
| T1439 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/14.xbar_error_and_unmapped_addr.1374918931 |
|
|
Aug 27 08:35:19 PM UTC 24 |
Aug 27 08:35:44 PM UTC 24 |
156532545 ps |
| T509 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/14.xbar_access_same_device.2773191504 |
|
|
Aug 27 08:34:39 PM UTC 24 |
Aug 27 08:35:53 PM UTC 24 |
704567453 ps |
| T1440 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/9.chip_csr_rw.3157816097 |
|
|
Aug 27 08:24:53 PM UTC 24 |
Aug 27 08:36:05 PM UTC 24 |
5761617149 ps |
| T505 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/10.xbar_random_large_delays.2959096173 |
|
|
Aug 27 08:25:35 PM UTC 24 |
Aug 27 08:36:27 PM UTC 24 |
60116106892 ps |
| T533 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/9.xbar_random_slow_rsp.2981897389 |
|
|
Aug 27 08:23:25 PM UTC 24 |
Aug 27 08:36:28 PM UTC 24 |
55980161335 ps |
| T1441 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/15.xbar_smoke.1504261133 |
|
|
Aug 27 08:36:15 PM UTC 24 |
Aug 27 08:36:29 PM UTC 24 |
204924087 ps |
| T493 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/8.xbar_random_slow_rsp.838889986 |
|
|
Aug 27 08:20:47 PM UTC 24 |
Aug 27 08:36:34 PM UTC 24 |
63666116325 ps |
| T1442 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/15.xbar_smoke_zero_delays.2293098396 |
|
|
Aug 27 08:36:27 PM UTC 24 |
Aug 27 08:36:38 PM UTC 24 |
46302249 ps |
| T1443 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/14.xbar_random_slow_rsp.2099922343 |
|
|
Aug 27 08:33:50 PM UTC 24 |
Aug 27 08:36:45 PM UTC 24 |
14155144309 ps |
| T845 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/13.xbar_stress_all_with_reset_error.3477656995 |
|
|
Aug 27 08:32:48 PM UTC 24 |
Aug 27 08:36:58 PM UTC 24 |
934752125 ps |
| T819 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/9.xbar_stress_all_with_reset_error.851343813 |
|
|
Aug 27 08:24:43 PM UTC 24 |
Aug 27 08:37:16 PM UTC 24 |
14963347259 ps |
| T382 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/4.chip_same_csr_outstanding.28945536 |
|
|
Aug 27 08:12:32 PM UTC 24 |
Aug 27 08:37:20 PM UTC 24 |
16368613174 ps |
| T586 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/13.chip_tl_errors.1608296418 |
|
|
Aug 27 08:31:07 PM UTC 24 |
Aug 27 08:37:22 PM UTC 24 |
4910095320 ps |
| T1444 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/10.chip_csr_mem_rw_with_rand_reset.472282366 |
|
|
Aug 27 08:26:45 PM UTC 24 |
Aug 27 08:37:29 PM UTC 24 |
8026472984 ps |
| T1445 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/15.xbar_random.4055049021 |
|
|
Aug 27 08:36:52 PM UTC 24 |
Aug 27 08:37:34 PM UTC 24 |
373011700 ps |
| T840 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/15.xbar_access_same_device.3332541987 |
|
|
Aug 27 08:37:21 PM UTC 24 |
Aug 27 08:37:41 PM UTC 24 |
113539871 ps |
| T1446 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/13.chip_csr_rw.960572961 |
|
|
Aug 27 08:32:52 PM UTC 24 |
Aug 27 08:37:50 PM UTC 24 |
3710897916 ps |
| T1447 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/15.xbar_random_zero_delays.1605139654 |
|
|
Aug 27 08:36:56 PM UTC 24 |
Aug 27 08:37:52 PM UTC 24 |
510121832 ps |
| T1448 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/15.xbar_same_source.1134484376 |
|
|
Aug 27 08:37:40 PM UTC 24 |
Aug 27 08:37:56 PM UTC 24 |
295687546 ps |
| T1449 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/15.xbar_unmapped_addr.3565091937 |
|
|
Aug 27 08:37:50 PM UTC 24 |
Aug 27 08:37:59 PM UTC 24 |
35517639 ps |
| T1450 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/15.xbar_error_and_unmapped_addr.2405193820 |
|
|
Aug 27 08:37:56 PM UTC 24 |
Aug 27 08:38:03 PM UTC 24 |
58082294 ps |
| T1451 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/15.xbar_error_random.1304294860 |
|
|
Aug 27 08:37:41 PM UTC 24 |
Aug 27 08:38:24 PM UTC 24 |
388981185 ps |
| T1452 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/12.chip_csr_rw.1723809033 |
|
|
Aug 27 08:30:58 PM UTC 24 |
Aug 27 08:38:25 PM UTC 24 |
5879367234 ps |
| T1453 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/15.xbar_smoke_slow_rsp.3563169040 |
|
|
Aug 27 08:36:51 PM UTC 24 |
Aug 27 08:38:30 PM UTC 24 |
5368211176 ps |
| T788 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/6.xbar_access_same_device_slow_rsp.3552879612 |
|
|
Aug 27 08:17:04 PM UTC 24 |
Aug 27 08:38:30 PM UTC 24 |
69486444294 ps |
| T1454 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/15.xbar_smoke_large_delays.901091 |
|
|
Aug 27 08:36:50 PM UTC 24 |
Aug 27 08:38:40 PM UTC 24 |
8111781079 ps |
| T383 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/2.chip_same_csr_outstanding.2499900041 |
|
|
Aug 27 08:08:52 PM UTC 24 |
Aug 27 08:38:49 PM UTC 24 |
14446847553 ps |
| T1455 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/8.chip_csr_mem_rw_with_rand_reset.723166719 |
|
|
Aug 27 08:22:26 PM UTC 24 |
Aug 27 08:38:50 PM UTC 24 |
13024762356 ps |
| T1456 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/16.xbar_smoke.3190210871 |
|
|
Aug 27 08:38:52 PM UTC 24 |
Aug 27 08:39:02 PM UTC 24 |
44035375 ps |
| T1457 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/16.xbar_smoke_zero_delays.1165287941 |
|
|
Aug 27 08:38:53 PM UTC 24 |
Aug 27 08:39:03 PM UTC 24 |
45253141 ps |
| T1458 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/12.chip_csr_mem_rw_with_rand_reset.455760293 |
|
|
Aug 27 08:30:59 PM UTC 24 |
Aug 27 08:39:03 PM UTC 24 |
6386133336 ps |
| T468 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/13.xbar_stress_all.1150513809 |
|
|
Aug 27 08:32:32 PM UTC 24 |
Aug 27 08:39:03 PM UTC 24 |
9250573388 ps |
| T527 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/11.xbar_stress_all_with_rand_reset.2979017314 |
|
|
Aug 27 08:28:45 PM UTC 24 |
Aug 27 08:39:38 PM UTC 24 |
5187078294 ps |
| T617 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/14.chip_tl_errors.2454080156 |
|
|
Aug 27 08:32:56 PM UTC 24 |
Aug 27 08:39:45 PM UTC 24 |
4303195926 ps |
| T384 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/0.chip_same_csr_outstanding.352407784 |
|
|
Aug 27 08:07:46 PM UTC 24 |
Aug 27 08:39:48 PM UTC 24 |
14031130776 ps |
| T571 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/15.chip_tl_errors.4275516269 |
|
|
Aug 27 08:36:07 PM UTC 24 |
Aug 27 08:39:51 PM UTC 24 |
3580117288 ps |
| T1459 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/11.chip_csr_rw.1166515118 |
|
|
Aug 27 08:29:11 PM UTC 24 |
Aug 27 08:39:54 PM UTC 24 |
5218602056 ps |
| T488 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/16.xbar_random.566600470 |
|
|
Aug 27 08:39:13 PM UTC 24 |
Aug 27 08:40:09 PM UTC 24 |
1130209084 ps |
| T1460 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/16.xbar_same_source.1445001824 |
|
|
Aug 27 08:40:06 PM UTC 24 |
Aug 27 08:40:29 PM UTC 24 |
177788522 ps |
| T1461 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/16.xbar_unmapped_addr.276429202 |
|
|
Aug 27 08:40:13 PM UTC 24 |
Aug 27 08:40:29 PM UTC 24 |
115739405 ps |
| T1462 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/16.xbar_random_zero_delays.2600611145 |
|
|
Aug 27 08:39:24 PM UTC 24 |
Aug 27 08:40:30 PM UTC 24 |
588947217 ps |
| T1463 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/13.chip_csr_mem_rw_with_rand_reset.2976158533 |
|
|
Aug 27 08:32:54 PM UTC 24 |
Aug 27 08:40:31 PM UTC 24 |
6073187871 ps |
| T1464 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/9.xbar_random_large_delays.1910828042 |
|
|
Aug 27 08:23:07 PM UTC 24 |
Aug 27 08:40:34 PM UTC 24 |
100250358376 ps |
| T1465 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/16.xbar_error_and_unmapped_addr.3877389401 |
|
|
Aug 27 08:40:16 PM UTC 24 |
Aug 27 08:40:42 PM UTC 24 |
158313009 ps |
| T812 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/12.xbar_stress_all_with_error.1695348832 |
|
|
Aug 27 08:30:48 PM UTC 24 |
Aug 27 08:40:44 PM UTC 24 |
12254994644 ps |
| T1466 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/16.xbar_error_random.3968289355 |
|
|
Aug 27 08:40:11 PM UTC 24 |
Aug 27 08:40:46 PM UTC 24 |
322221784 ps |
| T1467 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/16.xbar_smoke_slow_rsp.3146463159 |
|
|
Aug 27 08:39:12 PM UTC 24 |
Aug 27 08:40:52 PM UTC 24 |
5406663682 ps |
| T1468 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/15.xbar_stress_all_with_reset_error.3670841197 |
|
|
Aug 27 08:38:18 PM UTC 24 |
Aug 27 08:40:53 PM UTC 24 |
397427394 ps |
| T1469 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/16.xbar_random_large_delays.3438841560 |
|
|
Aug 27 08:39:22 PM UTC 24 |
Aug 27 08:40:55 PM UTC 24 |
10952393198 ps |
| T484 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/15.xbar_stress_all.320285094 |
|
|
Aug 27 08:38:02 PM UTC 24 |
Aug 27 08:41:10 PM UTC 24 |
2475394701 ps |
| T872 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/15.xbar_stress_all_with_rand_reset.3693888786 |
|
|
Aug 27 08:38:12 PM UTC 24 |
Aug 27 08:41:11 PM UTC 24 |
440491316 ps |
| T494 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/16.xbar_access_same_device.2971055214 |
|
|
Aug 27 08:39:25 PM UTC 24 |
Aug 27 08:41:20 PM UTC 24 |
2169018445 ps |
| T1470 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/17.xbar_smoke_zero_delays.3293847583 |
|
|
Aug 27 08:41:14 PM UTC 24 |
Aug 27 08:41:24 PM UTC 24 |
41176845 ps |
| T1471 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/17.xbar_smoke.248943172 |
|
|
Aug 27 08:41:09 PM UTC 24 |
Aug 27 08:41:25 PM UTC 24 |
259174305 ps |
| T1472 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/16.xbar_stress_all_with_reset_error.3462248725 |
|
|
Aug 27 08:40:50 PM UTC 24 |
Aug 27 08:41:29 PM UTC 24 |
36549902 ps |
| T1473 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/16.xbar_smoke_large_delays.1920645777 |
|
|
Aug 27 08:39:03 PM UTC 24 |
Aug 27 08:41:34 PM UTC 24 |
9574509040 ps |
| T1474 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/17.xbar_random_zero_delays.2787124322 |
|
|
Aug 27 08:41:33 PM UTC 24 |
Aug 27 08:41:57 PM UTC 24 |
177922344 ps |
| T1475 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/15.xbar_stress_all_with_error.1843866309 |
|
|
Aug 27 08:38:13 PM UTC 24 |
Aug 27 08:42:00 PM UTC 24 |
6289907905 ps |
| T515 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/12.xbar_random_slow_rsp.3567067282 |
|
|
Aug 27 08:29:56 PM UTC 24 |
Aug 27 08:42:02 PM UTC 24 |
49297011350 ps |
| T1476 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/17.xbar_smoke_slow_rsp.3764334476 |
|
|
Aug 27 08:41:17 PM UTC 24 |
Aug 27 08:42:34 PM UTC 24 |
6035279715 ps |
| T1477 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/14.xbar_stress_all_with_error.1467633423 |
|
|
Aug 27 08:35:42 PM UTC 24 |
Aug 27 08:42:37 PM UTC 24 |
4661135959 ps |
| T470 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/17.xbar_same_source.25182226 |
|
|
Aug 27 08:41:56 PM UTC 24 |
Aug 27 08:42:37 PM UTC 24 |
369751439 ps |
| T1478 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/17.xbar_error_and_unmapped_addr.1777159252 |
|
|
Aug 27 08:42:23 PM UTC 24 |
Aug 27 08:42:43 PM UTC 24 |
269785939 ps |
| T1479 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/17.xbar_unmapped_addr.3881199265 |
|
|
Aug 27 08:42:22 PM UTC 24 |
Aug 27 08:42:43 PM UTC 24 |
265831836 ps |
| T1480 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/14.xbar_stress_all_with_reset_error.1535287946 |
|
|
Aug 27 08:35:53 PM UTC 24 |
Aug 27 08:42:47 PM UTC 24 |
4450324251 ps |
| T475 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/16.xbar_stress_all.1639847197 |
|
|
Aug 27 08:40:31 PM UTC 24 |
Aug 27 08:42:48 PM UTC 24 |
4408518442 ps |
| T1481 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/16.xbar_stress_all_with_error.3877377894 |
|
|
Aug 27 08:40:50 PM UTC 24 |
Aug 27 08:43:04 PM UTC 24 |
2984960355 ps |
| T1482 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/17.xbar_smoke_large_delays.3455841401 |
|
|
Aug 27 08:41:15 PM UTC 24 |
Aug 27 08:43:09 PM UTC 24 |
10755964613 ps |
| T1483 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/17.xbar_error_random.73223197 |
|
|
Aug 27 08:42:19 PM UTC 24 |
Aug 27 08:43:09 PM UTC 24 |
470961521 ps |
| T1484 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/13.xbar_random_slow_rsp.1857611485 |
|
|
Aug 27 08:31:51 PM UTC 24 |
Aug 27 08:43:18 PM UTC 24 |
41880930972 ps |
| T1485 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/17.xbar_random.1526762841 |
|
|
Aug 27 08:41:32 PM UTC 24 |
Aug 27 08:43:29 PM UTC 24 |
2322794017 ps |
| T828 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/17.xbar_access_same_device.574760740 |
|
|
Aug 27 08:41:48 PM UTC 24 |
Aug 27 08:43:34 PM UTC 24 |
992147542 ps |
| T1486 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/18.xbar_smoke_zero_delays.1959019480 |
|
|
Aug 27 08:43:32 PM UTC 24 |
Aug 27 08:43:42 PM UTC 24 |
53728176 ps |
| T1487 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/18.xbar_smoke.3213360176 |
|
|
Aug 27 08:43:32 PM UTC 24 |
Aug 27 08:43:45 PM UTC 24 |
150652649 ps |
| T1488 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/17.xbar_stress_all.2067485099 |
|
|
Aug 27 08:42:55 PM UTC 24 |
Aug 27 08:44:05 PM UTC 24 |
2014616367 ps |
| T1489 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/17.xbar_stress_all_with_error.91098999 |
|
|
Aug 27 08:43:01 PM UTC 24 |
Aug 27 08:44:12 PM UTC 24 |
850535754 ps |
| T1490 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/14.chip_csr_rw.4139023938 |
|
|
Aug 27 08:35:55 PM UTC 24 |
Aug 27 08:44:17 PM UTC 24 |
5512177800 ps |
| T1491 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/11.chip_csr_mem_rw_with_rand_reset.912865349 |
|
|
Aug 27 08:29:12 PM UTC 24 |
Aug 27 08:44:22 PM UTC 24 |
9565402824 ps |
| T1492 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/18.xbar_random_zero_delays.3435681794 |
|
|
Aug 27 08:44:05 PM UTC 24 |
Aug 27 08:44:26 PM UTC 24 |
150073900 ps |
| T598 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/16.chip_tl_errors.2690906331 |
|
|
Aug 27 08:38:47 PM UTC 24 |
Aug 27 08:44:34 PM UTC 24 |
3936840645 ps |
| T1493 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/18.xbar_random.3816259559 |
|
|
Aug 27 08:43:54 PM UTC 24 |
Aug 27 08:44:38 PM UTC 24 |
858393754 ps |
| T1494 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/16.xbar_random_slow_rsp.896003658 |
|
|
Aug 27 08:39:22 PM UTC 24 |
Aug 27 08:44:50 PM UTC 24 |
19108194668 ps |
| T1495 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/15.chip_csr_rw.2735382625 |
|
|
Aug 27 08:38:21 PM UTC 24 |
Aug 27 08:44:52 PM UTC 24 |
3844557080 ps |
| T1496 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/18.xbar_access_same_device.790958225 |
|
|
Aug 27 08:44:34 PM UTC 24 |
Aug 27 08:44:52 PM UTC 24 |
260303814 ps |
| T1497 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/18.xbar_smoke_large_delays.2729233272 |
|
|
Aug 27 08:43:41 PM UTC 24 |
Aug 27 08:45:04 PM UTC 24 |
5065516947 ps |
| T1498 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/18.xbar_unmapped_addr.2755603309 |
|
|
Aug 27 08:44:56 PM UTC 24 |
Aug 27 08:45:05 PM UTC 24 |
80805832 ps |
| T1499 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/18.xbar_error_random.3299252659 |
|
|
Aug 27 08:44:48 PM UTC 24 |
Aug 27 08:45:07 PM UTC 24 |
385939904 ps |
| T652 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/17.chip_tl_errors.2585331363 |
|
|
Aug 27 08:41:05 PM UTC 24 |
Aug 27 08:45:09 PM UTC 24 |
3708958922 ps |
| T1500 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/18.xbar_same_source.3307934221 |
|
|
Aug 27 08:44:44 PM UTC 24 |
Aug 27 08:45:15 PM UTC 24 |
403386793 ps |
| T792 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/13.xbar_stress_all_with_rand_reset.2680450332 |
|
|
Aug 27 08:32:40 PM UTC 24 |
Aug 27 08:45:28 PM UTC 24 |
10156808979 ps |
| T1501 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/15.xbar_random_large_delays.210826423 |
|
|
Aug 27 08:37:00 PM UTC 24 |
Aug 27 08:45:33 PM UTC 24 |
54834164718 ps |
| T1502 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/18.xbar_error_and_unmapped_addr.1962806107 |
|
|
Aug 27 08:45:01 PM UTC 24 |
Aug 27 08:45:44 PM UTC 24 |
325763916 ps |
| T1503 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/19.xbar_smoke.3291865131 |
|
|
Aug 27 08:45:50 PM UTC 24 |
Aug 27 08:46:00 PM UTC 24 |
51444104 ps |
| T1504 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/19.xbar_smoke_zero_delays.2515212673 |
|
|
Aug 27 08:45:53 PM UTC 24 |
Aug 27 08:46:03 PM UTC 24 |
51979817 ps |
| T1505 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/18.xbar_smoke_slow_rsp.1505798285 |
|
|
Aug 27 08:43:51 PM UTC 24 |
Aug 27 08:46:10 PM UTC 24 |
6367705188 ps |
| T1506 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/14.chip_csr_mem_rw_with_rand_reset.647871126 |
|
|
Aug 27 08:35:55 PM UTC 24 |
Aug 27 08:46:11 PM UTC 24 |
7820307942 ps |
| T855 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/17.xbar_stress_all_with_rand_reset.145678328 |
|
|
Aug 27 08:42:56 PM UTC 24 |
Aug 27 08:46:22 PM UTC 24 |
357052075 ps |
| T1507 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/18.xbar_stress_all.1412335238 |
|
|
Aug 27 08:45:13 PM UTC 24 |
Aug 27 08:46:28 PM UTC 24 |
578217037 ps |
| T877 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/17.xbar_stress_all_with_reset_error.3852248618 |
|
|
Aug 27 08:43:05 PM UTC 24 |
Aug 27 08:46:55 PM UTC 24 |
920110006 ps |
| T1508 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/19.xbar_random_zero_delays.3799635540 |
|
|
Aug 27 08:46:31 PM UTC 24 |
Aug 27 08:46:58 PM UTC 24 |
186899691 ps |
| T1509 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/19.xbar_random.1735299059 |
|
|
Aug 27 08:46:26 PM UTC 24 |
Aug 27 08:47:03 PM UTC 24 |
656575860 ps |
| T801 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/19.xbar_access_same_device.318328135 |
|
|
Aug 27 08:46:51 PM UTC 24 |
Aug 27 08:47:12 PM UTC 24 |
118034937 ps |
| T1510 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/19.xbar_same_source.3366684446 |
|
|
Aug 27 08:47:21 PM UTC 24 |
Aug 27 08:47:40 PM UTC 24 |
157131320 ps |
| T1511 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/19.xbar_error_and_unmapped_addr.377220509 |
|
|
Aug 27 08:48:03 PM UTC 24 |
Aug 27 08:48:12 PM UTC 24 |
21306960 ps |
| T1512 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/19.xbar_random_slow_rsp.1950489197 |
|
|
Aug 27 08:46:46 PM UTC 24 |
Aug 27 08:48:16 PM UTC 24 |
3835093249 ps |
| T1513 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/16.chip_csr_mem_rw_with_rand_reset.1479682111 |
|
|
Aug 27 08:40:52 PM UTC 24 |
Aug 27 08:48:20 PM UTC 24 |
5870090503 ps |
| T1514 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/19.xbar_smoke_slow_rsp.2626400939 |
|
|
Aug 27 08:46:23 PM UTC 24 |
Aug 27 08:48:22 PM UTC 24 |
5228762815 ps |
| T1515 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/19.xbar_unmapped_addr.188410775 |
|
|
Aug 27 08:47:34 PM UTC 24 |
Aug 27 08:48:27 PM UTC 24 |
308066701 ps |
| T529 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/16.xbar_stress_all_with_rand_reset.290808771 |
|
|
Aug 27 08:40:52 PM UTC 24 |
Aug 27 08:48:31 PM UTC 24 |
3576421597 ps |
| T1516 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/19.xbar_smoke_large_delays.136607465 |
|
|
Aug 27 08:46:07 PM UTC 24 |
Aug 27 08:48:37 PM UTC 24 |
9809911138 ps |
| T789 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/4.xbar_access_same_device_slow_rsp.3643337365 |
|
|
Aug 27 08:13:11 PM UTC 24 |
Aug 27 08:48:40 PM UTC 24 |
142233850251 ps |
| T1517 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/19.xbar_error_random.3941959061 |
|
|
Aug 27 08:47:25 PM UTC 24 |
Aug 27 08:48:59 PM UTC 24 |
1775912965 ps |
| T619 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/18.chip_tl_errors.4080124567 |
|
|
Aug 27 08:43:27 PM UTC 24 |
Aug 27 08:49:09 PM UTC 24 |
3854146612 ps |
| T512 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/14.xbar_stress_all_with_rand_reset.2208199232 |
|
|
Aug 27 08:35:44 PM UTC 24 |
Aug 27 08:49:11 PM UTC 24 |
5914748974 ps |
| T539 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/14.xbar_stress_all.3113415964 |
|
|
Aug 27 08:35:34 PM UTC 24 |
Aug 27 08:49:13 PM UTC 24 |
21461667803 ps |
| T1518 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/20.xbar_smoke.3497812473 |
|
|
Aug 27 08:49:02 PM UTC 24 |
Aug 27 08:49:15 PM UTC 24 |
180295550 ps |
| T805 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/7.xbar_access_same_device_slow_rsp.931137338 |
|
|
Aug 27 08:19:06 PM UTC 24 |
Aug 27 08:49:20 PM UTC 24 |
121490719421 ps |
| T1519 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/18.chip_csr_rw.414755144 |
|
|
Aug 27 08:45:26 PM UTC 24 |
Aug 27 08:50:07 PM UTC 24 |
4073594130 ps |
| T1520 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/20.xbar_smoke_zero_delays.4044445259 |
|
|
Aug 27 08:49:20 PM UTC 24 |
Aug 27 08:49:30 PM UTC 24 |
49964743 ps |
| T1521 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/20.xbar_random_zero_delays.2479721009 |
|
|
Aug 27 08:49:37 PM UTC 24 |
Aug 27 08:49:58 PM UTC 24 |
142773016 ps |
| T875 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/19.xbar_stress_all_with_rand_reset.4171017638 |
|
|
Aug 27 08:48:38 PM UTC 24 |
Aug 27 08:50:08 PM UTC 24 |
312036127 ps |
| T835 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/18.xbar_stress_all_with_reset_error.1778097365 |
|
|
Aug 27 08:45:28 PM UTC 24 |
Aug 27 08:50:23 PM UTC 24 |
4255026978 ps |
| T1522 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/16.chip_csr_rw.1380493628 |
|
|
Aug 27 08:40:51 PM UTC 24 |
Aug 27 08:50:25 PM UTC 24 |
5416018440 ps |
| T813 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/19.xbar_stress_all_with_error.2776103162 |
|
|
Aug 27 08:48:42 PM UTC 24 |
Aug 27 08:50:33 PM UTC 24 |
4148873775 ps |
| T1523 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/17.chip_csr_mem_rw_with_rand_reset.2104470517 |
|
|
Aug 27 08:43:09 PM UTC 24 |
Aug 27 08:50:37 PM UTC 24 |
5300594392 ps |
| T1524 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/15.chip_csr_mem_rw_with_rand_reset.933205123 |
|
|
Aug 27 08:38:22 PM UTC 24 |
Aug 27 08:50:44 PM UTC 24 |
9243210138 ps |
| T1525 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/20.xbar_smoke_slow_rsp.2552693415 |
|
|
Aug 27 08:49:33 PM UTC 24 |
Aug 27 08:50:50 PM UTC 24 |
4906844791 ps |
| T653 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/19.chip_tl_errors.3576877919 |
|
|
Aug 27 08:45:37 PM UTC 24 |
Aug 27 08:50:58 PM UTC 24 |
3261316244 ps |
| T1526 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/20.xbar_unmapped_addr.559252036 |
|
|
Aug 27 08:50:46 PM UTC 24 |
Aug 27 08:51:00 PM UTC 24 |
87176849 ps |
| T1527 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/17.xbar_random_slow_rsp.3491413811 |
|
|
Aug 27 08:41:47 PM UTC 24 |
Aug 27 08:51:00 PM UTC 24 |
34930439158 ps |
| T1528 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/20.xbar_random.2053273034 |
|
|
Aug 27 08:49:35 PM UTC 24 |
Aug 27 08:51:05 PM UTC 24 |
1807220869 ps |
| T1529 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/20.xbar_error_and_unmapped_addr.3542970116 |
|
|
Aug 27 08:50:54 PM UTC 24 |
Aug 27 08:51:10 PM UTC 24 |
233054454 ps |
| T1530 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/20.xbar_same_source.2374009980 |
|
|
Aug 27 08:50:31 PM UTC 24 |
Aug 27 08:51:12 PM UTC 24 |
518113610 ps |
| T1531 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/20.xbar_error_random.2372521555 |
|
|
Aug 27 08:50:42 PM UTC 24 |
Aug 27 08:51:29 PM UTC 24 |
502293119 ps |
| T1532 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/20.xbar_smoke_large_delays.3925680830 |
|
|
Aug 27 08:49:31 PM UTC 24 |
Aug 27 08:51:30 PM UTC 24 |
8827536824 ps |
| T1533 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/21.xbar_smoke.31136832 |
|
|
Aug 27 08:51:23 PM UTC 24 |
Aug 27 08:51:36 PM UTC 24 |
147283319 ps |
| T1534 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/21.xbar_smoke_zero_delays.298108967 |
|
|
Aug 27 08:51:26 PM UTC 24 |
Aug 27 08:51:36 PM UTC 24 |
40589469 ps |
| T1535 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/17.chip_csr_rw.1969753790 |
|
|
Aug 27 08:43:04 PM UTC 24 |
Aug 27 08:51:41 PM UTC 24 |
5764765312 ps |
| T517 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/15.xbar_random_slow_rsp.3017215039 |
|
|
Aug 27 08:37:08 PM UTC 24 |
Aug 27 08:51:44 PM UTC 24 |
53590833898 ps |
| T825 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/19.xbar_access_same_device_slow_rsp.1148876874 |
|
|
Aug 27 08:47:17 PM UTC 24 |
Aug 27 08:52:04 PM UTC 24 |
15468590375 ps |
| T1536 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/21.xbar_random.1917428484 |
|
|
Aug 27 08:51:50 PM UTC 24 |
Aug 27 08:52:16 PM UTC 24 |
387287589 ps |
| T1537 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/21.xbar_random_zero_delays.2485224448 |
|
|
Aug 27 08:51:53 PM UTC 24 |
Aug 27 08:52:27 PM UTC 24 |
258335295 ps |
| T1538 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/21.xbar_smoke_slow_rsp.1593554067 |
|
|
Aug 27 08:51:35 PM UTC 24 |
Aug 27 08:52:45 PM UTC 24 |
4258316405 ps |
| T820 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/15.xbar_access_same_device_slow_rsp.327549483 |
|
|
Aug 27 08:37:38 PM UTC 24 |
Aug 27 08:52:49 PM UTC 24 |
62378892695 ps |
| T1539 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/6.chip_same_csr_outstanding.3640185199 |
|
|
Aug 27 08:16:12 PM UTC 24 |
Aug 27 08:52:52 PM UTC 24 |
15173698151 ps |
| T546 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/20.xbar_access_same_device.775515794 |
|
|
Aug 27 08:50:19 PM UTC 24 |
Aug 27 08:52:54 PM UTC 24 |
2619163496 ps |
| T1540 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/21.xbar_same_source.2761720826 |
|
|
Aug 27 08:52:24 PM UTC 24 |
Aug 27 08:53:16 PM UTC 24 |
1475863227 ps |
| T1541 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/21.xbar_error_and_unmapped_addr.3027796368 |
|
|
Aug 27 08:53:07 PM UTC 24 |
Aug 27 08:53:18 PM UTC 24 |
133074111 ps |
| T1542 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/21.xbar_error_random.4270237178 |
|
|
Aug 27 08:52:39 PM UTC 24 |
Aug 27 08:53:32 PM UTC 24 |
588785073 ps |
| T496 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/3.xbar_access_same_device_slow_rsp.4029830261 |
|
|
Aug 27 08:11:29 PM UTC 24 |
Aug 27 08:53:41 PM UTC 24 |
146822417422 ps |
| T1543 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/21.xbar_unmapped_addr.2705573196 |
|
|
Aug 27 08:52:50 PM UTC 24 |
Aug 27 08:53:45 PM UTC 24 |
1247233626 ps |
| T814 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/18.xbar_stress_all_with_error.3359128341 |
|
|
Aug 27 08:45:15 PM UTC 24 |
Aug 27 08:53:45 PM UTC 24 |
13095533719 ps |
| T1544 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/20.xbar_stress_all_with_error.2953556508 |
|
|
Aug 27 08:51:12 PM UTC 24 |
Aug 27 08:53:46 PM UTC 24 |
1448675424 ps |
| T1545 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/21.xbar_smoke_large_delays.2330251019 |
|
|
Aug 27 08:51:32 PM UTC 24 |
Aug 27 08:53:59 PM UTC 24 |
9669505581 ps |
| T1546 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/22.xbar_smoke.4195540100 |
|
|
Aug 27 08:53:54 PM UTC 24 |
Aug 27 08:54:05 PM UTC 24 |
54047693 ps |
| T1547 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/22.xbar_smoke_zero_delays.2031041290 |
|
|
Aug 27 08:54:04 PM UTC 24 |
Aug 27 08:54:14 PM UTC 24 |
45916078 ps |
| T1548 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/21.xbar_random_large_delays.2798399487 |
|
|
Aug 27 08:51:59 PM UTC 24 |
Aug 27 08:54:26 PM UTC 24 |
12933525650 ps |
| T1549 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/22.xbar_random.1270294195 |
|
|
Aug 27 08:54:08 PM UTC 24 |
Aug 27 08:54:31 PM UTC 24 |
140371657 ps |
| T806 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/21.xbar_access_same_device.2520948264 |
|
|
Aug 27 08:52:00 PM UTC 24 |
Aug 27 08:54:34 PM UTC 24 |
3156133164 ps |
| T535 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/18.xbar_stress_all_with_rand_reset.769319485 |
|
|
Aug 27 08:45:15 PM UTC 24 |
Aug 27 08:54:44 PM UTC 24 |
10890867225 ps |
| T1550 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/21.xbar_stress_all_with_reset_error.164555954 |
|
|
Aug 27 08:53:37 PM UTC 24 |
Aug 27 08:55:06 PM UTC 24 |
287396341 ps |
| T1551 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/22.xbar_random_zero_delays.1259206829 |
|
|
Aug 27 08:54:21 PM UTC 24 |
Aug 27 08:55:08 PM UTC 24 |
611848085 ps |
| T1552 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/22.xbar_same_source.1568421832 |
|
|
Aug 27 08:54:56 PM UTC 24 |
Aug 27 08:55:18 PM UTC 24 |
144539500 ps |
| T1553 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/17.xbar_random_large_delays.3574208246 |
|
|
Aug 27 08:41:43 PM UTC 24 |
Aug 27 08:55:21 PM UTC 24 |
74681907980 ps |
| T1554 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/22.xbar_smoke_slow_rsp.2382830703 |
|
|
Aug 27 08:54:08 PM UTC 24 |
Aug 27 08:55:22 PM UTC 24 |
4371605905 ps |
| T1555 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/19.xbar_stress_all_with_reset_error.3341589027 |
|
|
Aug 27 08:48:44 PM UTC 24 |
Aug 27 08:55:27 PM UTC 24 |
1870546877 ps |
| T654 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/20.chip_tl_errors.3694193091 |
|
|
Aug 27 08:48:59 PM UTC 24 |
Aug 27 08:55:30 PM UTC 24 |
4248571898 ps |
| T1556 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/22.xbar_error_random.914446641 |
|
|
Aug 27 08:55:06 PM UTC 24 |
Aug 27 08:55:37 PM UTC 24 |
302245084 ps |
| T1557 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/22.xbar_error_and_unmapped_addr.3394253314 |
|
|
Aug 27 08:55:30 PM UTC 24 |
Aug 27 08:55:41 PM UTC 24 |
42440130 ps |
| T862 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/20.xbar_stress_all_with_reset_error.763832868 |
|
|
Aug 27 08:51:20 PM UTC 24 |
Aug 27 08:55:47 PM UTC 24 |
3988745115 ps |
| T1558 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/14.xbar_random_large_delays.795885090 |
|
|
Aug 27 08:33:51 PM UTC 24 |
Aug 27 08:55:56 PM UTC 24 |
106071512703 ps |
| T799 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/13.xbar_access_same_device_slow_rsp.670732276 |
|
|
Aug 27 08:31:49 PM UTC 24 |
Aug 27 08:56:00 PM UTC 24 |
92458120817 ps |
| T1559 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/22.xbar_smoke_large_delays.679090255 |
|
|
Aug 27 08:54:08 PM UTC 24 |
Aug 27 08:56:02 PM UTC 24 |
10187142168 ps |
| T1560 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/19.xbar_random_large_delays.909193115 |
|
|
Aug 27 08:46:34 PM UTC 24 |
Aug 27 08:56:06 PM UTC 24 |
44862974983 ps |
| T1561 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/22.xbar_access_same_device.4214505058 |
|
|
Aug 27 08:54:49 PM UTC 24 |
Aug 27 08:56:06 PM UTC 24 |
1536597117 ps |
| T1562 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/23.xbar_smoke.809058746 |
|
|
Aug 27 08:55:58 PM UTC 24 |
Aug 27 08:56:09 PM UTC 24 |
121028632 ps |
| T1563 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/23.xbar_smoke_zero_delays.1753744343 |
|
|
Aug 27 08:56:02 PM UTC 24 |
Aug 27 08:56:09 PM UTC 24 |
45805450 ps |
| T486 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/19.xbar_stress_all.1628378190 |
|
|
Aug 27 08:48:35 PM UTC 24 |
Aug 27 08:56:11 PM UTC 24 |
13611081715 ps |
| T1564 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/22.xbar_unmapped_addr.1258613556 |
|
|
Aug 27 08:55:26 PM UTC 24 |
Aug 27 08:56:12 PM UTC 24 |
291928659 ps |
| T802 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/12.xbar_access_same_device_slow_rsp.1942022894 |
|
|
Aug 27 08:30:08 PM UTC 24 |
Aug 27 08:56:19 PM UTC 24 |
96813422757 ps |
| T1565 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/23.xbar_random_zero_delays.391443654 |
|
|
Aug 27 08:56:24 PM UTC 24 |
Aug 27 08:56:40 PM UTC 24 |
89676867 ps |
| T497 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/21.xbar_stress_all.337390853 |
|
|
Aug 27 08:53:10 PM UTC 24 |
Aug 27 08:56:40 PM UTC 24 |
5328679481 ps |
| T1566 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/23.xbar_random.566200321 |
|
|
Aug 27 08:56:22 PM UTC 24 |
Aug 27 08:56:42 PM UTC 24 |
540085079 ps |
| T863 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/21.xbar_stress_all_with_rand_reset.296656553 |
|
|
Aug 27 08:53:13 PM UTC 24 |
Aug 27 08:56:53 PM UTC 24 |
1731207005 ps |
| T1567 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/23.xbar_unmapped_addr.3743238695 |
|
|
Aug 27 08:56:41 PM UTC 24 |
Aug 27 08:56:59 PM UTC 24 |
79548451 ps |
| T1568 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/19.chip_csr_mem_rw_with_rand_reset.1505702383 |
|
|
Aug 27 08:48:53 PM UTC 24 |
Aug 27 08:57:02 PM UTC 24 |
6299418526 ps |
| T870 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/22.xbar_stress_all_with_reset_error.3601163501 |
|
|
Aug 27 08:55:49 PM UTC 24 |
Aug 27 08:57:07 PM UTC 24 |
189405559 ps |
| T1569 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/22.xbar_stress_all_with_rand_reset.3233621580 |
|
|
Aug 27 08:55:41 PM UTC 24 |
Aug 27 08:57:13 PM UTC 24 |
745752758 ps |
| T1570 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/23.xbar_error_random.1902527532 |
|
|
Aug 27 08:56:35 PM UTC 24 |
Aug 27 08:57:14 PM UTC 24 |
342310637 ps |
| T506 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/20.xbar_stress_all_with_rand_reset.3529622648 |
|
|
Aug 27 08:51:05 PM UTC 24 |
Aug 27 08:57:20 PM UTC 24 |
4712234981 ps |
| T609 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/21.xbar_stress_all_with_error.2260243486 |
|
|
Aug 27 08:53:17 PM UTC 24 |
Aug 27 08:57:26 PM UTC 24 |
8117430725 ps |
| T1571 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/22.chip_tl_errors.2707958231 |
|
|
Aug 27 08:53:39 PM UTC 24 |
Aug 27 08:57:37 PM UTC 24 |
3721775747 ps |
| T1572 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/24.xbar_smoke.3255675971 |
|
|
Aug 27 08:57:29 PM UTC 24 |
Aug 27 08:57:39 PM UTC 24 |
38665087 ps |
| T1573 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/23.xbar_smoke_large_delays.3068666058 |
|
|
Aug 27 08:56:08 PM UTC 24 |
Aug 27 08:57:40 PM UTC 24 |
9559042177 ps |
| T1574 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/23.xbar_error_and_unmapped_addr.3878601219 |
|
|
Aug 27 08:57:03 PM UTC 24 |
Aug 27 08:57:42 PM UTC 24 |
875495242 ps |
| T1575 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/24.xbar_smoke_zero_delays.2660475555 |
|
|
Aug 27 08:57:35 PM UTC 24 |
Aug 27 08:57:46 PM UTC 24 |
57478210 ps |
| T829 |
/workspaces/repo/scratch/os_regression_2024_08_26/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/23.xbar_access_same_device.1997435560 |
|
|
Aug 27 08:56:31 PM UTC 24 |
Aug 27 08:57:48 PM UTC 24 |
1143616511 ps |