| T54 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/default/0.rom_e2e_shutdown_output.3605472795 |
|
|
Aug 29 04:24:43 PM UTC 24 |
Aug 29 05:34:52 PM UTC 24 |
32545230864 ps |
| T296 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_good_rma.583046588 |
|
|
Aug 29 04:25:00 PM UTC 24 |
Aug 29 05:35:32 PM UTC 24 |
15475866992 ps |
| T297 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_rstmgr_rst_cnsty_escalation.3125945573 |
|
|
Aug 29 05:21:09 PM UTC 24 |
Aug 29 05:35:33 PM UTC 24 |
4923971320 ps |
| T298 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_uart_tx_rx.3852228573 |
|
|
Aug 29 05:24:26 PM UTC 24 |
Aug 29 05:36:04 PM UTC 24 |
4586635194 ps |
| T258 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_lc_walkthrough_prod.332014282 |
|
|
Aug 29 03:41:14 PM UTC 24 |
Aug 29 05:36:46 PM UTC 24 |
48498021453 ps |
| T299 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/default/0.rom_e2e_shutdown_exception_c.2009867061 |
|
|
Aug 29 04:24:36 PM UTC 24 |
Aug 29 05:36:47 PM UTC 24 |
14396465025 ps |
| T300 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_bad_rma.1108639981 |
|
|
Aug 29 04:26:23 PM UTC 24 |
Aug 29 05:36:48 PM UTC 24 |
15347560360 ps |
| T634 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq.3131758215 |
|
|
Aug 29 04:17:26 PM UTC 24 |
Aug 29 05:36:51 PM UTC 24 |
25202094498 ps |
| T380 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_nothing_dev.1430323214 |
|
|
Aug 29 04:26:59 PM UTC 24 |
Aug 29 05:37:05 PM UTC 24 |
14076995816 ps |
| T130 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_uart_tx_rx_idx1.3783628124 |
|
|
Aug 29 05:25:48 PM UTC 24 |
Aug 29 05:37:20 PM UTC 24 |
4516162760 ps |
| T919 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_nothing_rma.3401992023 |
|
|
Aug 29 04:30:49 PM UTC 24 |
Aug 29 05:37:27 PM UTC 24 |
13536086075 ps |
| T132 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_uart_tx_rx_alt_clk_freq_low_speed.2623850713 |
|
|
Aug 29 05:30:18 PM UTC 24 |
Aug 29 05:38:17 PM UTC 24 |
3543162331 ps |
| T351 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_uart_tx_rx_idx2.2817291828 |
|
|
Aug 29 05:26:18 PM UTC 24 |
Aug 29 05:39:18 PM UTC 24 |
4848848480 ps |
| T920 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/default/0.rom_e2e_smoke.1184235555 |
|
|
Aug 29 04:23:51 PM UTC 24 |
Aug 29 05:39:36 PM UTC 24 |
14784195006 ps |
| T259 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_lc_walkthrough_rma.3250992832 |
|
|
Aug 29 03:41:34 PM UTC 24 |
Aug 29 05:40:05 PM UTC 24 |
46942511814 ps |
| T45 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_spi_host_tx_rx.95196 |
|
|
Aug 29 05:35:23 PM UTC 24 |
Aug 29 05:40:15 PM UTC 24 |
2950323096 ps |
| T921 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/default/0.rom_e2e_sigverify_always_a_nothing_b_bad_dev.1107022021 |
|
|
Aug 29 04:31:21 PM UTC 24 |
Aug 29 05:40:17 PM UTC 24 |
15124798875 ps |
| T133 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_uart_tx_rx_idx3.3696789921 |
|
|
Aug 29 05:26:42 PM UTC 24 |
Aug 29 05:40:44 PM UTC 24 |
4650172358 ps |
| T922 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_good_dev.4091947261 |
|
|
Aug 29 04:25:39 PM UTC 24 |
Aug 29 05:40:56 PM UTC 24 |
15048547066 ps |
| T122 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_i2c_host_tx_rx.510834000 |
|
|
Aug 29 05:30:15 PM UTC 24 |
Aug 29 05:41:59 PM UTC 24 |
4267276200 ps |
| T923 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_uart_tx_rx_alt_clk_freq.2828141309 |
|
|
Aug 29 05:30:21 PM UTC 24 |
Aug 29 05:42:14 PM UTC 24 |
4622563364 ps |
| T924 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_bad_dev.892434931 |
|
|
Aug 29 04:28:35 PM UTC 24 |
Aug 29 05:42:19 PM UTC 24 |
15957892160 ps |
| T78 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_spi_device_pinmux_sleep_retention.2206140315 |
|
|
Aug 29 05:35:28 PM UTC 24 |
Aug 29 05:42:21 PM UTC 24 |
3411788616 ps |
| T49 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_spi_device_tpm.2235401582 |
|
|
Aug 29 05:34:20 PM UTC 24 |
Aug 29 05:42:41 PM UTC 24 |
3687923066 ps |
| T664 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_nothing_prod.1112917511 |
|
|
Aug 29 04:30:48 PM UTC 24 |
Aug 29 05:42:45 PM UTC 24 |
14312268175 ps |
| T354 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_i2c_device_tx_rx.555892349 |
|
|
Aug 29 05:34:20 PM UTC 24 |
Aug 29 05:43:30 PM UTC 24 |
3622287528 ps |
| T925 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/default/0.rom_e2e_sigverify_always_a_nothing_b_bad_rma.349898142 |
|
|
Aug 29 04:31:00 PM UTC 24 |
Aug 29 05:43:31 PM UTC 24 |
14285775638 ps |
| T926 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_good_prod.3694258021 |
|
|
Aug 29 04:26:27 PM UTC 24 |
Aug 29 05:44:06 PM UTC 24 |
15549033250 ps |
| T41 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_gpio.12899734 |
|
|
Aug 29 05:36:36 PM UTC 24 |
Aug 29 05:44:14 PM UTC 24 |
3870845758 ps |
| T131 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_uart_rand_baudrate.1372739091 |
|
|
Aug 29 05:30:23 PM UTC 24 |
Aug 29 05:44:28 PM UTC 24 |
4513073536 ps |
| T188 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_otp_ctrl_vendor_test_csr_access.2829279108 |
|
|
Aug 29 05:42:32 PM UTC 24 |
Aug 29 05:44:34 PM UTC 24 |
2665816790 ps |
| T927 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/default/0.rom_e2e_sigverify_always_a_nothing_b_bad_prod.1895246507 |
|
|
Aug 29 04:31:21 PM UTC 24 |
Aug 29 05:44:47 PM UTC 24 |
15116543691 ps |
| T928 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/default/0.rom_e2e_asm_init_dev.985135782 |
|
|
Aug 29 04:30:17 PM UTC 24 |
Aug 29 05:44:50 PM UTC 24 |
15667112036 ps |
| T123 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_i2c_host_tx_rx_idx2.1700401693 |
|
|
Aug 29 05:30:40 PM UTC 24 |
Aug 29 05:44:50 PM UTC 24 |
4841548866 ps |
| T223 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_spi_device_pass_through_collision.3073677628 |
|
|
Aug 29 05:36:19 PM UTC 24 |
Aug 29 05:45:29 PM UTC 24 |
4356796675 ps |
| T137 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_i2c_host_tx_rx_idx1.3469633219 |
|
|
Aug 29 05:30:13 PM UTC 24 |
Aug 29 05:45:31 PM UTC 24 |
5501717180 ps |
| T929 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_lc_ctrl_otp_hw_cfg0.2782091112 |
|
|
Aug 29 05:40:59 PM UTC 24 |
Aug 29 05:45:38 PM UTC 24 |
2233021800 ps |
| T930 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_nothing_prod_end.2845966579 |
|
|
Aug 29 04:30:40 PM UTC 24 |
Aug 29 05:45:44 PM UTC 24 |
14678229588 ps |
| T931 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_good_prod_end.3046222538 |
|
|
Aug 29 04:28:04 PM UTC 24 |
Aug 29 05:45:51 PM UTC 24 |
15363204000 ps |
| T932 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_flash_ctrl_idle_low_power.2501638666 |
|
|
Aug 29 05:38:30 PM UTC 24 |
Aug 29 05:45:55 PM UTC 24 |
3637770400 ps |
| T933 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_kmac_entropy.3422335455 |
|
|
Aug 29 05:40:11 PM UTC 24 |
Aug 29 05:45:57 PM UTC 24 |
3141142896 ps |
| T638 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_lc_ctrl_volatile_raw_unlock.3264164995 |
|
|
Aug 29 05:44:14 PM UTC 24 |
Aug 29 05:46:04 PM UTC 24 |
1879551497 ps |
| T934 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/default/0.rom_e2e_sigverify_always_a_nothing_b_bad_prod_end.2352940330 |
|
|
Aug 29 04:30:46 PM UTC 24 |
Aug 29 05:46:44 PM UTC 24 |
14594421300 ps |
| T263 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_flash_ctrl_lc_rw_en.145731867 |
|
|
Aug 29 05:38:29 PM UTC 24 |
Aug 29 05:46:44 PM UTC 24 |
5414223064 ps |
| T935 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_bad_prod_end.3498793314 |
|
|
Aug 29 04:29:39 PM UTC 24 |
Aug 29 05:47:34 PM UTC 24 |
15651991598 ps |
| T639 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_lc_ctrl_rand_to_scrap.1193650619 |
|
|
Aug 29 05:43:24 PM UTC 24 |
Aug 29 05:47:44 PM UTC 24 |
3899805909 ps |
| T936 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/default/0.rom_e2e_asm_init_prod_end.1313280319 |
|
|
Aug 29 04:32:19 PM UTC 24 |
Aug 29 05:47:44 PM UTC 24 |
15430228548 ps |
| T640 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz.2137460831 |
|
|
Aug 29 05:46:18 PM UTC 24 |
Aug 29 05:48:12 PM UTC 24 |
1785292742 ps |
| T937 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_bad_prod.1592773864 |
|
|
Aug 29 04:27:15 PM UTC 24 |
Aug 29 05:48:12 PM UTC 24 |
14852864912 ps |
| T363 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_flash_ctrl_ops.466024116 |
|
|
Aug 29 05:38:30 PM UTC 24 |
Aug 29 05:48:23 PM UTC 24 |
4453411450 ps |
| T938 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_sleep_pwm_pulses.2545303270 |
|
|
Aug 29 05:23:28 PM UTC 24 |
Aug 29 05:48:32 PM UTC 24 |
8907400484 ps |
| T939 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_otp_ctrl_ecc_error_vendor_test.917220890 |
|
|
Aug 29 05:43:31 PM UTC 24 |
Aug 29 05:48:35 PM UTC 24 |
2541284378 ps |
| T224 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_spi_device_pass_through.178736397 |
|
|
Aug 29 05:36:18 PM UTC 24 |
Aug 29 05:49:00 PM UTC 24 |
6667467892 ps |
| T940 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/default/0.rom_e2e_asm_init_prod.3473511722 |
|
|
Aug 29 04:30:41 PM UTC 24 |
Aug 29 05:49:22 PM UTC 24 |
15986180001 ps |
| T941 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_rstmgr_sw_rst.3833348841 |
|
|
Aug 29 05:45:49 PM UTC 24 |
Aug 29 05:49:42 PM UTC 24 |
2846384884 ps |
| T942 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/default/0.rom_e2e_jtag_inject_dev.4141203993 |
|
|
Aug 29 04:40:21 PM UTC 24 |
Aug 29 05:49:55 PM UTC 24 |
29310197153 ps |
| T442 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/default/0.rom_e2e_jtag_inject_rma.3382022682 |
|
|
Aug 29 04:42:53 PM UTC 24 |
Aug 29 05:50:32 PM UTC 24 |
37425484110 ps |
| T359 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_flash_ctrl_ops_jitter_en.1617178960 |
|
|
Aug 29 05:38:28 PM UTC 24 |
Aug 29 05:50:35 PM UTC 24 |
5008038323 ps |
| T943 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/default/0.rom_e2e_asm_init_rma.1778139340 |
|
|
Aug 29 04:34:11 PM UTC 24 |
Aug 29 05:50:52 PM UTC 24 |
14967045444 ps |
| T944 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_otp_ctrl_lc_signals_test_unlocked0.3379237350 |
|
|
Aug 29 05:41:04 PM UTC 24 |
Aug 29 05:51:46 PM UTC 24 |
4474140248 ps |
| T945 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_rstmgr_sw_req.4197780843 |
|
|
Aug 29 05:46:52 PM UTC 24 |
Aug 29 05:53:12 PM UTC 24 |
3342031708 ps |
| T946 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_rv_timer_irq.2473007300 |
|
|
Aug 29 05:49:27 PM UTC 24 |
Aug 29 05:53:26 PM UTC 24 |
3323652964 ps |
| T653 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_pwrmgr_sleep_disabled.2170247422 |
|
|
Aug 29 05:48:31 PM UTC 24 |
Aug 29 05:53:35 PM UTC 24 |
3168678700 ps |
| T173 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_pwrmgr_full_aon_reset.152150449 |
|
|
Aug 29 05:47:22 PM UTC 24 |
Aug 29 05:54:03 PM UTC 24 |
6775653063 ps |
| T947 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_flash_ctrl_access_jitter_en.2948183828 |
|
|
Aug 29 05:38:28 PM UTC 24 |
Aug 29 05:54:40 PM UTC 24 |
6424076581 ps |
| T948 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_pwrmgr_main_power_glitch_reset.3611424935 |
|
|
Aug 29 05:47:41 PM UTC 24 |
Aug 29 05:55:34 PM UTC 24 |
4364508096 ps |
| T230 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_sysrst_ctrl_inputs.3281413147 |
|
|
Aug 29 05:49:55 PM UTC 24 |
Aug 29 05:55:45 PM UTC 24 |
3502560978 ps |
| T949 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_pwrmgr_usb_clk_disabled_when_active.3960702359 |
|
|
Aug 29 05:48:42 PM UTC 24 |
Aug 29 05:56:08 PM UTC 24 |
5593746088 ps |
| T231 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_sysrst_ctrl_outputs.370827241 |
|
|
Aug 29 05:49:59 PM UTC 24 |
Aug 29 05:56:20 PM UTC 24 |
3743106220 ps |
| T950 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_flash_ctrl_access.363866974 |
|
|
Aug 29 05:38:13 PM UTC 24 |
Aug 29 05:56:22 PM UTC 24 |
5900092320 ps |
| T47 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_sysrst_ctrl_ulp_z3_wakeup.1916209257 |
|
|
Aug 29 05:49:34 PM UTC 24 |
Aug 29 05:57:21 PM UTC 24 |
6256760064 ps |
| T370 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_aon_timer_irq.3675641244 |
|
|
Aug 29 05:50:29 PM UTC 24 |
Aug 29 05:57:39 PM UTC 24 |
3655605000 ps |
| T951 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_flash_ctrl_clock_freqs.1367892083 |
|
|
Aug 29 05:39:52 PM UTC 24 |
Aug 29 05:58:03 PM UTC 24 |
5811266655 ps |
| T952 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_pwrmgr_deep_sleep_power_glitch_reset.3293450298 |
|
|
Aug 29 05:47:45 PM UTC 24 |
Aug 29 05:58:18 PM UTC 24 |
6285296910 ps |
| T953 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/default/0.rom_e2e_keymgr_init_rom_ext_meas.3114365803 |
|
|
Aug 29 04:44:50 PM UTC 24 |
Aug 29 05:58:30 PM UTC 24 |
15783760180 ps |
| T954 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_lc_ctrl_transition.3133953931 |
|
|
Aug 29 05:43:27 PM UTC 24 |
Aug 29 05:58:31 PM UTC 24 |
11017873030 ps |
| T955 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_pwrmgr_normal_sleep_por_reset.2034639210 |
|
|
Aug 29 05:47:18 PM UTC 24 |
Aug 29 05:58:48 PM UTC 24 |
6118233970 ps |
| T956 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_aon_timer_sleep_wdog_sleep_pause.2749635366 |
|
|
Aug 29 05:51:25 PM UTC 24 |
Aug 29 05:59:35 PM UTC 24 |
6686089792 ps |
| T957 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_lc_walkthrough_prodend.2694935228 |
|
|
Aug 29 05:44:14 PM UTC 24 |
Aug 29 06:00:20 PM UTC 24 |
9197212000 ps |
| T958 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_aes_enc.1108482338 |
|
|
Aug 29 05:56:21 PM UTC 24 |
Aug 29 06:00:41 PM UTC 24 |
3488853830 ps |
| T959 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_aes_idle.2721421468 |
|
|
Aug 29 05:57:06 PM UTC 24 |
Aug 29 06:00:54 PM UTC 24 |
2567592558 ps |
| T960 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_otp_ctrl_lc_signals_rma.305094074 |
|
|
Aug 29 05:41:29 PM UTC 24 |
Aug 29 06:01:04 PM UTC 24 |
7535877886 ps |
| T961 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_pwrmgr_deep_sleep_por_reset.2787196444 |
|
|
Aug 29 05:48:14 PM UTC 24 |
Aug 29 06:01:05 PM UTC 24 |
10446174414 ps |
| T232 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_sysrst_ctrl_in_irq.2291207579 |
|
|
Aug 29 05:49:52 PM UTC 24 |
Aug 29 06:01:09 PM UTC 24 |
4488007869 ps |
| T91 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_usbdev_pincfg.3402201070 |
|
|
Aug 29 03:33:05 PM UTC 24 |
Aug 29 06:01:21 PM UTC 24 |
32172592814 ps |
| T268 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_rstmgr_cpu_info.2531911338 |
|
|
Aug 29 05:46:53 PM UTC 24 |
Aug 29 06:01:43 PM UTC 24 |
6000028032 ps |
| T962 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_aes_enc_jitter_en.292056331 |
|
|
Aug 29 05:56:50 PM UTC 24 |
Aug 29 06:01:47 PM UTC 24 |
2444824636 ps |
| T963 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_pwrmgr_wdog_reset.1235630618 |
|
|
Aug 29 05:51:29 PM UTC 24 |
Aug 29 06:02:12 PM UTC 24 |
4460071160 ps |
| T964 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_aes_masking_off.1061937370 |
|
|
Aug 29 05:57:07 PM UTC 24 |
Aug 29 06:02:23 PM UTC 24 |
2370500836 ps |
| T965 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/default/0.rom_e2e_keymgr_init_rom_ext_invalid_meas.2409217705 |
|
|
Aug 29 04:47:09 PM UTC 24 |
Aug 29 06:02:33 PM UTC 24 |
15229823560 ps |
| T966 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_pwrmgr_sysrst_ctrl_reset.2861842030 |
|
|
Aug 29 05:47:45 PM UTC 24 |
Aug 29 06:02:52 PM UTC 24 |
7767878522 ps |
| T967 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_otp_ctrl_lc_signals_dev.3169798896 |
|
|
Aug 29 05:41:04 PM UTC 24 |
Aug 29 06:03:01 PM UTC 24 |
7323400188 ps |
| T968 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/default/0.rom_e2e_keymgr_init_rom_ext_no_meas.2442394803 |
|
|
Aug 29 04:45:39 PM UTC 24 |
Aug 29 06:03:21 PM UTC 24 |
15646813800 ps |
| T74 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_alert_test.335476510 |
|
|
Aug 29 05:57:56 PM UTC 24 |
Aug 29 06:03:37 PM UTC 24 |
3634913048 ps |
| T301 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_otbn_mem_scramble.3135906575 |
|
|
Aug 29 05:54:38 PM UTC 24 |
Aug 29 06:03:45 PM UTC 24 |
4012547108 ps |
| T969 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_otp_ctrl_lc_signals_prod.1706722844 |
|
|
Aug 29 05:41:26 PM UTC 24 |
Aug 29 06:03:56 PM UTC 24 |
8791956530 ps |
| T364 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_alert_handler_ping_timeout.2282589575 |
|
|
Aug 29 05:58:37 PM UTC 24 |
Aug 29 06:05:06 PM UTC 24 |
3736841356 ps |
| T970 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_aon_timer_wdog_lc_escalate.1856247383 |
|
|
Aug 29 05:52:20 PM UTC 24 |
Aug 29 06:05:26 PM UTC 24 |
6421963500 ps |
| T369 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_adc_ctrl_sleep_debug_cable_wakeup.54893246 |
|
|
Aug 29 05:54:18 PM UTC 24 |
Aug 29 06:06:23 PM UTC 24 |
18636869018 ps |
| T971 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_entropy_src_kat_test.144324659 |
|
|
Aug 29 06:03:07 PM UTC 24 |
Aug 29 06:06:35 PM UTC 24 |
2447232572 ps |
| T448 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_csrng_edn_concurrency.2070498454 |
|
|
Aug 29 03:55:02 PM UTC 24 |
Aug 29 06:06:46 PM UTC 24 |
24902624148 ps |
| T972 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_pwrmgr_normal_sleep_all_reset_reqs.2197109648 |
|
|
Aug 29 05:47:37 PM UTC 24 |
Aug 29 06:07:13 PM UTC 24 |
9964008757 ps |
| T449 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_alert_handler_lpg_sleep_mode_alerts.197757310 |
|
|
Aug 29 05:59:31 PM UTC 24 |
Aug 29 06:07:13 PM UTC 24 |
4244324324 ps |
| T101 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_alert_handler_entropy.3446843782 |
|
|
Aug 29 06:01:14 PM UTC 24 |
Aug 29 06:07:23 PM UTC 24 |
3213117293 ps |
| T973 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_aes_entropy.225292338 |
|
|
Aug 29 06:02:06 PM UTC 24 |
Aug 29 06:07:32 PM UTC 24 |
3162763020 ps |
| T974 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_entropy_src_ast_rng_req.2164355063 |
|
|
Aug 29 06:03:43 PM UTC 24 |
Aug 29 06:07:35 PM UTC 24 |
2557347052 ps |
| T975 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_aon_timer_wdog_bite_reset.3516137037 |
|
|
Aug 29 05:51:26 PM UTC 24 |
Aug 29 06:08:41 PM UTC 24 |
10049000448 ps |
| T976 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_csrng_kat_test.627961438 |
|
|
Aug 29 06:03:25 PM UTC 24 |
Aug 29 06:08:49 PM UTC 24 |
3145340034 ps |
| T977 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_hmac_enc.2045605876 |
|
|
Aug 29 06:04:36 PM UTC 24 |
Aug 29 06:08:58 PM UTC 24 |
2649397216 ps |
| T978 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_alert_handler_escalation.4152967458 |
|
|
Aug 29 05:58:13 PM UTC 24 |
Aug 29 06:09:12 PM UTC 24 |
5282810558 ps |
| T979 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_hmac_enc_idle.2412745837 |
|
|
Aug 29 06:05:39 PM UTC 24 |
Aug 29 06:09:46 PM UTC 24 |
2901590688 ps |
| T980 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_hmac_enc_jitter_en.3383827019 |
|
|
Aug 29 06:04:36 PM UTC 24 |
Aug 29 06:10:10 PM UTC 24 |
2534763455 ps |
| T981 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_otbn_randomness.2456017760 |
|
|
Aug 29 05:54:34 PM UTC 24 |
Aug 29 06:10:13 PM UTC 24 |
5896554840 ps |
| T982 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_rv_core_ibex_rnd.3413521614 |
|
|
Aug 29 05:55:13 PM UTC 24 |
Aug 29 06:11:09 PM UTC 24 |
5800105670 ps |
| T348 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_rstmgr_alert_info.3386437668 |
|
|
Aug 29 05:45:48 PM UTC 24 |
Aug 29 06:11:34 PM UTC 24 |
10450669264 ps |
| T983 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_bad_test_unlocked0.4269778964 |
|
|
Aug 29 04:31:17 PM UTC 24 |
Aug 29 06:11:58 PM UTC 24 |
18420782130 ps |
| T398 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/default/0.rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0.1692952284 |
|
|
Aug 29 04:30:59 PM UTC 24 |
Aug 29 06:11:59 PM UTC 24 |
18573609788 ps |
| T984 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_hmac_oneshot.3159746711 |
|
|
Aug 29 06:05:59 PM UTC 24 |
Aug 29 06:12:29 PM UTC 24 |
3051822486 ps |
| T985 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/default/0.rom_e2e_static_critical.2090519816 |
|
|
Aug 29 04:44:49 PM UTC 24 |
Aug 29 06:12:48 PM UTC 24 |
17153699456 ps |
| T986 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_csrng_fuse_en_sw_app_read_test.471602981 |
|
|
Aug 29 06:03:24 PM UTC 24 |
Aug 29 06:12:53 PM UTC 24 |
3740840120 ps |
| T630 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_edn_boot_mode.1437312701 |
|
|
Aug 29 06:03:05 PM UTC 24 |
Aug 29 06:13:24 PM UTC 24 |
2996771080 ps |
| T987 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_kmac_mode_cshake.3072874872 |
|
|
Aug 29 06:08:33 PM UTC 24 |
Aug 29 06:13:25 PM UTC 24 |
2597028000 ps |
| T988 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_edn_kat.1423555186 |
|
|
Aug 29 06:02:33 PM UTC 24 |
Aug 29 06:13:51 PM UTC 24 |
3444296000 ps |
| T451 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_rv_core_ibex_nmi_irq.2401173974 |
|
|
Aug 29 05:56:17 PM UTC 24 |
Aug 29 06:14:14 PM UTC 24 |
4736475288 ps |
| T164 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_sensor_ctrl_alert.1319545611 |
|
|
Aug 29 06:12:44 PM UTC 24 |
Aug 29 06:27:58 PM UTC 24 |
7070900334 ps |
| T416 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_kmac_app_rom.450432631 |
|
|
Aug 29 06:09:47 PM UTC 24 |
Aug 29 06:14:40 PM UTC 24 |
2913946632 ps |
| T989 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_kmac_mode_kmac_jitter_en.886857859 |
|
|
Aug 29 06:09:42 PM UTC 24 |
Aug 29 06:14:42 PM UTC 24 |
3503719987 ps |
| T990 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_pwrmgr_all_reset_reqs.3783592978 |
|
|
Aug 29 05:47:41 PM UTC 24 |
Aug 29 06:15:36 PM UTC 24 |
9373442711 ps |
| T991 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_kmac_idle.2795110665 |
|
|
Aug 29 06:09:50 PM UTC 24 |
Aug 29 06:15:43 PM UTC 24 |
3389356616 ps |
| T992 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_csrng_lc_hw_debug_en_test.4031128177 |
|
|
Aug 29 06:03:37 PM UTC 24 |
Aug 29 06:15:59 PM UTC 24 |
6567444340 ps |
| T993 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_kmac_mode_kmac.71286707 |
|
|
Aug 29 06:09:34 PM UTC 24 |
Aug 29 06:15:59 PM UTC 24 |
3558994872 ps |
| T335 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_sensor_ctrl_status.1785414590 |
|
|
Aug 29 06:13:03 PM UTC 24 |
Aug 29 06:17:46 PM UTC 24 |
2937470153 ps |
| T994 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_pwrmgr_deep_sleep_all_reset_reqs.243034463 |
|
|
Aug 29 05:47:35 PM UTC 24 |
Aug 29 06:17:58 PM UTC 24 |
17015756514 ps |
| T233 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_sysrst_ctrl_reset.843240512 |
|
|
Aug 29 05:50:01 PM UTC 24 |
Aug 29 06:19:00 PM UTC 24 |
23174463596 ps |
| T417 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_rom_ctrl_integrity_check.2786408575 |
|
|
Aug 29 06:10:18 PM UTC 24 |
Aug 29 06:19:10 PM UTC 24 |
9776543766 ps |
| T281 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_plic_sw_irq.590026625 |
|
|
Aug 29 06:14:48 PM UTC 24 |
Aug 29 06:19:31 PM UTC 24 |
3089464088 ps |
| T302 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_sram_ctrl_scrambled_access_jitter_en.4267412920 |
|
|
Aug 29 06:10:55 PM UTC 24 |
Aug 29 06:20:20 PM UTC 24 |
4706659239 ps |
| T632 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_edn_auto_mode.2116613179 |
|
|
Aug 29 06:02:07 PM UTC 24 |
Aug 29 06:20:44 PM UTC 24 |
4448831040 ps |
| T260 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_flash_init.1821402684 |
|
|
Aug 29 05:38:17 PM UTC 24 |
Aug 29 06:20:48 PM UTC 24 |
24814025532 ps |
| T303 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_sram_ctrl_scrambled_access.182118202 |
|
|
Aug 29 06:10:54 PM UTC 24 |
Aug 29 06:20:54 PM UTC 24 |
4736209824 ps |
| T163 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup.3391733995 |
|
|
Aug 29 06:13:33 PM UTC 24 |
Aug 29 06:22:04 PM UTC 24 |
4721335494 ps |
| T995 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_sleep_sram_ret_contents_no_scramble.3038449557 |
|
|
Aug 29 06:12:08 PM UTC 24 |
Aug 29 06:22:51 PM UTC 24 |
6874320260 ps |
| T183 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_plic_all_irqs_10.3083234041 |
|
|
Aug 29 06:14:11 PM UTC 24 |
Aug 29 06:23:00 PM UTC 24 |
4654419942 ps |
| T996 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_alert_handler_lpg_clkoff.2564716930 |
|
|
Aug 29 06:00:10 PM UTC 24 |
Aug 29 06:23:07 PM UTC 24 |
6472332864 ps |
| T997 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_alert_handler_ping_ok.1937936818 |
|
|
Aug 29 05:59:27 PM UTC 24 |
Aug 29 06:23:08 PM UTC 24 |
7667900072 ps |
| T998 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_pwrmgr_random_sleep_all_reset_reqs.2710760826 |
|
|
Aug 29 05:47:36 PM UTC 24 |
Aug 29 06:23:30 PM UTC 24 |
23843412340 ps |
| T999 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_clkmgr_off_otbn_trans.3813191217 |
|
|
Aug 29 06:16:29 PM UTC 24 |
Aug 29 06:23:30 PM UTC 24 |
4616706160 ps |
| T282 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_alert_handler_lpg_sleep_mode_pings.1992317789 |
|
|
Aug 29 05:59:32 PM UTC 24 |
Aug 29 06:24:12 PM UTC 24 |
11497442800 ps |
| T1000 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_clkmgr_off_aes_trans.1718098240 |
|
|
Aug 29 06:15:37 PM UTC 24 |
Aug 29 06:24:13 PM UTC 24 |
5528638750 ps |
| T320 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_sram_ctrl_execution_main.4203053255 |
|
|
Aug 29 06:11:42 PM UTC 24 |
Aug 29 06:25:28 PM UTC 24 |
8020418918 ps |
| T1001 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_clkmgr_off_hmac_trans.2351906183 |
|
|
Aug 29 06:15:37 PM UTC 24 |
Aug 29 06:25:49 PM UTC 24 |
4066062004 ps |
| T1002 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_lc_walkthrough_testunlocks.3914166645 |
|
|
Aug 29 05:46:30 PM UTC 24 |
Aug 29 06:25:53 PM UTC 24 |
29894019905 ps |
| T304 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_sleep_sram_ret_contents_scramble.4108319177 |
|
|
Aug 29 06:12:43 PM UTC 24 |
Aug 29 06:25:55 PM UTC 24 |
7804142612 ps |
| T1003 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_edn_entropy_reqs_jitter.3636821920 |
|
|
Aug 29 06:04:34 PM UTC 24 |
Aug 29 06:26:06 PM UTC 24 |
6655096004 ps |
| T1004 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_clkmgr_off_kmac_trans.3122966731 |
|
|
Aug 29 06:16:39 PM UTC 24 |
Aug 29 06:26:13 PM UTC 24 |
5238893742 ps |
| T1005 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_clkmgr_jitter.2521519771 |
|
|
Aug 29 06:21:37 PM UTC 24 |
Aug 29 06:26:19 PM UTC 24 |
2857431061 ps |
| T1006 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_clkmgr_external_clk_src_for_lc.2903098691 |
|
|
Aug 29 06:16:45 PM UTC 24 |
Aug 29 06:26:21 PM UTC 24 |
7661252664 ps |
| T327 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_plic_all_irqs_20.3984705015 |
|
|
Aug 29 06:14:26 PM UTC 24 |
Aug 29 06:27:01 PM UTC 24 |
4941659028 ps |
| T1007 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0.437443161 |
|
|
Aug 29 06:18:29 PM UTC 24 |
Aug 29 06:27:32 PM UTC 24 |
4125356220 ps |
| T1008 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0.3184580078 |
|
|
Aug 29 06:16:41 PM UTC 24 |
Aug 29 06:27:38 PM UTC 24 |
3871830546 ps |
| T97 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_jtag_csr_rw.3183726605 |
|
|
Aug 29 06:22:25 PM UTC 24 |
Aug 29 06:27:51 PM UTC 24 |
4512076876 ps |
| T1009 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_edn_entropy_reqs.1939440093 |
|
|
Aug 29 06:04:27 PM UTC 24 |
Aug 29 06:27:54 PM UTC 24 |
7638422204 ps |
| T1010 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_clkmgr_jitter_frequency.2757587137 |
|
|
Aug 29 06:21:37 PM UTC 24 |
Aug 29 06:28:35 PM UTC 24 |
3440492192 ps |
| T1011 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_clkmgr_reset_frequency.2124347164 |
|
|
Aug 29 06:20:54 PM UTC 24 |
Aug 29 06:29:21 PM UTC 24 |
4190398816 ps |
| T90 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_tap_straps_testunlock0.3070367625 |
|
|
Aug 29 06:27:02 PM UTC 24 |
Aug 29 06:29:50 PM UTC 24 |
2913438836 ps |
| T1012 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_clkmgr_external_clk_src_for_sw_slow_dev.3364408574 |
|
|
Aug 29 06:19:41 PM UTC 24 |
Aug 29 06:29:51 PM UTC 24 |
4251927784 ps |
| T1013 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_tap_straps_rma.3987270897 |
|
|
Aug 29 06:26:50 PM UTC 24 |
Aug 29 06:29:58 PM UTC 24 |
2888972223 ps |
| T1014 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_clkmgr_external_clk_src_for_sw_slow_rma.3596827632 |
|
|
Aug 29 06:20:05 PM UTC 24 |
Aug 29 06:30:11 PM UTC 24 |
4904044634 ps |
| T1015 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_clkmgr_external_clk_src_for_sw_fast_dev.2106800811 |
|
|
Aug 29 06:18:34 PM UTC 24 |
Aug 29 06:30:30 PM UTC 24 |
3882082502 ps |
| T1016 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_clkmgr_external_clk_src_for_sw_fast_rma.175797234 |
|
|
Aug 29 06:19:44 PM UTC 24 |
Aug 29 06:30:40 PM UTC 24 |
4429461320 ps |
| T356 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_pwrmgr_lowpower_cancel.1001175931 |
|
|
Aug 29 06:24:22 PM UTC 24 |
Aug 29 06:30:55 PM UTC 24 |
3628625924 ps |
| T1017 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_clkmgr_sleep_frequency.1006015343 |
|
|
Aug 29 06:21:40 PM UTC 24 |
Aug 29 06:31:32 PM UTC 24 |
4853248760 ps |
| T1018 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_keymgr_key_derivation_prod.3074493159 |
|
|
Aug 29 06:07:24 PM UTC 24 |
Aug 29 06:32:33 PM UTC 24 |
7762295288 ps |
| T115 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_pwrmgr_normal_sleep_all_wake_ups.142011159 |
|
|
Aug 29 06:24:23 PM UTC 24 |
Aug 29 06:32:46 PM UTC 24 |
7555732000 ps |
| T194 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_lc_ctrl_program_error.1021219508 |
|
|
Aug 29 06:24:19 PM UTC 24 |
Aug 29 06:32:52 PM UTC 24 |
4613582076 ps |
| T207 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_rv_core_ibex_icache_invalidate.483089157 |
|
|
Aug 29 06:28:55 PM UTC 24 |
Aug 29 06:32:55 PM UTC 24 |
2977090367 ps |
| T1019 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_edn_sw_mode.2551628426 |
|
|
Aug 29 06:02:46 PM UTC 24 |
Aug 29 06:33:32 PM UTC 24 |
7820136492 ps |
| T1020 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_tap_straps_dev.2899806439 |
|
|
Aug 29 06:27:03 PM UTC 24 |
Aug 29 06:33:35 PM UTC 24 |
3794463160 ps |
| T1021 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_clkmgr_jitter_reduced_freq.3052602023 |
|
|
Aug 29 06:29:10 PM UTC 24 |
Aug 29 06:33:38 PM UTC 24 |
2943636072 ps |
| T1022 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_pwrmgr_sleep_wake_5_bug.599514112 |
|
|
Aug 29 06:25:04 PM UTC 24 |
Aug 29 06:33:39 PM UTC 24 |
5167537368 ps |
| T269 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_rv_core_ibex_address_translation.1448581611 |
|
|
Aug 29 06:28:24 PM UTC 24 |
Aug 29 06:33:44 PM UTC 24 |
3150476050 ps |
| T337 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_entropy_src_csrng.961184248 |
|
|
Aug 29 06:03:54 PM UTC 24 |
Aug 29 06:34:12 PM UTC 24 |
7820132492 ps |
| T381 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up.2446065850 |
|
|
Aug 29 06:26:01 PM UTC 24 |
Aug 29 06:34:43 PM UTC 24 |
6728221830 ps |
| T636 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_rv_dm_access_after_escalation_reset.2760664294 |
|
|
Aug 29 06:27:11 PM UTC 24 |
Aug 29 06:35:05 PM UTC 24 |
4518253706 ps |
| T1023 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_rv_dm_access_after_wakeup.3854089837 |
|
|
Aug 29 06:27:10 PM UTC 24 |
Aug 29 06:35:33 PM UTC 24 |
5985653220 ps |
| T117 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_rv_dm_ndm_reset_req.3881233040 |
|
|
Aug 29 06:27:12 PM UTC 24 |
Aug 29 06:35:35 PM UTC 24 |
3849240024 ps |
| T330 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_plic_all_irqs_0.2080911531 |
|
|
Aug 29 06:14:11 PM UTC 24 |
Aug 29 06:35:48 PM UTC 24 |
6466893750 ps |
| T1024 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_bad_prod.4160495166 |
|
|
Aug 29 04:28:01 PM UTC 24 |
Aug 29 06:35:51 PM UTC 24 |
24052019688 ps |
| T1025 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_hmac_enc_jitter_en_reduced_freq.2494056843 |
|
|
Aug 29 06:31:27 PM UTC 24 |
Aug 29 06:35:56 PM UTC 24 |
3079554961 ps |
| T1026 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_flash_ctrl_write_clear.341291279 |
|
|
Aug 29 06:29:05 PM UTC 24 |
Aug 29 06:36:07 PM UTC 24 |
3594958920 ps |
| T1027 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_alert_handler_lpg_reset_toggle.521762921 |
|
|
Aug 29 06:00:52 PM UTC 24 |
Aug 29 06:36:16 PM UTC 24 |
8461587928 ps |
| T1028 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_aes_enc_jitter_en_reduced_freq.2497750540 |
|
|
Aug 29 06:31:26 PM UTC 24 |
Aug 29 06:36:49 PM UTC 24 |
3146479780 ps |
| T1029 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_keymgr_key_derivation.1733930494 |
|
|
Aug 29 06:07:23 PM UTC 24 |
Aug 29 06:37:01 PM UTC 24 |
9214706700 ps |
| T1030 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_kmac_mode_kmac_jitter_en_reduced_freq.2251287497 |
|
|
Aug 29 06:31:35 PM UTC 24 |
Aug 29 06:37:04 PM UTC 24 |
2690272065 ps |
| T372 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_rv_dm_ndm_reset_req_when_cpu_halted.1519590494 |
|
|
Aug 29 06:27:09 PM UTC 24 |
Aug 29 06:37:20 PM UTC 24 |
5399765750 ps |
| T1031 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_hmac_multistream.2588926523 |
|
|
Aug 29 06:07:06 PM UTC 24 |
Aug 29 06:37:49 PM UTC 24 |
8042361928 ps |
| T368 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_flash_crash_alert.110804120 |
|
|
Aug 29 06:28:53 PM UTC 24 |
Aug 29 06:37:50 PM UTC 24 |
5048814190 ps |
| T399 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/default/0.rom_e2e_boot_policy_valid_a_bad_b_good_prod_end.392649091 |
|
|
Aug 29 04:30:19 PM UTC 24 |
Aug 29 06:37:56 PM UTC 24 |
24296833800 ps |
| T1032 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_bad_rma.4287089663 |
|
|
Aug 29 04:30:15 PM UTC 24 |
Aug 29 06:38:03 PM UTC 24 |
22645552830 ps |
| T1033 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_clkmgr_off_peri.4029421111 |
|
|
Aug 29 06:15:36 PM UTC 24 |
Aug 29 06:38:24 PM UTC 24 |
11389295236 ps |
| T1034 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_bad_prod_end.2738083947 |
|
|
Aug 29 04:31:29 PM UTC 24 |
Aug 29 06:39:21 PM UTC 24 |
23934829640 ps |
| T400 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/default/0.rom_e2e_boot_policy_valid_a_bad_b_good_dev.338130025 |
|
|
Aug 29 04:30:16 PM UTC 24 |
Aug 29 06:39:28 PM UTC 24 |
24406662418 ps |
| T366 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_flash_ctrl_ops_jitter_en_reduced_freq.823591113 |
|
|
Aug 29 06:29:57 PM UTC 24 |
Aug 29 06:39:55 PM UTC 24 |
4902478090 ps |
| T658 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_power_sleep_load.1657990468 |
|
|
Aug 29 06:34:11 PM UTC 24 |
Aug 29 06:40:24 PM UTC 24 |
4644534304 ps |
| T1035 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_ast_clk_outputs.4099160012 |
|
|
Aug 29 06:24:08 PM UTC 24 |
Aug 29 06:42:34 PM UTC 24 |
8007352984 ps |
| T305 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq.681173773 |
|
|
Aug 29 06:31:34 PM UTC 24 |
Aug 29 06:42:39 PM UTC 24 |
5131415923 ps |
| T1036 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_flash_scrambling_smoketest.2937848176 |
|
|
Aug 29 06:38:16 PM UTC 24 |
Aug 29 06:42:41 PM UTC 24 |
3054011918 ps |
| T1037 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/default/1.rom_volatile_raw_unlock.3001557340 |
|
|
Aug 29 06:41:05 PM UTC 24 |
Aug 29 06:43:37 PM UTC 24 |
2253471054 ps |
| T179 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/default/1.rom_raw_unlock.1550534274 |
|
|
Aug 29 06:39:24 PM UTC 24 |
Aug 29 06:43:43 PM UTC 24 |
6058087946 ps |
| T1038 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/default/0.rom_e2e_boot_policy_valid_a_bad_b_good_rma.26158781 |
|
|
Aug 29 04:27:41 PM UTC 24 |
Aug 29 06:44:24 PM UTC 24 |
24013396488 ps |
| T1039 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_aon_timer_smoketest.2752220061 |
|
|
Aug 29 06:39:32 PM UTC 24 |
Aug 29 06:44:32 PM UTC 24 |
2505654580 ps |
| T1040 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_clkmgr_smoketest.144070140 |
|
|
Aug 29 06:40:22 PM UTC 24 |
Aug 29 06:44:54 PM UTC 24 |
3289561396 ps |
| T1041 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_aes_smoketest.244975462 |
|
|
Aug 29 06:39:57 PM UTC 24 |
Aug 29 06:44:59 PM UTC 24 |
3250770400 ps |
| T1042 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_bad_dev.2964303820 |
|
|
Aug 29 04:31:26 PM UTC 24 |
Aug 29 06:45:11 PM UTC 24 |
23967672340 ps |
| T1043 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_power_idle_load.353748869 |
|
|
Aug 29 06:34:36 PM UTC 24 |
Aug 29 06:45:32 PM UTC 24 |
4969192446 ps |
| T1044 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_kmac_smoketest.3136915778 |
|
|
Aug 29 06:40:40 PM UTC 24 |
Aug 29 06:45:37 PM UTC 24 |
3328063810 ps |
| T1045 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_csrng_smoketest.1727320295 |
|
|
Aug 29 06:40:57 PM UTC 24 |
Aug 29 06:45:37 PM UTC 24 |
2902806010 ps |
| T1046 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_hmac_smoketest.2603530497 |
|
|
Aug 29 06:40:43 PM UTC 24 |
Aug 29 06:45:38 PM UTC 24 |
3136876200 ps |
| T1047 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_gpio_smoketest.1289536272 |
|
|
Aug 29 06:41:03 PM UTC 24 |
Aug 29 06:45:40 PM UTC 24 |
2945378906 ps |
| T227 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_jtag_mem_access.670566144 |
|
|
Aug 29 06:23:10 PM UTC 24 |
Aug 29 06:45:56 PM UTC 24 |
14170136819 ps |
| T1048 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_otp_ctrl_smoketest.667550037 |
|
|
Aug 29 06:41:07 PM UTC 24 |
Aug 29 06:46:13 PM UTC 24 |
2911555360 ps |
| T1049 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_rv_plic_smoketest.3703772059 |
|
|
Aug 29 06:43:28 PM UTC 24 |
Aug 29 06:47:03 PM UTC 24 |
2667724752 ps |
| T1050 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_example_rom.2828175853 |
|
|
Aug 29 06:45:28 PM UTC 24 |
Aug 29 06:48:06 PM UTC 24 |
2889814124 ps |
| T1051 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_entropy_src_smoketest.2849504173 |
|
|
Aug 29 06:40:14 PM UTC 24 |
Aug 29 06:48:15 PM UTC 24 |
3292881700 ps |
| T1052 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_sram_ctrl_smoketest.1373226827 |
|
|
Aug 29 06:45:08 PM UTC 24 |
Aug 29 06:48:34 PM UTC 24 |
2738163682 ps |
| T1053 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/default/0.rom_e2e_boot_policy_valid_a_bad_b_good_prod.3211476433 |
|
|
Aug 29 04:31:26 PM UTC 24 |
Aug 29 06:48:40 PM UTC 24 |
24247696252 ps |
| T1054 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_example_manufacturer.2274486674 |
|
|
Aug 29 06:45:46 PM UTC 24 |
Aug 29 06:48:42 PM UTC 24 |
2512127498 ps |
| T1055 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_pwrmgr_usbdev_smoketest.2558049697 |
|
|
Aug 29 06:43:28 PM UTC 24 |
Aug 29 06:48:45 PM UTC 24 |
5777137668 ps |
| T1056 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_rstmgr_smoketest.508809301 |
|
|
Aug 29 06:44:21 PM UTC 24 |
Aug 29 06:49:05 PM UTC 24 |
2779480216 ps |
| T1057 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_rv_timer_smoketest.866120168 |
|
|
Aug 29 06:44:21 PM UTC 24 |
Aug 29 06:49:19 PM UTC 24 |
3478675356 ps |
| T1058 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_flash_ctrl_access_jitter_en_reduced_freq.1229765653 |
|
|
Aug 29 06:31:26 PM UTC 24 |
Aug 29 06:49:34 PM UTC 24 |
7543751678 ps |
| T1059 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_example_flash.862743819 |
|
|
Aug 29 06:45:31 PM UTC 24 |
Aug 29 06:50:27 PM UTC 24 |
2909724710 ps |
| T1060 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_uart_smoketest.1501716015 |
|
|
Aug 29 06:45:09 PM UTC 24 |
Aug 29 06:50:48 PM UTC 24 |
3221693448 ps |
| T1061 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_keymgr_sideload_kmac.4291848694 |
|
|
Aug 29 06:08:36 PM UTC 24 |
Aug 29 06:50:53 PM UTC 24 |
12506178756 ps |
| T1062 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_keymgr_key_derivation_jitter_en.1659094436 |
|
|
Aug 29 06:08:31 PM UTC 24 |
Aug 29 06:50:54 PM UTC 24 |
11827928071 ps |
| T1063 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_tap_straps_prod.3617277888 |
|
|
Aug 29 06:27:27 PM UTC 24 |
Aug 29 06:50:58 PM UTC 24 |
13539471823 ps |
| T1064 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_pwrmgr_smoketest.391734371 |
|
|
Aug 29 06:43:31 PM UTC 24 |
Aug 29 06:51:16 PM UTC 24 |
5656279080 ps |
| T1065 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/default/1.rom_keymgr_functest.2700150060 |
|
|
Aug 29 06:40:56 PM UTC 24 |
Aug 29 06:51:20 PM UTC 24 |
5521322888 ps |
| T77 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_sleep_pin_retention.1842961777 |
|
|
Aug 29 06:47:37 PM UTC 24 |
Aug 29 06:51:54 PM UTC 24 |
3403674408 ps |
| T135 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_pattgen_ios.2937185365 |
|
|
Aug 29 06:48:51 PM UTC 24 |
Aug 29 06:52:11 PM UTC 24 |
2660127064 ps |
| T1066 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_example_concurrency.2221576984 |
|
|
Aug 29 06:46:53 PM UTC 24 |
Aug 29 06:52:11 PM UTC 24 |
2864038906 ps |
| T251 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_keymgr_sideload_aes.3565485330 |
|
|
Aug 29 06:08:33 PM UTC 24 |
Aug 29 06:52:20 PM UTC 24 |
12504984430 ps |
| T22 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_sleep_pin_mio_dio_val.2454493433 |
|
|
Aug 29 06:47:19 PM UTC 24 |
Aug 29 06:53:06 PM UTC 24 |
3361584306 ps |
| T1067 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sival_flash_info_access.856251296 |
|
|
Aug 29 06:46:52 PM UTC 24 |
Aug 29 06:53:19 PM UTC 24 |
3224950910 ps |
| T1068 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_sysrst_ctrl_ec_rst_l.1768266022 |
|
|
Aug 29 05:50:16 PM UTC 24 |
Aug 29 06:53:22 PM UTC 24 |
20846243446 ps |
| T1069 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_flash_ctrl_mem_protection.270128771 |
|
|
Aug 29 06:38:04 PM UTC 24 |
Aug 29 06:55:31 PM UTC 24 |
4904598008 ps |
| T1070 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_pwrmgr_b2b_sleep_reset_req.3507695222 |
|
|
Aug 29 06:13:34 PM UTC 24 |
Aug 29 06:56:25 PM UTC 24 |
27039100480 ps |
| T27 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_sleep_pin_wake.3414543527 |
|
|
Aug 29 06:47:14 PM UTC 24 |
Aug 29 06:57:50 PM UTC 24 |
6614314742 ps |
| T1071 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_rstmgr_rst_cnsty_escalation.7727921 |
|
|
Aug 29 06:47:19 PM UTC 24 |
Aug 29 06:58:54 PM UTC 24 |
5939119434 ps |
| T50 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_spi_device_tpm.1470191302 |
|
|
Aug 29 06:53:06 PM UTC 24 |
Aug 29 06:58:56 PM UTC 24 |
3606539856 ps |