| T2512 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/69.xbar_access_same_device_slow_rsp.2703732373 |
|
|
Aug 29 02:54:34 PM UTC 24 |
Aug 29 03:06:48 PM UTC 24 |
39641775614 ps |
| T2513 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/78.xbar_smoke_large_delays.3642817427 |
|
|
Aug 29 03:04:32 PM UTC 24 |
Aug 29 03:06:51 PM UTC 24 |
9110945579 ps |
| T2514 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/80.xbar_smoke_zero_delays.2690052610 |
|
|
Aug 29 03:06:43 PM UTC 24 |
Aug 29 03:06:52 PM UTC 24 |
34097958 ps |
| T2515 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/74.xbar_stress_all_with_error.140317313 |
|
|
Aug 29 03:00:09 PM UTC 24 |
Aug 29 03:06:53 PM UTC 24 |
4932228323 ps |
| T2516 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/79.xbar_smoke_slow_rsp.2303555708 |
|
|
Aug 29 03:05:40 PM UTC 24 |
Aug 29 03:06:56 PM UTC 24 |
3298538441 ps |
| T2517 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/80.xbar_smoke.1554503308 |
|
|
Aug 29 03:06:43 PM UTC 24 |
Aug 29 03:06:57 PM UTC 24 |
174586343 ps |
| T2518 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/73.xbar_random_large_delays.3129334238 |
|
|
Aug 29 02:58:42 PM UTC 24 |
Aug 29 03:06:59 PM UTC 24 |
38856794408 ps |
| T2519 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/60.xbar_access_same_device_slow_rsp.2648305745 |
|
|
Aug 29 02:44:11 PM UTC 24 |
Aug 29 03:06:59 PM UTC 24 |
83506715325 ps |
| T2520 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/73.xbar_stress_all_with_reset_error.2657820632 |
|
|
Aug 29 02:59:14 PM UTC 24 |
Aug 29 03:07:02 PM UTC 24 |
4948206495 ps |
| T2521 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/78.xbar_stress_all_with_reset_error.2684066511 |
|
|
Aug 29 03:05:16 PM UTC 24 |
Aug 29 03:07:07 PM UTC 24 |
336705449 ps |
| T2522 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/73.xbar_stress_all_with_error.4208467215 |
|
|
Aug 29 02:59:14 PM UTC 24 |
Aug 29 03:07:10 PM UTC 24 |
12984226554 ps |
| T2523 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/79.xbar_smoke_large_delays.73741216 |
|
|
Aug 29 03:05:37 PM UTC 24 |
Aug 29 03:07:14 PM UTC 24 |
6690500928 ps |
| T2524 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/66.xbar_access_same_device_slow_rsp.3077989291 |
|
|
Aug 29 02:51:11 PM UTC 24 |
Aug 29 03:07:18 PM UTC 24 |
55752709267 ps |
| T2525 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/80.xbar_access_same_device.3623467311 |
|
|
Aug 29 03:07:09 PM UTC 24 |
Aug 29 03:07:18 PM UTC 24 |
64524655 ps |
| T2526 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/80.xbar_random.911649219 |
|
|
Aug 29 03:06:52 PM UTC 24 |
Aug 29 03:07:20 PM UTC 24 |
616003443 ps |
| T2527 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/67.xbar_random_large_delays.1191748636 |
|
|
Aug 29 02:52:09 PM UTC 24 |
Aug 29 03:07:22 PM UTC 24 |
75032045613 ps |
| T2528 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/70.xbar_random_large_delays.1146662721 |
|
|
Aug 29 02:55:42 PM UTC 24 |
Aug 29 03:07:23 PM UTC 24 |
64180769027 ps |
| T2529 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/80.xbar_random_zero_delays.3624846032 |
|
|
Aug 29 03:06:54 PM UTC 24 |
Aug 29 03:07:25 PM UTC 24 |
308391934 ps |
| T2530 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/80.xbar_error_random.1562062475 |
|
|
Aug 29 03:07:10 PM UTC 24 |
Aug 29 03:07:25 PM UTC 24 |
334246732 ps |
| T2531 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/75.xbar_stress_all_with_error.2691658830 |
|
|
Aug 29 03:01:14 PM UTC 24 |
Aug 29 03:07:29 PM UTC 24 |
4221771852 ps |
| T2532 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/77.xbar_random_large_delays.2458641775 |
|
|
Aug 29 03:03:26 PM UTC 24 |
Aug 29 03:07:36 PM UTC 24 |
18249609088 ps |
| T2533 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/81.xbar_smoke.523452062 |
|
|
Aug 29 03:07:26 PM UTC 24 |
Aug 29 03:07:37 PM UTC 24 |
51766814 ps |
| T2534 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/77.xbar_stress_all_with_error.3405885039 |
|
|
Aug 29 03:04:11 PM UTC 24 |
Aug 29 03:07:40 PM UTC 24 |
2820957792 ps |
| T2535 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/81.xbar_smoke_zero_delays.1807232444 |
|
|
Aug 29 03:07:30 PM UTC 24 |
Aug 29 03:07:40 PM UTC 24 |
37085898 ps |
| T2536 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/80.xbar_error_and_unmapped_addr.16311964 |
|
|
Aug 29 03:07:15 PM UTC 24 |
Aug 29 03:07:40 PM UTC 24 |
223622835 ps |
| T2537 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/81.xbar_random_zero_delays.2973995191 |
|
|
Aug 29 03:07:39 PM UTC 24 |
Aug 29 03:07:52 PM UTC 24 |
68983138 ps |
| T2538 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/80.xbar_unmapped_addr.1895017752 |
|
|
Aug 29 03:07:13 PM UTC 24 |
Aug 29 03:07:53 PM UTC 24 |
959625754 ps |
| T2539 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/81.xbar_access_same_device.1466237923 |
|
|
Aug 29 03:07:44 PM UTC 24 |
Aug 29 03:07:59 PM UTC 24 |
239462089 ps |
| T2540 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/80.xbar_same_source.2082464402 |
|
|
Aug 29 03:07:11 PM UTC 24 |
Aug 29 03:08:08 PM UTC 24 |
1336577951 ps |
| T2541 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/81.xbar_error_and_unmapped_addr.2570843191 |
|
|
Aug 29 03:08:01 PM UTC 24 |
Aug 29 03:08:11 PM UTC 24 |
73799415 ps |
| T2542 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/79.xbar_access_same_device.1924146285 |
|
|
Aug 29 03:05:54 PM UTC 24 |
Aug 29 03:08:15 PM UTC 24 |
2895057743 ps |
| T2543 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/81.xbar_same_source.1235805456 |
|
|
Aug 29 03:07:49 PM UTC 24 |
Aug 29 03:08:17 PM UTC 24 |
599014031 ps |
| T2544 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/77.xbar_random_slow_rsp.3161331727 |
|
|
Aug 29 03:03:27 PM UTC 24 |
Aug 29 03:08:18 PM UTC 24 |
20802283517 ps |
| T2545 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/81.xbar_error_random.1157728499 |
|
|
Aug 29 03:07:55 PM UTC 24 |
Aug 29 03:08:20 PM UTC 24 |
443881391 ps |
| T607 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/76.xbar_stress_all_with_error.1646380136 |
|
|
Aug 29 03:02:53 PM UTC 24 |
Aug 29 03:08:19 PM UTC 24 |
10571124037 ps |
| T2546 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/79.xbar_stress_all_with_rand_reset.342181716 |
|
|
Aug 29 03:06:32 PM UTC 24 |
Aug 29 03:08:24 PM UTC 24 |
317171319 ps |
| T2547 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/80.xbar_smoke_large_delays.1705908672 |
|
|
Aug 29 03:06:51 PM UTC 24 |
Aug 29 03:08:28 PM UTC 24 |
9792256289 ps |
| T2548 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/80.xbar_smoke_slow_rsp.3820162378 |
|
|
Aug 29 03:06:51 PM UTC 24 |
Aug 29 03:08:29 PM UTC 24 |
4733112838 ps |
| T2549 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/82.xbar_smoke.3221617011 |
|
|
Aug 29 03:08:20 PM UTC 24 |
Aug 29 03:08:30 PM UTC 24 |
49236952 ps |
| T2550 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/82.xbar_smoke_zero_delays.2994323026 |
|
|
Aug 29 03:08:27 PM UTC 24 |
Aug 29 03:08:37 PM UTC 24 |
42731834 ps |
| T2551 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/80.xbar_stress_all_with_error.4235826541 |
|
|
Aug 29 03:07:20 PM UTC 24 |
Aug 29 03:08:37 PM UTC 24 |
1090775114 ps |
| T2552 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/49.xbar_access_same_device_slow_rsp.2324104696 |
|
|
Aug 29 02:30:08 PM UTC 24 |
Aug 29 03:08:47 PM UTC 24 |
157778180129 ps |
| T2553 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/78.xbar_access_same_device_slow_rsp.1820868620 |
|
|
Aug 29 03:04:51 PM UTC 24 |
Aug 29 03:08:53 PM UTC 24 |
13831225494 ps |
| T2554 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/82.xbar_access_same_device.3348877680 |
|
|
Aug 29 03:08:43 PM UTC 24 |
Aug 29 03:08:55 PM UTC 24 |
79828780 ps |
| T2555 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/80.xbar_random_slow_rsp.4073654536 |
|
|
Aug 29 03:07:01 PM UTC 24 |
Aug 29 03:08:55 PM UTC 24 |
5957122449 ps |
| T2556 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/81.xbar_smoke_slow_rsp.3224889525 |
|
|
Aug 29 03:07:38 PM UTC 24 |
Aug 29 03:08:57 PM UTC 24 |
5412313514 ps |
| T2557 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/82.xbar_same_source.1384871348 |
|
|
Aug 29 03:08:49 PM UTC 24 |
Aug 29 03:08:59 PM UTC 24 |
49974816 ps |
| T2558 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/82.xbar_random_zero_delays.977521043 |
|
|
Aug 29 03:08:39 PM UTC 24 |
Aug 29 03:09:00 PM UTC 24 |
148174283 ps |
| T2559 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/70.xbar_random_slow_rsp.813762463 |
|
|
Aug 29 02:55:43 PM UTC 24 |
Aug 29 03:09:04 PM UTC 24 |
44617581514 ps |
| T2560 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/81.xbar_unmapped_addr.2716295935 |
|
|
Aug 29 03:07:58 PM UTC 24 |
Aug 29 03:09:06 PM UTC 24 |
1181972152 ps |
| T2561 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/81.xbar_smoke_large_delays.2042701336 |
|
|
Aug 29 03:07:32 PM UTC 24 |
Aug 29 03:09:07 PM UTC 24 |
7621193811 ps |
| T2562 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/68.xbar_access_same_device_slow_rsp.3398925530 |
|
|
Aug 29 02:53:18 PM UTC 24 |
Aug 29 03:09:10 PM UTC 24 |
59279519266 ps |
| T2563 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/81.xbar_random.391145191 |
|
|
Aug 29 03:07:38 PM UTC 24 |
Aug 29 03:09:11 PM UTC 24 |
2535170542 ps |
| T2564 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/82.xbar_error_random.3503611737 |
|
|
Aug 29 03:08:48 PM UTC 24 |
Aug 29 03:09:11 PM UTC 24 |
290808925 ps |
| T2565 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/82.xbar_error_and_unmapped_addr.3568717483 |
|
|
Aug 29 03:08:57 PM UTC 24 |
Aug 29 03:09:11 PM UTC 24 |
66919579 ps |
| T2566 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/82.xbar_unmapped_addr.3808339914 |
|
|
Aug 29 03:08:55 PM UTC 24 |
Aug 29 03:09:13 PM UTC 24 |
424719557 ps |
| T2567 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/82.xbar_random.1944020454 |
|
|
Aug 29 03:08:37 PM UTC 24 |
Aug 29 03:09:24 PM UTC 24 |
474608610 ps |
| T2568 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/83.xbar_smoke_zero_delays.725757128 |
|
|
Aug 29 03:09:20 PM UTC 24 |
Aug 29 03:09:29 PM UTC 24 |
37973177 ps |
| T2569 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/83.xbar_smoke.977500692 |
|
|
Aug 29 03:09:17 PM UTC 24 |
Aug 29 03:09:30 PM UTC 24 |
196333827 ps |
| T2570 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/82.xbar_smoke_slow_rsp.3966327479 |
|
|
Aug 29 03:08:34 PM UTC 24 |
Aug 29 03:09:49 PM UTC 24 |
5222912179 ps |
| T2571 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/83.xbar_random_zero_delays.3272415394 |
|
|
Aug 29 03:09:28 PM UTC 24 |
Aug 29 03:09:54 PM UTC 24 |
196862857 ps |
| T2572 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/75.xbar_stress_all_with_rand_reset.40686080 |
|
|
Aug 29 03:01:06 PM UTC 24 |
Aug 29 03:09:59 PM UTC 24 |
8419714413 ps |
| T2573 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/80.xbar_stress_all_with_reset_error.3715575031 |
|
|
Aug 29 03:07:22 PM UTC 24 |
Aug 29 03:10:05 PM UTC 24 |
3144419571 ps |
| T2574 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/62.xbar_access_same_device_slow_rsp.3537962256 |
|
|
Aug 29 02:46:10 PM UTC 24 |
Aug 29 03:10:09 PM UTC 24 |
87769341189 ps |
| T2575 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/83.xbar_error_and_unmapped_addr.1540984181 |
|
|
Aug 29 03:09:51 PM UTC 24 |
Aug 29 03:10:17 PM UTC 24 |
408007256 ps |
| T2576 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/69.xbar_random_large_delays.1323148452 |
|
|
Aug 29 02:54:27 PM UTC 24 |
Aug 29 03:10:17 PM UTC 24 |
78432185001 ps |
| T2577 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/82.xbar_stress_all_with_error.2970459769 |
|
|
Aug 29 03:09:16 PM UTC 24 |
Aug 29 03:10:18 PM UTC 24 |
813111715 ps |
| T2578 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/83.xbar_same_source.4128181826 |
|
|
Aug 29 03:09:33 PM UTC 24 |
Aug 29 03:10:23 PM UTC 24 |
1240566185 ps |
| T2579 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/51.xbar_access_same_device_slow_rsp.3562064120 |
|
|
Aug 29 02:33:36 PM UTC 24 |
Aug 29 03:10:33 PM UTC 24 |
123650794002 ps |
| T2580 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/84.xbar_smoke.1717747063 |
|
|
Aug 29 03:10:29 PM UTC 24 |
Aug 29 03:10:39 PM UTC 24 |
44023659 ps |
| T2581 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/83.xbar_unmapped_addr.350290402 |
|
|
Aug 29 03:09:49 PM UTC 24 |
Aug 29 03:10:42 PM UTC 24 |
1020540093 ps |
| T2582 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/84.xbar_smoke_zero_delays.1666153675 |
|
|
Aug 29 03:10:38 PM UTC 24 |
Aug 29 03:10:47 PM UTC 24 |
40273639 ps |
| T2583 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/50.xbar_access_same_device_slow_rsp.3751430627 |
|
|
Aug 29 02:31:39 PM UTC 24 |
Aug 29 03:10:52 PM UTC 24 |
137172246168 ps |
| T2584 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/77.xbar_stress_all_with_reset_error.44113645 |
|
|
Aug 29 03:04:20 PM UTC 24 |
Aug 29 03:10:54 PM UTC 24 |
1836585905 ps |
| T2585 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/82.xbar_smoke_large_delays.501532752 |
|
|
Aug 29 03:08:32 PM UTC 24 |
Aug 29 03:10:56 PM UTC 24 |
9215731038 ps |
| T2586 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/83.xbar_stress_all_with_rand_reset.1670318605 |
|
|
Aug 29 03:10:15 PM UTC 24 |
Aug 29 03:10:57 PM UTC 24 |
22857062 ps |
| T2587 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/58.xbar_access_same_device_slow_rsp.2752817462 |
|
|
Aug 29 02:42:21 PM UTC 24 |
Aug 29 03:11:05 PM UTC 24 |
92313374147 ps |
| T2588 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/83.xbar_access_same_device.3470833784 |
|
|
Aug 29 03:09:31 PM UTC 24 |
Aug 29 03:11:09 PM UTC 24 |
995673758 ps |
| T2589 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/80.xbar_stress_all.4284054170 |
|
|
Aug 29 03:07:18 PM UTC 24 |
Aug 29 03:11:09 PM UTC 24 |
2608967816 ps |
| T2590 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/83.xbar_smoke_large_delays.391902554 |
|
|
Aug 29 03:09:20 PM UTC 24 |
Aug 29 03:11:09 PM UTC 24 |
9730569550 ps |
| T2591 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/76.xbar_random_slow_rsp.2935450485 |
|
|
Aug 29 03:02:04 PM UTC 24 |
Aug 29 03:11:14 PM UTC 24 |
33243423424 ps |
| T2592 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/83.xbar_error_random.2316080405 |
|
|
Aug 29 03:09:45 PM UTC 24 |
Aug 29 03:11:17 PM UTC 24 |
2075702256 ps |
| T2593 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/84.xbar_access_same_device.3931331263 |
|
|
Aug 29 03:11:08 PM UTC 24 |
Aug 29 03:11:19 PM UTC 24 |
74154487 ps |
| T2594 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/83.xbar_smoke_slow_rsp.1943277575 |
|
|
Aug 29 03:09:26 PM UTC 24 |
Aug 29 03:11:21 PM UTC 24 |
5494390916 ps |
| T2595 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/78.xbar_stress_all_with_rand_reset.1304411065 |
|
|
Aug 29 03:05:09 PM UTC 24 |
Aug 29 03:11:28 PM UTC 24 |
8030558188 ps |
| T2596 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/83.xbar_stress_all_with_error.3400223101 |
|
|
Aug 29 03:10:20 PM UTC 24 |
Aug 29 03:11:29 PM UTC 24 |
715741268 ps |
| T2597 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/84.xbar_random_zero_delays.3285721293 |
|
|
Aug 29 03:10:53 PM UTC 24 |
Aug 29 03:11:31 PM UTC 24 |
453518499 ps |
| T2598 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/84.xbar_unmapped_addr.2040294216 |
|
|
Aug 29 03:11:17 PM UTC 24 |
Aug 29 03:11:33 PM UTC 24 |
181622718 ps |
| T2599 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/84.xbar_error_and_unmapped_addr.1841779642 |
|
|
Aug 29 03:11:25 PM UTC 24 |
Aug 29 03:11:36 PM UTC 24 |
140683706 ps |
| T2600 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/74.xbar_stress_all_with_rand_reset.1215980584 |
|
|
Aug 29 03:00:09 PM UTC 24 |
Aug 29 03:11:37 PM UTC 24 |
10986017049 ps |
| T2601 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/84.xbar_error_random.1510723325 |
|
|
Aug 29 03:11:16 PM UTC 24 |
Aug 29 03:11:37 PM UTC 24 |
375033690 ps |
| T2602 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/85.xbar_smoke.2113134729 |
|
|
Aug 29 03:11:34 PM UTC 24 |
Aug 29 03:11:44 PM UTC 24 |
42251725 ps |
| T2603 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/83.xbar_stress_all.1222837968 |
|
|
Aug 29 03:10:11 PM UTC 24 |
Aug 29 03:11:48 PM UTC 24 |
1070587233 ps |
| T2604 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/84.xbar_random.96448706 |
|
|
Aug 29 03:10:42 PM UTC 24 |
Aug 29 03:11:48 PM UTC 24 |
1258223995 ps |
| T2605 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/85.xbar_smoke_zero_delays.2326411321 |
|
|
Aug 29 03:11:38 PM UTC 24 |
Aug 29 03:11:49 PM UTC 24 |
57314282 ps |
| T2606 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/74.xbar_random_slow_rsp.716865549 |
|
|
Aug 29 02:59:39 PM UTC 24 |
Aug 29 03:11:52 PM UTC 24 |
41826628858 ps |
| T2607 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/85.xbar_random_zero_delays.3139824496 |
|
|
Aug 29 03:11:49 PM UTC 24 |
Aug 29 03:12:03 PM UTC 24 |
77182502 ps |
| T2608 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/81.xbar_stress_all_with_error.4193114927 |
|
|
Aug 29 03:08:13 PM UTC 24 |
Aug 29 03:12:03 PM UTC 24 |
6828519972 ps |
| T2609 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/79.xbar_stress_all_with_error.811941420 |
|
|
Aug 29 03:06:35 PM UTC 24 |
Aug 29 03:12:13 PM UTC 24 |
10671043142 ps |
| T2610 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/77.xbar_stress_all.1122870616 |
|
|
Aug 29 03:04:03 PM UTC 24 |
Aug 29 03:12:13 PM UTC 24 |
13281168290 ps |
| T2611 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/84.xbar_smoke_large_delays.1456481335 |
|
|
Aug 29 03:10:38 PM UTC 24 |
Aug 29 03:12:21 PM UTC 24 |
9997491011 ps |
| T2612 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/84.xbar_smoke_slow_rsp.485334307 |
|
|
Aug 29 03:10:37 PM UTC 24 |
Aug 29 03:12:21 PM UTC 24 |
6301958302 ps |
| T2613 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/85.xbar_error_and_unmapped_addr.3739454719 |
|
|
Aug 29 03:12:09 PM UTC 24 |
Aug 29 03:12:21 PM UTC 24 |
46281510 ps |
| T2614 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/85.xbar_error_random.337197887 |
|
|
Aug 29 03:12:05 PM UTC 24 |
Aug 29 03:12:24 PM UTC 24 |
326350088 ps |
| T2615 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/75.xbar_random_large_delays.2534519972 |
|
|
Aug 29 03:00:44 PM UTC 24 |
Aug 29 03:12:24 PM UTC 24 |
55013991338 ps |
| T2616 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/84.xbar_same_source.478944710 |
|
|
Aug 29 03:11:15 PM UTC 24 |
Aug 29 03:12:38 PM UTC 24 |
2161900137 ps |
| T2617 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/86.xbar_smoke_zero_delays.3325215683 |
|
|
Aug 29 03:12:32 PM UTC 24 |
Aug 29 03:12:42 PM UTC 24 |
46381661 ps |
| T2618 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/86.xbar_smoke.1518423707 |
|
|
Aug 29 03:12:33 PM UTC 24 |
Aug 29 03:12:44 PM UTC 24 |
51698552 ps |
| T2619 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/85.xbar_access_same_device.775120780 |
|
|
Aug 29 03:11:56 PM UTC 24 |
Aug 29 03:12:46 PM UTC 24 |
521450225 ps |
| T2620 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/85.xbar_same_source.2814332634 |
|
|
Aug 29 03:11:57 PM UTC 24 |
Aug 29 03:12:49 PM UTC 24 |
1200729555 ps |
| T2621 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/80.xbar_access_same_device_slow_rsp.2377339074 |
|
|
Aug 29 03:07:11 PM UTC 24 |
Aug 29 03:12:55 PM UTC 24 |
21298680375 ps |
| T2622 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/85.xbar_random.2925804620 |
|
|
Aug 29 03:11:49 PM UTC 24 |
Aug 29 03:12:58 PM UTC 24 |
2050738476 ps |
| T2623 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/68.xbar_random_large_delays.1999372496 |
|
|
Aug 29 02:53:01 PM UTC 24 |
Aug 29 03:12:59 PM UTC 24 |
95554284262 ps |
| T2624 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/85.xbar_unmapped_addr.1971546827 |
|
|
Aug 29 03:12:08 PM UTC 24 |
Aug 29 03:13:03 PM UTC 24 |
1313038221 ps |
| T2625 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/78.xbar_stress_all_with_error.1137468474 |
|
|
Aug 29 03:05:13 PM UTC 24 |
Aug 29 03:13:07 PM UTC 24 |
13496959945 ps |
| T2626 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/85.xbar_smoke_slow_rsp.3262548070 |
|
|
Aug 29 03:11:42 PM UTC 24 |
Aug 29 03:13:11 PM UTC 24 |
4461911160 ps |
| T2627 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/79.xbar_random_slow_rsp.1482306324 |
|
|
Aug 29 03:05:51 PM UTC 24 |
Aug 29 03:13:11 PM UTC 24 |
26997092851 ps |
| T2628 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/82.xbar_random_large_delays.2038011419 |
|
|
Aug 29 03:08:38 PM UTC 24 |
Aug 29 03:13:21 PM UTC 24 |
28765587585 ps |
| T2629 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/85.xbar_smoke_large_delays.4204122497 |
|
|
Aug 29 03:11:39 PM UTC 24 |
Aug 29 03:13:22 PM UTC 24 |
6948461390 ps |
| T2630 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/83.xbar_random_large_delays.917587725 |
|
|
Aug 29 03:09:30 PM UTC 24 |
Aug 29 03:13:23 PM UTC 24 |
22765918943 ps |
| T2631 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/86.xbar_random_zero_delays.2270659367 |
|
|
Aug 29 03:12:45 PM UTC 24 |
Aug 29 03:13:25 PM UTC 24 |
302814360 ps |
| T2632 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/87.xbar_smoke.2455320946 |
|
|
Aug 29 03:13:31 PM UTC 24 |
Aug 29 03:13:41 PM UTC 24 |
40471593 ps |
| T2633 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/81.xbar_stress_all_with_rand_reset.2693582231 |
|
|
Aug 29 03:08:01 PM UTC 24 |
Aug 29 03:13:41 PM UTC 24 |
1905300413 ps |
| T2634 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/86.xbar_error_random.3609037520 |
|
|
Aug 29 03:13:09 PM UTC 24 |
Aug 29 03:13:43 PM UTC 24 |
316110881 ps |
| T2635 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/86.xbar_smoke_slow_rsp.938047411 |
|
|
Aug 29 03:12:42 PM UTC 24 |
Aug 29 03:13:47 PM UTC 24 |
3872842436 ps |
| T2636 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/87.xbar_smoke_zero_delays.2266387013 |
|
|
Aug 29 03:13:41 PM UTC 24 |
Aug 29 03:13:49 PM UTC 24 |
47176244 ps |
| T2637 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/86.xbar_access_same_device.3887096642 |
|
|
Aug 29 03:13:02 PM UTC 24 |
Aug 29 03:13:59 PM UTC 24 |
1421313016 ps |
| T2638 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/78.xbar_stress_all.423193764 |
|
|
Aug 29 03:05:03 PM UTC 24 |
Aug 29 03:13:59 PM UTC 24 |
15762195720 ps |
| T2639 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/82.xbar_stress_all.2875217725 |
|
|
Aug 29 03:09:05 PM UTC 24 |
Aug 29 03:14:05 PM UTC 24 |
3826424999 ps |
| T2640 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/86.xbar_unmapped_addr.2301249394 |
|
|
Aug 29 03:13:16 PM UTC 24 |
Aug 29 03:14:08 PM UTC 24 |
329987700 ps |
| T2641 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/81.xbar_stress_all.748672625 |
|
|
Aug 29 03:08:01 PM UTC 24 |
Aug 29 03:14:11 PM UTC 24 |
4586749894 ps |
| T2642 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/86.xbar_same_source.2186941872 |
|
|
Aug 29 03:13:04 PM UTC 24 |
Aug 29 03:14:14 PM UTC 24 |
1643986245 ps |
| T2643 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/86.xbar_random.2649089755 |
|
|
Aug 29 03:12:43 PM UTC 24 |
Aug 29 03:14:14 PM UTC 24 |
2269439606 ps |
| T2644 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/86.xbar_error_and_unmapped_addr.367934759 |
|
|
Aug 29 03:13:19 PM UTC 24 |
Aug 29 03:14:25 PM UTC 24 |
1295615202 ps |
| T2645 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/83.xbar_stress_all_with_reset_error.733216902 |
|
|
Aug 29 03:10:26 PM UTC 24 |
Aug 29 03:14:34 PM UTC 24 |
615233180 ps |
| T2646 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/87.xbar_random_zero_delays.442717691 |
|
|
Aug 29 03:14:02 PM UTC 24 |
Aug 29 03:14:35 PM UTC 24 |
254015901 ps |
| T2647 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/87.xbar_random.2890195019 |
|
|
Aug 29 03:13:47 PM UTC 24 |
Aug 29 03:14:38 PM UTC 24 |
598801471 ps |
| T2648 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/86.xbar_smoke_large_delays.4217467479 |
|
|
Aug 29 03:12:42 PM UTC 24 |
Aug 29 03:14:40 PM UTC 24 |
8601919716 ps |
| T2649 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/87.xbar_error_and_unmapped_addr.2469682898 |
|
|
Aug 29 03:14:29 PM UTC 24 |
Aug 29 03:14:49 PM UTC 24 |
462158373 ps |
| T2650 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/74.xbar_random_large_delays.2565094769 |
|
|
Aug 29 02:59:42 PM UTC 24 |
Aug 29 03:14:52 PM UTC 24 |
85139295194 ps |
| T2651 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/84.xbar_stress_all.761153775 |
|
|
Aug 29 03:11:27 PM UTC 24 |
Aug 29 03:14:58 PM UTC 24 |
2077658048 ps |
| T2652 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/81.xbar_stress_all_with_reset_error.2237722366 |
|
|
Aug 29 03:08:13 PM UTC 24 |
Aug 29 03:14:59 PM UTC 24 |
3891756849 ps |
| T2653 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/88.xbar_smoke_zero_delays.3237914330 |
|
|
Aug 29 03:14:56 PM UTC 24 |
Aug 29 03:15:03 PM UTC 24 |
53776038 ps |
| T2654 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/87.xbar_stress_all_with_reset_error.1808370412 |
|
|
Aug 29 03:14:45 PM UTC 24 |
Aug 29 03:15:05 PM UTC 24 |
112187883 ps |
| T2655 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/87.xbar_error_random.2877038957 |
|
|
Aug 29 03:14:21 PM UTC 24 |
Aug 29 03:15:06 PM UTC 24 |
439783393 ps |
| T2656 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/87.xbar_smoke_slow_rsp.3071592415 |
|
|
Aug 29 03:13:43 PM UTC 24 |
Aug 29 03:15:07 PM UTC 24 |
6154518982 ps |
| T2657 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/88.xbar_smoke.461534653 |
|
|
Aug 29 03:14:54 PM UTC 24 |
Aug 29 03:15:09 PM UTC 24 |
240740563 ps |
| T2658 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/84.xbar_random_large_delays.4099778153 |
|
|
Aug 29 03:10:58 PM UTC 24 |
Aug 29 03:15:10 PM UTC 24 |
23090148722 ps |
| T2659 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/87.xbar_unmapped_addr.4064797388 |
|
|
Aug 29 03:14:26 PM UTC 24 |
Aug 29 03:15:12 PM UTC 24 |
1027247868 ps |
| T2660 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/75.xbar_random_slow_rsp.1384802798 |
|
|
Aug 29 03:00:43 PM UTC 24 |
Aug 29 03:15:16 PM UTC 24 |
51342468141 ps |
| T2661 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/79.xbar_random_large_delays.3574433163 |
|
|
Aug 29 03:05:48 PM UTC 24 |
Aug 29 03:15:16 PM UTC 24 |
54894067318 ps |
| T2662 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/87.xbar_same_source.2641002879 |
|
|
Aug 29 03:14:19 PM UTC 24 |
Aug 29 03:15:17 PM UTC 24 |
1523453128 ps |
| T2663 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/87.xbar_access_same_device.3832829033 |
|
|
Aug 29 03:14:08 PM UTC 24 |
Aug 29 03:15:34 PM UTC 24 |
1677724144 ps |
| T2664 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/88.xbar_random_zero_delays.2903493718 |
|
|
Aug 29 03:15:13 PM UTC 24 |
Aug 29 03:15:41 PM UTC 24 |
297162206 ps |
| T2665 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/85.xbar_stress_all.3104778364 |
|
|
Aug 29 03:12:09 PM UTC 24 |
Aug 29 03:15:42 PM UTC 24 |
4987293719 ps |
| T2666 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/72.xbar_random_slow_rsp.3283307460 |
|
|
Aug 29 02:57:36 PM UTC 24 |
Aug 29 03:15:42 PM UTC 24 |
65365883301 ps |
| T2667 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/87.xbar_random_large_delays.3895891214 |
|
|
Aug 29 03:14:02 PM UTC 24 |
Aug 29 03:15:48 PM UTC 24 |
6331921443 ps |
| T2668 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/87.xbar_smoke_large_delays.75394978 |
|
|
Aug 29 03:13:41 PM UTC 24 |
Aug 29 03:15:48 PM UTC 24 |
9057601851 ps |
| T2669 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/82.xbar_stress_all_with_reset_error.1426496936 |
|
|
Aug 29 03:09:16 PM UTC 24 |
Aug 29 03:15:48 PM UTC 24 |
6737346043 ps |
| T2670 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/79.xbar_stress_all.3830151031 |
|
|
Aug 29 03:06:18 PM UTC 24 |
Aug 29 03:15:52 PM UTC 24 |
13594149016 ps |
| T2671 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/88.xbar_smoke_large_delays.801547431 |
|
|
Aug 29 03:14:59 PM UTC 24 |
Aug 29 03:16:03 PM UTC 24 |
6566191955 ps |
| T2672 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/88.xbar_random_large_delays.2456589657 |
|
|
Aug 29 03:15:18 PM UTC 24 |
Aug 29 03:16:04 PM UTC 24 |
4369701729 ps |
| T2673 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/88.xbar_unmapped_addr.1764227697 |
|
|
Aug 29 03:15:30 PM UTC 24 |
Aug 29 03:16:05 PM UTC 24 |
587513496 ps |
| T2674 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/88.xbar_same_source.4168852707 |
|
|
Aug 29 03:15:25 PM UTC 24 |
Aug 29 03:16:05 PM UTC 24 |
1042204809 ps |
| T2675 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/89.xbar_smoke.1969000136 |
|
|
Aug 29 03:15:53 PM UTC 24 |
Aug 29 03:16:06 PM UTC 24 |
206613850 ps |
| T2676 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/88.xbar_smoke_slow_rsp.2945722619 |
|
|
Aug 29 03:14:59 PM UTC 24 |
Aug 29 03:16:07 PM UTC 24 |
3363927110 ps |
| T2677 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/79.xbar_access_same_device_slow_rsp.28124753 |
|
|
Aug 29 03:05:59 PM UTC 24 |
Aug 29 03:16:09 PM UTC 24 |
37790832192 ps |
| T2678 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/88.xbar_stress_all_with_rand_reset.2313597262 |
|
|
Aug 29 03:15:34 PM UTC 24 |
Aug 29 03:16:10 PM UTC 24 |
41023177 ps |
| T2679 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/89.xbar_smoke_zero_delays.2487884896 |
|
|
Aug 29 03:16:02 PM UTC 24 |
Aug 29 03:16:12 PM UTC 24 |
54046736 ps |
| T2680 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/88.xbar_error_and_unmapped_addr.3959575702 |
|
|
Aug 29 03:15:30 PM UTC 24 |
Aug 29 03:16:17 PM UTC 24 |
1366096992 ps |
| T2681 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/79.xbar_stress_all_with_reset_error.3073623324 |
|
|
Aug 29 03:06:42 PM UTC 24 |
Aug 29 03:16:23 PM UTC 24 |
11725571722 ps |
| T2682 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/88.xbar_stress_all.1047367817 |
|
|
Aug 29 03:15:32 PM UTC 24 |
Aug 29 03:16:24 PM UTC 24 |
1641598565 ps |
| T2683 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/84.xbar_stress_all_with_rand_reset.1018174186 |
|
|
Aug 29 03:11:30 PM UTC 24 |
Aug 29 03:16:27 PM UTC 24 |
1876343125 ps |
| T2684 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/89.xbar_random_zero_delays.3932098073 |
|
|
Aug 29 03:16:08 PM UTC 24 |
Aug 29 03:16:34 PM UTC 24 |
213560389 ps |
| T2685 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/89.xbar_access_same_device.2739333064 |
|
|
Aug 29 03:16:23 PM UTC 24 |
Aug 29 03:16:34 PM UTC 24 |
251705800 ps |
| T2686 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/89.xbar_error_random.10716512 |
|
|
Aug 29 03:16:23 PM UTC 24 |
Aug 29 03:16:34 PM UTC 24 |
125434866 ps |
| T2687 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/84.xbar_stress_all_with_reset_error.3527967207 |
|
|
Aug 29 03:11:30 PM UTC 24 |
Aug 29 03:16:43 PM UTC 24 |
5439553580 ps |
| T2688 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/88.xbar_random.3518149872 |
|
|
Aug 29 03:15:09 PM UTC 24 |
Aug 29 03:16:44 PM UTC 24 |
2116868210 ps |
| T2689 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/88.xbar_error_random.3050256491 |
|
|
Aug 29 03:15:28 PM UTC 24 |
Aug 29 03:16:46 PM UTC 24 |
1833839167 ps |
| T2690 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/88.xbar_stress_all_with_error.3470222886 |
|
|
Aug 29 03:15:36 PM UTC 24 |
Aug 29 03:16:49 PM UTC 24 |
945281151 ps |
| T2691 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/86.xbar_stress_all.2000049446 |
|
|
Aug 29 03:13:20 PM UTC 24 |
Aug 29 03:16:50 PM UTC 24 |
4734310022 ps |
| T2692 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/89.xbar_error_and_unmapped_addr.494434840 |
|
|
Aug 29 03:16:26 PM UTC 24 |
Aug 29 03:16:52 PM UTC 24 |
433918428 ps |
| T2693 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/90.xbar_smoke.2249054880 |
|
|
Aug 29 03:16:43 PM UTC 24 |
Aug 29 03:16:53 PM UTC 24 |
195551798 ps |
| T2694 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/78.xbar_random_slow_rsp.437319666 |
|
|
Aug 29 03:04:49 PM UTC 24 |
Aug 29 03:16:54 PM UTC 24 |
48062023788 ps |
| T2695 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/90.xbar_smoke_zero_delays.1172572606 |
|
|
Aug 29 03:16:44 PM UTC 24 |
Aug 29 03:16:54 PM UTC 24 |
50176419 ps |
| T2696 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/89.xbar_smoke_slow_rsp.2320593937 |
|
|
Aug 29 03:16:04 PM UTC 24 |
Aug 29 03:17:15 PM UTC 24 |
3256694723 ps |
| T2697 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/89.xbar_unmapped_addr.1286349273 |
|
|
Aug 29 03:16:26 PM UTC 24 |
Aug 29 03:17:17 PM UTC 24 |
298903428 ps |
| T2698 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/89.xbar_same_source.1188795674 |
|
|
Aug 29 03:16:25 PM UTC 24 |
Aug 29 03:17:19 PM UTC 24 |
568651951 ps |
| T2699 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/85.xbar_random_slow_rsp.2923496832 |
|
|
Aug 29 03:11:54 PM UTC 24 |
Aug 29 03:17:26 PM UTC 24 |
17304071183 ps |
| T2700 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/90.xbar_random.1463603208 |
|
|
Aug 29 03:16:53 PM UTC 24 |
Aug 29 03:17:29 PM UTC 24 |
381341717 ps |
| T2701 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/89.xbar_smoke_large_delays.3371912806 |
|
|
Aug 29 03:16:03 PM UTC 24 |
Aug 29 03:17:29 PM UTC 24 |
7455163168 ps |
| T2702 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/90.xbar_random_zero_delays.2792698473 |
|
|
Aug 29 03:16:55 PM UTC 24 |
Aug 29 03:17:35 PM UTC 24 |
417955804 ps |
| T2703 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/90.xbar_same_source.2270995316 |
|
|
Aug 29 03:17:09 PM UTC 24 |
Aug 29 03:17:37 PM UTC 24 |
525179354 ps |
| T2704 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/90.xbar_unmapped_addr.794718453 |
|
|
Aug 29 03:17:11 PM UTC 24 |
Aug 29 03:17:42 PM UTC 24 |
527871948 ps |
| T2705 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/86.xbar_stress_all_with_error.2151594266 |
|
|
Aug 29 03:13:27 PM UTC 24 |
Aug 29 03:17:42 PM UTC 24 |
3183763390 ps |
| T2706 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/88.xbar_access_same_device.607834637 |
|
|
Aug 29 03:15:23 PM UTC 24 |
Aug 29 03:17:43 PM UTC 24 |
2727927038 ps |
| T2707 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/89.xbar_random.3923693973 |
|
|
Aug 29 03:16:09 PM UTC 24 |
Aug 29 03:17:44 PM UTC 24 |
1946741171 ps |
| T2708 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/87.xbar_stress_all_with_rand_reset.958702793 |
|
|
Aug 29 03:14:35 PM UTC 24 |
Aug 29 03:17:44 PM UTC 24 |
297585701 ps |
| T2709 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/85.xbar_stress_all_with_error.2091182094 |
|
|
Aug 29 03:12:23 PM UTC 24 |
Aug 29 03:17:50 PM UTC 24 |
8993971449 ps |
| T2710 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/90.xbar_error_random.2456846287 |
|
|
Aug 29 03:17:11 PM UTC 24 |
Aug 29 03:17:53 PM UTC 24 |
943816278 ps |
| T2711 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/91.xbar_smoke_zero_delays.1535022260 |
|
|
Aug 29 03:17:50 PM UTC 24 |
Aug 29 03:17:59 PM UTC 24 |
42333632 ps |
| T2712 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/91.xbar_smoke.1751376960 |
|
|
Aug 29 03:17:47 PM UTC 24 |
Aug 29 03:18:01 PM UTC 24 |
217094158 ps |
| T2713 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/90.xbar_smoke_large_delays.1349832465 |
|
|
Aug 29 03:16:48 PM UTC 24 |
Aug 29 03:18:06 PM UTC 24 |
6400321479 ps |
| T2714 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/90.xbar_access_same_device.2339792699 |
|
|
Aug 29 03:17:07 PM UTC 24 |
Aug 29 03:18:11 PM UTC 24 |
1716791232 ps |
| T2715 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/90.xbar_error_and_unmapped_addr.3440316543 |
|
|
Aug 29 03:17:14 PM UTC 24 |
Aug 29 03:18:20 PM UTC 24 |
1463276876 ps |
| T2716 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/86.xbar_stress_all_with_rand_reset.2199931547 |
|
|
Aug 29 03:13:24 PM UTC 24 |
Aug 29 03:18:28 PM UTC 24 |
2766720890 ps |
| T2717 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/91.xbar_error_and_unmapped_addr.2405264879 |
|
|
Aug 29 03:18:23 PM UTC 24 |
Aug 29 03:18:31 PM UTC 24 |
75094949 ps |
| T2718 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/89.xbar_stress_all_with_reset_error.610255733 |
|
|
Aug 29 03:16:36 PM UTC 24 |
Aug 29 03:18:33 PM UTC 24 |
351150899 ps |
| T2719 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/91.xbar_random.1608004911 |
|
|
Aug 29 03:17:57 PM UTC 24 |
Aug 29 03:18:33 PM UTC 24 |
317364293 ps |
| T2720 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/91.xbar_random_zero_delays.2589114439 |
|
|
Aug 29 03:18:03 PM UTC 24 |
Aug 29 03:18:34 PM UTC 24 |
234532139 ps |
| T2721 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/91.xbar_error_random.344441723 |
|
|
Aug 29 03:18:14 PM UTC 24 |
Aug 29 03:18:46 PM UTC 24 |
260588947 ps |
| T2722 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/91.xbar_same_source.1528687473 |
|
|
Aug 29 03:18:11 PM UTC 24 |
Aug 29 03:18:46 PM UTC 24 |
780993432 ps |
| T2723 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/91.xbar_unmapped_addr.3632573036 |
|
|
Aug 29 03:18:20 PM UTC 24 |
Aug 29 03:18:49 PM UTC 24 |
154734064 ps |
| T2724 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/90.xbar_smoke_slow_rsp.369922026 |
|
|
Aug 29 03:16:51 PM UTC 24 |
Aug 29 03:18:51 PM UTC 24 |
6790157151 ps |
| T2725 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/92.xbar_smoke.2715011640 |
|
|
Aug 29 03:18:52 PM UTC 24 |
Aug 29 03:19:01 PM UTC 24 |
35640059 ps |
| T2726 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/92.xbar_smoke_zero_delays.3691060570 |
|
|
Aug 29 03:18:54 PM UTC 24 |
Aug 29 03:19:05 PM UTC 24 |
49706220 ps |
| T2727 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/86.xbar_stress_all_with_reset_error.1939157342 |
|
|
Aug 29 03:13:31 PM UTC 24 |
Aug 29 03:19:19 PM UTC 24 |
2863954692 ps |
| T2728 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/80.xbar_random_large_delays.3031286590 |
|
|
Aug 29 03:06:57 PM UTC 24 |
Aug 29 03:19:20 PM UTC 24 |
58605862097 ps |
| T2729 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/85.xbar_stress_all_with_rand_reset.2741463090 |
|
|
Aug 29 03:12:12 PM UTC 24 |
Aug 29 03:19:21 PM UTC 24 |
2808003422 ps |
| T2730 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/54.xbar_access_same_device_slow_rsp.3135636289 |
|
|
Aug 29 02:37:39 PM UTC 24 |
Aug 29 03:19:27 PM UTC 24 |
137284325332 ps |
| T2731 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/91.xbar_stress_all_with_error.194416937 |
|
|
Aug 29 03:18:40 PM UTC 24 |
Aug 29 03:19:29 PM UTC 24 |
632099071 ps |
| T2732 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/91.xbar_smoke_large_delays.3016439386 |
|
|
Aug 29 03:17:50 PM UTC 24 |
Aug 29 03:19:35 PM UTC 24 |
8824501531 ps |
| T2733 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/92.xbar_random_zero_delays.400107274 |
|
|
Aug 29 03:19:08 PM UTC 24 |
Aug 29 03:19:39 PM UTC 24 |
249436477 ps |
| T2734 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/91.xbar_access_same_device.3250596624 |
|
|
Aug 29 03:18:05 PM UTC 24 |
Aug 29 03:19:48 PM UTC 24 |
2317763787 ps |
| T2735 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/76.xbar_random_large_delays.3164537794 |
|
|
Aug 29 03:01:58 PM UTC 24 |
Aug 29 03:20:00 PM UTC 24 |
101658809767 ps |
| T2736 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/92.xbar_error_and_unmapped_addr.378069206 |
|
|
Aug 29 03:19:48 PM UTC 24 |
Aug 29 03:20:03 PM UTC 24 |
126550142 ps |
| T2737 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/92.xbar_same_source.2253665361 |
|
|
Aug 29 03:19:40 PM UTC 24 |
Aug 29 03:20:04 PM UTC 24 |
195703616 ps |
| T2738 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/92.xbar_access_same_device.2781930699 |
|
|
Aug 29 03:19:22 PM UTC 24 |
Aug 29 03:20:07 PM UTC 24 |
458288541 ps |
| T2739 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/90.xbar_access_same_device_slow_rsp.3596329314 |
|
|
Aug 29 03:17:07 PM UTC 24 |
Aug 29 03:20:07 PM UTC 24 |
11380469973 ps |
| T2740 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/92.xbar_error_random.235760660 |
|
|
Aug 29 03:19:42 PM UTC 24 |
Aug 29 03:20:16 PM UTC 24 |
308961767 ps |
| T2741 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/85.xbar_stress_all_with_reset_error.4188931485 |
|
|
Aug 29 03:12:24 PM UTC 24 |
Aug 29 03:20:22 PM UTC 24 |
10974710040 ps |
| T2742 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/92.xbar_random.3803876355 |
|
|
Aug 29 03:19:06 PM UTC 24 |
Aug 29 03:20:22 PM UTC 24 |
2237457122 ps |
| T2743 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/92.xbar_smoke_slow_rsp.1677039045 |
|
|
Aug 29 03:18:55 PM UTC 24 |
Aug 29 03:20:26 PM UTC 24 |
4465840885 ps |
| T2744 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/92.xbar_unmapped_addr.501761997 |
|
|
Aug 29 03:19:42 PM UTC 24 |
Aug 29 03:20:30 PM UTC 24 |
1015287274 ps |
| T2745 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/91.xbar_smoke_slow_rsp.550590163 |
|
|
Aug 29 03:17:55 PM UTC 24 |
Aug 29 03:20:30 PM UTC 24 |
6377769695 ps |
| T2746 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/92.xbar_smoke_large_delays.2281287330 |
|
|
Aug 29 03:18:54 PM UTC 24 |
Aug 29 03:20:31 PM UTC 24 |
5595305014 ps |
| T2747 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/93.xbar_smoke_zero_delays.2313736370 |
|
|
Aug 29 03:20:23 PM UTC 24 |
Aug 29 03:20:31 PM UTC 24 |
47358506 ps |
| T2748 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/91.xbar_stress_all_with_rand_reset.2212341776 |
|
|
Aug 29 03:18:31 PM UTC 24 |
Aug 29 03:20:32 PM UTC 24 |
269865192 ps |
| T2749 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/90.xbar_stress_all_with_error.1876431277 |
|
|
Aug 29 03:17:38 PM UTC 24 |
Aug 29 03:20:33 PM UTC 24 |
4767710942 ps |
| T2750 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/71.xbar_access_same_device_slow_rsp.925010773 |
|
|
Aug 29 02:56:38 PM UTC 24 |
Aug 29 03:20:39 PM UTC 24 |
88219769229 ps |
| T2751 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/87.xbar_stress_all.2149194669 |
|
|
Aug 29 03:14:31 PM UTC 24 |
Aug 29 03:20:39 PM UTC 24 |
11310235697 ps |
| T2752 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/93.xbar_random.2120581640 |
|
|
Aug 29 03:20:27 PM UTC 24 |
Aug 29 03:20:46 PM UTC 24 |
131979702 ps |
| T2753 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/84.xbar_stress_all_with_error.128463029 |
|
|
Aug 29 03:11:28 PM UTC 24 |
Aug 29 03:21:01 PM UTC 24 |
15804764785 ps |
| T2754 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/89.xbar_stress_all.1749081217 |
|
|
Aug 29 03:16:29 PM UTC 24 |
Aug 29 03:21:05 PM UTC 24 |
2647171581 ps |
| T2755 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/93.xbar_error_random.853558291 |
|
|
Aug 29 03:20:50 PM UTC 24 |
Aug 29 03:21:07 PM UTC 24 |
266714055 ps |
| T2756 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/93.xbar_stress_all_with_rand_reset.1040146470 |
|
|
Aug 29 03:20:52 PM UTC 24 |
Aug 29 03:21:18 PM UTC 24 |
90370307 ps |
| T2757 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/93.xbar_same_source.892280037 |
|
|
Aug 29 03:20:49 PM UTC 24 |
Aug 29 03:21:18 PM UTC 24 |
968458016 ps |
| T2758 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/90.xbar_random_slow_rsp.4037020175 |
|
|
Aug 29 03:17:01 PM UTC 24 |
Aug 29 03:21:21 PM UTC 24 |
15997101513 ps |
| T2759 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/93.xbar_random_zero_delays.3684629018 |
|
|
Aug 29 03:20:35 PM UTC 24 |
Aug 29 03:21:21 PM UTC 24 |
461080205 ps |
| T2760 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/94.xbar_smoke.2247922382 |
|
|
Aug 29 03:21:07 PM UTC 24 |
Aug 29 03:21:21 PM UTC 24 |
194009117 ps |