| T2264 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/66.xbar_smoke_zero_delays.2665492675 |
|
|
Aug 29 02:50:45 PM UTC 24 |
Aug 29 02:50:55 PM UTC 24 |
44485273 ps |
| T2265 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/63.xbar_stress_all.1671802840 |
|
|
Aug 29 02:47:59 PM UTC 24 |
Aug 29 02:50:56 PM UTC 24 |
4358843929 ps |
| T2266 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/60.xbar_stress_all_with_error.2228674609 |
|
|
Aug 29 02:44:25 PM UTC 24 |
Aug 29 02:51:00 PM UTC 24 |
10185225661 ps |
| T2267 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/66.xbar_random.2135338805 |
|
|
Aug 29 02:50:51 PM UTC 24 |
Aug 29 02:51:07 PM UTC 24 |
92771274 ps |
| T2268 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/65.xbar_error_and_unmapped_addr.223836850 |
|
|
Aug 29 02:50:18 PM UTC 24 |
Aug 29 02:51:15 PM UTC 24 |
1245960617 ps |
| T2269 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/66.xbar_random_zero_delays.3282358394 |
|
|
Aug 29 02:50:54 PM UTC 24 |
Aug 29 02:51:20 PM UTC 24 |
210379361 ps |
| T2270 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/65.xbar_access_same_device.2727128597 |
|
|
Aug 29 02:50:00 PM UTC 24 |
Aug 29 02:51:20 PM UTC 24 |
801719613 ps |
| T2271 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/18.chip_same_csr_outstanding.1911149831 |
|
|
Aug 29 01:39:03 PM UTC 24 |
Aug 29 02:51:21 PM UTC 24 |
30602090927 ps |
| T2272 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/63.xbar_stress_all_with_rand_reset.2500009936 |
|
|
Aug 29 02:48:00 PM UTC 24 |
Aug 29 02:51:34 PM UTC 24 |
1172077923 ps |
| T2273 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/66.xbar_same_source.3605192912 |
|
|
Aug 29 02:51:13 PM UTC 24 |
Aug 29 02:51:39 PM UTC 24 |
528597248 ps |
| T2274 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/65.xbar_stress_all_with_error.415282271 |
|
|
Aug 29 02:50:24 PM UTC 24 |
Aug 29 02:51:46 PM UTC 24 |
1237785574 ps |
| T2275 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/65.xbar_same_source.2230751806 |
|
|
Aug 29 02:50:04 PM UTC 24 |
Aug 29 02:51:47 PM UTC 24 |
2558441058 ps |
| T2276 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/66.xbar_unmapped_addr.4275217080 |
|
|
Aug 29 02:51:17 PM UTC 24 |
Aug 29 02:51:48 PM UTC 24 |
709261058 ps |
| T2277 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/41.xbar_access_same_device_slow_rsp.817103563 |
|
|
Aug 29 02:18:53 PM UTC 24 |
Aug 29 02:51:48 PM UTC 24 |
128404999976 ps |
| T2278 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/67.xbar_smoke.3330696843 |
|
|
Aug 29 02:51:41 PM UTC 24 |
Aug 29 02:51:49 PM UTC 24 |
43646375 ps |
| T872 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/52.xbar_stress_all_with_rand_reset.3984777417 |
|
|
Aug 29 02:35:40 PM UTC 24 |
Aug 29 02:51:50 PM UTC 24 |
12493995695 ps |
| T2279 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/66.xbar_error_and_unmapped_addr.3668519197 |
|
|
Aug 29 02:51:17 PM UTC 24 |
Aug 29 02:51:52 PM UTC 24 |
245015559 ps |
| T2280 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/67.xbar_smoke_zero_delays.4048420939 |
|
|
Aug 29 02:51:41 PM UTC 24 |
Aug 29 02:51:52 PM UTC 24 |
56268201 ps |
| T2281 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/83.xbar_random.2192488063 |
|
|
Aug 29 03:09:25 PM UTC 24 |
Aug 29 03:11:06 PM UTC 24 |
2374344879 ps |
| T2282 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/65.xbar_stress_all_with_rand_reset.2159389392 |
|
|
Aug 29 02:50:24 PM UTC 24 |
Aug 29 02:51:55 PM UTC 24 |
151058926 ps |
| T2283 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/62.xbar_stress_all_with_error.228823998 |
|
|
Aug 29 02:46:46 PM UTC 24 |
Aug 29 02:51:56 PM UTC 24 |
8208334130 ps |
| T2284 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/56.xbar_random_large_delays.3763199411 |
|
|
Aug 29 02:39:54 PM UTC 24 |
Aug 29 02:51:59 PM UTC 24 |
63645743732 ps |
| T2285 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/65.xbar_smoke_large_delays.1846091667 |
|
|
Aug 29 02:49:46 PM UTC 24 |
Aug 29 02:52:02 PM UTC 24 |
10275394579 ps |
| T2286 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/65.xbar_smoke_slow_rsp.1760570933 |
|
|
Aug 29 02:49:50 PM UTC 24 |
Aug 29 02:52:04 PM UTC 24 |
5613936013 ps |
| T2287 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/66.xbar_smoke_large_delays.720593888 |
|
|
Aug 29 02:50:49 PM UTC 24 |
Aug 29 02:52:09 PM UTC 24 |
8652461131 ps |
| T2288 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/61.xbar_stress_all_with_rand_reset.861662427 |
|
|
Aug 29 02:45:24 PM UTC 24 |
Aug 29 02:52:11 PM UTC 24 |
1805477724 ps |
| T2289 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/66.xbar_smoke_slow_rsp.302714810 |
|
|
Aug 29 02:50:51 PM UTC 24 |
Aug 29 02:52:21 PM UTC 24 |
5235719827 ps |
| T2290 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/66.xbar_access_same_device.976779213 |
|
|
Aug 29 02:51:08 PM UTC 24 |
Aug 29 02:52:24 PM UTC 24 |
1016115766 ps |
| T2291 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/67.xbar_error_random.1523708508 |
|
|
Aug 29 02:52:13 PM UTC 24 |
Aug 29 02:52:27 PM UTC 24 |
93362353 ps |
| T2292 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/67.xbar_unmapped_addr.2167442859 |
|
|
Aug 29 02:52:16 PM UTC 24 |
Aug 29 02:52:36 PM UTC 24 |
310412966 ps |
| T2293 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/67.xbar_same_source.1682540155 |
|
|
Aug 29 02:52:12 PM UTC 24 |
Aug 29 02:52:36 PM UTC 24 |
542750908 ps |
| T2294 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/68.xbar_smoke.1908610832 |
|
|
Aug 29 02:52:33 PM UTC 24 |
Aug 29 02:52:40 PM UTC 24 |
43029719 ps |
| T2295 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/66.xbar_error_random.1271939905 |
|
|
Aug 29 02:51:11 PM UTC 24 |
Aug 29 02:52:45 PM UTC 24 |
2050952794 ps |
| T2296 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/68.xbar_smoke_zero_delays.1774053161 |
|
|
Aug 29 02:52:42 PM UTC 24 |
Aug 29 02:52:51 PM UTC 24 |
46286791 ps |
| T2297 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/67.xbar_random_zero_delays.2916108057 |
|
|
Aug 29 02:52:07 PM UTC 24 |
Aug 29 02:52:58 PM UTC 24 |
477710825 ps |
| T2298 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/67.xbar_error_and_unmapped_addr.2599578420 |
|
|
Aug 29 02:52:17 PM UTC 24 |
Aug 29 02:53:05 PM UTC 24 |
885670972 ps |
| T2299 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/58.xbar_random_slow_rsp.2481903174 |
|
|
Aug 29 02:42:16 PM UTC 24 |
Aug 29 02:53:07 PM UTC 24 |
46806969094 ps |
| T2300 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/68.xbar_random.3247305642 |
|
|
Aug 29 02:52:57 PM UTC 24 |
Aug 29 02:53:09 PM UTC 24 |
60914576 ps |
| T2301 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/1.chip_csr_aliasing.476833129 |
|
|
Aug 29 01:00:31 PM UTC 24 |
Aug 29 02:53:19 PM UTC 24 |
34838150747 ps |
| T2302 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/67.xbar_random.2350984489 |
|
|
Aug 29 02:52:04 PM UTC 24 |
Aug 29 02:53:20 PM UTC 24 |
2364529076 ps |
| T2303 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/56.xbar_access_same_device_slow_rsp.1209135429 |
|
|
Aug 29 02:40:15 PM UTC 24 |
Aug 29 02:53:26 PM UTC 24 |
53096435674 ps |
| T2304 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/67.xbar_smoke_large_delays.2185231863 |
|
|
Aug 29 02:51:54 PM UTC 24 |
Aug 29 02:53:27 PM UTC 24 |
6909829243 ps |
| T2305 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/68.xbar_random_zero_delays.1195641797 |
|
|
Aug 29 02:52:57 PM UTC 24 |
Aug 29 02:53:29 PM UTC 24 |
273057101 ps |
| T2306 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/65.xbar_stress_all_with_reset_error.3058393687 |
|
|
Aug 29 02:50:31 PM UTC 24 |
Aug 29 02:53:39 PM UTC 24 |
384254946 ps |
| T2307 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/64.xbar_stress_all.752104084 |
|
|
Aug 29 02:49:04 PM UTC 24 |
Aug 29 02:53:45 PM UTC 24 |
3058548331 ps |
| T2308 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/59.xbar_access_same_device_slow_rsp.1228025394 |
|
|
Aug 29 02:43:13 PM UTC 24 |
Aug 29 02:53:46 PM UTC 24 |
35861978693 ps |
| T2309 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/68.xbar_error_and_unmapped_addr.2225152102 |
|
|
Aug 29 02:53:40 PM UTC 24 |
Aug 29 02:53:50 PM UTC 24 |
87060388 ps |
| T2310 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/68.xbar_same_source.3659136399 |
|
|
Aug 29 02:53:26 PM UTC 24 |
Aug 29 02:53:52 PM UTC 24 |
229925561 ps |
| T2311 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/68.xbar_unmapped_addr.735521729 |
|
|
Aug 29 02:53:30 PM UTC 24 |
Aug 29 02:53:52 PM UTC 24 |
109600912 ps |
| T2312 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/69.xbar_smoke.2224763436 |
|
|
Aug 29 02:53:59 PM UTC 24 |
Aug 29 02:54:06 PM UTC 24 |
51921515 ps |
| T2313 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/53.xbar_random_large_delays.4236999632 |
|
|
Aug 29 02:36:12 PM UTC 24 |
Aug 29 02:54:08 PM UTC 24 |
85322820877 ps |
| T2314 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/69.xbar_smoke_zero_delays.4036766254 |
|
|
Aug 29 02:54:06 PM UTC 24 |
Aug 29 02:54:13 PM UTC 24 |
41727045 ps |
| T2315 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/68.xbar_error_random.3789270618 |
|
|
Aug 29 02:53:28 PM UTC 24 |
Aug 29 02:54:14 PM UTC 24 |
1106559875 ps |
| T2316 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/67.xbar_smoke_slow_rsp.1477028307 |
|
|
Aug 29 02:51:59 PM UTC 24 |
Aug 29 02:54:15 PM UTC 24 |
5588503944 ps |
| T2317 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/68.xbar_smoke_large_delays.3360686578 |
|
|
Aug 29 02:52:45 PM UTC 24 |
Aug 29 02:54:17 PM UTC 24 |
9051818903 ps |
| T2318 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/63.xbar_stress_all_with_error.2702604348 |
|
|
Aug 29 02:48:02 PM UTC 24 |
Aug 29 02:54:19 PM UTC 24 |
11134632322 ps |
| T2319 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/68.xbar_access_same_device.2856349202 |
|
|
Aug 29 02:53:13 PM UTC 24 |
Aug 29 02:54:25 PM UTC 24 |
1239043540 ps |
| T2320 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/66.xbar_stress_all.754599189 |
|
|
Aug 29 02:51:19 PM UTC 24 |
Aug 29 02:54:28 PM UTC 24 |
5443215004 ps |
| T2321 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/68.xbar_smoke_slow_rsp.1856849459 |
|
|
Aug 29 02:52:48 PM UTC 24 |
Aug 29 02:54:29 PM UTC 24 |
5228657410 ps |
| T2322 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/69.xbar_random_zero_delays.78052179 |
|
|
Aug 29 02:54:10 PM UTC 24 |
Aug 29 02:54:38 PM UTC 24 |
226309084 ps |
| T2323 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/67.xbar_access_same_device.2679549449 |
|
|
Aug 29 02:52:10 PM UTC 24 |
Aug 29 02:54:39 PM UTC 24 |
3025483011 ps |
| T2324 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/69.xbar_same_source.1453631894 |
|
|
Aug 29 02:54:33 PM UTC 24 |
Aug 29 02:55:00 PM UTC 24 |
227499542 ps |
| T2325 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/32.xbar_access_same_device_slow_rsp.3461272806 |
|
|
Aug 29 02:04:20 PM UTC 24 |
Aug 29 02:55:03 PM UTC 24 |
155037032750 ps |
| T2326 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/69.xbar_unmapped_addr.270606718 |
|
|
Aug 29 02:54:38 PM UTC 24 |
Aug 29 02:55:13 PM UTC 24 |
198945776 ps |
| T2327 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/63.xbar_stress_all_with_reset_error.473752147 |
|
|
Aug 29 02:48:03 PM UTC 24 |
Aug 29 02:55:13 PM UTC 24 |
3549011071 ps |
| T2328 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/69.xbar_smoke_slow_rsp.21015189 |
|
|
Aug 29 02:54:11 PM UTC 24 |
Aug 29 02:55:16 PM UTC 24 |
4289708977 ps |
| T2329 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/69.xbar_error_random.1673651152 |
|
|
Aug 29 02:54:36 PM UTC 24 |
Aug 29 02:55:16 PM UTC 24 |
952743893 ps |
| T2330 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/43.xbar_access_same_device_slow_rsp.1531262194 |
|
|
Aug 29 02:21:51 PM UTC 24 |
Aug 29 02:55:23 PM UTC 24 |
117334431566 ps |
| T2331 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/64.xbar_access_same_device_slow_rsp.3881744907 |
|
|
Aug 29 02:48:44 PM UTC 24 |
Aug 29 02:55:23 PM UTC 24 |
23433448287 ps |
| T2332 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/70.xbar_smoke.4142502686 |
|
|
Aug 29 02:55:20 PM UTC 24 |
Aug 29 02:55:27 PM UTC 24 |
40371353 ps |
| T2333 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/66.xbar_stress_all_with_error.79185647 |
|
|
Aug 29 02:51:36 PM UTC 24 |
Aug 29 02:55:29 PM UTC 24 |
3292019377 ps |
| T2334 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/69.xbar_smoke_large_delays.189104515 |
|
|
Aug 29 02:54:04 PM UTC 24 |
Aug 29 02:55:30 PM UTC 24 |
7695984015 ps |
| T2335 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/69.xbar_error_and_unmapped_addr.338190287 |
|
|
Aug 29 02:54:46 PM UTC 24 |
Aug 29 02:55:32 PM UTC 24 |
329868522 ps |
| T2336 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/70.xbar_smoke_zero_delays.4121760887 |
|
|
Aug 29 02:55:25 PM UTC 24 |
Aug 29 02:55:35 PM UTC 24 |
54480532 ps |
| T2337 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/65.xbar_stress_all.1822931808 |
|
|
Aug 29 02:50:18 PM UTC 24 |
Aug 29 02:55:36 PM UTC 24 |
2624535461 ps |
| T2338 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/57.xbar_access_same_device_slow_rsp.943827359 |
|
|
Aug 29 02:41:17 PM UTC 24 |
Aug 29 02:55:45 PM UTC 24 |
55682963352 ps |
| T2339 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/69.xbar_stress_all.1565652327 |
|
|
Aug 29 02:54:48 PM UTC 24 |
Aug 29 02:55:52 PM UTC 24 |
526175892 ps |
| T2340 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/58.xbar_random_large_delays.402737307 |
|
|
Aug 29 02:42:13 PM UTC 24 |
Aug 29 02:55:52 PM UTC 24 |
78124093457 ps |
| T2341 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/69.xbar_random.4151804251 |
|
|
Aug 29 02:54:11 PM UTC 24 |
Aug 29 02:56:01 PM UTC 24 |
2316217452 ps |
| T2342 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/59.xbar_stress_all_with_reset_error.2943101442 |
|
|
Aug 29 02:43:32 PM UTC 24 |
Aug 29 02:56:03 PM UTC 24 |
7090775964 ps |
| T2343 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/70.xbar_random.2598724453 |
|
|
Aug 29 02:55:37 PM UTC 24 |
Aug 29 02:56:04 PM UTC 24 |
261413394 ps |
| T2344 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/68.xbar_stress_all_with_error.1525147243 |
|
|
Aug 29 02:53:46 PM UTC 24 |
Aug 29 02:56:05 PM UTC 24 |
1562392481 ps |
| T2345 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/62.xbar_stress_all_with_rand_reset.4258432069 |
|
|
Aug 29 02:46:42 PM UTC 24 |
Aug 29 02:56:06 PM UTC 24 |
3458037534 ps |
| T2346 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/70.xbar_error_and_unmapped_addr.1965322771 |
|
|
Aug 29 02:55:56 PM UTC 24 |
Aug 29 02:56:06 PM UTC 24 |
36330035 ps |
| T2347 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/70.xbar_same_source.903886045 |
|
|
Aug 29 02:55:51 PM UTC 24 |
Aug 29 02:56:08 PM UTC 24 |
530114448 ps |
| T2348 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/70.xbar_random_zero_delays.3673351134 |
|
|
Aug 29 02:55:35 PM UTC 24 |
Aug 29 02:56:11 PM UTC 24 |
320788601 ps |
| T2349 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/69.xbar_stress_all_with_reset_error.2064423596 |
|
|
Aug 29 02:55:00 PM UTC 24 |
Aug 29 02:56:14 PM UTC 24 |
151361215 ps |
| T2350 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/64.xbar_random_slow_rsp.2633855325 |
|
|
Aug 29 02:48:40 PM UTC 24 |
Aug 29 02:56:15 PM UTC 24 |
23129727129 ps |
| T2351 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/57.xbar_random_large_delays.946271321 |
|
|
Aug 29 02:41:10 PM UTC 24 |
Aug 29 02:56:18 PM UTC 24 |
84526269842 ps |
| T2352 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/69.xbar_random_slow_rsp.1695426779 |
|
|
Aug 29 02:54:26 PM UTC 24 |
Aug 29 02:56:19 PM UTC 24 |
5079546316 ps |
| T2353 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/68.xbar_random_slow_rsp.819501372 |
|
|
Aug 29 02:53:06 PM UTC 24 |
Aug 29 02:56:25 PM UTC 24 |
11694857015 ps |
| T2354 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/69.xbar_access_same_device.392615917 |
|
|
Aug 29 02:54:33 PM UTC 24 |
Aug 29 02:56:25 PM UTC 24 |
2189087007 ps |
| T2355 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/70.xbar_access_same_device.2098249909 |
|
|
Aug 29 02:55:49 PM UTC 24 |
Aug 29 02:56:27 PM UTC 24 |
606697202 ps |
| T2356 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/71.xbar_smoke.3708517133 |
|
|
Aug 29 02:56:24 PM UTC 24 |
Aug 29 02:56:33 PM UTC 24 |
50144646 ps |
| T2357 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/70.xbar_unmapped_addr.2183666960 |
|
|
Aug 29 02:55:56 PM UTC 24 |
Aug 29 02:56:33 PM UTC 24 |
638672265 ps |
| T2358 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/71.xbar_smoke_zero_delays.2496656286 |
|
|
Aug 29 02:56:25 PM UTC 24 |
Aug 29 02:56:36 PM UTC 24 |
48345353 ps |
| T2359 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/79.xbar_error_random.2418156913 |
|
|
Aug 29 03:06:06 PM UTC 24 |
Aug 29 03:06:50 PM UTC 24 |
404960562 ps |
| T2360 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/68.xbar_stress_all_with_rand_reset.2697327170 |
|
|
Aug 29 02:53:47 PM UTC 24 |
Aug 29 02:56:38 PM UTC 24 |
256035085 ps |
| T2361 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/71.xbar_random_zero_delays.1940556735 |
|
|
Aug 29 02:56:28 PM UTC 24 |
Aug 29 02:56:48 PM UTC 24 |
190061350 ps |
| T2362 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/69.xbar_stress_all_with_rand_reset.3303487472 |
|
|
Aug 29 02:54:50 PM UTC 24 |
Aug 29 02:56:54 PM UTC 24 |
207769638 ps |
| T2363 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/70.xbar_smoke_slow_rsp.320622335 |
|
|
Aug 29 02:55:35 PM UTC 24 |
Aug 29 02:56:56 PM UTC 24 |
4446322084 ps |
| T2364 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/70.xbar_stress_all_with_rand_reset.1115620668 |
|
|
Aug 29 02:56:12 PM UTC 24 |
Aug 29 02:57:00 PM UTC 24 |
137572514 ps |
| T2365 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/71.xbar_error_and_unmapped_addr.2518075123 |
|
|
Aug 29 02:56:48 PM UTC 24 |
Aug 29 02:57:03 PM UTC 24 |
191402896 ps |
| T2366 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/71.xbar_same_source.3562959924 |
|
|
Aug 29 02:56:40 PM UTC 24 |
Aug 29 02:57:08 PM UTC 24 |
351501032 ps |
| T2367 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/70.xbar_stress_all_with_error.3425950375 |
|
|
Aug 29 02:56:14 PM UTC 24 |
Aug 29 02:57:09 PM UTC 24 |
767780805 ps |
| T2368 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/71.xbar_random.617511350 |
|
|
Aug 29 02:56:26 PM UTC 24 |
Aug 29 02:57:16 PM UTC 24 |
554032700 ps |
| T2369 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/72.xbar_smoke.3224509046 |
|
|
Aug 29 02:57:06 PM UTC 24 |
Aug 29 02:57:16 PM UTC 24 |
47063257 ps |
| T2370 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/70.xbar_error_random.678678956 |
|
|
Aug 29 02:55:52 PM UTC 24 |
Aug 29 02:57:23 PM UTC 24 |
2365454062 ps |
| T2371 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/72.xbar_smoke_zero_delays.3589135720 |
|
|
Aug 29 02:57:14 PM UTC 24 |
Aug 29 02:57:24 PM UTC 24 |
47261008 ps |
| T2372 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/67.xbar_stress_all.3308788129 |
|
|
Aug 29 02:52:21 PM UTC 24 |
Aug 29 02:57:25 PM UTC 24 |
8050544370 ps |
| T2373 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/71.xbar_unmapped_addr.1779535891 |
|
|
Aug 29 02:56:46 PM UTC 24 |
Aug 29 02:57:26 PM UTC 24 |
289002605 ps |
| T2374 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/71.xbar_stress_all_with_reset_error.3128458034 |
|
|
Aug 29 02:56:57 PM UTC 24 |
Aug 29 02:57:37 PM UTC 24 |
64908317 ps |
| T2375 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/61.xbar_access_same_device_slow_rsp.3083065058 |
|
|
Aug 29 02:45:05 PM UTC 24 |
Aug 29 02:57:50 PM UTC 24 |
43196634663 ps |
| T2376 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/72.xbar_random_zero_delays.3239235793 |
|
|
Aug 29 02:57:26 PM UTC 24 |
Aug 29 02:57:54 PM UTC 24 |
223714577 ps |
| T2377 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/51.xbar_random_large_delays.2025268614 |
|
|
Aug 29 02:33:29 PM UTC 24 |
Aug 29 02:57:56 PM UTC 24 |
113606485379 ps |
| T2378 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/72.xbar_random.1951940769 |
|
|
Aug 29 02:57:23 PM UTC 24 |
Aug 29 02:58:00 PM UTC 24 |
1241423463 ps |
| T2379 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/70.xbar_smoke_large_delays.3580452160 |
|
|
Aug 29 02:55:33 PM UTC 24 |
Aug 29 02:58:03 PM UTC 24 |
8931425562 ps |
| T2380 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/72.xbar_same_source.127502570 |
|
|
Aug 29 02:57:45 PM UTC 24 |
Aug 29 02:58:06 PM UTC 24 |
164177695 ps |
| T2381 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/63.xbar_random_large_delays.4052178396 |
|
|
Aug 29 02:47:22 PM UTC 24 |
Aug 29 02:58:07 PM UTC 24 |
51153623711 ps |
| T2382 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/71.xbar_error_random.33433680 |
|
|
Aug 29 02:56:46 PM UTC 24 |
Aug 29 02:58:09 PM UTC 24 |
2019130669 ps |
| T2383 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/72.xbar_error_and_unmapped_addr.1234728611 |
|
|
Aug 29 02:57:57 PM UTC 24 |
Aug 29 02:58:18 PM UTC 24 |
125855951 ps |
| T2384 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/71.xbar_smoke_slow_rsp.3900044497 |
|
|
Aug 29 02:56:26 PM UTC 24 |
Aug 29 02:58:19 PM UTC 24 |
4709738019 ps |
| T2385 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/71.xbar_access_same_device.1465207145 |
|
|
Aug 29 02:56:35 PM UTC 24 |
Aug 29 02:58:21 PM UTC 24 |
1915980928 ps |
| T2386 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/71.xbar_smoke_large_delays.3103149654 |
|
|
Aug 29 02:56:25 PM UTC 24 |
Aug 29 02:58:24 PM UTC 24 |
7257666940 ps |
| T2387 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/72.xbar_unmapped_addr.3922035108 |
|
|
Aug 29 02:57:41 PM UTC 24 |
Aug 29 02:58:30 PM UTC 24 |
1062925950 ps |
| T2388 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/71.xbar_stress_all_with_error.327257746 |
|
|
Aug 29 02:56:57 PM UTC 24 |
Aug 29 02:58:34 PM UTC 24 |
2176019211 ps |
| T2389 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/73.xbar_smoke.3732490320 |
|
|
Aug 29 02:58:24 PM UTC 24 |
Aug 29 02:58:35 PM UTC 24 |
241603090 ps |
| T2390 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/73.xbar_smoke_zero_delays.593903437 |
|
|
Aug 29 02:58:27 PM UTC 24 |
Aug 29 02:58:37 PM UTC 24 |
45278190 ps |
| T2391 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/72.xbar_smoke_slow_rsp.1950365526 |
|
|
Aug 29 02:57:20 PM UTC 24 |
Aug 29 02:58:38 PM UTC 24 |
5525652838 ps |
| T2392 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/68.xbar_stress_all_with_reset_error.4097514251 |
|
|
Aug 29 02:53:48 PM UTC 24 |
Aug 29 02:58:41 PM UTC 24 |
2186529909 ps |
| T2393 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/70.xbar_stress_all_with_reset_error.3736335817 |
|
|
Aug 29 02:56:22 PM UTC 24 |
Aug 29 02:58:46 PM UTC 24 |
463684035 ps |
| T2394 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/72.xbar_error_random.774863462 |
|
|
Aug 29 02:57:44 PM UTC 24 |
Aug 29 02:58:46 PM UTC 24 |
1872885869 ps |
| T2395 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/72.xbar_smoke_large_delays.3492717750 |
|
|
Aug 29 02:57:15 PM UTC 24 |
Aug 29 02:58:53 PM UTC 24 |
7331345286 ps |
| T2396 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/70.xbar_stress_all.3540256929 |
|
|
Aug 29 02:56:06 PM UTC 24 |
Aug 29 02:58:53 PM UTC 24 |
1557225242 ps |
| T2397 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/72.xbar_access_same_device.3879916539 |
|
|
Aug 29 02:57:33 PM UTC 24 |
Aug 29 02:58:55 PM UTC 24 |
1254626073 ps |
| T2398 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/66.xbar_stress_all_with_rand_reset.2633199084 |
|
|
Aug 29 02:51:28 PM UTC 24 |
Aug 29 02:59:01 PM UTC 24 |
4383051447 ps |
| T2399 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/71.xbar_random_slow_rsp.2227117859 |
|
|
Aug 29 02:56:34 PM UTC 24 |
Aug 29 02:59:03 PM UTC 24 |
11194709767 ps |
| T2400 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/66.xbar_random_large_delays.956338704 |
|
|
Aug 29 02:50:55 PM UTC 24 |
Aug 29 02:59:05 PM UTC 24 |
40197957348 ps |
| T2401 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/73.xbar_same_source.2502078436 |
|
|
Aug 29 02:58:57 PM UTC 24 |
Aug 29 02:59:15 PM UTC 24 |
149530351 ps |
| T2402 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/73.xbar_error_and_unmapped_addr.2769613124 |
|
|
Aug 29 02:59:02 PM UTC 24 |
Aug 29 02:59:17 PM UTC 24 |
82427652 ps |
| T2403 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/72.xbar_stress_all.427382067 |
|
|
Aug 29 02:58:11 PM UTC 24 |
Aug 29 02:59:23 PM UTC 24 |
733018596 ps |
| T2404 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/64.xbar_random_large_delays.2831323376 |
|
|
Aug 29 02:48:37 PM UTC 24 |
Aug 29 02:59:24 PM UTC 24 |
61060112207 ps |
| T2405 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/73.xbar_unmapped_addr.4174500146 |
|
|
Aug 29 02:58:58 PM UTC 24 |
Aug 29 02:59:24 PM UTC 24 |
143043013 ps |
| T2406 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/65.xbar_random_slow_rsp.884631382 |
|
|
Aug 29 02:50:01 PM UTC 24 |
Aug 29 02:59:26 PM UTC 24 |
37315720757 ps |
| T2407 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/55.xbar_random_large_delays.1980522874 |
|
|
Aug 29 02:38:40 PM UTC 24 |
Aug 29 02:59:28 PM UTC 24 |
102916906936 ps |
| T2408 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/74.xbar_smoke.1063511454 |
|
|
Aug 29 02:59:14 PM UTC 24 |
Aug 29 02:59:29 PM UTC 24 |
243761891 ps |
| T2409 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/74.xbar_smoke_zero_delays.1588210427 |
|
|
Aug 29 02:59:23 PM UTC 24 |
Aug 29 02:59:32 PM UTC 24 |
39886886 ps |
| T2410 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/65.xbar_access_same_device_slow_rsp.3204773034 |
|
|
Aug 29 02:50:01 PM UTC 24 |
Aug 29 02:59:41 PM UTC 24 |
35682913250 ps |
| T2411 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/73.xbar_random.1342946073 |
|
|
Aug 29 02:58:39 PM UTC 24 |
Aug 29 02:59:42 PM UTC 24 |
545599815 ps |
| T2412 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/73.xbar_smoke_large_delays.775791552 |
|
|
Aug 29 02:58:27 PM UTC 24 |
Aug 29 02:59:50 PM UTC 24 |
6600912362 ps |
| T2413 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/68.xbar_stress_all.2251104452 |
|
|
Aug 29 02:53:41 PM UTC 24 |
Aug 29 02:59:53 PM UTC 24 |
9229377739 ps |
| T2414 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/73.xbar_access_same_device_slow_rsp.188982817 |
|
|
Aug 29 02:58:56 PM UTC 24 |
Aug 29 02:59:54 PM UTC 24 |
3092561794 ps |
| T2415 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/73.xbar_random_zero_delays.3799745871 |
|
|
Aug 29 02:58:39 PM UTC 24 |
Aug 29 02:59:54 PM UTC 24 |
641535493 ps |
| T2416 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/74.xbar_unmapped_addr.3933056899 |
|
|
Aug 29 02:59:52 PM UTC 24 |
Aug 29 03:00:12 PM UTC 24 |
92655803 ps |
| T2417 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/73.xbar_smoke_slow_rsp.2873884009 |
|
|
Aug 29 02:58:29 PM UTC 24 |
Aug 29 03:00:16 PM UTC 24 |
6476417244 ps |
| T2418 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/74.xbar_random_zero_delays.3867142270 |
|
|
Aug 29 02:59:37 PM UTC 24 |
Aug 29 03:00:16 PM UTC 24 |
505964025 ps |
| T2419 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/62.xbar_random_slow_rsp.3975014874 |
|
|
Aug 29 02:46:08 PM UTC 24 |
Aug 29 03:00:17 PM UTC 24 |
51121035474 ps |
| T2420 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/74.xbar_access_same_device.3531587154 |
|
|
Aug 29 02:59:45 PM UTC 24 |
Aug 29 03:00:22 PM UTC 24 |
337514644 ps |
| T2421 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/75.xbar_smoke.269700479 |
|
|
Aug 29 03:00:15 PM UTC 24 |
Aug 29 03:00:23 PM UTC 24 |
135334808 ps |
| T2422 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/73.xbar_error_random.1322909001 |
|
|
Aug 29 02:58:56 PM UTC 24 |
Aug 29 03:00:23 PM UTC 24 |
2472685157 ps |
| T2423 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/73.xbar_stress_all.2613238878 |
|
|
Aug 29 02:59:03 PM UTC 24 |
Aug 29 03:00:30 PM UTC 24 |
2410803139 ps |
| T2424 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/74.xbar_error_and_unmapped_addr.3516493269 |
|
|
Aug 29 03:00:01 PM UTC 24 |
Aug 29 03:00:35 PM UTC 24 |
233181994 ps |
| T2425 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/74.xbar_random.3474458855 |
|
|
Aug 29 02:59:35 PM UTC 24 |
Aug 29 03:00:35 PM UTC 24 |
1852628880 ps |
| T2426 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/74.xbar_same_source.1501496449 |
|
|
Aug 29 02:59:49 PM UTC 24 |
Aug 29 03:00:38 PM UTC 24 |
478276217 ps |
| T2427 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/75.xbar_smoke_zero_delays.11664572 |
|
|
Aug 29 03:00:33 PM UTC 24 |
Aug 29 03:00:43 PM UTC 24 |
48379600 ps |
| T2428 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/65.xbar_random_large_delays.4122064657 |
|
|
Aug 29 02:49:59 PM UTC 24 |
Aug 29 03:00:43 PM UTC 24 |
57451949927 ps |
| T2429 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/74.xbar_stress_all_with_reset_error.921415934 |
|
|
Aug 29 03:00:15 PM UTC 24 |
Aug 29 03:00:45 PM UTC 24 |
108587908 ps |
| T2430 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/71.xbar_stress_all_with_rand_reset.2165129387 |
|
|
Aug 29 02:56:53 PM UTC 24 |
Aug 29 03:00:49 PM UTC 24 |
341736438 ps |
| T2431 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/75.xbar_random_zero_delays.4292091490 |
|
|
Aug 29 03:00:42 PM UTC 24 |
Aug 29 03:00:52 PM UTC 24 |
72014802 ps |
| T2432 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/74.xbar_error_random.242663631 |
|
|
Aug 29 02:59:49 PM UTC 24 |
Aug 29 03:01:00 PM UTC 24 |
2176357169 ps |
| T2433 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/74.xbar_smoke_large_delays.4271596272 |
|
|
Aug 29 02:59:23 PM UTC 24 |
Aug 29 03:01:08 PM UTC 24 |
8421502557 ps |
| T2434 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/72.xbar_stress_all_with_rand_reset.2414393272 |
|
|
Aug 29 02:58:14 PM UTC 24 |
Aug 29 03:01:17 PM UTC 24 |
227222067 ps |
| T2435 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/73.xbar_access_same_device.1709293748 |
|
|
Aug 29 02:58:50 PM UTC 24 |
Aug 29 03:01:33 PM UTC 24 |
3421132776 ps |
| T2436 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/75.xbar_random.609936604 |
|
|
Aug 29 03:00:39 PM UTC 24 |
Aug 29 03:01:34 PM UTC 24 |
447061787 ps |
| T2437 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/75.xbar_error_and_unmapped_addr.1437259725 |
|
|
Aug 29 03:01:01 PM UTC 24 |
Aug 29 03:01:36 PM UTC 24 |
834012884 ps |
| T2438 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/67.xbar_stress_all_with_error.3709728975 |
|
|
Aug 29 02:52:24 PM UTC 24 |
Aug 29 03:01:37 PM UTC 24 |
13530621967 ps |
| T2439 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/76.xbar_smoke.3661856537 |
|
|
Aug 29 03:01:29 PM UTC 24 |
Aug 29 03:01:38 PM UTC 24 |
40077409 ps |
| T2440 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/74.xbar_smoke_slow_rsp.3541495822 |
|
|
Aug 29 02:59:25 PM UTC 24 |
Aug 29 03:01:43 PM UTC 24 |
5909292272 ps |
| T2441 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/76.xbar_smoke_zero_delays.749861175 |
|
|
Aug 29 03:01:38 PM UTC 24 |
Aug 29 03:01:48 PM UTC 24 |
41661357 ps |
| T2442 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/63.xbar_access_same_device_slow_rsp.3169968833 |
|
|
Aug 29 02:47:50 PM UTC 24 |
Aug 29 03:01:50 PM UTC 24 |
55515919575 ps |
| T2443 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/75.xbar_same_source.2857038973 |
|
|
Aug 29 03:00:52 PM UTC 24 |
Aug 29 03:02:01 PM UTC 24 |
2066925081 ps |
| T2444 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/75.xbar_smoke_slow_rsp.257580738 |
|
|
Aug 29 03:00:37 PM UTC 24 |
Aug 29 03:02:06 PM UTC 24 |
3715982582 ps |
| T2445 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/75.xbar_error_random.169327978 |
|
|
Aug 29 03:00:57 PM UTC 24 |
Aug 29 03:02:06 PM UTC 24 |
1872149352 ps |
| T2446 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/75.xbar_unmapped_addr.2674172583 |
|
|
Aug 29 03:01:01 PM UTC 24 |
Aug 29 03:02:11 PM UTC 24 |
1389156953 ps |
| T2447 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/71.xbar_random_large_delays.4138780010 |
|
|
Aug 29 02:56:33 PM UTC 24 |
Aug 29 03:02:27 PM UTC 24 |
33418281432 ps |
| T2448 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/76.xbar_random_zero_delays.4152100440 |
|
|
Aug 29 03:01:55 PM UTC 24 |
Aug 29 03:02:31 PM UTC 24 |
273250373 ps |
| T2449 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/67.xbar_stress_all_with_rand_reset.1232835829 |
|
|
Aug 29 02:52:23 PM UTC 24 |
Aug 29 03:02:32 PM UTC 24 |
7668981109 ps |
| T606 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/62.xbar_stress_all_with_reset_error.2462460535 |
|
|
Aug 29 02:46:47 PM UTC 24 |
Aug 29 03:02:33 PM UTC 24 |
23128189298 ps |
| T2450 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/76.xbar_random.3626166772 |
|
|
Aug 29 03:01:54 PM UTC 24 |
Aug 29 03:02:37 PM UTC 24 |
850693091 ps |
| T2451 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/75.xbar_smoke_large_delays.2270195256 |
|
|
Aug 29 03:00:37 PM UTC 24 |
Aug 29 03:02:42 PM UTC 24 |
8858031255 ps |
| T2452 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/75.xbar_access_same_device.2959399325 |
|
|
Aug 29 03:00:49 PM UTC 24 |
Aug 29 03:02:54 PM UTC 24 |
2700609946 ps |
| T2453 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/76.xbar_error_random.824471169 |
|
|
Aug 29 03:02:25 PM UTC 24 |
Aug 29 03:02:56 PM UTC 24 |
676179931 ps |
| T2454 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/76.xbar_unmapped_addr.1537252822 |
|
|
Aug 29 03:02:24 PM UTC 24 |
Aug 29 03:03:02 PM UTC 24 |
819908231 ps |
| T2455 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/76.xbar_error_and_unmapped_addr.2649644165 |
|
|
Aug 29 03:02:31 PM UTC 24 |
Aug 29 03:03:04 PM UTC 24 |
226594957 ps |
| T2456 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/76.xbar_same_source.3302520295 |
|
|
Aug 29 03:02:20 PM UTC 24 |
Aug 29 03:03:06 PM UTC 24 |
461393955 ps |
| T2457 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/55.xbar_access_same_device_slow_rsp.4160686356 |
|
|
Aug 29 02:38:46 PM UTC 24 |
Aug 29 03:03:06 PM UTC 24 |
96474326270 ps |
| T2458 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/77.xbar_smoke.3702933491 |
|
|
Aug 29 03:02:57 PM UTC 24 |
Aug 29 03:03:07 PM UTC 24 |
47355788 ps |
| T2459 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/77.xbar_smoke_zero_delays.4290784289 |
|
|
Aug 29 03:03:02 PM UTC 24 |
Aug 29 03:03:11 PM UTC 24 |
39220349 ps |
| T2460 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/76.xbar_smoke_large_delays.622016627 |
|
|
Aug 29 03:01:54 PM UTC 24 |
Aug 29 03:03:17 PM UTC 24 |
7320687261 ps |
| T2461 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/69.xbar_stress_all_with_error.1952557797 |
|
|
Aug 29 02:54:59 PM UTC 24 |
Aug 29 03:03:21 PM UTC 24 |
13403472394 ps |
| T2462 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/74.xbar_stress_all.1090784214 |
|
|
Aug 29 03:00:01 PM UTC 24 |
Aug 29 03:03:24 PM UTC 24 |
5317374597 ps |
| T2463 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/75.xbar_stress_all_with_reset_error.471216584 |
|
|
Aug 29 03:01:21 PM UTC 24 |
Aug 29 03:03:25 PM UTC 24 |
476081379 ps |
| T2464 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/76.xbar_smoke_slow_rsp.1503896902 |
|
|
Aug 29 03:01:56 PM UTC 24 |
Aug 29 03:03:42 PM UTC 24 |
6172731643 ps |
| T2465 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/76.xbar_stress_all.1408502028 |
|
|
Aug 29 03:02:47 PM UTC 24 |
Aug 29 03:03:46 PM UTC 24 |
590321355 ps |
| T2466 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/77.xbar_same_source.4130062164 |
|
|
Aug 29 03:03:37 PM UTC 24 |
Aug 29 03:03:50 PM UTC 24 |
249236522 ps |
| T2467 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/75.xbar_stress_all.2598789271 |
|
|
Aug 29 03:01:05 PM UTC 24 |
Aug 29 03:03:58 PM UTC 24 |
4757628518 ps |
| T2468 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/72.xbar_stress_all_with_error.1254447043 |
|
|
Aug 29 02:58:17 PM UTC 24 |
Aug 29 03:04:01 PM UTC 24 |
9421374473 ps |
| T2469 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/76.xbar_access_same_device.294615759 |
|
|
Aug 29 03:02:07 PM UTC 24 |
Aug 29 03:04:03 PM UTC 24 |
2768255726 ps |
| T2470 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/67.xbar_stress_all_with_reset_error.513368789 |
|
|
Aug 29 02:52:28 PM UTC 24 |
Aug 29 03:04:12 PM UTC 24 |
5921216097 ps |
| T2471 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/77.xbar_error_and_unmapped_addr.782162734 |
|
|
Aug 29 03:03:46 PM UTC 24 |
Aug 29 03:04:18 PM UTC 24 |
213438515 ps |
| T2472 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/77.xbar_error_random.2002071410 |
|
|
Aug 29 03:03:41 PM UTC 24 |
Aug 29 03:04:18 PM UTC 24 |
1266943293 ps |
| T2473 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/77.xbar_random.24211674 |
|
|
Aug 29 03:03:20 PM UTC 24 |
Aug 29 03:04:20 PM UTC 24 |
1256975237 ps |
| T2474 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/77.xbar_unmapped_addr.1634773837 |
|
|
Aug 29 03:03:44 PM UTC 24 |
Aug 29 03:04:24 PM UTC 24 |
267478056 ps |
| T2475 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/77.xbar_random_zero_delays.2069353234 |
|
|
Aug 29 03:03:25 PM UTC 24 |
Aug 29 03:04:28 PM UTC 24 |
563056341 ps |
| T2476 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/78.xbar_smoke.1667598963 |
|
|
Aug 29 03:04:21 PM UTC 24 |
Aug 29 03:04:29 PM UTC 24 |
44357256 ps |
| T2477 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/72.xbar_stress_all_with_reset_error.4279144955 |
|
|
Aug 29 02:58:22 PM UTC 24 |
Aug 29 03:04:30 PM UTC 24 |
2599653006 ps |
| T2478 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/78.xbar_smoke_zero_delays.386068447 |
|
|
Aug 29 03:04:24 PM UTC 24 |
Aug 29 03:04:33 PM UTC 24 |
49763021 ps |
| T2479 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/77.xbar_stress_all_with_rand_reset.3115017002 |
|
|
Aug 29 03:04:07 PM UTC 24 |
Aug 29 03:04:33 PM UTC 24 |
60589880 ps |
| T2480 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/77.xbar_smoke_slow_rsp.460312044 |
|
|
Aug 29 03:03:16 PM UTC 24 |
Aug 29 03:04:38 PM UTC 24 |
4339819937 ps |
| T2481 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/73.xbar_random_slow_rsp.217190574 |
|
|
Aug 29 02:58:44 PM UTC 24 |
Aug 29 03:04:45 PM UTC 24 |
22708703566 ps |
| T2482 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/76.xbar_stress_all_with_reset_error.906899709 |
|
|
Aug 29 03:02:54 PM UTC 24 |
Aug 29 03:04:47 PM UTC 24 |
226181899 ps |
| T2483 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/67.xbar_random_slow_rsp.1508431450 |
|
|
Aug 29 02:52:09 PM UTC 24 |
Aug 29 03:04:51 PM UTC 24 |
47637482781 ps |
| T2484 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/75.xbar_access_same_device_slow_rsp.811478997 |
|
|
Aug 29 03:00:55 PM UTC 24 |
Aug 29 03:04:53 PM UTC 24 |
13998413065 ps |
| T2485 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/78.xbar_random_zero_delays.3202521658 |
|
|
Aug 29 03:04:40 PM UTC 24 |
Aug 29 03:04:55 PM UTC 24 |
121234990 ps |
| T2486 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/77.xbar_access_same_device.4131999125 |
|
|
Aug 29 03:03:28 PM UTC 24 |
Aug 29 03:04:56 PM UTC 24 |
904068745 ps |
| T2487 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/77.xbar_smoke_large_delays.3387191186 |
|
|
Aug 29 03:03:15 PM UTC 24 |
Aug 29 03:05:04 PM UTC 24 |
7937199122 ps |
| T2488 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/78.xbar_error_and_unmapped_addr.3820475267 |
|
|
Aug 29 03:05:06 PM UTC 24 |
Aug 29 03:05:17 PM UTC 24 |
89752870 ps |
| T2489 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/78.xbar_random.2613876585 |
|
|
Aug 29 03:04:39 PM UTC 24 |
Aug 29 03:05:19 PM UTC 24 |
483237055 ps |
| T2490 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/78.xbar_error_random.3735853086 |
|
|
Aug 29 03:04:55 PM UTC 24 |
Aug 29 03:05:21 PM UTC 24 |
319214877 ps |
| T2491 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/79.xbar_smoke.1660516016 |
|
|
Aug 29 03:05:14 PM UTC 24 |
Aug 29 03:05:26 PM UTC 24 |
151799512 ps |
| T2492 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/67.xbar_access_same_device_slow_rsp.3651206189 |
|
|
Aug 29 02:52:12 PM UTC 24 |
Aug 29 03:05:27 PM UTC 24 |
47827791732 ps |
| T2493 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/78.xbar_unmapped_addr.3279438488 |
|
|
Aug 29 03:04:57 PM UTC 24 |
Aug 29 03:05:31 PM UTC 24 |
523658494 ps |
| T2494 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/79.xbar_smoke_zero_delays.2754814482 |
|
|
Aug 29 03:05:24 PM UTC 24 |
Aug 29 03:05:33 PM UTC 24 |
49672402 ps |
| T2495 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/60.xbar_random_large_delays.1381537868 |
|
|
Aug 29 02:43:59 PM UTC 24 |
Aug 29 03:05:38 PM UTC 24 |
108718950327 ps |
| T2496 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/66.xbar_stress_all_with_reset_error.1029851311 |
|
|
Aug 29 02:51:40 PM UTC 24 |
Aug 29 03:05:42 PM UTC 24 |
18478120061 ps |
| T2497 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/78.xbar_same_source.1942574980 |
|
|
Aug 29 03:04:54 PM UTC 24 |
Aug 29 03:05:45 PM UTC 24 |
1656680479 ps |
| T2498 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/73.xbar_stress_all_with_rand_reset.2052484785 |
|
|
Aug 29 02:59:05 PM UTC 24 |
Aug 29 03:05:49 PM UTC 24 |
8532750001 ps |
| T2499 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/78.xbar_access_same_device.1664101371 |
|
|
Aug 29 03:04:49 PM UTC 24 |
Aug 29 03:05:54 PM UTC 24 |
1051984916 ps |
| T2500 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/63.xbar_random_slow_rsp.305164918 |
|
|
Aug 29 02:47:27 PM UTC 24 |
Aug 29 03:05:59 PM UTC 24 |
61164566736 ps |
| T2501 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/71.xbar_stress_all.152911991 |
|
|
Aug 29 02:56:53 PM UTC 24 |
Aug 29 03:06:13 PM UTC 24 |
14424495328 ps |
| T2502 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/76.xbar_stress_all_with_rand_reset.1939528394 |
|
|
Aug 29 03:02:53 PM UTC 24 |
Aug 29 03:06:15 PM UTC 24 |
517174154 ps |
| T2503 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/79.xbar_same_source.3629455552 |
|
|
Aug 29 03:06:02 PM UTC 24 |
Aug 29 03:06:22 PM UTC 24 |
177436916 ps |
| T2504 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/76.xbar_access_same_device_slow_rsp.2924856358 |
|
|
Aug 29 03:02:11 PM UTC 24 |
Aug 29 03:06:23 PM UTC 24 |
17578056412 ps |
| T2505 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/66.xbar_random_slow_rsp.132732076 |
|
|
Aug 29 02:51:02 PM UTC 24 |
Aug 29 03:06:24 PM UTC 24 |
61085698185 ps |
| T2506 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/79.xbar_random_zero_delays.1715472864 |
|
|
Aug 29 03:05:46 PM UTC 24 |
Aug 29 03:06:31 PM UTC 24 |
544954626 ps |
| T2507 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/78.xbar_smoke_slow_rsp.1855010394 |
|
|
Aug 29 03:04:38 PM UTC 24 |
Aug 29 03:06:31 PM UTC 24 |
6394115508 ps |
| T2508 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/79.xbar_error_and_unmapped_addr.605582594 |
|
|
Aug 29 03:06:14 PM UTC 24 |
Aug 29 03:06:33 PM UTC 24 |
471511736 ps |
| T2509 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/79.xbar_random.4032428098 |
|
|
Aug 29 03:05:41 PM UTC 24 |
Aug 29 03:06:34 PM UTC 24 |
454014117 ps |
| T2510 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/72.xbar_random_large_delays.97230815 |
|
|
Aug 29 02:57:28 PM UTC 24 |
Aug 29 03:06:38 PM UTC 24 |
46505555094 ps |
| T2511 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/79.xbar_unmapped_addr.678755219 |
|
|
Aug 29 03:06:10 PM UTC 24 |
Aug 29 03:06:40 PM UTC 24 |
589825086 ps |