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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
96.14 95.50 93.91 95.52 94.84 97.53 99.55


Total test records in report: 2926
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T649 /workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/47.xbar_stress_all_with_error.3010563812 Aug 29 02:27:42 PM UTC 24 Aug 29 02:35:19 PM UTC 24 10761111739 ps
T2022 /workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/28.xbar_access_same_device_slow_rsp.4260905950 Aug 29 01:59:10 PM UTC 24 Aug 29 02:35:23 PM UTC 24 127741708207 ps
T2023 /workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/35.xbar_access_same_device_slow_rsp.618579403 Aug 29 02:08:36 PM UTC 24 Aug 29 02:35:24 PM UTC 24 103042000517 ps
T2024 /workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/52.xbar_error_random.1792147645 Aug 29 02:35:08 PM UTC 24 Aug 29 02:35:25 PM UTC 24 298021600 ps
T2025 /workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/52.xbar_access_same_device.2945421438 Aug 29 02:35:06 PM UTC 24 Aug 29 02:35:29 PM UTC 24 288995671 ps
T2026 /workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/52.xbar_unmapped_addr.2391536274 Aug 29 02:35:14 PM UTC 24 Aug 29 02:35:29 PM UTC 24 203384694 ps
T2027 /workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/52.xbar_same_source.2797466088 Aug 29 02:35:07 PM UTC 24 Aug 29 02:35:35 PM UTC 24 287983900 ps
T2028 /workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/49.xbar_stress_all.3658015813 Aug 29 02:30:38 PM UTC 24 Aug 29 02:35:47 PM UTC 24 9120848614 ps
T2029 /workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/52.xbar_random.661035456 Aug 29 02:34:45 PM UTC 24 Aug 29 02:35:49 PM UTC 24 1851738036 ps
T2030 /workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/52.xbar_random_zero_delays.1891855730 Aug 29 02:34:49 PM UTC 24 Aug 29 02:35:53 PM UTC 24 584302904 ps
T2031 /workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/53.xbar_smoke.967960992 Aug 29 02:35:46 PM UTC 24 Aug 29 02:35:58 PM UTC 24 168399727 ps
T2032 /workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/53.xbar_smoke_zero_delays.3308029076 Aug 29 02:35:50 PM UTC 24 Aug 29 02:36:01 PM UTC 24 50027792 ps
T2033 /workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/42.xbar_access_same_device_slow_rsp.390497308 Aug 29 02:20:37 PM UTC 24 Aug 29 02:36:07 PM UTC 24 51294464766 ps
T2034 /workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/52.xbar_smoke_large_delays.1854786302 Aug 29 02:34:37 PM UTC 24 Aug 29 02:36:09 PM UTC 24 8331313849 ps
T2035 /workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/52.xbar_error_and_unmapped_addr.1896889946 Aug 29 02:35:27 PM UTC 24 Aug 29 02:36:11 PM UTC 24 1158620606 ps
T2036 /workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/49.xbar_stress_all_with_error.1744810180 Aug 29 02:30:48 PM UTC 24 Aug 29 02:36:23 PM UTC 24 10376822956 ps
T2037 /workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/51.xbar_stress_all_with_reset_error.2726484868 Aug 29 02:34:26 PM UTC 24 Aug 29 02:36:25 PM UTC 24 365290261 ps
T2038 /workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/46.xbar_random_large_delays.1622814546 Aug 29 02:25:53 PM UTC 24 Aug 29 02:36:31 PM UTC 24 60847063208 ps
T2039 /workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/2.chip_csr_bit_bash.3932800764 Aug 29 01:01:28 PM UTC 24 Aug 29 02:36:34 PM UTC 24 48253633899 ps
T2040 /workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/43.xbar_random_slow_rsp.3883873001 Aug 29 02:21:42 PM UTC 24 Aug 29 02:36:41 PM UTC 24 49578907468 ps
T2041 /workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/53.xbar_access_same_device.2878688605 Aug 29 02:36:21 PM UTC 24 Aug 29 02:36:47 PM UTC 24 228625892 ps
T2042 /workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/52.xbar_smoke_slow_rsp.3936177875 Aug 29 02:34:40 PM UTC 24 Aug 29 02:36:48 PM UTC 24 6279570528 ps
T2043 /workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/53.xbar_random_zero_delays.2393337714 Aug 29 02:36:09 PM UTC 24 Aug 29 02:36:48 PM UTC 24 311594003 ps
T2044 /workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/52.xbar_stress_all_with_error.4103002593 Aug 29 02:35:44 PM UTC 24 Aug 29 02:36:58 PM UTC 24 1599148806 ps
T2045 /workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/53.xbar_error_and_unmapped_addr.2877956956 Aug 29 02:36:46 PM UTC 24 Aug 29 02:36:59 PM UTC 24 113575834 ps
T2046 /workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/53.xbar_unmapped_addr.389029298 Aug 29 02:36:45 PM UTC 24 Aug 29 02:37:00 PM UTC 24 63877045 ps
T2047 /workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/53.xbar_random.591790227 Aug 29 02:36:07 PM UTC 24 Aug 29 02:37:00 PM UTC 24 1153371589 ps
T2048 /workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/33.xbar_access_same_device_slow_rsp.3359725464 Aug 29 02:05:48 PM UTC 24 Aug 29 02:37:05 PM UTC 24 119581312607 ps
T2049 /workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/53.xbar_error_random.796691732 Aug 29 02:36:29 PM UTC 24 Aug 29 02:37:13 PM UTC 24 925578420 ps
T2050 /workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/37.xbar_random_large_delays.2609963793 Aug 29 02:11:57 PM UTC 24 Aug 29 02:37:15 PM UTC 24 109802869451 ps
T2051 /workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/54.xbar_smoke_zero_delays.388491757 Aug 29 02:37:08 PM UTC 24 Aug 29 02:37:18 PM UTC 24 39894195 ps
T2052 /workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/53.xbar_smoke_large_delays.1700228088 Aug 29 02:35:50 PM UTC 24 Aug 29 02:37:21 PM UTC 24 7598112941 ps
T2053 /workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/54.xbar_smoke.1389774702 Aug 29 02:37:09 PM UTC 24 Aug 29 02:37:22 PM UTC 24 190682438 ps
T2054 /workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/39.xbar_random_large_delays.924645465 Aug 29 02:15:04 PM UTC 24 Aug 29 02:37:25 PM UTC 24 115486843178 ps
T2055 /workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/53.xbar_smoke_slow_rsp.1823853984 Aug 29 02:35:55 PM UTC 24 Aug 29 02:37:32 PM UTC 24 4349081217 ps
T2056 /workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/53.xbar_same_source.1590667836 Aug 29 02:36:30 PM UTC 24 Aug 29 02:37:42 PM UTC 24 1712230507 ps
T2057 /workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/52.xbar_stress_all_with_reset_error.48973176 Aug 29 02:35:42 PM UTC 24 Aug 29 02:37:53 PM UTC 24 2265398635 ps
T2058 /workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/54.xbar_random.1746985082 Aug 29 02:37:18 PM UTC 24 Aug 29 02:37:55 PM UTC 24 295802886 ps
T2059 /workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/54.xbar_error_and_unmapped_addr.1788031233 Aug 29 02:37:53 PM UTC 24 Aug 29 02:38:08 PM UTC 24 356700157 ps
T2060 /workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/54.xbar_random_zero_delays.1989624339 Aug 29 02:37:21 PM UTC 24 Aug 29 02:38:09 PM UTC 24 482551811 ps
T2061 /workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/48.xbar_stress_all_with_reset_error.1538965745 Aug 29 02:29:27 PM UTC 24 Aug 29 02:38:09 PM UTC 24 3069681604 ps
T2062 /workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/45.xbar_random_slow_rsp.3132092116 Aug 29 02:24:50 PM UTC 24 Aug 29 02:38:12 PM UTC 24 45880904503 ps
T2063 /workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/54.xbar_access_same_device.3006499115 Aug 29 02:37:35 PM UTC 24 Aug 29 02:38:19 PM UTC 24 806121048 ps
T2064 /workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/54.xbar_error_random.1916213018 Aug 29 02:37:42 PM UTC 24 Aug 29 02:38:19 PM UTC 24 356659919 ps
T2065 /workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/52.xbar_access_same_device_slow_rsp.3513083256 Aug 29 02:35:07 PM UTC 24 Aug 29 02:38:20 PM UTC 24 11409568081 ps
T2066 /workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/50.xbar_random_slow_rsp.2892461599 Aug 29 02:31:33 PM UTC 24 Aug 29 02:38:21 PM UTC 24 24217229211 ps
T2067 /workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/51.xbar_stress_all_with_error.1243651967 Aug 29 02:34:19 PM UTC 24 Aug 29 02:38:23 PM UTC 24 8156143164 ps
T880 /workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/43.xbar_stress_all_with_reset_error.2106056775 Aug 29 02:22:38 PM UTC 24 Aug 29 02:38:23 PM UTC 24 16266013455 ps
T2068 /workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/54.xbar_unmapped_addr.2420551369 Aug 29 02:37:45 PM UTC 24 Aug 29 02:38:27 PM UTC 24 860428179 ps
T2069 /workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/54.xbar_random_large_delays.3257002383 Aug 29 02:37:26 PM UTC 24 Aug 29 02:38:29 PM UTC 24 4656847617 ps
T2070 /workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/55.xbar_smoke_zero_delays.966974756 Aug 29 02:38:30 PM UTC 24 Aug 29 02:38:40 PM UTC 24 45590073 ps
T2071 /workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/55.xbar_smoke.1453586978 Aug 29 02:38:31 PM UTC 24 Aug 29 02:38:46 PM UTC 24 257293010 ps
T2072 /workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/55.xbar_random.984660861 Aug 29 02:38:38 PM UTC 24 Aug 29 02:38:57 PM UTC 24 165941176 ps
T2073 /workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/54.xbar_same_source.2601562870 Aug 29 02:37:41 PM UTC 24 Aug 29 02:39:04 PM UTC 24 2631649172 ps
T444 /workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/15.chip_same_csr_outstanding.1055911511 Aug 29 01:30:35 PM UTC 24 Aug 29 02:39:06 PM UTC 24 28810302288 ps
T2074 /workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/55.xbar_random_zero_delays.211610371 Aug 29 02:38:40 PM UTC 24 Aug 29 02:39:09 PM UTC 24 226260371 ps
T2075 /workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/51.xbar_stress_all_with_rand_reset.3343145910 Aug 29 02:34:19 PM UTC 24 Aug 29 02:39:20 PM UTC 24 690437865 ps
T2076 /workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/54.xbar_smoke_slow_rsp.2408366466 Aug 29 02:37:18 PM UTC 24 Aug 29 02:39:27 PM UTC 24 5580865462 ps
T2077 /workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/47.xbar_random_large_delays.2002785283 Aug 29 02:27:11 PM UTC 24 Aug 29 02:39:28 PM UTC 24 60463056837 ps
T2078 /workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/53.xbar_stress_all_with_reset_error.1615639246 Aug 29 02:37:09 PM UTC 24 Aug 29 02:39:29 PM UTC 24 311897752 ps
T2079 /workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/51.xbar_stress_all.1249489242 Aug 29 02:34:10 PM UTC 24 Aug 29 02:39:31 PM UTC 24 7882637249 ps
T2080 /workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/47.xbar_access_same_device_slow_rsp.534596561 Aug 29 02:27:25 PM UTC 24 Aug 29 02:39:32 PM UTC 24 40129042678 ps
T2081 /workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/55.xbar_same_source.909978364 Aug 29 02:38:46 PM UTC 24 Aug 29 02:39:33 PM UTC 24 1488232887 ps
T2082 /workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/55.xbar_unmapped_addr.3469817169 Aug 29 02:39:07 PM UTC 24 Aug 29 02:39:33 PM UTC 24 224002792 ps
T2083 /workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/55.xbar_access_same_device.297586550 Aug 29 02:38:45 PM UTC 24 Aug 29 02:39:38 PM UTC 24 1494708603 ps
T2084 /workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/54.xbar_smoke_large_delays.683398340 Aug 29 02:37:19 PM UTC 24 Aug 29 02:39:39 PM UTC 24 8717059504 ps
T2085 /workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/34.xbar_access_same_device_slow_rsp.1660008466 Aug 29 02:07:16 PM UTC 24 Aug 29 02:39:54 PM UTC 24 117615032417 ps
T2086 /workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/56.xbar_smoke.97195202 Aug 29 02:39:45 PM UTC 24 Aug 29 02:39:58 PM UTC 24 174672160 ps
T2087 /workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/44.xbar_random_slow_rsp.2699577489 Aug 29 02:23:21 PM UTC 24 Aug 29 02:39:58 PM UTC 24 60864813436 ps
T2088 /workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/56.xbar_smoke_zero_delays.1064716213 Aug 29 02:39:49 PM UTC 24 Aug 29 02:39:59 PM UTC 24 48674934 ps
T2089 /workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/52.xbar_random_large_delays.3918210264 Aug 29 02:35:01 PM UTC 24 Aug 29 02:40:02 PM UTC 24 26804069074 ps
T2090 /workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/54.xbar_random_slow_rsp.1743272264 Aug 29 02:37:33 PM UTC 24 Aug 29 02:40:06 PM UTC 24 8996601673 ps
T2091 /workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/50.xbar_stress_all.3991346285 Aug 29 02:32:21 PM UTC 24 Aug 29 02:40:10 PM UTC 24 12229952317 ps
T2092 /workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/55.xbar_smoke_large_delays.1680890023 Aug 29 02:38:31 PM UTC 24 Aug 29 02:40:14 PM UTC 24 6700151968 ps
T2093 /workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/56.xbar_random.2635719400 Aug 29 02:39:50 PM UTC 24 Aug 29 02:40:18 PM UTC 24 694013597 ps
T2094 /workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/56.xbar_random_zero_delays.787210739 Aug 29 02:39:53 PM UTC 24 Aug 29 02:40:19 PM UTC 24 260532385 ps
T2095 /workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/42.xbar_random_large_delays.3606017875 Aug 29 02:20:20 PM UTC 24 Aug 29 02:40:23 PM UTC 24 95303805938 ps
T2096 /workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/55.xbar_error_and_unmapped_addr.824816573 Aug 29 02:39:19 PM UTC 24 Aug 29 02:40:29 PM UTC 24 1371204978 ps
T2097 /workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/55.xbar_error_random.2518047877 Aug 29 02:38:59 PM UTC 24 Aug 29 02:40:36 PM UTC 24 2452236543 ps
T2098 /workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/56.xbar_unmapped_addr.298544198 Aug 29 02:40:21 PM UTC 24 Aug 29 02:40:43 PM UTC 24 130619287 ps
T2099 /workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/3.chip_csr_aliasing.272178965 Aug 29 01:02:53 PM UTC 24 Aug 29 02:40:45 PM UTC 24 33050032420 ps
T2100 /workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/57.xbar_smoke.516968638 Aug 29 02:40:39 PM UTC 24 Aug 29 02:40:49 PM UTC 24 36262749 ps
T2101 /workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/57.xbar_smoke_zero_delays.3408987222 Aug 29 02:40:41 PM UTC 24 Aug 29 02:40:51 PM UTC 24 40767804 ps
T2102 /workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/55.xbar_smoke_slow_rsp.835422187 Aug 29 02:38:39 PM UTC 24 Aug 29 02:40:51 PM UTC 24 5875215348 ps
T2103 /workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/56.xbar_error_and_unmapped_addr.1630688607 Aug 29 02:40:23 PM UTC 24 Aug 29 02:40:55 PM UTC 24 299263611 ps
T2104 /workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/56.xbar_same_source.190868536 Aug 29 02:40:19 PM UTC 24 Aug 29 02:40:58 PM UTC 24 988774120 ps
T2105 /workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/56.xbar_error_random.1734665780 Aug 29 02:40:19 PM UTC 24 Aug 29 02:41:04 PM UTC 24 1241871115 ps
T2106 /workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/44.xbar_access_same_device_slow_rsp.1794871791 Aug 29 02:23:30 PM UTC 24 Aug 29 02:41:12 PM UTC 24 62925476745 ps
T2107 /workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/56.xbar_smoke_slow_rsp.1108348526 Aug 29 02:39:51 PM UTC 24 Aug 29 02:41:16 PM UTC 24 5860271799 ps
T2108 /workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/44.xbar_random_large_delays.3944866335 Aug 29 02:23:18 PM UTC 24 Aug 29 02:41:17 PM UTC 24 96773287361 ps
T2109 /workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/50.xbar_random_large_delays.624558202 Aug 29 02:31:33 PM UTC 24 Aug 29 02:41:26 PM UTC 24 50709506960 ps
T2110 /workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/56.xbar_smoke_large_delays.2570419631 Aug 29 02:39:47 PM UTC 24 Aug 29 02:41:27 PM UTC 24 9797868127 ps
T2111 /workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/50.xbar_stress_all_with_error.2393585697 Aug 29 02:32:42 PM UTC 24 Aug 29 02:41:31 PM UTC 24 15848472895 ps
T2112 /workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/56.xbar_access_same_device.3927273128 Aug 29 02:39:57 PM UTC 24 Aug 29 02:41:37 PM UTC 24 2191225500 ps
T878 /workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/50.xbar_stress_all_with_reset_error.169507187 Aug 29 02:32:51 PM UTC 24 Aug 29 02:41:43 PM UTC 24 7213635254 ps
T2113 /workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/57.xbar_access_same_device.1329716951 Aug 29 02:41:12 PM UTC 24 Aug 29 02:41:48 PM UTC 24 636667743 ps
T2114 /workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/57.xbar_random_zero_delays.2261296669 Aug 29 02:41:05 PM UTC 24 Aug 29 02:41:50 PM UTC 24 556025504 ps
T650 /workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/53.xbar_stress_all_with_error.253593746 Aug 29 02:37:01 PM UTC 24 Aug 29 02:41:52 PM UTC 24 2914982938 ps
T2115 /workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/56.xbar_random_slow_rsp.3804299636 Aug 29 02:39:55 PM UTC 24 Aug 29 02:41:53 PM UTC 24 6616711371 ps
T2116 /workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/56.xbar_stress_all_with_reset_error.2212977753 Aug 29 02:40:38 PM UTC 24 Aug 29 02:41:53 PM UTC 24 190544570 ps
T2117 /workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/57.xbar_random.2420067387 Aug 29 02:41:02 PM UTC 24 Aug 29 02:41:58 PM UTC 24 463226834 ps
T2118 /workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/57.xbar_error_random.482454201 Aug 29 02:41:23 PM UTC 24 Aug 29 02:41:59 PM UTC 24 973860808 ps
T2119 /workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/48.xbar_random_slow_rsp.1335358980 Aug 29 02:28:26 PM UTC 24 Aug 29 02:42:02 PM UTC 24 52677726707 ps
T2120 /workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/54.xbar_stress_all_with_rand_reset.3944384327 Aug 29 02:38:14 PM UTC 24 Aug 29 02:42:03 PM UTC 24 1740973423 ps
T2121 /workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/57.xbar_smoke_slow_rsp.901458301 Aug 29 02:40:55 PM UTC 24 Aug 29 02:42:04 PM UTC 24 4647809277 ps
T2122 /workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/58.xbar_smoke.1113312108 Aug 29 02:41:57 PM UTC 24 Aug 29 02:42:10 PM UTC 24 192482984 ps
T2123 /workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/57.xbar_error_and_unmapped_addr.2426221237 Aug 29 02:41:36 PM UTC 24 Aug 29 02:42:11 PM UTC 24 264589913 ps
T2124 /workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/52.xbar_stress_all.385122285 Aug 29 02:35:38 PM UTC 24 Aug 29 02:42:13 PM UTC 24 8528119330 ps
T2125 /workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/58.xbar_smoke_zero_delays.4234076708 Aug 29 02:42:04 PM UTC 24 Aug 29 02:42:14 PM UTC 24 46904309 ps
T2126 /workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/45.xbar_random_large_delays.655127831 Aug 29 02:24:48 PM UTC 24 Aug 29 02:42:14 PM UTC 24 91016816035 ps
T2127 /workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/54.xbar_stress_all_with_error.2503009497 Aug 29 02:38:15 PM UTC 24 Aug 29 02:42:16 PM UTC 24 2803726992 ps
T2128 /workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/54.xbar_stress_all.2396790947 Aug 29 02:38:04 PM UTC 24 Aug 29 02:42:18 PM UTC 24 2472660132 ps
T2129 /workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/57.xbar_same_source.3326980002 Aug 29 02:41:19 PM UTC 24 Aug 29 02:42:20 PM UTC 24 1837018175 ps
T2130 /workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/57.xbar_unmapped_addr.2262760676 Aug 29 02:41:29 PM UTC 24 Aug 29 02:42:20 PM UTC 24 308172781 ps
T2131 /workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/53.xbar_stress_all.1737824086 Aug 29 02:36:52 PM UTC 24 Aug 29 02:42:34 PM UTC 24 3449915595 ps
T2132 /workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/55.xbar_stress_all.2098897078 Aug 29 02:39:25 PM UTC 24 Aug 29 02:42:41 PM UTC 24 2019751539 ps
T2133 /workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/58.xbar_error_random.4019096574 Aug 29 02:42:24 PM UTC 24 Aug 29 02:42:47 PM UTC 24 191403616 ps
T2134 /workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/58.xbar_error_and_unmapped_addr.2254805915 Aug 29 02:42:30 PM UTC 24 Aug 29 02:42:48 PM UTC 24 254614546 ps
T2135 /workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/59.xbar_smoke.3425453245 Aug 29 02:42:37 PM UTC 24 Aug 29 02:42:48 PM UTC 24 105776900 ps
T2136 /workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/59.xbar_smoke_zero_delays.1096751671 Aug 29 02:42:41 PM UTC 24 Aug 29 02:42:50 PM UTC 24 40618663 ps
T2137 /workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/56.xbar_stress_all_with_rand_reset.1450004210 Aug 29 02:40:31 PM UTC 24 Aug 29 02:42:55 PM UTC 24 347970836 ps
T2138 /workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/58.xbar_unmapped_addr.2315052831 Aug 29 02:42:31 PM UTC 24 Aug 29 02:42:56 PM UTC 24 116497810 ps
T2139 /workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/57.xbar_smoke_large_delays.3116956277 Aug 29 02:40:46 PM UTC 24 Aug 29 02:42:57 PM UTC 24 8062091832 ps
T2140 /workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/53.xbar_random_slow_rsp.1552202546 Aug 29 02:36:18 PM UTC 24 Aug 29 02:42:57 PM UTC 24 27912553447 ps
T2141 /workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/58.xbar_same_source.263004854 Aug 29 02:42:23 PM UTC 24 Aug 29 02:42:57 PM UTC 24 352706390 ps
T2142 /workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/17.chip_same_csr_outstanding.1963096207 Aug 29 01:36:05 PM UTC 24 Aug 29 02:42:58 PM UTC 24 27220069353 ps
T2143 /workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/58.xbar_stress_all_with_reset_error.2874701119 Aug 29 02:42:35 PM UTC 24 Aug 29 02:43:04 PM UTC 24 68924658 ps
T2144 /workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/57.xbar_stress_all_with_error.2942468022 Aug 29 02:41:44 PM UTC 24 Aug 29 02:43:09 PM UTC 24 2263668945 ps
T2145 /workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/59.xbar_random.3575288315 Aug 29 02:43:02 PM UTC 24 Aug 29 02:43:11 PM UTC 24 64424723 ps
T2146 /workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/58.xbar_random_zero_delays.1759874565 Aug 29 02:42:13 PM UTC 24 Aug 29 02:43:16 PM UTC 24 580252520 ps
T2147 /workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/58.xbar_random.1402008813 Aug 29 02:42:11 PM UTC 24 Aug 29 02:43:21 PM UTC 24 1467940319 ps
T2148 /workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/58.xbar_smoke_slow_rsp.624109767 Aug 29 02:42:10 PM UTC 24 Aug 29 02:43:23 PM UTC 24 4907559997 ps
T2149 /workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/45.xbar_access_same_device_slow_rsp.3204001363 Aug 29 02:24:53 PM UTC 24 Aug 29 02:43:26 PM UTC 24 59964918007 ps
T2150 /workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/59.xbar_access_same_device.2151712580 Aug 29 02:43:09 PM UTC 24 Aug 29 02:43:32 PM UTC 24 128811504 ps
T2151 /workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/11.chip_same_csr_outstanding.842818547 Aug 29 01:21:20 PM UTC 24 Aug 29 02:43:35 PM UTC 24 27494378400 ps
T2152 /workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/58.xbar_smoke_large_delays.728169974 Aug 29 02:42:05 PM UTC 24 Aug 29 02:43:39 PM UTC 24 9918338466 ps
T2153 /workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/59.xbar_unmapped_addr.3564130066 Aug 29 02:43:18 PM UTC 24 Aug 29 02:43:39 PM UTC 24 268090180 ps
T2154 /workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/60.xbar_smoke.3744802479 Aug 29 02:43:36 PM UTC 24 Aug 29 02:43:46 PM UTC 24 166264552 ps
T2155 /workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/60.xbar_smoke_zero_delays.3761862828 Aug 29 02:43:42 PM UTC 24 Aug 29 02:43:52 PM UTC 24 42864990 ps
T2156 /workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/57.xbar_stress_all_with_reset_error.982523087 Aug 29 02:41:48 PM UTC 24 Aug 29 02:43:55 PM UTC 24 625630374 ps
T2157 /workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/59.xbar_random_slow_rsp.2891882198 Aug 29 02:43:08 PM UTC 24 Aug 29 02:43:57 PM UTC 24 3586238465 ps
T2158 /workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/59.xbar_random_zero_delays.2311866820 Aug 29 02:43:06 PM UTC 24 Aug 29 02:43:57 PM UTC 24 458082656 ps
T2159 /workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/58.xbar_stress_all_with_error.2940269269 Aug 29 02:42:33 PM UTC 24 Aug 29 02:43:58 PM UTC 24 2233910429 ps
T2160 /workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/59.xbar_same_source.27795005 Aug 29 02:43:16 PM UTC 24 Aug 29 02:44:01 PM UTC 24 526643122 ps
T2161 /workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/59.xbar_error_and_unmapped_addr.3192208730 Aug 29 02:43:18 PM UTC 24 Aug 29 02:44:04 PM UTC 24 969817613 ps
T2162 /workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/53.xbar_access_same_device_slow_rsp.3426784521 Aug 29 02:36:28 PM UTC 24 Aug 29 02:44:06 PM UTC 24 26394333336 ps
T2163 /workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/58.xbar_access_same_device.2261741570 Aug 29 02:42:19 PM UTC 24 Aug 29 02:44:08 PM UTC 24 2674012160 ps
T2164 /workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/59.xbar_error_random.2572924852 Aug 29 02:43:18 PM UTC 24 Aug 29 02:44:09 PM UTC 24 1507492233 ps
T2165 /workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/60.xbar_random.3962386374 Aug 29 02:43:53 PM UTC 24 Aug 29 02:44:15 PM UTC 24 173031939 ps
T2166 /workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/52.xbar_random_slow_rsp.1463892006 Aug 29 02:35:01 PM UTC 24 Aug 29 02:44:32 PM UTC 24 34788939108 ps
T2167 /workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/60.xbar_access_same_device.3708795094 Aug 29 02:44:07 PM UTC 24 Aug 29 02:44:35 PM UTC 24 440603385 ps
T2168 /workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/49.xbar_random_slow_rsp.2617393714 Aug 29 02:30:05 PM UTC 24 Aug 29 02:44:35 PM UTC 24 53994267262 ps
T2169 /workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/60.xbar_same_source.3703903758 Aug 29 02:44:16 PM UTC 24 Aug 29 02:44:36 PM UTC 24 151017202 ps
T2170 /workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/61.xbar_smoke.973604129 Aug 29 02:44:27 PM UTC 24 Aug 29 02:44:39 PM UTC 24 162617414 ps
T2171 /workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/60.xbar_random_zero_delays.3372503669 Aug 29 02:43:55 PM UTC 24 Aug 29 02:44:41 PM UTC 24 548389710 ps
T2172 /workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/55.xbar_stress_all_with_error.119061872 Aug 29 02:39:30 PM UTC 24 Aug 29 02:44:44 PM UTC 24 9056797606 ps
T2173 /workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/55.xbar_stress_all_with_reset_error.295149299 Aug 29 02:39:41 PM UTC 24 Aug 29 02:44:44 PM UTC 24 2562020827 ps
T2174 /workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/61.xbar_smoke_zero_delays.1684168129 Aug 29 02:44:35 PM UTC 24 Aug 29 02:44:45 PM UTC 24 52226070 ps
T2175 /workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/59.xbar_smoke_large_delays.3154081027 Aug 29 02:42:40 PM UTC 24 Aug 29 02:44:49 PM UTC 24 8199536732 ps
T2176 /workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/60.xbar_error_random.1434794684 Aug 29 02:44:16 PM UTC 24 Aug 29 02:44:50 PM UTC 24 293128525 ps
T2177 /workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/60.xbar_unmapped_addr.722699361 Aug 29 02:44:17 PM UTC 24 Aug 29 02:44:54 PM UTC 24 319319192 ps
T2178 /workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/56.xbar_stress_all.3956444159 Aug 29 02:40:28 PM UTC 24 Aug 29 02:45:00 PM UTC 24 6931847431 ps
T2179 /workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/59.xbar_smoke_slow_rsp.832744558 Aug 29 02:42:55 PM UTC 24 Aug 29 02:45:02 PM UTC 24 6192320500 ps
T2180 /workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/60.xbar_error_and_unmapped_addr.2019561340 Aug 29 02:44:16 PM UTC 24 Aug 29 02:45:04 PM UTC 24 961614138 ps
T2181 /workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/60.xbar_stress_all.1807865472 Aug 29 02:44:20 PM UTC 24 Aug 29 02:45:07 PM UTC 24 475907147 ps
T2182 /workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/57.xbar_stress_all.3350148080 Aug 29 02:41:39 PM UTC 24 Aug 29 02:45:17 PM UTC 24 2263214397 ps
T2183 /workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/60.xbar_smoke_slow_rsp.1024576361 Aug 29 02:43:47 PM UTC 24 Aug 29 02:45:18 PM UTC 24 5485593817 ps
T2184 /workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/61.xbar_unmapped_addr.2720704036 Aug 29 02:45:11 PM UTC 24 Aug 29 02:45:32 PM UTC 24 381795310 ps
T2185 /workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/60.xbar_smoke_large_delays.3764881364 Aug 29 02:43:43 PM UTC 24 Aug 29 02:45:45 PM UTC 24 10021973581 ps
T870 /workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/55.xbar_stress_all_with_rand_reset.2165121425 Aug 29 02:39:27 PM UTC 24 Aug 29 02:45:47 PM UTC 24 782310109 ps
T2186 /workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/61.xbar_random.2969029908 Aug 29 02:44:55 PM UTC 24 Aug 29 02:45:48 PM UTC 24 1756254648 ps
T2187 /workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/62.xbar_smoke_zero_delays.3902759503 Aug 29 02:45:39 PM UTC 24 Aug 29 02:45:48 PM UTC 24 57167822 ps
T2188 /workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/61.xbar_error_random.358873028 Aug 29 02:45:10 PM UTC 24 Aug 29 02:45:49 PM UTC 24 387273167 ps
T2189 /workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/61.xbar_error_and_unmapped_addr.4281623208 Aug 29 02:45:15 PM UTC 24 Aug 29 02:45:50 PM UTC 24 250683361 ps
T2190 /workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/62.xbar_smoke.2640299152 Aug 29 02:45:37 PM UTC 24 Aug 29 02:45:52 PM UTC 24 272759034 ps
T2191 /workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/56.xbar_stress_all_with_error.1929938516 Aug 29 02:40:35 PM UTC 24 Aug 29 02:45:59 PM UTC 24 8571617745 ps
T2192 /workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/61.xbar_random_zero_delays.4115870211 Aug 29 02:44:55 PM UTC 24 Aug 29 02:45:59 PM UTC 24 614240460 ps
T2193 /workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/62.xbar_random.1538904600 Aug 29 02:46:07 PM UTC 24 Aug 29 02:46:17 PM UTC 24 153669318 ps
T2194 /workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/48.xbar_access_same_device_slow_rsp.3478215972 Aug 29 02:28:29 PM UTC 24 Aug 29 02:46:17 PM UTC 24 67169302573 ps
T2195 /workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/48.xbar_random_large_delays.3740924089 Aug 29 02:28:27 PM UTC 24 Aug 29 02:46:21 PM UTC 24 86598882915 ps
T2196 /workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/61.xbar_smoke_slow_rsp.2485499057 Aug 29 02:44:56 PM UTC 24 Aug 29 02:46:22 PM UTC 24 3817292791 ps
T2197 /workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/59.xbar_stress_all_with_rand_reset.3329184635 Aug 29 02:43:24 PM UTC 24 Aug 29 02:46:25 PM UTC 24 1942969711 ps
T2198 /workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/61.xbar_same_source.2184052383 Aug 29 02:45:05 PM UTC 24 Aug 29 02:46:26 PM UTC 24 2257712448 ps
T2199 /workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/61.xbar_access_same_device.226054663 Aug 29 02:45:04 PM UTC 24 Aug 29 02:46:29 PM UTC 24 2285970380 ps
T2200 /workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/62.xbar_random_zero_delays.3826456945 Aug 29 02:46:09 PM UTC 24 Aug 29 02:46:30 PM UTC 24 174230227 ps
T2201 /workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/53.xbar_stress_all_with_rand_reset.1589871047 Aug 29 02:36:55 PM UTC 24 Aug 29 02:46:38 PM UTC 24 4486245429 ps
T2202 /workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/47.xbar_random_slow_rsp.1202091411 Aug 29 02:27:16 PM UTC 24 Aug 29 02:46:51 PM UTC 24 69354283372 ps
T2203 /workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/62.xbar_same_source.3973565932 Aug 29 02:46:19 PM UTC 24 Aug 29 02:46:59 PM UTC 24 591842574 ps
T2204 /workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/63.xbar_smoke_zero_delays.3949229256 Aug 29 02:46:50 PM UTC 24 Aug 29 02:46:59 PM UTC 24 51804166 ps
T2205 /workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/63.xbar_smoke.2957274282 Aug 29 02:46:48 PM UTC 24 Aug 29 02:47:01 PM UTC 24 229809215 ps
T2206 /workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/62.xbar_error_random.550558811 Aug 29 02:46:19 PM UTC 24 Aug 29 02:47:08 PM UTC 24 1701044734 ps
T2207 /workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/93.xbar_smoke.2084449375 Aug 29 03:20:20 PM UTC 24 Aug 29 03:20:29 PM UTC 24 162046392 ps
T2208 /workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/61.xbar_smoke_large_delays.2647945349 Aug 29 02:44:53 PM UTC 24 Aug 29 02:47:17 PM UTC 24 8832137715 ps
T2209 /workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/30.xbar_access_same_device_slow_rsp.2309235848 Aug 29 02:01:49 PM UTC 24 Aug 29 02:47:29 PM UTC 24 174536293980 ps
T2210 /workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/62.xbar_access_same_device.979607350 Aug 29 02:46:11 PM UTC 24 Aug 29 02:47:29 PM UTC 24 1123253152 ps
T2211 /workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/62.xbar_error_and_unmapped_addr.1155119720 Aug 29 02:46:36 PM UTC 24 Aug 29 02:47:32 PM UTC 24 1105453453 ps
T651 /workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/54.xbar_stress_all_with_reset_error.3340415249 Aug 29 02:38:26 PM UTC 24 Aug 29 02:47:33 PM UTC 24 14969152777 ps
T2212 /workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/62.xbar_smoke_large_delays.1301000022 Aug 29 02:45:53 PM UTC 24 Aug 29 02:47:37 PM UTC 24 6601381381 ps
T2213 /workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/63.xbar_random.3187791756 Aug 29 02:47:19 PM UTC 24 Aug 29 02:47:39 PM UTC 24 606138057 ps
T2214 /workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/57.xbar_random_slow_rsp.2801745573 Aug 29 02:41:12 PM UTC 24 Aug 29 02:47:40 PM UTC 24 23391104881 ps
T2215 /workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/62.xbar_unmapped_addr.4264056165 Aug 29 02:46:36 PM UTC 24 Aug 29 02:47:41 PM UTC 24 1131527510 ps
T2216 /workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/61.xbar_stress_all_with_error.2285848147 Aug 29 02:45:25 PM UTC 24 Aug 29 02:47:43 PM UTC 24 4727916420 ps
T2217 /workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/61.xbar_stress_all_with_reset_error.3147298358 Aug 29 02:45:24 PM UTC 24 Aug 29 02:47:45 PM UTC 24 396626026 ps
T2218 /workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/63.xbar_random_zero_delays.3841795364 Aug 29 02:47:21 PM UTC 24 Aug 29 02:47:51 PM UTC 24 297730143 ps
T2219 /workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/62.xbar_smoke_slow_rsp.3245452530 Aug 29 02:46:05 PM UTC 24 Aug 29 02:47:57 PM UTC 24 5324397318 ps
T2220 /workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/63.xbar_same_source.730859205 Aug 29 02:47:49 PM UTC 24 Aug 29 02:48:04 PM UTC 24 257327517 ps
T2221 /workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/63.xbar_error_random.1036970247 Aug 29 02:47:53 PM UTC 24 Aug 29 02:48:06 PM UTC 24 132277968 ps
T2222 /workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/63.xbar_error_and_unmapped_addr.3146596881 Aug 29 02:47:59 PM UTC 24 Aug 29 02:48:13 PM UTC 24 184896167 ps
T2223 /workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/63.xbar_unmapped_addr.1154474672 Aug 29 02:47:55 PM UTC 24 Aug 29 02:48:16 PM UTC 24 293866621 ps
T2224 /workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/64.xbar_smoke.393691466 Aug 29 02:48:06 PM UTC 24 Aug 29 02:48:19 PM UTC 24 184892518 ps
T2225 /workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/64.xbar_smoke_zero_delays.3667260894 Aug 29 02:48:12 PM UTC 24 Aug 29 02:48:23 PM UTC 24 57919847 ps
T2226 /workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/61.xbar_random_slow_rsp.3401656093 Aug 29 02:45:02 PM UTC 24 Aug 29 02:48:23 PM UTC 24 11710813489 ps
T2227 /workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/60.xbar_random_slow_rsp.2154923569 Aug 29 02:43:59 PM UTC 24 Aug 29 02:48:26 PM UTC 24 17779600339 ps
T2228 /workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/63.xbar_smoke_slow_rsp.3496696701 Aug 29 02:47:12 PM UTC 24 Aug 29 02:48:28 PM UTC 24 4961152699 ps
T2229 /workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/63.xbar_access_same_device.1751025957 Aug 29 02:47:37 PM UTC 24 Aug 29 02:48:42 PM UTC 24 796969160 ps
T2230 /workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/61.xbar_random_large_delays.2289985307 Aug 29 02:44:55 PM UTC 24 Aug 29 02:48:45 PM UTC 24 19332106935 ps
T2231 /workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/59.xbar_random_large_delays.1817993211 Aug 29 02:43:09 PM UTC 24 Aug 29 02:48:47 PM UTC 24 24716190062 ps
T2232 /workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/60.xbar_stress_all_with_reset_error.680469285 Aug 29 02:44:29 PM UTC 24 Aug 29 02:48:53 PM UTC 24 3898611661 ps
T2233 /workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/63.xbar_smoke_large_delays.2729041081 Aug 29 02:46:58 PM UTC 24 Aug 29 02:48:56 PM UTC 24 8553424761 ps
T2234 /workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/64.xbar_same_source.3094495907 Aug 29 02:48:46 PM UTC 24 Aug 29 02:48:56 PM UTC 24 34441088 ps
T2235 /workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/62.xbar_stress_all.2167006229 Aug 29 02:46:41 PM UTC 24 Aug 29 02:48:57 PM UTC 24 4519049615 ps
T2236 /workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/64.xbar_unmapped_addr.948875375 Aug 29 02:49:02 PM UTC 24 Aug 29 02:49:12 PM UTC 24 24686704 ps
T2237 /workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/61.xbar_stress_all.4286768465 Aug 29 02:45:21 PM UTC 24 Aug 29 02:49:25 PM UTC 24 3096810682 ps
T2238 /workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/65.xbar_smoke.2378821705 Aug 29 02:49:18 PM UTC 24 Aug 29 02:49:28 PM UTC 24 46512416 ps
T2239 /workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/64.xbar_random.376190080 Aug 29 02:48:27 PM UTC 24 Aug 29 02:49:30 PM UTC 24 1380247221 ps
T2240 /workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/64.xbar_random_zero_delays.1719711170 Aug 29 02:48:35 PM UTC 24 Aug 29 02:49:32 PM UTC 24 525580629 ps
T2241 /workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/59.xbar_stress_all.1588522151 Aug 29 02:43:19 PM UTC 24 Aug 29 02:49:38 PM UTC 24 9403217968 ps
T2242 /workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/64.xbar_smoke_large_delays.2574864602 Aug 29 02:48:15 PM UTC 24 Aug 29 02:49:40 PM UTC 24 7236991604 ps
T2243 /workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/64.xbar_access_same_device.1075465512 Aug 29 02:48:44 PM UTC 24 Aug 29 02:49:40 PM UTC 24 928177984 ps
T2244 /workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/58.xbar_stress_all_with_rand_reset.4178165611 Aug 29 02:42:31 PM UTC 24 Aug 29 02:49:40 PM UTC 24 3681444544 ps
T2245 /workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/59.xbar_stress_all_with_error.172778930 Aug 29 02:43:26 PM UTC 24 Aug 29 02:49:42 PM UTC 24 8372883123 ps
T2246 /workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/65.xbar_smoke_zero_delays.1103515310 Aug 29 02:49:32 PM UTC 24 Aug 29 02:49:43 PM UTC 24 53320814 ps
T2247 /workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/64.xbar_error_and_unmapped_addr.2593445328 Aug 29 02:49:05 PM UTC 24 Aug 29 02:49:45 PM UTC 24 261043991 ps
T2248 /workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/64.xbar_smoke_slow_rsp.2532468747 Aug 29 02:48:24 PM UTC 24 Aug 29 02:50:01 PM UTC 24 5495139171 ps
T2249 /workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/64.xbar_stress_all_with_error.1264076435 Aug 29 02:49:17 PM UTC 24 Aug 29 02:50:01 PM UTC 24 884453021 ps
T2250 /workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/64.xbar_error_random.2697481981 Aug 29 02:48:49 PM UTC 24 Aug 29 02:50:03 PM UTC 24 2163039684 ps
T481 /workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/57.xbar_stress_all_with_rand_reset.3004357097 Aug 29 02:41:46 PM UTC 24 Aug 29 02:50:03 PM UTC 24 4991903163 ps
T2251 /workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/55.xbar_random_slow_rsp.3383095259 Aug 29 02:38:41 PM UTC 24 Aug 29 02:50:11 PM UTC 24 47634481579 ps
T2252 /workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/64.xbar_stress_all_with_rand_reset.4084749730 Aug 29 02:49:14 PM UTC 24 Aug 29 02:50:23 PM UTC 24 166484932 ps
T2253 /workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/60.xbar_stress_all_with_rand_reset.2714928640 Aug 29 02:44:26 PM UTC 24 Aug 29 02:50:26 PM UTC 24 2812117350 ps
T2254 /workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/58.xbar_stress_all.3119673523 Aug 29 02:42:34 PM UTC 24 Aug 29 02:50:28 PM UTC 24 13067778642 ps
T2255 /workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/64.xbar_stress_all_with_reset_error.428798356 Aug 29 02:49:17 PM UTC 24 Aug 29 02:50:30 PM UTC 24 144960149 ps
T2256 /workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/65.xbar_error_random.2008494824 Aug 29 02:50:01 PM UTC 24 Aug 29 02:50:30 PM UTC 24 269729819 ps
T2257 /workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/46.xbar_access_same_device_slow_rsp.3698621169 Aug 29 02:26:01 PM UTC 24 Aug 29 02:50:34 PM UTC 24 96930041040 ps
T2258 /workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/51.xbar_random_slow_rsp.948600811 Aug 29 02:33:30 PM UTC 24 Aug 29 02:50:35 PM UTC 24 61428075300 ps
T2259 /workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/65.xbar_random_zero_delays.1022376115 Aug 29 02:49:52 PM UTC 24 Aug 29 02:50:42 PM UTC 24 470587579 ps
T2260 /workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/62.xbar_random_large_delays.2978372617 Aug 29 02:46:09 PM UTC 24 Aug 29 02:50:49 PM UTC 24 25333406777 ps
T2261 /workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/65.xbar_random.356347200 Aug 29 02:49:51 PM UTC 24 Aug 29 02:50:50 PM UTC 24 1618507005 ps
T2262 /workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/66.xbar_smoke.80276747 Aug 29 02:50:43 PM UTC 24 Aug 29 02:50:52 PM UTC 24 37893609 ps
T2263 /workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/65.xbar_unmapped_addr.2355215893 Aug 29 02:50:05 PM UTC 24 Aug 29 02:50:53 PM UTC 24 1185587721 ps
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