| T118 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_pwrmgr_random_sleep_all_wake_ups.46981281 |
|
|
Aug 29 06:25:03 PM UTC 24 |
Aug 29 06:59:14 PM UTC 24 |
21554417412 ps |
| T46 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_spi_host_tx_rx.1545960236 |
|
|
Aug 29 06:53:19 PM UTC 24 |
Aug 29 06:59:19 PM UTC 24 |
2580400378 ps |
| T79 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_spi_device_pinmux_sleep_retention.1834819635 |
|
|
Aug 29 06:53:19 PM UTC 24 |
Aug 29 06:59:34 PM UTC 24 |
3271743940 ps |
| T1072 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_uart_rand_baudrate.4149005633 |
|
|
Aug 29 06:51:01 PM UTC 24 |
Aug 29 06:59:35 PM UTC 24 |
3197807762 ps |
| T352 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_uart_tx_rx_idx2.3418057694 |
|
|
Aug 29 06:50:21 PM UTC 24 |
Aug 29 06:59:52 PM UTC 24 |
4031341046 ps |
| T685 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_all_escalation_resets.1647303945 |
|
|
Aug 29 06:47:15 PM UTC 24 |
Aug 29 07:00:36 PM UTC 24 |
5547390468 ps |
| T1073 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_uart_tx_rx_idx3.3960755242 |
|
|
Aug 29 06:50:19 PM UTC 24 |
Aug 29 07:00:49 PM UTC 24 |
4481496040 ps |
| T355 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_i2c_device_tx_rx.2232433222 |
|
|
Aug 29 06:53:10 PM UTC 24 |
Aug 29 07:00:59 PM UTC 24 |
3206542476 ps |
| T1074 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_csrng_edn_concurrency_reduced_freq.3573152013 |
|
|
Aug 29 06:33:38 PM UTC 24 |
Aug 29 07:01:12 PM UTC 24 |
9551137661 ps |
| T292 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_data_integrity_escalation.2047745490 |
|
|
Aug 29 06:47:18 PM UTC 24 |
Aug 29 07:01:19 PM UTC 24 |
5727872120 ps |
| T430 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_pwrmgr_deep_sleep_all_wake_ups.157508871 |
|
|
Aug 29 06:24:24 PM UTC 24 |
Aug 29 07:01:42 PM UTC 24 |
23662540064 ps |
| T1075 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_keymgr_key_derivation_jitter_en_reduced_freq.1820734694 |
|
|
Aug 29 06:31:34 PM UTC 24 |
Aug 29 07:01:52 PM UTC 24 |
11589025433 ps |
| T1076 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_uart_tx_rx_idx1.998050001 |
|
|
Aug 29 06:50:11 PM UTC 24 |
Aug 29 07:02:08 PM UTC 24 |
4771245368 ps |
| T1077 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_uart_tx_rx.492163428 |
|
|
Aug 29 06:50:21 PM UTC 24 |
Aug 29 07:02:36 PM UTC 24 |
4576935604 ps |
| T42 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_gpio.2763653414 |
|
|
Aug 29 06:54:04 PM UTC 24 |
Aug 29 07:02:55 PM UTC 24 |
4262897208 ps |
| T125 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_power_virus.739259160 |
|
|
Aug 29 06:37:11 PM UTC 24 |
Aug 29 07:03:12 PM UTC 24 |
6042256024 ps |
| T256 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_flash_init_reduced_freq.2549061137 |
|
|
Aug 29 06:32:00 PM UTC 24 |
Aug 29 07:03:38 PM UTC 24 |
20653007963 ps |
| T1078 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_flash_ctrl_lc_rw_en.960145240 |
|
|
Aug 29 06:56:58 PM UTC 24 |
Aug 29 07:05:06 PM UTC 24 |
3800378880 ps |
| T1079 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_uart_tx_rx_alt_clk_freq.1811858794 |
|
|
Aug 29 06:52:19 PM UTC 24 |
Aug 29 07:05:10 PM UTC 24 |
4610178190 ps |
| T225 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_spi_device_pass_through_collision.3765196335 |
|
|
Aug 29 06:53:50 PM UTC 24 |
Aug 29 07:05:42 PM UTC 24 |
4272292020 ps |
| T1080 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_lc_ctrl_otp_hw_cfg0.1445998675 |
|
|
Aug 29 07:00:30 PM UTC 24 |
Aug 29 07:05:44 PM UTC 24 |
2946870788 ps |
| T1081 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_kmac_entropy.837526583 |
|
|
Aug 29 07:00:27 PM UTC 24 |
Aug 29 07:05:45 PM UTC 24 |
3158649610 ps |
| T1082 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_flash_ctrl_idle_low_power.2625809399 |
|
|
Aug 29 06:59:53 PM UTC 24 |
Aug 29 07:05:49 PM UTC 24 |
3080900394 ps |
| T1083 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_flash_ctrl_ops.2623107910 |
|
|
Aug 29 06:54:07 PM UTC 24 |
Aug 29 07:06:18 PM UTC 24 |
3465105752 ps |
| T1084 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_lc_ctrl_rand_to_scrap.2770317707 |
|
|
Aug 29 07:02:41 PM UTC 24 |
Aug 29 07:06:33 PM UTC 24 |
2954151275 ps |
| T1085 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_lc_ctrl_volatile_raw_unlock.2527738805 |
|
|
Aug 29 07:04:11 PM UTC 24 |
Aug 29 07:07:00 PM UTC 24 |
2429322558 ps |
| T347 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_i2c_host_tx_rx.1687859656 |
|
|
Aug 29 06:53:11 PM UTC 24 |
Aug 29 07:07:01 PM UTC 24 |
4704378882 ps |
| T1086 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_i2c_host_tx_rx_idx2.709807919 |
|
|
Aug 29 06:53:15 PM UTC 24 |
Aug 29 07:07:07 PM UTC 24 |
4420592636 ps |
| T187 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_otp_ctrl_vendor_test_csr_access.4089972460 |
|
|
Aug 29 07:02:01 PM UTC 24 |
Aug 29 07:07:22 PM UTC 24 |
3110905303 ps |
| T353 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_i2c_host_tx_rx_idx1.3408613495 |
|
|
Aug 29 06:53:14 PM UTC 24 |
Aug 29 07:07:55 PM UTC 24 |
5186100458 ps |
| T1087 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz.424766793 |
|
|
Aug 29 07:05:50 PM UTC 24 |
Aug 29 07:08:03 PM UTC 24 |
1892102846 ps |
| T1088 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_otbn_ecdsa_op_irq.1608102349 |
|
|
Aug 29 05:54:21 PM UTC 24 |
Aug 29 07:08:08 PM UTC 24 |
16546930508 ps |
| T360 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_flash_ctrl_ops_jitter_en.1861368302 |
|
|
Aug 29 06:56:05 PM UTC 24 |
Aug 29 07:08:31 PM UTC 24 |
3659886608 ps |
| T226 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_spi_device_pass_through.1570538453 |
|
|
Aug 29 06:53:14 PM UTC 24 |
Aug 29 07:08:32 PM UTC 24 |
7245703209 ps |
| T1089 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_otp_ctrl_ecc_error_vendor_test.3962928324 |
|
|
Aug 29 07:02:23 PM UTC 24 |
Aug 29 07:08:42 PM UTC 24 |
2634539514 ps |
| T1090 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_sleep_pwm_pulses.2871221328 |
|
|
Aug 29 06:48:48 PM UTC 24 |
Aug 29 07:08:44 PM UTC 24 |
8452034102 ps |
| T1091 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_rstmgr_sw_rst.2463072049 |
|
|
Aug 29 07:06:51 PM UTC 24 |
Aug 29 07:10:50 PM UTC 24 |
2651062370 ps |
| T1092 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_uart_tx_rx_alt_clk_freq_low_speed.1486242567 |
|
|
Aug 29 06:52:55 PM UTC 24 |
Aug 29 07:11:02 PM UTC 24 |
7871950861 ps |
| T253 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_keymgr_sideload_otbn.1016402074 |
|
|
Aug 29 06:08:38 PM UTC 24 |
Aug 29 07:12:00 PM UTC 24 |
13106953616 ps |
| T1093 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_otbn_ecdsa_op_irq_jitter_en.1020727794 |
|
|
Aug 29 05:54:24 PM UTC 24 |
Aug 29 07:12:24 PM UTC 24 |
18464018079 ps |
| T1094 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_otp_ctrl_lc_signals_test_unlocked0.3560683469 |
|
|
Aug 29 07:01:29 PM UTC 24 |
Aug 29 07:13:19 PM UTC 24 |
5207082236 ps |
| T1095 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_rstmgr_sw_req.4289495887 |
|
|
Aug 29 07:06:54 PM UTC 24 |
Aug 29 07:13:32 PM UTC 24 |
3459978846 ps |
| T654 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_pwrmgr_sleep_disabled.1011721188 |
|
|
Aug 29 07:10:27 PM UTC 24 |
Aug 29 07:14:18 PM UTC 24 |
3124762070 ps |
| T1096 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_pwrmgr_main_power_glitch_reset.553869358 |
|
|
Aug 29 07:08:10 PM UTC 24 |
Aug 29 07:14:22 PM UTC 24 |
3945179853 ps |
| T1097 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_flash_ctrl_access.3766345274 |
|
|
Aug 29 06:58:24 PM UTC 24 |
Aug 29 07:14:46 PM UTC 24 |
5602891244 ps |
| T1098 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_pwrmgr_deep_sleep_power_glitch_reset.4284145136 |
|
|
Aug 29 07:09:40 PM UTC 24 |
Aug 29 07:16:55 PM UTC 24 |
7248506152 ps |
| T1099 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_rv_timer_irq.3892694059 |
|
|
Aug 29 07:11:37 PM UTC 24 |
Aug 29 07:17:03 PM UTC 24 |
2694387600 ps |
| T1100 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_flash_ctrl_access_jitter_en.3378800747 |
|
|
Aug 29 06:59:53 PM UTC 24 |
Aug 29 07:17:41 PM UTC 24 |
6391124724 ps |
| T1101 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_sysrst_ctrl_inputs.3650632614 |
|
|
Aug 29 07:12:56 PM UTC 24 |
Aug 29 07:18:13 PM UTC 24 |
3264946584 ps |
| T1102 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/default/0.rom_e2e_self_hash.1397433579 |
|
|
Aug 29 04:55:38 PM UTC 24 |
Aug 29 07:18:15 PM UTC 24 |
26295931600 ps |
| T1103 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_pwrmgr_usb_clk_disabled_when_active.3130028117 |
|
|
Aug 29 07:11:33 PM UTC 24 |
Aug 29 07:18:42 PM UTC 24 |
5500198216 ps |
| T1104 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_pwrmgr_deep_sleep_por_reset.3179691892 |
|
|
Aug 29 07:09:30 PM UTC 24 |
Aug 29 07:18:45 PM UTC 24 |
6786269380 ps |
| T1105 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_flash_ctrl_clock_freqs.3646097216 |
|
|
Aug 29 07:00:25 PM UTC 24 |
Aug 29 07:18:48 PM UTC 24 |
5978930433 ps |
| T1106 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_pwrmgr_full_aon_reset.3458301973 |
|
|
Aug 29 07:07:13 PM UTC 24 |
Aug 29 07:18:50 PM UTC 24 |
9474259248 ps |
| T283 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_rstmgr_cpu_info.752145171 |
|
|
Aug 29 07:07:11 PM UTC 24 |
Aug 29 07:19:02 PM UTC 24 |
6799957786 ps |
| T48 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_sysrst_ctrl_ulp_z3_wakeup.3979665555 |
|
|
Aug 29 07:14:08 PM UTC 24 |
Aug 29 07:20:38 PM UTC 24 |
6251165672 ps |
| T210 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_flash_rma_unlocked.249769691 |
|
|
Aug 29 05:38:43 PM UTC 24 |
Aug 29 07:20:52 PM UTC 24 |
45151058051 ps |
| T1107 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_pwrmgr_normal_sleep_por_reset.1327947110 |
|
|
Aug 29 07:09:40 PM UTC 24 |
Aug 29 07:21:29 PM UTC 24 |
6353611992 ps |
| T1108 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_sysrst_ctrl_outputs.2544912176 |
|
|
Aug 29 07:15:24 PM UTC 24 |
Aug 29 07:21:32 PM UTC 24 |
3883155668 ps |
| T1109 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_otp_ctrl_lc_signals_rma.1435943462 |
|
|
Aug 29 07:02:00 PM UTC 24 |
Aug 29 07:22:03 PM UTC 24 |
8179005094 ps |
| T1110 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_lc_walkthrough_prodend.2246276104 |
|
|
Aug 29 07:03:45 PM UTC 24 |
Aug 29 07:22:36 PM UTC 24 |
8250559008 ps |
| T1111 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_lc_ctrl_transition.4051572918 |
|
|
Aug 29 07:02:27 PM UTC 24 |
Aug 29 07:22:47 PM UTC 24 |
10941238447 ps |
| T1112 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_sysrst_ctrl_in_irq.3980853596 |
|
|
Aug 29 07:14:03 PM UTC 24 |
Aug 29 07:23:13 PM UTC 24 |
4011569388 ps |
| T1113 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_aon_timer_irq.1140726257 |
|
|
Aug 29 07:15:25 PM UTC 24 |
Aug 29 07:23:34 PM UTC 24 |
4368172872 ps |
| T1114 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_otp_ctrl_lc_signals_prod.2766961453 |
|
|
Aug 29 07:01:55 PM UTC 24 |
Aug 29 07:24:44 PM UTC 24 |
8166950360 ps |
| T1115 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_aes_enc_jitter_en.2897965704 |
|
|
Aug 29 07:21:26 PM UTC 24 |
Aug 29 07:25:15 PM UTC 24 |
2526272062 ps |
| T1116 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_pwrmgr_sysrst_ctrl_reset.562940480 |
|
|
Aug 29 07:08:07 PM UTC 24 |
Aug 29 07:25:42 PM UTC 24 |
6218382592 ps |
| T1117 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_otp_ctrl_lc_signals_dev.2081311158 |
|
|
Aug 29 07:01:34 PM UTC 24 |
Aug 29 07:26:04 PM UTC 24 |
8896514578 ps |
| T1118 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_aon_timer_sleep_wdog_sleep_pause.3222098109 |
|
|
Aug 29 07:16:52 PM UTC 24 |
Aug 29 07:26:12 PM UTC 24 |
7614816588 ps |
| T1119 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_aes_idle.3874700944 |
|
|
Aug 29 07:22:15 PM UTC 24 |
Aug 29 07:26:56 PM UTC 24 |
2402196660 ps |
| T1120 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_aes_enc.2995011734 |
|
|
Aug 29 07:21:12 PM UTC 24 |
Aug 29 07:27:31 PM UTC 24 |
3237954660 ps |
| T75 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_alert_test.4086325676 |
|
|
Aug 29 07:22:38 PM UTC 24 |
Aug 29 07:28:27 PM UTC 24 |
2787013108 ps |
| T1121 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_otbn_mem_scramble.1292760615 |
|
|
Aug 29 07:20:01 PM UTC 24 |
Aug 29 07:28:30 PM UTC 24 |
3791430856 ps |
| T1122 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_otbn_smoketest.382644399 |
|
|
Aug 29 06:41:03 PM UTC 24 |
Aug 29 07:28:45 PM UTC 24 |
11097059578 ps |
| T1123 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_aon_timer_wdog_lc_escalate.1437979791 |
|
|
Aug 29 07:18:15 PM UTC 24 |
Aug 29 07:29:18 PM UTC 24 |
5649557036 ps |
| T1124 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_aes_masking_off.1769872287 |
|
|
Aug 29 07:22:15 PM UTC 24 |
Aug 29 07:29:35 PM UTC 24 |
3452215938 ps |
| T1125 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_pwrmgr_all_reset_reqs.1428921235 |
|
|
Aug 29 07:08:05 PM UTC 24 |
Aug 29 07:30:36 PM UTC 24 |
9445057168 ps |
| T1126 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_adc_ctrl_sleep_debug_cable_wakeup.1344216683 |
|
|
Aug 29 07:18:57 PM UTC 24 |
Aug 29 07:30:48 PM UTC 24 |
20160509934 ps |
| T1127 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_pwrmgr_wdog_reset.4108201497 |
|
|
Aug 29 07:17:41 PM UTC 24 |
Aug 29 07:30:55 PM UTC 24 |
4521480616 ps |
| T1128 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_pwrmgr_deep_sleep_all_reset_reqs.3685328440 |
|
|
Aug 29 07:08:52 PM UTC 24 |
Aug 29 07:31:15 PM UTC 24 |
12077341471 ps |
| T1129 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/default/1.rom_e2e_asm_init_test_unlocked0.3980757268 |
|
|
Aug 29 06:36:30 PM UTC 24 |
Aug 29 07:31:18 PM UTC 24 |
11615255223 ps |
| T1130 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_aes_entropy.2311247654 |
|
|
Aug 29 07:27:28 PM UTC 24 |
Aug 29 07:31:49 PM UTC 24 |
2911190920 ps |
| T1131 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_entropy_src_kat_test.495923142 |
|
|
Aug 29 07:28:04 PM UTC 24 |
Aug 29 07:32:10 PM UTC 24 |
3181512054 ps |
| T710 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_alert_handler_lpg_sleep_mode_alerts.1788971835 |
|
|
Aug 29 07:25:18 PM UTC 24 |
Aug 29 07:32:48 PM UTC 24 |
3465734376 ps |
| T1132 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_alert_handler_entropy.4259641149 |
|
|
Aug 29 07:26:50 PM UTC 24 |
Aug 29 07:33:06 PM UTC 24 |
3471567535 ps |
| T262 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_flash_init.3199835600 |
|
|
Aug 29 06:59:47 PM UTC 24 |
Aug 29 07:33:24 PM UTC 24 |
22928107200 ps |
| T1133 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_alert_handler_escalation.367855623 |
|
|
Aug 29 07:23:20 PM UTC 24 |
Aug 29 07:33:32 PM UTC 24 |
4492550752 ps |
| T1134 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_aon_timer_wdog_bite_reset.3498070204 |
|
|
Aug 29 07:17:39 PM UTC 24 |
Aug 29 07:33:35 PM UTC 24 |
8839512056 ps |
| T1135 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_pwrmgr_normal_sleep_all_reset_reqs.1592507195 |
|
|
Aug 29 07:09:32 PM UTC 24 |
Aug 29 07:33:47 PM UTC 24 |
13077954884 ps |
| T452 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_rv_core_ibex_nmi_irq.4112741650 |
|
|
Aug 29 07:19:55 PM UTC 24 |
Aug 29 07:34:17 PM UTC 24 |
4970947284 ps |
| T257 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_lc_walkthrough_rma.2861610616 |
|
|
Aug 29 05:45:59 PM UTC 24 |
Aug 29 07:34:25 PM UTC 24 |
47433090095 ps |
| T1136 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_alert_handler_ping_timeout.2017427856 |
|
|
Aug 29 07:23:23 PM UTC 24 |
Aug 29 07:34:30 PM UTC 24 |
5303478612 ps |
| T1137 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_otbn_randomness.4251173369 |
|
|
Aug 29 07:18:58 PM UTC 24 |
Aug 29 07:35:00 PM UTC 24 |
5948061488 ps |
| T1138 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_entropy_src_ast_rng_req.3338664335 |
|
|
Aug 29 07:31:59 PM UTC 24 |
Aug 29 07:36:20 PM UTC 24 |
3136344868 ps |
| T349 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_rstmgr_alert_info.3269277254 |
|
|
Aug 29 07:07:12 PM UTC 24 |
Aug 29 07:36:45 PM UTC 24 |
14664593880 ps |
| T1139 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_csrng_kat_test.2054841008 |
|
|
Aug 29 07:31:43 PM UTC 24 |
Aug 29 07:37:05 PM UTC 24 |
2870431544 ps |
| T1140 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_hmac_enc_idle.3924318712 |
|
|
Aug 29 07:34:25 PM UTC 24 |
Aug 29 07:37:31 PM UTC 24 |
2354130820 ps |
| T1141 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_hmac_enc_jitter_en.1978489681 |
|
|
Aug 29 07:33:37 PM UTC 24 |
Aug 29 07:37:31 PM UTC 24 |
2361147279 ps |
| T1142 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_rv_core_ibex_rnd.1968363775 |
|
|
Aug 29 07:19:56 PM UTC 24 |
Aug 29 07:37:59 PM UTC 24 |
5530759756 ps |
| T1143 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_lc_walkthrough_prod.4044283420 |
|
|
Aug 29 05:43:35 PM UTC 24 |
Aug 29 07:38:38 PM UTC 24 |
46303190412 ps |
| T631 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_edn_boot_mode.2064568721 |
|
|
Aug 29 07:29:26 PM UTC 24 |
Aug 29 07:38:51 PM UTC 24 |
3146785838 ps |
| T1144 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_hmac_enc.1194342072 |
|
|
Aug 29 07:33:22 PM UTC 24 |
Aug 29 07:39:52 PM UTC 24 |
3433450836 ps |
| T1145 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_csrng_fuse_en_sw_app_read_test.3994916717 |
|
|
Aug 29 07:31:44 PM UTC 24 |
Aug 29 07:40:06 PM UTC 24 |
4081631216 ps |
| T1146 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_kmac_mode_cshake.2792496287 |
|
|
Aug 29 07:37:18 PM UTC 24 |
Aug 29 07:40:48 PM UTC 24 |
2662322888 ps |
| T1147 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_lc_walkthrough_dev.3941786803 |
|
|
Aug 29 05:43:34 PM UTC 24 |
Aug 29 07:41:05 PM UTC 24 |
48764831873 ps |
| T1148 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_edn_kat.4178617069 |
|
|
Aug 29 07:29:26 PM UTC 24 |
Aug 29 07:41:13 PM UTC 24 |
3663474154 ps |
| T1149 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_hmac_oneshot.2268254672 |
|
|
Aug 29 07:34:33 PM UTC 24 |
Aug 29 07:41:14 PM UTC 24 |
3366507606 ps |
| T1150 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_kmac_mode_kmac.2131446453 |
|
|
Aug 29 07:37:40 PM UTC 24 |
Aug 29 07:42:39 PM UTC 24 |
3278229716 ps |
| T1151 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_kmac_idle.2080604773 |
|
|
Aug 29 07:38:32 PM UTC 24 |
Aug 29 07:42:49 PM UTC 24 |
2937707724 ps |
| T1152 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_csrng_lc_hw_debug_en_test.2251322699 |
|
|
Aug 29 07:30:09 PM UTC 24 |
Aug 29 07:43:22 PM UTC 24 |
7732768504 ps |
| T1153 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_sysrst_ctrl_reset.1104874406 |
|
|
Aug 29 07:15:28 PM UTC 24 |
Aug 29 07:43:29 PM UTC 24 |
23665889304 ps |
| T688 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_alert_handler_lpg_sleep_mode_pings.2855708158 |
|
|
Aug 29 07:25:50 PM UTC 24 |
Aug 29 07:43:31 PM UTC 24 |
9401016568 ps |
| T1154 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_kmac_app_rom.1586985140 |
|
|
Aug 29 07:38:14 PM UTC 24 |
Aug 29 07:44:03 PM UTC 24 |
2622124248 ps |
| T1155 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_kmac_mode_kmac_jitter_en.3207828798 |
|
|
Aug 29 07:38:14 PM UTC 24 |
Aug 29 07:44:37 PM UTC 24 |
3173138301 ps |
| T365 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_sensor_ctrl_status.2331751082 |
|
|
Aug 29 07:42:02 PM UTC 24 |
Aug 29 07:45:51 PM UTC 24 |
2888706169 ps |
| T1156 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_alert_handler_lpg_reset_toggle.2215601890 |
|
|
Aug 29 07:26:49 PM UTC 24 |
Aug 29 07:47:46 PM UTC 24 |
6291166892 ps |
| T1157 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_edn_entropy_reqs.3253946767 |
|
|
Aug 29 07:32:26 PM UTC 24 |
Aug 29 07:48:38 PM UTC 24 |
6341175588 ps |
| T1158 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_lc_walkthrough_testunlocks.3958055013 |
|
|
Aug 29 07:06:40 PM UTC 24 |
Aug 29 07:49:07 PM UTC 24 |
29162292104 ps |
| T1159 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_sram_ctrl_scrambled_access.994908975 |
|
|
Aug 29 07:39:26 PM UTC 24 |
Aug 29 07:49:51 PM UTC 24 |
5302476448 ps |
| T1160 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_alert_handler_ping_ok.2806911260 |
|
|
Aug 29 07:23:46 PM UTC 24 |
Aug 29 07:49:54 PM UTC 24 |
8844692544 ps |
| T1161 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_rom_ctrl_integrity_check.2198270663 |
|
|
Aug 29 07:39:12 PM UTC 24 |
Aug 29 07:50:21 PM UTC 24 |
8980883054 ps |
| T322 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_plic_sw_irq.87945244 |
|
|
Aug 29 07:44:36 PM UTC 24 |
Aug 29 07:50:24 PM UTC 24 |
3148038232 ps |
| T1162 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/default/1.rom_e2e_shutdown_exception_c.1591056376 |
|
|
Aug 29 06:35:56 PM UTC 24 |
Aug 29 07:52:02 PM UTC 24 |
14748370692 ps |
| T1163 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_sleep_sram_ret_contents_scramble.3525475463 |
|
|
Aug 29 07:41:59 PM UTC 24 |
Aug 29 07:52:38 PM UTC 24 |
6008977328 ps |
| T167 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup.4169552069 |
|
|
Aug 29 07:43:20 PM UTC 24 |
Aug 29 07:53:09 PM UTC 24 |
5608140818 ps |
| T252 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_keymgr_sideload_aes.964569803 |
|
|
Aug 29 07:35:34 PM UTC 24 |
Aug 29 07:53:41 PM UTC 24 |
6974199640 ps |
| T1164 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_sram_ctrl_scrambled_access_jitter_en.3267890859 |
|
|
Aug 29 07:40:26 PM UTC 24 |
Aug 29 07:54:06 PM UTC 24 |
5188037800 ps |
| T1165 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_edn_entropy_reqs_jitter.464423589 |
|
|
Aug 29 07:32:43 PM UTC 24 |
Aug 29 07:54:08 PM UTC 24 |
6705396989 ps |
| T321 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_sram_ctrl_execution_main.3803446163 |
|
|
Aug 29 07:40:39 PM UTC 24 |
Aug 29 07:54:14 PM UTC 24 |
8660797558 ps |
| T1166 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_clkmgr_off_aes_trans.2672139975 |
|
|
Aug 29 07:46:25 PM UTC 24 |
Aug 29 07:54:32 PM UTC 24 |
4407477656 ps |
| T1167 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/default/1.rom_e2e_asm_init_prod.2601865233 |
|
|
Aug 29 06:38:25 PM UTC 24 |
Aug 29 07:54:38 PM UTC 24 |
16021026185 ps |
| T373 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/default/1.rom_e2e_shutdown_output.3634597654 |
|
|
Aug 29 06:38:52 PM UTC 24 |
Aug 29 07:54:46 PM UTC 24 |
25048590920 ps |
| T184 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_plic_all_irqs_10.385117071 |
|
|
Aug 29 07:44:20 PM UTC 24 |
Aug 29 07:55:38 PM UTC 24 |
4173133082 ps |
| T1168 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/default/1.rom_e2e_smoke.2900282728 |
|
|
Aug 29 06:40:15 PM UTC 24 |
Aug 29 07:56:15 PM UTC 24 |
14857881596 ps |
| T1169 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/default/1.rom_e2e_keymgr_init_rom_ext_invalid_meas.604288849 |
|
|
Aug 29 06:40:58 PM UTC 24 |
Aug 29 07:57:07 PM UTC 24 |
15066862468 ps |
| T1170 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_clkmgr_external_clk_src_for_lc.2283605201 |
|
|
Aug 29 07:49:40 PM UTC 24 |
Aug 29 07:57:08 PM UTC 24 |
7219460111 ps |
| T1171 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_sleep_sram_ret_contents_no_scramble.3407870808 |
|
|
Aug 29 07:41:23 PM UTC 24 |
Aug 29 07:57:11 PM UTC 24 |
6587382166 ps |
| T1172 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/default/1.rom_e2e_asm_init_rma.2145635984 |
|
|
Aug 29 06:39:33 PM UTC 24 |
Aug 29 07:57:38 PM UTC 24 |
14517840800 ps |
| T165 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_sensor_ctrl_alert.3942688905 |
|
|
Aug 29 07:41:58 PM UTC 24 |
Aug 29 07:57:42 PM UTC 24 |
7607249792 ps |
| T1173 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_clkmgr_off_otbn_trans.658010039 |
|
|
Aug 29 07:49:13 PM UTC 24 |
Aug 29 07:58:02 PM UTC 24 |
4476196426 ps |
| T1174 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/default/1.rom_e2e_keymgr_init_rom_ext_no_meas.1485766571 |
|
|
Aug 29 06:40:41 PM UTC 24 |
Aug 29 07:58:07 PM UTC 24 |
15119116246 ps |
| T328 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_plic_all_irqs_20.1749711405 |
|
|
Aug 29 07:44:32 PM UTC 24 |
Aug 29 07:58:11 PM UTC 24 |
4037162800 ps |
| T1175 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_clkmgr_off_hmac_trans.3180886470 |
|
|
Aug 29 07:48:21 PM UTC 24 |
Aug 29 07:58:11 PM UTC 24 |
4640203096 ps |
| T1176 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_edn_auto_mode.3366779939 |
|
|
Aug 29 07:29:25 PM UTC 24 |
Aug 29 07:58:16 PM UTC 24 |
5966200088 ps |
| T1177 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_clkmgr_off_kmac_trans.3980003861 |
|
|
Aug 29 07:48:46 PM UTC 24 |
Aug 29 07:58:22 PM UTC 24 |
5139100090 ps |
| T635 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq.215672699 |
|
|
Aug 29 06:31:32 PM UTC 24 |
Aug 29 07:58:44 PM UTC 24 |
25623834174 ps |
| T1178 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_clkmgr_jitter.3950793637 |
|
|
Aug 29 07:54:15 PM UTC 24 |
Aug 29 07:58:44 PM UTC 24 |
2848333966 ps |
| T1179 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/default/1.rom_e2e_keymgr_init_rom_ext_meas.2657554230 |
|
|
Aug 29 06:39:27 PM UTC 24 |
Aug 29 07:59:14 PM UTC 24 |
14862243440 ps |
| T1180 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/default/1.rom_e2e_asm_init_dev.1742310390 |
|
|
Aug 29 06:39:35 PM UTC 24 |
Aug 29 07:59:17 PM UTC 24 |
15316343228 ps |
| T1181 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_pwrmgr_random_sleep_all_reset_reqs.2714378230 |
|
|
Aug 29 07:08:11 PM UTC 24 |
Aug 29 07:59:24 PM UTC 24 |
22963026733 ps |
| T1182 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_clkmgr_jitter_frequency.232700939 |
|
|
Aug 29 07:53:44 PM UTC 24 |
Aug 29 07:59:26 PM UTC 24 |
2687338112 ps |
| T1183 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_clkmgr_reset_frequency.1076598587 |
|
|
Aug 29 07:53:12 PM UTC 24 |
Aug 29 07:59:35 PM UTC 24 |
2854114452 ps |
| T1184 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_alert_handler_lpg_clkoff.242876363 |
|
|
Aug 29 07:26:17 PM UTC 24 |
Aug 29 07:59:46 PM UTC 24 |
8702103896 ps |
| T1185 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/default/1.rom_e2e_asm_init_prod_end.4128143869 |
|
|
Aug 29 06:40:45 PM UTC 24 |
Aug 29 08:00:49 PM UTC 24 |
15322680836 ps |
| T1186 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_clkmgr_external_clk_src_for_sw_fast_dev.2494850517 |
|
|
Aug 29 07:51:13 PM UTC 24 |
Aug 29 08:01:31 PM UTC 24 |
3395074760 ps |
| T1187 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0.1164534568 |
|
|
Aug 29 07:50:36 PM UTC 24 |
Aug 29 08:01:46 PM UTC 24 |
5287740136 ps |
| T195 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_lc_ctrl_program_error.2654279617 |
|
|
Aug 29 07:55:27 PM UTC 24 |
Aug 29 08:01:54 PM UTC 24 |
4464286636 ps |
| T1188 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_tap_straps_dev.1602373312 |
|
|
Aug 29 07:58:49 PM UTC 24 |
Aug 29 08:02:03 PM UTC 24 |
3125950930 ps |
| T431 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_pwrmgr_normal_sleep_all_wake_ups.525075282 |
|
|
Aug 29 07:55:30 PM UTC 24 |
Aug 29 08:02:24 PM UTC 24 |
7697102964 ps |
| T1189 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_tap_straps_prod.1696252428 |
|
|
Aug 29 07:59:11 PM UTC 24 |
Aug 29 08:02:46 PM UTC 24 |
2985966829 ps |
| T1190 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0.4126114669 |
|
|
Aug 29 07:50:36 PM UTC 24 |
Aug 29 08:02:50 PM UTC 24 |
4444475674 ps |
| T1191 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_clkmgr_external_clk_src_for_sw_slow_rma.4172734595 |
|
|
Aug 29 07:52:36 PM UTC 24 |
Aug 29 08:02:55 PM UTC 24 |
4617197310 ps |
| T401 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_rv_core_ibex_lockstep_glitch.1732524194 |
|
|
Aug 29 08:00:27 PM UTC 24 |
Aug 29 08:03:23 PM UTC 24 |
2468426400 ps |
| T357 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_pwrmgr_lowpower_cancel.2857334352 |
|
|
Aug 29 07:56:12 PM UTC 24 |
Aug 29 08:03:48 PM UTC 24 |
3884507048 ps |
| T1192 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_clkmgr_external_clk_src_for_sw_fast_rma.3394906616 |
|
|
Aug 29 07:51:16 PM UTC 24 |
Aug 29 08:03:50 PM UTC 24 |
3744422760 ps |
| T1193 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_clkmgr_external_clk_src_for_sw_slow_dev.3727939910 |
|
|
Aug 29 07:51:17 PM UTC 24 |
Aug 29 08:03:56 PM UTC 24 |
4903933304 ps |
| T1194 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_keymgr_key_derivation_jitter_en.3888298649 |
|
|
Aug 29 07:35:15 PM UTC 24 |
Aug 29 08:04:03 PM UTC 24 |
9404572330 ps |
| T1195 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_clkmgr_jitter_reduced_freq.1171643542 |
|
|
Aug 29 08:00:47 PM UTC 24 |
Aug 29 08:04:16 PM UTC 24 |
2801224382 ps |
| T1196 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_clkmgr_sleep_frequency.1449727396 |
|
|
Aug 29 07:54:38 PM UTC 24 |
Aug 29 08:05:20 PM UTC 24 |
4660218600 ps |
| T1197 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_keymgr_sideload_kmac.821799761 |
|
|
Aug 29 07:35:16 PM UTC 24 |
Aug 29 08:05:26 PM UTC 24 |
8450800056 ps |
| T270 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_rv_core_ibex_address_translation.4102905962 |
|
|
Aug 29 08:00:44 PM UTC 24 |
Aug 29 08:05:47 PM UTC 24 |
3894563580 ps |
| T331 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_plic_all_irqs_0.4195965131 |
|
|
Aug 29 07:44:20 PM UTC 24 |
Aug 29 08:06:00 PM UTC 24 |
5915613528 ps |
| T1198 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/default/1.rom_e2e_static_critical.4256417878 |
|
|
Aug 29 06:40:39 PM UTC 24 |
Aug 29 08:06:01 PM UTC 24 |
17201243168 ps |
| T1199 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_rv_dm_access_after_wakeup.4112888200 |
|
|
Aug 29 07:59:13 PM UTC 24 |
Aug 29 08:06:04 PM UTC 24 |
6332863000 ps |
| T317 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_rv_core_ibex_icache_invalidate.665365618 |
|
|
Aug 29 08:00:53 PM UTC 24 |
Aug 29 08:06:05 PM UTC 24 |
2739101301 ps |
| T439 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_rv_dm_ndm_reset_req.2362598172 |
|
|
Aug 29 07:58:59 PM UTC 24 |
Aug 29 08:06:20 PM UTC 24 |
4812153420 ps |
| T382 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up.3864632862 |
|
|
Aug 29 07:59:09 PM UTC 24 |
Aug 29 08:06:27 PM UTC 24 |
6629508860 ps |
| T1200 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_aes_enc_jitter_en_reduced_freq.1373211448 |
|
|
Aug 29 08:02:05 PM UTC 24 |
Aug 29 08:06:49 PM UTC 24 |
2951222713 ps |
| T1201 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_hmac_enc_jitter_en_reduced_freq.2595079460 |
|
|
Aug 29 08:02:41 PM UTC 24 |
Aug 29 08:06:53 PM UTC 24 |
2306377596 ps |
| T1202 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_clkmgr_off_peri.2278029498 |
|
|
Aug 29 07:45:11 PM UTC 24 |
Aug 29 08:06:53 PM UTC 24 |
9720925840 ps |
| T1203 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_hmac_multistream.1784597229 |
|
|
Aug 29 07:34:36 PM UTC 24 |
Aug 29 08:07:01 PM UTC 24 |
8111718728 ps |
| T1204 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_flash_ctrl_write_clear.1643799860 |
|
|
Aug 29 08:00:54 PM UTC 24 |
Aug 29 08:07:32 PM UTC 24 |
3698082450 ps |
| T1205 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_kmac_mode_kmac_jitter_en_reduced_freq.3282644471 |
|
|
Aug 29 08:02:53 PM UTC 24 |
Aug 29 08:07:39 PM UTC 24 |
3565699177 ps |
| T1206 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_rv_dm_ndm_reset_req_when_cpu_halted.2991725028 |
|
|
Aug 29 07:59:23 PM UTC 24 |
Aug 29 08:08:14 PM UTC 24 |
4429504602 ps |
| T350 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_entropy_src_csrng.229329010 |
|
|
Aug 29 07:32:00 PM UTC 24 |
Aug 29 08:08:16 PM UTC 24 |
8310363974 ps |
| T637 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_rv_dm_access_after_escalation_reset.2727616239 |
|
|
Aug 29 07:59:36 PM UTC 24 |
Aug 29 08:09:03 PM UTC 24 |
5032043703 ps |
| T83 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_tap_straps_testunlock0.496641074 |
|
|
Aug 29 07:59:38 PM UTC 24 |
Aug 29 08:10:21 PM UTC 24 |
6660844028 ps |
| T1207 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/default/4.chip_tap_straps_prod.505655750 |
|
|
Aug 29 08:29:40 PM UTC 24 |
Aug 29 08:39:27 PM UTC 24 |
5543687749 ps |
| T1208 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_flash_scrambling_smoketest.4101657445 |
|
|
Aug 29 08:05:36 PM UTC 24 |
Aug 29 08:10:23 PM UTC 24 |
2925475924 ps |
| T1209 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_pwrmgr_sleep_wake_5_bug.53611222 |
|
|
Aug 29 08:00:05 PM UTC 24 |
Aug 29 08:10:26 PM UTC 24 |
6983538518 ps |
| T670 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_flash_crash_alert.3646618833 |
|
|
Aug 29 08:00:49 PM UTC 24 |
Aug 29 08:10:36 PM UTC 24 |
4478056284 ps |
| T371 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_flash_ctrl_ops_jitter_en_reduced_freq.484189282 |
|
|
Aug 29 08:00:54 PM UTC 24 |
Aug 29 08:11:01 PM UTC 24 |
4666003601 ps |
| T228 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_jtag_csr_rw.1611385917 |
|
|
Aug 29 07:54:26 PM UTC 24 |
Aug 29 08:11:50 PM UTC 24 |
10882513254 ps |
| T1210 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/default/2.rom_volatile_raw_unlock.2666362071 |
|
|
Aug 29 08:09:59 PM UTC 24 |
Aug 29 08:12:19 PM UTC 24 |
2495786306 ps |
| T1211 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq.1827094053 |
|
|
Aug 29 08:02:57 PM UTC 24 |
Aug 29 08:12:19 PM UTC 24 |
5672748231 ps |
| T84 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_tap_straps_rma.2956055049 |
|
|
Aug 29 07:58:58 PM UTC 24 |
Aug 29 08:12:40 PM UTC 24 |
8285542774 ps |
| T1212 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/default/2.rom_raw_unlock.3034372030 |
|
|
Aug 29 08:08:35 PM UTC 24 |
Aug 29 08:13:19 PM UTC 24 |
5206651311 ps |
| T1213 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_power_idle_load.937570359 |
|
|
Aug 29 08:04:00 PM UTC 24 |
Aug 29 08:13:22 PM UTC 24 |
4046564714 ps |
| T1214 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_clkmgr_smoketest.1056333767 |
|
|
Aug 29 08:10:08 PM UTC 24 |
Aug 29 08:13:53 PM UTC 24 |
2833626760 ps |
| T1215 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_csrng_smoketest.3066124518 |
|
|
Aug 29 08:10:19 PM UTC 24 |
Aug 29 08:15:00 PM UTC 24 |
3172134810 ps |
| T1216 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_ast_clk_outputs.673594781 |
|
|
Aug 29 07:55:26 PM UTC 24 |
Aug 29 08:15:21 PM UTC 24 |
7968014200 ps |
| T1217 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_aon_timer_smoketest.3150026246 |
|
|
Aug 29 08:10:14 PM UTC 24 |
Aug 29 08:15:26 PM UTC 24 |
2634833266 ps |
| T1218 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_aes_smoketest.2731300511 |
|
|
Aug 29 08:10:16 PM UTC 24 |
Aug 29 08:15:49 PM UTC 24 |
3445244292 ps |
| T1219 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_edn_sw_mode.192950478 |
|
|
Aug 29 07:29:51 PM UTC 24 |
Aug 29 08:15:55 PM UTC 24 |
10418473000 ps |
| T1220 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_power_sleep_load.1500317417 |
|
|
Aug 29 08:03:58 PM UTC 24 |
Aug 29 08:16:00 PM UTC 24 |
10192285940 ps |
| T1221 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_kmac_smoketest.453556586 |
|
|
Aug 29 08:11:34 PM UTC 24 |
Aug 29 08:16:17 PM UTC 24 |
3518664852 ps |
| T1222 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_sysrst_ctrl_ec_rst_l.4210490684 |
|
|
Aug 29 07:15:29 PM UTC 24 |
Aug 29 08:16:25 PM UTC 24 |
20146882987 ps |
| T1223 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_rv_plic_smoketest.3125951963 |
|
|
Aug 29 08:13:17 PM UTC 24 |
Aug 29 08:16:41 PM UTC 24 |
2381359114 ps |
| T1224 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_otp_ctrl_smoketest.2746100302 |
|
|
Aug 29 08:12:23 PM UTC 24 |
Aug 29 08:16:53 PM UTC 24 |
2462787440 ps |
| T1225 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_gpio_smoketest.2348757469 |
|
|
Aug 29 08:11:34 PM UTC 24 |
Aug 29 08:16:56 PM UTC 24 |
2630561538 ps |
| T1226 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_hmac_smoketest.147337407 |
|
|
Aug 29 08:11:22 PM UTC 24 |
Aug 29 08:17:08 PM UTC 24 |
3530243038 ps |
| T1227 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_rstmgr_smoketest.2976938930 |
|
|
Aug 29 08:14:05 PM UTC 24 |
Aug 29 08:17:27 PM UTC 24 |
2118653348 ps |
| T1228 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/default/2.rom_keymgr_functest.2019452561 |
|
|
Aug 29 08:09:13 PM UTC 24 |
Aug 29 08:17:47 PM UTC 24 |
4127272852 ps |
| T1229 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_rv_timer_smoketest.1327088472 |
|
|
Aug 29 08:14:04 PM UTC 24 |
Aug 29 08:17:55 PM UTC 24 |
2417776980 ps |
| T235 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_inject_scramble_seed.1824039680 |
|
|
Aug 29 03:35:00 PM UTC 24 |
Aug 29 08:18:08 PM UTC 24 |
65905397509 ps |
| T1230 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_flash_ctrl_access_jitter_en_reduced_freq.2441121426 |
|
|
Aug 29 08:00:57 PM UTC 24 |
Aug 29 08:18:16 PM UTC 24 |
7177446659 ps |
| T1231 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_keymgr_key_derivation.2192572447 |
|
|
Aug 29 07:34:32 PM UTC 24 |
Aug 29 08:18:38 PM UTC 24 |
11806048884 ps |
| T1232 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_sram_ctrl_smoketest.1553362780 |
|
|
Aug 29 08:14:26 PM UTC 24 |
Aug 29 08:19:28 PM UTC 24 |
3147676872 ps |
| T1233 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_keymgr_key_derivation_prod.2481351371 |
|
|
Aug 29 07:35:16 PM UTC 24 |
Aug 29 08:19:30 PM UTC 24 |
11345930468 ps |
| T1234 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_pwrmgr_usbdev_smoketest.1784831504 |
|
|
Aug 29 08:13:12 PM UTC 24 |
Aug 29 08:19:32 PM UTC 24 |
4783274656 ps |
| T1235 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_entropy_src_smoketest.1531796447 |
|
|
Aug 29 08:11:22 PM UTC 24 |
Aug 29 08:19:57 PM UTC 24 |
3703525204 ps |
| T1236 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_uart_smoketest.3297873561 |
|
|
Aug 29 08:15:31 PM UTC 24 |
Aug 29 08:20:39 PM UTC 24 |
2890293688 ps |
| T229 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_jtag_mem_access.1135097964 |
|
|
Aug 29 07:54:33 PM UTC 24 |
Aug 29 08:21:51 PM UTC 24 |
14088732888 ps |
| T1237 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_pwrmgr_smoketest.556765965 |
|
|
Aug 29 08:13:12 PM UTC 24 |
Aug 29 08:21:56 PM UTC 24 |
5703369576 ps |
| T1238 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/default/3.chip_tap_straps_dev.2459162237 |
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Aug 29 08:18:52 PM UTC 24 |
Aug 29 08:23:19 PM UTC 24 |
3199926781 ps |
| T1239 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_flash_ctrl_mem_protection.2095342910 |
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Aug 29 08:05:37 PM UTC 24 |
Aug 29 08:24:58 PM UTC 24 |
6037095440 ps |
| T1240 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/default/3.chip_tap_straps_testunlock0.3872029538 |
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Aug 29 08:18:51 PM UTC 24 |
Aug 29 08:25:15 PM UTC 24 |
4985484699 ps |
| T1241 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_keymgr_key_derivation_jitter_en_reduced_freq.1187490173 |
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Aug 29 08:02:41 PM UTC 24 |
Aug 29 08:26:00 PM UTC 24 |
9275514786 ps |
| T1242 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/default/3.chip_sw_data_integrity_escalation.1158010356 |
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Aug 29 08:16:09 PM UTC 24 |
Aug 29 08:26:52 PM UTC 24 |
5572307660 ps |
| T728 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/default/3.chip_sw_all_escalation_resets.950977920 |
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Aug 29 08:16:08 PM UTC 24 |
Aug 29 08:26:53 PM UTC 24 |
5359996504 ps |
| T1243 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/default/3.chip_sw_aon_timer_sleep_wdog_sleep_pause.1459918148 |
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Aug 29 08:18:58 PM UTC 24 |
Aug 29 08:27:38 PM UTC 24 |
7364045184 ps |
| T758 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/default/3.chip_sw_alert_handler_lpg_sleep_mode_alerts.3740246766 |
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Aug 29 08:18:59 PM UTC 24 |
Aug 29 08:27:52 PM UTC 24 |
3690314734 ps |
| T1244 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/default/3.chip_sw_uart_tx_rx_idx1.2047194604 |
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Aug 29 08:17:57 PM UTC 24 |
Aug 29 08:28:17 PM UTC 24 |
4456278276 ps |
| T168 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/default/3.chip_sw_sensor_ctrl_alert.531124631 |
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Aug 29 08:18:57 PM UTC 24 |
Aug 29 08:28:26 PM UTC 24 |
3751002110 ps |
| T1245 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/default/3.chip_sw_uart_tx_rx_idx3.112831985 |
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Aug 29 08:18:36 PM UTC 24 |
Aug 29 08:28:50 PM UTC 24 |
4291638280 ps |
| T432 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_pwrmgr_deep_sleep_all_wake_ups.2161499336 |
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Aug 29 07:56:49 PM UTC 24 |
Aug 29 08:29:13 PM UTC 24 |
22049855288 ps |
| T1246 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/default/3.chip_sw_uart_tx_rx.2558366636 |
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Aug 29 08:18:34 PM UTC 24 |
Aug 29 08:30:09 PM UTC 24 |
4616232088 ps |
| T1247 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_pwrmgr_b2b_sleep_reset_req.1643868035 |
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Aug 29 07:43:23 PM UTC 24 |
Aug 29 08:30:16 PM UTC 24 |
28111342376 ps |
| T1248 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/default/3.chip_tap_straps_rma.272721456 |
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Aug 29 08:19:07 PM UTC 24 |
Aug 29 08:30:22 PM UTC 24 |
7145543872 ps |
| T1249 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/default/3.chip_sw_uart_tx_rx_idx2.1809597155 |
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Aug 29 08:17:57 PM UTC 24 |
Aug 29 08:30:27 PM UTC 24 |
4425888140 ps |
| T1250 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/default/3.chip_sw_lc_ctrl_transition.844840146 |
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Aug 29 08:18:35 PM UTC 24 |
Aug 29 08:31:47 PM UTC 24 |
7201563808 ps |
| T126 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_power_virus.984792233 |
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Aug 29 08:05:39 PM UTC 24 |
Aug 29 08:31:56 PM UTC 24 |
6049422406 ps |
| T433 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_pwrmgr_random_sleep_all_wake_ups.3125515495 |
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Aug 29 07:58:22 PM UTC 24 |
Aug 29 08:32:35 PM UTC 24 |
21859369280 ps |
| T1251 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/default/4.chip_sw_uart_tx_rx.3405204136 |
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Aug 29 08:20:38 PM UTC 24 |
Aug 29 08:32:44 PM UTC 24 |
3994278060 ps |
| T725 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/default/4.chip_sw_all_escalation_resets.2815116197 |
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Aug 29 08:20:36 PM UTC 24 |
Aug 29 08:33:23 PM UTC 24 |
5808077930 ps |
| T1252 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/default/4.chip_sw_uart_tx_rx_idx2.823336796 |
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Aug 29 08:22:37 PM UTC 24 |
Aug 29 08:33:28 PM UTC 24 |
4607669518 ps |
| T1253 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/default/4.chip_sw_data_integrity_escalation.365676072 |
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Aug 29 08:20:33 PM UTC 24 |
Aug 29 08:33:49 PM UTC 24 |
6665253588 ps |
| T1254 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/default/4.chip_sw_lc_ctrl_transition.1803100469 |
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Aug 29 08:26:33 PM UTC 24 |
Aug 29 08:34:45 PM UTC 24 |
5523189136 ps |
| T1255 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/default/4.chip_sw_uart_rand_baudrate.1063795092 |
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Aug 29 08:23:54 PM UTC 24 |
Aug 29 08:34:53 PM UTC 24 |
4560835408 ps |
| T1256 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/default/4.chip_sw_uart_tx_rx_idx3.4072631925 |
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Aug 29 08:22:37 PM UTC 24 |
Aug 29 08:34:56 PM UTC 24 |
4331661940 ps |