| T1337 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/default/9.chip_sw_csrng_edn_concurrency.4238534480 |
|
|
Aug 29 08:40:34 PM UTC 24 |
Aug 29 10:07:50 PM UTC 24 |
20316252408 ps |
| T633 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_csrng_edn_concurrency_reduced_freq.1795930629 |
|
|
Aug 29 04:18:38 PM UTC 24 |
Aug 29 10:11:05 PM UTC 24 |
115309961925 ps |
| T1338 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_exit_test_unlocked_bootstrap.3696494251 |
|
|
Aug 29 06:50:26 PM UTC 24 |
Aug 29 10:29:06 PM UTC 24 |
59305968375 ps |
| T1339 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_uart_tx_rx_bootstrap.3027980033 |
|
|
Aug 29 05:27:48 PM UTC 24 |
Aug 29 10:32:30 PM UTC 24 |
80199269720 ps |
| T1340 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_inject_scramble_seed.851517747 |
|
|
Aug 29 06:50:28 PM UTC 24 |
Aug 29 10:35:30 PM UTC 24 |
66457828667 ps |
| T1341 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/default/6.chip_sw_csrng_edn_concurrency.2099245468 |
|
|
Aug 29 08:34:24 PM UTC 24 |
Aug 29 10:43:31 PM UTC 24 |
35756539448 ps |
| T1342 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_alert_handler_reverse_ping_in_deep_sleep.527801219 |
|
|
Aug 29 07:24:04 PM UTC 24 |
Aug 29 11:01:41 PM UTC 24 |
254541379112 ps |
| T1343 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_uart_tx_rx_bootstrap.2971353631 |
|
|
Aug 29 06:50:26 PM UTC 24 |
Aug 29 11:05:21 PM UTC 24 |
79480844272 ps |
| T94 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/0.xbar_smoke.2215904952 |
|
|
Aug 29 01:00:23 PM UTC 24 |
Aug 29 01:00:30 PM UTC 24 |
50712445 ps |
| T95 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/0.xbar_smoke_zero_delays.1127016569 |
|
|
Aug 29 01:00:26 PM UTC 24 |
Aug 29 01:00:35 PM UTC 24 |
41304876 ps |
| T96 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/1.xbar_smoke.1303024351 |
|
|
Aug 29 01:00:29 PM UTC 24 |
Aug 29 01:00:36 PM UTC 24 |
52921444 ps |
| T98 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/0.xbar_same_source.628825407 |
|
|
Aug 29 01:00:27 PM UTC 24 |
Aug 29 01:00:38 PM UTC 24 |
57729123 ps |
| T158 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/0.xbar_error_random.561121023 |
|
|
Aug 29 01:00:24 PM UTC 24 |
Aug 29 01:00:39 PM UTC 24 |
359976181 ps |
| T177 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/1.xbar_smoke_zero_delays.2615353282 |
|
|
Aug 29 01:00:31 PM UTC 24 |
Aug 29 01:00:40 PM UTC 24 |
47283164 ps |
| T570 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/0.xbar_access_same_device.1026373294 |
|
|
Aug 29 01:00:28 PM UTC 24 |
Aug 29 01:00:48 PM UTC 24 |
204351337 ps |
| T241 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/0.xbar_error_and_unmapped_addr.3573501400 |
|
|
Aug 29 01:00:28 PM UTC 24 |
Aug 29 01:00:57 PM UTC 24 |
747267477 ps |
| T279 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/1.xbar_random.1565380567 |
|
|
Aug 29 01:00:38 PM UTC 24 |
Aug 29 01:01:02 PM UTC 24 |
500719769 ps |
| T459 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/1.xbar_error_and_unmapped_addr.1273537640 |
|
|
Aug 29 01:00:58 PM UTC 24 |
Aug 29 01:01:07 PM UTC 24 |
29007228 ps |
| T460 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/1.xbar_random_zero_delays.2222648911 |
|
|
Aug 29 01:00:46 PM UTC 24 |
Aug 29 01:01:09 PM UTC 24 |
158499073 ps |
| T438 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/0.xbar_random.291083051 |
|
|
Aug 29 01:00:28 PM UTC 24 |
Aug 29 01:01:10 PM UTC 24 |
475297010 ps |
| T429 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/0.xbar_random_zero_delays.509591061 |
|
|
Aug 29 01:00:26 PM UTC 24 |
Aug 29 01:01:13 PM UTC 24 |
389182393 ps |
| T456 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/1.xbar_same_source.3429862524 |
|
|
Aug 29 01:00:57 PM UTC 24 |
Aug 29 01:01:17 PM UTC 24 |
173191197 ps |
| T453 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/0.xbar_unmapped_addr.2229516824 |
|
|
Aug 29 01:00:27 PM UTC 24 |
Aug 29 01:01:21 PM UTC 24 |
1414949744 ps |
| T689 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/1.xbar_access_same_device.1686168256 |
|
|
Aug 29 01:00:56 PM UTC 24 |
Aug 29 01:01:24 PM UTC 24 |
296004680 ps |
| T457 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/1.xbar_unmapped_addr.2402224585 |
|
|
Aug 29 01:00:57 PM UTC 24 |
Aug 29 01:01:35 PM UTC 24 |
801585166 ps |
| T563 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/2.xbar_smoke_zero_delays.105901364 |
|
|
Aug 29 01:01:42 PM UTC 24 |
Aug 29 01:01:49 PM UTC 24 |
43047362 ps |
| T557 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/0.xbar_random_large_delays.2802149971 |
|
|
Aug 29 01:00:26 PM UTC 24 |
Aug 29 01:01:51 PM UTC 24 |
9156370653 ps |
| T556 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/2.xbar_smoke.1454289868 |
|
|
Aug 29 01:01:38 PM UTC 24 |
Aug 29 01:01:52 PM UTC 24 |
214430911 ps |
| T554 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/0.xbar_smoke_slow_rsp.2998267575 |
|
|
Aug 29 01:00:26 PM UTC 24 |
Aug 29 01:01:52 PM UTC 24 |
4288354150 ps |
| T561 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/1.xbar_smoke_slow_rsp.2235336414 |
|
|
Aug 29 01:00:31 PM UTC 24 |
Aug 29 01:02:01 PM UTC 24 |
5321964715 ps |
| T566 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/0.xbar_smoke_large_delays.150344000 |
|
|
Aug 29 01:00:28 PM UTC 24 |
Aug 29 01:02:02 PM UTC 24 |
9100175734 ps |
| T546 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/1.xbar_error_random.4174580320 |
|
|
Aug 29 01:00:55 PM UTC 24 |
Aug 29 01:02:17 PM UTC 24 |
2248657327 ps |
| T569 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/2.xbar_error_and_unmapped_addr.2496520268 |
|
|
Aug 29 01:02:12 PM UTC 24 |
Aug 29 01:02:22 PM UTC 24 |
85292292 ps |
| T555 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/2.xbar_same_source.1821552293 |
|
|
Aug 29 01:02:09 PM UTC 24 |
Aug 29 01:02:28 PM UTC 24 |
410510001 ps |
| T454 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/2.xbar_access_same_device.1621827130 |
|
|
Aug 29 01:02:08 PM UTC 24 |
Aug 29 01:02:30 PM UTC 24 |
144644357 ps |
| T437 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/2.xbar_random.1315709135 |
|
|
Aug 29 01:01:48 PM UTC 24 |
Aug 29 01:02:32 PM UTC 24 |
489995310 ps |
| T547 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/2.xbar_unmapped_addr.2610640869 |
|
|
Aug 29 01:02:12 PM UTC 24 |
Aug 29 01:02:34 PM UTC 24 |
268081679 ps |
| T552 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/2.xbar_random_zero_delays.1435747411 |
|
|
Aug 29 01:01:52 PM UTC 24 |
Aug 29 01:02:38 PM UTC 24 |
385912687 ps |
| T560 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/1.xbar_smoke_large_delays.612752685 |
|
|
Aug 29 01:00:31 PM UTC 24 |
Aug 29 01:02:41 PM UTC 24 |
11202467747 ps |
| T884 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/2.chip_prim_tl_access.1561726314 |
|
|
Aug 29 01:01:33 PM UTC 24 |
Aug 29 01:07:12 PM UTC 24 |
5490988560 ps |
| T548 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/1.xbar_stress_all.666327047 |
|
|
Aug 29 01:00:58 PM UTC 24 |
Aug 29 01:02:44 PM UTC 24 |
2361630302 ps |
| T1344 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/2.xbar_smoke_large_delays.472817410 |
|
|
Aug 29 01:01:45 PM UTC 24 |
Aug 29 01:02:53 PM UTC 24 |
6902969526 ps |
| T562 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/2.xbar_smoke_slow_rsp.3522191817 |
|
|
Aug 29 01:01:45 PM UTC 24 |
Aug 29 01:02:59 PM UTC 24 |
4503149629 ps |
| T558 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/0.xbar_stress_all_with_reset_error.2547875943 |
|
|
Aug 29 01:00:29 PM UTC 24 |
Aug 29 01:03:02 PM UTC 24 |
1867929811 ps |
| T568 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/3.xbar_smoke_zero_delays.3625368172 |
|
|
Aug 29 01:03:03 PM UTC 24 |
Aug 29 01:03:11 PM UTC 24 |
45599541 ps |
| T564 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/3.xbar_smoke.1092859247 |
|
|
Aug 29 01:03:01 PM UTC 24 |
Aug 29 01:03:14 PM UTC 24 |
199994191 ps |
| T551 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/2.xbar_error_random.582293412 |
|
|
Aug 29 01:02:11 PM UTC 24 |
Aug 29 01:03:24 PM UTC 24 |
2051038503 ps |
| T567 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/3.xbar_random_zero_delays.2323557158 |
|
|
Aug 29 01:03:29 PM UTC 24 |
Aug 29 01:03:40 PM UTC 24 |
101519418 ps |
| T426 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/2.xbar_stress_all.3603167252 |
|
|
Aug 29 01:02:21 PM UTC 24 |
Aug 29 01:03:51 PM UTC 24 |
2493500788 ps |
| T441 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/0.xbar_stress_all_with_rand_reset.148161972 |
|
|
Aug 29 01:00:27 PM UTC 24 |
Aug 29 01:03:51 PM UTC 24 |
567185866 ps |
| T549 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/0.xbar_stress_all_with_error.3328670890 |
|
|
Aug 29 01:00:27 PM UTC 24 |
Aug 29 01:03:53 PM UTC 24 |
5230980720 ps |
| T559 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/3.xbar_random.2704668065 |
|
|
Aug 29 01:03:21 PM UTC 24 |
Aug 29 01:03:55 PM UTC 24 |
257589624 ps |
| T1345 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/3.xbar_same_source.4264636948 |
|
|
Aug 29 01:04:01 PM UTC 24 |
Aug 29 01:04:10 PM UTC 24 |
34991885 ps |
| T550 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/1.xbar_stress_all_with_reset_error.77528096 |
|
|
Aug 29 01:01:17 PM UTC 24 |
Aug 29 01:04:18 PM UTC 24 |
506477005 ps |
| T553 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/1.xbar_stress_all_with_error.1832416639 |
|
|
Aug 29 01:01:13 PM UTC 24 |
Aug 29 01:04:19 PM UTC 24 |
5268395541 ps |
| T1346 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/3.xbar_error_and_unmapped_addr.1543381918 |
|
|
Aug 29 01:04:12 PM UTC 24 |
Aug 29 01:04:22 PM UTC 24 |
32478254 ps |
| T170 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/0.chip_csr_hw_reset.2607263137 |
|
|
Aug 29 01:00:27 PM UTC 24 |
Aug 29 01:04:27 PM UTC 24 |
4955914220 ps |
| T565 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/3.xbar_error_random.1528479761 |
|
|
Aug 29 01:04:05 PM UTC 24 |
Aug 29 01:04:40 PM UTC 24 |
658290579 ps |
| T615 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/3.xbar_random_slow_rsp.3140858021 |
|
|
Aug 29 01:03:34 PM UTC 24 |
Aug 29 01:04:51 PM UTC 24 |
4709842386 ps |
| T404 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/1.chip_tl_errors.1171468917 |
|
|
Aug 29 01:00:30 PM UTC 24 |
Aug 29 01:04:55 PM UTC 24 |
4389993399 ps |
| T582 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/0.xbar_stress_all.4173781964 |
|
|
Aug 29 01:00:28 PM UTC 24 |
Aug 29 01:04:56 PM UTC 24 |
6154244849 ps |
| T845 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/3.xbar_smoke_slow_rsp.1800997532 |
|
|
Aug 29 01:03:19 PM UTC 24 |
Aug 29 01:04:59 PM UTC 24 |
4985879192 ps |
| T1347 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/3.xbar_smoke_large_delays.2682333848 |
|
|
Aug 29 01:03:14 PM UTC 24 |
Aug 29 01:05:14 PM UTC 24 |
9090499511 ps |
| T647 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/3.xbar_stress_all_with_rand_reset.44072615 |
|
|
Aug 29 01:04:15 PM UTC 24 |
Aug 29 01:05:26 PM UTC 24 |
124983423 ps |
| T1348 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/4.xbar_smoke.2249636934 |
|
|
Aug 29 01:05:20 PM UTC 24 |
Aug 29 01:05:31 PM UTC 24 |
138379636 ps |
| T501 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/3.xbar_unmapped_addr.2014668098 |
|
|
Aug 29 01:04:11 PM UTC 24 |
Aug 29 01:05:34 PM UTC 24 |
1346214618 ps |
| T1349 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/0.chip_prim_tl_access.3600566947 |
|
|
Aug 29 01:00:25 PM UTC 24 |
Aug 29 01:05:42 PM UTC 24 |
6529689966 ps |
| T623 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/4.xbar_smoke_zero_delays.3177713629 |
|
|
Aug 29 01:05:36 PM UTC 24 |
Aug 29 01:05:44 PM UTC 24 |
43195106 ps |
| T571 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/3.xbar_access_same_device.1037241506 |
|
|
Aug 29 01:03:44 PM UTC 24 |
Aug 29 01:05:53 PM UTC 24 |
2110118854 ps |
| T169 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/2.chip_csr_hw_reset.585839581 |
|
|
Aug 29 01:02:40 PM UTC 24 |
Aug 29 01:06:00 PM UTC 24 |
4089388230 ps |
| T1350 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/4.xbar_random_zero_delays.2183830729 |
|
|
Aug 29 01:05:53 PM UTC 24 |
Aug 29 01:06:07 PM UTC 24 |
108900269 ps |
| T171 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/1.chip_csr_hw_reset.1837360198 |
|
|
Aug 29 01:01:23 PM UTC 24 |
Aug 29 01:06:09 PM UTC 24 |
4806777702 ps |
| T641 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/3.xbar_stress_all_with_error.2812684334 |
|
|
Aug 29 01:04:30 PM UTC 24 |
Aug 29 01:06:10 PM UTC 24 |
3161010529 ps |
| T574 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/2.chip_tl_errors.649431730 |
|
|
Aug 29 01:01:31 PM UTC 24 |
Aug 29 01:06:11 PM UTC 24 |
3554460718 ps |
| T1351 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/4.xbar_stress_all.3567221949 |
|
|
Aug 29 01:06:31 PM UTC 24 |
Aug 29 01:06:38 PM UTC 24 |
6344150 ps |
| T467 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/4.xbar_random.2696374229 |
|
|
Aug 29 01:05:53 PM UTC 24 |
Aug 29 01:06:49 PM UTC 24 |
498204507 ps |
| T580 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/4.xbar_same_source.3242249597 |
|
|
Aug 29 01:06:20 PM UTC 24 |
Aug 29 01:06:50 PM UTC 24 |
293517891 ps |
| T620 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/4.xbar_unmapped_addr.1052103493 |
|
|
Aug 29 01:06:29 PM UTC 24 |
Aug 29 01:06:51 PM UTC 24 |
110137576 ps |
| T667 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/1.xbar_random_large_delays.3317345465 |
|
|
Aug 29 01:00:47 PM UTC 24 |
Aug 29 01:07:07 PM UTC 24 |
29087731110 ps |
| T575 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/3.chip_tl_errors.3917158378 |
|
|
Aug 29 01:02:58 PM UTC 24 |
Aug 29 01:07:21 PM UTC 24 |
3354729464 ps |
| T576 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/0.chip_tl_errors.27428673 |
|
|
Aug 29 01:00:23 PM UTC 24 |
Aug 29 01:07:26 PM UTC 24 |
4608531462 ps |
| T854 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/4.xbar_error_random.2786788195 |
|
|
Aug 29 01:06:24 PM UTC 24 |
Aug 29 01:07:31 PM UTC 24 |
624843215 ps |
| T1352 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/4.xbar_error_and_unmapped_addr.3444853132 |
|
|
Aug 29 01:06:29 PM UTC 24 |
Aug 29 01:07:38 PM UTC 24 |
1220612040 ps |
| T1353 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/3.chip_csr_bit_bash.3677080892 |
|
|
Aug 29 01:02:50 PM UTC 24 |
Aug 29 01:07:45 PM UTC 24 |
3875157394 ps |
| T1354 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/5.xbar_smoke.3188760130 |
|
|
Aug 29 01:07:50 PM UTC 24 |
Aug 29 01:07:57 PM UTC 24 |
44427157 ps |
| T1355 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/5.xbar_smoke_zero_delays.3087908121 |
|
|
Aug 29 01:07:56 PM UTC 24 |
Aug 29 01:08:05 PM UTC 24 |
41384590 ps |
| T668 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/4.xbar_smoke_large_delays.1310359970 |
|
|
Aug 29 01:05:48 PM UTC 24 |
Aug 29 01:08:05 PM UTC 24 |
8219458588 ps |
| T1356 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/1.chip_prim_tl_access.2939831347 |
|
|
Aug 29 01:00:31 PM UTC 24 |
Aug 29 01:08:08 PM UTC 24 |
9285184232 ps |
| T846 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/4.xbar_smoke_slow_rsp.781597317 |
|
|
Aug 29 01:05:53 PM UTC 24 |
Aug 29 01:08:10 PM UTC 24 |
5455577439 ps |
| T470 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/4.xbar_access_same_device.1481541093 |
|
|
Aug 29 01:06:04 PM UTC 24 |
Aug 29 01:08:38 PM UTC 24 |
3080198700 ps |
| T397 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/1.chip_csr_rw.1776306021 |
|
|
Aug 29 01:01:26 PM UTC 24 |
Aug 29 01:08:38 PM UTC 24 |
4619784680 ps |
| T665 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/5.xbar_random.3866946987 |
|
|
Aug 29 01:08:16 PM UTC 24 |
Aug 29 01:09:01 PM UTC 24 |
756564470 ps |
| T617 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/0.xbar_random_slow_rsp.3209237034 |
|
|
Aug 29 01:00:28 PM UTC 24 |
Aug 29 01:09:02 PM UTC 24 |
34840123473 ps |
| T796 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/5.xbar_access_same_device.2143348264 |
|
|
Aug 29 01:08:31 PM UTC 24 |
Aug 29 01:09:07 PM UTC 24 |
517236128 ps |
| T598 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/5.xbar_random_zero_delays.1066714309 |
|
|
Aug 29 01:08:25 PM UTC 24 |
Aug 29 01:09:23 PM UTC 24 |
501334219 ps |
| T613 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/5.xbar_smoke_large_delays.307729607 |
|
|
Aug 29 01:07:58 PM UTC 24 |
Aug 29 01:09:48 PM UTC 24 |
6932658692 ps |
| T611 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/5.xbar_same_source.2163340822 |
|
|
Aug 29 01:08:58 PM UTC 24 |
Aug 29 01:09:49 PM UTC 24 |
487081323 ps |
| T642 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/5.xbar_error_random.3925326747 |
|
|
Aug 29 01:09:22 PM UTC 24 |
Aug 29 01:09:51 PM UTC 24 |
244198417 ps |
| T1357 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/5.xbar_smoke_slow_rsp.92546720 |
|
|
Aug 29 01:08:04 PM UTC 24 |
Aug 29 01:10:01 PM UTC 24 |
5192587776 ps |
| T666 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/5.xbar_unmapped_addr.2739287418 |
|
|
Aug 29 01:09:23 PM UTC 24 |
Aug 29 01:10:06 PM UTC 24 |
734302758 ps |
| T643 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/5.xbar_error_and_unmapped_addr.3090134457 |
|
|
Aug 29 01:09:25 PM UTC 24 |
Aug 29 01:10:09 PM UTC 24 |
265717824 ps |
| T462 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/3.xbar_stress_all.3698777742 |
|
|
Aug 29 01:04:11 PM UTC 24 |
Aug 29 01:10:11 PM UTC 24 |
3527390606 ps |
| T577 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/4.chip_tl_errors.149842499 |
|
|
Aug 29 01:05:17 PM UTC 24 |
Aug 29 01:10:13 PM UTC 24 |
3272900225 ps |
| T502 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/1.xbar_stress_all_with_rand_reset.4288589820 |
|
|
Aug 29 01:01:08 PM UTC 24 |
Aug 29 01:10:21 PM UTC 24 |
7677768982 ps |
| T825 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/2.xbar_random_slow_rsp.2799744183 |
|
|
Aug 29 01:02:03 PM UTC 24 |
Aug 29 01:10:29 PM UTC 24 |
30535113757 ps |
| T1358 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/2.chip_rv_dm_lc_disabled.3311955094 |
|
|
Aug 29 01:01:36 PM UTC 24 |
Aug 29 01:10:38 PM UTC 24 |
9704590083 ps |
| T1359 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/6.xbar_smoke.78014020 |
|
|
Aug 29 01:10:31 PM UTC 24 |
Aug 29 01:10:43 PM UTC 24 |
149901753 ps |
| T791 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/5.xbar_random_slow_rsp.2367205865 |
|
|
Aug 29 01:08:28 PM UTC 24 |
Aug 29 01:10:43 PM UTC 24 |
6226932321 ps |
| T1360 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/6.xbar_smoke_zero_delays.3845646316 |
|
|
Aug 29 01:10:42 PM UTC 24 |
Aug 29 01:10:51 PM UTC 24 |
41839560 ps |
| T799 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/4.xbar_stress_all_with_error.2077817747 |
|
|
Aug 29 01:07:10 PM UTC 24 |
Aug 29 01:10:58 PM UTC 24 |
3514600033 ps |
| T174 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/0.chip_csr_rw.3766778177 |
|
|
Aug 29 01:00:28 PM UTC 24 |
Aug 29 01:11:42 PM UTC 24 |
6443085492 ps |
| T1361 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/0.chip_rv_dm_lc_disabled.446289631 |
|
|
Aug 29 01:00:24 PM UTC 24 |
Aug 29 01:11:45 PM UTC 24 |
19231129050 ps |
| T608 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/6.xbar_random_zero_delays.2524464723 |
|
|
Aug 29 01:11:03 PM UTC 24 |
Aug 29 01:11:47 PM UTC 24 |
318455890 ps |
| T581 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/2.xbar_stress_all_with_reset_error.555721691 |
|
|
Aug 29 01:02:38 PM UTC 24 |
Aug 29 01:11:54 PM UTC 24 |
9770361700 ps |
| T406 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/2.chip_csr_rw.2092850151 |
|
|
Aug 29 01:02:39 PM UTC 24 |
Aug 29 01:12:00 PM UTC 24 |
4545973550 ps |
| T468 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/5.xbar_stress_all.693647128 |
|
|
Aug 29 01:09:42 PM UTC 24 |
Aug 29 01:12:02 PM UTC 24 |
1455918002 ps |
| T601 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/6.xbar_random.3523881852 |
|
|
Aug 29 01:10:58 PM UTC 24 |
Aug 29 01:12:04 PM UTC 24 |
1870568414 ps |
| T858 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/4.xbar_stress_all_with_reset_error.4226243518 |
|
|
Aug 29 01:07:10 PM UTC 24 |
Aug 29 01:12:06 PM UTC 24 |
4465366209 ps |
| T855 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/6.xbar_smoke_slow_rsp.2600035191 |
|
|
Aug 29 01:10:49 PM UTC 24 |
Aug 29 01:12:10 PM UTC 24 |
3590131565 ps |
| T463 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/2.xbar_stress_all_with_rand_reset.849912822 |
|
|
Aug 29 01:02:20 PM UTC 24 |
Aug 29 01:12:12 PM UTC 24 |
3788585867 ps |
| T578 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/5.chip_tl_errors.2457879880 |
|
|
Aug 29 01:07:46 PM UTC 24 |
Aug 29 01:12:26 PM UTC 24 |
3423640218 ps |
| T797 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/2.xbar_stress_all_with_error.3024209265 |
|
|
Aug 29 01:02:30 PM UTC 24 |
Aug 29 01:12:37 PM UTC 24 |
13418549997 ps |
| T1362 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/6.xbar_error_and_unmapped_addr.313397647 |
|
|
Aug 29 01:12:14 PM UTC 24 |
Aug 29 01:12:42 PM UTC 24 |
261299474 ps |
| T1363 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/6.xbar_smoke_large_delays.1446980067 |
|
|
Aug 29 01:10:42 PM UTC 24 |
Aug 29 01:12:46 PM UTC 24 |
8972499493 ps |
| T792 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/6.xbar_access_same_device.2784462074 |
|
|
Aug 29 01:11:17 PM UTC 24 |
Aug 29 01:12:46 PM UTC 24 |
887942211 ps |
| T597 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/6.xbar_same_source.999134828 |
|
|
Aug 29 01:12:02 PM UTC 24 |
Aug 29 01:12:47 PM UTC 24 |
1024468674 ps |
| T603 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/1.xbar_random_slow_rsp.3516861048 |
|
|
Aug 29 01:00:50 PM UTC 24 |
Aug 29 01:12:48 PM UTC 24 |
42317309166 ps |
| T579 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/6.chip_tl_errors.2826309224 |
|
|
Aug 29 01:10:31 PM UTC 24 |
Aug 29 01:12:54 PM UTC 24 |
3157422776 ps |
| T1364 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/6.xbar_unmapped_addr.3377997206 |
|
|
Aug 29 01:12:07 PM UTC 24 |
Aug 29 01:13:08 PM UTC 24 |
1138488351 ps |
| T1365 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/7.xbar_smoke.3337769347 |
|
|
Aug 29 01:13:03 PM UTC 24 |
Aug 29 01:13:14 PM UTC 24 |
54328480 ps |
| T644 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/6.xbar_error_random.2777476712 |
|
|
Aug 29 01:12:05 PM UTC 24 |
Aug 29 01:13:15 PM UTC 24 |
581768382 ps |
| T1366 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/7.xbar_smoke_zero_delays.222221708 |
|
|
Aug 29 01:13:06 PM UTC 24 |
Aug 29 01:13:17 PM UTC 24 |
46712608 ps |
| T92 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/4.chip_csr_hw_reset.1025006786 |
|
|
Aug 29 01:07:12 PM UTC 24 |
Aug 29 01:13:20 PM UTC 24 |
6412414905 ps |
| T93 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/3.chip_csr_hw_reset.2633485081 |
|
|
Aug 29 01:04:39 PM UTC 24 |
Aug 29 01:13:23 PM UTC 24 |
6713568769 ps |
| T624 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/7.xbar_random.3195933366 |
|
|
Aug 29 01:13:05 PM UTC 24 |
Aug 29 01:13:26 PM UTC 24 |
153874414 ps |
| T1367 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/1.chip_rv_dm_lc_disabled.1664947146 |
|
|
Aug 29 01:00:30 PM UTC 24 |
Aug 29 01:13:37 PM UTC 24 |
11787137314 ps |
| T873 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/5.xbar_stress_all_with_reset_error.1377189715 |
|
|
Aug 29 01:10:12 PM UTC 24 |
Aug 29 01:13:42 PM UTC 24 |
2973156528 ps |
| T420 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/3.chip_csr_mem_rw_with_rand_reset.4166477422 |
|
|
Aug 29 01:04:48 PM UTC 24 |
Aug 29 01:13:44 PM UTC 24 |
6958731322 ps |
| T482 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/4.xbar_stress_all_with_rand_reset.2177693651 |
|
|
Aug 29 01:06:58 PM UTC 24 |
Aug 29 01:13:46 PM UTC 24 |
2680348252 ps |
| T616 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/2.xbar_random_large_delays.1655745837 |
|
|
Aug 29 01:01:53 PM UTC 24 |
Aug 29 01:14:03 PM UTC 24 |
66487015515 ps |
| T421 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/5.chip_csr_rw.1994778522 |
|
|
Aug 29 01:10:21 PM UTC 24 |
Aug 29 01:14:03 PM UTC 24 |
3958393933 ps |
| T1368 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/7.xbar_unmapped_addr.2684327705 |
|
|
Aug 29 01:13:49 PM UTC 24 |
Aug 29 01:14:06 PM UTC 24 |
164237608 ps |
| T504 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/7.xbar_random_zero_delays.859476619 |
|
|
Aug 29 01:13:13 PM UTC 24 |
Aug 29 01:14:14 PM UTC 24 |
364693056 ps |
| T1369 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/7.xbar_smoke_large_delays.3400261346 |
|
|
Aug 29 01:13:04 PM UTC 24 |
Aug 29 01:14:15 PM UTC 24 |
7289995100 ps |
| T422 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/3.chip_csr_rw.2059491970 |
|
|
Aug 29 01:04:42 PM UTC 24 |
Aug 29 01:14:23 PM UTC 24 |
5791830590 ps |
| T821 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/6.xbar_access_same_device_slow_rsp.4193709027 |
|
|
Aug 29 01:11:47 PM UTC 24 |
Aug 29 01:14:24 PM UTC 24 |
7948444255 ps |
| T1370 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/7.xbar_same_source.228283051 |
|
|
Aug 29 01:13:44 PM UTC 24 |
Aug 29 01:14:25 PM UTC 24 |
941238370 ps |
| T862 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/6.xbar_stress_all_with_rand_reset.1116698244 |
|
|
Aug 29 01:12:21 PM UTC 24 |
Aug 29 01:14:25 PM UTC 24 |
539723298 ps |
| T508 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/3.xbar_random_large_delays.2075274179 |
|
|
Aug 29 01:03:30 PM UTC 24 |
Aug 29 01:14:32 PM UTC 24 |
65940733104 ps |
| T1371 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/7.xbar_error_and_unmapped_addr.784293478 |
|
|
Aug 29 01:13:55 PM UTC 24 |
Aug 29 01:14:39 PM UTC 24 |
300036136 ps |
| T604 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/8.xbar_smoke.3639660668 |
|
|
Aug 29 01:14:35 PM UTC 24 |
Aug 29 01:14:46 PM UTC 24 |
57742273 ps |
| T833 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/5.xbar_stress_all_with_rand_reset.2993171145 |
|
|
Aug 29 01:10:08 PM UTC 24 |
Aug 29 01:14:49 PM UTC 24 |
623349281 ps |
| T1372 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/8.xbar_smoke_zero_delays.3827775553 |
|
|
Aug 29 01:14:42 PM UTC 24 |
Aug 29 01:14:51 PM UTC 24 |
37285971 ps |
| T595 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/7.xbar_stress_all.3762723953 |
|
|
Aug 29 01:14:02 PM UTC 24 |
Aug 29 01:14:52 PM UTC 24 |
313317635 ps |
| T1373 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/7.xbar_smoke_slow_rsp.4077176945 |
|
|
Aug 29 01:13:06 PM UTC 24 |
Aug 29 01:15:02 PM UTC 24 |
4829940661 ps |
| T1374 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/8.xbar_random_zero_delays.2173462207 |
|
|
Aug 29 01:14:52 PM UTC 24 |
Aug 29 01:15:18 PM UTC 24 |
164961224 ps |
| T471 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/8.xbar_random.4105727596 |
|
|
Aug 29 01:14:44 PM UTC 24 |
Aug 29 01:15:19 PM UTC 24 |
335469710 ps |
| T464 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/7.xbar_access_same_device.2390218410 |
|
|
Aug 29 01:13:39 PM UTC 24 |
Aug 29 01:15:20 PM UTC 24 |
2267149878 ps |
| T645 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/7.xbar_error_random.571735587 |
|
|
Aug 29 01:13:47 PM UTC 24 |
Aug 29 01:15:22 PM UTC 24 |
2078300596 ps |
| T826 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/4.xbar_access_same_device_slow_rsp.941905359 |
|
|
Aug 29 01:06:13 PM UTC 24 |
Aug 29 01:15:23 PM UTC 24 |
30633774062 ps |
| T614 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/6.xbar_random_large_delays.573603124 |
|
|
Aug 29 01:11:03 PM UTC 24 |
Aug 29 01:15:24 PM UTC 24 |
25013594797 ps |
| T1375 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/8.xbar_unmapped_addr.2767105507 |
|
|
Aug 29 01:15:38 PM UTC 24 |
Aug 29 01:15:49 PM UTC 24 |
82191356 ps |
| T1376 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/8.xbar_error_random.2665514083 |
|
|
Aug 29 01:15:22 PM UTC 24 |
Aug 29 01:15:55 PM UTC 24 |
587505834 ps |
| T465 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/4.xbar_random_slow_rsp.3740051322 |
|
|
Aug 29 01:06:03 PM UTC 24 |
Aug 29 01:16:11 PM UTC 24 |
28393337979 ps |
| T628 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/8.xbar_smoke_slow_rsp.628196013 |
|
|
Aug 29 01:14:45 PM UTC 24 |
Aug 29 01:16:11 PM UTC 24 |
5141581142 ps |
| T539 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/8.xbar_same_source.2573269699 |
|
|
Aug 29 01:15:13 PM UTC 24 |
Aug 29 01:16:14 PM UTC 24 |
588395387 ps |
| T423 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/4.chip_csr_mem_rw_with_rand_reset.1992645848 |
|
|
Aug 29 01:07:31 PM UTC 24 |
Aug 29 01:16:18 PM UTC 24 |
5670284600 ps |
| T1377 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/8.xbar_error_and_unmapped_addr.2685712289 |
|
|
Aug 29 01:15:38 PM UTC 24 |
Aug 29 01:16:23 PM UTC 24 |
684934208 ps |
| T1378 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/7.xbar_random_large_delays.2760816676 |
|
|
Aug 29 01:13:28 PM UTC 24 |
Aug 29 01:16:29 PM UTC 24 |
16702655984 ps |
| T827 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/8.xbar_random_large_delays.981834758 |
|
|
Aug 29 01:14:59 PM UTC 24 |
Aug 29 01:16:30 PM UTC 24 |
5682413369 ps |
| T1379 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/8.xbar_smoke_large_delays.1031424407 |
|
|
Aug 29 01:14:45 PM UTC 24 |
Aug 29 01:16:43 PM UTC 24 |
7655562495 ps |
| T1380 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/9.xbar_smoke.3398340220 |
|
|
Aug 29 01:16:34 PM UTC 24 |
Aug 29 01:16:47 PM UTC 24 |
163857461 ps |
| T874 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/8.xbar_stress_all_with_rand_reset.692141549 |
|
|
Aug 29 01:15:44 PM UTC 24 |
Aug 29 01:16:47 PM UTC 24 |
79463076 ps |
| T1381 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/9.xbar_smoke_zero_delays.250858633 |
|
|
Aug 29 01:16:38 PM UTC 24 |
Aug 29 01:16:48 PM UTC 24 |
53515863 ps |
| T572 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/7.chip_tl_errors.3035220860 |
|
|
Aug 29 01:12:57 PM UTC 24 |
Aug 29 01:17:30 PM UTC 24 |
3650198032 ps |
| T882 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/8.xbar_stress_all_with_reset_error.2509343804 |
|
|
Aug 29 01:15:44 PM UTC 24 |
Aug 29 01:17:11 PM UTC 24 |
251824581 ps |
| T804 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/8.xbar_access_same_device.2568038101 |
|
|
Aug 29 01:15:09 PM UTC 24 |
Aug 29 01:17:38 PM UTC 24 |
3607211431 ps |
| T1382 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/9.xbar_smoke_large_delays.3191424288 |
|
|
Aug 29 01:16:43 PM UTC 24 |
Aug 29 01:17:54 PM UTC 24 |
5439767857 ps |
| T622 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/9.xbar_random_zero_delays.1168924215 |
|
|
Aug 29 01:17:00 PM UTC 24 |
Aug 29 01:17:58 PM UTC 24 |
430111725 ps |
| T1383 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/9.xbar_random.1880944047 |
|
|
Aug 29 01:16:50 PM UTC 24 |
Aug 29 01:18:06 PM UTC 24 |
1465801724 ps |
| T1384 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/9.xbar_smoke_slow_rsp.3064118498 |
|
|
Aug 29 01:16:49 PM UTC 24 |
Aug 29 01:18:11 PM UTC 24 |
5166723562 ps |
| T542 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/6.xbar_stress_all.4130511945 |
|
|
Aug 29 01:12:20 PM UTC 24 |
Aug 29 01:18:13 PM UTC 24 |
10794758706 ps |
| T839 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/9.xbar_access_same_device.2214722343 |
|
|
Aug 29 01:17:09 PM UTC 24 |
Aug 29 01:18:15 PM UTC 24 |
1096649463 ps |
| T533 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/9.xbar_same_source.773044157 |
|
|
Aug 29 01:17:50 PM UTC 24 |
Aug 29 01:18:16 PM UTC 24 |
188884987 ps |
| T646 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/3.xbar_stress_all_with_reset_error.2521300639 |
|
|
Aug 29 01:04:38 PM UTC 24 |
Aug 29 01:18:25 PM UTC 24 |
7426423831 ps |
| T793 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/5.xbar_stress_all_with_error.3591916947 |
|
|
Aug 29 01:10:08 PM UTC 24 |
Aug 29 01:18:31 PM UTC 24 |
13348791119 ps |
| T844 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/7.xbar_stress_all_with_reset_error.1921491719 |
|
|
Aug 29 01:14:06 PM UTC 24 |
Aug 29 01:18:34 PM UTC 24 |
3062135441 ps |
| T1385 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/9.xbar_unmapped_addr.868797755 |
|
|
Aug 29 01:18:14 PM UTC 24 |
Aug 29 01:18:37 PM UTC 24 |
127841219 ps |
| T407 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/4.chip_csr_rw.2608354345 |
|
|
Aug 29 01:07:28 PM UTC 24 |
Aug 29 01:18:41 PM UTC 24 |
6384486610 ps |
| T1386 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/9.xbar_error_random.4082367957 |
|
|
Aug 29 01:17:58 PM UTC 24 |
Aug 29 01:18:48 PM UTC 24 |
507996660 ps |
| T424 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/2.chip_csr_mem_rw_with_rand_reset.3068000345 |
|
|
Aug 29 01:02:47 PM UTC 24 |
Aug 29 01:18:54 PM UTC 24 |
12252142008 ps |
| T1387 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/10.xbar_smoke.1964269361 |
|
|
Aug 29 01:18:54 PM UTC 24 |
Aug 29 01:19:04 PM UTC 24 |
45060101 ps |
| T1388 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/10.xbar_smoke_zero_delays.2980124654 |
|
|
Aug 29 01:18:56 PM UTC 24 |
Aug 29 01:19:05 PM UTC 24 |
44487901 ps |
| T408 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/1.chip_csr_mem_rw_with_rand_reset.1872744899 |
|
|
Aug 29 01:01:25 PM UTC 24 |
Aug 29 01:19:11 PM UTC 24 |
10684909958 ps |
| T1389 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/9.xbar_error_and_unmapped_addr.3320925167 |
|
|
Aug 29 01:18:19 PM UTC 24 |
Aug 29 01:19:24 PM UTC 24 |
1200614727 ps |
| T585 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/9.chip_tl_errors.1904256141 |
|
|
Aug 29 01:16:31 PM UTC 24 |
Aug 29 01:19:26 PM UTC 24 |
3037999374 ps |
| T600 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/10.xbar_random.1426927849 |
|
|
Aug 29 01:19:14 PM UTC 24 |
Aug 29 01:19:40 PM UTC 24 |
311972076 ps |
| T487 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/9.xbar_stress_all.3022066803 |
|
|
Aug 29 01:18:26 PM UTC 24 |
Aug 29 01:19:52 PM UTC 24 |
699741288 ps |
| T1390 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/9.xbar_random_slow_rsp.2516579535 |
|
|
Aug 29 01:17:08 PM UTC 24 |
Aug 29 01:20:02 PM UTC 24 |
11090561352 ps |
| T621 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/10.xbar_random_zero_delays.2168026167 |
|
|
Aug 29 01:19:19 PM UTC 24 |
Aug 29 01:20:11 PM UTC 24 |
392274070 ps |
| T831 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/7.xbar_stress_all_with_error.3304898142 |
|
|
Aug 29 01:14:07 PM UTC 24 |
Aug 29 01:20:17 PM UTC 24 |
10402124554 ps |
| T794 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/6.xbar_stress_all_with_error.1688519272 |
|
|
Aug 29 01:12:24 PM UTC 24 |
Aug 29 01:20:21 PM UTC 24 |
9154186705 ps |
| T816 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/10.xbar_access_same_device.3454625641 |
|
|
Aug 29 01:19:31 PM UTC 24 |
Aug 29 01:20:32 PM UTC 24 |
1268015093 ps |
| T1391 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/10.xbar_error_and_unmapped_addr.1172585704 |
|
|
Aug 29 01:20:22 PM UTC 24 |
Aug 29 01:20:41 PM UTC 24 |
217747854 ps |
| T584 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/10.xbar_same_source.2528468096 |
|
|
Aug 29 01:19:46 PM UTC 24 |
Aug 29 01:20:51 PM UTC 24 |
1609936493 ps |
| T1392 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/10.xbar_unmapped_addr.3698658996 |
|
|
Aug 29 01:20:13 PM UTC 24 |
Aug 29 01:21:02 PM UTC 24 |
1116383406 ps |
| T461 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/8.chip_csr_rw.57316490 |
|
|
Aug 29 01:16:10 PM UTC 24 |
Aug 29 01:21:05 PM UTC 24 |
4448287024 ps |
| T1393 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/9.xbar_random_large_delays.3222144961 |
|
|
Aug 29 01:17:08 PM UTC 24 |
Aug 29 01:21:07 PM UTC 24 |
23492338459 ps |
| T1394 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/10.xbar_smoke_slow_rsp.3317278076 |
|
|
Aug 29 01:19:09 PM UTC 24 |
Aug 29 01:21:08 PM UTC 24 |
5901792903 ps |
| T619 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/10.xbar_error_random.2895801572 |
|
|
Aug 29 01:20:00 PM UTC 24 |
Aug 29 01:21:17 PM UTC 24 |
2091777728 ps |
| T1395 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/4.xbar_random_large_delays.1387579608 |
|
|
Aug 29 01:05:56 PM UTC 24 |
Aug 29 01:21:22 PM UTC 24 |
75612666652 ps |
| T1396 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/10.xbar_smoke_large_delays.424452201 |
|
|
Aug 29 01:19:01 PM UTC 24 |
Aug 29 01:21:24 PM UTC 24 |
9223580180 ps |
| T812 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/5.xbar_access_same_device_slow_rsp.1689001752 |
|
|
Aug 29 01:08:58 PM UTC 24 |
Aug 29 01:21:24 PM UTC 24 |
40028516167 ps |
| T544 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/6.chip_csr_mem_rw_with_rand_reset.2114096914 |
|
|
Aug 29 01:12:33 PM UTC 24 |
Aug 29 01:21:24 PM UTC 24 |
6256252872 ps |
| T817 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/6.xbar_stress_all_with_reset_error.1374362877 |
|
|
Aug 29 01:12:25 PM UTC 24 |
Aug 29 01:21:34 PM UTC 24 |
7096035710 ps |
| T1397 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/11.xbar_smoke_zero_delays.3635648720 |
|
|
Aug 29 01:21:28 PM UTC 24 |
Aug 29 01:21:35 PM UTC 24 |
42749061 ps |
| T476 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/11.xbar_smoke.4261297082 |
|
|
Aug 29 01:21:27 PM UTC 24 |
Aug 29 01:21:41 PM UTC 24 |
228061149 ps |
| T1398 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/11.xbar_random.2162091132 |
|
|
Aug 29 01:21:44 PM UTC 24 |
Aug 29 01:21:54 PM UTC 24 |
38100849 ps |
| T402 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/0.chip_csr_mem_rw_with_rand_reset.3527378060 |
|
|
Aug 29 01:00:29 PM UTC 24 |
Aug 29 01:21:56 PM UTC 24 |
12170966509 ps |
| T573 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/8.chip_tl_errors.853124778 |
|
|
Aug 29 01:14:35 PM UTC 24 |
Aug 29 01:22:08 PM UTC 24 |
5018362545 ps |
| T1399 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/11.xbar_access_same_device.792823189 |
|
|
Aug 29 01:21:54 PM UTC 24 |
Aug 29 01:22:19 PM UTC 24 |
220147051 ps |
| T586 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/10.chip_tl_errors.3248119860 |
|
|
Aug 29 01:18:48 PM UTC 24 |
Aug 29 01:22:30 PM UTC 24 |
3820823527 ps |
| T596 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/11.xbar_random_zero_delays.2392496319 |
|
|
Aug 29 01:21:44 PM UTC 24 |
Aug 29 01:22:51 PM UTC 24 |
546929973 ps |
| T521 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/11.xbar_same_source.2020712044 |
|
|
Aug 29 01:22:14 PM UTC 24 |
Aug 29 01:22:53 PM UTC 24 |
928933829 ps |
| T1400 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/11.xbar_error_random.1977186336 |
|
|
Aug 29 01:22:15 PM UTC 24 |
Aug 29 01:22:58 PM UTC 24 |
345385956 ps |
| T1401 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/9.xbar_stress_all_with_error.2307336302 |
|
|
Aug 29 01:18:33 PM UTC 24 |
Aug 29 01:22:59 PM UTC 24 |
8122422877 ps |
| T813 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/0.xbar_access_same_device_slow_rsp.2231519793 |
|
|
Aug 29 01:00:27 PM UTC 24 |
Aug 29 01:23:05 PM UTC 24 |
77248774547 ps |
| T592 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/11.xbar_random_slow_rsp.3957080614 |
|
|
Aug 29 01:21:52 PM UTC 24 |
Aug 29 01:23:06 PM UTC 24 |
3458870697 ps |
| T523 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/8.xbar_stress_all.3240978461 |
|
|
Aug 29 01:15:40 PM UTC 24 |
Aug 29 01:23:09 PM UTC 24 |
9557440306 ps |
| T1402 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/11.xbar_error_and_unmapped_addr.769609516 |
|
|
Aug 29 01:22:39 PM UTC 24 |
Aug 29 01:23:12 PM UTC 24 |
325842481 ps |
| T1403 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/11.xbar_unmapped_addr.3621118355 |
|
|
Aug 29 01:22:29 PM UTC 24 |
Aug 29 01:23:15 PM UTC 24 |
281277107 ps |
| T1404 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/11.xbar_smoke_slow_rsp.2557460502 |
|
|
Aug 29 01:21:42 PM UTC 24 |
Aug 29 01:23:20 PM UTC 24 |
5739206283 ps |
| T856 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/9.xbar_stress_all_with_reset_error.2661010745 |
|
|
Aug 29 01:18:35 PM UTC 24 |
Aug 29 01:23:21 PM UTC 24 |
6144132993 ps |
| T1405 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/10.xbar_stress_all.3687870754 |
|
|
Aug 29 01:20:31 PM UTC 24 |
Aug 29 01:23:22 PM UTC 24 |
3598012036 ps |
| T626 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/9.xbar_stress_all_with_rand_reset.2243662280 |
|
|
Aug 29 01:18:31 PM UTC 24 |
Aug 29 01:23:24 PM UTC 24 |
5360021996 ps |
| T1406 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/11.xbar_smoke_large_delays.2680031056 |
|
|
Aug 29 01:21:37 PM UTC 24 |
Aug 29 01:23:30 PM UTC 24 |
7271928282 ps |
| T589 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/6.xbar_random_slow_rsp.4214662166 |
|
|
Aug 29 01:11:11 PM UTC 24 |
Aug 29 01:23:44 PM UTC 24 |
48713389630 ps |
| T1407 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/12.xbar_smoke.2682162231 |
|
|
Aug 29 01:23:31 PM UTC 24 |
Aug 29 01:23:45 PM UTC 24 |
207843154 ps |
| T492 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/12.xbar_smoke_zero_delays.2161815755 |
|
|
Aug 29 01:23:35 PM UTC 24 |
Aug 29 01:23:46 PM UTC 24 |
52506948 ps |
| T1408 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/7.chip_csr_mem_rw_with_rand_reset.1992596658 |
|
|
Aug 29 01:14:23 PM UTC 24 |
Aug 29 01:24:01 PM UTC 24 |
8333791446 ps |
| T1409 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/12.xbar_random_zero_delays.3548666135 |
|
|
Aug 29 01:23:44 PM UTC 24 |
Aug 29 01:24:06 PM UTC 24 |
153253182 ps |
| T503 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/11.xbar_stress_all.2678828425 |
|
|
Aug 29 01:22:49 PM UTC 24 |
Aug 29 01:24:08 PM UTC 24 |
657817409 ps |
| T1410 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/12.xbar_random.4196673699 |
|
|
Aug 29 01:23:42 PM UTC 24 |
Aug 29 01:24:09 PM UTC 24 |
622009864 ps |
| T1411 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/7.xbar_random_slow_rsp.340703631 |
|
|
Aug 29 01:13:34 PM UTC 24 |
Aug 29 01:24:11 PM UTC 24 |
36793570221 ps |
| T814 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/10.xbar_stress_all_with_reset_error.1143439089 |
|
|
Aug 29 01:20:50 PM UTC 24 |
Aug 29 01:24:31 PM UTC 24 |
2919265717 ps |
| T1412 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/11.xbar_random_large_delays.64473249 |
|
|
Aug 29 01:21:43 PM UTC 24 |
Aug 29 01:24:31 PM UTC 24 |
10992212616 ps |
| T1413 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/12.xbar_smoke_slow_rsp.1461903544 |
|
|
Aug 29 01:23:41 PM UTC 24 |
Aug 29 01:24:43 PM UTC 24 |
4010949405 ps |
| T1414 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/12.xbar_error_and_unmapped_addr.2248219191 |
|
|
Aug 29 01:24:30 PM UTC 24 |
Aug 29 01:24:51 PM UTC 24 |
298104177 ps |
| T1415 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/12.xbar_smoke_large_delays.438565144 |
|
|
Aug 29 01:23:41 PM UTC 24 |
Aug 29 01:24:52 PM UTC 24 |
5730145832 ps |
| T1416 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/12.xbar_same_source.2693617234 |
|
|
Aug 29 01:24:21 PM UTC 24 |
Aug 29 01:24:57 PM UTC 24 |
704580572 ps |