| T1577 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/16.xbar_random_large_delays.4229431700 |
|
|
Aug 29 01:34:11 PM UTC 24 |
Aug 29 01:52:23 PM UTC 24 |
79844138693 ps |
| T1578 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/24.xbar_smoke_large_delays.940960298 |
|
|
Aug 29 01:51:01 PM UTC 24 |
Aug 29 01:52:30 PM UTC 24 |
6222679190 ps |
| T1579 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/24.xbar_smoke_slow_rsp.1431937170 |
|
|
Aug 29 01:51:00 PM UTC 24 |
Aug 29 01:52:37 PM UTC 24 |
4326387457 ps |
| T1580 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/25.xbar_smoke.3465154015 |
|
|
Aug 29 01:52:23 PM UTC 24 |
Aug 29 01:52:38 PM UTC 24 |
213498454 ps |
| T1581 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/25.xbar_smoke_zero_delays.1722254760 |
|
|
Aug 29 01:52:32 PM UTC 24 |
Aug 29 01:52:42 PM UTC 24 |
50182778 ps |
| T1582 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/22.xbar_stress_all_with_rand_reset.1102461692 |
|
|
Aug 29 01:49:01 PM UTC 24 |
Aug 29 01:52:45 PM UTC 24 |
1645555811 ps |
| T863 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/23.xbar_stress_all_with_reset_error.3485547491 |
|
|
Aug 29 01:50:43 PM UTC 24 |
Aug 29 01:52:48 PM UTC 24 |
297211536 ps |
| T657 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/23.chip_tl_errors.4219957891 |
|
|
Aug 29 01:49:10 PM UTC 24 |
Aug 29 01:53:07 PM UTC 24 |
3222895090 ps |
| T869 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/24.xbar_stress_all_with_rand_reset.141735644 |
|
|
Aug 29 01:52:01 PM UTC 24 |
Aug 29 01:53:14 PM UTC 24 |
187691837 ps |
| T1583 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/25.xbar_error_random.2793024458 |
|
|
Aug 29 01:53:08 PM UTC 24 |
Aug 29 01:53:20 PM UTC 24 |
99383355 ps |
| T518 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/25.xbar_random_zero_delays.2750202743 |
|
|
Aug 29 01:52:39 PM UTC 24 |
Aug 29 01:53:29 PM UTC 24 |
629101931 ps |
| T1584 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/25.xbar_same_source.2360341495 |
|
|
Aug 29 01:53:04 PM UTC 24 |
Aug 29 01:53:33 PM UTC 24 |
556289716 ps |
| T1585 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/25.xbar_error_and_unmapped_addr.1580437926 |
|
|
Aug 29 01:53:34 PM UTC 24 |
Aug 29 01:53:44 PM UTC 24 |
25345243 ps |
| T1586 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/24.xbar_stress_all.4069727102 |
|
|
Aug 29 01:51:58 PM UTC 24 |
Aug 29 01:53:50 PM UTC 24 |
2836236154 ps |
| T1587 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/25.xbar_stress_all_with_error.395716897 |
|
|
Aug 29 01:53:54 PM UTC 24 |
Aug 29 01:54:01 PM UTC 24 |
5517701 ps |
| T520 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/25.xbar_random.1324847285 |
|
|
Aug 29 01:52:41 PM UTC 24 |
Aug 29 01:54:04 PM UTC 24 |
1770093686 ps |
| T1588 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/25.xbar_smoke_slow_rsp.1207517846 |
|
|
Aug 29 01:52:37 PM UTC 24 |
Aug 29 01:54:13 PM UTC 24 |
6421057204 ps |
| T1589 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/25.xbar_smoke_large_delays.2170905927 |
|
|
Aug 29 01:52:36 PM UTC 24 |
Aug 29 01:54:16 PM UTC 24 |
6369602922 ps |
| T1590 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/26.xbar_smoke.2475456401 |
|
|
Aug 29 01:54:19 PM UTC 24 |
Aug 29 01:54:29 PM UTC 24 |
56831893 ps |
| T1591 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/25.xbar_unmapped_addr.1813814210 |
|
|
Aug 29 01:53:27 PM UTC 24 |
Aug 29 01:54:32 PM UTC 24 |
1125347892 ps |
| T1592 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/26.xbar_smoke_zero_delays.948071113 |
|
|
Aug 29 01:54:24 PM UTC 24 |
Aug 29 01:54:34 PM UTC 24 |
57778038 ps |
| T808 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/25.xbar_access_same_device.1240525313 |
|
|
Aug 29 01:52:58 PM UTC 24 |
Aug 29 01:54:39 PM UTC 24 |
2123928452 ps |
| T1593 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/26.xbar_random.1830281380 |
|
|
Aug 29 01:54:50 PM UTC 24 |
Aug 29 01:55:13 PM UTC 24 |
158458279 ps |
| T1594 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/22.xbar_stress_all_with_error.143994555 |
|
|
Aug 29 01:49:03 PM UTC 24 |
Aug 29 01:55:41 PM UTC 24 |
4323949109 ps |
| T1595 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/22.xbar_stress_all.3950725052 |
|
|
Aug 29 01:48:54 PM UTC 24 |
Aug 29 01:55:42 PM UTC 24 |
3891069397 ps |
| T396 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/13.chip_same_csr_outstanding.1100417874 |
|
|
Aug 29 01:25:16 PM UTC 24 |
Aug 29 01:55:43 PM UTC 24 |
16077833196 ps |
| T1596 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/24.xbar_random_slow_rsp.1962235838 |
|
|
Aug 29 01:51:14 PM UTC 24 |
Aug 29 01:55:44 PM UTC 24 |
16205273051 ps |
| T525 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/26.xbar_random_zero_delays.3862797025 |
|
|
Aug 29 01:54:53 PM UTC 24 |
Aug 29 01:55:44 PM UTC 24 |
429990543 ps |
| T860 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/24.xbar_stress_all_with_reset_error.3576200489 |
|
|
Aug 29 01:52:17 PM UTC 24 |
Aug 29 01:56:00 PM UTC 24 |
2338789866 ps |
| T1597 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/24.xbar_stress_all_with_error.545252637 |
|
|
Aug 29 01:52:10 PM UTC 24 |
Aug 29 01:56:01 PM UTC 24 |
5674735730 ps |
| T1598 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/20.xbar_random_slow_rsp.3059862294 |
|
|
Aug 29 01:44:39 PM UTC 24 |
Aug 29 01:56:22 PM UTC 24 |
37683502993 ps |
| T1599 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/24.xbar_random_large_delays.2527360219 |
|
|
Aug 29 01:51:13 PM UTC 24 |
Aug 29 01:56:30 PM UTC 24 |
21755119984 ps |
| T1600 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/26.xbar_error_random.4207857532 |
|
|
Aug 29 01:56:05 PM UTC 24 |
Aug 29 01:56:34 PM UTC 24 |
652417309 ps |
| T528 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/26.xbar_access_same_device.45606182 |
|
|
Aug 29 01:55:33 PM UTC 24 |
Aug 29 01:56:43 PM UTC 24 |
586096596 ps |
| T1601 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/26.xbar_unmapped_addr.1753645598 |
|
|
Aug 29 01:56:01 PM UTC 24 |
Aug 29 01:56:45 PM UTC 24 |
771416444 ps |
| T1602 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/18.xbar_random_slow_rsp.1405521132 |
|
|
Aug 29 01:39:34 PM UTC 24 |
Aug 29 01:56:49 PM UTC 24 |
65599106278 ps |
| T1603 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/26.xbar_smoke_slow_rsp.2200673180 |
|
|
Aug 29 01:54:37 PM UTC 24 |
Aug 29 01:56:49 PM UTC 24 |
5351829303 ps |
| T1604 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/26.xbar_smoke_large_delays.1797834205 |
|
|
Aug 29 01:54:34 PM UTC 24 |
Aug 29 01:57:03 PM UTC 24 |
9231807039 ps |
| T1605 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/27.xbar_smoke.1500054900 |
|
|
Aug 29 01:57:03 PM UTC 24 |
Aug 29 01:57:12 PM UTC 24 |
172113908 ps |
| T1606 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/26.xbar_error_and_unmapped_addr.3082464168 |
|
|
Aug 29 01:56:04 PM UTC 24 |
Aug 29 01:57:12 PM UTC 24 |
1220367112 ps |
| T1607 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/18.chip_csr_mem_rw_with_rand_reset.826891597 |
|
|
Aug 29 01:40:56 PM UTC 24 |
Aug 29 01:57:12 PM UTC 24 |
11116142425 ps |
| T1608 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/27.xbar_smoke_zero_delays.4041200120 |
|
|
Aug 29 01:57:05 PM UTC 24 |
Aug 29 01:57:16 PM UTC 24 |
45389720 ps |
| T1609 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/26.xbar_same_source.3391648533 |
|
|
Aug 29 01:56:03 PM UTC 24 |
Aug 29 01:57:21 PM UTC 24 |
1885623801 ps |
| T801 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/16.xbar_access_same_device_slow_rsp.822597110 |
|
|
Aug 29 01:34:32 PM UTC 24 |
Aug 29 01:57:36 PM UTC 24 |
80020315352 ps |
| T497 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/22.xbar_random_slow_rsp.2652253506 |
|
|
Aug 29 01:48:09 PM UTC 24 |
Aug 29 01:57:38 PM UTC 24 |
34445469729 ps |
| T1610 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/12.chip_same_csr_outstanding.2634478842 |
|
|
Aug 29 01:23:25 PM UTC 24 |
Aug 29 01:57:39 PM UTC 24 |
15773220266 ps |
| T1611 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/26.chip_tl_errors.2720494996 |
|
|
Aug 29 01:54:10 PM UTC 24 |
Aug 29 01:57:39 PM UTC 24 |
3088504176 ps |
| T1612 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/25.chip_tl_errors.1380168331 |
|
|
Aug 29 01:52:20 PM UTC 24 |
Aug 29 01:57:39 PM UTC 24 |
4835685875 ps |
| T837 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/23.xbar_stress_all.991760511 |
|
|
Aug 29 01:49:53 PM UTC 24 |
Aug 29 01:57:43 PM UTC 24 |
13748040852 ps |
| T1613 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/24.chip_tl_errors.3852032564 |
|
|
Aug 29 01:50:48 PM UTC 24 |
Aug 29 01:57:59 PM UTC 24 |
4261242160 ps |
| T531 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/19.xbar_random_slow_rsp.581443768 |
|
|
Aug 29 01:42:17 PM UTC 24 |
Aug 29 01:58:01 PM UTC 24 |
52637145620 ps |
| T485 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/25.xbar_random_large_delays.2334839750 |
|
|
Aug 29 01:52:50 PM UTC 24 |
Aug 29 01:58:02 PM UTC 24 |
25346489392 ps |
| T1614 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/26.xbar_stress_all.2919111790 |
|
|
Aug 29 01:56:20 PM UTC 24 |
Aug 29 01:58:07 PM UTC 24 |
2355747870 ps |
| T1615 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/27.xbar_random.1813569856 |
|
|
Aug 29 01:57:23 PM UTC 24 |
Aug 29 01:58:17 PM UTC 24 |
1095095278 ps |
| T1616 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/27.xbar_error_and_unmapped_addr.163351197 |
|
|
Aug 29 01:58:00 PM UTC 24 |
Aug 29 01:58:20 PM UTC 24 |
98771313 ps |
| T1617 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/21.xbar_random_large_delays.1677741160 |
|
|
Aug 29 01:46:33 PM UTC 24 |
Aug 29 01:58:20 PM UTC 24 |
68881879878 ps |
| T1618 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/27.xbar_error_random.114396426 |
|
|
Aug 29 01:57:59 PM UTC 24 |
Aug 29 01:58:23 PM UTC 24 |
186341191 ps |
| T852 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/23.xbar_stress_all_with_error.2990168869 |
|
|
Aug 29 01:50:35 PM UTC 24 |
Aug 29 01:58:32 PM UTC 24 |
11159857298 ps |
| T1619 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/28.xbar_smoke.635505223 |
|
|
Aug 29 01:58:27 PM UTC 24 |
Aug 29 01:58:41 PM UTC 24 |
209924691 ps |
| T1620 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/20.xbar_stress_all_with_error.2564464535 |
|
|
Aug 29 01:45:47 PM UTC 24 |
Aug 29 01:58:46 PM UTC 24 |
16385168475 ps |
| T1621 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/27.xbar_random_zero_delays.2427976200 |
|
|
Aug 29 01:57:31 PM UTC 24 |
Aug 29 01:58:47 PM UTC 24 |
609546490 ps |
| T1622 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/28.xbar_smoke_zero_delays.2939256137 |
|
|
Aug 29 01:58:37 PM UTC 24 |
Aug 29 01:58:50 PM UTC 24 |
58144481 ps |
| T1623 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/27.xbar_same_source.1949749123 |
|
|
Aug 29 01:57:56 PM UTC 24 |
Aug 29 01:59:00 PM UTC 24 |
1535826953 ps |
| T1624 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/27.xbar_smoke_large_delays.1168903568 |
|
|
Aug 29 01:57:08 PM UTC 24 |
Aug 29 01:59:04 PM UTC 24 |
7359865975 ps |
| T1625 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/27.xbar_unmapped_addr.2684893104 |
|
|
Aug 29 01:57:59 PM UTC 24 |
Aug 29 01:59:04 PM UTC 24 |
1019075137 ps |
| T1626 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/27.xbar_access_same_device.4163960432 |
|
|
Aug 29 01:57:36 PM UTC 24 |
Aug 29 01:59:06 PM UTC 24 |
2020126088 ps |
| T443 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/19.chip_csr_mem_rw_with_rand_reset.4006570030 |
|
|
Aug 29 01:43:45 PM UTC 24 |
Aug 29 01:59:07 PM UTC 24 |
8681493704 ps |
| T1627 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/27.xbar_stress_all_with_reset_error.3301898246 |
|
|
Aug 29 01:58:21 PM UTC 24 |
Aug 29 01:59:09 PM UTC 24 |
102581706 ps |
| T1628 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/25.xbar_stress_all_with_rand_reset.3702898900 |
|
|
Aug 29 01:53:49 PM UTC 24 |
Aug 29 01:59:12 PM UTC 24 |
778483921 ps |
| T1629 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/28.xbar_random.1166531783 |
|
|
Aug 29 01:58:43 PM UTC 24 |
Aug 29 01:59:15 PM UTC 24 |
611813335 ps |
| T1630 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/28.xbar_random_zero_delays.928799800 |
|
|
Aug 29 01:58:52 PM UTC 24 |
Aug 29 01:59:17 PM UTC 24 |
178795614 ps |
| T1631 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/27.xbar_smoke_slow_rsp.1757161053 |
|
|
Aug 29 01:57:09 PM UTC 24 |
Aug 29 01:59:38 PM UTC 24 |
6474774796 ps |
| T1632 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/25.xbar_random_slow_rsp.3919691708 |
|
|
Aug 29 01:52:58 PM UTC 24 |
Aug 29 01:59:39 PM UTC 24 |
24516823470 ps |
| T1633 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/28.xbar_error_and_unmapped_addr.2231249765 |
|
|
Aug 29 01:59:26 PM UTC 24 |
Aug 29 01:59:39 PM UTC 24 |
88362662 ps |
| T1634 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/29.xbar_smoke_zero_delays.1896965008 |
|
|
Aug 29 02:00:00 PM UTC 24 |
Aug 29 02:00:11 PM UTC 24 |
57839317 ps |
| T1635 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/28.xbar_smoke_slow_rsp.457893482 |
|
|
Aug 29 01:58:39 PM UTC 24 |
Aug 29 02:00:13 PM UTC 24 |
5349135980 ps |
| T1636 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/29.xbar_smoke.2030110470 |
|
|
Aug 29 01:59:58 PM UTC 24 |
Aug 29 02:00:13 PM UTC 24 |
229105575 ps |
| T403 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/4.chip_same_csr_outstanding.3844337864 |
|
|
Aug 29 01:05:15 PM UTC 24 |
Aug 29 02:00:16 PM UTC 24 |
27313445945 ps |
| T1637 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/28.xbar_unmapped_addr.1584607465 |
|
|
Aug 29 01:59:25 PM UTC 24 |
Aug 29 02:00:21 PM UTC 24 |
958737131 ps |
| T1638 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/28.xbar_stress_all_with_reset_error.1191550920 |
|
|
Aug 29 01:59:35 PM UTC 24 |
Aug 29 02:00:22 PM UTC 24 |
165894331 ps |
| T535 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/23.xbar_stress_all_with_rand_reset.3502091156 |
|
|
Aug 29 01:50:09 PM UTC 24 |
Aug 29 02:00:23 PM UTC 24 |
10358883241 ps |
| T879 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/25.xbar_stress_all_with_reset_error.1914033087 |
|
|
Aug 29 01:54:04 PM UTC 24 |
Aug 29 02:00:26 PM UTC 24 |
7245210256 ps |
| T1639 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/27.xbar_stress_all_with_rand_reset.3416962895 |
|
|
Aug 29 01:58:04 PM UTC 24 |
Aug 29 02:00:26 PM UTC 24 |
341814172 ps |
| T1640 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/28.xbar_same_source.2798006976 |
|
|
Aug 29 01:59:21 PM UTC 24 |
Aug 29 02:00:27 PM UTC 24 |
1547993730 ps |
| T1641 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/28.xbar_error_random.712974704 |
|
|
Aug 29 01:59:24 PM UTC 24 |
Aug 29 02:00:30 PM UTC 24 |
1799615956 ps |
| T875 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/26.xbar_stress_all_with_reset_error.166624613 |
|
|
Aug 29 01:56:50 PM UTC 24 |
Aug 29 02:00:31 PM UTC 24 |
630625974 ps |
| T1642 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/28.xbar_smoke_large_delays.1814289205 |
|
|
Aug 29 01:58:40 PM UTC 24 |
Aug 29 02:00:39 PM UTC 24 |
9324715026 ps |
| T1643 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/26.xbar_stress_all_with_rand_reset.252469414 |
|
|
Aug 29 01:56:22 PM UTC 24 |
Aug 29 02:00:45 PM UTC 24 |
349977919 ps |
| T802 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/28.xbar_access_same_device.1268366255 |
|
|
Aug 29 01:59:08 PM UTC 24 |
Aug 29 02:00:50 PM UTC 24 |
2013692318 ps |
| T1644 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/29.xbar_random.1082420302 |
|
|
Aug 29 02:00:34 PM UTC 24 |
Aug 29 02:00:50 PM UTC 24 |
220826691 ps |
| T1645 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/27.xbar_random_large_delays.2533501362 |
|
|
Aug 29 01:57:32 PM UTC 24 |
Aug 29 02:00:59 PM UTC 24 |
19278179251 ps |
| T1646 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/29.xbar_stress_all.1037651522 |
|
|
Aug 29 02:00:50 PM UTC 24 |
Aug 29 02:01:00 PM UTC 24 |
50784762 ps |
| T1647 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/29.xbar_random_zero_delays.3059037778 |
|
|
Aug 29 02:00:33 PM UTC 24 |
Aug 29 02:01:09 PM UTC 24 |
365949045 ps |
| T1648 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/29.xbar_error_and_unmapped_addr.1120964007 |
|
|
Aug 29 02:00:50 PM UTC 24 |
Aug 29 02:01:09 PM UTC 24 |
87228262 ps |
| T1649 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/29.xbar_access_same_device.3061715262 |
|
|
Aug 29 02:00:43 PM UTC 24 |
Aug 29 02:01:09 PM UTC 24 |
341894339 ps |
| T519 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/25.xbar_stress_all.971492638 |
|
|
Aug 29 01:53:40 PM UTC 24 |
Aug 29 02:01:16 PM UTC 24 |
11365833281 ps |
| T1650 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/30.xbar_smoke.558337066 |
|
|
Aug 29 02:01:11 PM UTC 24 |
Aug 29 02:01:23 PM UTC 24 |
165785451 ps |
| T1651 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/16.chip_same_csr_outstanding.1034939851 |
|
|
Aug 29 01:33:23 PM UTC 24 |
Aug 29 02:01:26 PM UTC 24 |
15963519272 ps |
| T1652 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/30.xbar_smoke_zero_delays.2176302042 |
|
|
Aug 29 02:01:19 PM UTC 24 |
Aug 29 02:01:29 PM UTC 24 |
43192939 ps |
| T1653 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/29.xbar_smoke_large_delays.479215330 |
|
|
Aug 29 01:59:59 PM UTC 24 |
Aug 29 02:01:32 PM UTC 24 |
7762218983 ps |
| T1654 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/29.xbar_unmapped_addr.4006721491 |
|
|
Aug 29 02:00:46 PM UTC 24 |
Aug 29 02:01:33 PM UTC 24 |
992224084 ps |
| T1655 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/29.xbar_same_source.2672190759 |
|
|
Aug 29 02:00:46 PM UTC 24 |
Aug 29 02:01:33 PM UTC 24 |
429071385 ps |
| T1656 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/23.xbar_random_slow_rsp.1242331295 |
|
|
Aug 29 01:49:36 PM UTC 24 |
Aug 29 02:01:39 PM UTC 24 |
42489418749 ps |
| T1657 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/30.xbar_random_zero_delays.2714759752 |
|
|
Aug 29 02:01:27 PM UTC 24 |
Aug 29 02:01:39 PM UTC 24 |
62687734 ps |
| T1658 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/29.xbar_error_random.63782224 |
|
|
Aug 29 02:00:46 PM UTC 24 |
Aug 29 02:01:48 PM UTC 24 |
1210827236 ps |
| T838 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/26.xbar_stress_all_with_error.2535690291 |
|
|
Aug 29 01:56:41 PM UTC 24 |
Aug 29 02:01:56 PM UTC 24 |
8546517908 ps |
| T1659 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/28.chip_tl_errors.4045830732 |
|
|
Aug 29 01:58:21 PM UTC 24 |
Aug 29 02:02:03 PM UTC 24 |
3337852371 ps |
| T1660 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/19.xbar_random_large_delays.2544794229 |
|
|
Aug 29 01:41:49 PM UTC 24 |
Aug 29 02:02:06 PM UTC 24 |
97773064584 ps |
| T1661 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/30.xbar_access_same_device.2775488158 |
|
|
Aug 29 02:01:45 PM UTC 24 |
Aug 29 02:02:12 PM UTC 24 |
154679075 ps |
| T1662 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/29.xbar_smoke_slow_rsp.596085986 |
|
|
Aug 29 02:00:31 PM UTC 24 |
Aug 29 02:02:14 PM UTC 24 |
5302109411 ps |
| T850 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/18.xbar_access_same_device_slow_rsp.618777105 |
|
|
Aug 29 01:39:43 PM UTC 24 |
Aug 29 02:02:15 PM UTC 24 |
77301405730 ps |
| T1663 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/27.chip_tl_errors.3432114635 |
|
|
Aug 29 01:56:54 PM UTC 24 |
Aug 29 02:02:16 PM UTC 24 |
3316963448 ps |
| T1664 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/29.xbar_stress_all_with_error.1221543821 |
|
|
Aug 29 02:01:05 PM UTC 24 |
Aug 29 02:02:16 PM UTC 24 |
856685628 ps |
| T1665 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/30.xbar_smoke_slow_rsp.3779503384 |
|
|
Aug 29 02:01:29 PM UTC 24 |
Aug 29 02:02:18 PM UTC 24 |
3212473368 ps |
| T538 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/30.xbar_same_source.387021305 |
|
|
Aug 29 02:01:51 PM UTC 24 |
Aug 29 02:02:25 PM UTC 24 |
900460794 ps |
| T474 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/20.xbar_stress_all.3737864431 |
|
|
Aug 29 01:45:37 PM UTC 24 |
Aug 29 02:02:26 PM UTC 24 |
23960528848 ps |
| T1666 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/23.xbar_random_large_delays.974149759 |
|
|
Aug 29 01:49:35 PM UTC 24 |
Aug 29 02:02:27 PM UTC 24 |
58670110031 ps |
| T1667 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/30.xbar_unmapped_addr.2816018936 |
|
|
Aug 29 02:01:54 PM UTC 24 |
Aug 29 02:02:33 PM UTC 24 |
236449969 ps |
| T1668 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/31.xbar_smoke.2501890779 |
|
|
Aug 29 02:02:27 PM UTC 24 |
Aug 29 02:02:34 PM UTC 24 |
44049200 ps |
| T1669 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/31.xbar_smoke_zero_delays.1592976409 |
|
|
Aug 29 02:02:29 PM UTC 24 |
Aug 29 02:02:38 PM UTC 24 |
47393640 ps |
| T1670 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/31.xbar_random.2781736366 |
|
|
Aug 29 02:02:34 PM UTC 24 |
Aug 29 02:02:44 PM UTC 24 |
30283539 ps |
| T1671 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/30.xbar_smoke_large_delays.2359994565 |
|
|
Aug 29 02:01:20 PM UTC 24 |
Aug 29 02:02:50 PM UTC 24 |
8218093528 ps |
| T1672 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/30.xbar_error_and_unmapped_addr.1307570405 |
|
|
Aug 29 02:01:57 PM UTC 24 |
Aug 29 02:02:51 PM UTC 24 |
1089885419 ps |
| T1673 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/30.xbar_error_random.2353042674 |
|
|
Aug 29 02:01:51 PM UTC 24 |
Aug 29 02:03:02 PM UTC 24 |
1638152073 ps |
| T1674 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/31.xbar_random_zero_delays.4186582314 |
|
|
Aug 29 02:02:33 PM UTC 24 |
Aug 29 02:03:04 PM UTC 24 |
222813210 ps |
| T1675 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/36.xbar_random_slow_rsp.1321838491 |
|
|
Aug 29 02:10:02 PM UTC 24 |
Aug 29 02:11:39 PM UTC 24 |
3771476773 ps |
| T1676 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/31.xbar_same_source.3356782556 |
|
|
Aug 29 02:02:52 PM UTC 24 |
Aug 29 02:03:15 PM UTC 24 |
398977680 ps |
| T475 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/28.xbar_stress_all.612579357 |
|
|
Aug 29 01:59:28 PM UTC 24 |
Aug 29 02:03:17 PM UTC 24 |
5087037663 ps |
| T517 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/30.xbar_random.4015238610 |
|
|
Aug 29 02:01:29 PM UTC 24 |
Aug 29 02:03:27 PM UTC 24 |
2461753300 ps |
| T1677 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/31.xbar_error_random.1023462406 |
|
|
Aug 29 02:02:54 PM UTC 24 |
Aug 29 02:03:38 PM UTC 24 |
407320455 ps |
| T1678 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/31.xbar_error_and_unmapped_addr.1330760152 |
|
|
Aug 29 02:03:02 PM UTC 24 |
Aug 29 02:03:42 PM UTC 24 |
332952593 ps |
| T1679 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/31.xbar_unmapped_addr.4256623420 |
|
|
Aug 29 02:02:58 PM UTC 24 |
Aug 29 02:03:45 PM UTC 24 |
754773499 ps |
| T1680 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/30.xbar_stress_all_with_rand_reset.697724728 |
|
|
Aug 29 02:02:09 PM UTC 24 |
Aug 29 02:03:45 PM UTC 24 |
2255371362 ps |
| T1681 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/32.xbar_smoke_zero_delays.3474938881 |
|
|
Aug 29 02:03:37 PM UTC 24 |
Aug 29 02:03:47 PM UTC 24 |
52003577 ps |
| T1682 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/32.xbar_smoke.1560884666 |
|
|
Aug 29 02:03:34 PM UTC 24 |
Aug 29 02:03:49 PM UTC 24 |
229999550 ps |
| T1683 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/31.xbar_smoke_slow_rsp.2597802411 |
|
|
Aug 29 02:02:34 PM UTC 24 |
Aug 29 02:04:00 PM UTC 24 |
6535408235 ps |
| T1684 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/31.xbar_access_same_device.1763544867 |
|
|
Aug 29 02:02:45 PM UTC 24 |
Aug 29 02:04:01 PM UTC 24 |
1640143427 ps |
| T1685 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/2.chip_same_csr_outstanding.3266814879 |
|
|
Aug 29 01:01:30 PM UTC 24 |
Aug 29 02:04:10 PM UTC 24 |
30189549497 ps |
| T1686 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/32.xbar_random_zero_delays.2794645809 |
|
|
Aug 29 02:04:05 PM UTC 24 |
Aug 29 02:04:15 PM UTC 24 |
32216772 ps |
| T1687 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/4.chip_csr_bit_bash.3992135542 |
|
|
Aug 29 01:05:00 PM UTC 24 |
Aug 29 02:04:25 PM UTC 24 |
30735575366 ps |
| T1688 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/32.xbar_same_source.2364955141 |
|
|
Aug 29 02:04:21 PM UTC 24 |
Aug 29 02:04:31 PM UTC 24 |
154344654 ps |
| T1689 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/31.xbar_access_same_device_slow_rsp.2090859168 |
|
|
Aug 29 02:02:45 PM UTC 24 |
Aug 29 02:04:40 PM UTC 24 |
4998581908 ps |
| T1690 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/31.xbar_stress_all_with_rand_reset.2160715765 |
|
|
Aug 29 02:03:11 PM UTC 24 |
Aug 29 02:04:43 PM UTC 24 |
100793962 ps |
| T489 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/27.xbar_stress_all.1273827279 |
|
|
Aug 29 01:58:01 PM UTC 24 |
Aug 29 02:04:49 PM UTC 24 |
9325419460 ps |
| T1691 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/28.xbar_stress_all_with_error.1005536687 |
|
|
Aug 29 01:59:33 PM UTC 24 |
Aug 29 02:05:06 PM UTC 24 |
6652682975 ps |
| T1692 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/31.xbar_smoke_large_delays.214893461 |
|
|
Aug 29 02:02:34 PM UTC 24 |
Aug 29 02:05:07 PM UTC 24 |
9658590809 ps |
| T1693 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/31.xbar_stress_all.3787834363 |
|
|
Aug 29 02:03:10 PM UTC 24 |
Aug 29 02:05:08 PM UTC 24 |
3394816574 ps |
| T1694 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/32.xbar_smoke_slow_rsp.1166304527 |
|
|
Aug 29 02:03:59 PM UTC 24 |
Aug 29 02:05:09 PM UTC 24 |
4712681602 ps |
| T1695 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/32.xbar_smoke_large_delays.3900749832 |
|
|
Aug 29 02:03:46 PM UTC 24 |
Aug 29 02:05:09 PM UTC 24 |
6208828931 ps |
| T1696 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/32.xbar_access_same_device.2030310958 |
|
|
Aug 29 02:04:08 PM UTC 24 |
Aug 29 02:05:10 PM UTC 24 |
595701617 ps |
| T1697 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/32.xbar_random.1320208826 |
|
|
Aug 29 02:04:02 PM UTC 24 |
Aug 29 02:05:12 PM UTC 24 |
1819093685 ps |
| T1698 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/27.xbar_stress_all_with_error.1404381718 |
|
|
Aug 29 01:58:20 PM UTC 24 |
Aug 29 02:05:13 PM UTC 24 |
12101712686 ps |
| T1699 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/26.xbar_random_large_delays.2527313635 |
|
|
Aug 29 01:54:55 PM UTC 24 |
Aug 29 02:05:14 PM UTC 24 |
42764905475 ps |
| T1700 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/32.xbar_unmapped_addr.2357626837 |
|
|
Aug 29 02:04:35 PM UTC 24 |
Aug 29 02:05:27 PM UTC 24 |
1043299713 ps |
| T1701 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/32.xbar_error_and_unmapped_addr.1945958652 |
|
|
Aug 29 02:04:44 PM UTC 24 |
Aug 29 02:05:37 PM UTC 24 |
1079089047 ps |
| T1702 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/33.xbar_smoke_zero_delays.1397391003 |
|
|
Aug 29 02:05:26 PM UTC 24 |
Aug 29 02:05:37 PM UTC 24 |
56235139 ps |
| T1703 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/33.xbar_smoke.3785354302 |
|
|
Aug 29 02:05:25 PM UTC 24 |
Aug 29 02:05:38 PM UTC 24 |
198452672 ps |
| T656 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/29.chip_tl_errors.4165220775 |
|
|
Aug 29 01:59:37 PM UTC 24 |
Aug 29 02:05:38 PM UTC 24 |
4024206616 ps |
| T835 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/13.xbar_access_same_device_slow_rsp.581301842 |
|
|
Aug 29 01:26:48 PM UTC 24 |
Aug 29 02:05:49 PM UTC 24 |
124344277316 ps |
| T529 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/33.xbar_random_zero_delays.205499056 |
|
|
Aug 29 02:05:26 PM UTC 24 |
Aug 29 02:05:59 PM UTC 24 |
416474159 ps |
| T1704 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/32.xbar_error_random.3914309260 |
|
|
Aug 29 02:04:30 PM UTC 24 |
Aug 29 02:06:01 PM UTC 24 |
2025876570 ps |
| T1705 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/33.xbar_unmapped_addr.2454037615 |
|
|
Aug 29 02:05:59 PM UTC 24 |
Aug 29 02:06:08 PM UTC 24 |
22825907 ps |
| T507 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/30.xbar_stress_all.2651729242 |
|
|
Aug 29 02:02:00 PM UTC 24 |
Aug 29 02:06:11 PM UTC 24 |
6325343377 ps |
| T1706 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/33.xbar_same_source.934796604 |
|
|
Aug 29 02:05:58 PM UTC 24 |
Aug 29 02:06:14 PM UTC 24 |
120375270 ps |
| T1707 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/31.xbar_stress_all_with_reset_error.1162081518 |
|
|
Aug 29 02:03:23 PM UTC 24 |
Aug 29 02:06:23 PM UTC 24 |
607400335 ps |
| T1708 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/29.xbar_random_large_delays.3282592395 |
|
|
Aug 29 02:00:35 PM UTC 24 |
Aug 29 02:06:24 PM UTC 24 |
22959958518 ps |
| T1709 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/30.xbar_stress_all_with_error.1547012226 |
|
|
Aug 29 02:02:16 PM UTC 24 |
Aug 29 02:06:32 PM UTC 24 |
2993476742 ps |
| T1710 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/33.xbar_access_same_device.3614817128 |
|
|
Aug 29 02:05:34 PM UTC 24 |
Aug 29 02:06:42 PM UTC 24 |
1683323009 ps |
| T1711 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/34.xbar_smoke_zero_delays.2178984733 |
|
|
Aug 29 02:06:34 PM UTC 24 |
Aug 29 02:06:45 PM UTC 24 |
42657994 ps |
| T1712 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/34.xbar_smoke.4055908453 |
|
|
Aug 29 02:06:31 PM UTC 24 |
Aug 29 02:06:46 PM UTC 24 |
241949084 ps |
| T1713 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/33.xbar_error_and_unmapped_addr.2955436837 |
|
|
Aug 29 02:05:59 PM UTC 24 |
Aug 29 02:06:52 PM UTC 24 |
1253344389 ps |
| T1714 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/33.xbar_error_random.4292654642 |
|
|
Aug 29 02:05:57 PM UTC 24 |
Aug 29 02:06:56 PM UTC 24 |
1259508782 ps |
| T1715 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/33.xbar_stress_all_with_rand_reset.2027581905 |
|
|
Aug 29 02:06:19 PM UTC 24 |
Aug 29 02:06:58 PM UTC 24 |
49998177 ps |
| T1716 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/33.xbar_smoke_large_delays.1021737049 |
|
|
Aug 29 02:05:27 PM UTC 24 |
Aug 29 02:06:58 PM UTC 24 |
8874511911 ps |
| T1717 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/33.xbar_smoke_slow_rsp.2591991990 |
|
|
Aug 29 02:05:26 PM UTC 24 |
Aug 29 02:07:06 PM UTC 24 |
6594290968 ps |
| T1718 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/31.xbar_random_large_delays.1852916608 |
|
|
Aug 29 02:02:37 PM UTC 24 |
Aug 29 02:07:06 PM UTC 24 |
25697661230 ps |
| T1719 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/30.xbar_stress_all_with_reset_error.137760183 |
|
|
Aug 29 02:02:24 PM UTC 24 |
Aug 29 02:07:08 PM UTC 24 |
4626445556 ps |
| T1720 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/33.xbar_random.3029909262 |
|
|
Aug 29 02:05:30 PM UTC 24 |
Aug 29 02:07:20 PM UTC 24 |
2281867705 ps |
| T1721 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/34.xbar_random_zero_delays.3680944811 |
|
|
Aug 29 02:07:03 PM UTC 24 |
Aug 29 02:07:31 PM UTC 24 |
190098191 ps |
| T1722 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/34.xbar_same_source.1935800427 |
|
|
Aug 29 02:07:17 PM UTC 24 |
Aug 29 02:07:34 PM UTC 24 |
554370208 ps |
| T1723 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/32.xbar_stress_all_with_rand_reset.2513514122 |
|
|
Aug 29 02:05:02 PM UTC 24 |
Aug 29 02:07:41 PM UTC 24 |
316339295 ps |
| T1724 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/22.xbar_random_large_delays.2257317770 |
|
|
Aug 29 01:48:09 PM UTC 24 |
Aug 29 02:07:46 PM UTC 24 |
95597310378 ps |
| T1725 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/28.xbar_random_slow_rsp.1234949477 |
|
|
Aug 29 01:59:06 PM UTC 24 |
Aug 29 02:07:51 PM UTC 24 |
33138484648 ps |
| T1726 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/34.xbar_unmapped_addr.2820725389 |
|
|
Aug 29 02:07:26 PM UTC 24 |
Aug 29 02:07:53 PM UTC 24 |
408107091 ps |
| T1727 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/34.xbar_random.2212882280 |
|
|
Aug 29 02:06:51 PM UTC 24 |
Aug 29 02:07:57 PM UTC 24 |
1939466926 ps |
| T1728 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/34.xbar_access_same_device.2315643316 |
|
|
Aug 29 02:07:10 PM UTC 24 |
Aug 29 02:08:00 PM UTC 24 |
628220799 ps |
| T1729 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/34.xbar_smoke_slow_rsp.3481633525 |
|
|
Aug 29 02:06:45 PM UTC 24 |
Aug 29 02:08:10 PM UTC 24 |
4374167865 ps |
| T1730 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/34.xbar_random_slow_rsp.1150516199 |
|
|
Aug 29 02:07:06 PM UTC 24 |
Aug 29 02:08:11 PM UTC 24 |
3061513358 ps |
| T1731 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/35.xbar_smoke.442949570 |
|
|
Aug 29 02:08:02 PM UTC 24 |
Aug 29 02:08:15 PM UTC 24 |
194057804 ps |
| T1732 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/35.xbar_smoke_zero_delays.4030572309 |
|
|
Aug 29 02:08:07 PM UTC 24 |
Aug 29 02:08:16 PM UTC 24 |
40924949 ps |
| T1733 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/34.xbar_error_and_unmapped_addr.3085169073 |
|
|
Aug 29 02:07:26 PM UTC 24 |
Aug 29 02:08:29 PM UTC 24 |
1219202966 ps |
| T866 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/32.xbar_stress_all_with_reset_error.2267736511 |
|
|
Aug 29 02:05:10 PM UTC 24 |
Aug 29 02:08:42 PM UTC 24 |
474393970 ps |
| T1734 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/33.xbar_stress_all_with_error.755807327 |
|
|
Aug 29 02:06:16 PM UTC 24 |
Aug 29 02:08:44 PM UTC 24 |
3970211203 ps |
| T1735 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/33.xbar_stress_all_with_reset_error.2810333484 |
|
|
Aug 29 02:06:29 PM UTC 24 |
Aug 29 02:09:00 PM UTC 24 |
1049776980 ps |
| T1736 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/35.xbar_access_same_device.1874137493 |
|
|
Aug 29 02:08:35 PM UTC 24 |
Aug 29 02:09:04 PM UTC 24 |
537333931 ps |
| T1737 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/35.xbar_random.1467600283 |
|
|
Aug 29 02:08:16 PM UTC 24 |
Aug 29 02:09:04 PM UTC 24 |
924262695 ps |
| T1738 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/35.xbar_random_zero_delays.3756777370 |
|
|
Aug 29 02:08:21 PM UTC 24 |
Aug 29 02:09:05 PM UTC 24 |
346283413 ps |
| T841 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/32.xbar_stress_all.2736895680 |
|
|
Aug 29 02:04:51 PM UTC 24 |
Aug 29 02:09:07 PM UTC 24 |
4943484226 ps |
| T1739 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/34.xbar_smoke_large_delays.2465605331 |
|
|
Aug 29 02:06:43 PM UTC 24 |
Aug 29 02:09:09 PM UTC 24 |
9390618631 ps |
| T1740 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/29.xbar_stress_all_with_reset_error.2992246475 |
|
|
Aug 29 02:01:10 PM UTC 24 |
Aug 29 02:09:10 PM UTC 24 |
7965303444 ps |
| T1741 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/34.xbar_error_random.4263820192 |
|
|
Aug 29 02:07:16 PM UTC 24 |
Aug 29 02:09:10 PM UTC 24 |
2525404804 ps |
| T1742 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/35.xbar_smoke_large_delays.78146463 |
|
|
Aug 29 02:08:12 PM UTC 24 |
Aug 29 02:09:22 PM UTC 24 |
6635884615 ps |
| T1743 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/30.xbar_random_slow_rsp.3997228539 |
|
|
Aug 29 02:01:42 PM UTC 24 |
Aug 29 02:09:27 PM UTC 24 |
23109388313 ps |
| T1744 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/35.xbar_same_source.2101111604 |
|
|
Aug 29 02:08:50 PM UTC 24 |
Aug 29 02:09:31 PM UTC 24 |
383128276 ps |
| T1745 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/36.xbar_smoke.3629699807 |
|
|
Aug 29 02:09:30 PM UTC 24 |
Aug 29 02:09:40 PM UTC 24 |
44220868 ps |
| T1746 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/36.xbar_smoke_zero_delays.124011557 |
|
|
Aug 29 02:09:31 PM UTC 24 |
Aug 29 02:09:41 PM UTC 24 |
39091769 ps |
| T1747 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/35.xbar_error_and_unmapped_addr.4080667192 |
|
|
Aug 29 02:09:21 PM UTC 24 |
Aug 29 02:09:44 PM UTC 24 |
338022802 ps |
| T1748 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/35.xbar_unmapped_addr.2023172297 |
|
|
Aug 29 02:09:05 PM UTC 24 |
Aug 29 02:09:48 PM UTC 24 |
714813483 ps |
| T1749 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/34.xbar_stress_all.1793960859 |
|
|
Aug 29 02:07:29 PM UTC 24 |
Aug 29 02:09:51 PM UTC 24 |
1462094630 ps |
| T1750 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/35.xbar_random_large_delays.617799892 |
|
|
Aug 29 02:08:30 PM UTC 24 |
Aug 29 02:09:55 PM UTC 24 |
6555908163 ps |
| T1751 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/35.xbar_smoke_slow_rsp.4267176310 |
|
|
Aug 29 02:08:14 PM UTC 24 |
Aug 29 02:09:55 PM UTC 24 |
5490656952 ps |
| T1752 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/36.xbar_random.1917378202 |
|
|
Aug 29 02:09:47 PM UTC 24 |
Aug 29 02:10:07 PM UTC 24 |
109071836 ps |
| T534 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/36.xbar_random_zero_delays.4030770137 |
|
|
Aug 29 02:09:51 PM UTC 24 |
Aug 29 02:10:13 PM UTC 24 |
155510978 ps |
| T1753 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/36.xbar_unmapped_addr.2165209228 |
|
|
Aug 29 02:10:16 PM UTC 24 |
Aug 29 02:10:37 PM UTC 24 |
251788689 ps |
| T1754 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/36.xbar_smoke_slow_rsp.3037030471 |
|
|
Aug 29 02:09:42 PM UTC 24 |
Aug 29 02:10:41 PM UTC 24 |
3640070223 ps |
| T1755 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/36.xbar_error_and_unmapped_addr.439648796 |
|
|
Aug 29 02:10:26 PM UTC 24 |
Aug 29 02:10:42 PM UTC 24 |
84324285 ps |
| T1756 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/35.xbar_error_random.3959371891 |
|
|
Aug 29 02:09:03 PM UTC 24 |
Aug 29 02:10:46 PM UTC 24 |
2242937387 ps |
| T1757 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/36.xbar_same_source.2726048366 |
|
|
Aug 29 02:10:11 PM UTC 24 |
Aug 29 02:11:07 PM UTC 24 |
1216059490 ps |
| T1758 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/37.xbar_smoke.2928453500 |
|
|
Aug 29 02:11:05 PM UTC 24 |
Aug 29 02:11:19 PM UTC 24 |
201855489 ps |
| T1759 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/36.xbar_smoke_large_delays.1374279345 |
|
|
Aug 29 02:09:31 PM UTC 24 |
Aug 29 02:11:24 PM UTC 24 |
8790732148 ps |
| T1760 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/36.xbar_error_random.2047257880 |
|
|
Aug 29 02:10:16 PM UTC 24 |
Aug 29 02:11:32 PM UTC 24 |
1759131056 ps |
| T486 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/29.xbar_stress_all_with_rand_reset.1431761197 |
|
|
Aug 29 02:00:58 PM UTC 24 |
Aug 29 02:11:37 PM UTC 24 |
4640287730 ps |
| T1761 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/35.xbar_stress_all_with_rand_reset.1572628324 |
|
|
Aug 29 02:09:24 PM UTC 24 |
Aug 29 02:11:37 PM UTC 24 |
291388327 ps |
| T1762 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/37.xbar_smoke_zero_delays.2082128784 |
|
|
Aug 29 02:11:28 PM UTC 24 |
Aug 29 02:11:38 PM UTC 24 |
40429956 ps |
| T1763 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/36.xbar_access_same_device.2096701266 |
|
|
Aug 29 02:10:05 PM UTC 24 |
Aug 29 02:11:38 PM UTC 24 |
1747516912 ps |
| T1764 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/34.xbar_stress_all_with_error.2991365068 |
|
|
Aug 29 02:07:51 PM UTC 24 |
Aug 29 02:11:39 PM UTC 24 |
6672772871 ps |
| T1765 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/34.xbar_random_large_delays.246428683 |
|
|
Aug 29 02:07:05 PM UTC 24 |
Aug 29 02:11:43 PM UTC 24 |
25311030093 ps |
| T1766 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/26.xbar_random_slow_rsp.3078602499 |
|
|
Aug 29 01:55:00 PM UTC 24 |
Aug 29 02:11:43 PM UTC 24 |
50839309243 ps |
| T1767 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/30.xbar_random_large_delays.2067351099 |
|
|
Aug 29 02:01:35 PM UTC 24 |
Aug 29 02:12:04 PM UTC 24 |
44839507861 ps |
| T1768 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/0.chip_csr_bit_bash.3613660696 |
|
|
Aug 29 01:00:24 PM UTC 24 |
Aug 29 02:12:06 PM UTC 24 |
38218792750 ps |
| T1769 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/6.chip_same_csr_outstanding.1665882954 |
|
|
Aug 29 01:10:29 PM UTC 24 |
Aug 29 02:12:18 PM UTC 24 |
26590505096 ps |
| T1770 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/37.xbar_unmapped_addr.164528599 |
|
|
Aug 29 02:12:04 PM UTC 24 |
Aug 29 02:12:18 PM UTC 24 |
57802286 ps |
| T1771 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/37.xbar_random_zero_delays.3988208516 |
|
|
Aug 29 02:11:57 PM UTC 24 |
Aug 29 02:12:24 PM UTC 24 |
220866881 ps |
| T1772 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/37.xbar_error_random.3001321430 |
|
|
Aug 29 02:12:01 PM UTC 24 |
Aug 29 02:12:28 PM UTC 24 |
559186537 ps |
| T1773 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/37.xbar_access_same_device.4031542583 |
|
|
Aug 29 02:11:57 PM UTC 24 |
Aug 29 02:12:31 PM UTC 24 |
346095909 ps |
| T1774 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/37.xbar_random.2899582190 |
|
|
Aug 29 02:11:52 PM UTC 24 |
Aug 29 02:12:34 PM UTC 24 |
370386988 ps |
| T536 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/33.xbar_stress_all.2628369906 |
|
|
Aug 29 02:06:10 PM UTC 24 |
Aug 29 02:12:38 PM UTC 24 |
10989996425 ps |
| T1775 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/32.xbar_random_slow_rsp.3967938994 |
|
|
Aug 29 02:04:07 PM UTC 24 |
Aug 29 02:12:55 PM UTC 24 |
32014018660 ps |
| T1776 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/38.xbar_smoke.238544438 |
|
|
Aug 29 02:12:49 PM UTC 24 |
Aug 29 02:12:58 PM UTC 24 |
34757616 ps |
| T1777 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/37.xbar_same_source.4246254421 |
|
|
Aug 29 02:12:00 PM UTC 24 |
Aug 29 02:12:59 PM UTC 24 |
2199291142 ps |
| T1778 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/35.xbar_stress_all_with_reset_error.2671461488 |
|
|
Aug 29 02:09:28 PM UTC 24 |
Aug 29 02:13:00 PM UTC 24 |
4712337461 ps |
| T1779 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/38.xbar_smoke_zero_delays.765041996 |
|
|
Aug 29 02:12:52 PM UTC 24 |
Aug 29 02:13:02 PM UTC 24 |
43401686 ps |
| T530 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/35.xbar_stress_all.2100234456 |
|
|
Aug 29 02:09:24 PM UTC 24 |
Aug 29 02:13:04 PM UTC 24 |
2127444025 ps |
| T1780 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/37.xbar_error_and_unmapped_addr.1989919161 |
|
|
Aug 29 02:12:24 PM UTC 24 |
Aug 29 02:13:26 PM UTC 24 |
1136758396 ps |
| T1781 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/38.xbar_random.3780631491 |
|
|
Aug 29 02:13:15 PM UTC 24 |
Aug 29 02:13:31 PM UTC 24 |
233252216 ps |
| T1782 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/37.xbar_smoke_large_delays.936725974 |
|
|
Aug 29 02:11:40 PM UTC 24 |
Aug 29 02:13:33 PM UTC 24 |
9920439673 ps |
| T1783 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/1.chip_same_csr_outstanding.2402573661 |
|
|
Aug 29 01:00:30 PM UTC 24 |
Aug 29 02:13:40 PM UTC 24 |
29429892172 ps |
| T1784 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/38.xbar_random_zero_delays.3380298076 |
|
|
Aug 29 02:13:20 PM UTC 24 |
Aug 29 02:13:40 PM UTC 24 |
115686276 ps |
| T1785 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/37.xbar_smoke_slow_rsp.1764371448 |
|
|
Aug 29 02:11:45 PM UTC 24 |
Aug 29 02:13:42 PM UTC 24 |
5189567979 ps |
| T512 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/28.xbar_stress_all_with_rand_reset.4119085416 |
|
|
Aug 29 01:59:29 PM UTC 24 |
Aug 29 02:13:48 PM UTC 24 |
7696601775 ps |