| T803 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/19.xbar_access_same_device_slow_rsp.1858163073 |
|
|
Aug 29 01:42:37 PM UTC 24 |
Aug 29 02:13:54 PM UTC 24 |
105174631070 ps |
| T1786 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/36.xbar_stress_all_with_rand_reset.571004098 |
|
|
Aug 29 02:10:57 PM UTC 24 |
Aug 29 02:14:18 PM UTC 24 |
385991403 ps |
| T1787 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/38.xbar_error_and_unmapped_addr.1718371297 |
|
|
Aug 29 02:13:58 PM UTC 24 |
Aug 29 02:14:18 PM UTC 24 |
293744939 ps |
| T1788 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/19.chip_same_csr_outstanding.1649462795 |
|
|
Aug 29 01:41:07 PM UTC 24 |
Aug 29 02:14:21 PM UTC 24 |
15752841037 ps |
| T1789 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/38.xbar_same_source.1570879928 |
|
|
Aug 29 02:13:45 PM UTC 24 |
Aug 29 02:14:22 PM UTC 24 |
333847342 ps |
| T1790 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/38.xbar_stress_all_with_rand_reset.1166907457 |
|
|
Aug 29 02:14:02 PM UTC 24 |
Aug 29 02:14:22 PM UTC 24 |
7680692 ps |
| T1791 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/38.xbar_error_random.1708451772 |
|
|
Aug 29 02:13:49 PM UTC 24 |
Aug 29 02:14:24 PM UTC 24 |
340013325 ps |
| T1792 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/38.xbar_smoke_large_delays.2974613799 |
|
|
Aug 29 02:12:54 PM UTC 24 |
Aug 29 02:14:44 PM UTC 24 |
9019626099 ps |
| T1793 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/39.xbar_smoke_zero_delays.3207853391 |
|
|
Aug 29 02:14:39 PM UTC 24 |
Aug 29 02:14:48 PM UTC 24 |
43340380 ps |
| T1794 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/39.xbar_smoke.1851048560 |
|
|
Aug 29 02:14:39 PM UTC 24 |
Aug 29 02:14:52 PM UTC 24 |
199850753 ps |
| T1795 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/37.xbar_stress_all_with_error.3052364295 |
|
|
Aug 29 02:12:39 PM UTC 24 |
Aug 29 02:14:52 PM UTC 24 |
1642682019 ps |
| T1796 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/29.xbar_random_slow_rsp.1493629900 |
|
|
Aug 29 02:00:40 PM UTC 24 |
Aug 29 02:14:56 PM UTC 24 |
52694020754 ps |
| T1797 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/38.xbar_access_same_device.4016748380 |
|
|
Aug 29 02:13:23 PM UTC 24 |
Aug 29 02:15:01 PM UTC 24 |
1691620432 ps |
| T1798 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/38.xbar_unmapped_addr.60795079 |
|
|
Aug 29 02:13:52 PM UTC 24 |
Aug 29 02:15:03 PM UTC 24 |
1242401551 ps |
| T1799 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/36.xbar_access_same_device_slow_rsp.1077877254 |
|
|
Aug 29 02:10:08 PM UTC 24 |
Aug 29 02:15:05 PM UTC 24 |
12795499724 ps |
| T1800 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/38.xbar_smoke_slow_rsp.1993318208 |
|
|
Aug 29 02:12:58 PM UTC 24 |
Aug 29 02:15:08 PM UTC 24 |
5543913406 ps |
| T1801 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/39.xbar_error_and_unmapped_addr.3699726668 |
|
|
Aug 29 02:15:26 PM UTC 24 |
Aug 29 02:15:37 PM UTC 24 |
188231005 ps |
| T1802 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/39.xbar_random_zero_delays.1385670385 |
|
|
Aug 29 02:14:45 PM UTC 24 |
Aug 29 02:15:37 PM UTC 24 |
420654566 ps |
| T1803 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/17.xbar_access_same_device_slow_rsp.311346084 |
|
|
Aug 29 01:38:05 PM UTC 24 |
Aug 29 02:15:38 PM UTC 24 |
125857814646 ps |
| T1804 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/39.xbar_same_source.4221284753 |
|
|
Aug 29 02:15:14 PM UTC 24 |
Aug 29 02:15:50 PM UTC 24 |
707857312 ps |
| T1805 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/27.xbar_random_slow_rsp.3315168308 |
|
|
Aug 29 01:57:33 PM UTC 24 |
Aug 29 02:15:52 PM UTC 24 |
58824725849 ps |
| T1806 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/39.xbar_random.3080053605 |
|
|
Aug 29 02:14:43 PM UTC 24 |
Aug 29 02:16:01 PM UTC 24 |
2336225391 ps |
| T1807 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/32.xbar_stress_all_with_error.2160485377 |
|
|
Aug 29 02:05:04 PM UTC 24 |
Aug 29 02:16:04 PM UTC 24 |
15903901694 ps |
| T1808 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/39.xbar_smoke_slow_rsp.1917938799 |
|
|
Aug 29 02:14:42 PM UTC 24 |
Aug 29 02:16:20 PM UTC 24 |
5814639756 ps |
| T1809 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/31.xbar_stress_all_with_error.2701343697 |
|
|
Aug 29 02:03:20 PM UTC 24 |
Aug 29 02:16:21 PM UTC 24 |
19020509084 ps |
| T1810 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/39.xbar_unmapped_addr.318280101 |
|
|
Aug 29 02:15:24 PM UTC 24 |
Aug 29 02:16:21 PM UTC 24 |
1095160615 ps |
| T1811 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/40.xbar_smoke_zero_delays.2503901733 |
|
|
Aug 29 02:16:12 PM UTC 24 |
Aug 29 02:16:23 PM UTC 24 |
48719902 ps |
| T1812 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/40.xbar_smoke.3055038833 |
|
|
Aug 29 02:16:10 PM UTC 24 |
Aug 29 02:16:25 PM UTC 24 |
217350725 ps |
| T1813 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/39.xbar_error_random.3459174443 |
|
|
Aug 29 02:15:21 PM UTC 24 |
Aug 29 02:16:44 PM UTC 24 |
2318000520 ps |
| T498 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/36.xbar_stress_all.3266121495 |
|
|
Aug 29 02:10:34 PM UTC 24 |
Aug 29 02:16:53 PM UTC 24 |
3597105553 ps |
| T1814 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/39.xbar_smoke_large_delays.15821741 |
|
|
Aug 29 02:14:41 PM UTC 24 |
Aug 29 02:16:53 PM UTC 24 |
7993151760 ps |
| T1815 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/28.xbar_random_large_delays.3918738396 |
|
|
Aug 29 01:59:02 PM UTC 24 |
Aug 29 02:17:01 PM UTC 24 |
88308831125 ps |
| T1816 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/40.xbar_access_same_device.3985312372 |
|
|
Aug 29 02:16:46 PM UTC 24 |
Aug 29 02:17:18 PM UTC 24 |
243333580 ps |
| T1817 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/40.xbar_smoke_large_delays.509502919 |
|
|
Aug 29 02:16:22 PM UTC 24 |
Aug 29 02:17:31 PM UTC 24 |
6524502122 ps |
| T1818 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/35.xbar_stress_all_with_error.235526374 |
|
|
Aug 29 02:09:26 PM UTC 24 |
Aug 29 02:17:32 PM UTC 24 |
13185942590 ps |
| T1819 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/40.xbar_random_zero_delays.440489126 |
|
|
Aug 29 02:16:41 PM UTC 24 |
Aug 29 02:17:34 PM UTC 24 |
409474487 ps |
| T1820 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/40.xbar_unmapped_addr.3669920621 |
|
|
Aug 29 02:17:21 PM UTC 24 |
Aug 29 02:17:50 PM UTC 24 |
160114940 ps |
| T1821 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/40.xbar_error_random.2279265991 |
|
|
Aug 29 02:17:15 PM UTC 24 |
Aug 29 02:17:58 PM UTC 24 |
551289807 ps |
| T1822 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/22.xbar_access_same_device_slow_rsp.3938672552 |
|
|
Aug 29 01:48:25 PM UTC 24 |
Aug 29 02:18:01 PM UTC 24 |
115400922489 ps |
| T1823 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/40.xbar_error_and_unmapped_addr.3648709089 |
|
|
Aug 29 02:17:38 PM UTC 24 |
Aug 29 02:18:06 PM UTC 24 |
170058465 ps |
| T1824 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/40.xbar_random.2330129271 |
|
|
Aug 29 02:16:40 PM UTC 24 |
Aug 29 02:18:10 PM UTC 24 |
1732459306 ps |
| T1825 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/40.xbar_smoke_slow_rsp.1267233533 |
|
|
Aug 29 02:16:23 PM UTC 24 |
Aug 29 02:18:14 PM UTC 24 |
4681908772 ps |
| T1826 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/39.xbar_access_same_device.4045513264 |
|
|
Aug 29 02:15:12 PM UTC 24 |
Aug 29 02:18:15 PM UTC 24 |
4026703264 ps |
| T1827 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/41.xbar_smoke.4100199826 |
|
|
Aug 29 02:18:16 PM UTC 24 |
Aug 29 02:18:26 PM UTC 24 |
45277282 ps |
| T1828 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/3.chip_same_csr_outstanding.3936376566 |
|
|
Aug 29 01:02:53 PM UTC 24 |
Aug 29 02:18:27 PM UTC 24 |
27989415233 ps |
| T1829 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/41.xbar_smoke_zero_delays.618737972 |
|
|
Aug 29 02:18:20 PM UTC 24 |
Aug 29 02:18:30 PM UTC 24 |
46594786 ps |
| T1830 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/31.xbar_random_slow_rsp.2007030176 |
|
|
Aug 29 02:02:42 PM UTC 24 |
Aug 29 02:18:33 PM UTC 24 |
57895884741 ps |
| T1831 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/40.xbar_same_source.2464308552 |
|
|
Aug 29 02:17:13 PM UTC 24 |
Aug 29 02:18:42 PM UTC 24 |
2416168790 ps |
| T1832 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/7.chip_same_csr_outstanding.1136763266 |
|
|
Aug 29 01:12:47 PM UTC 24 |
Aug 29 02:18:49 PM UTC 24 |
31380318320 ps |
| T1833 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/41.xbar_same_source.1618728704 |
|
|
Aug 29 02:19:03 PM UTC 24 |
Aug 29 02:19:13 PM UTC 24 |
40467190 ps |
| T1834 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/41.xbar_random_zero_delays.1877720112 |
|
|
Aug 29 02:18:36 PM UTC 24 |
Aug 29 02:19:18 PM UTC 24 |
430854322 ps |
| T848 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/36.xbar_stress_all_with_error.2504092067 |
|
|
Aug 29 02:11:03 PM UTC 24 |
Aug 29 02:19:25 PM UTC 24 |
13432136989 ps |
| T1835 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/38.xbar_random_large_delays.1244541719 |
|
|
Aug 29 02:13:19 PM UTC 24 |
Aug 29 02:19:26 PM UTC 24 |
28727795650 ps |
| T1836 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/41.xbar_random.283990194 |
|
|
Aug 29 02:18:35 PM UTC 24 |
Aug 29 02:19:38 PM UTC 24 |
1253725078 ps |
| T1837 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/41.xbar_error_random.861240685 |
|
|
Aug 29 02:19:10 PM UTC 24 |
Aug 29 02:19:38 PM UTC 24 |
552523391 ps |
| T861 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/36.xbar_stress_all_with_reset_error.1674530478 |
|
|
Aug 29 02:11:02 PM UTC 24 |
Aug 29 02:19:41 PM UTC 24 |
5341919240 ps |
| T1838 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/40.xbar_stress_all_with_error.3328754506 |
|
|
Aug 29 02:17:55 PM UTC 24 |
Aug 29 02:19:46 PM UTC 24 |
2199005955 ps |
| T1839 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/41.xbar_error_and_unmapped_addr.470079662 |
|
|
Aug 29 02:19:39 PM UTC 24 |
Aug 29 02:19:53 PM UTC 24 |
163274636 ps |
| T1840 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/39.xbar_random_slow_rsp.4078238575 |
|
|
Aug 29 02:15:07 PM UTC 24 |
Aug 29 02:19:53 PM UTC 24 |
15916061137 ps |
| T1841 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/41.xbar_smoke_slow_rsp.3796543038 |
|
|
Aug 29 02:18:31 PM UTC 24 |
Aug 29 02:19:55 PM UTC 24 |
6169641088 ps |
| T513 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/34.xbar_stress_all_with_rand_reset.194935728 |
|
|
Aug 29 02:07:41 PM UTC 24 |
Aug 29 02:19:58 PM UTC 24 |
4699281295 ps |
| T612 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/34.xbar_stress_all_with_reset_error.2613399083 |
|
|
Aug 29 02:07:54 PM UTC 24 |
Aug 29 02:20:00 PM UTC 24 |
6232562502 ps |
| T1842 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/41.xbar_smoke_large_delays.101351725 |
|
|
Aug 29 02:18:28 PM UTC 24 |
Aug 29 02:20:08 PM UTC 24 |
9157259750 ps |
| T1843 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/32.xbar_random_large_delays.2072283493 |
|
|
Aug 29 02:04:06 PM UTC 24 |
Aug 29 02:20:10 PM UTC 24 |
72435780409 ps |
| T1844 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/42.xbar_smoke.1115895476 |
|
|
Aug 29 02:20:03 PM UTC 24 |
Aug 29 02:20:17 PM UTC 24 |
213321242 ps |
| T1845 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/42.xbar_smoke_zero_delays.3968366329 |
|
|
Aug 29 02:20:07 PM UTC 24 |
Aug 29 02:20:17 PM UTC 24 |
39463996 ps |
| T1846 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/42.xbar_random.3161587117 |
|
|
Aug 29 02:20:17 PM UTC 24 |
Aug 29 02:20:28 PM UTC 24 |
122738227 ps |
| T1847 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/35.xbar_random_slow_rsp.212611967 |
|
|
Aug 29 02:08:31 PM UTC 24 |
Aug 29 02:20:34 PM UTC 24 |
46242299151 ps |
| T1848 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/41.xbar_unmapped_addr.2749454912 |
|
|
Aug 29 02:19:34 PM UTC 24 |
Aug 29 02:20:34 PM UTC 24 |
1027002231 ps |
| T1849 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/37.xbar_access_same_device_slow_rsp.1892098335 |
|
|
Aug 29 02:12:00 PM UTC 24 |
Aug 29 02:20:38 PM UTC 24 |
29464007099 ps |
| T526 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/38.xbar_stress_all.1510230674 |
|
|
Aug 29 02:14:00 PM UTC 24 |
Aug 29 02:20:38 PM UTC 24 |
4321139151 ps |
| T1850 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/42.xbar_random_zero_delays.3291171093 |
|
|
Aug 29 02:20:18 PM UTC 24 |
Aug 29 02:20:40 PM UTC 24 |
151414207 ps |
| T1851 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/42.xbar_access_same_device.3655519066 |
|
|
Aug 29 02:20:31 PM UTC 24 |
Aug 29 02:20:41 PM UTC 24 |
14564992 ps |
| T1852 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/33.xbar_random_slow_rsp.3070151925 |
|
|
Aug 29 02:05:33 PM UTC 24 |
Aug 29 02:20:53 PM UTC 24 |
59719783366 ps |
| T1853 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/41.xbar_access_same_device.987707755 |
|
|
Aug 29 02:18:49 PM UTC 24 |
Aug 29 02:21:00 PM UTC 24 |
1299215195 ps |
| T1854 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/42.xbar_same_source.3003989520 |
|
|
Aug 29 02:20:37 PM UTC 24 |
Aug 29 02:21:15 PM UTC 24 |
484056472 ps |
| T1855 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/42.xbar_error_random.3738674893 |
|
|
Aug 29 02:20:49 PM UTC 24 |
Aug 29 02:21:16 PM UTC 24 |
484333707 ps |
| T1856 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/42.xbar_unmapped_addr.3833593813 |
|
|
Aug 29 02:20:53 PM UTC 24 |
Aug 29 02:21:16 PM UTC 24 |
329856639 ps |
| T1857 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/40.xbar_stress_all.3131171028 |
|
|
Aug 29 02:17:51 PM UTC 24 |
Aug 29 02:21:18 PM UTC 24 |
2070030525 ps |
| T1858 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/36.xbar_random_large_delays.3849442005 |
|
|
Aug 29 02:10:00 PM UTC 24 |
Aug 29 02:21:19 PM UTC 24 |
63355807098 ps |
| T1859 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/43.xbar_smoke.3541614538 |
|
|
Aug 29 02:21:12 PM UTC 24 |
Aug 29 02:21:25 PM UTC 24 |
189548722 ps |
| T1860 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/42.xbar_smoke_large_delays.226703702 |
|
|
Aug 29 02:20:14 PM UTC 24 |
Aug 29 02:21:27 PM UTC 24 |
6796473174 ps |
| T1861 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/43.xbar_smoke_zero_delays.2704574020 |
|
|
Aug 29 02:21:20 PM UTC 24 |
Aug 29 02:21:30 PM UTC 24 |
45963872 ps |
| T795 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/38.xbar_access_same_device_slow_rsp.567182475 |
|
|
Aug 29 02:13:25 PM UTC 24 |
Aug 29 02:21:43 PM UTC 24 |
23616057547 ps |
| T1862 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/43.xbar_random.4257923151 |
|
|
Aug 29 02:21:36 PM UTC 24 |
Aug 29 02:21:52 PM UTC 24 |
173534540 ps |
| T1863 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/41.xbar_stress_all.1203866186 |
|
|
Aug 29 02:19:46 PM UTC 24 |
Aug 29 02:21:52 PM UTC 24 |
3020935685 ps |
| T1864 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/42.xbar_smoke_slow_rsp.1599784045 |
|
|
Aug 29 02:20:13 PM UTC 24 |
Aug 29 02:21:54 PM UTC 24 |
4679600045 ps |
| T1865 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/42.xbar_error_and_unmapped_addr.3177446302 |
|
|
Aug 29 02:20:55 PM UTC 24 |
Aug 29 02:21:55 PM UTC 24 |
1460413085 ps |
| T1866 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/42.xbar_random_slow_rsp.2909950219 |
|
|
Aug 29 02:20:29 PM UTC 24 |
Aug 29 02:21:59 PM UTC 24 |
3950130665 ps |
| T1867 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/38.xbar_stress_all_with_reset_error.2344419874 |
|
|
Aug 29 02:14:15 PM UTC 24 |
Aug 29 02:22:10 PM UTC 24 |
3890811516 ps |
| T1868 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/37.xbar_random_slow_rsp.3236742089 |
|
|
Aug 29 02:11:59 PM UTC 24 |
Aug 29 02:22:17 PM UTC 24 |
40374062210 ps |
| T1869 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/43.xbar_access_same_device.1437218845 |
|
|
Aug 29 02:21:48 PM UTC 24 |
Aug 29 02:22:23 PM UTC 24 |
277188914 ps |
| T1870 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/40.xbar_random_slow_rsp.39400152 |
|
|
Aug 29 02:16:44 PM UTC 24 |
Aug 29 02:22:24 PM UTC 24 |
16371177575 ps |
| T1871 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/40.xbar_stress_all_with_reset_error.1634083004 |
|
|
Aug 29 02:18:08 PM UTC 24 |
Aug 29 02:22:32 PM UTC 24 |
4007934688 ps |
| T1872 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/43.xbar_random_zero_delays.844283689 |
|
|
Aug 29 02:21:40 PM UTC 24 |
Aug 29 02:22:41 PM UTC 24 |
500266329 ps |
| T1873 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/43.xbar_smoke_slow_rsp.387076241 |
|
|
Aug 29 02:21:33 PM UTC 24 |
Aug 29 02:22:50 PM UTC 24 |
5435777957 ps |
| T1874 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/44.xbar_smoke_zero_delays.1210751329 |
|
|
Aug 29 02:22:45 PM UTC 24 |
Aug 29 02:22:55 PM UTC 24 |
51231484 ps |
| T1875 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/44.xbar_smoke.443061119 |
|
|
Aug 29 02:22:43 PM UTC 24 |
Aug 29 02:22:57 PM UTC 24 |
206777447 ps |
| T809 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/24.xbar_access_same_device_slow_rsp.1737727024 |
|
|
Aug 29 01:51:24 PM UTC 24 |
Aug 29 02:23:01 PM UTC 24 |
110891216873 ps |
| T1876 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/43.xbar_unmapped_addr.2811112206 |
|
|
Aug 29 02:22:11 PM UTC 24 |
Aug 29 02:23:05 PM UTC 24 |
314379629 ps |
| T1877 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/40.xbar_random_large_delays.1575901050 |
|
|
Aug 29 02:16:42 PM UTC 24 |
Aug 29 02:23:10 PM UTC 24 |
34005072185 ps |
| T1878 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/43.xbar_error_and_unmapped_addr.300765525 |
|
|
Aug 29 02:22:14 PM UTC 24 |
Aug 29 02:23:10 PM UTC 24 |
1135254667 ps |
| T1879 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/43.xbar_error_random.2966533784 |
|
|
Aug 29 02:22:12 PM UTC 24 |
Aug 29 02:23:14 PM UTC 24 |
1507887407 ps |
| T1880 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/39.xbar_stress_all_with_reset_error.2214671846 |
|
|
Aug 29 02:15:58 PM UTC 24 |
Aug 29 02:23:28 PM UTC 24 |
6278364865 ps |
| T618 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/39.xbar_stress_all_with_error.2964888125 |
|
|
Aug 29 02:15:58 PM UTC 24 |
Aug 29 02:23:35 PM UTC 24 |
12823693653 ps |
| T1881 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/44.xbar_random_zero_delays.857855769 |
|
|
Aug 29 02:23:16 PM UTC 24 |
Aug 29 02:23:39 PM UTC 24 |
159286231 ps |
| T1882 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/37.xbar_stress_all_with_reset_error.1611565942 |
|
|
Aug 29 02:12:45 PM UTC 24 |
Aug 29 02:23:41 PM UTC 24 |
7057449696 ps |
| T1883 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/41.xbar_stress_all_with_reset_error.1453274101 |
|
|
Aug 29 02:19:59 PM UTC 24 |
Aug 29 02:23:42 PM UTC 24 |
4097891713 ps |
| T1884 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/43.xbar_same_source.2564706461 |
|
|
Aug 29 02:22:04 PM UTC 24 |
Aug 29 02:23:52 PM UTC 24 |
2664709054 ps |
| T1885 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/43.xbar_smoke_large_delays.3636880659 |
|
|
Aug 29 02:21:36 PM UTC 24 |
Aug 29 02:24:01 PM UTC 24 |
9900006758 ps |
| T1886 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/39.xbar_stress_all.3979653623 |
|
|
Aug 29 02:15:28 PM UTC 24 |
Aug 29 02:24:04 PM UTC 24 |
15379962326 ps |
| T1887 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/44.xbar_unmapped_addr.4103226042 |
|
|
Aug 29 02:23:48 PM UTC 24 |
Aug 29 02:24:05 PM UTC 24 |
82254569 ps |
| T1888 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/44.xbar_same_source.90616227 |
|
|
Aug 29 02:23:31 PM UTC 24 |
Aug 29 02:24:08 PM UTC 24 |
353253994 ps |
| T1889 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/40.xbar_access_same_device_slow_rsp.439152625 |
|
|
Aug 29 02:17:04 PM UTC 24 |
Aug 29 02:24:16 PM UTC 24 |
27952919441 ps |
| T1890 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/44.xbar_access_same_device.788341648 |
|
|
Aug 29 02:23:26 PM UTC 24 |
Aug 29 02:24:18 PM UTC 24 |
599236283 ps |
| T1891 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/44.xbar_error_and_unmapped_addr.3502010895 |
|
|
Aug 29 02:23:56 PM UTC 24 |
Aug 29 02:24:28 PM UTC 24 |
823025553 ps |
| T1892 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/44.xbar_stress_all.24362930 |
|
|
Aug 29 02:24:00 PM UTC 24 |
Aug 29 02:24:28 PM UTC 24 |
250418645 ps |
| T1893 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/45.xbar_smoke.1383137807 |
|
|
Aug 29 02:24:21 PM UTC 24 |
Aug 29 02:24:30 PM UTC 24 |
140926266 ps |
| T1894 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/44.xbar_smoke_slow_rsp.3131542271 |
|
|
Aug 29 02:23:02 PM UTC 24 |
Aug 29 02:24:32 PM UTC 24 |
5138492219 ps |
| T1895 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/45.xbar_smoke_zero_delays.751217917 |
|
|
Aug 29 02:24:24 PM UTC 24 |
Aug 29 02:24:34 PM UTC 24 |
42694659 ps |
| T1896 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/44.xbar_error_random.562938929 |
|
|
Aug 29 02:23:34 PM UTC 24 |
Aug 29 02:24:40 PM UTC 24 |
1827786847 ps |
| T1897 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/42.xbar_stress_all_with_reset_error.3279032963 |
|
|
Aug 29 02:21:02 PM UTC 24 |
Aug 29 02:24:43 PM UTC 24 |
686949140 ps |
| T810 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/37.xbar_stress_all.573024288 |
|
|
Aug 29 02:12:26 PM UTC 24 |
Aug 29 02:24:43 PM UTC 24 |
17466013334 ps |
| T1898 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/43.xbar_stress_all_with_error.71446973 |
|
|
Aug 29 02:22:29 PM UTC 24 |
Aug 29 02:24:45 PM UTC 24 |
3700048213 ps |
| T1899 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/44.xbar_random.463381351 |
|
|
Aug 29 02:23:11 PM UTC 24 |
Aug 29 02:24:46 PM UTC 24 |
2201137796 ps |
| T1900 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/39.xbar_stress_all_with_rand_reset.1820574116 |
|
|
Aug 29 02:15:57 PM UTC 24 |
Aug 29 02:24:53 PM UTC 24 |
2380298698 ps |
| T1901 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/44.xbar_smoke_large_delays.3604046970 |
|
|
Aug 29 02:22:52 PM UTC 24 |
Aug 29 02:25:01 PM UTC 24 |
7117142422 ps |
| T1902 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/45.xbar_random.235865711 |
|
|
Aug 29 02:24:36 PM UTC 24 |
Aug 29 02:25:02 PM UTC 24 |
546131545 ps |
| T1903 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/38.xbar_stress_all_with_error.2432016788 |
|
|
Aug 29 02:14:09 PM UTC 24 |
Aug 29 02:25:03 PM UTC 24 |
18971113971 ps |
| T1904 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/38.xbar_random_slow_rsp.3156462142 |
|
|
Aug 29 02:13:21 PM UTC 24 |
Aug 29 02:25:11 PM UTC 24 |
40841817232 ps |
| T1905 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/42.xbar_stress_all.1814844500 |
|
|
Aug 29 02:20:57 PM UTC 24 |
Aug 29 02:25:13 PM UTC 24 |
3223060597 ps |
| T1906 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/45.xbar_random_zero_delays.1674159101 |
|
|
Aug 29 02:24:39 PM UTC 24 |
Aug 29 02:25:19 PM UTC 24 |
407662006 ps |
| T1907 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/45.xbar_unmapped_addr.3111653101 |
|
|
Aug 29 02:25:04 PM UTC 24 |
Aug 29 02:25:33 PM UTC 24 |
464533659 ps |
| T1908 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/45.xbar_error_and_unmapped_addr.4051380162 |
|
|
Aug 29 02:25:04 PM UTC 24 |
Aug 29 02:25:34 PM UTC 24 |
223191760 ps |
| T1909 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/46.xbar_smoke_zero_delays.4276740660 |
|
|
Aug 29 02:25:24 PM UTC 24 |
Aug 29 02:25:34 PM UTC 24 |
48564484 ps |
| T1910 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/46.xbar_smoke.2941869346 |
|
|
Aug 29 02:25:23 PM UTC 24 |
Aug 29 02:25:34 PM UTC 24 |
127270387 ps |
| T1911 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/41.xbar_stress_all_with_error.2267054316 |
|
|
Aug 29 02:19:58 PM UTC 24 |
Aug 29 02:25:41 PM UTC 24 |
7338801187 ps |
| T1912 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/45.xbar_error_random.11142965 |
|
|
Aug 29 02:25:00 PM UTC 24 |
Aug 29 02:25:43 PM UTC 24 |
606089295 ps |
| T1913 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/45.xbar_smoke_slow_rsp.4115586466 |
|
|
Aug 29 02:24:29 PM UTC 24 |
Aug 29 02:25:47 PM UTC 24 |
4991267687 ps |
| T1914 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/37.xbar_stress_all_with_rand_reset.773965045 |
|
|
Aug 29 02:12:36 PM UTC 24 |
Aug 29 02:25:53 PM UTC 24 |
5238416918 ps |
| T1915 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/45.xbar_same_source.2243278537 |
|
|
Aug 29 02:24:53 PM UTC 24 |
Aug 29 02:26:09 PM UTC 24 |
1658585429 ps |
| T1916 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/45.xbar_smoke_large_delays.2853630215 |
|
|
Aug 29 02:24:25 PM UTC 24 |
Aug 29 02:26:13 PM UTC 24 |
6669651142 ps |
| T1917 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/44.xbar_stress_all_with_reset_error.1476777917 |
|
|
Aug 29 02:24:12 PM UTC 24 |
Aug 29 02:26:14 PM UTC 24 |
460048412 ps |
| T1918 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/46.xbar_random_zero_delays.4111108639 |
|
|
Aug 29 02:25:53 PM UTC 24 |
Aug 29 02:26:17 PM UTC 24 |
177299985 ps |
| T1919 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/43.xbar_stress_all_with_rand_reset.403714332 |
|
|
Aug 29 02:22:20 PM UTC 24 |
Aug 29 02:26:26 PM UTC 24 |
640195632 ps |
| T1920 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/46.xbar_same_source.3840801344 |
|
|
Aug 29 02:26:04 PM UTC 24 |
Aug 29 02:26:29 PM UTC 24 |
580300120 ps |
| T1921 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/41.xbar_stress_all_with_rand_reset.2156306880 |
|
|
Aug 29 02:19:47 PM UTC 24 |
Aug 29 02:26:33 PM UTC 24 |
5544234731 ps |
| T1922 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/46.xbar_access_same_device.113666919 |
|
|
Aug 29 02:25:53 PM UTC 24 |
Aug 29 02:26:42 PM UTC 24 |
737980512 ps |
| T1923 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/29.xbar_access_same_device_slow_rsp.1051140794 |
|
|
Aug 29 02:00:43 PM UTC 24 |
Aug 29 02:26:44 PM UTC 24 |
77967908353 ps |
| T1924 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/33.xbar_random_large_delays.2965233830 |
|
|
Aug 29 02:05:33 PM UTC 24 |
Aug 29 02:26:45 PM UTC 24 |
102513348867 ps |
| T1925 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/46.xbar_error_random.2397007526 |
|
|
Aug 29 02:26:08 PM UTC 24 |
Aug 29 02:26:49 PM UTC 24 |
871568385 ps |
| T1926 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/46.xbar_error_and_unmapped_addr.476967281 |
|
|
Aug 29 02:26:29 PM UTC 24 |
Aug 29 02:26:51 PM UTC 24 |
128699638 ps |
| T1927 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/40.xbar_stress_all_with_rand_reset.3615684059 |
|
|
Aug 29 02:17:51 PM UTC 24 |
Aug 29 02:26:56 PM UTC 24 |
3335728630 ps |
| T1928 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/46.xbar_stress_all_with_reset_error.3772244170 |
|
|
Aug 29 02:26:45 PM UTC 24 |
Aug 29 02:27:00 PM UTC 24 |
102697083 ps |
| T1929 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/47.xbar_smoke.457462568 |
|
|
Aug 29 02:26:50 PM UTC 24 |
Aug 29 02:27:03 PM UTC 24 |
172906554 ps |
| T1930 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/44.xbar_stress_all_with_error.553638979 |
|
|
Aug 29 02:24:03 PM UTC 24 |
Aug 29 02:27:04 PM UTC 24 |
4442178670 ps |
| T1931 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/47.xbar_smoke_zero_delays.453065312 |
|
|
Aug 29 02:26:54 PM UTC 24 |
Aug 29 02:27:05 PM UTC 24 |
58383136 ps |
| T1932 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/9.chip_same_csr_outstanding.921017588 |
|
|
Aug 29 01:16:32 PM UTC 24 |
Aug 29 02:27:09 PM UTC 24 |
28192214072 ps |
| T1933 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/46.xbar_random.705803277 |
|
|
Aug 29 02:25:39 PM UTC 24 |
Aug 29 02:27:09 PM UTC 24 |
1791903018 ps |
| T1934 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/46.xbar_smoke_large_delays.1940794505 |
|
|
Aug 29 02:25:31 PM UTC 24 |
Aug 29 02:27:10 PM UTC 24 |
8273655861 ps |
| T1935 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/46.xbar_unmapped_addr.697644081 |
|
|
Aug 29 02:26:13 PM UTC 24 |
Aug 29 02:27:12 PM UTC 24 |
972517391 ps |
| T1936 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/47.xbar_random.3814431113 |
|
|
Aug 29 02:27:06 PM UTC 24 |
Aug 29 02:27:22 PM UTC 24 |
92295981 ps |
| T1937 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/47.xbar_same_source.3402771268 |
|
|
Aug 29 02:27:20 PM UTC 24 |
Aug 29 02:27:29 PM UTC 24 |
31536816 ps |
| T1938 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/46.xbar_smoke_slow_rsp.1347007956 |
|
|
Aug 29 02:25:32 PM UTC 24 |
Aug 29 02:27:35 PM UTC 24 |
5541331796 ps |
| T1939 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/45.xbar_access_same_device.1815394292 |
|
|
Aug 29 02:24:51 PM UTC 24 |
Aug 29 02:27:39 PM UTC 24 |
3532605718 ps |
| T1940 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/47.xbar_random_zero_delays.1081941932 |
|
|
Aug 29 02:27:09 PM UTC 24 |
Aug 29 02:27:42 PM UTC 24 |
237100106 ps |
| T1941 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/42.xbar_stress_all_with_rand_reset.303114319 |
|
|
Aug 29 02:20:59 PM UTC 24 |
Aug 29 02:27:43 PM UTC 24 |
2466123526 ps |
| T1942 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/47.xbar_error_and_unmapped_addr.125945119 |
|
|
Aug 29 02:27:29 PM UTC 24 |
Aug 29 02:27:48 PM UTC 24 |
113274133 ps |
| T1943 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/43.xbar_random_large_delays.1382844170 |
|
|
Aug 29 02:21:39 PM UTC 24 |
Aug 29 02:28:00 PM UTC 24 |
32295351640 ps |
| T1944 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/47.xbar_access_same_device.1751749436 |
|
|
Aug 29 02:27:20 PM UTC 24 |
Aug 29 02:28:05 PM UTC 24 |
398248536 ps |
| T1945 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/48.xbar_smoke.2090637014 |
|
|
Aug 29 02:27:55 PM UTC 24 |
Aug 29 02:28:06 PM UTC 24 |
192815724 ps |
| T1946 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/47.xbar_unmapped_addr.3496564588 |
|
|
Aug 29 02:27:27 PM UTC 24 |
Aug 29 02:28:08 PM UTC 24 |
272059804 ps |
| T1947 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/48.xbar_smoke_zero_delays.2996803583 |
|
|
Aug 29 02:27:59 PM UTC 24 |
Aug 29 02:28:09 PM UTC 24 |
40950525 ps |
| T1948 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/47.xbar_stress_all_with_rand_reset.2917106701 |
|
|
Aug 29 02:27:32 PM UTC 24 |
Aug 29 02:28:22 PM UTC 24 |
65110078 ps |
| T1949 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/45.xbar_stress_all_with_error.1734717734 |
|
|
Aug 29 02:25:12 PM UTC 24 |
Aug 29 02:28:24 PM UTC 24 |
5950482250 ps |
| T1950 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/48.xbar_random_zero_delays.1757917610 |
|
|
Aug 29 02:28:21 PM UTC 24 |
Aug 29 02:28:31 PM UTC 24 |
35655212 ps |
| T1951 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/48.xbar_random.3817617392 |
|
|
Aug 29 02:28:08 PM UTC 24 |
Aug 29 02:28:38 PM UTC 24 |
553332208 ps |
| T1952 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/47.xbar_error_random.4109895217 |
|
|
Aug 29 02:27:25 PM UTC 24 |
Aug 29 02:28:50 PM UTC 24 |
1910964373 ps |
| T1953 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/47.xbar_smoke_large_delays.2922036049 |
|
|
Aug 29 02:27:03 PM UTC 24 |
Aug 29 02:29:06 PM UTC 24 |
8317123343 ps |
| T1954 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/47.xbar_stress_all_with_reset_error.2639653692 |
|
|
Aug 29 02:27:46 PM UTC 24 |
Aug 29 02:29:06 PM UTC 24 |
185186933 ps |
| T1955 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/47.xbar_smoke_slow_rsp.1600875034 |
|
|
Aug 29 02:27:05 PM UTC 24 |
Aug 29 02:29:10 PM UTC 24 |
5424336570 ps |
| T1956 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/48.xbar_smoke_slow_rsp.3978648950 |
|
|
Aug 29 02:28:04 PM UTC 24 |
Aug 29 02:29:17 PM UTC 24 |
3070057150 ps |
| T1957 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/48.xbar_error_random.374662632 |
|
|
Aug 29 02:28:44 PM UTC 24 |
Aug 29 02:29:21 PM UTC 24 |
392277507 ps |
| T1958 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/48.xbar_stress_all.2843008398 |
|
|
Aug 29 02:29:11 PM UTC 24 |
Aug 29 02:29:21 PM UTC 24 |
51574977 ps |
| T811 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/23.xbar_access_same_device_slow_rsp.2860624614 |
|
|
Aug 29 01:49:38 PM UTC 24 |
Aug 29 02:29:26 PM UTC 24 |
139089900546 ps |
| T1959 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/48.xbar_unmapped_addr.2458742182 |
|
|
Aug 29 02:28:51 PM UTC 24 |
Aug 29 02:29:38 PM UTC 24 |
1032860183 ps |
| T1960 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/42.xbar_stress_all_with_error.129538558 |
|
|
Aug 29 02:21:00 PM UTC 24 |
Aug 29 02:29:40 PM UTC 24 |
12972106480 ps |
| T1961 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/45.xbar_stress_all.1681246703 |
|
|
Aug 29 02:25:04 PM UTC 24 |
Aug 29 02:29:45 PM UTC 24 |
6420863712 ps |
| T1962 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/46.xbar_stress_all_with_rand_reset.3227784540 |
|
|
Aug 29 02:26:35 PM UTC 24 |
Aug 29 02:29:45 PM UTC 24 |
624549029 ps |
| T1963 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/49.xbar_smoke.1428909202 |
|
|
Aug 29 02:29:38 PM UTC 24 |
Aug 29 02:29:46 PM UTC 24 |
39202168 ps |
| T1964 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/48.xbar_same_source.74855893 |
|
|
Aug 29 02:28:42 PM UTC 24 |
Aug 29 02:29:48 PM UTC 24 |
1801259061 ps |
| T1965 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/25.xbar_access_same_device_slow_rsp.3978286937 |
|
|
Aug 29 01:53:03 PM UTC 24 |
Aug 29 02:29:49 PM UTC 24 |
132201171197 ps |
| T1966 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/49.xbar_smoke_zero_delays.3686024833 |
|
|
Aug 29 02:29:40 PM UTC 24 |
Aug 29 02:29:49 PM UTC 24 |
51735543 ps |
| T1967 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/48.xbar_error_and_unmapped_addr.299322914 |
|
|
Aug 29 02:28:59 PM UTC 24 |
Aug 29 02:29:50 PM UTC 24 |
1012693289 ps |
| T1968 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/48.xbar_smoke_large_delays.1000623865 |
|
|
Aug 29 02:28:02 PM UTC 24 |
Aug 29 02:29:53 PM UTC 24 |
8090130246 ps |
| T871 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/44.xbar_stress_all_with_rand_reset.1874091976 |
|
|
Aug 29 02:24:02 PM UTC 24 |
Aug 29 02:30:17 PM UTC 24 |
4091232581 ps |
| T1969 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/49.xbar_random.2331816244 |
|
|
Aug 29 02:29:56 PM UTC 24 |
Aug 29 02:30:23 PM UTC 24 |
565541246 ps |
| T1970 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/46.xbar_stress_all.53590600 |
|
|
Aug 29 02:26:34 PM UTC 24 |
Aug 29 02:30:28 PM UTC 24 |
2331631361 ps |
| T1971 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/45.xbar_stress_all_with_reset_error.1499219954 |
|
|
Aug 29 02:25:22 PM UTC 24 |
Aug 29 02:30:31 PM UTC 24 |
1419766072 ps |
| T1972 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/49.xbar_same_source.819358938 |
|
|
Aug 29 02:30:06 PM UTC 24 |
Aug 29 02:30:46 PM UTC 24 |
817518047 ps |
| T1973 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/43.xbar_stress_all.22065289 |
|
|
Aug 29 02:22:15 PM UTC 24 |
Aug 29 02:30:47 PM UTC 24 |
14761910026 ps |
| T1974 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/49.xbar_error_and_unmapped_addr.725676619 |
|
|
Aug 29 02:30:12 PM UTC 24 |
Aug 29 02:30:57 PM UTC 24 |
1035044074 ps |
| T1975 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/49.xbar_random_zero_delays.2835388491 |
|
|
Aug 29 02:29:59 PM UTC 24 |
Aug 29 02:31:02 PM UTC 24 |
528042914 ps |
| T1976 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/49.xbar_error_random.3146198462 |
|
|
Aug 29 02:30:08 PM UTC 24 |
Aug 29 02:31:10 PM UTC 24 |
2008446830 ps |
| T1977 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/49.xbar_unmapped_addr.3798693670 |
|
|
Aug 29 02:30:08 PM UTC 24 |
Aug 29 02:31:11 PM UTC 24 |
1194616603 ps |
| T1978 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/48.xbar_access_same_device.3279768954 |
|
|
Aug 29 02:28:28 PM UTC 24 |
Aug 29 02:31:14 PM UTC 24 |
3359796600 ps |
| T1979 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/49.xbar_smoke_large_delays.2779691872 |
|
|
Aug 29 02:29:41 PM UTC 24 |
Aug 29 02:31:14 PM UTC 24 |
8775979638 ps |
| T1980 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/50.xbar_smoke_zero_delays.2773786402 |
|
|
Aug 29 02:31:08 PM UTC 24 |
Aug 29 02:31:17 PM UTC 24 |
43325316 ps |
| T1981 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/49.xbar_access_same_device.3171487932 |
|
|
Aug 29 02:30:03 PM UTC 24 |
Aug 29 02:31:20 PM UTC 24 |
1259247670 ps |
| T1982 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/50.xbar_smoke.1151822045 |
|
|
Aug 29 02:31:06 PM UTC 24 |
Aug 29 02:31:20 PM UTC 24 |
190814263 ps |
| T1983 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/48.xbar_stress_all_with_error.1798384938 |
|
|
Aug 29 02:29:27 PM UTC 24 |
Aug 29 02:31:38 PM UTC 24 |
1119823842 ps |
| T1984 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/50.xbar_random.4074686657 |
|
|
Aug 29 02:31:32 PM UTC 24 |
Aug 29 02:31:50 PM UTC 24 |
104078036 ps |
| T1985 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/46.xbar_stress_all_with_error.3706796143 |
|
|
Aug 29 02:26:38 PM UTC 24 |
Aug 29 02:31:56 PM UTC 24 |
8822018718 ps |
| T1986 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/50.xbar_same_source.1496580960 |
|
|
Aug 29 02:31:39 PM UTC 24 |
Aug 29 02:32:00 PM UTC 24 |
410275630 ps |
| T1987 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/49.xbar_smoke_slow_rsp.604863617 |
|
|
Aug 29 02:29:47 PM UTC 24 |
Aug 29 02:32:01 PM UTC 24 |
6512165758 ps |
| T1988 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/50.xbar_unmapped_addr.3930125988 |
|
|
Aug 29 02:32:11 PM UTC 24 |
Aug 29 02:32:21 PM UTC 24 |
78826966 ps |
| T1989 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/50.xbar_error_and_unmapped_addr.3091112729 |
|
|
Aug 29 02:32:16 PM UTC 24 |
Aug 29 02:32:31 PM UTC 24 |
67331661 ps |
| T1990 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/49.xbar_random_large_delays.3275665889 |
|
|
Aug 29 02:30:05 PM UTC 24 |
Aug 29 02:32:39 PM UTC 24 |
12163728846 ps |
| T1991 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/50.xbar_random_zero_delays.1163869678 |
|
|
Aug 29 02:31:30 PM UTC 24 |
Aug 29 02:32:39 PM UTC 24 |
525482096 ps |
| T1992 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/27.xbar_access_same_device_slow_rsp.480647347 |
|
|
Aug 29 01:57:41 PM UTC 24 |
Aug 29 02:32:51 PM UTC 24 |
129769570305 ps |
| T1993 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/50.xbar_smoke_slow_rsp.719008409 |
|
|
Aug 29 02:31:21 PM UTC 24 |
Aug 29 02:32:56 PM UTC 24 |
4172623911 ps |
| T1994 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/50.xbar_smoke_large_delays.1335900158 |
|
|
Aug 29 02:31:17 PM UTC 24 |
Aug 29 02:33:03 PM UTC 24 |
7354432009 ps |
| T1995 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/14.chip_same_csr_outstanding.3752631444 |
|
|
Aug 29 01:27:30 PM UTC 24 |
Aug 29 02:33:07 PM UTC 24 |
29096490747 ps |
| T1996 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/50.xbar_access_same_device.3654363612 |
|
|
Aug 29 02:31:37 PM UTC 24 |
Aug 29 02:33:08 PM UTC 24 |
1990279908 ps |
| T1997 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/51.xbar_smoke_zero_delays.2636938341 |
|
|
Aug 29 02:33:00 PM UTC 24 |
Aug 29 02:33:09 PM UTC 24 |
40644015 ps |
| T1998 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/51.xbar_smoke.2728035638 |
|
|
Aug 29 02:32:59 PM UTC 24 |
Aug 29 02:33:10 PM UTC 24 |
57492701 ps |
| T1999 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/48.xbar_stress_all_with_rand_reset.243871618 |
|
|
Aug 29 02:29:26 PM UTC 24 |
Aug 29 02:33:15 PM UTC 24 |
1290261690 ps |
| T2000 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/46.xbar_random_slow_rsp.1667820123 |
|
|
Aug 29 02:25:55 PM UTC 24 |
Aug 29 02:33:23 PM UTC 24 |
29001637729 ps |
| T2001 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/50.xbar_error_random.4133970166 |
|
|
Aug 29 02:31:58 PM UTC 24 |
Aug 29 02:33:25 PM UTC 24 |
2370432083 ps |
| T2002 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/41.xbar_random_large_delays.3289008007 |
|
|
Aug 29 02:18:46 PM UTC 24 |
Aug 29 02:33:44 PM UTC 24 |
58423649181 ps |
| T2003 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/51.xbar_random_zero_delays.3872875853 |
|
|
Aug 29 02:33:27 PM UTC 24 |
Aug 29 02:33:45 PM UTC 24 |
115313019 ps |
| T2004 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/51.xbar_random.3989993849 |
|
|
Aug 29 02:33:24 PM UTC 24 |
Aug 29 02:33:52 PM UTC 24 |
263800162 ps |
| T2005 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/51.xbar_error_random.638166960 |
|
|
Aug 29 02:33:44 PM UTC 24 |
Aug 29 02:33:59 PM UTC 24 |
106166541 ps |
| T2006 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/39.xbar_access_same_device_slow_rsp.1257022210 |
|
|
Aug 29 02:15:13 PM UTC 24 |
Aug 29 02:34:01 PM UTC 24 |
75074452131 ps |
| T2007 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/51.xbar_same_source.869980206 |
|
|
Aug 29 02:33:43 PM UTC 24 |
Aug 29 02:34:09 PM UTC 24 |
738947047 ps |
| T2008 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/51.xbar_smoke_large_delays.1609901935 |
|
|
Aug 29 02:33:12 PM UTC 24 |
Aug 29 02:34:10 PM UTC 24 |
5910429056 ps |
| T2009 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/51.xbar_error_and_unmapped_addr.2870981071 |
|
|
Aug 29 02:34:06 PM UTC 24 |
Aug 29 02:34:17 PM UTC 24 |
88741029 ps |
| T2010 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/45.xbar_stress_all_with_rand_reset.3285720794 |
|
|
Aug 29 02:25:07 PM UTC 24 |
Aug 29 02:34:18 PM UTC 24 |
7604726526 ps |
| T2011 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/47.xbar_stress_all.1305391997 |
|
|
Aug 29 02:27:30 PM UTC 24 |
Aug 29 02:34:21 PM UTC 24 |
4888945576 ps |
| T2012 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/41.xbar_random_slow_rsp.478795790 |
|
|
Aug 29 02:18:48 PM UTC 24 |
Aug 29 02:34:24 PM UTC 24 |
52174747388 ps |
| T2013 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/51.xbar_unmapped_addr.1016352186 |
|
|
Aug 29 02:34:02 PM UTC 24 |
Aug 29 02:34:28 PM UTC 24 |
559631307 ps |
| T2014 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/5.chip_same_csr_outstanding.1620022849 |
|
|
Aug 29 01:07:40 PM UTC 24 |
Aug 29 02:34:39 PM UTC 24 |
31504105478 ps |
| T849 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/26.xbar_access_same_device_slow_rsp.7857108 |
|
|
Aug 29 01:56:01 PM UTC 24 |
Aug 29 02:34:41 PM UTC 24 |
135347476338 ps |
| T2015 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/52.xbar_smoke.3665935571 |
|
|
Aug 29 02:34:28 PM UTC 24 |
Aug 29 02:34:45 PM UTC 24 |
276278346 ps |
| T2016 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/52.xbar_smoke_zero_delays.257162696 |
|
|
Aug 29 02:34:36 PM UTC 24 |
Aug 29 02:34:45 PM UTC 24 |
40789872 ps |
| T2017 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/50.xbar_stress_all_with_rand_reset.4258351572 |
|
|
Aug 29 02:32:22 PM UTC 24 |
Aug 29 02:34:47 PM UTC 24 |
290383886 ps |
| T2018 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/51.xbar_access_same_device.7266675 |
|
|
Aug 29 02:33:30 PM UTC 24 |
Aug 29 02:34:47 PM UTC 24 |
1569489412 ps |
| T2019 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/49.xbar_stress_all_with_reset_error.294443462 |
|
|
Aug 29 02:30:52 PM UTC 24 |
Aug 29 02:34:52 PM UTC 24 |
774865231 ps |
| T2020 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/51.xbar_smoke_slow_rsp.1010300299 |
|
|
Aug 29 02:33:16 PM UTC 24 |
Aug 29 02:35:07 PM UTC 24 |
4658421222 ps |
| T2021 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/49.xbar_stress_all_with_rand_reset.1037387310 |
|
|
Aug 29 02:30:43 PM UTC 24 |
Aug 29 02:35:17 PM UTC 24 |
1617249060 ps |