| T677 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/default/4.chip_sw_alert_handler_lpg_sleep_mode_alerts.2707938604 |
|
|
Aug 29 08:27:38 PM UTC 24 |
Aug 29 08:35:04 PM UTC 24 |
3610089398 ps |
| T1257 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/default/4.chip_sw_uart_tx_rx_idx1.3693308425 |
|
|
Aug 29 08:21:15 PM UTC 24 |
Aug 29 08:35:17 PM UTC 24 |
3820542882 ps |
| T1258 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/default/4.chip_tap_straps_testunlock0.3944986763 |
|
|
Aug 29 08:28:53 PM UTC 24 |
Aug 29 08:35:27 PM UTC 24 |
4587792079 ps |
| T1259 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_otbn_ecdsa_op_irq.1986710474 |
|
|
Aug 29 07:20:00 PM UTC 24 |
Aug 29 08:35:45 PM UTC 24 |
17098285964 ps |
| T1260 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/default/4.chip_tap_straps_dev.3845968526 |
|
|
Aug 29 08:28:44 PM UTC 24 |
Aug 29 08:36:13 PM UTC 24 |
4438444576 ps |
| T1261 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/default/4.chip_tap_straps_rma.3412391573 |
|
|
Aug 29 08:29:18 PM UTC 24 |
Aug 29 08:36:36 PM UTC 24 |
5193997197 ps |
| T1262 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_otbn_ecdsa_op_irq_jitter_en.2471255817 |
|
|
Aug 29 07:19:57 PM UTC 24 |
Aug 29 08:36:44 PM UTC 24 |
18589030967 ps |
| T1263 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/default/4.chip_sw_aon_timer_sleep_wdog_sleep_pause.3507171165 |
|
|
Aug 29 08:27:39 PM UTC 24 |
Aug 29 08:36:56 PM UTC 24 |
7990925428 ps |
| T1264 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/default/3.chip_sw_uart_tx_rx_alt_clk_freq_low_speed.2333045478 |
|
|
Aug 29 08:18:32 PM UTC 24 |
Aug 29 08:37:02 PM UTC 24 |
8200966071 ps |
| T701 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/default/5.chip_sw_alert_handler_lpg_sleep_mode_alerts.2008284085 |
|
|
Aug 29 08:32:34 PM UTC 24 |
Aug 29 08:39:47 PM UTC 24 |
3379741036 ps |
| T1265 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/default/5.chip_sw_lc_ctrl_transition.1163558092 |
|
|
Aug 29 08:31:15 PM UTC 24 |
Aug 29 08:39:53 PM UTC 24 |
7514820657 ps |
| T1266 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/default/5.chip_sw_uart_rand_baudrate.436990771 |
|
|
Aug 29 08:31:21 PM UTC 24 |
Aug 29 08:40:54 PM UTC 24 |
3606001666 ps |
| T762 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/default/6.chip_sw_alert_handler_lpg_sleep_mode_alerts.1461981145 |
|
|
Aug 29 08:34:10 PM UTC 24 |
Aug 29 08:40:57 PM UTC 24 |
4232948402 ps |
| T680 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/default/5.chip_sw_all_escalation_resets.2169511581 |
|
|
Aug 29 08:31:21 PM UTC 24 |
Aug 29 08:41:29 PM UTC 24 |
4755544464 ps |
| T166 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/default/4.chip_sw_sensor_ctrl_alert.2839546768 |
|
|
Aug 29 08:28:27 PM UTC 24 |
Aug 29 08:42:58 PM UTC 24 |
6447017216 ps |
| T293 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/default/5.chip_sw_data_integrity_escalation.1977928673 |
|
|
Aug 29 08:31:15 PM UTC 24 |
Aug 29 08:43:39 PM UTC 24 |
4651684500 ps |
| T261 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_flash_init_reduced_freq.954347092 |
|
|
Aug 29 08:03:29 PM UTC 24 |
Aug 29 08:43:59 PM UTC 24 |
18571512659 ps |
| T1267 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/default/7.chip_sw_uart_rand_baudrate.345583244 |
|
|
Aug 29 08:36:25 PM UTC 24 |
Aug 29 08:44:38 PM UTC 24 |
3586545064 ps |
| T1268 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/default/6.chip_sw_all_escalation_resets.1904315737 |
|
|
Aug 29 08:33:23 PM UTC 24 |
Aug 29 08:45:30 PM UTC 24 |
6365243334 ps |
| T1269 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/default/8.chip_sw_lc_ctrl_transition.2632209010 |
|
|
Aug 29 08:36:49 PM UTC 24 |
Aug 29 08:45:34 PM UTC 24 |
6582835864 ps |
| T1270 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/default/4.chip_sw_uart_tx_rx_alt_clk_freq_low_speed.1261304961 |
|
|
Aug 29 08:25:51 PM UTC 24 |
Aug 29 08:45:42 PM UTC 24 |
9042505038 ps |
| T763 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/default/8.chip_sw_alert_handler_lpg_sleep_mode_alerts.2266376407 |
|
|
Aug 29 08:37:45 PM UTC 24 |
Aug 29 08:46:00 PM UTC 24 |
3424747210 ps |
| T734 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/default/7.chip_sw_all_escalation_resets.1356992589 |
|
|
Aug 29 08:36:11 PM UTC 24 |
Aug 29 08:46:00 PM UTC 24 |
4184167400 ps |
| T745 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/default/7.chip_sw_alert_handler_lpg_sleep_mode_alerts.750598082 |
|
|
Aug 29 08:36:30 PM UTC 24 |
Aug 29 08:46:18 PM UTC 24 |
3874022440 ps |
| T671 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/default/9.chip_sw_alert_handler_lpg_sleep_mode_alerts.671435103 |
|
|
Aug 29 08:40:33 PM UTC 24 |
Aug 29 08:47:07 PM UTC 24 |
3522329256 ps |
| T1271 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/default/9.chip_sw_uart_rand_baudrate.328630516 |
|
|
Aug 29 08:37:44 PM UTC 24 |
Aug 29 08:47:27 PM UTC 24 |
4273560856 ps |
| T190 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/default/9.chip_sw_all_escalation_resets.2956055822 |
|
|
Aug 29 08:37:49 PM UTC 24 |
Aug 29 08:47:48 PM UTC 24 |
5122010534 ps |
| T1272 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/default/3.chip_sw_uart_tx_rx_alt_clk_freq.2561231652 |
|
|
Aug 29 08:17:47 PM UTC 24 |
Aug 29 08:48:59 PM UTC 24 |
8501023917 ps |
| T1273 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/default/3.chip_tap_straps_prod.725638040 |
|
|
Aug 29 08:20:16 PM UTC 24 |
Aug 29 08:49:32 PM UTC 24 |
14841216177 ps |
| T764 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/default/8.chip_sw_all_escalation_resets.2580053408 |
|
|
Aug 29 08:36:33 PM UTC 24 |
Aug 29 08:50:40 PM UTC 24 |
5122022472 ps |
| T727 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/default/10.chip_sw_alert_handler_lpg_sleep_mode_alerts.1137685805 |
|
|
Aug 29 08:43:33 PM UTC 24 |
Aug 29 08:51:01 PM UTC 24 |
4067383836 ps |
| T1274 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/default/6.chip_sw_lc_ctrl_transition.1800050656 |
|
|
Aug 29 08:34:09 PM UTC 24 |
Aug 29 08:51:41 PM UTC 24 |
13385831777 ps |
| T1275 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/default/10.chip_sw_lc_ctrl_transition.972046591 |
|
|
Aug 29 08:42:02 PM UTC 24 |
Aug 29 08:52:25 PM UTC 24 |
6813508833 ps |
| T211 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_flash_rma_unlocked.1267954854 |
|
|
Aug 29 06:59:51 PM UTC 24 |
Aug 29 08:52:53 PM UTC 24 |
44206419933 ps |
| T1276 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/default/11.chip_sw_lc_ctrl_transition.1266745359 |
|
|
Aug 29 08:45:11 PM UTC 24 |
Aug 29 08:53:01 PM UTC 24 |
6781821549 ps |
| T746 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/default/12.chip_sw_alert_handler_lpg_sleep_mode_alerts.3908151146 |
|
|
Aug 29 08:46:58 PM UTC 24 |
Aug 29 08:53:11 PM UTC 24 |
3101778480 ps |
| T1277 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_otbn_smoketest.3928088395 |
|
|
Aug 29 08:11:37 PM UTC 24 |
Aug 29 08:53:22 PM UTC 24 |
10323917228 ps |
| T698 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/default/11.chip_sw_alert_handler_lpg_sleep_mode_alerts.2270641443 |
|
|
Aug 29 08:46:57 PM UTC 24 |
Aug 29 08:54:01 PM UTC 24 |
3587912370 ps |
| T1278 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/default/7.chip_sw_lc_ctrl_transition.1374680353 |
|
|
Aug 29 08:36:32 PM UTC 24 |
Aug 29 08:55:15 PM UTC 24 |
8893952994 ps |
| T777 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/default/13.chip_sw_alert_handler_lpg_sleep_mode_alerts.2460832776 |
|
|
Aug 29 08:48:23 PM UTC 24 |
Aug 29 08:56:17 PM UTC 24 |
4161443838 ps |
| T276 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/default/10.chip_sw_all_escalation_resets.477560310 |
|
|
Aug 29 08:41:42 PM UTC 24 |
Aug 29 08:56:35 PM UTC 24 |
4857465800 ps |
| T309 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/default/12.chip_sw_all_escalation_resets.2186713684 |
|
|
Aug 29 08:47:06 PM UTC 24 |
Aug 29 08:56:40 PM UTC 24 |
4904882472 ps |
| T310 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/default/13.chip_sw_uart_rand_baudrate.2221536105 |
|
|
Aug 29 08:47:43 PM UTC 24 |
Aug 29 08:56:42 PM UTC 24 |
3889989078 ps |
| T311 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/default/12.chip_sw_uart_rand_baudrate.1301628651 |
|
|
Aug 29 08:47:07 PM UTC 24 |
Aug 29 08:57:22 PM UTC 24 |
3761000920 ps |
| T312 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/default/12.chip_sw_lc_ctrl_transition.695156027 |
|
|
Aug 29 08:47:09 PM UTC 24 |
Aug 29 08:57:46 PM UTC 24 |
5894842020 ps |
| T313 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/default/14.chip_sw_alert_handler_lpg_sleep_mode_alerts.1589482645 |
|
|
Aug 29 08:51:33 PM UTC 24 |
Aug 29 08:58:26 PM UTC 24 |
3125417874 ps |
| T314 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_csrng_edn_concurrency.2872457809 |
|
|
Aug 29 07:31:29 PM UTC 24 |
Aug 29 08:58:46 PM UTC 24 |
18228967490 ps |
| T315 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/default/1.rom_e2e_self_hash.3127361058 |
|
|
Aug 29 06:40:40 PM UTC 24 |
Aug 29 08:59:08 PM UTC 24 |
26287871268 ps |
| T316 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/default/11.chip_sw_all_escalation_resets.4048146285 |
|
|
Aug 29 08:44:15 PM UTC 24 |
Aug 29 08:59:11 PM UTC 24 |
5645438084 ps |
| T140 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_ast_clk_rst_inputs.1958291207 |
|
|
Aug 29 08:04:02 PM UTC 24 |
Aug 29 09:00:01 PM UTC 24 |
19477729790 ps |
| T1279 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/default/9.chip_sw_lc_ctrl_transition.3036249260 |
|
|
Aug 29 08:40:02 PM UTC 24 |
Aug 29 09:00:45 PM UTC 24 |
12017015698 ps |
| T721 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/default/15.chip_sw_alert_handler_lpg_sleep_mode_alerts.3064838344 |
|
|
Aug 29 08:54:02 PM UTC 24 |
Aug 29 09:01:17 PM UTC 24 |
4228454896 ps |
| T736 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/default/13.chip_sw_all_escalation_resets.681022930 |
|
|
Aug 29 08:47:11 PM UTC 24 |
Aug 29 09:01:41 PM UTC 24 |
5237171584 ps |
| T778 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/default/16.chip_sw_alert_handler_lpg_sleep_mode_alerts.3651746185 |
|
|
Aug 29 08:54:03 PM UTC 24 |
Aug 29 09:01:49 PM UTC 24 |
4060185270 ps |
| T775 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/default/14.chip_sw_all_escalation_resets.915635142 |
|
|
Aug 29 08:49:35 PM UTC 24 |
Aug 29 09:02:24 PM UTC 24 |
4941815462 ps |
| T1280 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/default/6.chip_sw_uart_rand_baudrate.3519313189 |
|
|
Aug 29 08:33:24 PM UTC 24 |
Aug 29 09:02:42 PM UTC 24 |
8321996390 ps |
| T1281 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_csrng_edn_concurrency.4034193661 |
|
|
Aug 29 06:03:25 PM UTC 24 |
Aug 29 09:03:36 PM UTC 24 |
32344098110 ps |
| T712 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/default/18.chip_sw_alert_handler_lpg_sleep_mode_alerts.1386782633 |
|
|
Aug 29 08:57:29 PM UTC 24 |
Aug 29 09:03:45 PM UTC 24 |
4089969436 ps |
| T1282 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/default/16.chip_sw_uart_rand_baudrate.399896669 |
|
|
Aug 29 08:54:04 PM UTC 24 |
Aug 29 09:03:58 PM UTC 24 |
3955239150 ps |
| T254 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_keymgr_sideload_otbn.137557752 |
|
|
Aug 29 07:36:55 PM UTC 24 |
Aug 29 09:04:11 PM UTC 24 |
18402422724 ps |
| T1283 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/default/3.chip_sw_uart_rand_baudrate.1014042763 |
|
|
Aug 29 08:17:38 PM UTC 24 |
Aug 29 09:04:24 PM UTC 24 |
12836426676 ps |
| T1284 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/default/13.chip_sw_lc_ctrl_transition.2980601867 |
|
|
Aug 29 08:47:58 PM UTC 24 |
Aug 29 09:04:40 PM UTC 24 |
12089159121 ps |
| T691 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/default/17.chip_sw_alert_handler_lpg_sleep_mode_alerts.1609437894 |
|
|
Aug 29 08:56:53 PM UTC 24 |
Aug 29 09:04:50 PM UTC 24 |
3469276528 ps |
| T277 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/default/15.chip_sw_all_escalation_resets.121346763 |
|
|
Aug 29 08:52:15 PM UTC 24 |
Aug 29 09:06:11 PM UTC 24 |
6423082120 ps |
| T695 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/default/19.chip_sw_alert_handler_lpg_sleep_mode_alerts.1206579272 |
|
|
Aug 29 08:59:02 PM UTC 24 |
Aug 29 09:06:26 PM UTC 24 |
4106880780 ps |
| T781 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/default/16.chip_sw_all_escalation_resets.2445267980 |
|
|
Aug 29 08:54:05 PM UTC 24 |
Aug 29 09:06:35 PM UTC 24 |
6108229698 ps |
| T1285 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_lc_walkthrough_dev.4228716887 |
|
|
Aug 29 07:03:10 PM UTC 24 |
Aug 29 09:07:16 PM UTC 24 |
47703754550 ps |
| T753 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/default/17.chip_sw_all_escalation_resets.146853671 |
|
|
Aug 29 08:54:37 PM UTC 24 |
Aug 29 09:07:18 PM UTC 24 |
5852109964 ps |
| T747 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/default/21.chip_sw_alert_handler_lpg_sleep_mode_alerts.4268252714 |
|
|
Aug 29 09:00:36 PM UTC 24 |
Aug 29 09:07:57 PM UTC 24 |
3610242296 ps |
| T1286 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/default/10.chip_sw_uart_rand_baudrate.2941666548 |
|
|
Aug 29 08:41:42 PM UTC 24 |
Aug 29 09:08:15 PM UTC 24 |
8079164158 ps |
| T1287 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/default/8.chip_sw_uart_rand_baudrate.383848349 |
|
|
Aug 29 08:36:45 PM UTC 24 |
Aug 29 09:08:18 PM UTC 24 |
8516055560 ps |
| T1288 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_lc_walkthrough_rma.188024645 |
|
|
Aug 29 07:05:51 PM UTC 24 |
Aug 29 09:08:37 PM UTC 24 |
47846411081 ps |
| T1289 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/default/19.chip_sw_uart_rand_baudrate.3024687860 |
|
|
Aug 29 08:58:21 PM UTC 24 |
Aug 29 09:08:37 PM UTC 24 |
4088602156 ps |
| T730 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/default/23.chip_sw_alert_handler_lpg_sleep_mode_alerts.4239947937 |
|
|
Aug 29 09:02:32 PM UTC 24 |
Aug 29 09:08:39 PM UTC 24 |
3559267170 ps |
| T716 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/default/20.chip_sw_alert_handler_lpg_sleep_mode_alerts.1803310782 |
|
|
Aug 29 08:59:55 PM UTC 24 |
Aug 29 09:08:54 PM UTC 24 |
3629898108 ps |
| T375 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/default/22.chip_sw_alert_handler_lpg_sleep_mode_alerts.2269459854 |
|
|
Aug 29 09:01:49 PM UTC 24 |
Aug 29 09:08:54 PM UTC 24 |
3832748936 ps |
| T385 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/default/21.chip_sw_all_escalation_resets.1880274232 |
|
|
Aug 29 08:59:55 PM UTC 24 |
Aug 29 09:09:13 PM UTC 24 |
5919167500 ps |
| T386 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/default/24.chip_sw_alert_handler_lpg_sleep_mode_alerts.1632859504 |
|
|
Aug 29 09:02:58 PM UTC 24 |
Aug 29 09:09:21 PM UTC 24 |
3624353780 ps |
| T387 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/default/19.chip_sw_all_escalation_resets.9780901 |
|
|
Aug 29 08:57:55 PM UTC 24 |
Aug 29 09:09:32 PM UTC 24 |
4823859144 ps |
| T388 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/default/18.chip_sw_all_escalation_resets.4055597507 |
|
|
Aug 29 08:57:29 PM UTC 24 |
Aug 29 09:10:13 PM UTC 24 |
6480612928 ps |
| T389 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/default/20.chip_sw_all_escalation_resets.504838052 |
|
|
Aug 29 08:59:19 PM UTC 24 |
Aug 29 09:10:56 PM UTC 24 |
5324711040 ps |
| T390 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_lc_walkthrough_prod.625184453 |
|
|
Aug 29 07:03:30 PM UTC 24 |
Aug 29 09:11:47 PM UTC 24 |
51656771839 ps |
| T391 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/default/28.chip_sw_alert_handler_lpg_sleep_mode_alerts.1652378857 |
|
|
Aug 29 09:05:31 PM UTC 24 |
Aug 29 09:11:53 PM UTC 24 |
4186803828 ps |
| T392 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/default/14.chip_sw_lc_ctrl_transition.2899248557 |
|
|
Aug 29 08:51:15 PM UTC 24 |
Aug 29 09:12:11 PM UTC 24 |
11483714805 ps |
| T393 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/default/25.chip_sw_all_escalation_resets.1440725253 |
|
|
Aug 29 09:03:18 PM UTC 24 |
Aug 29 09:12:40 PM UTC 24 |
5616182580 ps |
| T742 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/default/26.chip_sw_alert_handler_lpg_sleep_mode_alerts.915001149 |
|
|
Aug 29 09:04:59 PM UTC 24 |
Aug 29 09:12:51 PM UTC 24 |
4166685000 ps |
| T783 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/default/22.chip_sw_all_escalation_resets.2851262154 |
|
|
Aug 29 09:01:21 PM UTC 24 |
Aug 29 09:12:52 PM UTC 24 |
4552688376 ps |
| T697 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/default/27.chip_sw_alert_handler_lpg_sleep_mode_alerts.2112187898 |
|
|
Aug 29 09:05:24 PM UTC 24 |
Aug 29 09:12:53 PM UTC 24 |
4090055376 ps |
| T702 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/default/25.chip_sw_alert_handler_lpg_sleep_mode_alerts.4177700069 |
|
|
Aug 29 09:04:33 PM UTC 24 |
Aug 29 09:12:57 PM UTC 24 |
3731208704 ps |
| T1290 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/default/2.rom_e2e_asm_init_test_unlocked0.1748966417 |
|
|
Aug 29 08:09:55 PM UTC 24 |
Aug 29 09:13:02 PM UTC 24 |
11288610800 ps |
| T1291 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/default/11.chip_sw_uart_rand_baudrate.1625141757 |
|
|
Aug 29 08:44:34 PM UTC 24 |
Aug 29 09:13:36 PM UTC 24 |
7893127940 ps |
| T278 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/default/29.chip_sw_alert_handler_lpg_sleep_mode_alerts.872280847 |
|
|
Aug 29 09:07:13 PM UTC 24 |
Aug 29 09:13:48 PM UTC 24 |
3831790588 ps |
| T756 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/default/23.chip_sw_all_escalation_resets.3199456387 |
|
|
Aug 29 09:02:25 PM UTC 24 |
Aug 29 09:14:14 PM UTC 24 |
5067570840 ps |
| T773 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/default/24.chip_sw_all_escalation_resets.2030596024 |
|
|
Aug 29 09:02:31 PM UTC 24 |
Aug 29 09:14:55 PM UTC 24 |
4440085440 ps |
| T714 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/default/27.chip_sw_all_escalation_resets.189798708 |
|
|
Aug 29 09:05:23 PM UTC 24 |
Aug 29 09:15:16 PM UTC 24 |
6076815956 ps |
| T284 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/default/26.chip_sw_all_escalation_resets.3361111206 |
|
|
Aug 29 09:04:44 PM UTC 24 |
Aug 29 09:15:38 PM UTC 24 |
5345736920 ps |
| T751 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/default/30.chip_sw_alert_handler_lpg_sleep_mode_alerts.390321354 |
|
|
Aug 29 09:08:04 PM UTC 24 |
Aug 29 09:15:44 PM UTC 24 |
3525033428 ps |
| T1292 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/default/4.chip_sw_uart_tx_rx_alt_clk_freq.2523670783 |
|
|
Aug 29 08:25:46 PM UTC 24 |
Aug 29 09:16:21 PM UTC 24 |
12719141098 ps |
| T743 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/default/30.chip_sw_all_escalation_resets.2605288759 |
|
|
Aug 29 09:07:14 PM UTC 24 |
Aug 29 09:16:54 PM UTC 24 |
5982876740 ps |
| T731 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/default/29.chip_sw_all_escalation_resets.3517366998 |
|
|
Aug 29 09:06:55 PM UTC 24 |
Aug 29 09:17:09 PM UTC 24 |
4741791650 ps |
| T723 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/default/34.chip_sw_alert_handler_lpg_sleep_mode_alerts.3636801122 |
|
|
Aug 29 09:10:42 PM UTC 24 |
Aug 29 09:17:18 PM UTC 24 |
3466242560 ps |
| T1293 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/default/32.chip_sw_alert_handler_lpg_sleep_mode_alerts.2510280557 |
|
|
Aug 29 09:10:56 PM UTC 24 |
Aug 29 09:17:28 PM UTC 24 |
4209881660 ps |
| T338 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/default/31.chip_sw_alert_handler_lpg_sleep_mode_alerts.2027021875 |
|
|
Aug 29 09:08:33 PM UTC 24 |
Aug 29 09:17:47 PM UTC 24 |
3909934760 ps |
| T342 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/default/36.chip_sw_alert_handler_lpg_sleep_mode_alerts.1414835671 |
|
|
Aug 29 09:10:40 PM UTC 24 |
Aug 29 09:17:54 PM UTC 24 |
4105572318 ps |
| T343 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/default/35.chip_sw_alert_handler_lpg_sleep_mode_alerts.1807173084 |
|
|
Aug 29 09:11:07 PM UTC 24 |
Aug 29 09:18:02 PM UTC 24 |
3898748744 ps |
| T308 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/default/28.chip_sw_all_escalation_resets.889745877 |
|
|
Aug 29 09:05:30 PM UTC 24 |
Aug 29 09:18:45 PM UTC 24 |
5501237480 ps |
| T344 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/default/14.chip_sw_uart_rand_baudrate.3880567479 |
|
|
Aug 29 08:50:07 PM UTC 24 |
Aug 29 09:18:51 PM UTC 24 |
8695679792 ps |
| T102 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/default/37.chip_sw_alert_handler_lpg_sleep_mode_alerts.1867476938 |
|
|
Aug 29 09:11:14 PM UTC 24 |
Aug 29 09:19:23 PM UTC 24 |
3532570074 ps |
| T106 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/default/33.chip_sw_alert_handler_lpg_sleep_mode_alerts.2290022841 |
|
|
Aug 29 09:11:06 PM UTC 24 |
Aug 29 09:19:40 PM UTC 24 |
4334166576 ps |
| T107 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/default/36.chip_sw_all_escalation_resets.657724282 |
|
|
Aug 29 09:10:59 PM UTC 24 |
Aug 29 09:20:01 PM UTC 24 |
4809009958 ps |
| T108 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/default/31.chip_sw_all_escalation_resets.1325869245 |
|
|
Aug 29 09:08:04 PM UTC 24 |
Aug 29 09:20:23 PM UTC 24 |
4633650790 ps |
| T109 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/default/39.chip_sw_alert_handler_lpg_sleep_mode_alerts.2637324904 |
|
|
Aug 29 09:13:01 PM UTC 24 |
Aug 29 09:20:35 PM UTC 24 |
4015624884 ps |
| T110 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/default/32.chip_sw_all_escalation_resets.825287947 |
|
|
Aug 29 09:09:29 PM UTC 24 |
Aug 29 09:20:46 PM UTC 24 |
5919503736 ps |
| T111 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_csrng_edn_concurrency_reduced_freq.4229739686 |
|
|
Aug 29 08:03:42 PM UTC 24 |
Aug 29 09:21:01 PM UTC 24 |
21936729010 ps |
| T112 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/default/2.rom_e2e_shutdown_output.1382295396 |
|
|
Aug 29 08:07:49 PM UTC 24 |
Aug 29 09:21:27 PM UTC 24 |
29871920680 ps |
| T113 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/default/2.rom_e2e_shutdown_exception_c.119971142 |
|
|
Aug 29 08:05:39 PM UTC 24 |
Aug 29 09:21:43 PM UTC 24 |
14293882375 ps |
| T114 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/default/33.chip_sw_all_escalation_resets.1160179298 |
|
|
Aug 29 09:10:24 PM UTC 24 |
Aug 29 09:21:46 PM UTC 24 |
5276549960 ps |
| T103 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/default/38.chip_sw_alert_handler_lpg_sleep_mode_alerts.2012357315 |
|
|
Aug 29 09:13:00 PM UTC 24 |
Aug 29 09:21:53 PM UTC 24 |
3854655496 ps |
| T717 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/default/40.chip_sw_alert_handler_lpg_sleep_mode_alerts.2137587721 |
|
|
Aug 29 09:14:19 PM UTC 24 |
Aug 29 09:22:03 PM UTC 24 |
3616102372 ps |
| T104 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/default/42.chip_sw_alert_handler_lpg_sleep_mode_alerts.3446752200 |
|
|
Aug 29 09:15:01 PM UTC 24 |
Aug 29 09:22:14 PM UTC 24 |
3917754886 ps |
| T681 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/default/35.chip_sw_all_escalation_resets.3165939287 |
|
|
Aug 29 09:11:06 PM UTC 24 |
Aug 29 09:22:38 PM UTC 24 |
5217222896 ps |
| T1294 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/default/15.chip_sw_uart_rand_baudrate.954026250 |
|
|
Aug 29 08:53:02 PM UTC 24 |
Aug 29 09:22:52 PM UTC 24 |
8687322770 ps |
| T682 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/default/34.chip_sw_all_escalation_resets.611383142 |
|
|
Aug 29 09:10:55 PM UTC 24 |
Aug 29 09:22:52 PM UTC 24 |
6170337746 ps |
| T1295 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/default/44.chip_sw_alert_handler_lpg_sleep_mode_alerts.2468834956 |
|
|
Aug 29 09:15:06 PM UTC 24 |
Aug 29 09:23:08 PM UTC 24 |
3360273920 ps |
| T754 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/default/43.chip_sw_alert_handler_lpg_sleep_mode_alerts.4219833239 |
|
|
Aug 29 09:15:05 PM UTC 24 |
Aug 29 09:23:10 PM UTC 24 |
3729685564 ps |
| T779 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/default/41.chip_sw_alert_handler_lpg_sleep_mode_alerts.2109934697 |
|
|
Aug 29 09:14:57 PM UTC 24 |
Aug 29 09:23:16 PM UTC 24 |
4164962408 ps |
| T1296 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/default/2.rom_e2e_asm_init_rma.1937901565 |
|
|
Aug 29 08:09:16 PM UTC 24 |
Aug 29 09:23:19 PM UTC 24 |
14736047080 ps |
| T1297 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/default/2.rom_e2e_smoke.3819115224 |
|
|
Aug 29 08:05:37 PM UTC 24 |
Aug 29 09:23:42 PM UTC 24 |
15072642600 ps |
| T674 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/default/37.chip_sw_all_escalation_resets.57107469 |
|
|
Aug 29 09:11:12 PM UTC 24 |
Aug 29 09:24:01 PM UTC 24 |
4897018610 ps |
| T339 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/default/38.chip_sw_all_escalation_resets.3455523361 |
|
|
Aug 29 09:11:30 PM UTC 24 |
Aug 29 09:24:05 PM UTC 24 |
5657462040 ps |
| T707 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/default/41.chip_sw_all_escalation_resets.2967671104 |
|
|
Aug 29 09:14:19 PM UTC 24 |
Aug 29 09:24:15 PM UTC 24 |
5092014410 ps |
| T236 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_uart_tx_rx_bootstrap.1156323845 |
|
|
Aug 29 03:35:56 PM UTC 24 |
Aug 29 09:24:15 PM UTC 24 |
79099398090 ps |
| T340 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/default/43.chip_sw_all_escalation_resets.102559193 |
|
|
Aug 29 09:14:13 PM UTC 24 |
Aug 29 09:24:19 PM UTC 24 |
5100450560 ps |
| T719 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/default/45.chip_sw_alert_handler_lpg_sleep_mode_alerts.2088264388 |
|
|
Aug 29 09:15:51 PM UTC 24 |
Aug 29 09:24:43 PM UTC 24 |
3721896494 ps |
| T675 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/default/48.chip_sw_alert_handler_lpg_sleep_mode_alerts.1885328193 |
|
|
Aug 29 09:18:10 PM UTC 24 |
Aug 29 09:24:46 PM UTC 24 |
4172177960 ps |
| T732 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/default/39.chip_sw_all_escalation_resets.543760894 |
|
|
Aug 29 09:12:59 PM UTC 24 |
Aug 29 09:25:06 PM UTC 24 |
4797402624 ps |
| T771 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/default/47.chip_sw_alert_handler_lpg_sleep_mode_alerts.1993017855 |
|
|
Aug 29 09:17:29 PM UTC 24 |
Aug 29 09:25:14 PM UTC 24 |
3787927048 ps |
| T782 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/default/44.chip_sw_all_escalation_resets.3317481749 |
|
|
Aug 29 09:15:06 PM UTC 24 |
Aug 29 09:25:22 PM UTC 24 |
4989724160 ps |
| T785 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/default/51.chip_sw_alert_handler_lpg_sleep_mode_alerts.1576724656 |
|
|
Aug 29 09:19:33 PM UTC 24 |
Aug 29 09:25:32 PM UTC 24 |
3668795228 ps |
| T1298 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/default/2.rom_e2e_keymgr_init_rom_ext_meas.2748239680 |
|
|
Aug 29 08:10:01 PM UTC 24 |
Aug 29 09:25:49 PM UTC 24 |
14791019540 ps |
| T690 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/default/49.chip_sw_alert_handler_lpg_sleep_mode_alerts.2634442081 |
|
|
Aug 29 09:18:47 PM UTC 24 |
Aug 29 09:25:53 PM UTC 24 |
3611186200 ps |
| T285 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/default/40.chip_sw_all_escalation_resets.3236405154 |
|
|
Aug 29 09:13:45 PM UTC 24 |
Aug 29 09:26:02 PM UTC 24 |
5642202288 ps |
| T1299 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/default/2.rom_e2e_keymgr_init_rom_ext_no_meas.4230704488 |
|
|
Aug 29 08:10:08 PM UTC 24 |
Aug 29 09:26:06 PM UTC 24 |
15729731866 ps |
| T1300 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/default/2.rom_e2e_asm_init_dev.820323241 |
|
|
Aug 29 08:09:36 PM UTC 24 |
Aug 29 09:26:10 PM UTC 24 |
15274671823 ps |
| T786 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/default/50.chip_sw_alert_handler_lpg_sleep_mode_alerts.2683437097 |
|
|
Aug 29 09:18:51 PM UTC 24 |
Aug 29 09:26:17 PM UTC 24 |
4514890122 ps |
| T1301 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq.2078612201 |
|
|
Aug 29 08:01:22 PM UTC 24 |
Aug 29 09:26:19 PM UTC 24 |
25107622369 ps |
| T1302 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/default/2.rom_e2e_keymgr_init_rom_ext_invalid_meas.3979883493 |
|
|
Aug 29 08:10:02 PM UTC 24 |
Aug 29 09:26:34 PM UTC 24 |
15336873310 ps |
| T1303 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/default/52.chip_sw_alert_handler_lpg_sleep_mode_alerts.1124346890 |
|
|
Aug 29 09:20:17 PM UTC 24 |
Aug 29 09:26:43 PM UTC 24 |
3991797564 ps |
| T765 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/default/45.chip_sw_all_escalation_resets.2724385548 |
|
|
Aug 29 09:15:27 PM UTC 24 |
Aug 29 09:26:54 PM UTC 24 |
4601735982 ps |
| T699 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/default/42.chip_sw_all_escalation_resets.1817821821 |
|
|
Aug 29 09:14:54 PM UTC 24 |
Aug 29 09:27:09 PM UTC 24 |
6120129470 ps |
| T733 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/default/47.chip_sw_all_escalation_resets.3199784296 |
|
|
Aug 29 09:16:55 PM UTC 24 |
Aug 29 09:27:37 PM UTC 24 |
5729837820 ps |
| T739 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/default/54.chip_sw_alert_handler_lpg_sleep_mode_alerts.186558158 |
|
|
Aug 29 09:21:35 PM UTC 24 |
Aug 29 09:27:44 PM UTC 24 |
4314012664 ps |
| T748 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/default/46.chip_sw_all_escalation_resets.1276304065 |
|
|
Aug 29 09:16:21 PM UTC 24 |
Aug 29 09:27:49 PM UTC 24 |
6056068676 ps |
| T749 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/default/53.chip_sw_alert_handler_lpg_sleep_mode_alerts.1505976182 |
|
|
Aug 29 09:21:17 PM UTC 24 |
Aug 29 09:28:01 PM UTC 24 |
3367730268 ps |
| T1304 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/default/2.rom_e2e_asm_init_prod_end.2093705069 |
|
|
Aug 29 08:10:14 PM UTC 24 |
Aug 29 09:28:06 PM UTC 24 |
15151943548 ps |
| T692 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/default/55.chip_sw_alert_handler_lpg_sleep_mode_alerts.3211499679 |
|
|
Aug 29 09:22:03 PM UTC 24 |
Aug 29 09:28:07 PM UTC 24 |
3743698920 ps |
| T722 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/default/50.chip_sw_all_escalation_resets.1697156742 |
|
|
Aug 29 09:18:51 PM UTC 24 |
Aug 29 09:28:10 PM UTC 24 |
5462631704 ps |
| T737 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/default/56.chip_sw_alert_handler_lpg_sleep_mode_alerts.3998695860 |
|
|
Aug 29 09:22:58 PM UTC 24 |
Aug 29 09:28:12 PM UTC 24 |
3255509494 ps |
| T1305 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/default/18.chip_sw_uart_rand_baudrate.1864631117 |
|
|
Aug 29 08:57:34 PM UTC 24 |
Aug 29 09:28:36 PM UTC 24 |
9417813258 ps |
| T768 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/default/49.chip_sw_all_escalation_resets.1573055854 |
|
|
Aug 29 09:18:09 PM UTC 24 |
Aug 29 09:29:02 PM UTC 24 |
5019522060 ps |
| T788 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/default/48.chip_sw_all_escalation_resets.3661829830 |
|
|
Aug 29 09:18:08 PM UTC 24 |
Aug 29 09:29:27 PM UTC 24 |
4682514300 ps |
| T1306 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/default/2.rom_e2e_asm_init_prod.543846236 |
|
|
Aug 29 08:09:55 PM UTC 24 |
Aug 29 09:29:40 PM UTC 24 |
15828915046 ps |
| T684 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/default/51.chip_sw_all_escalation_resets.3981675009 |
|
|
Aug 29 09:19:32 PM UTC 24 |
Aug 29 09:29:55 PM UTC 24 |
6800941310 ps |
| T724 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/default/57.chip_sw_alert_handler_lpg_sleep_mode_alerts.2119035806 |
|
|
Aug 29 09:24:17 PM UTC 24 |
Aug 29 09:30:01 PM UTC 24 |
4485862724 ps |
| T1307 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/default/53.chip_sw_all_escalation_resets.3884057510 |
|
|
Aug 29 09:20:35 PM UTC 24 |
Aug 29 09:30:08 PM UTC 24 |
5550005840 ps |
| T738 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/default/58.chip_sw_alert_handler_lpg_sleep_mode_alerts.4136577984 |
|
|
Aug 29 09:24:27 PM UTC 24 |
Aug 29 09:30:30 PM UTC 24 |
4339765130 ps |
| T704 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/default/59.chip_sw_alert_handler_lpg_sleep_mode_alerts.2568080695 |
|
|
Aug 29 09:25:03 PM UTC 24 |
Aug 29 09:30:34 PM UTC 24 |
3851649318 ps |
| T787 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/default/54.chip_sw_all_escalation_resets.3068018825 |
|
|
Aug 29 09:21:34 PM UTC 24 |
Aug 29 09:30:49 PM UTC 24 |
5059120900 ps |
| T683 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/default/58.chip_sw_all_escalation_resets.2156364085 |
|
|
Aug 29 09:23:53 PM UTC 24 |
Aug 29 09:30:59 PM UTC 24 |
4682404352 ps |
| T676 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/default/52.chip_sw_all_escalation_resets.676999974 |
|
|
Aug 29 09:19:59 PM UTC 24 |
Aug 29 09:31:20 PM UTC 24 |
6271874120 ps |
| T726 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/default/55.chip_sw_all_escalation_resets.1520489858 |
|
|
Aug 29 09:21:40 PM UTC 24 |
Aug 29 09:31:24 PM UTC 24 |
5260334574 ps |
| T271 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/default/56.chip_sw_all_escalation_resets.671686868 |
|
|
Aug 29 09:23:41 PM UTC 24 |
Aug 29 09:31:30 PM UTC 24 |
4680698354 ps |
| T1308 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/default/2.rom_e2e_static_critical.4120582047 |
|
|
Aug 29 08:10:14 PM UTC 24 |
Aug 29 09:32:16 PM UTC 24 |
16771439720 ps |
| T769 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/default/62.chip_sw_all_escalation_resets.7917643 |
|
|
Aug 29 09:25:50 PM UTC 24 |
Aug 29 09:32:37 PM UTC 24 |
5649149532 ps |
| T735 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/default/60.chip_sw_alert_handler_lpg_sleep_mode_alerts.1421895530 |
|
|
Aug 29 09:27:58 PM UTC 24 |
Aug 29 09:33:12 PM UTC 24 |
3879183490 ps |
| T341 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/default/64.chip_sw_alert_handler_lpg_sleep_mode_alerts.3032027345 |
|
|
Aug 29 09:27:51 PM UTC 24 |
Aug 29 09:33:30 PM UTC 24 |
3219292802 ps |
| T705 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/default/61.chip_sw_alert_handler_lpg_sleep_mode_alerts.4197566628 |
|
|
Aug 29 09:29:19 PM UTC 24 |
Aug 29 09:35:05 PM UTC 24 |
3833830082 ps |
| T1309 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/default/67.chip_sw_alert_handler_lpg_sleep_mode_alerts.410590303 |
|
|
Aug 29 09:28:02 PM UTC 24 |
Aug 29 09:35:10 PM UTC 24 |
4316961100 ps |
| T700 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/default/61.chip_sw_all_escalation_resets.3333497595 |
|
|
Aug 29 09:25:19 PM UTC 24 |
Aug 29 09:35:25 PM UTC 24 |
4873645180 ps |
| T711 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/default/63.chip_sw_alert_handler_lpg_sleep_mode_alerts.1290042688 |
|
|
Aug 29 09:30:06 PM UTC 24 |
Aug 29 09:35:36 PM UTC 24 |
3729747800 ps |
| T761 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/default/69.chip_sw_alert_handler_lpg_sleep_mode_alerts.2040458545 |
|
|
Aug 29 09:29:56 PM UTC 24 |
Aug 29 09:35:37 PM UTC 24 |
3698381934 ps |
| T750 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/default/62.chip_sw_alert_handler_lpg_sleep_mode_alerts.3633948268 |
|
|
Aug 29 09:28:26 PM UTC 24 |
Aug 29 09:35:58 PM UTC 24 |
4312787308 ps |
| T780 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/default/73.chip_sw_alert_handler_lpg_sleep_mode_alerts.2281974218 |
|
|
Aug 29 09:29:58 PM UTC 24 |
Aug 29 09:36:08 PM UTC 24 |
4035337504 ps |
| T715 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/default/68.chip_sw_all_escalation_resets.2893982379 |
|
|
Aug 29 09:27:01 PM UTC 24 |
Aug 29 09:36:14 PM UTC 24 |
5802070340 ps |
| T1310 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/default/57.chip_sw_all_escalation_resets.4263429309 |
|
|
Aug 29 09:27:00 PM UTC 24 |
Aug 29 09:36:37 PM UTC 24 |
4316573640 ps |
| T740 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/default/65.chip_sw_alert_handler_lpg_sleep_mode_alerts.2443266701 |
|
|
Aug 29 09:29:49 PM UTC 24 |
Aug 29 09:36:39 PM UTC 24 |
3782659320 ps |
| T1311 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/default/66.chip_sw_alert_handler_lpg_sleep_mode_alerts.1990550162 |
|
|
Aug 29 09:29:41 PM UTC 24 |
Aug 29 09:36:41 PM UTC 24 |
3511374244 ps |
| T1312 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/default/76.chip_sw_alert_handler_lpg_sleep_mode_alerts.3873241504 |
|
|
Aug 29 09:30:07 PM UTC 24 |
Aug 29 09:37:21 PM UTC 24 |
3585198544 ps |
| T1313 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/default/66.chip_sw_all_escalation_resets.2293540390 |
|
|
Aug 29 09:28:55 PM UTC 24 |
Aug 29 09:37:23 PM UTC 24 |
6225852620 ps |
| T744 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/default/75.chip_sw_alert_handler_lpg_sleep_mode_alerts.2225372112 |
|
|
Aug 29 09:31:34 PM UTC 24 |
Aug 29 09:37:24 PM UTC 24 |
3936516226 ps |
| T713 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/default/63.chip_sw_all_escalation_resets.3198722135 |
|
|
Aug 29 09:27:23 PM UTC 24 |
Aug 29 09:37:33 PM UTC 24 |
5545035520 ps |
| T376 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/default/77.chip_sw_alert_handler_lpg_sleep_mode_alerts.598817332 |
|
|
Aug 29 09:30:05 PM UTC 24 |
Aug 29 09:37:37 PM UTC 24 |
3470960610 ps |
| T693 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/default/72.chip_sw_alert_handler_lpg_sleep_mode_alerts.3695923913 |
|
|
Aug 29 09:30:50 PM UTC 24 |
Aug 29 09:37:43 PM UTC 24 |
3333745890 ps |
| T772 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/default/78.chip_sw_alert_handler_lpg_sleep_mode_alerts.3294815629 |
|
|
Aug 29 09:30:09 PM UTC 24 |
Aug 29 09:37:50 PM UTC 24 |
3514882506 ps |
| T1314 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/default/74.chip_sw_alert_handler_lpg_sleep_mode_alerts.4095024136 |
|
|
Aug 29 09:30:51 PM UTC 24 |
Aug 29 09:38:13 PM UTC 24 |
4264154462 ps |
| T766 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/default/80.chip_sw_alert_handler_lpg_sleep_mode_alerts.1807658393 |
|
|
Aug 29 09:32:09 PM UTC 24 |
Aug 29 09:38:33 PM UTC 24 |
3365865472 ps |
| T377 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/default/79.chip_sw_alert_handler_lpg_sleep_mode_alerts.4070449047 |
|
|
Aug 29 09:31:03 PM UTC 24 |
Aug 29 09:38:35 PM UTC 24 |
4305493644 ps |
| T672 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/default/60.chip_sw_all_escalation_resets.3623299086 |
|
|
Aug 29 09:30:37 PM UTC 24 |
Aug 29 09:38:45 PM UTC 24 |
4442404844 ps |
| T755 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/default/72.chip_sw_all_escalation_resets.2635040899 |
|
|
Aug 29 09:28:40 PM UTC 24 |
Aug 29 09:38:52 PM UTC 24 |
5032445020 ps |
| T1315 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/default/59.chip_sw_all_escalation_resets.3413485238 |
|
|
Aug 29 09:27:44 PM UTC 24 |
Aug 29 09:39:11 PM UTC 24 |
5018167718 ps |
| T706 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/default/70.chip_sw_alert_handler_lpg_sleep_mode_alerts.1003484150 |
|
|
Aug 29 09:32:07 PM UTC 24 |
Aug 29 09:39:12 PM UTC 24 |
4100768664 ps |
| T383 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/default/71.chip_sw_all_escalation_resets.3255598576 |
|
|
Aug 29 09:29:40 PM UTC 24 |
Aug 29 09:39:35 PM UTC 24 |
6443044680 ps |
| T708 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/default/82.chip_sw_alert_handler_lpg_sleep_mode_alerts.2435108351 |
|
|
Aug 29 09:33:10 PM UTC 24 |
Aug 29 09:39:41 PM UTC 24 |
4173829122 ps |
| T729 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/default/81.chip_sw_alert_handler_lpg_sleep_mode_alerts.2259977599 |
|
|
Aug 29 09:32:55 PM UTC 24 |
Aug 29 09:39:47 PM UTC 24 |
3597333342 ps |
| T1316 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/default/86.chip_sw_alert_handler_lpg_sleep_mode_alerts.3743401055 |
|
|
Aug 29 09:34:06 PM UTC 24 |
Aug 29 09:39:50 PM UTC 24 |
4386751240 ps |
| T678 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/default/71.chip_sw_alert_handler_lpg_sleep_mode_alerts.1911990634 |
|
|
Aug 29 09:33:21 PM UTC 24 |
Aug 29 09:40:07 PM UTC 24 |
3554145080 ps |
| T1317 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/default/65.chip_sw_all_escalation_resets.1599367884 |
|
|
Aug 29 09:30:05 PM UTC 24 |
Aug 29 09:40:09 PM UTC 24 |
4692996220 ps |
| T789 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/default/75.chip_sw_all_escalation_resets.3393421461 |
|
|
Aug 29 09:29:49 PM UTC 24 |
Aug 29 09:40:23 PM UTC 24 |
4796828560 ps |
| T770 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/default/78.chip_sw_all_escalation_resets.1039743972 |
|
|
Aug 29 09:30:10 PM UTC 24 |
Aug 29 09:40:38 PM UTC 24 |
4364079416 ps |
| T1318 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/default/70.chip_sw_all_escalation_resets.3083842643 |
|
|
Aug 29 09:30:38 PM UTC 24 |
Aug 29 09:40:43 PM UTC 24 |
6392941304 ps |
| T1319 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/default/17.chip_sw_uart_rand_baudrate.506322960 |
|
|
Aug 29 08:55:51 PM UTC 24 |
Aug 29 09:41:11 PM UTC 24 |
13076444870 ps |
| T767 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/default/77.chip_sw_all_escalation_resets.708301980 |
|
|
Aug 29 09:30:09 PM UTC 24 |
Aug 29 09:41:15 PM UTC 24 |
4856564432 ps |
| T752 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/default/83.chip_sw_alert_handler_lpg_sleep_mode_alerts.832248041 |
|
|
Aug 29 09:33:13 PM UTC 24 |
Aug 29 09:41:22 PM UTC 24 |
4023863850 ps |
| T384 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/default/84.chip_sw_alert_handler_lpg_sleep_mode_alerts.1365806112 |
|
|
Aug 29 09:33:12 PM UTC 24 |
Aug 29 09:41:38 PM UTC 24 |
3535436480 ps |
| T741 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/default/64.chip_sw_all_escalation_resets.302383397 |
|
|
Aug 29 09:29:56 PM UTC 24 |
Aug 29 09:42:05 PM UTC 24 |
4981150822 ps |
| T1320 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/default/8.chip_sw_csrng_edn_concurrency.2791598970 |
|
|
Aug 29 08:37:48 PM UTC 24 |
Aug 29 09:42:10 PM UTC 24 |
13982608636 ps |
| T1321 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/default/76.chip_sw_all_escalation_resets.3309998365 |
|
|
Aug 29 09:30:23 PM UTC 24 |
Aug 29 09:42:27 PM UTC 24 |
5786116028 ps |
| T696 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/default/80.chip_sw_all_escalation_resets.4218134924 |
|
|
Aug 29 09:31:29 PM UTC 24 |
Aug 29 09:42:38 PM UTC 24 |
4849469844 ps |
| T694 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/default/74.chip_sw_all_escalation_resets.131165348 |
|
|
Aug 29 09:31:29 PM UTC 24 |
Aug 29 09:42:47 PM UTC 24 |
4864361808 ps |
| T776 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/default/69.chip_sw_all_escalation_resets.2814243038 |
|
|
Aug 29 09:31:30 PM UTC 24 |
Aug 29 09:43:17 PM UTC 24 |
4872203336 ps |
| T272 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/default/86.chip_sw_all_escalation_resets.3318690583 |
|
|
Aug 29 09:33:46 PM UTC 24 |
Aug 29 09:43:23 PM UTC 24 |
4750425848 ps |
| T703 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/default/81.chip_sw_all_escalation_resets.1281564207 |
|
|
Aug 29 09:32:57 PM UTC 24 |
Aug 29 09:43:24 PM UTC 24 |
5075001400 ps |
| T759 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/default/67.chip_sw_all_escalation_resets.78127642 |
|
|
Aug 29 09:30:26 PM UTC 24 |
Aug 29 09:43:25 PM UTC 24 |
5988963120 ps |
| T673 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/default/87.chip_sw_alert_handler_lpg_sleep_mode_alerts.1037156425 |
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|
Aug 29 09:36:33 PM UTC 24 |
Aug 29 09:43:37 PM UTC 24 |
3706499600 ps |
| T790 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/default/73.chip_sw_all_escalation_resets.286524053 |
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|
Aug 29 09:31:45 PM UTC 24 |
Aug 29 09:43:38 PM UTC 24 |
4364484094 ps |
| T1322 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/default/84.chip_sw_all_escalation_resets.2637330302 |
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|
Aug 29 09:32:44 PM UTC 24 |
Aug 29 09:43:40 PM UTC 24 |
5243913600 ps |
| T757 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/default/89.chip_sw_alert_handler_lpg_sleep_mode_alerts.753845781 |
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|
Aug 29 09:37:25 PM UTC 24 |
Aug 29 09:43:41 PM UTC 24 |
3264714024 ps |
| T784 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/default/79.chip_sw_all_escalation_resets.1524808906 |
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|
Aug 29 09:32:55 PM UTC 24 |
Aug 29 09:43:46 PM UTC 24 |
6130238292 ps |
| T1323 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/default/83.chip_sw_all_escalation_resets.741321432 |
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|
Aug 29 09:33:22 PM UTC 24 |
Aug 29 09:44:10 PM UTC 24 |
4905450048 ps |
| T720 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/default/87.chip_sw_all_escalation_resets.586387383 |
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|
Aug 29 09:35:58 PM UTC 24 |
Aug 29 09:44:10 PM UTC 24 |
5078223720 ps |
| T760 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/default/88.chip_sw_alert_handler_lpg_sleep_mode_alerts.3215726262 |
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|
Aug 29 09:37:00 PM UTC 24 |
Aug 29 09:44:16 PM UTC 24 |
3931897496 ps |
| T105 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/default/85.chip_sw_all_escalation_resets.3751257530 |
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|
Aug 29 09:33:20 PM UTC 24 |
Aug 29 09:45:47 PM UTC 24 |
4966578776 ps |
| T1324 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/default/88.chip_sw_all_escalation_resets.2081855292 |
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|
Aug 29 09:37:39 PM UTC 24 |
Aug 29 09:45:47 PM UTC 24 |
5724725816 ps |
| T1325 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/default/82.chip_sw_all_escalation_resets.2861967079 |
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|
Aug 29 09:33:14 PM UTC 24 |
Aug 29 09:46:07 PM UTC 24 |
6603459400 ps |
| T679 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/default/94.chip_sw_all_escalation_resets.3849173843 |
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|
Aug 29 09:37:56 PM UTC 24 |
Aug 29 09:46:16 PM UTC 24 |
4860937512 ps |
| T1326 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/default/93.chip_sw_all_escalation_resets.3358107013 |
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|
Aug 29 09:38:58 PM UTC 24 |
Aug 29 09:46:58 PM UTC 24 |
4217385760 ps |
| T709 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/default/99.chip_sw_all_escalation_resets.1738660389 |
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|
Aug 29 09:39:06 PM UTC 24 |
Aug 29 09:47:02 PM UTC 24 |
5228560500 ps |
| T1327 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/default/95.chip_sw_all_escalation_resets.2395926029 |
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|
Aug 29 09:38:49 PM UTC 24 |
Aug 29 09:47:19 PM UTC 24 |
5784664432 ps |
| T1328 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/default/90.chip_sw_all_escalation_resets.1556881450 |
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|
Aug 29 09:38:23 PM UTC 24 |
Aug 29 09:47:48 PM UTC 24 |
4259804196 ps |
| T1329 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/default/97.chip_sw_all_escalation_resets.10428521 |
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|
Aug 29 09:39:05 PM UTC 24 |
Aug 29 09:47:59 PM UTC 24 |
5208923956 ps |
| T718 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/default/89.chip_sw_all_escalation_resets.60411718 |
|
|
Aug 29 09:38:52 PM UTC 24 |
Aug 29 09:48:00 PM UTC 24 |
6040271126 ps |
| T1330 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/default/98.chip_sw_all_escalation_resets.2232388458 |
|
|
Aug 29 09:39:01 PM UTC 24 |
Aug 29 09:48:07 PM UTC 24 |
5515853392 ps |
| T774 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/default/91.chip_sw_all_escalation_resets.4081039886 |
|
|
Aug 29 09:38:48 PM UTC 24 |
Aug 29 09:48:16 PM UTC 24 |
6142603754 ps |
| T1331 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/default/96.chip_sw_all_escalation_resets.2106103462 |
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|
Aug 29 09:38:58 PM UTC 24 |
Aug 29 09:48:36 PM UTC 24 |
5820224200 ps |
| T1332 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/default/7.chip_sw_csrng_edn_concurrency.2149369626 |
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|
Aug 29 08:36:31 PM UTC 24 |
Aug 29 09:49:57 PM UTC 24 |
17184752200 ps |
| T374 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_inject_scramble_seed.2573932314 |
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|
Aug 29 05:28:10 PM UTC 24 |
Aug 29 10:01:48 PM UTC 24 |
65212849139 ps |
| T1333 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/default/2.rom_e2e_self_hash.1753106094 |
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|
Aug 29 08:10:16 PM UTC 24 |
Aug 29 10:04:14 PM UTC 24 |
26188473500 ps |
| T1334 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/default/3.chip_sw_csrng_edn_concurrency.3066018755 |
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|
Aug 29 08:19:06 PM UTC 24 |
Aug 29 10:06:07 PM UTC 24 |
24695063750 ps |
| T1335 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/default/5.chip_sw_csrng_edn_concurrency.2150158828 |
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|
Aug 29 08:32:35 PM UTC 24 |
Aug 29 10:06:38 PM UTC 24 |
24237546100 ps |
| T1336 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/default/4.chip_sw_csrng_edn_concurrency.4026060776 |
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|
Aug 29 08:28:22 PM UTC 24 |
Aug 29 10:06:43 PM UTC 24 |
22536681410 ps |