| T1417 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/12.xbar_stress_all_with_error.244859353 |
|
|
Aug 29 01:24:51 PM UTC 24 |
Aug 29 01:24:57 PM UTC 24 |
5816955 ps |
| T828 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/12.xbar_access_same_device.1159586995 |
|
|
Aug 29 01:24:06 PM UTC 24 |
Aug 29 01:25:24 PM UTC 24 |
1670277440 ps |
| T1418 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/12.xbar_unmapped_addr.2820736499 |
|
|
Aug 29 01:24:28 PM UTC 24 |
Aug 29 01:25:34 PM UTC 24 |
1308393707 ps |
| T847 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/11.xbar_stress_all_with_reset_error.3266072904 |
|
|
Aug 29 01:23:20 PM UTC 24 |
Aug 29 01:25:41 PM UTC 24 |
2734925893 ps |
| T1419 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/13.xbar_smoke.2638312890 |
|
|
Aug 29 01:25:41 PM UTC 24 |
Aug 29 01:25:54 PM UTC 24 |
169483138 ps |
| T1420 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/13.xbar_smoke_zero_delays.2045637660 |
|
|
Aug 29 01:25:42 PM UTC 24 |
Aug 29 01:25:52 PM UTC 24 |
42184305 ps |
| T545 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/10.chip_csr_rw.73446062 |
|
|
Aug 29 01:21:02 PM UTC 24 |
Aug 29 01:26:00 PM UTC 24 |
4262344942 ps |
| T1421 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/12.xbar_error_random.52273315 |
|
|
Aug 29 01:24:24 PM UTC 24 |
Aug 29 01:26:12 PM UTC 24 |
2412040549 ps |
| T1422 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/7.chip_csr_rw.2597147250 |
|
|
Aug 29 01:14:23 PM UTC 24 |
Aug 29 01:26:27 PM UTC 24 |
5420826966 ps |
| T857 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/11.xbar_stress_all_with_rand_reset.3806072392 |
|
|
Aug 29 01:23:11 PM UTC 24 |
Aug 29 01:26:30 PM UTC 24 |
522469710 ps |
| T527 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/5.xbar_random_large_delays.2448360396 |
|
|
Aug 29 01:08:26 PM UTC 24 |
Aug 29 01:26:32 PM UTC 24 |
92681024548 ps |
| T1423 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/6.chip_csr_rw.494479040 |
|
|
Aug 29 01:12:30 PM UTC 24 |
Aug 29 01:26:41 PM UTC 24 |
6500845850 ps |
| T1424 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/13.xbar_random.404285136 |
|
|
Aug 29 01:26:11 PM UTC 24 |
Aug 29 01:26:44 PM UTC 24 |
739090556 ps |
| T800 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/8.xbar_stress_all_with_error.2540541043 |
|
|
Aug 29 01:15:43 PM UTC 24 |
Aug 29 01:26:44 PM UTC 24 |
18052208361 ps |
| T1425 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/11.xbar_stress_all_with_error.499737911 |
|
|
Aug 29 01:23:15 PM UTC 24 |
Aug 29 01:26:50 PM UTC 24 |
4974655380 ps |
| T859 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/12.xbar_stress_all_with_rand_reset.3646279716 |
|
|
Aug 29 01:24:51 PM UTC 24 |
Aug 29 01:26:52 PM UTC 24 |
233541815 ps |
| T543 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/5.chip_csr_mem_rw_with_rand_reset.2796395585 |
|
|
Aug 29 01:10:25 PM UTC 24 |
Aug 29 01:26:56 PM UTC 24 |
8922482568 ps |
| T469 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/10.xbar_stress_all_with_rand_reset.3998922273 |
|
|
Aug 29 01:20:36 PM UTC 24 |
Aug 29 01:27:00 PM UTC 24 |
3567470628 ps |
| T493 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/13.xbar_random_zero_delays.2572513965 |
|
|
Aug 29 01:26:15 PM UTC 24 |
Aug 29 01:27:02 PM UTC 24 |
469780801 ps |
| T815 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/9.xbar_access_same_device_slow_rsp.3366574460 |
|
|
Aug 29 01:17:30 PM UTC 24 |
Aug 29 01:27:12 PM UTC 24 |
32161814699 ps |
| T1426 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/13.xbar_same_source.2724683467 |
|
|
Aug 29 01:26:51 PM UTC 24 |
Aug 29 01:27:12 PM UTC 24 |
160524632 ps |
| T1427 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/13.xbar_smoke_large_delays.807865402 |
|
|
Aug 29 01:25:55 PM UTC 24 |
Aug 29 01:27:22 PM UTC 24 |
5764445197 ps |
| T599 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/11.chip_tl_errors.3802580878 |
|
|
Aug 29 01:21:24 PM UTC 24 |
Aug 29 01:27:40 PM UTC 24 |
4503875387 ps |
| T541 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/13.xbar_unmapped_addr.3431608790 |
|
|
Aug 29 01:27:03 PM UTC 24 |
Aug 29 01:27:45 PM UTC 24 |
743822800 ps |
| T1428 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/13.xbar_error_and_unmapped_addr.236631516 |
|
|
Aug 29 01:27:04 PM UTC 24 |
Aug 29 01:27:51 PM UTC 24 |
1124836605 ps |
| T1429 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/13.xbar_smoke_slow_rsp.3168553605 |
|
|
Aug 29 01:26:01 PM UTC 24 |
Aug 29 01:28:03 PM UTC 24 |
5131846979 ps |
| T1430 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/14.xbar_smoke.651019565 |
|
|
Aug 29 01:27:59 PM UTC 24 |
Aug 29 01:28:09 PM UTC 24 |
37602169 ps |
| T1431 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/14.xbar_smoke_zero_delays.1746215694 |
|
|
Aug 29 01:28:05 PM UTC 24 |
Aug 29 01:28:15 PM UTC 24 |
44831857 ps |
| T509 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/7.xbar_stress_all_with_rand_reset.1541470094 |
|
|
Aug 29 01:14:04 PM UTC 24 |
Aug 29 01:28:43 PM UTC 24 |
16290714056 ps |
| T590 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/13.chip_tl_errors.2568777503 |
|
|
Aug 29 01:25:16 PM UTC 24 |
Aug 29 01:28:47 PM UTC 24 |
3438353670 ps |
| T1432 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/9.chip_csr_rw.3142186785 |
|
|
Aug 29 01:18:37 PM UTC 24 |
Aug 29 01:28:50 PM UTC 24 |
5773053650 ps |
| T1433 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/13.xbar_error_random.1018226178 |
|
|
Aug 29 01:27:01 PM UTC 24 |
Aug 29 01:28:52 PM UTC 24 |
2410851434 ps |
| T593 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/12.chip_tl_errors.1327325317 |
|
|
Aug 29 01:23:29 PM UTC 24 |
Aug 29 01:28:54 PM UTC 24 |
4524118900 ps |
| T514 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/14.xbar_random.2660215847 |
|
|
Aug 29 01:28:30 PM UTC 24 |
Aug 29 01:29:07 PM UTC 24 |
250906334 ps |
| T820 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/13.xbar_access_same_device.1778373621 |
|
|
Aug 29 01:26:47 PM UTC 24 |
Aug 29 01:29:16 PM UTC 24 |
2453000880 ps |
| T524 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/14.xbar_random_zero_delays.1926591015 |
|
|
Aug 29 01:28:34 PM UTC 24 |
Aug 29 01:29:16 PM UTC 24 |
468421744 ps |
| T1434 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/8.chip_csr_mem_rw_with_rand_reset.820219964 |
|
|
Aug 29 01:16:15 PM UTC 24 |
Aug 29 01:29:24 PM UTC 24 |
9667434200 ps |
| T1435 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/14.xbar_smoke_large_delays.3238466469 |
|
|
Aug 29 01:28:11 PM UTC 24 |
Aug 29 01:29:38 PM UTC 24 |
6781069358 ps |
| T479 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/14.xbar_same_source.2321511324 |
|
|
Aug 29 01:29:14 PM UTC 24 |
Aug 29 01:29:45 PM UTC 24 |
637055186 ps |
| T876 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/13.xbar_stress_all_with_reset_error.795462351 |
|
|
Aug 29 01:27:20 PM UTC 24 |
Aug 29 01:29:55 PM UTC 24 |
296530403 ps |
| T1436 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/14.xbar_error_random.637917763 |
|
|
Aug 29 01:29:27 PM UTC 24 |
Aug 29 01:29:57 PM UTC 24 |
207109019 ps |
| T1437 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/14.xbar_stress_all_with_error.2057002596 |
|
|
Aug 29 01:30:06 PM UTC 24 |
Aug 29 01:30:15 PM UTC 24 |
17326711 ps |
| T1438 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/14.xbar_unmapped_addr.2112654091 |
|
|
Aug 29 01:29:37 PM UTC 24 |
Aug 29 01:30:15 PM UTC 24 |
721197217 ps |
| T832 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/14.xbar_access_same_device.563839325 |
|
|
Aug 29 01:29:10 PM UTC 24 |
Aug 29 01:30:18 PM UTC 24 |
454662991 ps |
| T1439 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/14.xbar_error_and_unmapped_addr.788342552 |
|
|
Aug 29 01:29:37 PM UTC 24 |
Aug 29 01:30:35 PM UTC 24 |
1143817291 ps |
| T1440 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/14.xbar_smoke_slow_rsp.1678918521 |
|
|
Aug 29 01:28:22 PM UTC 24 |
Aug 29 01:30:37 PM UTC 24 |
5756582361 ps |
| T1441 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/15.xbar_smoke_zero_delays.2958521220 |
|
|
Aug 29 01:30:57 PM UTC 24 |
Aug 29 01:31:06 PM UTC 24 |
47852062 ps |
| T1442 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/15.xbar_smoke.1254054987 |
|
|
Aug 29 01:30:56 PM UTC 24 |
Aug 29 01:31:09 PM UTC 24 |
172837018 ps |
| T843 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/12.xbar_stress_all_with_reset_error.1572376618 |
|
|
Aug 29 01:25:03 PM UTC 24 |
Aug 29 01:31:12 PM UTC 24 |
5297231328 ps |
| T583 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/14.chip_tl_errors.2791112633 |
|
|
Aug 29 01:27:41 PM UTC 24 |
Aug 29 01:31:23 PM UTC 24 |
3557403637 ps |
| T610 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/10.xbar_stress_all_with_error.4212507306 |
|
|
Aug 29 01:20:41 PM UTC 24 |
Aug 29 01:31:23 PM UTC 24 |
16932746602 ps |
| T505 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/12.xbar_stress_all.46884848 |
|
|
Aug 29 01:24:32 PM UTC 24 |
Aug 29 01:31:26 PM UTC 24 |
3559577544 ps |
| T1443 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/15.xbar_random_zero_delays.3737140573 |
|
|
Aug 29 01:31:43 PM UTC 24 |
Aug 29 01:31:53 PM UTC 24 |
39914258 ps |
| T881 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/14.xbar_stress_all_with_reset_error.1200048627 |
|
|
Aug 29 01:30:16 PM UTC 24 |
Aug 29 01:31:58 PM UTC 24 |
507168349 ps |
| T1444 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/15.xbar_random.3196952342 |
|
|
Aug 29 01:31:31 PM UTC 24 |
Aug 29 01:32:01 PM UTC 24 |
224509762 ps |
| T625 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/8.xbar_random_slow_rsp.1104550900 |
|
|
Aug 29 01:15:06 PM UTC 24 |
Aug 29 01:32:16 PM UTC 24 |
58694217173 ps |
| T1445 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/13.chip_csr_rw.3543028413 |
|
|
Aug 29 01:27:22 PM UTC 24 |
Aug 29 01:32:27 PM UTC 24 |
4197177910 ps |
| T1446 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/15.xbar_same_source.3756217480 |
|
|
Aug 29 01:32:18 PM UTC 24 |
Aug 29 01:32:29 PM UTC 24 |
137795796 ps |
| T1447 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/15.xbar_error_random.4267692968 |
|
|
Aug 29 01:32:22 PM UTC 24 |
Aug 29 01:32:30 PM UTC 24 |
89136347 ps |
| T483 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/15.xbar_random_slow_rsp.1589200340 |
|
|
Aug 29 01:31:46 PM UTC 24 |
Aug 29 01:32:38 PM UTC 24 |
3055994044 ps |
| T1448 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/15.xbar_smoke_large_delays.3093616935 |
|
|
Aug 29 01:31:25 PM UTC 24 |
Aug 29 01:32:51 PM UTC 24 |
7380150400 ps |
| T834 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/13.xbar_stress_all_with_error.3280561579 |
|
|
Aug 29 01:27:17 PM UTC 24 |
Aug 29 01:33:02 PM UTC 24 |
7640326341 ps |
| T1449 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/15.xbar_unmapped_addr.580219790 |
|
|
Aug 29 01:32:22 PM UTC 24 |
Aug 29 01:33:02 PM UTC 24 |
275630306 ps |
| T822 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/14.xbar_access_same_device_slow_rsp.632009899 |
|
|
Aug 29 01:29:12 PM UTC 24 |
Aug 29 01:33:09 PM UTC 24 |
11378643755 ps |
| T1450 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/15.xbar_error_and_unmapped_addr.2566918320 |
|
|
Aug 29 01:32:37 PM UTC 24 |
Aug 29 01:33:14 PM UTC 24 |
814325111 ps |
| T1451 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/15.xbar_smoke_slow_rsp.3997548569 |
|
|
Aug 29 01:31:29 PM UTC 24 |
Aug 29 01:33:15 PM UTC 24 |
5163488510 ps |
| T818 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/13.xbar_stress_all.4109722574 |
|
|
Aug 29 01:27:09 PM UTC 24 |
Aug 29 01:33:36 PM UTC 24 |
9534105633 ps |
| T1452 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/9.chip_csr_mem_rw_with_rand_reset.3396064650 |
|
|
Aug 29 01:18:39 PM UTC 24 |
Aug 29 01:33:46 PM UTC 24 |
9618792664 ps |
| T1453 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/16.xbar_smoke_zero_delays.3795235662 |
|
|
Aug 29 01:33:36 PM UTC 24 |
Aug 29 01:33:46 PM UTC 24 |
51531874 ps |
| T1454 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/16.xbar_smoke.4095237779 |
|
|
Aug 29 01:33:34 PM UTC 24 |
Aug 29 01:33:48 PM UTC 24 |
224993050 ps |
| T494 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/14.xbar_stress_all.3309333036 |
|
|
Aug 29 01:29:45 PM UTC 24 |
Aug 29 01:33:51 PM UTC 24 |
4155757937 ps |
| T1455 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/11.chip_csr_rw.2659314519 |
|
|
Aug 29 01:23:21 PM UTC 24 |
Aug 29 01:33:51 PM UTC 24 |
5334307337 ps |
| T823 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/15.xbar_access_same_device.2365639317 |
|
|
Aug 29 01:32:14 PM UTC 24 |
Aug 29 01:33:53 PM UTC 24 |
1874076654 ps |
| T1456 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/12.chip_csr_mem_rw_with_rand_reset.4240482903 |
|
|
Aug 29 01:25:10 PM UTC 24 |
Aug 29 01:34:11 PM UTC 24 |
7915726031 ps |
| T1457 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/12.chip_csr_rw.3187048880 |
|
|
Aug 29 01:25:10 PM UTC 24 |
Aug 29 01:34:26 PM UTC 24 |
5651602736 ps |
| T1458 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/13.chip_csr_mem_rw_with_rand_reset.1161593198 |
|
|
Aug 29 01:27:32 PM UTC 24 |
Aug 29 01:34:26 PM UTC 24 |
7030346505 ps |
| T1459 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/10.xbar_random_slow_rsp.1244677810 |
|
|
Aug 29 01:19:25 PM UTC 24 |
Aug 29 01:34:44 PM UTC 24 |
50527515416 ps |
| T1460 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/16.xbar_random_zero_delays.2914379459 |
|
|
Aug 29 01:34:08 PM UTC 24 |
Aug 29 01:34:50 PM UTC 24 |
318701384 ps |
| T798 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/16.xbar_access_same_device.563229161 |
|
|
Aug 29 01:34:14 PM UTC 24 |
Aug 29 01:34:59 PM UTC 24 |
775647242 ps |
| T1461 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/16.xbar_smoke_large_delays.479381067 |
|
|
Aug 29 01:33:56 PM UTC 24 |
Aug 29 01:35:18 PM UTC 24 |
6611794670 ps |
| T1462 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/16.xbar_error_random.2262022308 |
|
|
Aug 29 01:34:47 PM UTC 24 |
Aug 29 01:35:20 PM UTC 24 |
638316046 ps |
| T500 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/16.xbar_same_source.1473203596 |
|
|
Aug 29 01:34:47 PM UTC 24 |
Aug 29 01:35:26 PM UTC 24 |
383111861 ps |
| T877 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/15.xbar_stress_all_with_reset_error.3104873353 |
|
|
Aug 29 01:32:58 PM UTC 24 |
Aug 29 01:35:28 PM UTC 24 |
1714602004 ps |
| T1463 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/11.chip_csr_mem_rw_with_rand_reset.2720350138 |
|
|
Aug 29 01:23:25 PM UTC 24 |
Aug 29 01:35:33 PM UTC 24 |
7724316436 ps |
| T1464 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/16.xbar_random.3388194283 |
|
|
Aug 29 01:34:07 PM UTC 24 |
Aug 29 01:35:44 PM UTC 24 |
1803405472 ps |
| T1465 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/16.xbar_error_and_unmapped_addr.2353060818 |
|
|
Aug 29 01:35:10 PM UTC 24 |
Aug 29 01:35:53 PM UTC 24 |
905745827 ps |
| T1466 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/16.xbar_smoke_slow_rsp.1901662211 |
|
|
Aug 29 01:34:07 PM UTC 24 |
Aug 29 01:35:55 PM UTC 24 |
4569949338 ps |
| T1467 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/16.xbar_unmapped_addr.3120798420 |
|
|
Aug 29 01:35:04 PM UTC 24 |
Aug 29 01:36:18 PM UTC 24 |
1193686072 ps |
| T1468 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/17.xbar_smoke.1617880005 |
|
|
Aug 29 01:36:15 PM UTC 24 |
Aug 29 01:36:30 PM UTC 24 |
224060442 ps |
| T587 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/16.chip_tl_errors.2735150301 |
|
|
Aug 29 01:33:29 PM UTC 24 |
Aug 29 01:36:41 PM UTC 24 |
3416371995 ps |
| T473 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/3.xbar_access_same_device_slow_rsp.2727548900 |
|
|
Aug 29 01:03:49 PM UTC 24 |
Aug 29 01:36:44 PM UTC 24 |
111872351884 ps |
| T1469 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/17.xbar_smoke_zero_delays.3625724095 |
|
|
Aug 29 01:36:38 PM UTC 24 |
Aug 29 01:36:49 PM UTC 24 |
41103031 ps |
| T602 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/15.xbar_stress_all_with_error.398488303 |
|
|
Aug 29 01:32:51 PM UTC 24 |
Aug 29 01:37:04 PM UTC 24 |
3037810001 ps |
| T842 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/10.xbar_access_same_device_slow_rsp.1523478934 |
|
|
Aug 29 01:19:44 PM UTC 24 |
Aug 29 01:37:04 PM UTC 24 |
58522362010 ps |
| T466 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/16.xbar_stress_all.4189357570 |
|
|
Aug 29 01:35:19 PM UTC 24 |
Aug 29 01:37:11 PM UTC 24 |
1187396872 ps |
| T1470 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/17.xbar_access_same_device.1493885566 |
|
|
Aug 29 01:37:31 PM UTC 24 |
Aug 29 01:37:45 PM UTC 24 |
100660274 ps |
| T1471 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/15.chip_csr_rw.279532663 |
|
|
Aug 29 01:33:11 PM UTC 24 |
Aug 29 01:37:48 PM UTC 24 |
3975956508 ps |
| T445 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/10.chip_csr_mem_rw_with_rand_reset.2871434574 |
|
|
Aug 29 01:21:11 PM UTC 24 |
Aug 29 01:37:49 PM UTC 24 |
11130770863 ps |
| T1472 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/17.xbar_random_zero_delays.1142386767 |
|
|
Aug 29 01:37:10 PM UTC 24 |
Aug 29 01:37:52 PM UTC 24 |
441949713 ps |
| T1473 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/16.xbar_stress_all_with_error.3408323233 |
|
|
Aug 29 01:35:40 PM UTC 24 |
Aug 29 01:37:56 PM UTC 24 |
3315883604 ps |
| T540 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/15.xbar_stress_all_with_rand_reset.2050223635 |
|
|
Aug 29 01:32:50 PM UTC 24 |
Aug 29 01:37:59 PM UTC 24 |
768203168 ps |
| T1474 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/17.xbar_random.1138480783 |
|
|
Aug 29 01:37:04 PM UTC 24 |
Aug 29 01:38:06 PM UTC 24 |
1202872157 ps |
| T1475 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/14.xbar_random_large_delays.2740793247 |
|
|
Aug 29 01:29:04 PM UTC 24 |
Aug 29 01:38:08 PM UTC 24 |
49363407499 ps |
| T472 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/15.xbar_stress_all.633156160 |
|
|
Aug 29 01:32:47 PM UTC 24 |
Aug 29 01:38:27 PM UTC 24 |
6909887581 ps |
| T490 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/2.xbar_access_same_device_slow_rsp.1310316766 |
|
|
Aug 29 01:02:10 PM UTC 24 |
Aug 29 01:38:33 PM UTC 24 |
117225658579 ps |
| T1476 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/17.xbar_random_slow_rsp.3509394895 |
|
|
Aug 29 01:37:23 PM UTC 24 |
Aug 29 01:38:34 PM UTC 24 |
2887967434 ps |
| T522 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/17.xbar_unmapped_addr.4033771455 |
|
|
Aug 29 01:38:12 PM UTC 24 |
Aug 29 01:38:42 PM UTC 24 |
493796575 ps |
| T499 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/11.xbar_access_same_device_slow_rsp.2137368056 |
|
|
Aug 29 01:21:57 PM UTC 24 |
Aug 29 01:38:48 PM UTC 24 |
61277364081 ps |
| T1477 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/17.xbar_error_random.1335994679 |
|
|
Aug 29 01:38:09 PM UTC 24 |
Aug 29 01:38:50 PM UTC 24 |
382348974 ps |
| T1478 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/17.xbar_same_source.3807915718 |
|
|
Aug 29 01:38:05 PM UTC 24 |
Aug 29 01:38:52 PM UTC 24 |
1656500958 ps |
| T1479 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/14.chip_csr_mem_rw_with_rand_reset.1149719292 |
|
|
Aug 29 01:30:35 PM UTC 24 |
Aug 29 01:38:55 PM UTC 24 |
5596446014 ps |
| T510 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/14.xbar_stress_all_with_rand_reset.2215016440 |
|
|
Aug 29 01:29:59 PM UTC 24 |
Aug 29 01:38:56 PM UTC 24 |
5485022057 ps |
| T1480 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/17.xbar_smoke_large_delays.3450755373 |
|
|
Aug 29 01:36:50 PM UTC 24 |
Aug 29 01:38:58 PM UTC 24 |
8710394833 ps |
| T1481 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/17.xbar_smoke_slow_rsp.3642182614 |
|
|
Aug 29 01:37:02 PM UTC 24 |
Aug 29 01:39:02 PM UTC 24 |
5229573051 ps |
| T1482 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/17.xbar_error_and_unmapped_addr.1500599747 |
|
|
Aug 29 01:38:15 PM UTC 24 |
Aug 29 01:39:05 PM UTC 24 |
317348808 ps |
| T609 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/13.xbar_random_slow_rsp.2228894348 |
|
|
Aug 29 01:26:32 PM UTC 24 |
Aug 29 01:39:13 PM UTC 24 |
43517885869 ps |
| T1483 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/18.xbar_smoke_zero_delays.2765715381 |
|
|
Aug 29 01:39:12 PM UTC 24 |
Aug 29 01:39:22 PM UTC 24 |
47144531 ps |
| T1484 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/18.xbar_smoke.1252797089 |
|
|
Aug 29 01:39:11 PM UTC 24 |
Aug 29 01:39:22 PM UTC 24 |
143699050 ps |
| T1485 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/18.xbar_random_zero_delays.344936229 |
|
|
Aug 29 01:39:22 PM UTC 24 |
Aug 29 01:39:35 PM UTC 24 |
60283072 ps |
| T1486 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/15.chip_csr_mem_rw_with_rand_reset.203856461 |
|
|
Aug 29 01:33:23 PM UTC 24 |
Aug 29 01:39:41 PM UTC 24 |
7109692224 ps |
| T1487 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/10.xbar_random_large_delays.371071932 |
|
|
Aug 29 01:19:23 PM UTC 24 |
Aug 29 01:39:49 PM UTC 24 |
97697769927 ps |
| T591 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/17.chip_tl_errors.2116056144 |
|
|
Aug 29 01:36:14 PM UTC 24 |
Aug 29 01:40:06 PM UTC 24 |
3053224840 ps |
| T588 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/15.chip_tl_errors.3371200209 |
|
|
Aug 29 01:30:38 PM UTC 24 |
Aug 29 01:40:08 PM UTC 24 |
4523066248 ps |
| T1488 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/18.xbar_error_random.3457398581 |
|
|
Aug 29 01:40:02 PM UTC 24 |
Aug 29 01:40:13 PM UTC 24 |
115726720 ps |
| T1489 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/17.xbar_stress_all_with_rand_reset.50387776 |
|
|
Aug 29 01:38:26 PM UTC 24 |
Aug 29 01:40:19 PM UTC 24 |
202435599 ps |
| T853 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/17.xbar_stress_all.697916609 |
|
|
Aug 29 01:38:17 PM UTC 24 |
Aug 29 01:40:30 PM UTC 24 |
3133180820 ps |
| T1490 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/18.xbar_same_source.3234533721 |
|
|
Aug 29 01:39:55 PM UTC 24 |
Aug 29 01:40:34 PM UTC 24 |
827661708 ps |
| T1491 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/18.xbar_random.1157267208 |
|
|
Aug 29 01:39:17 PM UTC 24 |
Aug 29 01:40:36 PM UTC 24 |
2350300865 ps |
| T1492 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/18.xbar_smoke_large_delays.2435323728 |
|
|
Aug 29 01:39:14 PM UTC 24 |
Aug 29 01:40:47 PM UTC 24 |
7665874454 ps |
| T1493 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/18.xbar_unmapped_addr.3317650338 |
|
|
Aug 29 01:40:10 PM UTC 24 |
Aug 29 01:40:56 PM UTC 24 |
1030973867 ps |
| T1494 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/18.xbar_smoke_slow_rsp.2564681791 |
|
|
Aug 29 01:39:16 PM UTC 24 |
Aug 29 01:40:58 PM UTC 24 |
4382429028 ps |
| T1495 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/18.xbar_error_and_unmapped_addr.2294767102 |
|
|
Aug 29 01:40:26 PM UTC 24 |
Aug 29 01:40:59 PM UTC 24 |
760314886 ps |
| T1496 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/14.chip_csr_rw.841280713 |
|
|
Aug 29 01:30:18 PM UTC 24 |
Aug 29 01:41:05 PM UTC 24 |
5331749624 ps |
| T829 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/8.xbar_access_same_device_slow_rsp.4139511917 |
|
|
Aug 29 01:15:12 PM UTC 24 |
Aug 29 01:41:16 PM UTC 24 |
85022841726 ps |
| T819 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/18.xbar_access_same_device.20908084 |
|
|
Aug 29 01:39:42 PM UTC 24 |
Aug 29 01:41:22 PM UTC 24 |
1692654460 ps |
| T1497 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/19.xbar_smoke.2871817653 |
|
|
Aug 29 01:41:18 PM UTC 24 |
Aug 29 01:41:27 PM UTC 24 |
208924030 ps |
| T1498 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/19.xbar_smoke_zero_delays.2820346384 |
|
|
Aug 29 01:41:19 PM UTC 24 |
Aug 29 01:41:29 PM UTC 24 |
43395716 ps |
| T830 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/12.xbar_access_same_device_slow_rsp.2252651704 |
|
|
Aug 29 01:24:07 PM UTC 24 |
Aug 29 01:41:56 PM UTC 24 |
75084450778 ps |
| T1499 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/19.xbar_random_zero_delays.1361016843 |
|
|
Aug 29 01:41:47 PM UTC 24 |
Aug 29 01:42:11 PM UTC 24 |
184935000 ps |
| T480 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/16.xbar_random_slow_rsp.4016622991 |
|
|
Aug 29 01:34:12 PM UTC 24 |
Aug 29 01:42:17 PM UTC 24 |
30185352258 ps |
| T883 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/18.xbar_stress_all_with_reset_error.205754312 |
|
|
Aug 29 01:40:49 PM UTC 24 |
Aug 29 01:42:37 PM UTC 24 |
205336664 ps |
| T1500 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/19.xbar_smoke_slow_rsp.3746564430 |
|
|
Aug 29 01:41:36 PM UTC 24 |
Aug 29 01:42:38 PM UTC 24 |
3878580740 ps |
| T1501 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/19.xbar_random.3275915810 |
|
|
Aug 29 01:41:43 PM UTC 24 |
Aug 29 01:42:43 PM UTC 24 |
550327724 ps |
| T394 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/0.chip_same_csr_outstanding.3152356241 |
|
|
Aug 29 01:00:23 PM UTC 24 |
Aug 29 01:42:50 PM UTC 24 |
18040656840 ps |
| T1502 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/19.xbar_smoke_large_delays.2299975798 |
|
|
Aug 29 01:41:25 PM UTC 24 |
Aug 29 01:43:02 PM UTC 24 |
6944481657 ps |
| T1503 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/18.xbar_random_large_delays.3190776398 |
|
|
Aug 29 01:39:25 PM UTC 24 |
Aug 29 01:43:10 PM UTC 24 |
19684320336 ps |
| T648 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/16.xbar_stress_all_with_reset_error.4150132794 |
|
|
Aug 29 01:35:46 PM UTC 24 |
Aug 29 01:43:14 PM UTC 24 |
2988215216 ps |
| T488 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/19.xbar_unmapped_addr.3894589349 |
|
|
Aug 29 01:43:04 PM UTC 24 |
Aug 29 01:43:19 PM UTC 24 |
56889760 ps |
| T1504 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/19.xbar_same_source.2415744852 |
|
|
Aug 29 01:42:58 PM UTC 24 |
Aug 29 01:43:26 PM UTC 24 |
224490518 ps |
| T1505 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/19.xbar_error_random.2440039970 |
|
|
Aug 29 01:42:59 PM UTC 24 |
Aug 29 01:43:26 PM UTC 24 |
542310585 ps |
| T511 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/16.xbar_stress_all_with_rand_reset.4251264432 |
|
|
Aug 29 01:35:38 PM UTC 24 |
Aug 29 01:43:39 PM UTC 24 |
3163992001 ps |
| T806 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/15.xbar_access_same_device_slow_rsp.666686439 |
|
|
Aug 29 01:32:14 PM UTC 24 |
Aug 29 01:43:43 PM UTC 24 |
46181131620 ps |
| T495 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/13.xbar_stress_all_with_rand_reset.1828043398 |
|
|
Aug 29 01:27:12 PM UTC 24 |
Aug 29 01:43:48 PM UTC 24 |
5969394678 ps |
| T1506 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/17.chip_csr_rw.3174236321 |
|
|
Aug 29 01:38:53 PM UTC 24 |
Aug 29 01:43:53 PM UTC 24 |
3868106920 ps |
| T594 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/18.chip_tl_errors.2603939951 |
|
|
Aug 29 01:39:08 PM UTC 24 |
Aug 29 01:43:54 PM UTC 24 |
2781188676 ps |
| T515 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/19.xbar_access_same_device.2700577382 |
|
|
Aug 29 01:42:31 PM UTC 24 |
Aug 29 01:44:12 PM UTC 24 |
1123110842 ps |
| T1507 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/19.xbar_error_and_unmapped_addr.789357347 |
|
|
Aug 29 01:43:10 PM UTC 24 |
Aug 29 01:44:12 PM UTC 24 |
1049954579 ps |
| T1508 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/20.xbar_smoke.3994614490 |
|
|
Aug 29 01:44:03 PM UTC 24 |
Aug 29 01:44:18 PM UTC 24 |
216931584 ps |
| T1509 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/20.xbar_smoke_zero_delays.966718023 |
|
|
Aug 29 01:44:08 PM UTC 24 |
Aug 29 01:44:19 PM UTC 24 |
54274499 ps |
| T1510 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/16.chip_csr_mem_rw_with_rand_reset.2209141417 |
|
|
Aug 29 01:35:54 PM UTC 24 |
Aug 29 01:44:19 PM UTC 24 |
6770086933 ps |
| T477 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/19.xbar_stress_all.1412117897 |
|
|
Aug 29 01:43:21 PM UTC 24 |
Aug 29 01:44:28 PM UTC 24 |
627106910 ps |
| T824 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/18.xbar_stress_all_with_error.3086478283 |
|
|
Aug 29 01:40:39 PM UTC 24 |
Aug 29 01:44:30 PM UTC 24 |
5410160301 ps |
| T496 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/12.xbar_random_slow_rsp.1520307648 |
|
|
Aug 29 01:24:04 PM UTC 24 |
Aug 29 01:44:33 PM UTC 24 |
64062978828 ps |
| T1511 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/20.xbar_random_zero_delays.156921409 |
|
|
Aug 29 01:44:32 PM UTC 24 |
Aug 29 01:44:46 PM UTC 24 |
67026787 ps |
| T1512 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/20.xbar_random.3376396777 |
|
|
Aug 29 01:44:33 PM UTC 24 |
Aug 29 01:44:49 PM UTC 24 |
182739106 ps |
| T1513 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/20.xbar_error_random.4148195327 |
|
|
Aug 29 01:44:53 PM UTC 24 |
Aug 29 01:45:17 PM UTC 24 |
430041004 ps |
| T1514 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/15.xbar_random_large_delays.3708289708 |
|
|
Aug 29 01:31:43 PM UTC 24 |
Aug 29 01:45:22 PM UTC 24 |
59926591026 ps |
| T1515 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/20.xbar_unmapped_addr.306783181 |
|
|
Aug 29 01:45:07 PM UTC 24 |
Aug 29 01:45:26 PM UTC 24 |
244334291 ps |
| T1516 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/17.xbar_random_large_delays.308760575 |
|
|
Aug 29 01:37:22 PM UTC 24 |
Aug 29 01:45:26 PM UTC 24 |
47921328526 ps |
| T1517 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/12.xbar_random_large_delays.95749537 |
|
|
Aug 29 01:23:49 PM UTC 24 |
Aug 29 01:45:30 PM UTC 24 |
110546472529 ps |
| T1518 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/16.chip_csr_rw.2131201241 |
|
|
Aug 29 01:35:48 PM UTC 24 |
Aug 29 01:45:41 PM UTC 24 |
6216285092 ps |
| T1519 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/20.xbar_smoke_large_delays.1923422843 |
|
|
Aug 29 01:44:14 PM UTC 24 |
Aug 29 01:45:45 PM UTC 24 |
5911493283 ps |
| T864 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/18.xbar_stress_all_with_rand_reset.2984341990 |
|
|
Aug 29 01:40:33 PM UTC 24 |
Aug 29 01:46:01 PM UTC 24 |
712365654 ps |
| T506 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/18.xbar_stress_all.4120442032 |
|
|
Aug 29 01:40:28 PM UTC 24 |
Aug 29 01:46:01 PM UTC 24 |
7926412105 ps |
| T1520 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/20.xbar_random_large_delays.2747362111 |
|
|
Aug 29 01:44:38 PM UTC 24 |
Aug 29 01:46:09 PM UTC 24 |
5583155370 ps |
| T1521 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/19.xbar_stress_all_with_error.1138549578 |
|
|
Aug 29 01:43:34 PM UTC 24 |
Aug 29 01:46:09 PM UTC 24 |
1608348960 ps |
| T1522 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/21.xbar_smoke_zero_delays.1450767724 |
|
|
Aug 29 01:46:03 PM UTC 24 |
Aug 29 01:46:13 PM UTC 24 |
50927574 ps |
| T1523 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/21.xbar_smoke.1654820858 |
|
|
Aug 29 01:46:02 PM UTC 24 |
Aug 29 01:46:13 PM UTC 24 |
139664734 ps |
| T1524 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/20.xbar_stress_all_with_reset_error.1565651344 |
|
|
Aug 29 01:45:46 PM UTC 24 |
Aug 29 01:46:15 PM UTC 24 |
144159704 ps |
| T1525 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/20.xbar_error_and_unmapped_addr.3299158010 |
|
|
Aug 29 01:45:09 PM UTC 24 |
Aug 29 01:46:16 PM UTC 24 |
1118856885 ps |
| T1526 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/20.xbar_same_source.788610935 |
|
|
Aug 29 01:44:50 PM UTC 24 |
Aug 29 01:46:16 PM UTC 24 |
1941610326 ps |
| T868 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/17.xbar_stress_all_with_reset_error.2009072347 |
|
|
Aug 29 01:38:47 PM UTC 24 |
Aug 29 01:46:18 PM UTC 24 |
8033561960 ps |
| T1527 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/20.xbar_smoke_slow_rsp.1122098258 |
|
|
Aug 29 01:44:14 PM UTC 24 |
Aug 29 01:46:18 PM UTC 24 |
5970693326 ps |
| T405 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/8.chip_same_csr_outstanding.294382403 |
|
|
Aug 29 01:14:26 PM UTC 24 |
Aug 29 01:46:44 PM UTC 24 |
16863719416 ps |
| T1528 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/21.xbar_access_same_device.3604123501 |
|
|
Aug 29 01:46:36 PM UTC 24 |
Aug 29 01:46:52 PM UTC 24 |
94400455 ps |
| T1529 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/13.xbar_random_large_delays.617388753 |
|
|
Aug 29 01:26:20 PM UTC 24 |
Aug 29 01:47:00 PM UTC 24 |
88953107721 ps |
| T1530 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/21.xbar_random.26263110 |
|
|
Aug 29 01:46:29 PM UTC 24 |
Aug 29 01:47:04 PM UTC 24 |
364875333 ps |
| T1531 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/21.xbar_unmapped_addr.998325214 |
|
|
Aug 29 01:46:39 PM UTC 24 |
Aug 29 01:47:07 PM UTC 24 |
152437520 ps |
| T840 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/20.xbar_access_same_device.1197100853 |
|
|
Aug 29 01:44:40 PM UTC 24 |
Aug 29 01:47:17 PM UTC 24 |
2951371705 ps |
| T865 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/19.xbar_stress_all_with_rand_reset.3697265093 |
|
|
Aug 29 01:43:29 PM UTC 24 |
Aug 29 01:47:19 PM UTC 24 |
340629276 ps |
| T1532 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/21.xbar_error_random.3663616405 |
|
|
Aug 29 01:46:38 PM UTC 24 |
Aug 29 01:47:34 PM UTC 24 |
1248865951 ps |
| T1533 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/21.xbar_smoke_slow_rsp.3577198480 |
|
|
Aug 29 01:46:21 PM UTC 24 |
Aug 29 01:47:36 PM UTC 24 |
5179333827 ps |
| T1534 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/20.xbar_stress_all_with_rand_reset.2336767190 |
|
|
Aug 29 01:45:43 PM UTC 24 |
Aug 29 01:47:39 PM UTC 24 |
125645820 ps |
| T1535 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/21.xbar_random_zero_delays.2212764510 |
|
|
Aug 29 01:46:29 PM UTC 24 |
Aug 29 01:47:40 PM UTC 24 |
583089808 ps |
| T1536 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/21.xbar_same_source.1906998756 |
|
|
Aug 29 01:46:36 PM UTC 24 |
Aug 29 01:47:46 PM UTC 24 |
1728885499 ps |
| T1537 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/22.xbar_smoke.1089433318 |
|
|
Aug 29 01:47:39 PM UTC 24 |
Aug 29 01:47:49 PM UTC 24 |
44835844 ps |
| T1538 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/18.chip_csr_rw.1794201757 |
|
|
Aug 29 01:40:54 PM UTC 24 |
Aug 29 01:47:49 PM UTC 24 |
4120060505 ps |
| T1539 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/17.xbar_stress_all_with_error.762713869 |
|
|
Aug 29 01:38:27 PM UTC 24 |
Aug 29 01:47:59 PM UTC 24 |
15132159140 ps |
| T1540 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/22.xbar_smoke_zero_delays.2805458590 |
|
|
Aug 29 01:47:54 PM UTC 24 |
Aug 29 01:48:04 PM UTC 24 |
45126566 ps |
| T1541 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/21.xbar_error_and_unmapped_addr.400267314 |
|
|
Aug 29 01:47:04 PM UTC 24 |
Aug 29 01:48:09 PM UTC 24 |
1295015585 ps |
| T1542 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/17.chip_csr_mem_rw_with_rand_reset.3644330359 |
|
|
Aug 29 01:38:54 PM UTC 24 |
Aug 29 01:48:15 PM UTC 24 |
7294907344 ps |
| T627 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/19.chip_tl_errors.3342938264 |
|
|
Aug 29 01:41:17 PM UTC 24 |
Aug 29 01:48:19 PM UTC 24 |
4567132332 ps |
| T1543 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/21.xbar_access_same_device_slow_rsp.2609641579 |
|
|
Aug 29 01:46:37 PM UTC 24 |
Aug 29 01:48:23 PM UTC 24 |
4069168097 ps |
| T1544 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/22.xbar_random.1897778439 |
|
|
Aug 29 01:48:00 PM UTC 24 |
Aug 29 01:48:32 PM UTC 24 |
234557508 ps |
| T1545 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/21.xbar_smoke_large_delays.3471883890 |
|
|
Aug 29 01:46:22 PM UTC 24 |
Aug 29 01:48:42 PM UTC 24 |
10681695223 ps |
| T1546 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/1.chip_csr_bit_bash.3242395757 |
|
|
Aug 29 01:00:29 PM UTC 24 |
Aug 29 01:48:43 PM UTC 24 |
29739854761 ps |
| T1547 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/19.chip_csr_rw.3427226185 |
|
|
Aug 29 01:43:46 PM UTC 24 |
Aug 29 01:48:50 PM UTC 24 |
4136883370 ps |
| T1548 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/22.xbar_random_zero_delays.1558463068 |
|
|
Aug 29 01:48:07 PM UTC 24 |
Aug 29 01:48:54 PM UTC 24 |
341797254 ps |
| T1549 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/22.xbar_unmapped_addr.4136834861 |
|
|
Aug 29 01:48:41 PM UTC 24 |
Aug 29 01:48:57 PM UTC 24 |
60061392 ps |
| T867 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/19.xbar_stress_all_with_reset_error.2390069464 |
|
|
Aug 29 01:43:38 PM UTC 24 |
Aug 29 01:48:58 PM UTC 24 |
2516234049 ps |
| T1550 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/22.xbar_same_source.1839499979 |
|
|
Aug 29 01:48:29 PM UTC 24 |
Aug 29 01:49:00 PM UTC 24 |
705547146 ps |
| T807 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/1.xbar_access_same_device_slow_rsp.480210053 |
|
|
Aug 29 01:00:57 PM UTC 24 |
Aug 29 01:49:00 PM UTC 24 |
166695180689 ps |
| T1551 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/22.xbar_error_random.1201985996 |
|
|
Aug 29 01:48:34 PM UTC 24 |
Aug 29 01:49:06 PM UTC 24 |
250697998 ps |
| T1552 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/21.xbar_stress_all.2253558798 |
|
|
Aug 29 01:47:12 PM UTC 24 |
Aug 29 01:49:15 PM UTC 24 |
2491317839 ps |
| T1553 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/22.xbar_smoke_large_delays.1879205700 |
|
|
Aug 29 01:47:56 PM UTC 24 |
Aug 29 01:49:16 PM UTC 24 |
5929220652 ps |
| T478 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/22.xbar_access_same_device.3812775809 |
|
|
Aug 29 01:48:20 PM UTC 24 |
Aug 29 01:49:17 PM UTC 24 |
281121956 ps |
| T1554 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/22.xbar_error_and_unmapped_addr.591126626 |
|
|
Aug 29 01:48:43 PM UTC 24 |
Aug 29 01:49:19 PM UTC 24 |
326644497 ps |
| T655 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/20.chip_tl_errors.1913323216 |
|
|
Aug 29 01:43:59 PM UTC 24 |
Aug 29 01:49:26 PM UTC 24 |
3957083920 ps |
| T1555 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/23.xbar_smoke_zero_delays.1129946858 |
|
|
Aug 29 01:49:17 PM UTC 24 |
Aug 29 01:49:28 PM UTC 24 |
56434728 ps |
| T1556 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/23.xbar_smoke.3559659166 |
|
|
Aug 29 01:49:14 PM UTC 24 |
Aug 29 01:49:29 PM UTC 24 |
232505267 ps |
| T1557 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/21.xbar_stress_all_with_rand_reset.3713378427 |
|
|
Aug 29 01:47:19 PM UTC 24 |
Aug 29 01:49:33 PM UTC 24 |
758255629 ps |
| T491 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/22.xbar_smoke_slow_rsp.3376952459 |
|
|
Aug 29 01:48:00 PM UTC 24 |
Aug 29 01:49:33 PM UTC 24 |
5696326813 ps |
| T1558 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/23.xbar_random.4280220540 |
|
|
Aug 29 01:49:20 PM UTC 24 |
Aug 29 01:49:49 PM UTC 24 |
511738581 ps |
| T516 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/14.xbar_random_slow_rsp.3335791796 |
|
|
Aug 29 01:29:06 PM UTC 24 |
Aug 29 01:50:15 PM UTC 24 |
65203601315 ps |
| T1559 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/23.xbar_error_and_unmapped_addr.1759354857 |
|
|
Aug 29 01:49:52 PM UTC 24 |
Aug 29 01:50:24 PM UTC 24 |
185534305 ps |
| T836 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/21.xbar_stress_all_with_reset_error.2443169805 |
|
|
Aug 29 01:47:27 PM UTC 24 |
Aug 29 01:50:30 PM UTC 24 |
1909374738 ps |
| T805 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/20.xbar_access_same_device_slow_rsp.692616854 |
|
|
Aug 29 01:44:48 PM UTC 24 |
Aug 29 01:50:31 PM UTC 24 |
23485903599 ps |
| T1560 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/23.xbar_same_source.137090000 |
|
|
Aug 29 01:49:44 PM UTC 24 |
Aug 29 01:50:38 PM UTC 24 |
1305363250 ps |
| T1561 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/23.xbar_random_zero_delays.3645272246 |
|
|
Aug 29 01:49:25 PM UTC 24 |
Aug 29 01:50:41 PM UTC 24 |
637934344 ps |
| T1562 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/23.xbar_smoke_slow_rsp.405594384 |
|
|
Aug 29 01:49:19 PM UTC 24 |
Aug 29 01:50:42 PM UTC 24 |
5903870973 ps |
| T1563 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/21.xbar_random_slow_rsp.21214959 |
|
|
Aug 29 01:46:33 PM UTC 24 |
Aug 29 01:50:43 PM UTC 24 |
15572321038 ps |
| T605 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/22.chip_tl_errors.631129339 |
|
|
Aug 29 01:47:37 PM UTC 24 |
Aug 29 01:50:45 PM UTC 24 |
3416218230 ps |
| T1564 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/23.xbar_error_random.3776712580 |
|
|
Aug 29 01:49:47 PM UTC 24 |
Aug 29 01:50:52 PM UTC 24 |
513729084 ps |
| T1565 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/21.chip_tl_errors.1959728236 |
|
|
Aug 29 01:45:49 PM UTC 24 |
Aug 29 01:50:53 PM UTC 24 |
3922640547 ps |
| T1566 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/23.xbar_unmapped_addr.728360097 |
|
|
Aug 29 01:49:49 PM UTC 24 |
Aug 29 01:51:02 PM UTC 24 |
1345653630 ps |
| T1567 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/21.xbar_stress_all_with_error.1984428033 |
|
|
Aug 29 01:47:23 PM UTC 24 |
Aug 29 01:51:03 PM UTC 24 |
5681794687 ps |
| T851 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/23.xbar_access_same_device.2134992537 |
|
|
Aug 29 01:49:35 PM UTC 24 |
Aug 29 01:51:03 PM UTC 24 |
918291686 ps |
| T1568 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/24.xbar_smoke.2895039200 |
|
|
Aug 29 01:50:51 PM UTC 24 |
Aug 29 01:51:06 PM UTC 24 |
258889077 ps |
| T1569 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/24.xbar_smoke_zero_delays.2844005664 |
|
|
Aug 29 01:50:56 PM UTC 24 |
Aug 29 01:51:07 PM UTC 24 |
48837760 ps |
| T1570 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/23.xbar_smoke_large_delays.643768793 |
|
|
Aug 29 01:49:19 PM UTC 24 |
Aug 29 01:51:18 PM UTC 24 |
8460339180 ps |
| T1571 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/24.xbar_random.1672668861 |
|
|
Aug 29 01:51:04 PM UTC 24 |
Aug 29 01:51:38 PM UTC 24 |
907554445 ps |
| T1572 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/24.xbar_access_same_device.4171254858 |
|
|
Aug 29 01:51:22 PM UTC 24 |
Aug 29 01:51:41 PM UTC 24 |
92266871 ps |
| T1573 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/24.xbar_error_and_unmapped_addr.1415572658 |
|
|
Aug 29 01:51:38 PM UTC 24 |
Aug 29 01:51:49 PM UTC 24 |
73032431 ps |
| T395 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/10.chip_same_csr_outstanding.132490769 |
|
|
Aug 29 01:18:45 PM UTC 24 |
Aug 29 01:51:56 PM UTC 24 |
15693037157 ps |
| T1574 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/24.xbar_error_random.1149402275 |
|
|
Aug 29 01:51:25 PM UTC 24 |
Aug 29 01:52:01 PM UTC 24 |
626058688 ps |
| T484 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/24.xbar_random_zero_delays.574039320 |
|
|
Aug 29 01:51:06 PM UTC 24 |
Aug 29 01:52:02 PM UTC 24 |
570489277 ps |
| T537 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/24.xbar_same_source.3046839279 |
|
|
Aug 29 01:51:24 PM UTC 24 |
Aug 29 01:52:11 PM UTC 24 |
451366285 ps |
| T1575 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/22.xbar_stress_all_with_reset_error.3661650359 |
|
|
Aug 29 01:49:04 PM UTC 24 |
Aug 29 01:52:15 PM UTC 24 |
1773358771 ps |
| T532 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/7.xbar_access_same_device_slow_rsp.1520394777 |
|
|
Aug 29 01:13:41 PM UTC 24 |
Aug 29 01:52:17 PM UTC 24 |
121191924401 ps |
| T1576 |
/workspaces/repo/scratch/os_regression_2024_08_28/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/24.xbar_unmapped_addr.917459379 |
|
|
Aug 29 01:51:27 PM UTC 24 |
Aug 29 01:52:22 PM UTC 24 |
922572456 ps |