| T52 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/0.rom_e2e_shutdown_exception_c.362177509 |
|
|
Sep 02 03:02:46 AM UTC 24 |
Sep 02 04:20:23 AM UTC 24 |
15091875840 ps |
| T117 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_uart_tx_rx_idx2.1759672798 |
|
|
Sep 02 04:10:54 AM UTC 24 |
Sep 02 04:22:14 AM UTC 24 |
3922810400 ps |
| T118 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_nothing_rma.2702118632 |
|
|
Sep 02 03:10:18 AM UTC 24 |
Sep 02 04:22:19 AM UTC 24 |
14335406854 ps |
| T119 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_uart_tx_rx_idx1.176972094 |
|
|
Sep 02 04:09:13 AM UTC 24 |
Sep 02 04:23:16 AM UTC 24 |
4590053944 ps |
| T120 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_uart_tx_rx_idx3.3946301885 |
|
|
Sep 02 04:10:54 AM UTC 24 |
Sep 02 04:23:31 AM UTC 24 |
3699031600 ps |
| T247 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_lc_walkthrough_rma.2522441203 |
|
|
Sep 02 02:23:22 AM UTC 24 |
Sep 02 04:24:02 AM UTC 24 |
45949256653 ps |
| T78 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_spi_device_pinmux_sleep_retention.2770321484 |
|
|
Sep 02 04:20:38 AM UTC 24 |
Sep 02 04:25:13 AM UTC 24 |
3030155841 ps |
| T48 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_spi_device_tpm.582395703 |
|
|
Sep 02 04:20:05 AM UTC 24 |
Sep 02 04:25:48 AM UTC 24 |
3514013989 ps |
| T43 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_spi_host_tx_rx.1656775941 |
|
|
Sep 02 04:20:38 AM UTC 24 |
Sep 02 04:26:36 AM UTC 24 |
3371621428 ps |
| T889 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/0.rom_e2e_smoke.623103706 |
|
|
Sep 02 03:06:19 AM UTC 24 |
Sep 02 04:26:53 AM UTC 24 |
14539849496 ps |
| T365 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_good_dev.1109298426 |
|
|
Sep 02 03:05:15 AM UTC 24 |
Sep 02 04:27:32 AM UTC 24 |
14889219906 ps |
| T245 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_lc_walkthrough_prod.2436271265 |
|
|
Sep 02 02:17:45 AM UTC 24 |
Sep 02 04:28:04 AM UTC 24 |
47376169849 ps |
| T62 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_i2c_host_tx_rx_idx2.873521636 |
|
|
Sep 02 04:18:38 AM UTC 24 |
Sep 02 04:29:12 AM UTC 24 |
3784203458 ps |
| T890 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_good_rma.2346467088 |
|
|
Sep 02 03:08:59 AM UTC 24 |
Sep 02 04:29:32 AM UTC 24 |
14804665760 ps |
| T891 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/0.rom_e2e_asm_init_rma.2721936838 |
|
|
Sep 02 03:12:58 AM UTC 24 |
Sep 02 04:29:33 AM UTC 24 |
14979713661 ps |
| T342 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_i2c_device_tx_rx.839158912 |
|
|
Sep 02 04:19:31 AM UTC 24 |
Sep 02 04:29:57 AM UTC 24 |
4350995912 ps |
| T366 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_bad_dev.3354542985 |
|
|
Sep 02 03:08:29 AM UTC 24 |
Sep 02 04:30:04 AM UTC 24 |
15528476470 ps |
| T614 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/0.rom_e2e_sigverify_always_a_nothing_b_bad_rma.789217494 |
|
|
Sep 02 03:13:05 AM UTC 24 |
Sep 02 04:30:08 AM UTC 24 |
14476244648 ps |
| T892 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_bad_prod_end.2086419924 |
|
|
Sep 02 03:06:54 AM UTC 24 |
Sep 02 04:30:25 AM UTC 24 |
15744070636 ps |
| T893 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_bad_rma.969686301 |
|
|
Sep 02 03:09:01 AM UTC 24 |
Sep 02 04:30:44 AM UTC 24 |
15298741766 ps |
| T137 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_i2c_host_tx_rx.1348999987 |
|
|
Sep 02 04:17:39 AM UTC 24 |
Sep 02 04:31:25 AM UTC 24 |
5152375400 ps |
| T285 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/0.rom_e2e_sigverify_always_a_nothing_b_bad_dev.3524607915 |
|
|
Sep 02 03:11:16 AM UTC 24 |
Sep 02 04:31:36 AM UTC 24 |
15165849473 ps |
| T592 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq.698281256 |
|
|
Sep 02 03:00:56 AM UTC 24 |
Sep 02 04:31:46 AM UTC 24 |
25193941476 ps |
| T248 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_lc_walkthrough_dev.2111686662 |
|
|
Sep 02 02:17:40 AM UTC 24 |
Sep 02 04:32:00 AM UTC 24 |
49503414460 ps |
| T221 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_spi_device_pass_through_collision.519228358 |
|
|
Sep 02 04:21:41 AM UTC 24 |
Sep 02 04:32:15 AM UTC 24 |
4442141495 ps |
| T361 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/0.rom_e2e_shutdown_output.709605630 |
|
|
Sep 02 03:05:14 AM UTC 24 |
Sep 02 04:32:23 AM UTC 24 |
28396263402 ps |
| T894 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_good_prod_end.2495052840 |
|
|
Sep 02 03:04:52 AM UTC 24 |
Sep 02 04:32:29 AM UTC 24 |
16248547652 ps |
| T286 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/0.rom_e2e_sigverify_always_a_nothing_b_bad_prod_end.1404594365 |
|
|
Sep 02 03:12:41 AM UTC 24 |
Sep 02 04:32:31 AM UTC 24 |
15445332938 ps |
| T60 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_i2c_host_tx_rx_idx1.1230518127 |
|
|
Sep 02 04:17:39 AM UTC 24 |
Sep 02 04:32:51 AM UTC 24 |
5214760448 ps |
| T895 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/0.rom_e2e_asm_init_prod_end.2204204061 |
|
|
Sep 02 03:13:07 AM UTC 24 |
Sep 02 04:32:57 AM UTC 24 |
15512830245 ps |
| T896 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_nothing_prod_end.2423444506 |
|
|
Sep 02 03:11:00 AM UTC 24 |
Sep 02 04:33:00 AM UTC 24 |
14342423538 ps |
| T39 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_gpio.552743414 |
|
|
Sep 02 04:23:03 AM UTC 24 |
Sep 02 04:33:04 AM UTC 24 |
4828787358 ps |
| T897 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_good_prod.2149221572 |
|
|
Sep 02 03:06:19 AM UTC 24 |
Sep 02 04:33:19 AM UTC 24 |
15803801200 ps |
| T898 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_sleep_pwm_pulses.2414717111 |
|
|
Sep 02 04:07:28 AM UTC 24 |
Sep 02 04:33:30 AM UTC 24 |
8558654452 ps |
| T249 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_flash_ctrl_lc_rw_en.1524745021 |
|
|
Sep 02 04:24:07 AM UTC 24 |
Sep 02 04:33:42 AM UTC 24 |
4293767529 ps |
| T899 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_kmac_entropy.3208840524 |
|
|
Sep 02 04:28:38 AM UTC 24 |
Sep 02 04:34:05 AM UTC 24 |
2942665052 ps |
| T346 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_flash_ctrl_ops.4268948136 |
|
|
Sep 02 04:23:04 AM UTC 24 |
Sep 02 04:34:06 AM UTC 24 |
4133719752 ps |
| T900 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_flash_ctrl_idle_low_power.3976985217 |
|
|
Sep 02 04:26:25 AM UTC 24 |
Sep 02 04:34:08 AM UTC 24 |
3858302048 ps |
| T901 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_lc_ctrl_otp_hw_cfg0.305945469 |
|
|
Sep 02 04:29:48 AM UTC 24 |
Sep 02 04:34:49 AM UTC 24 |
2878035512 ps |
| T902 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_nothing_dev.404085732 |
|
|
Sep 02 03:12:09 AM UTC 24 |
Sep 02 04:35:36 AM UTC 24 |
15475455544 ps |
| T597 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_lc_ctrl_volatile_raw_unlock.464467887 |
|
|
Sep 02 04:33:37 AM UTC 24 |
Sep 02 04:35:37 AM UTC 24 |
2105016866 ps |
| T903 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_otp_ctrl_ecc_error_vendor_test.1820505724 |
|
|
Sep 02 04:31:10 AM UTC 24 |
Sep 02 04:35:52 AM UTC 24 |
2466227851 ps |
| T222 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_spi_device_pass_through.2510226756 |
|
|
Sep 02 04:21:01 AM UTC 24 |
Sep 02 04:35:57 AM UTC 24 |
6672463981 ps |
| T191 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_otp_ctrl_vendor_test_csr_access.2568099180 |
|
|
Sep 02 04:31:20 AM UTC 24 |
Sep 02 04:36:04 AM UTC 24 |
3032632949 ps |
| T358 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_flash_ctrl_ops_jitter_en.3180776043 |
|
|
Sep 02 04:24:02 AM UTC 24 |
Sep 02 04:36:21 AM UTC 24 |
4157797378 ps |
| T904 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/0.rom_e2e_sigverify_always_a_nothing_b_bad_prod.2073260540 |
|
|
Sep 02 03:11:42 AM UTC 24 |
Sep 02 04:36:36 AM UTC 24 |
14651007644 ps |
| T133 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_uart_tx_rx_alt_clk_freq_low_speed.1808194964 |
|
|
Sep 02 04:15:31 AM UTC 24 |
Sep 02 04:36:49 AM UTC 24 |
8130418437 ps |
| T905 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_bad_prod.535880710 |
|
|
Sep 02 03:09:11 AM UTC 24 |
Sep 02 04:37:02 AM UTC 24 |
15692511618 ps |
| T598 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz.2137108791 |
|
|
Sep 02 04:34:58 AM UTC 24 |
Sep 02 04:37:22 AM UTC 24 |
2480613391 ps |
| T906 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_nothing_prod.2062051332 |
|
|
Sep 02 03:12:11 AM UTC 24 |
Sep 02 04:38:25 AM UTC 24 |
14118702154 ps |
| T907 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_rstmgr_sw_rst.2520142692 |
|
|
Sep 02 04:34:06 AM UTC 24 |
Sep 02 04:38:29 AM UTC 24 |
2918082272 ps |
| T427 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/0.rom_e2e_jtag_inject_test_unlocked0.1923311107 |
|
|
Sep 02 03:18:22 AM UTC 24 |
Sep 02 04:39:02 AM UTC 24 |
34235193901 ps |
| T619 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/0.rom_e2e_jtag_inject_rma.1289719771 |
|
|
Sep 02 03:20:36 AM UTC 24 |
Sep 02 04:39:11 AM UTC 24 |
42002820246 ps |
| T908 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/0.rom_e2e_asm_init_prod.3530563835 |
|
|
Sep 02 03:13:04 AM UTC 24 |
Sep 02 04:39:41 AM UTC 24 |
15451944669 ps |
| T909 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_otp_ctrl_lc_signals_test_unlocked0.488718322 |
|
|
Sep 02 04:30:19 AM UTC 24 |
Sep 02 04:40:34 AM UTC 24 |
4157948460 ps |
| T910 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/0.rom_e2e_asm_init_dev.4143433402 |
|
|
Sep 02 03:13:06 AM UTC 24 |
Sep 02 04:40:48 AM UTC 24 |
15320047114 ps |
| T911 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_lc_ctrl_transition.2052031024 |
|
|
Sep 02 04:31:25 AM UTC 24 |
Sep 02 04:41:22 AM UTC 24 |
5761769062 ps |
| T912 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_pwrmgr_main_power_glitch_reset.3223453578 |
|
|
Sep 02 04:35:41 AM UTC 24 |
Sep 02 04:41:48 AM UTC 24 |
4387699500 ps |
| T913 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/0.rom_e2e_keymgr_init_rom_ext_meas.1123251036 |
|
|
Sep 02 03:21:38 AM UTC 24 |
Sep 02 04:42:00 AM UTC 24 |
15508531056 ps |
| T914 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_uart_rand_baudrate.3763865268 |
|
|
Sep 02 04:14:39 AM UTC 24 |
Sep 02 04:42:54 AM UTC 24 |
7999346240 ps |
| T438 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_csrng_edn_concurrency.1428003570 |
|
|
Sep 02 02:35:22 AM UTC 24 |
Sep 02 04:43:03 AM UTC 24 |
22462342496 ps |
| T915 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_rv_timer_irq.745518631 |
|
|
Sep 02 04:38:04 AM UTC 24 |
Sep 02 04:43:07 AM UTC 24 |
2342797860 ps |
| T607 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_pwrmgr_sleep_disabled.1358455349 |
|
|
Sep 02 04:38:03 AM UTC 24 |
Sep 02 04:43:22 AM UTC 24 |
3307637508 ps |
| T916 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_rstmgr_sw_req.4187618204 |
|
|
Sep 02 04:35:34 AM UTC 24 |
Sep 02 04:44:04 AM UTC 24 |
5001689552 ps |
| T917 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_flash_ctrl_access_jitter_en.3309889345 |
|
|
Sep 02 04:25:50 AM UTC 24 |
Sep 02 04:44:16 AM UTC 24 |
6395662420 ps |
| T918 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_flash_ctrl_access.3340444388 |
|
|
Sep 02 04:24:39 AM UTC 24 |
Sep 02 04:44:25 AM UTC 24 |
5709007804 ps |
| T177 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_pwrmgr_full_aon_reset.2407114583 |
|
|
Sep 02 04:34:59 AM UTC 24 |
Sep 02 04:44:28 AM UTC 24 |
8420183729 ps |
| T228 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_sysrst_ctrl_inputs.402845870 |
|
|
Sep 02 04:38:07 AM UTC 24 |
Sep 02 04:44:39 AM UTC 24 |
2758083605 ps |
| T45 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_sysrst_ctrl_ulp_z3_wakeup.1689192872 |
|
|
Sep 02 04:39:17 AM UTC 24 |
Sep 02 04:46:21 AM UTC 24 |
5432482850 ps |
| T919 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_pwrmgr_deep_sleep_power_glitch_reset.1459826106 |
|
|
Sep 02 04:37:54 AM UTC 24 |
Sep 02 04:47:15 AM UTC 24 |
7810289980 ps |
| T920 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_aon_timer_irq.2716056757 |
|
|
Sep 02 04:41:11 AM UTC 24 |
Sep 02 04:47:23 AM UTC 24 |
4050006168 ps |
| T229 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_sysrst_ctrl_outputs.1919416125 |
|
|
Sep 02 04:39:52 AM UTC 24 |
Sep 02 04:47:26 AM UTC 24 |
3966473516 ps |
| T921 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_flash_ctrl_clock_freqs.3408974801 |
|
|
Sep 02 04:28:09 AM UTC 24 |
Sep 02 04:47:49 AM UTC 24 |
5222080472 ps |
| T93 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_usbdev_pincfg.512885564 |
|
|
Sep 02 02:10:02 AM UTC 24 |
Sep 02 04:47:53 AM UTC 24 |
32107388816 ps |
| T922 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_pwrmgr_normal_sleep_por_reset.2798656955 |
|
|
Sep 02 04:37:00 AM UTC 24 |
Sep 02 04:48:38 AM UTC 24 |
5099816086 ps |
| T923 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/0.rom_e2e_keymgr_init_rom_ext_no_meas.3887147810 |
|
|
Sep 02 03:21:49 AM UTC 24 |
Sep 02 04:48:46 AM UTC 24 |
15751918028 ps |
| T258 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_rstmgr_cpu_info.1742433515 |
|
|
Sep 02 04:35:35 AM UTC 24 |
Sep 02 04:49:32 AM UTC 24 |
6881243524 ps |
| T230 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_sysrst_ctrl_in_irq.2234410726 |
|
|
Sep 02 04:39:16 AM UTC 24 |
Sep 02 04:49:43 AM UTC 24 |
4312779389 ps |
| T924 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_pwrmgr_usb_clk_disabled_when_active.3438283246 |
|
|
Sep 02 04:38:02 AM UTC 24 |
Sep 02 04:50:36 AM UTC 24 |
6134586928 ps |
| T925 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_pwrmgr_deep_sleep_por_reset.2300789495 |
|
|
Sep 02 04:37:34 AM UTC 24 |
Sep 02 04:50:47 AM UTC 24 |
7334944940 ps |
| T926 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_aes_idle.1296556688 |
|
|
Sep 02 04:45:29 AM UTC 24 |
Sep 02 04:50:50 AM UTC 24 |
2764740500 ps |
| T927 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_aon_timer_sleep_wdog_sleep_pause.3477791909 |
|
|
Sep 02 04:41:35 AM UTC 24 |
Sep 02 04:50:54 AM UTC 24 |
8155369684 ps |
| T928 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_aes_enc.2197924870 |
|
|
Sep 02 04:45:21 AM UTC 24 |
Sep 02 04:51:09 AM UTC 24 |
2986252524 ps |
| T929 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_otp_ctrl_lc_signals_dev.3322469992 |
|
|
Sep 02 04:30:19 AM UTC 24 |
Sep 02 04:51:25 AM UTC 24 |
8033914944 ps |
| T930 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_aes_masking_off.2615698583 |
|
|
Sep 02 04:45:28 AM UTC 24 |
Sep 02 04:51:35 AM UTC 24 |
2772910554 ps |
| T931 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_aes_enc_jitter_en.2531719349 |
|
|
Sep 02 04:45:25 AM UTC 24 |
Sep 02 04:51:41 AM UTC 24 |
3280795896 ps |
| T76 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_alert_test.422014958 |
|
|
Sep 02 04:46:59 AM UTC 24 |
Sep 02 04:52:10 AM UTC 24 |
2618275112 ps |
| T932 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/0.rom_e2e_static_critical.1735006058 |
|
|
Sep 02 03:21:07 AM UTC 24 |
Sep 02 04:52:17 AM UTC 24 |
16942268436 ps |
| T933 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_adc_ctrl_sleep_debug_cable_wakeup.75436010 |
|
|
Sep 02 04:42:39 AM UTC 24 |
Sep 02 04:52:59 AM UTC 24 |
17938037512 ps |
| T934 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_pwrmgr_wdog_reset.308719107 |
|
|
Sep 02 04:41:57 AM UTC 24 |
Sep 02 04:53:03 AM UTC 24 |
6163464176 ps |
| T935 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_pwrmgr_sysrst_ctrl_reset.786748106 |
|
|
Sep 02 04:35:42 AM UTC 24 |
Sep 02 04:53:59 AM UTC 24 |
6027340192 ps |
| T936 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_aon_timer_wdog_lc_escalate.868337635 |
|
|
Sep 02 04:42:35 AM UTC 24 |
Sep 02 04:54:19 AM UTC 24 |
4404516628 ps |
| T937 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_lc_walkthrough_prodend.160216516 |
|
|
Sep 02 04:34:08 AM UTC 24 |
Sep 02 04:55:03 AM UTC 24 |
11787285170 ps |
| T938 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_otp_ctrl_lc_signals_prod.1666736683 |
|
|
Sep 02 04:31:05 AM UTC 24 |
Sep 02 04:55:24 AM UTC 24 |
7458095416 ps |
| T102 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_alert_handler_entropy.1048418782 |
|
|
Sep 02 04:50:23 AM UTC 24 |
Sep 02 04:55:28 AM UTC 24 |
3236340486 ps |
| T356 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_alert_handler_ping_timeout.1269946764 |
|
|
Sep 02 04:48:38 AM UTC 24 |
Sep 02 04:55:50 AM UTC 24 |
3275676648 ps |
| T389 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/0.rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0.411171635 |
|
|
Sep 02 03:05:52 AM UTC 24 |
Sep 02 04:56:25 AM UTC 24 |
17825346880 ps |
| T939 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/0.rom_e2e_keymgr_init_rom_ext_invalid_meas.846185598 |
|
|
Sep 02 03:30:00 AM UTC 24 |
Sep 02 04:57:12 AM UTC 24 |
14414222240 ps |
| T940 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_otp_ctrl_lc_signals_rma.4091228913 |
|
|
Sep 02 04:31:09 AM UTC 24 |
Sep 02 04:57:22 AM UTC 24 |
7752646134 ps |
| T941 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_aes_entropy.591403745 |
|
|
Sep 02 04:51:52 AM UTC 24 |
Sep 02 04:57:31 AM UTC 24 |
3365403082 ps |
| T636 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_alert_handler_lpg_sleep_mode_alerts.2490023815 |
|
|
Sep 02 04:48:45 AM UTC 24 |
Sep 02 04:57:33 AM UTC 24 |
3470065248 ps |
| T942 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_entropy_src_kat_test.3745464936 |
|
|
Sep 02 04:52:28 AM UTC 24 |
Sep 02 04:57:38 AM UTC 24 |
2740579468 ps |
| T943 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_entropy_src_ast_rng_req.1349816443 |
|
|
Sep 02 04:53:33 AM UTC 24 |
Sep 02 04:57:59 AM UTC 24 |
2838752520 ps |
| T944 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_csrng_kat_test.1656530220 |
|
|
Sep 02 04:53:16 AM UTC 24 |
Sep 02 04:58:02 AM UTC 24 |
3064521324 ps |
| T439 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_rv_core_ibex_nmi_irq.3134665801 |
|
|
Sep 02 04:45:07 AM UTC 24 |
Sep 02 04:58:48 AM UTC 24 |
5065111806 ps |
| T945 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_hmac_enc.1757806576 |
|
|
Sep 02 04:54:54 AM UTC 24 |
Sep 02 04:58:53 AM UTC 24 |
3003644440 ps |
| T946 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_pwrmgr_all_reset_reqs.2306057936 |
|
|
Sep 02 04:35:45 AM UTC 24 |
Sep 02 04:59:05 AM UTC 24 |
10609673433 ps |
| T947 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_aon_timer_wdog_bite_reset.785167130 |
|
|
Sep 02 04:41:35 AM UTC 24 |
Sep 02 04:59:51 AM UTC 24 |
10566841400 ps |
| T948 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_alert_handler_escalation.2444272822 |
|
|
Sep 02 04:48:41 AM UTC 24 |
Sep 02 05:00:00 AM UTC 24 |
5586064306 ps |
| T949 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_pwrmgr_normal_sleep_all_reset_reqs.4267991381 |
|
|
Sep 02 04:35:40 AM UTC 24 |
Sep 02 05:00:02 AM UTC 24 |
9151466698 ps |
| T950 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_otbn_randomness.1766687045 |
|
|
Sep 02 04:44:18 AM UTC 24 |
Sep 02 05:00:32 AM UTC 24 |
5346728440 ps |
| T951 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_csrng_fuse_en_sw_app_read_test.3923473372 |
|
|
Sep 02 04:53:32 AM UTC 24 |
Sep 02 05:00:44 AM UTC 24 |
4770392792 ps |
| T952 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_hmac_enc_idle.2556015425 |
|
|
Sep 02 04:56:23 AM UTC 24 |
Sep 02 05:01:21 AM UTC 24 |
2924873492 ps |
| T360 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_hmac_enc_jitter_en.2510704064 |
|
|
Sep 02 04:55:40 AM UTC 24 |
Sep 02 05:01:32 AM UTC 24 |
3277006300 ps |
| T586 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_edn_boot_mode.599345106 |
|
|
Sep 02 04:53:15 AM UTC 24 |
Sep 02 05:02:49 AM UTC 24 |
3168607720 ps |
| T953 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_bad_test_unlocked0.4092238021 |
|
|
Sep 02 03:10:54 AM UTC 24 |
Sep 02 05:03:14 AM UTC 24 |
17738540970 ps |
| T954 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_rv_core_ibex_rnd.1262981034 |
|
|
Sep 02 04:44:22 AM UTC 24 |
Sep 02 05:03:40 AM UTC 24 |
5891940424 ps |
| T955 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_hmac_oneshot.1952411905 |
|
|
Sep 02 04:56:23 AM UTC 24 |
Sep 02 05:03:59 AM UTC 24 |
3055357448 ps |
| T956 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_kmac_mode_cshake.928927318 |
|
|
Sep 02 04:59:04 AM UTC 24 |
Sep 02 05:04:08 AM UTC 24 |
2696392736 ps |
| T957 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_kmac_mode_kmac.1499093219 |
|
|
Sep 02 04:59:02 AM UTC 24 |
Sep 02 05:04:40 AM UTC 24 |
2994746184 ps |
| T958 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_edn_kat.3474733110 |
|
|
Sep 02 04:52:45 AM UTC 24 |
Sep 02 05:04:44 AM UTC 24 |
3305401548 ps |
| T959 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_csrng_lc_hw_debug_en_test.1503850793 |
|
|
Sep 02 04:53:03 AM UTC 24 |
Sep 02 05:04:57 AM UTC 24 |
4757932278 ps |
| T960 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_kmac_idle.348379824 |
|
|
Sep 02 04:59:46 AM UTC 24 |
Sep 02 05:04:59 AM UTC 24 |
2254447060 ps |
| T406 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_kmac_app_rom.631419531 |
|
|
Sep 02 04:59:45 AM UTC 24 |
Sep 02 05:05:04 AM UTC 24 |
2700449772 ps |
| T961 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_pwrmgr_deep_sleep_all_reset_reqs.3626054388 |
|
|
Sep 02 04:35:27 AM UTC 24 |
Sep 02 05:06:07 AM UTC 24 |
15966733555 ps |
| T962 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_kmac_mode_kmac_jitter_en.518396097 |
|
|
Sep 02 04:59:44 AM UTC 24 |
Sep 02 05:06:53 AM UTC 24 |
3526531353 ps |
| T250 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_flash_init.2199311459 |
|
|
Sep 02 04:27:06 AM UTC 24 |
Sep 02 05:07:02 AM UTC 24 |
17352946048 ps |
| T963 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_alert_handler_lpg_clkoff.479881184 |
|
|
Sep 02 04:49:26 AM UTC 24 |
Sep 02 05:07:37 AM UTC 24 |
5232855142 ps |
| T348 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_sensor_ctrl_status.4283799139 |
|
|
Sep 02 05:03:26 AM UTC 24 |
Sep 02 05:08:16 AM UTC 24 |
2852909518 ps |
| T964 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_sysrst_ctrl_reset.4261123529 |
|
|
Sep 02 04:39:51 AM UTC 24 |
Sep 02 05:08:39 AM UTC 24 |
21273899650 ps |
| T353 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_uart_tx_rx_alt_clk_freq.2725816605 |
|
|
Sep 02 04:15:15 AM UTC 24 |
Sep 02 05:09:06 AM UTC 24 |
13492118785 ps |
| T965 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_sleep_sram_ret_contents_no_scramble.2311463361 |
|
|
Sep 02 05:01:21 AM UTC 24 |
Sep 02 05:10:31 AM UTC 24 |
6697789024 ps |
| T272 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_plic_sw_irq.3091891462 |
|
|
Sep 02 05:06:03 AM UTC 24 |
Sep 02 05:12:23 AM UTC 24 |
2828856296 ps |
| T966 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_edn_entropy_reqs_jitter.55156284 |
|
|
Sep 02 04:54:37 AM UTC 24 |
Sep 02 05:12:49 AM UTC 24 |
6593478166 ps |
| T407 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_rom_ctrl_integrity_check.3532883396 |
|
|
Sep 02 05:00:53 AM UTC 24 |
Sep 02 05:13:04 AM UTC 24 |
8684841756 ps |
| T296 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_sram_ctrl_scrambled_access_jitter_en.1507922014 |
|
|
Sep 02 05:00:52 AM UTC 24 |
Sep 02 05:13:07 AM UTC 24 |
6034540156 ps |
| T274 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_alert_handler_lpg_sleep_mode_pings.511335061 |
|
|
Sep 02 04:49:25 AM UTC 24 |
Sep 02 05:13:15 AM UTC 24 |
10980945080 ps |
| T166 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup.1369761566 |
|
|
Sep 02 05:03:50 AM UTC 24 |
Sep 02 05:13:33 AM UTC 24 |
5185671600 ps |
| T297 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_sram_ctrl_scrambled_access.2224981912 |
|
|
Sep 02 05:00:51 AM UTC 24 |
Sep 02 05:14:21 AM UTC 24 |
5240487452 ps |
| T316 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_sram_ctrl_execution_main.1429960176 |
|
|
Sep 02 05:01:17 AM UTC 24 |
Sep 02 05:14:38 AM UTC 24 |
7171821429 ps |
| T967 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_clkmgr_off_otbn_trans.3970092975 |
|
|
Sep 02 05:07:39 AM UTC 24 |
Sep 02 05:14:49 AM UTC 24 |
4873938996 ps |
| T968 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_clkmgr_off_kmac_trans.447421097 |
|
|
Sep 02 05:06:43 AM UTC 24 |
Sep 02 05:14:53 AM UTC 24 |
4883571752 ps |
| T969 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_lc_walkthrough_testunlocks.2065897724 |
|
|
Sep 02 04:34:09 AM UTC 24 |
Sep 02 05:15:11 AM UTC 24 |
27382862632 ps |
| T338 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_rstmgr_alert_info.934687853 |
|
|
Sep 02 04:35:27 AM UTC 24 |
Sep 02 05:15:26 AM UTC 24 |
11525402984 ps |
| T186 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_plic_all_irqs_10.3710413289 |
|
|
Sep 02 05:04:48 AM UTC 24 |
Sep 02 05:15:44 AM UTC 24 |
4089002598 ps |
| T970 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_alert_handler_ping_ok.2525736548 |
|
|
Sep 02 04:48:24 AM UTC 24 |
Sep 02 05:15:56 AM UTC 24 |
7653901856 ps |
| T971 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_clkmgr_off_aes_trans.2355587774 |
|
|
Sep 02 05:06:05 AM UTC 24 |
Sep 02 05:16:18 AM UTC 24 |
4547289230 ps |
| T972 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_edn_entropy_reqs.1161753773 |
|
|
Sep 02 04:53:50 AM UTC 24 |
Sep 02 05:17:46 AM UTC 24 |
6985051748 ps |
| T973 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_clkmgr_off_hmac_trans.3911881073 |
|
|
Sep 02 05:06:06 AM UTC 24 |
Sep 02 05:17:52 AM UTC 24 |
5676766280 ps |
| T974 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_sleep_sram_ret_contents_scramble.1867608205 |
|
|
Sep 02 05:02:06 AM UTC 24 |
Sep 02 05:18:19 AM UTC 24 |
8354813130 ps |
| T975 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0.3722717868 |
|
|
Sep 02 05:08:14 AM UTC 24 |
Sep 02 05:19:07 AM UTC 24 |
3904691712 ps |
| T976 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_pwrmgr_random_sleep_all_reset_reqs.3111403172 |
|
|
Sep 02 04:35:41 AM UTC 24 |
Sep 02 05:19:26 AM UTC 24 |
23193527413 ps |
| T977 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_clkmgr_external_clk_src_for_sw_fast_dev.2917171432 |
|
|
Sep 02 05:09:15 AM UTC 24 |
Sep 02 05:19:39 AM UTC 24 |
4354772668 ps |
| T978 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_clkmgr_jitter.110981746 |
|
|
Sep 02 05:14:03 AM UTC 24 |
Sep 02 05:19:54 AM UTC 24 |
3393670155 ps |
| T979 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_clkmgr_reset_frequency.2337015051 |
|
|
Sep 02 05:13:24 AM UTC 24 |
Sep 02 05:20:12 AM UTC 24 |
2921538336 ps |
| T325 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_plic_all_irqs_20.541273317 |
|
|
Sep 02 05:06:01 AM UTC 24 |
Sep 02 05:20:23 AM UTC 24 |
4554116160 ps |
| T980 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0.1543343260 |
|
|
Sep 02 05:08:54 AM UTC 24 |
Sep 02 05:20:44 AM UTC 24 |
5140275752 ps |
| T589 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_edn_auto_mode.2240389819 |
|
|
Sep 02 04:52:37 AM UTC 24 |
Sep 02 05:20:45 AM UTC 24 |
6077986760 ps |
| T981 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_clkmgr_external_clk_src_for_sw_slow_dev.877367398 |
|
|
Sep 02 05:09:44 AM UTC 24 |
Sep 02 05:21:25 AM UTC 24 |
4857005424 ps |
| T982 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_bad_dev.2628629606 |
|
|
Sep 02 03:08:25 AM UTC 24 |
Sep 02 05:22:25 AM UTC 24 |
23355719448 ps |
| T171 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_sensor_ctrl_alert.368810245 |
|
|
Sep 02 05:02:09 AM UTC 24 |
Sep 02 05:22:39 AM UTC 24 |
8596987576 ps |
| T983 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_tap_straps_dev.305300592 |
|
|
Sep 02 05:19:55 AM UTC 24 |
Sep 02 05:23:06 AM UTC 24 |
2167867575 ps |
| T984 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_clkmgr_external_clk_src_for_sw_fast_rma.2106483053 |
|
|
Sep 02 05:11:08 AM UTC 24 |
Sep 02 05:23:08 AM UTC 24 |
3925881700 ps |
| T985 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_tap_straps_prod.3014378566 |
|
|
Sep 02 05:20:42 AM UTC 24 |
Sep 02 05:24:37 AM UTC 24 |
2794664202 ps |
| T986 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_alert_handler_lpg_reset_toggle.140569350 |
|
|
Sep 02 04:50:21 AM UTC 24 |
Sep 02 05:23:13 AM UTC 24 |
8228929396 ps |
| T987 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_clkmgr_jitter_frequency.880442316 |
|
|
Sep 02 05:14:04 AM UTC 24 |
Sep 02 05:23:27 AM UTC 24 |
3311332196 ps |
| T988 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_clkmgr_external_clk_src_for_sw_slow_rma.240308721 |
|
|
Sep 02 05:13:00 AM UTC 24 |
Sep 02 05:23:49 AM UTC 24 |
4604889396 ps |
| T121 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_pwrmgr_normal_sleep_all_wake_ups.3908707364 |
|
|
Sep 02 05:15:49 AM UTC 24 |
Sep 02 05:23:53 AM UTC 24 |
7021430898 ps |
| T368 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up.4208380220 |
|
|
Sep 02 05:16:56 AM UTC 24 |
Sep 02 05:23:56 AM UTC 24 |
4702404312 ps |
| T989 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_keymgr_key_derivation.3379714285 |
|
|
Sep 02 04:56:58 AM UTC 24 |
Sep 02 05:24:08 AM UTC 24 |
8824286040 ps |
| T990 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_clkmgr_off_peri.800483173 |
|
|
Sep 02 05:05:54 AM UTC 24 |
Sep 02 05:24:56 AM UTC 24 |
8191188000 ps |
| T991 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_clkmgr_sleep_frequency.1054641196 |
|
|
Sep 02 05:14:04 AM UTC 24 |
Sep 02 05:25:33 AM UTC 24 |
4371187960 ps |
| T337 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_entropy_src_csrng.473264144 |
|
|
Sep 02 04:53:47 AM UTC 24 |
Sep 02 05:25:41 AM UTC 24 |
7693681360 ps |
| T206 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_rv_core_ibex_address_translation.1922783881 |
|
|
Sep 02 05:21:00 AM UTC 24 |
Sep 02 05:26:24 AM UTC 24 |
2352324340 ps |
| T992 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_pwrmgr_sleep_wake_5_bug.983477314 |
|
|
Sep 02 05:16:37 AM UTC 24 |
Sep 02 05:26:42 AM UTC 24 |
6320794912 ps |
| T993 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_clkmgr_external_clk_src_for_lc.716829535 |
|
|
Sep 02 05:07:40 AM UTC 24 |
Sep 02 05:26:46 AM UTC 24 |
9940580616 ps |
| T311 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_rv_core_ibex_icache_invalidate.3655878134 |
|
|
Sep 02 05:21:31 AM UTC 24 |
Sep 02 05:26:50 AM UTC 24 |
3594030183 ps |
| T994 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_bad_prod.2249850984 |
|
|
Sep 02 03:12:12 AM UTC 24 |
Sep 02 05:26:52 AM UTC 24 |
24034147161 ps |
| T390 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/0.rom_e2e_boot_policy_valid_a_bad_b_good_dev.214927269 |
|
|
Sep 02 03:06:24 AM UTC 24 |
Sep 02 05:26:54 AM UTC 24 |
23766559720 ps |
| T328 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_plic_all_irqs_0.850926542 |
|
|
Sep 02 05:04:45 AM UTC 24 |
Sep 02 05:26:55 AM UTC 24 |
6468913246 ps |
| T995 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_clkmgr_jitter_reduced_freq.1463362763 |
|
|
Sep 02 05:23:15 AM UTC 24 |
Sep 02 05:27:07 AM UTC 24 |
3066618875 ps |
| T386 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_rv_dm_ndm_reset_req.2843583724 |
|
|
Sep 02 05:18:32 AM UTC 24 |
Sep 02 05:27:24 AM UTC 24 |
3861403644 ps |
| T322 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_rv_dm_ndm_reset_req_when_cpu_halted.4047354892 |
|
|
Sep 02 05:18:33 AM UTC 24 |
Sep 02 05:27:30 AM UTC 24 |
5094084206 ps |
| T996 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_bad_prod_end.1823439266 |
|
|
Sep 02 03:09:55 AM UTC 24 |
Sep 02 05:28:23 AM UTC 24 |
23408227176 ps |
| T196 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_lc_ctrl_program_error.2385820115 |
|
|
Sep 02 05:15:52 AM UTC 24 |
Sep 02 05:28:27 AM UTC 24 |
4506818952 ps |
| T997 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_rv_dm_access_after_wakeup.486948110 |
|
|
Sep 02 05:18:56 AM UTC 24 |
Sep 02 05:28:29 AM UTC 24 |
5744324698 ps |
| T91 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_tap_straps_testunlock0.3117212631 |
|
|
Sep 02 05:20:06 AM UTC 24 |
Sep 02 05:28:42 AM UTC 24 |
4451924521 ps |
| T391 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/0.rom_e2e_boot_policy_valid_a_bad_b_good_rma.4063862433 |
|
|
Sep 02 03:08:23 AM UTC 24 |
Sep 02 05:28:46 AM UTC 24 |
23557482864 ps |
| T92 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_tap_straps_rma.3730327804 |
|
|
Sep 02 05:20:24 AM UTC 24 |
Sep 02 05:29:23 AM UTC 24 |
5652441606 ps |
| T595 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_rv_dm_access_after_escalation_reset.2982299209 |
|
|
Sep 02 05:19:44 AM UTC 24 |
Sep 02 05:29:39 AM UTC 24 |
5263085804 ps |
| T998 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_hmac_enc_jitter_en_reduced_freq.2694381055 |
|
|
Sep 02 05:25:46 AM UTC 24 |
Sep 02 05:29:41 AM UTC 24 |
3542789048 ps |
| T999 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_flash_ctrl_write_clear.3329821614 |
|
|
Sep 02 05:23:11 AM UTC 24 |
Sep 02 05:29:49 AM UTC 24 |
3354846932 ps |
| T1000 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_hmac_multistream.2990778573 |
|
|
Sep 02 04:56:27 AM UTC 24 |
Sep 02 05:30:24 AM UTC 24 |
8070249796 ps |
| T1001 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_kmac_mode_kmac_jitter_en_reduced_freq.3692905265 |
|
|
Sep 02 05:25:01 AM UTC 24 |
Sep 02 05:30:27 AM UTC 24 |
3423663540 ps |
| T1002 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_aes_enc_jitter_en_reduced_freq.804678568 |
|
|
Sep 02 05:25:34 AM UTC 24 |
Sep 02 05:30:38 AM UTC 24 |
3149311945 ps |
| T65 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_jtag_csr_rw.1909186090 |
|
|
Sep 02 05:13:54 AM UTC 24 |
Sep 02 05:32:18 AM UTC 24 |
11217254584 ps |
| T273 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_power_sleep_load.2258874454 |
|
|
Sep 02 05:25:57 AM UTC 24 |
Sep 02 05:33:27 AM UTC 24 |
4397794088 ps |
| T1003 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_flash_crash_alert.1761517409 |
|
|
Sep 02 05:22:02 AM UTC 24 |
Sep 02 05:33:53 AM UTC 24 |
5541139974 ps |
| T1004 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_keymgr_key_derivation_prod.812412894 |
|
|
Sep 02 04:58:58 AM UTC 24 |
Sep 02 05:34:18 AM UTC 24 |
8324189680 ps |
| T1005 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_flash_scrambling_smoketest.2746331828 |
|
|
Sep 02 05:29:30 AM UTC 24 |
Sep 02 05:34:31 AM UTC 24 |
3309045150 ps |
| T298 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq.2605776929 |
|
|
Sep 02 05:25:33 AM UTC 24 |
Sep 02 05:34:58 AM UTC 24 |
3755987930 ps |
| T1006 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_ast_clk_outputs.4131078002 |
|
|
Sep 02 05:15:33 AM UTC 24 |
Sep 02 05:35:09 AM UTC 24 |
8271119720 ps |
| T599 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/1.rom_volatile_raw_unlock.4523457 |
|
|
Sep 02 05:33:03 AM UTC 24 |
Sep 02 05:35:10 AM UTC 24 |
2142961247 ps |
| T1007 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_clkmgr_smoketest.714933893 |
|
|
Sep 02 05:33:09 AM UTC 24 |
Sep 02 05:36:35 AM UTC 24 |
2467873306 ps |
| T349 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_flash_ctrl_ops_jitter_en_reduced_freq.833412074 |
|
|
Sep 02 05:24:57 AM UTC 24 |
Sep 02 05:36:38 AM UTC 24 |
5489987760 ps |
| T1008 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_edn_sw_mode.1274959783 |
|
|
Sep 02 04:52:45 AM UTC 24 |
Sep 02 05:36:54 AM UTC 24 |
9155716792 ps |
| T1009 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_bad_rma.5544522 |
|
|
Sep 02 03:12:38 AM UTC 24 |
Sep 02 05:37:38 AM UTC 24 |
22915582904 ps |
| T1010 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_csrng_smoketest.1154543659 |
|
|
Sep 02 05:33:18 AM UTC 24 |
Sep 02 05:37:49 AM UTC 24 |
2169803856 ps |
| T1011 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_aon_timer_smoketest.2008302611 |
|
|
Sep 02 05:32:03 AM UTC 24 |
Sep 02 05:37:59 AM UTC 24 |
2674702670 ps |
| T183 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/1.rom_raw_unlock.1213213563 |
|
|
Sep 02 05:33:14 AM UTC 24 |
Sep 02 05:38:12 AM UTC 24 |
5411673088 ps |
| T1012 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_aes_smoketest.4098959060 |
|
|
Sep 02 05:33:08 AM UTC 24 |
Sep 02 05:38:26 AM UTC 24 |
3152533312 ps |
| T1013 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_gpio_smoketest.6410971 |
|
|
Sep 02 05:33:19 AM UTC 24 |
Sep 02 05:38:55 AM UTC 24 |
3349416350 ps |
| T1014 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_entropy_src_smoketest.1224489204 |
|
|
Sep 02 05:32:14 AM UTC 24 |
Sep 02 05:39:20 AM UTC 24 |
3476461240 ps |
| T1015 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_power_idle_load.2452624496 |
|
|
Sep 02 05:26:08 AM UTC 24 |
Sep 02 05:39:21 AM UTC 24 |
4636563750 ps |
| T1016 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_kmac_smoketest.2030129255 |
|
|
Sep 02 05:34:27 AM UTC 24 |
Sep 02 05:40:06 AM UTC 24 |
3016637440 ps |
| T1017 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_hmac_smoketest.53099272 |
|
|
Sep 02 05:34:05 AM UTC 24 |
Sep 02 05:40:15 AM UTC 24 |
3502056702 ps |
| T1018 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_rv_plic_smoketest.2202525956 |
|
|
Sep 02 05:36:00 AM UTC 24 |
Sep 02 05:41:20 AM UTC 24 |
2390758170 ps |
| T225 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_jtag_mem_access.36686313 |
|
|
Sep 02 05:14:43 AM UTC 24 |
Sep 02 05:41:24 AM UTC 24 |
14273207668 ps |
| T1019 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_example_rom.1159405372 |
|
|
Sep 02 05:38:31 AM UTC 24 |
Sep 02 05:41:27 AM UTC 24 |
2940310614 ps |
| T402 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_pwrmgr_usbdev_smoketest.2422288137 |
|
|
Sep 02 05:35:59 AM UTC 24 |
Sep 02 05:41:41 AM UTC 24 |
4877777800 ps |
| T1020 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_otp_ctrl_smoketest.4275595901 |
|
|
Sep 02 05:35:09 AM UTC 24 |
Sep 02 05:41:58 AM UTC 24 |
3342656732 ps |
| T1021 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_rstmgr_smoketest.2902781017 |
|
|
Sep 02 05:37:31 AM UTC 24 |
Sep 02 05:42:21 AM UTC 24 |
3272981966 ps |
| T1022 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_rv_timer_smoketest.4140471308 |
|
|
Sep 02 05:37:31 AM UTC 24 |
Sep 02 05:42:29 AM UTC 24 |
2657940708 ps |
| T347 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_pattgen_ios.3270991291 |
|
|
Sep 02 05:43:29 AM UTC 24 |
Sep 02 05:49:27 AM UTC 24 |
2566985600 ps |
| T1023 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_uart_smoketest.1651071692 |
|
|
Sep 02 05:38:22 AM UTC 24 |
Sep 02 05:42:48 AM UTC 24 |
2868780310 ps |
| T1024 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_sram_ctrl_smoketest.3835979430 |
|
|
Sep 02 05:37:36 AM UTC 24 |
Sep 02 05:43:16 AM UTC 24 |
2804334616 ps |
| T1025 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_example_flash.1454005062 |
|
|
Sep 02 05:38:31 AM UTC 24 |
Sep 02 05:43:19 AM UTC 24 |
2392697392 ps |
| T1026 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_example_concurrency.2091623050 |
|
|
Sep 02 05:38:58 AM UTC 24 |
Sep 02 05:44:24 AM UTC 24 |
3105711102 ps |
| T1027 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/1.rom_keymgr_functest.2289352748 |
|
|
Sep 02 05:31:59 AM UTC 24 |
Sep 02 05:44:24 AM UTC 24 |
5204737940 ps |
| T1028 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sival_flash_info_access.817883674 |
|
|
Sep 02 05:39:34 AM UTC 24 |
Sep 02 05:44:27 AM UTC 24 |
2864234440 ps |
| T241 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_keymgr_sideload_aes.2783205504 |
|
|
Sep 02 04:58:51 AM UTC 24 |
Sep 02 05:44:30 AM UTC 24 |
11874432650 ps |
| T1029 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/0.rom_e2e_boot_policy_valid_a_bad_b_good_prod.4222580805 |
|
|
Sep 02 03:08:02 AM UTC 24 |
Sep 02 05:44:35 AM UTC 24 |
24494947990 ps |
| T1030 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/0.rom_e2e_boot_policy_valid_a_bad_b_good_prod_end.3566042770 |
|
|
Sep 02 03:09:37 AM UTC 24 |
Sep 02 05:44:40 AM UTC 24 |
24457416170 ps |
| T409 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_pwrmgr_deep_sleep_all_wake_ups.2846689218 |
|
|
Sep 02 05:16:19 AM UTC 24 |
Sep 02 05:44:56 AM UTC 24 |
22790604568 ps |
| T1031 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_example_manufacturer.2516108120 |
|
|
Sep 02 05:38:47 AM UTC 24 |
Sep 02 05:44:58 AM UTC 24 |
2980871600 ps |
| T1032 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_flash_ctrl_access_jitter_en_reduced_freq.2673923304 |
|
|
Sep 02 05:25:05 AM UTC 24 |
Sep 02 05:45:55 AM UTC 24 |
7237040803 ps |
| T1033 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_sysrst_ctrl_ec_rst_l.3605907484 |
|
|
Sep 02 04:40:17 AM UTC 24 |
Sep 02 05:46:04 AM UTC 24 |
20075050550 ps |
| T1034 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_pwrmgr_smoketest.2019975811 |
|
|
Sep 02 05:36:00 AM UTC 24 |
Sep 02 05:46:18 AM UTC 24 |
6713991572 ps |
| T36 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_sleep_pin_mio_dio_val.1065339125 |
|
|
Sep 02 05:40:57 AM UTC 24 |
Sep 02 05:47:19 AM UTC 24 |
3555210120 ps |
| T1035 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_flash_ctrl_mem_protection.3730844633 |
|
|
Sep 02 05:28:47 AM UTC 24 |
Sep 02 05:47:27 AM UTC 24 |
5670177890 ps |
| T124 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_pwrmgr_random_sleep_all_wake_ups.1877213274 |
|
|
Sep 02 05:16:36 AM UTC 24 |
Sep 02 05:48:01 AM UTC 24 |
24673593384 ps |
| T77 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_sleep_pin_retention.2198363878 |
|
|
Sep 02 05:42:44 AM UTC 24 |
Sep 02 05:48:29 AM UTC 24 |
4835492304 ps |
| T1036 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_keymgr_key_derivation_jitter_en.2574446372 |
|
|
Sep 02 04:59:05 AM UTC 24 |
Sep 02 05:48:53 AM UTC 24 |
12704319910 ps |
| T1037 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_keymgr_sideload_kmac.1505823240 |
|
|
Sep 02 04:59:03 AM UTC 24 |
Sep 02 05:51:02 AM UTC 24 |
12600909656 ps |
| T259 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_all_escalation_resets.2322381751 |
|
|
Sep 02 05:40:11 AM UTC 24 |
Sep 02 05:51:08 AM UTC 24 |
4667883464 ps |
| T1038 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_rstmgr_rst_cnsty_escalation.702698732 |
|
|
Sep 02 05:40:12 AM UTC 24 |
Sep 02 05:51:35 AM UTC 24 |
6046041132 ps |
| T68 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_power_virus.2089294104 |
|
|
Sep 02 05:26:43 AM UTC 24 |
Sep 02 05:52:28 AM UTC 24 |
6127121892 ps |
| T79 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_spi_device_pinmux_sleep_retention.389007903 |
|
|
Sep 02 05:46:56 AM UTC 24 |
Sep 02 05:53:00 AM UTC 24 |
4158815991 ps |
| T1039 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_pwrmgr_b2b_sleep_reset_req.219958788 |
|
|
Sep 02 05:04:17 AM UTC 24 |
Sep 02 05:53:13 AM UTC 24 |
26350758165 ps |
| T1040 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_uart_tx_rx_idx1.4260213292 |
|
|
Sep 02 05:43:27 AM UTC 24 |
Sep 02 05:53:19 AM UTC 24 |
3792661144 ps |