Tests
dashboard | hierarchy | modlist | groups | tests | asserts
Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
96.05 95.46 93.77 95.47 94.50 97.53 99.58


Total test records in report: 2919
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html | tests10.html | tests11.html | tests12.html | tests13.html | tests14.html | tests15.html | tests16.html | tests17.html | tests18.html | tests19.html | tests20.html | tests21.html | tests22.html | tests23.html | tests24.html | tests25.html | tests26.html | tests27.html | tests28.html | tests29.html | tests30.html | tests31.html | tests32.html | tests33.html | tests34.html | tests35.html | tests36.html | tests37.html | tests38.html | tests39.html | tests40.html | tests41.html | tests42.html | tests43.html | tests44.html | tests45.html | tests46.html | tests47.html | tests48.html | tests49.html | tests50.html | tests51.html | tests52.html | tests53.html | tests54.html | tests55.html | tests56.html | tests57.html | tests58.html | tests59.html | tests60.html | tests61.html
T2018 /workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/51.xbar_stress_all_with_rand_reset.2743468346 Sep 02 01:01:04 AM UTC 24 Sep 02 01:02:36 AM UTC 24 275835803 ps
T2019 /workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/52.xbar_access_same_device.2512329838 Sep 02 01:02:06 AM UTC 24 Sep 02 01:02:37 AM UTC 24 222435735 ps
T2020 /workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/52.xbar_error_random.3382226129 Sep 02 01:02:24 AM UTC 24 Sep 02 01:02:48 AM UTC 24 183286764 ps
T2021 /workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/53.xbar_smoke_zero_delays.1557852560 Sep 02 01:02:56 AM UTC 24 Sep 02 01:03:06 AM UTC 24 42734404 ps
T2022 /workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/37.xbar_random_large_delays.237962044 Sep 02 12:42:35 AM UTC 24 Sep 02 01:03:08 AM UTC 24 104262348887 ps
T2023 /workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/53.xbar_random.107641307 Sep 02 01:02:59 AM UTC 24 Sep 02 01:03:09 AM UTC 24 30008788 ps
T2024 /workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/53.xbar_smoke.226567974 Sep 02 01:02:56 AM UTC 24 Sep 02 01:03:12 AM UTC 24 233530406 ps
T826 /workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/40.xbar_stress_all_with_reset_error.821819684 Sep 02 12:46:43 AM UTC 24 Sep 02 01:03:15 AM UTC 24 18161284149 ps
T2025 /workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/52.xbar_smoke_large_delays.4078205323 Sep 02 01:01:30 AM UTC 24 Sep 02 01:03:17 AM UTC 24 9762440339 ps
T2026 /workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/52.xbar_unmapped_addr.4089185966 Sep 02 01:02:28 AM UTC 24 Sep 02 01:03:18 AM UTC 24 299985966 ps
T2027 /workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/52.xbar_smoke_slow_rsp.2784860009 Sep 02 01:01:47 AM UTC 24 Sep 02 01:03:20 AM UTC 24 4195458471 ps
T2028 /workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/35.xbar_random_large_delays.1193213209 Sep 02 12:39:58 AM UTC 24 Sep 02 01:03:23 AM UTC 24 105373569797 ps
T2029 /workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/52.xbar_error_and_unmapped_addr.475665283 Sep 02 01:02:29 AM UTC 24 Sep 02 01:03:25 AM UTC 24 1081365148 ps
T2030 /workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/52.xbar_stress_all_with_reset_error.3734908617 Sep 02 01:02:51 AM UTC 24 Sep 02 01:03:34 AM UTC 24 55882846 ps
T2031 /workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/30.xbar_access_same_device_slow_rsp.1127195800 Sep 02 12:34:36 AM UTC 24 Sep 02 01:03:43 AM UTC 24 101253605081 ps
T2032 /workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/53.xbar_unmapped_addr.2448034222 Sep 02 01:03:39 AM UTC 24 Sep 02 01:03:50 AM UTC 24 64912077 ps
T2033 /workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/53.xbar_error_and_unmapped_addr.1906466280 Sep 02 01:03:41 AM UTC 24 Sep 02 01:04:04 AM UTC 24 168371661 ps
T2034 /workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/50.xbar_stress_all_with_rand_reset.256361539 Sep 02 12:59:53 AM UTC 24 Sep 02 01:04:06 AM UTC 24 1336187716 ps
T2035 /workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/47.xbar_random_large_delays.55720469 Sep 02 12:55:27 AM UTC 24 Sep 02 01:04:07 AM UTC 24 47531493502 ps
T2036 /workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/46.xbar_stress_all.3672340430 Sep 02 12:54:51 AM UTC 24 Sep 02 01:04:08 AM UTC 24 12264640651 ps
T2037 /workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/53.xbar_random_zero_delays.1113303906 Sep 02 01:03:00 AM UTC 24 Sep 02 01:04:11 AM UTC 24 568376427 ps
T2038 /workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/53.xbar_same_source.1993446364 Sep 02 01:03:35 AM UTC 24 Sep 02 01:04:21 AM UTC 24 1056128012 ps
T2039 /workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/54.xbar_smoke.3853196589 Sep 02 01:04:07 AM UTC 24 Sep 02 01:04:21 AM UTC 24 209092378 ps
T2040 /workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/54.xbar_smoke_zero_delays.2052277327 Sep 02 01:04:12 AM UTC 24 Sep 02 01:04:23 AM UTC 24 53514156 ps
T2041 /workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/48.xbar_random_large_delays.3587191059 Sep 02 12:56:42 AM UTC 24 Sep 02 01:04:25 AM UTC 24 42937132479 ps
T2042 /workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/53.xbar_error_random.3241713399 Sep 02 01:03:39 AM UTC 24 Sep 02 01:04:32 AM UTC 24 475568473 ps
T2043 /workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/52.xbar_stress_all_with_rand_reset.1818121819 Sep 02 01:02:48 AM UTC 24 Sep 02 01:04:37 AM UTC 24 413983318 ps
T2044 /workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/48.xbar_random_slow_rsp.4156119599 Sep 02 12:56:39 AM UTC 24 Sep 02 01:04:38 AM UTC 24 28663074085 ps
T2045 /workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/25.xbar_access_same_device_slow_rsp.1720836967 Sep 02 12:25:12 AM UTC 24 Sep 02 01:04:39 AM UTC 24 141850163124 ps
T2046 /workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/52.xbar_stress_all_with_error.2343458232 Sep 02 01:02:51 AM UTC 24 Sep 02 01:04:45 AM UTC 24 3202148061 ps
T2047 /workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/51.xbar_stress_all.2069265907 Sep 02 01:01:04 AM UTC 24 Sep 02 01:04:46 AM UTC 24 2178756257 ps
T2048 /workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/53.xbar_smoke_large_delays.3115100460 Sep 02 01:02:57 AM UTC 24 Sep 02 01:05:06 AM UTC 24 9595014392 ps
T2049 /workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/53.xbar_access_same_device.743119242 Sep 02 01:03:31 AM UTC 24 Sep 02 01:05:06 AM UTC 24 994206164 ps
T2050 /workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/54.xbar_random.2834432281 Sep 02 01:04:29 AM UTC 24 Sep 02 01:05:10 AM UTC 24 423870532 ps
T2051 /workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/54.xbar_error_random.603794065 Sep 02 01:04:54 AM UTC 24 Sep 02 01:05:11 AM UTC 24 246432287 ps
T2052 /workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/53.xbar_smoke_slow_rsp.2064593460 Sep 02 01:02:57 AM UTC 24 Sep 02 01:05:14 AM UTC 24 5911175642 ps
T2053 /workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/54.xbar_same_source.2374340607 Sep 02 01:04:43 AM UTC 24 Sep 02 01:05:15 AM UTC 24 702660820 ps
T2054 /workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/45.xbar_random_slow_rsp.2244787270 Sep 02 12:53:15 AM UTC 24 Sep 02 01:05:18 AM UTC 24 41566388967 ps
T2055 /workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/43.xbar_random_large_delays.3150900525 Sep 02 12:50:04 AM UTC 24 Sep 02 01:05:19 AM UTC 24 78955523574 ps
T2056 /workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/54.xbar_unmapped_addr.3140121841 Sep 02 01:04:59 AM UTC 24 Sep 02 01:05:21 AM UTC 24 283931199 ps
T2057 /workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/53.xbar_stress_all_with_reset_error.2980988246 Sep 02 01:03:56 AM UTC 24 Sep 02 01:05:23 AM UTC 24 162698290 ps
T2058 /workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/54.xbar_random_zero_delays.4275679934 Sep 02 01:04:32 AM UTC 24 Sep 02 01:05:28 AM UTC 24 488068249 ps
T2059 /workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/52.xbar_random_large_delays.4033569617 Sep 02 01:02:00 AM UTC 24 Sep 02 01:05:32 AM UTC 24 19812193981 ps
T2060 /workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/54.xbar_error_and_unmapped_addr.2943843320 Sep 02 01:05:02 AM UTC 24 Sep 02 01:05:33 AM UTC 24 183943874 ps
T2061 /workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/49.xbar_random_slow_rsp.2941128768 Sep 02 12:57:54 AM UTC 24 Sep 02 01:05:38 AM UTC 24 28838686786 ps
T2062 /workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/55.xbar_smoke.2946744166 Sep 02 01:05:29 AM UTC 24 Sep 02 01:05:44 AM UTC 24 254486305 ps
T2063 /workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/55.xbar_smoke_zero_delays.973395370 Sep 02 01:05:33 AM UTC 24 Sep 02 01:05:44 AM UTC 24 47494595 ps
T2064 /workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/50.xbar_stress_all_with_reset_error.2847495516 Sep 02 01:00:01 AM UTC 24 Sep 02 01:05:47 AM UTC 24 1643804797 ps
T2065 /workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/47.xbar_random_slow_rsp.3894393510 Sep 02 12:55:29 AM UTC 24 Sep 02 01:05:54 AM UTC 24 35159216962 ps
T2066 /workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/54.xbar_access_same_device.1642349206 Sep 02 01:04:44 AM UTC 24 Sep 02 01:05:56 AM UTC 24 1218162661 ps
T2067 /workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/54.xbar_stress_all_with_rand_reset.3224537175 Sep 02 01:05:08 AM UTC 24 Sep 02 01:06:03 AM UTC 24 90612318 ps
T2068 /workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/45.xbar_stress_all_with_reset_error.1150541462 Sep 02 12:53:44 AM UTC 24 Sep 02 01:06:06 AM UTC 24 5979767377 ps
T2069 /workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/55.xbar_same_source.2554344504 Sep 02 01:05:55 AM UTC 24 Sep 02 01:06:20 AM UTC 24 190070876 ps
T2070 /workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/55.xbar_error_random.3273016837 Sep 02 01:05:56 AM UTC 24 Sep 02 01:06:21 AM UTC 24 173136589 ps
T2071 /workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/54.xbar_stress_all_with_error.247004007 Sep 02 01:05:08 AM UTC 24 Sep 02 01:06:21 AM UTC 24 1994738061 ps
T2072 /workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/54.xbar_smoke_large_delays.2196145640 Sep 02 01:04:27 AM UTC 24 Sep 02 01:06:31 AM UTC 24 8338613051 ps
T2073 /workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/55.xbar_random_zero_delays.1197863745 Sep 02 01:05:41 AM UTC 24 Sep 02 01:06:31 AM UTC 24 626864010 ps
T2074 /workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/33.xbar_access_same_device_slow_rsp.3641483711 Sep 02 12:37:45 AM UTC 24 Sep 02 01:06:31 AM UTC 24 96005984077 ps
T2075 /workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/50.xbar_random_slow_rsp.2712817934 Sep 02 12:59:25 AM UTC 24 Sep 02 01:06:35 AM UTC 24 21049777385 ps
T2076 /workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/55.xbar_error_and_unmapped_addr.2262704739 Sep 02 01:06:08 AM UTC 24 Sep 02 01:06:36 AM UTC 24 159524815 ps
T2077 /workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/49.xbar_stress_all_with_rand_reset.3126054026 Sep 02 12:58:30 AM UTC 24 Sep 02 01:06:38 AM UTC 24 2968746161 ps
T2078 /workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/55.xbar_random.1783075152 Sep 02 01:05:39 AM UTC 24 Sep 02 01:06:38 AM UTC 24 1297285230 ps
T2079 /workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/56.xbar_smoke_zero_delays.319825714 Sep 02 01:06:28 AM UTC 24 Sep 02 01:06:39 AM UTC 24 55280032 ps
T2080 /workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/56.xbar_smoke.2038364329 Sep 02 01:06:26 AM UTC 24 Sep 02 01:06:42 AM UTC 24 234969361 ps
T2081 /workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/53.xbar_stress_all_with_error.524638429 Sep 02 01:03:47 AM UTC 24 Sep 02 01:06:48 AM UTC 24 4781499734 ps
T2082 /workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/54.xbar_smoke_slow_rsp.3901658006 Sep 02 01:04:30 AM UTC 24 Sep 02 01:06:54 AM UTC 24 6571614005 ps
T2083 /workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/55.xbar_stress_all.3791107020 Sep 02 01:06:08 AM UTC 24 Sep 02 01:06:54 AM UTC 24 362198376 ps
T2084 /workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/54.xbar_stress_all.4011321506 Sep 02 01:05:02 AM UTC 24 Sep 02 01:06:54 AM UTC 24 973947396 ps
T2085 /workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/51.xbar_stress_all_with_reset_error.3907872780 Sep 02 01:01:23 AM UTC 24 Sep 02 01:06:54 AM UTC 24 2328827923 ps
T2086 /workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/55.xbar_smoke_slow_rsp.3017699284 Sep 02 01:05:37 AM UTC 24 Sep 02 01:07:01 AM UTC 24 5761920904 ps
T2087 /workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/55.xbar_stress_all_with_error.2884291681 Sep 02 01:06:18 AM UTC 24 Sep 02 01:07:05 AM UTC 24 506141675 ps
T2088 /workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/50.xbar_stress_all.2131955829 Sep 02 12:59:44 AM UTC 24 Sep 02 01:07:06 AM UTC 24 9014619245 ps
T2089 /workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/56.xbar_random.1550409723 Sep 02 01:06:44 AM UTC 24 Sep 02 01:07:11 AM UTC 24 204567372 ps
T2090 /workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/56.xbar_random_zero_delays.2996903395 Sep 02 01:06:54 AM UTC 24 Sep 02 01:07:12 AM UTC 24 107780464 ps
T2091 /workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/56.xbar_unmapped_addr.2802352317 Sep 02 01:07:00 AM UTC 24 Sep 02 01:07:14 AM UTC 24 71119624 ps
T2092 /workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/55.xbar_unmapped_addr.1763184506 Sep 02 01:06:02 AM UTC 24 Sep 02 01:07:16 AM UTC 24 1270756200 ps
T2093 /workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/46.xbar_stress_all_with_rand_reset.3442846788 Sep 02 12:54:54 AM UTC 24 Sep 02 01:07:17 AM UTC 24 5945262855 ps
T2094 /workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/57.xbar_smoke.1362761142 Sep 02 01:07:18 AM UTC 24 Sep 02 01:07:31 AM UTC 24 193895214 ps
T2095 /workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/57.xbar_smoke_zero_delays.3490217037 Sep 02 01:07:23 AM UTC 24 Sep 02 01:07:33 AM UTC 24 43707203 ps
T2096 /workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/56.xbar_error_and_unmapped_addr.251061343 Sep 02 01:07:03 AM UTC 24 Sep 02 01:07:35 AM UTC 24 223540061 ps
T2097 /workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/56.xbar_access_same_device.3991760154 Sep 02 01:06:58 AM UTC 24 Sep 02 01:07:37 AM UTC 24 249842307 ps
T2098 /workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/57.xbar_random_zero_delays.2566657798 Sep 02 01:07:31 AM UTC 24 Sep 02 01:07:42 AM UTC 24 35725900 ps
T2099 /workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/56.xbar_error_random.1036269723 Sep 02 01:07:00 AM UTC 24 Sep 02 01:07:44 AM UTC 24 383515672 ps
T2100 /workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/56.xbar_same_source.4164857954 Sep 02 01:07:01 AM UTC 24 Sep 02 01:07:59 AM UTC 24 2024383843 ps
T2101 /workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/56.xbar_smoke_large_delays.1216976093 Sep 02 01:06:41 AM UTC 24 Sep 02 01:08:02 AM UTC 24 7411189886 ps
T2102 /workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/53.xbar_stress_all_with_rand_reset.3200466311 Sep 02 01:03:46 AM UTC 24 Sep 02 01:08:07 AM UTC 24 510067949 ps
T2103 /workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/57.xbar_random.4138121006 Sep 02 01:07:34 AM UTC 24 Sep 02 01:08:09 AM UTC 24 260334146 ps
T2104 /workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/55.xbar_smoke_large_delays.3653202084 Sep 02 01:05:35 AM UTC 24 Sep 02 01:08:11 AM UTC 24 9831083665 ps
T2105 /workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/55.xbar_access_same_device.2017608759 Sep 02 01:05:46 AM UTC 24 Sep 02 01:08:12 AM UTC 24 3238776401 ps
T2106 /workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/56.xbar_stress_all_with_rand_reset.370655978 Sep 02 01:07:17 AM UTC 24 Sep 02 01:08:12 AM UTC 24 72119881 ps
T2107 /workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/57.xbar_same_source.1732497250 Sep 02 01:07:57 AM UTC 24 Sep 02 01:08:27 AM UTC 24 584680795 ps
T2108 /workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/13.chip_same_csr_outstanding.3955165374 Sep 01 11:56:24 PM UTC 24 Sep 02 01:08:30 AM UTC 24 29279770064 ps
T2109 /workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/53.xbar_stress_all.2592535372 Sep 02 01:03:42 AM UTC 24 Sep 02 01:08:35 AM UTC 24 6834859068 ps
T2110 /workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/58.xbar_smoke_zero_delays.222172182 Sep 02 01:08:34 AM UTC 24 Sep 02 01:08:44 AM UTC 24 45311319 ps
T2111 /workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/58.xbar_smoke.3112823111 Sep 02 01:08:31 AM UTC 24 Sep 02 01:08:45 AM UTC 24 220234642 ps
T2112 /workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/56.xbar_smoke_slow_rsp.2388177691 Sep 02 01:06:43 AM UTC 24 Sep 02 01:08:47 AM UTC 24 6380153118 ps
T2113 /workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/57.xbar_error_and_unmapped_addr.1713432904 Sep 02 01:08:05 AM UTC 24 Sep 02 01:08:49 AM UTC 24 276852938 ps
T2114 /workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/51.xbar_stress_all_with_error.1893048973 Sep 02 01:01:10 AM UTC 24 Sep 02 01:08:51 AM UTC 24 4807501435 ps
T2115 /workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/49.xbar_stress_all_with_reset_error.1940448610 Sep 02 12:58:31 AM UTC 24 Sep 02 01:08:53 AM UTC 24 12605262310 ps
T2116 /workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/57.xbar_error_random.2966635901 Sep 02 01:07:58 AM UTC 24 Sep 02 01:08:57 AM UTC 24 1248537328 ps
T2117 /workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/54.xbar_random_slow_rsp.859443500 Sep 02 01:04:44 AM UTC 24 Sep 02 01:09:04 AM UTC 24 13543442490 ps
T2118 /workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/57.xbar_unmapped_addr.2816016384 Sep 02 01:08:01 AM UTC 24 Sep 02 01:09:05 AM UTC 24 1103109478 ps
T2119 /workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/57.xbar_access_same_device.1426829481 Sep 02 01:07:41 AM UTC 24 Sep 02 01:09:05 AM UTC 24 1656314802 ps
T2120 /workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/57.xbar_stress_all_with_error.1098340811 Sep 02 01:08:24 AM UTC 24 Sep 02 01:09:06 AM UTC 24 421273907 ps
T2121 /workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/58.xbar_random_zero_delays.256010756 Sep 02 01:08:52 AM UTC 24 Sep 02 01:09:18 AM UTC 24 215319991 ps
T2122 /workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/58.xbar_same_source.1237764334 Sep 02 01:09:10 AM UTC 24 Sep 02 01:09:21 AM UTC 24 57929756 ps
T2123 /workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/57.xbar_smoke_large_delays.649242881 Sep 02 01:07:28 AM UTC 24 Sep 02 01:09:24 AM UTC 24 8980283065 ps
T2124 /workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/58.xbar_random.1861800786 Sep 02 01:08:48 AM UTC 24 Sep 02 01:09:32 AM UTC 24 777912074 ps
T2125 /workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/57.xbar_smoke_slow_rsp.3395397635 Sep 02 01:07:29 AM UTC 24 Sep 02 01:09:34 AM UTC 24 5199993378 ps
T2126 /workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/55.xbar_stress_all_with_reset_error.69135264 Sep 02 01:06:19 AM UTC 24 Sep 02 01:09:35 AM UTC 24 548540710 ps
T2127 /workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/46.xbar_random_slow_rsp.669157153 Sep 02 12:54:23 AM UTC 24 Sep 02 01:09:38 AM UTC 24 59454272829 ps
T2128 /workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/59.xbar_smoke_zero_delays.2262087021 Sep 02 01:09:42 AM UTC 24 Sep 02 01:09:52 AM UTC 24 36589233 ps
T2129 /workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/59.xbar_smoke.603754873 Sep 02 01:09:42 AM UTC 24 Sep 02 01:09:52 AM UTC 24 49991086 ps
T2130 /workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/58.xbar_error_random.3394006504 Sep 02 01:09:14 AM UTC 24 Sep 02 01:10:00 AM UTC 24 388089517 ps
T2131 /workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/58.xbar_error_and_unmapped_addr.3627752087 Sep 02 01:09:21 AM UTC 24 Sep 02 01:10:04 AM UTC 24 740771199 ps
T2132 /workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/48.xbar_access_same_device_slow_rsp.2365094744 Sep 02 12:56:42 AM UTC 24 Sep 02 01:10:05 AM UTC 24 49572096638 ps
T2133 /workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/58.xbar_unmapped_addr.4113763125 Sep 02 01:09:16 AM UTC 24 Sep 02 01:10:09 AM UTC 24 1049343442 ps
T2134 /workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/54.xbar_stress_all_with_reset_error.3335728613 Sep 02 01:05:30 AM UTC 24 Sep 02 01:10:14 AM UTC 24 1939822021 ps
T2135 /workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/58.xbar_smoke_large_delays.393333354 Sep 02 01:08:34 AM UTC 24 Sep 02 01:10:22 AM UTC 24 8141778348 ps
T2136 /workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/58.xbar_smoke_slow_rsp.143597142 Sep 02 01:08:36 AM UTC 24 Sep 02 01:10:28 AM UTC 24 4980846338 ps
T830 /workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/56.xbar_stress_all_with_reset_error.4169656822 Sep 02 01:07:18 AM UTC 24 Sep 02 01:10:36 AM UTC 24 1493324480 ps
T2137 /workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/59.xbar_error_random.1876729670 Sep 02 01:10:29 AM UTC 24 Sep 02 01:10:39 AM UTC 24 40517508 ps
T2138 /workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/54.xbar_random_large_delays.4215357344 Sep 02 01:04:34 AM UTC 24 Sep 02 01:10:45 AM UTC 24 36141872033 ps
T2139 /workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/58.xbar_access_same_device.1841632931 Sep 02 01:09:08 AM UTC 24 Sep 02 01:10:57 AM UTC 24 2623377029 ps
T2140 /workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/59.xbar_error_and_unmapped_addr.640798700 Sep 02 01:10:38 AM UTC 24 Sep 02 01:11:01 AM UTC 24 323921932 ps
T2141 /workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/9.chip_same_csr_outstanding.2771403989 Sep 01 11:46:46 PM UTC 24 Sep 02 01:11:01 AM UTC 24 30980074506 ps
T2142 /workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/59.xbar_random_zero_delays.3118379647 Sep 02 01:09:58 AM UTC 24 Sep 02 01:11:03 AM UTC 24 524409708 ps
T2143 /workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/59.xbar_same_source.1913683681 Sep 02 01:10:27 AM UTC 24 Sep 02 01:11:13 AM UTC 24 569747343 ps
T2144 /workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/60.xbar_smoke.4059696324 Sep 02 01:11:07 AM UTC 24 Sep 02 01:11:18 AM UTC 24 48772248 ps
T2145 /workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/51.xbar_random_slow_rsp.3866610463 Sep 02 01:00:32 AM UTC 24 Sep 02 01:11:19 AM UTC 24 42180727718 ps
T2146 /workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/59.xbar_random.813956887 Sep 02 01:09:58 AM UTC 24 Sep 02 01:11:28 AM UTC 24 1759247504 ps
T2147 /workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/57.xbar_stress_all_with_reset_error.131736010 Sep 02 01:08:30 AM UTC 24 Sep 02 01:11:28 AM UTC 24 655999395 ps
T2148 /workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/60.xbar_smoke_zero_delays.2160379736 Sep 02 01:11:21 AM UTC 24 Sep 02 01:11:33 AM UTC 24 57162940 ps
T2149 /workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/60.xbar_random.2834726797 Sep 02 01:11:23 AM UTC 24 Sep 02 01:11:33 AM UTC 24 68578704 ps
T2150 /workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/57.xbar_stress_all.513132894 Sep 02 01:08:06 AM UTC 24 Sep 02 01:11:36 AM UTC 24 1979897136 ps
T2151 /workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/59.xbar_stress_all_with_rand_reset.3828292157 Sep 02 01:10:51 AM UTC 24 Sep 02 01:11:36 AM UTC 24 59031830 ps
T2152 /workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/53.xbar_random_slow_rsp.905894725 Sep 02 01:03:28 AM UTC 24 Sep 02 01:11:46 AM UTC 24 29228564760 ps
T2153 /workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/59.xbar_smoke_slow_rsp.2327163065 Sep 02 01:09:55 AM UTC 24 Sep 02 01:11:52 AM UTC 24 5374652706 ps
T2154 /workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/59.xbar_unmapped_addr.781809387 Sep 02 01:10:32 AM UTC 24 Sep 02 01:11:53 AM UTC 24 1398901387 ps
T2155 /workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/59.xbar_smoke_large_delays.4124903217 Sep 02 01:09:47 AM UTC 24 Sep 02 01:12:00 AM UTC 24 9776678903 ps
T831 /workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/58.xbar_stress_all_with_reset_error.545774367 Sep 02 01:09:29 AM UTC 24 Sep 02 01:12:03 AM UTC 24 366523992 ps
T2156 /workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/60.xbar_unmapped_addr.720922118 Sep 02 01:12:00 AM UTC 24 Sep 02 01:12:09 AM UTC 24 19619213 ps
T2157 /workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/59.xbar_access_same_device.2805425102 Sep 02 01:10:16 AM UTC 24 Sep 02 01:12:15 AM UTC 24 2529120324 ps
T2158 /workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/60.xbar_same_source.4155782917 Sep 02 01:11:56 AM UTC 24 Sep 02 01:12:18 AM UTC 24 158565215 ps
T2159 /workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/60.xbar_random_zero_delays.1525892530 Sep 02 01:11:34 AM UTC 24 Sep 02 01:12:30 AM UTC 24 455765121 ps
T2160 /workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/58.xbar_stress_all.747852267 Sep 02 01:09:26 AM UTC 24 Sep 02 01:12:33 AM UTC 24 2145280135 ps
T2161 /workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/61.xbar_smoke.3908984395 Sep 02 01:12:26 AM UTC 24 Sep 02 01:12:37 AM UTC 24 174946901 ps
T2162 /workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/61.xbar_smoke_zero_delays.2320993162 Sep 02 01:12:32 AM UTC 24 Sep 02 01:12:42 AM UTC 24 35200340 ps
T2163 /workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/60.xbar_error_and_unmapped_addr.1737550986 Sep 02 01:11:59 AM UTC 24 Sep 02 01:12:42 AM UTC 24 1099391863 ps
T2164 /workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/60.xbar_access_same_device.3083324376 Sep 02 01:11:51 AM UTC 24 Sep 02 01:12:52 AM UTC 24 619807590 ps
T2165 /workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/60.xbar_smoke_slow_rsp.3411776504 Sep 02 01:11:20 AM UTC 24 Sep 02 01:12:53 AM UTC 24 3986909772 ps
T2166 /workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/60.xbar_error_random.2822226608 Sep 02 01:11:57 AM UTC 24 Sep 02 01:12:55 AM UTC 24 478896054 ps
T2167 /workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/57.xbar_stress_all_with_rand_reset.3285104731 Sep 02 01:08:23 AM UTC 24 Sep 02 01:13:08 AM UTC 24 545325387 ps
T2168 /workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/59.xbar_stress_all.1493401157 Sep 02 01:10:45 AM UTC 24 Sep 02 01:13:18 AM UTC 24 3615200915 ps
T2169 /workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/61.xbar_random_zero_delays.406738523 Sep 02 01:12:55 AM UTC 24 Sep 02 01:13:26 AM UTC 24 214420893 ps
T2170 /workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/57.xbar_access_same_device_slow_rsp.1635148534 Sep 02 01:07:54 AM UTC 24 Sep 02 01:13:30 AM UTC 24 19270827334 ps
T2171 /workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/60.xbar_smoke_large_delays.2002763329 Sep 02 01:11:23 AM UTC 24 Sep 02 01:13:47 AM UTC 24 9932981419 ps
T2172 /workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/61.xbar_error_random.1593794499 Sep 02 01:13:18 AM UTC 24 Sep 02 01:13:50 AM UTC 24 363957229 ps
T2173 /workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/61.xbar_error_and_unmapped_addr.3425898394 Sep 02 01:13:42 AM UTC 24 Sep 02 01:13:50 AM UTC 24 22528994 ps
T2174 /workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/42.xbar_access_same_device_slow_rsp.3802521663 Sep 02 12:49:05 AM UTC 24 Sep 02 01:13:56 AM UTC 24 84736437015 ps
T2175 /workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/61.xbar_random.4027652421 Sep 02 01:12:54 AM UTC 24 Sep 02 01:13:57 AM UTC 24 515105713 ps
T2176 /workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/61.xbar_same_source.3885094240 Sep 02 01:13:16 AM UTC 24 Sep 02 01:14:02 AM UTC 24 422877236 ps
T2177 /workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/61.xbar_access_same_device.3817028895 Sep 02 01:13:06 AM UTC 24 Sep 02 01:14:11 AM UTC 24 614376767 ps
T2178 /workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/50.xbar_random_large_delays.2949071996 Sep 02 12:59:14 AM UTC 24 Sep 02 01:14:16 AM UTC 24 78422542244 ps
T2179 /workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/55.xbar_random_large_delays.106429121 Sep 02 01:05:41 AM UTC 24 Sep 02 01:14:17 AM UTC 24 49922121406 ps
T2180 /workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/60.xbar_stress_all_with_reset_error.3650173550 Sep 02 01:12:24 AM UTC 24 Sep 02 01:14:20 AM UTC 24 420591065 ps
T2181 /workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/61.xbar_smoke_slow_rsp.228587866 Sep 02 01:12:41 AM UTC 24 Sep 02 01:14:24 AM UTC 24 5127174075 ps
T2182 /workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/62.xbar_smoke.4179204701 Sep 02 01:14:13 AM UTC 24 Sep 02 01:14:26 AM UTC 24 156208786 ps
T2183 /workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/55.xbar_stress_all_with_rand_reset.3430692645 Sep 02 01:06:11 AM UTC 24 Sep 02 01:14:30 AM UTC 24 6073039204 ps
T2184 /workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/62.xbar_smoke_zero_delays.1392279546 Sep 02 01:14:20 AM UTC 24 Sep 02 01:14:31 AM UTC 24 46092786 ps
T2185 /workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/61.xbar_unmapped_addr.3574764745 Sep 02 01:13:32 AM UTC 24 Sep 02 01:14:39 AM UTC 24 1129232109 ps
T2186 /workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/61.xbar_smoke_large_delays.352267857 Sep 02 01:12:38 AM UTC 24 Sep 02 01:14:43 AM UTC 24 7865042772 ps
T2187 /workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/62.xbar_random.4122760268 Sep 02 01:14:34 AM UTC 24 Sep 02 01:14:47 AM UTC 24 130174997 ps
T2188 /workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/52.xbar_stress_all.1396211149 Sep 02 01:02:32 AM UTC 24 Sep 02 01:14:50 AM UTC 24 15603121696 ps
T2189 /workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/62.xbar_same_source.3580322355 Sep 02 01:14:54 AM UTC 24 Sep 02 01:15:04 AM UTC 24 37719524 ps
T2190 /workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/62.xbar_random_zero_delays.2866244022 Sep 02 01:14:40 AM UTC 24 Sep 02 01:15:08 AM UTC 24 252955769 ps
T2191 /workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/61.xbar_stress_all_with_error.1167831748 Sep 02 01:14:10 AM UTC 24 Sep 02 01:15:13 AM UTC 24 467286381 ps
T2192 /workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/62.xbar_error_random.4221756319 Sep 02 01:14:54 AM UTC 24 Sep 02 01:15:13 AM UTC 24 129797645 ps
T2193 /workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/38.xbar_access_same_device_slow_rsp.1844022044 Sep 02 12:43:55 AM UTC 24 Sep 02 01:15:35 AM UTC 24 115317565540 ps
T2194 /workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/59.xbar_stress_all_with_error.2430242551 Sep 02 01:11:01 AM UTC 24 Sep 02 01:15:43 AM UTC 24 7203549081 ps
T2195 /workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/62.xbar_unmapped_addr.3239953655 Sep 02 01:15:02 AM UTC 24 Sep 02 01:15:43 AM UTC 24 221130422 ps
T2196 /workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/56.xbar_stress_all_with_error.86228232 Sep 02 01:07:16 AM UTC 24 Sep 02 01:15:43 AM UTC 24 15700327183 ps
T2197 /workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/63.xbar_smoke.2044531316 Sep 02 01:15:35 AM UTC 24 Sep 02 01:15:46 AM UTC 24 46558348 ps
T2198 /workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/62.xbar_error_and_unmapped_addr.2777100374 Sep 02 01:15:05 AM UTC 24 Sep 02 01:15:47 AM UTC 24 712643354 ps
T2199 /workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/63.xbar_smoke_zero_delays.1962063826 Sep 02 01:15:35 AM UTC 24 Sep 02 01:15:48 AM UTC 24 60702146 ps
T2200 /workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/61.xbar_stress_all.3435760228 Sep 02 01:13:49 AM UTC 24 Sep 02 01:15:53 AM UTC 24 995109325 ps
T2201 /workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/62.xbar_smoke_large_delays.1602345435 Sep 02 01:14:21 AM UTC 24 Sep 02 01:16:03 AM UTC 24 6538319191 ps
T2202 /workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/56.xbar_stress_all.98597567 Sep 02 01:07:10 AM UTC 24 Sep 02 01:16:04 AM UTC 24 12004653559 ps
T2203 /workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/58.xbar_stress_all_with_error.3141402266 Sep 02 01:09:29 AM UTC 24 Sep 02 01:16:08 AM UTC 24 5313724330 ps
T2204 /workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/62.xbar_access_same_device.3304331997 Sep 02 01:14:48 AM UTC 24 Sep 02 01:16:14 AM UTC 24 763584149 ps
T2205 /workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/62.xbar_smoke_slow_rsp.2181201699 Sep 02 01:14:26 AM UTC 24 Sep 02 01:16:33 AM UTC 24 5403108825 ps
T2206 /workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/0.chip_csr_bit_bash.619573669 Sep 01 11:27:05 PM UTC 24 Sep 02 01:16:34 AM UTC 24 57530664010 ps
T2207 /workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/55.xbar_random_slow_rsp.1641695861 Sep 02 01:05:44 AM UTC 24 Sep 02 01:16:39 AM UTC 24 39110689577 ps
T2208 /workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/63.xbar_error_random.3474157260 Sep 02 01:16:27 AM UTC 24 Sep 02 01:16:42 AM UTC 24 183188804 ps
T2209 /workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/60.xbar_stress_all.4058166378 Sep 02 01:12:10 AM UTC 24 Sep 02 01:16:43 AM UTC 24 6890838497 ps
T2210 /workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/62.xbar_stress_all_with_error.2813294409 Sep 02 01:15:26 AM UTC 24 Sep 02 01:16:53 AM UTC 24 749595231 ps
T2211 /workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/63.xbar_random_zero_delays.3909446062 Sep 02 01:16:04 AM UTC 24 Sep 02 01:16:58 AM UTC 24 417580963 ps
T2212 /workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/63.xbar_unmapped_addr.750461902 Sep 02 01:16:30 AM UTC 24 Sep 02 01:17:09 AM UTC 24 290368083 ps
T2213 /workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/63.xbar_access_same_device.2753955270 Sep 02 01:16:11 AM UTC 24 Sep 02 01:17:12 AM UTC 24 939697938 ps
T2214 /workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/64.xbar_smoke.1549997599 Sep 02 01:17:07 AM UTC 24 Sep 02 01:17:16 AM UTC 24 50523043 ps
T2215 /workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/63.xbar_error_and_unmapped_addr.1002943574 Sep 02 01:16:38 AM UTC 24 Sep 02 01:17:23 AM UTC 24 777516658 ps
T2216 /workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/64.xbar_smoke_zero_delays.1447396639 Sep 02 01:17:16 AM UTC 24 Sep 02 01:17:24 AM UTC 24 45493565 ps
T2217 /workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/51.xbar_access_same_device_slow_rsp.1658823408 Sep 02 01:00:39 AM UTC 24 Sep 02 01:17:26 AM UTC 24 62092161648 ps
T2218 /workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/63.xbar_same_source.160634762 Sep 02 01:16:27 AM UTC 24 Sep 02 01:17:32 AM UTC 24 1643357438 ps
T2219 /workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/63.xbar_random.1253594164 Sep 02 01:16:06 AM UTC 24 Sep 02 01:17:36 AM UTC 24 2508875063 ps
T2220 /workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/15.chip_same_csr_outstanding.1879148398 Sep 02 12:01:59 AM UTC 24 Sep 02 01:17:40 AM UTC 24 31426575109 ps
T2221 /workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/43.xbar_access_same_device_slow_rsp.911559113 Sep 02 12:50:17 AM UTC 24 Sep 02 01:17:42 AM UTC 24 112493189099 ps
T2222 /workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/62.xbar_stress_all.1886357244 Sep 02 01:15:11 AM UTC 24 Sep 02 01:17:43 AM UTC 24 1827253538 ps
T2223 /workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/64.xbar_random.947828449 Sep 02 01:17:36 AM UTC 24 Sep 02 01:17:55 AM UTC 24 118438968 ps
T2224 /workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/63.xbar_smoke_slow_rsp.2310294226 Sep 02 01:16:05 AM UTC 24 Sep 02 01:17:59 AM UTC 24 6157537771 ps
T2225 /workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/64.xbar_unmapped_addr.502758727 Sep 02 01:18:03 AM UTC 24 Sep 02 01:18:16 AM UTC 24 85887310 ps
T2226 /workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/64.xbar_error_and_unmapped_addr.2774400830 Sep 02 01:18:07 AM UTC 24 Sep 02 01:18:17 AM UTC 24 72720505 ps
T2227 /workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/60.xbar_stress_all_with_rand_reset.1002251573 Sep 02 01:12:16 AM UTC 24 Sep 02 01:18:20 AM UTC 24 3582815487 ps
T2228 /workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/64.xbar_same_source.254636316 Sep 02 01:17:58 AM UTC 24 Sep 02 01:18:23 AM UTC 24 195340328 ps
T2229 /workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/39.xbar_access_same_device_slow_rsp.3186411043 Sep 02 12:45:06 AM UTC 24 Sep 02 01:18:30 AM UTC 24 111946193639 ps
T2230 /workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/64.xbar_random_zero_delays.1604159229 Sep 02 01:17:39 AM UTC 24 Sep 02 01:18:30 AM UTC 24 398133719 ps
T2231 /workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/63.xbar_smoke_large_delays.3245836879 Sep 02 01:15:58 AM UTC 24 Sep 02 01:18:38 AM UTC 24 10694388146 ps
T2232 /workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/59.xbar_random_large_delays.940307342 Sep 02 01:10:01 AM UTC 24 Sep 02 01:18:41 AM UTC 24 43765259024 ps
T2233 /workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/64.xbar_smoke_large_delays.699709734 Sep 02 01:17:20 AM UTC 24 Sep 02 01:18:43 AM UTC 24 8435739547 ps
T2234 /workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/57.xbar_random_slow_rsp.3628774274 Sep 02 01:07:38 AM UTC 24 Sep 02 01:18:47 AM UTC 24 43816869770 ps
T2235 /workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/65.xbar_smoke.819329867 Sep 02 01:18:43 AM UTC 24 Sep 02 01:18:53 AM UTC 24 44910185 ps
T2236 /workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/65.xbar_smoke_zero_delays.1544816824 Sep 02 01:18:46 AM UTC 24 Sep 02 01:18:56 AM UTC 24 44594163 ps
T2237 /workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/64.xbar_error_random.2060354900 Sep 02 01:18:04 AM UTC 24 Sep 02 01:19:01 AM UTC 24 543952126 ps
T2238 /workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/64.xbar_random_large_delays.3529002007 Sep 02 01:17:45 AM UTC 24 Sep 02 01:19:11 AM UTC 24 6527427983 ps
T2239 /workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/14.chip_same_csr_outstanding.3872480343 Sep 01 11:58:38 PM UTC 24 Sep 02 01:19:12 AM UTC 24 30969513920 ps
T2240 /workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/65.xbar_random.3355579416 Sep 02 01:19:00 AM UTC 24 Sep 02 01:19:14 AM UTC 24 78002743 ps
T2241 /workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/65.xbar_random_zero_delays.2218426073 Sep 02 01:19:05 AM UTC 24 Sep 02 01:19:15 AM UTC 24 73111169 ps
T2242 /workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/60.xbar_stress_all_with_error.1484351161 Sep 02 01:12:17 AM UTC 24 Sep 02 01:19:18 AM UTC 24 4684257510 ps
T2243 /workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/64.xbar_smoke_slow_rsp.583561099 Sep 02 01:17:31 AM UTC 24 Sep 02 01:19:20 AM UTC 24 4742517728 ps
T2244 /workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/40.xbar_access_same_device_slow_rsp.1034947335 Sep 02 12:46:09 AM UTC 24 Sep 02 01:19:23 AM UTC 24 110384243079 ps
T2245 /workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/63.xbar_stress_all_with_rand_reset.2259305605 Sep 02 01:16:58 AM UTC 24 Sep 02 01:19:37 AM UTC 24 291945618 ps
T2246 /workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/59.xbar_stress_all_with_reset_error.1491063128 Sep 02 01:11:02 AM UTC 24 Sep 02 01:19:37 AM UTC 24 8086314015 ps
T2247 /workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/65.xbar_same_source.4030710364 Sep 02 01:19:25 AM UTC 24 Sep 02 01:19:44 AM UTC 24 125311254 ps
T2248 /workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/65.xbar_error_random.149189839 Sep 02 01:19:36 AM UTC 24 Sep 02 01:19:47 AM UTC 24 115586239 ps
T2249 /workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/60.xbar_random_slow_rsp.3036134463 Sep 02 01:11:43 AM UTC 24 Sep 02 01:19:48 AM UTC 24 29362826951 ps
T2250 /workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/65.xbar_error_and_unmapped_addr.3080706040 Sep 02 01:19:38 AM UTC 24 Sep 02 01:20:05 AM UTC 24 390706957 ps
T2251 /workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/64.xbar_access_same_device.3545369333 Sep 02 01:17:49 AM UTC 24 Sep 02 01:20:07 AM UTC 24 2395018668 ps
T2252 /workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/66.xbar_smoke_zero_delays.2163669032 Sep 02 01:20:02 AM UTC 24 Sep 02 01:20:11 AM UTC 24 38858512 ps
T2253 /workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/66.xbar_smoke.1591307437 Sep 02 01:20:00 AM UTC 24 Sep 02 01:20:17 AM UTC 24 242057274 ps
T2254 /workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/52.xbar_random_slow_rsp.1796962809 Sep 02 01:02:04 AM UTC 24 Sep 02 01:20:43 AM UTC 24 61476521390 ps
T2255 /workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/65.xbar_smoke_slow_rsp.2680321560 Sep 02 01:18:52 AM UTC 24 Sep 02 01:20:43 AM UTC 24 5851324672 ps
T2256 /workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/65.xbar_unmapped_addr.1142315892 Sep 02 01:19:38 AM UTC 24 Sep 02 01:20:46 AM UTC 24 1130239939 ps
T2257 /workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/65.xbar_access_same_device.1117194620 Sep 02 01:19:17 AM UTC 24 Sep 02 01:20:48 AM UTC 24 2260957833 ps
T2258 /workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/56.xbar_random_slow_rsp.2542260905 Sep 02 01:06:54 AM UTC 24 Sep 02 01:20:51 AM UTC 24 48851193429 ps
T2259 /workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/65.xbar_smoke_large_delays.1599601537 Sep 02 01:18:52 AM UTC 24 Sep 02 01:21:07 AM UTC 24 8059969841 ps
T2260 /workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/66.xbar_random_zero_delays.2598018617 Sep 02 01:20:28 AM UTC 24 Sep 02 01:21:07 AM UTC 24 302437762 ps
T2261 /workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/66.xbar_random.2577765688 Sep 02 01:20:12 AM UTC 24 Sep 02 01:21:13 AM UTC 24 1172397556 ps
T2262 /workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/62.xbar_random_slow_rsp.3045266064 Sep 02 01:14:44 AM UTC 24 Sep 02 01:21:13 AM UTC 24 22392492121 ps
T2263 /workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/58.xbar_stress_all_with_rand_reset.386361572 Sep 02 01:09:27 AM UTC 24 Sep 02 01:21:18 AM UTC 24 8329802300 ps
T2264 /workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/65.xbar_stress_all.1124971166 Sep 02 01:19:38 AM UTC 24 Sep 02 01:21:20 AM UTC 24 1153304197 ps
0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%