| T2265 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/66.xbar_error_random.3774552094 |
|
|
Sep 02 01:21:12 AM UTC 24 |
Sep 02 01:21:25 AM UTC 24 |
145066508 ps |
| T2266 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/66.xbar_access_same_device.3988546030 |
|
|
Sep 02 01:20:41 AM UTC 24 |
Sep 02 01:21:30 AM UTC 24 |
371195480 ps |
| T2267 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/66.xbar_error_and_unmapped_addr.2466588329 |
|
|
Sep 02 01:21:14 AM UTC 24 |
Sep 02 01:21:36 AM UTC 24 |
506768144 ps |
| T2268 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/63.xbar_stress_all_with_error.3118021278 |
|
|
Sep 02 01:17:02 AM UTC 24 |
Sep 02 01:21:38 AM UTC 24 |
7065389280 ps |
| T2269 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/65.xbar_random_slow_rsp.1445777200 |
|
|
Sep 02 01:19:09 AM UTC 24 |
Sep 02 01:21:39 AM UTC 24 |
7225157797 ps |
| T2270 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/66.xbar_same_source.2356500862 |
|
|
Sep 02 01:21:06 AM UTC 24 |
Sep 02 01:21:39 AM UTC 24 |
1032949287 ps |
| T2271 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/64.xbar_stress_all_with_error.2218348228 |
|
|
Sep 02 01:18:39 AM UTC 24 |
Sep 02 01:21:49 AM UTC 24 |
2032496929 ps |
| T2272 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/62.xbar_random_large_delays.1299287655 |
|
|
Sep 02 01:14:40 AM UTC 24 |
Sep 02 01:21:50 AM UTC 24 |
34133035344 ps |
| T2273 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/67.xbar_smoke.1628506546 |
|
|
Sep 02 01:21:40 AM UTC 24 |
Sep 02 01:21:50 AM UTC 24 |
42340515 ps |
| T2274 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/66.xbar_unmapped_addr.465454043 |
|
|
Sep 02 01:21:12 AM UTC 24 |
Sep 02 01:21:52 AM UTC 24 |
664325981 ps |
| T2275 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/67.xbar_smoke_zero_delays.3472450264 |
|
|
Sep 02 01:21:41 AM UTC 24 |
Sep 02 01:21:53 AM UTC 24 |
52181508 ps |
| T2276 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/62.xbar_stress_all_with_reset_error.127727772 |
|
|
Sep 02 01:15:28 AM UTC 24 |
Sep 02 01:21:54 AM UTC 24 |
6542045235 ps |
| T2277 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/63.xbar_random_large_delays.3003493854 |
|
|
Sep 02 01:16:09 AM UTC 24 |
Sep 02 01:21:56 AM UTC 24 |
33905905814 ps |
| T2278 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/66.xbar_smoke_slow_rsp.2390615992 |
|
|
Sep 02 01:20:10 AM UTC 24 |
Sep 02 01:22:00 AM UTC 24 |
5810043623 ps |
| T2279 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/64.xbar_stress_all_with_rand_reset.955411724 |
|
|
Sep 02 01:18:22 AM UTC 24 |
Sep 02 01:22:13 AM UTC 24 |
472659539 ps |
| T2280 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/63.xbar_stress_all_with_reset_error.1904891750 |
|
|
Sep 02 01:17:04 AM UTC 24 |
Sep 02 01:22:21 AM UTC 24 |
1898100597 ps |
| T2281 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/66.xbar_smoke_large_delays.2232104003 |
|
|
Sep 02 01:20:07 AM UTC 24 |
Sep 02 01:22:28 AM UTC 24 |
9567228345 ps |
| T2282 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/59.xbar_access_same_device_slow_rsp.2518774314 |
|
|
Sep 02 01:10:24 AM UTC 24 |
Sep 02 01:22:38 AM UTC 24 |
37128565298 ps |
| T2283 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/67.xbar_random_zero_delays.1008502598 |
|
|
Sep 02 01:21:59 AM UTC 24 |
Sep 02 01:22:43 AM UTC 24 |
443197436 ps |
| T2284 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/68.xbar_smoke.2772143354 |
|
|
Sep 02 01:22:51 AM UTC 24 |
Sep 02 01:23:01 AM UTC 24 |
44297239 ps |
| T2285 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/67.xbar_random.987192005 |
|
|
Sep 02 01:21:59 AM UTC 24 |
Sep 02 01:23:03 AM UTC 24 |
1460393123 ps |
| T2286 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/58.xbar_random_large_delays.1329325833 |
|
|
Sep 02 01:08:59 AM UTC 24 |
Sep 02 01:23:03 AM UTC 24 |
62172498944 ps |
| T2287 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/67.xbar_error_random.1985448190 |
|
|
Sep 02 01:22:15 AM UTC 24 |
Sep 02 01:23:07 AM UTC 24 |
582192002 ps |
| T2288 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/67.xbar_unmapped_addr.3107153458 |
|
|
Sep 02 01:22:16 AM UTC 24 |
Sep 02 01:23:08 AM UTC 24 |
892743756 ps |
| T2289 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/67.xbar_error_and_unmapped_addr.2552861635 |
|
|
Sep 02 01:22:19 AM UTC 24 |
Sep 02 01:23:11 AM UTC 24 |
921235068 ps |
| T2290 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/68.xbar_smoke_zero_delays.2022537932 |
|
|
Sep 02 01:23:02 AM UTC 24 |
Sep 02 01:23:13 AM UTC 24 |
46916212 ps |
| T2291 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/34.xbar_access_same_device_slow_rsp.1334428859 |
|
|
Sep 02 12:38:58 AM UTC 24 |
Sep 02 01:23:13 AM UTC 24 |
156931878785 ps |
| T2292 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/65.xbar_stress_all_with_error.979026872 |
|
|
Sep 02 01:19:42 AM UTC 24 |
Sep 02 01:23:13 AM UTC 24 |
5344706468 ps |
| T2293 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/67.xbar_smoke_large_delays.2497908891 |
|
|
Sep 02 01:21:49 AM UTC 24 |
Sep 02 01:23:15 AM UTC 24 |
8723851735 ps |
| T2294 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/67.xbar_same_source.640892657 |
|
|
Sep 02 01:22:16 AM UTC 24 |
Sep 02 01:23:17 AM UTC 24 |
1537247319 ps |
| T2295 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/67.xbar_access_same_device.3168903402 |
|
|
Sep 02 01:22:12 AM UTC 24 |
Sep 02 01:23:23 AM UTC 24 |
620831521 ps |
| T2296 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/68.xbar_random.3461448237 |
|
|
Sep 02 01:23:27 AM UTC 24 |
Sep 02 01:23:40 AM UTC 24 |
67106105 ps |
| T2297 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/65.xbar_random_large_delays.3264356252 |
|
|
Sep 02 01:19:05 AM UTC 24 |
Sep 02 01:23:41 AM UTC 24 |
30930458890 ps |
| T2298 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/67.xbar_smoke_slow_rsp.881807249 |
|
|
Sep 02 01:21:53 AM UTC 24 |
Sep 02 01:23:50 AM UTC 24 |
5901148508 ps |
| T2299 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/36.xbar_access_same_device_slow_rsp.2643939778 |
|
|
Sep 02 12:41:22 AM UTC 24 |
Sep 02 01:23:50 AM UTC 24 |
137703872641 ps |
| T2300 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/68.xbar_error_random.2741753078 |
|
|
Sep 02 01:23:36 AM UTC 24 |
Sep 02 01:23:51 AM UTC 24 |
258939543 ps |
| T839 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/61.xbar_stress_all_with_reset_error.2480249215 |
|
|
Sep 02 01:14:12 AM UTC 24 |
Sep 02 01:23:55 AM UTC 24 |
12324421273 ps |
| T2301 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/68.xbar_same_source.2011800255 |
|
|
Sep 02 01:23:37 AM UTC 24 |
Sep 02 01:23:55 AM UTC 24 |
373894706 ps |
| T2302 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/65.xbar_stress_all_with_rand_reset.3685587917 |
|
|
Sep 02 01:19:42 AM UTC 24 |
Sep 02 01:24:02 AM UTC 24 |
640706688 ps |
| T2303 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/59.xbar_random_slow_rsp.2017076517 |
|
|
Sep 02 01:10:16 AM UTC 24 |
Sep 02 01:24:06 AM UTC 24 |
45263279506 ps |
| T2304 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/68.xbar_unmapped_addr.4050543157 |
|
|
Sep 02 01:23:37 AM UTC 24 |
Sep 02 01:24:08 AM UTC 24 |
465821620 ps |
| T474 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/62.xbar_stress_all_with_rand_reset.51701057 |
|
|
Sep 02 01:15:11 AM UTC 24 |
Sep 02 01:24:12 AM UTC 24 |
7785597460 ps |
| T2305 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/67.xbar_stress_all.3194753247 |
|
|
Sep 02 01:22:19 AM UTC 24 |
Sep 02 01:24:14 AM UTC 24 |
2173703436 ps |
| T2306 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/68.xbar_random_zero_delays.4058680540 |
|
|
Sep 02 01:23:27 AM UTC 24 |
Sep 02 01:24:22 AM UTC 24 |
452946512 ps |
| T2307 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/69.xbar_smoke_zero_delays.3660923163 |
|
|
Sep 02 01:24:13 AM UTC 24 |
Sep 02 01:24:24 AM UTC 24 |
51243609 ps |
| T2308 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/69.xbar_smoke.3734145171 |
|
|
Sep 02 01:24:13 AM UTC 24 |
Sep 02 01:24:24 AM UTC 24 |
217659543 ps |
| T2309 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/67.xbar_stress_all_with_error.3123578911 |
|
|
Sep 02 01:22:34 AM UTC 24 |
Sep 02 01:24:28 AM UTC 24 |
1152061244 ps |
| T2310 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/68.xbar_smoke_slow_rsp.2999032672 |
|
|
Sep 02 01:23:25 AM UTC 24 |
Sep 02 01:24:33 AM UTC 24 |
4173904816 ps |
| T2311 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/68.xbar_error_and_unmapped_addr.398280940 |
|
|
Sep 02 01:23:41 AM UTC 24 |
Sep 02 01:24:33 AM UTC 24 |
1142940429 ps |
| T2312 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/51.xbar_random_large_delays.2521444370 |
|
|
Sep 02 01:00:25 AM UTC 24 |
Sep 02 01:24:38 AM UTC 24 |
103548569162 ps |
| T2313 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/69.xbar_random.3488231311 |
|
|
Sep 02 01:24:25 AM UTC 24 |
Sep 02 01:24:52 AM UTC 24 |
195637104 ps |
| T2314 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/69.xbar_access_same_device.1608331393 |
|
|
Sep 02 01:24:36 AM UTC 24 |
Sep 02 01:24:55 AM UTC 24 |
107860695 ps |
| T2315 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/58.xbar_access_same_device_slow_rsp.107053456 |
|
|
Sep 02 01:09:08 AM UTC 24 |
Sep 02 01:24:59 AM UTC 24 |
56948627660 ps |
| T2316 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/69.xbar_error_random.957991089 |
|
|
Sep 02 01:24:44 AM UTC 24 |
Sep 02 01:25:00 AM UTC 24 |
267573768 ps |
| T2317 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/68.xbar_smoke_large_delays.335242505 |
|
|
Sep 02 01:23:07 AM UTC 24 |
Sep 02 01:25:06 AM UTC 24 |
8734106796 ps |
| T2318 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/46.xbar_access_same_device_slow_rsp.292396732 |
|
|
Sep 02 12:54:24 AM UTC 24 |
Sep 02 01:25:12 AM UTC 24 |
103174945680 ps |
| T2319 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/68.xbar_access_same_device.3452110207 |
|
|
Sep 02 01:23:32 AM UTC 24 |
Sep 02 01:25:18 AM UTC 24 |
2149999365 ps |
| T2320 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/53.xbar_random_large_delays.3449840610 |
|
|
Sep 02 01:03:11 AM UTC 24 |
Sep 02 01:25:25 AM UTC 24 |
101930891899 ps |
| T2321 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/68.xbar_stress_all_with_rand_reset.3796326365 |
|
|
Sep 02 01:24:03 AM UTC 24 |
Sep 02 01:25:27 AM UTC 24 |
128448843 ps |
| T2322 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/69.xbar_unmapped_addr.3523754819 |
|
|
Sep 02 01:24:51 AM UTC 24 |
Sep 02 01:25:27 AM UTC 24 |
673237057 ps |
| T2323 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/69.xbar_same_source.3341882249 |
|
|
Sep 02 01:24:47 AM UTC 24 |
Sep 02 01:25:29 AM UTC 24 |
390530489 ps |
| T2324 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/56.xbar_random_large_delays.3172447162 |
|
|
Sep 02 01:06:53 AM UTC 24 |
Sep 02 01:25:30 AM UTC 24 |
97310651133 ps |
| T2325 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/70.xbar_smoke_zero_delays.464125039 |
|
|
Sep 02 01:25:23 AM UTC 24 |
Sep 02 01:25:32 AM UTC 24 |
36671721 ps |
| T2326 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/70.xbar_smoke.1132160607 |
|
|
Sep 02 01:25:20 AM UTC 24 |
Sep 02 01:25:34 AM UTC 24 |
207272514 ps |
| T2327 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/69.xbar_random_zero_delays.606229975 |
|
|
Sep 02 01:24:28 AM UTC 24 |
Sep 02 01:25:36 AM UTC 24 |
573738058 ps |
| T2328 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/69.xbar_stress_all_with_rand_reset.3813161305 |
|
|
Sep 02 01:25:02 AM UTC 24 |
Sep 02 01:25:50 AM UTC 24 |
113840753 ps |
| T2329 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/69.xbar_smoke_slow_rsp.1719144577 |
|
|
Sep 02 01:24:18 AM UTC 24 |
Sep 02 01:25:52 AM UTC 24 |
4058664678 ps |
| T2330 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/58.xbar_random_slow_rsp.3243580776 |
|
|
Sep 02 01:09:07 AM UTC 24 |
Sep 02 01:25:57 AM UTC 24 |
68667451664 ps |
| T2331 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/70.xbar_same_source.3236608616 |
|
|
Sep 02 01:25:55 AM UTC 24 |
Sep 02 01:26:09 AM UTC 24 |
126025651 ps |
| T2332 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/69.xbar_error_and_unmapped_addr.1587111554 |
|
|
Sep 02 01:24:57 AM UTC 24 |
Sep 02 01:26:12 AM UTC 24 |
1315753492 ps |
| T2333 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/66.xbar_stress_all_with_rand_reset.334491700 |
|
|
Sep 02 01:21:31 AM UTC 24 |
Sep 02 01:26:15 AM UTC 24 |
1387632804 ps |
| T2334 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/69.xbar_smoke_large_delays.2713716490 |
|
|
Sep 02 01:24:19 AM UTC 24 |
Sep 02 01:26:15 AM UTC 24 |
7153220720 ps |
| T2335 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/70.xbar_access_same_device.4193814611 |
|
|
Sep 02 01:25:51 AM UTC 24 |
Sep 02 01:26:17 AM UTC 24 |
196717061 ps |
| T2336 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/70.xbar_error_and_unmapped_addr.3814239201 |
|
|
Sep 02 01:26:10 AM UTC 24 |
Sep 02 01:26:25 AM UTC 24 |
117276985 ps |
| T2337 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/69.xbar_random_slow_rsp.3315569983 |
|
|
Sep 02 01:24:35 AM UTC 24 |
Sep 02 01:26:32 AM UTC 24 |
7213266167 ps |
| T2338 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/70.xbar_random_zero_delays.1789486186 |
|
|
Sep 02 01:25:47 AM UTC 24 |
Sep 02 01:26:39 AM UTC 24 |
430489333 ps |
| T2339 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/50.xbar_access_same_device_slow_rsp.1853475211 |
|
|
Sep 02 12:59:29 AM UTC 24 |
Sep 02 01:26:46 AM UTC 24 |
98390683039 ps |
| T2340 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/71.xbar_smoke_zero_delays.1258318262 |
|
|
Sep 02 01:26:39 AM UTC 24 |
Sep 02 01:26:49 AM UTC 24 |
49873492 ps |
| T2341 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/71.xbar_smoke.4034456356 |
|
|
Sep 02 01:26:38 AM UTC 24 |
Sep 02 01:26:52 AM UTC 24 |
179228379 ps |
| T2342 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/68.xbar_stress_all.3797249449 |
|
|
Sep 02 01:23:45 AM UTC 24 |
Sep 02 01:26:52 AM UTC 24 |
2053608194 ps |
| T2343 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/70.xbar_random.2028080138 |
|
|
Sep 02 01:25:40 AM UTC 24 |
Sep 02 01:26:55 AM UTC 24 |
1466147896 ps |
| T2344 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/70.xbar_unmapped_addr.1666279399 |
|
|
Sep 02 01:26:00 AM UTC 24 |
Sep 02 01:27:03 AM UTC 24 |
1213883367 ps |
| T2345 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/70.xbar_stress_all_with_error.3851291986 |
|
|
Sep 02 01:26:30 AM UTC 24 |
Sep 02 01:27:09 AM UTC 24 |
358498608 ps |
| T2346 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/71.xbar_random_zero_delays.3967370574 |
|
|
Sep 02 01:27:00 AM UTC 24 |
Sep 02 01:27:22 AM UTC 24 |
183230738 ps |
| T2347 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/70.xbar_error_random.2807947386 |
|
|
Sep 02 01:25:58 AM UTC 24 |
Sep 02 01:27:28 AM UTC 24 |
2545150110 ps |
| T2348 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/57.xbar_random_large_delays.4240334524 |
|
|
Sep 02 01:07:33 AM UTC 24 |
Sep 02 01:27:40 AM UTC 24 |
100927730644 ps |
| T2349 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/70.xbar_smoke_slow_rsp.944082341 |
|
|
Sep 02 01:25:34 AM UTC 24 |
Sep 02 01:27:43 AM UTC 24 |
6995913320 ps |
| T2350 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/71.xbar_random.778826767 |
|
|
Sep 02 01:26:55 AM UTC 24 |
Sep 02 01:27:53 AM UTC 24 |
1088844383 ps |
| T2351 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/71.xbar_unmapped_addr.1244431007 |
|
|
Sep 02 01:27:33 AM UTC 24 |
Sep 02 01:28:00 AM UTC 24 |
371960722 ps |
| T2352 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/67.xbar_access_same_device_slow_rsp.1681492641 |
|
|
Sep 02 01:22:15 AM UTC 24 |
Sep 02 01:28:01 AM UTC 24 |
22066324366 ps |
| T2353 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/70.xbar_smoke_large_delays.2612450570 |
|
|
Sep 02 01:25:29 AM UTC 24 |
Sep 02 01:28:04 AM UTC 24 |
9075936236 ps |
| T2354 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/71.xbar_smoke_slow_rsp.1353241118 |
|
|
Sep 02 01:26:49 AM UTC 24 |
Sep 02 01:28:04 AM UTC 24 |
3105130874 ps |
| T2355 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/66.xbar_stress_all_with_reset_error.128304650 |
|
|
Sep 02 01:21:37 AM UTC 24 |
Sep 02 01:28:06 AM UTC 24 |
1972038829 ps |
| T2356 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/69.xbar_stress_all.3845304724 |
|
|
Sep 02 01:24:56 AM UTC 24 |
Sep 02 01:28:11 AM UTC 24 |
4608073162 ps |
| T2357 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/71.xbar_error_and_unmapped_addr.539081476 |
|
|
Sep 02 01:27:45 AM UTC 24 |
Sep 02 01:28:11 AM UTC 24 |
536805960 ps |
| T821 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/65.xbar_stress_all_with_reset_error.718035943 |
|
|
Sep 02 01:19:47 AM UTC 24 |
Sep 02 01:28:15 AM UTC 24 |
10618081469 ps |
| T2358 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/60.xbar_random_large_delays.1337160277 |
|
|
Sep 02 01:11:39 AM UTC 24 |
Sep 02 01:28:16 AM UTC 24 |
99259215865 ps |
| T2359 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/66.xbar_stress_all_with_error.1026759578 |
|
|
Sep 02 01:21:36 AM UTC 24 |
Sep 02 01:28:18 AM UTC 24 |
9709524496 ps |
| T2360 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/53.xbar_access_same_device_slow_rsp.2467991140 |
|
|
Sep 02 01:03:32 AM UTC 24 |
Sep 02 01:28:20 AM UTC 24 |
78068766858 ps |
| T2361 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/61.xbar_random_slow_rsp.2528127541 |
|
|
Sep 02 01:13:04 AM UTC 24 |
Sep 02 01:28:23 AM UTC 24 |
51623424196 ps |
| T2362 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/71.xbar_smoke_large_delays.2915746175 |
|
|
Sep 02 01:26:40 AM UTC 24 |
Sep 02 01:28:26 AM UTC 24 |
7719913069 ps |
| T2363 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/72.xbar_smoke_zero_delays.2781688882 |
|
|
Sep 02 01:28:24 AM UTC 24 |
Sep 02 01:28:34 AM UTC 24 |
41525655 ps |
| T2364 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/71.xbar_same_source.4031401380 |
|
|
Sep 02 01:27:18 AM UTC 24 |
Sep 02 01:28:35 AM UTC 24 |
1718645623 ps |
| T2365 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/72.xbar_smoke.2086974598 |
|
|
Sep 02 01:28:23 AM UTC 24 |
Sep 02 01:28:38 AM UTC 24 |
219504472 ps |
| T2366 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/64.xbar_stress_all_with_reset_error.124795297 |
|
|
Sep 02 01:18:40 AM UTC 24 |
Sep 02 01:28:46 AM UTC 24 |
5373914252 ps |
| T2367 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/71.xbar_error_random.3309932465 |
|
|
Sep 02 01:27:26 AM UTC 24 |
Sep 02 01:28:59 AM UTC 24 |
2757774254 ps |
| T2368 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/72.xbar_error_and_unmapped_addr.1921497389 |
|
|
Sep 02 01:28:55 AM UTC 24 |
Sep 02 01:29:10 AM UTC 24 |
72057763 ps |
| T2369 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/55.xbar_access_same_device_slow_rsp.288788062 |
|
|
Sep 02 01:05:50 AM UTC 24 |
Sep 02 01:29:13 AM UTC 24 |
79862516323 ps |
| T2370 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/71.xbar_access_same_device.54552098 |
|
|
Sep 02 01:27:14 AM UTC 24 |
Sep 02 01:29:14 AM UTC 24 |
2728386645 ps |
| T2371 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/72.xbar_same_source.2413250823 |
|
|
Sep 02 01:28:41 AM UTC 24 |
Sep 02 01:29:21 AM UTC 24 |
406713812 ps |
| T2372 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/72.xbar_random_zero_delays.3304933624 |
|
|
Sep 02 01:28:34 AM UTC 24 |
Sep 02 01:29:33 AM UTC 24 |
512909228 ps |
| T2373 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/72.xbar_access_same_device.2487655452 |
|
|
Sep 02 01:28:37 AM UTC 24 |
Sep 02 01:29:35 AM UTC 24 |
462821067 ps |
| T2374 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/72.xbar_error_random.3742292917 |
|
|
Sep 02 01:28:47 AM UTC 24 |
Sep 02 01:29:38 AM UTC 24 |
1532039235 ps |
| T2375 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/73.xbar_smoke_zero_delays.1855684200 |
|
|
Sep 02 01:29:36 AM UTC 24 |
Sep 02 01:29:45 AM UTC 24 |
43070636 ps |
| T2376 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/73.xbar_smoke.853392304 |
|
|
Sep 02 01:29:34 AM UTC 24 |
Sep 02 01:29:48 AM UTC 24 |
193990515 ps |
| T2377 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/69.xbar_stress_all_with_error.1572656802 |
|
|
Sep 02 01:25:15 AM UTC 24 |
Sep 02 01:29:49 AM UTC 24 |
7087375130 ps |
| T2378 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/72.xbar_unmapped_addr.3053730503 |
|
|
Sep 02 01:28:50 AM UTC 24 |
Sep 02 01:30:02 AM UTC 24 |
1192699109 ps |
| T2379 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/64.xbar_random_slow_rsp.2099061624 |
|
|
Sep 02 01:17:47 AM UTC 24 |
Sep 02 01:30:04 AM UTC 24 |
39399671244 ps |
| T2380 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/72.xbar_stress_all_with_rand_reset.2922162111 |
|
|
Sep 02 01:29:00 AM UTC 24 |
Sep 02 01:30:05 AM UTC 24 |
110517552 ps |
| T2381 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/73.xbar_random.3176257796 |
|
|
Sep 02 01:29:56 AM UTC 24 |
Sep 02 01:30:10 AM UTC 24 |
101130189 ps |
| T2382 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/66.xbar_random_slow_rsp.3329383446 |
|
|
Sep 02 01:20:32 AM UTC 24 |
Sep 02 01:30:14 AM UTC 24 |
36491592057 ps |
| T2383 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/72.xbar_random.392249604 |
|
|
Sep 02 01:28:29 AM UTC 24 |
Sep 02 01:30:16 AM UTC 24 |
2128117242 ps |
| T2384 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/72.xbar_smoke_large_delays.964796336 |
|
|
Sep 02 01:28:26 AM UTC 24 |
Sep 02 01:30:18 AM UTC 24 |
8573952696 ps |
| T2385 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/72.xbar_smoke_slow_rsp.3049825101 |
|
|
Sep 02 01:28:25 AM UTC 24 |
Sep 02 01:30:19 AM UTC 24 |
4930458977 ps |
| T2386 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/66.xbar_stress_all.3873228122 |
|
|
Sep 02 01:21:25 AM UTC 24 |
Sep 02 01:30:22 AM UTC 24 |
12696840676 ps |
| T2387 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/70.xbar_stress_all.2591445784 |
|
|
Sep 02 01:26:15 AM UTC 24 |
Sep 02 01:30:24 AM UTC 24 |
2686792337 ps |
| T2388 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/70.xbar_random_large_delays.2749010619 |
|
|
Sep 02 01:25:51 AM UTC 24 |
Sep 02 01:30:24 AM UTC 24 |
18328541537 ps |
| T2389 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/73.xbar_random_zero_delays.2888727284 |
|
|
Sep 02 01:29:58 AM UTC 24 |
Sep 02 01:30:43 AM UTC 24 |
345044833 ps |
| T2390 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/63.xbar_stress_all.2412869149 |
|
|
Sep 02 01:16:57 AM UTC 24 |
Sep 02 01:30:47 AM UTC 24 |
19456426106 ps |
| T2391 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/73.xbar_stress_all_with_error.1810214117 |
|
|
Sep 02 01:30:40 AM UTC 24 |
Sep 02 01:30:50 AM UTC 24 |
40589117 ps |
| T2392 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/71.xbar_stress_all_with_rand_reset.445091624 |
|
|
Sep 02 01:28:02 AM UTC 24 |
Sep 02 01:32:57 AM UTC 24 |
529743561 ps |
| T2393 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/73.xbar_unmapped_addr.1039039318 |
|
|
Sep 02 01:30:27 AM UTC 24 |
Sep 02 01:30:53 AM UTC 24 |
333540564 ps |
| T2394 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/73.xbar_error_random.792818355 |
|
|
Sep 02 01:30:26 AM UTC 24 |
Sep 02 01:30:55 AM UTC 24 |
222355088 ps |
| T2395 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/74.xbar_smoke_zero_delays.1316542321 |
|
|
Sep 02 01:30:47 AM UTC 24 |
Sep 02 01:30:57 AM UTC 24 |
43794114 ps |
| T2396 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/74.xbar_smoke.526593155 |
|
|
Sep 02 01:30:45 AM UTC 24 |
Sep 02 01:30:58 AM UTC 24 |
192633249 ps |
| T2397 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/70.xbar_random_slow_rsp.1717120489 |
|
|
Sep 02 01:25:49 AM UTC 24 |
Sep 02 01:31:09 AM UTC 24 |
15137711182 ps |
| T2398 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/71.xbar_stress_all_with_reset_error.547827858 |
|
|
Sep 02 01:28:16 AM UTC 24 |
Sep 02 01:31:10 AM UTC 24 |
1638468571 ps |
| T2399 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/73.xbar_smoke_slow_rsp.1025694747 |
|
|
Sep 02 01:29:44 AM UTC 24 |
Sep 02 01:31:15 AM UTC 24 |
4965750935 ps |
| T2400 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/74.xbar_random_zero_delays.205608406 |
|
|
Sep 02 01:31:12 AM UTC 24 |
Sep 02 01:31:22 AM UTC 24 |
38256988 ps |
| T2401 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/73.xbar_access_same_device.4218870724 |
|
|
Sep 02 01:30:10 AM UTC 24 |
Sep 02 01:31:26 AM UTC 24 |
1601393410 ps |
| T2402 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/65.xbar_access_same_device_slow_rsp.983252738 |
|
|
Sep 02 01:19:19 AM UTC 24 |
Sep 02 01:31:33 AM UTC 24 |
42595108491 ps |
| T2403 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/73.xbar_smoke_large_delays.3108223605 |
|
|
Sep 02 01:29:37 AM UTC 24 |
Sep 02 01:31:36 AM UTC 24 |
8823350513 ps |
| T2404 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/73.xbar_error_and_unmapped_addr.1762241990 |
|
|
Sep 02 01:30:32 AM UTC 24 |
Sep 02 01:31:38 AM UTC 24 |
1332576242 ps |
| T2405 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/61.xbar_access_same_device_slow_rsp.3460082063 |
|
|
Sep 02 01:13:15 AM UTC 24 |
Sep 02 01:31:40 AM UTC 24 |
62351679917 ps |
| T2406 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/69.xbar_stress_all_with_reset_error.3377164536 |
|
|
Sep 02 01:25:18 AM UTC 24 |
Sep 02 01:31:42 AM UTC 24 |
2843511114 ps |
| T2407 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/73.xbar_same_source.1694363112 |
|
|
Sep 02 01:30:24 AM UTC 24 |
Sep 02 01:31:52 AM UTC 24 |
2394448733 ps |
| T2408 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/74.xbar_same_source.689626504 |
|
|
Sep 02 01:31:31 AM UTC 24 |
Sep 02 01:31:55 AM UTC 24 |
500144390 ps |
| T2409 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/72.xbar_stress_all_with_error.3047881317 |
|
|
Sep 02 01:29:09 AM UTC 24 |
Sep 02 01:31:55 AM UTC 24 |
1824571455 ps |
| T2410 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/70.xbar_stress_all_with_rand_reset.2405557874 |
|
|
Sep 02 01:26:18 AM UTC 24 |
Sep 02 01:31:56 AM UTC 24 |
846322947 ps |
| T2411 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/74.xbar_random.1405524998 |
|
|
Sep 02 01:31:10 AM UTC 24 |
Sep 02 01:31:57 AM UTC 24 |
1153001749 ps |
| T2412 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/74.xbar_error_and_unmapped_addr.682944517 |
|
|
Sep 02 01:31:45 AM UTC 24 |
Sep 02 01:32:12 AM UTC 24 |
411653142 ps |
| T2413 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/75.xbar_smoke_zero_delays.1896972330 |
|
|
Sep 02 01:32:05 AM UTC 24 |
Sep 02 01:32:15 AM UTC 24 |
40298116 ps |
| T2414 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/75.xbar_smoke.3136879925 |
|
|
Sep 02 01:32:02 AM UTC 24 |
Sep 02 01:32:15 AM UTC 24 |
170364380 ps |
| T2415 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/68.xbar_stress_all_with_error.4002525647 |
|
|
Sep 02 01:24:05 AM UTC 24 |
Sep 02 01:32:24 AM UTC 24 |
10699188969 ps |
| T2416 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/71.xbar_stress_all_with_error.3555481253 |
|
|
Sep 02 01:28:07 AM UTC 24 |
Sep 02 01:32:25 AM UTC 24 |
5969947715 ps |
| T2417 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/74.xbar_smoke_large_delays.3154990876 |
|
|
Sep 02 01:30:48 AM UTC 24 |
Sep 02 01:32:25 AM UTC 24 |
7073618302 ps |
| T2418 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/61.xbar_stress_all_with_rand_reset.768477617 |
|
|
Sep 02 01:13:52 AM UTC 24 |
Sep 02 01:32:27 AM UTC 24 |
9317175691 ps |
| T2419 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/64.xbar_stress_all.237728348 |
|
|
Sep 02 01:18:19 AM UTC 24 |
Sep 02 01:32:28 AM UTC 24 |
19281467332 ps |
| T2420 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/75.xbar_random.3544401191 |
|
|
Sep 02 01:32:19 AM UTC 24 |
Sep 02 01:32:31 AM UTC 24 |
109415120 ps |
| T2421 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/74.xbar_unmapped_addr.4092809780 |
|
|
Sep 02 01:31:38 AM UTC 24 |
Sep 02 01:32:32 AM UTC 24 |
358487542 ps |
| T2422 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/63.xbar_random_slow_rsp.2902254488 |
|
|
Sep 02 01:16:10 AM UTC 24 |
Sep 02 01:32:46 AM UTC 24 |
60501501438 ps |
| T2423 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/72.xbar_stress_all.3610529824 |
|
|
Sep 02 01:28:58 AM UTC 24 |
Sep 02 01:32:47 AM UTC 24 |
5687677869 ps |
| T2424 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/74.xbar_smoke_slow_rsp.1970075861 |
|
|
Sep 02 01:31:07 AM UTC 24 |
Sep 02 01:32:57 AM UTC 24 |
5443338159 ps |
| T2425 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/75.xbar_error_random.452463653 |
|
|
Sep 02 01:32:47 AM UTC 24 |
Sep 02 01:32:59 AM UTC 24 |
118111596 ps |
| T2426 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/75.xbar_unmapped_addr.3286645104 |
|
|
Sep 02 01:32:49 AM UTC 24 |
Sep 02 01:33:01 AM UTC 24 |
198061847 ps |
| T2427 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/74.xbar_error_random.4228506058 |
|
|
Sep 02 01:31:34 AM UTC 24 |
Sep 02 01:33:03 AM UTC 24 |
1884516273 ps |
| T2428 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/67.xbar_stress_all_with_reset_error.3383710592 |
|
|
Sep 02 01:22:44 AM UTC 24 |
Sep 02 01:33:06 AM UTC 24 |
6783356553 ps |
| T2429 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/74.xbar_access_same_device.186995441 |
|
|
Sep 02 01:31:17 AM UTC 24 |
Sep 02 01:33:13 AM UTC 24 |
2599866303 ps |
| T2430 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/75.xbar_error_and_unmapped_addr.1618072167 |
|
|
Sep 02 01:32:50 AM UTC 24 |
Sep 02 01:33:18 AM UTC 24 |
214022863 ps |
| T2431 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/66.xbar_random_large_delays.1684066762 |
|
|
Sep 02 01:20:30 AM UTC 24 |
Sep 02 01:33:18 AM UTC 24 |
63638607522 ps |
| T2432 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/61.xbar_random_large_delays.1062084816 |
|
|
Sep 02 01:13:00 AM UTC 24 |
Sep 02 01:33:23 AM UTC 24 |
105555300526 ps |
| T2433 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/76.xbar_smoke.852428732 |
|
|
Sep 02 01:33:10 AM UTC 24 |
Sep 02 01:33:24 AM UTC 24 |
217851443 ps |
| T2434 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/52.xbar_access_same_device_slow_rsp.3217572153 |
|
|
Sep 02 01:02:14 AM UTC 24 |
Sep 02 01:33:27 AM UTC 24 |
109282066300 ps |
| T2435 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/68.xbar_random_slow_rsp.3231203511 |
|
|
Sep 02 01:23:31 AM UTC 24 |
Sep 02 01:33:28 AM UTC 24 |
35300626938 ps |
| T2436 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/75.xbar_random_zero_delays.2816625527 |
|
|
Sep 02 01:32:19 AM UTC 24 |
Sep 02 01:33:29 AM UTC 24 |
590132509 ps |
| T2437 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/76.xbar_smoke_zero_delays.3416186697 |
|
|
Sep 02 01:33:21 AM UTC 24 |
Sep 02 01:33:31 AM UTC 24 |
43132842 ps |
| T2438 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/75.xbar_same_source.1373794175 |
|
|
Sep 02 01:32:49 AM UTC 24 |
Sep 02 01:33:33 AM UTC 24 |
1115432348 ps |
| T2439 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/76.xbar_random.531221968 |
|
|
Sep 02 01:33:23 AM UTC 24 |
Sep 02 01:33:36 AM UTC 24 |
149499600 ps |
| T2440 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/75.xbar_smoke_slow_rsp.247515633 |
|
|
Sep 02 01:32:19 AM UTC 24 |
Sep 02 01:33:44 AM UTC 24 |
4486249102 ps |
| T2441 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/75.xbar_stress_all_with_reset_error.1690945759 |
|
|
Sep 02 01:33:09 AM UTC 24 |
Sep 02 01:33:55 AM UTC 24 |
59562482 ps |
| T2442 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/76.xbar_access_same_device.3644000907 |
|
|
Sep 02 01:33:41 AM UTC 24 |
Sep 02 01:34:12 AM UTC 24 |
194559876 ps |
| T2443 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/77.xbar_smoke.2812190165 |
|
|
Sep 02 01:34:06 AM UTC 24 |
Sep 02 01:34:16 AM UTC 24 |
44288494 ps |
| T2444 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/76.xbar_error_random.1231308185 |
|
|
Sep 02 01:33:47 AM UTC 24 |
Sep 02 01:34:19 AM UTC 24 |
398062834 ps |
| T2445 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/76.xbar_random_zero_delays.2698347467 |
|
|
Sep 02 01:33:25 AM UTC 24 |
Sep 02 01:34:20 AM UTC 24 |
558341204 ps |
| T2446 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/75.xbar_random_slow_rsp.3147135558 |
|
|
Sep 02 01:32:35 AM UTC 24 |
Sep 02 01:34:22 AM UTC 24 |
6366788650 ps |
| T2447 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/84.xbar_random.2735362901 |
|
|
Sep 02 01:43:37 AM UTC 24 |
Sep 02 01:43:47 AM UTC 24 |
24727265 ps |
| T2448 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/75.xbar_smoke_large_delays.4274518199 |
|
|
Sep 02 01:32:15 AM UTC 24 |
Sep 02 01:34:23 AM UTC 24 |
8959586564 ps |
| T2449 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/75.xbar_access_same_device.1046565432 |
|
|
Sep 02 01:32:38 AM UTC 24 |
Sep 02 01:34:23 AM UTC 24 |
1176537276 ps |
| T2450 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/76.xbar_same_source.2586183889 |
|
|
Sep 02 01:33:47 AM UTC 24 |
Sep 02 01:34:27 AM UTC 24 |
876108524 ps |
| T2451 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/67.xbar_random_large_delays.2148639276 |
|
|
Sep 02 01:22:04 AM UTC 24 |
Sep 02 01:34:27 AM UTC 24 |
64780313420 ps |
| T2452 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/77.xbar_smoke_zero_delays.151297341 |
|
|
Sep 02 01:34:18 AM UTC 24 |
Sep 02 01:34:28 AM UTC 24 |
50187980 ps |
| T2453 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/67.xbar_stress_all_with_rand_reset.4048467630 |
|
|
Sep 02 01:22:24 AM UTC 24 |
Sep 02 01:34:29 AM UTC 24 |
4914968799 ps |
| T2454 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/67.xbar_random_slow_rsp.320460958 |
|
|
Sep 02 01:22:03 AM UTC 24 |
Sep 02 01:34:52 AM UTC 24 |
53664540870 ps |
| T2455 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/76.xbar_smoke_large_delays.1390063243 |
|
|
Sep 02 01:33:20 AM UTC 24 |
Sep 02 01:35:00 AM UTC 24 |
7692391641 ps |
| T2456 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/77.xbar_error_random.2539616028 |
|
|
Sep 02 01:34:51 AM UTC 24 |
Sep 02 01:35:01 AM UTC 24 |
35283101 ps |
| T2457 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/76.xbar_unmapped_addr.4228387352 |
|
|
Sep 02 01:33:51 AM UTC 24 |
Sep 02 01:35:05 AM UTC 24 |
1232381416 ps |
| T2458 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/77.xbar_unmapped_addr.3375648197 |
|
|
Sep 02 01:34:53 AM UTC 24 |
Sep 02 01:35:07 AM UTC 24 |
132352566 ps |
| T2459 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/76.xbar_smoke_slow_rsp.1577187189 |
|
|
Sep 02 01:33:23 AM UTC 24 |
Sep 02 01:35:10 AM UTC 24 |
5360397284 ps |
| T2460 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/76.xbar_error_and_unmapped_addr.727080822 |
|
|
Sep 02 01:33:52 AM UTC 24 |
Sep 02 01:35:10 AM UTC 24 |
1331547695 ps |
| T2461 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/49.xbar_access_same_device_slow_rsp.164568008 |
|
|
Sep 02 12:57:55 AM UTC 24 |
Sep 02 01:35:13 AM UTC 24 |
128750016329 ps |
| T2462 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/77.xbar_random.894039190 |
|
|
Sep 02 01:34:43 AM UTC 24 |
Sep 02 01:35:14 AM UTC 24 |
589960281 ps |
| T2463 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/54.xbar_access_same_device_slow_rsp.2867369919 |
|
|
Sep 02 01:04:44 AM UTC 24 |
Sep 02 01:35:19 AM UTC 24 |
101033662035 ps |
| T2464 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/77.xbar_same_source.1063154529 |
|
|
Sep 02 01:34:51 AM UTC 24 |
Sep 02 01:35:32 AM UTC 24 |
948939650 ps |
| T2465 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/74.xbar_stress_all_with_reset_error.2690332472 |
|
|
Sep 02 01:31:58 AM UTC 24 |
Sep 02 01:35:35 AM UTC 24 |
615977661 ps |
| T2466 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/74.xbar_stress_all_with_error.878396790 |
|
|
Sep 02 01:31:59 AM UTC 24 |
Sep 02 01:35:37 AM UTC 24 |
2551063297 ps |
| T2467 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/72.xbar_stress_all_with_reset_error.2672830925 |
|
|
Sep 02 01:29:23 AM UTC 24 |
Sep 02 01:35:40 AM UTC 24 |
1053438055 ps |
| T2468 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/78.xbar_smoke.1664147654 |
|
|
Sep 02 01:35:32 AM UTC 24 |
Sep 02 01:35:41 AM UTC 24 |
49279070 ps |
| T2469 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/78.xbar_smoke_zero_delays.1624590126 |
|
|
Sep 02 01:35:32 AM UTC 24 |
Sep 02 01:35:44 AM UTC 24 |
56863144 ps |
| T2470 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/76.xbar_stress_all_with_error.1358683841 |
|
|
Sep 02 01:33:56 AM UTC 24 |
Sep 02 01:35:51 AM UTC 24 |
3184857538 ps |
| T2471 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/77.xbar_random_zero_delays.3607244026 |
|
|
Sep 02 01:34:44 AM UTC 24 |
Sep 02 01:35:57 AM UTC 24 |
619273638 ps |
| T2472 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/75.xbar_stress_all_with_error.3685837385 |
|
|
Sep 02 01:32:56 AM UTC 24 |
Sep 02 01:35:57 AM UTC 24 |
2383840036 ps |
| T2473 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/78.xbar_random.874600851 |
|
|
Sep 02 01:35:41 AM UTC 24 |
Sep 02 01:36:17 AM UTC 24 |
623029134 ps |
| T2474 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/74.xbar_stress_all_with_rand_reset.583436473 |
|
|
Sep 02 01:31:57 AM UTC 24 |
Sep 02 01:36:22 AM UTC 24 |
489981998 ps |
| T2475 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/77.xbar_error_and_unmapped_addr.142496238 |
|
|
Sep 02 01:35:15 AM UTC 24 |
Sep 02 01:36:23 AM UTC 24 |
1245909926 ps |
| T2476 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/71.xbar_stress_all.2804946680 |
|
|
Sep 02 01:27:50 AM UTC 24 |
Sep 02 01:36:26 AM UTC 24 |
13317215528 ps |
| T2477 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/77.xbar_smoke_slow_rsp.1372803691 |
|
|
Sep 02 01:34:40 AM UTC 24 |
Sep 02 01:36:27 AM UTC 24 |
4675892085 ps |
| T2478 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/70.xbar_stress_all_with_reset_error.3254781784 |
|
|
Sep 02 01:26:35 AM UTC 24 |
Sep 02 01:36:29 AM UTC 24 |
5167459492 ps |
| T2479 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/77.xbar_stress_all.1653426671 |
|
|
Sep 02 01:35:22 AM UTC 24 |
Sep 02 01:36:36 AM UTC 24 |
1538118830 ps |
| T2480 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/76.xbar_stress_all_with_reset_error.3655494312 |
|
|
Sep 02 01:34:01 AM UTC 24 |
Sep 02 01:36:39 AM UTC 24 |
456576900 ps |
| T2481 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/78.xbar_unmapped_addr.1562592202 |
|
|
Sep 02 01:36:20 AM UTC 24 |
Sep 02 01:36:44 AM UTC 24 |
114061760 ps |
| T2482 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/77.xbar_access_same_device.751855993 |
|
|
Sep 02 01:34:47 AM UTC 24 |
Sep 02 01:36:44 AM UTC 24 |
2244756894 ps |
| T2483 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/76.xbar_stress_all_with_rand_reset.1960927089 |
|
|
Sep 02 01:33:54 AM UTC 24 |
Sep 02 01:36:48 AM UTC 24 |
510360815 ps |
| T2484 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/68.xbar_random_large_delays.552156681 |
|
|
Sep 02 01:23:31 AM UTC 24 |
Sep 02 01:36:49 AM UTC 24 |
68512919943 ps |
| T2485 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/77.xbar_smoke_large_delays.1319895836 |
|
|
Sep 02 01:34:35 AM UTC 24 |
Sep 02 01:36:49 AM UTC 24 |
9324906197 ps |
| T2486 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/75.xbar_random_large_delays.1897821264 |
|
|
Sep 02 01:32:20 AM UTC 24 |
Sep 02 01:36:59 AM UTC 24 |
27735273457 ps |
| T2487 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/78.xbar_error_random.2655078419 |
|
|
Sep 02 01:36:14 AM UTC 24 |
Sep 02 01:37:00 AM UTC 24 |
378406653 ps |
| T2488 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/78.xbar_error_and_unmapped_addr.3299524147 |
|
|
Sep 02 01:36:20 AM UTC 24 |
Sep 02 01:37:00 AM UTC 24 |
287910053 ps |
| T2489 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/79.xbar_smoke_zero_delays.2290444186 |
|
|
Sep 02 01:36:51 AM UTC 24 |
Sep 02 01:37:01 AM UTC 24 |
41360616 ps |
| T2490 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/79.xbar_smoke.1214324143 |
|
|
Sep 02 01:36:50 AM UTC 24 |
Sep 02 01:37:03 AM UTC 24 |
150551221 ps |
| T2491 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/78.xbar_same_source.3946797885 |
|
|
Sep 02 01:36:07 AM UTC 24 |
Sep 02 01:37:03 AM UTC 24 |
1508243071 ps |
| T2492 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/78.xbar_random_zero_delays.716516704 |
|
|
Sep 02 01:35:55 AM UTC 24 |
Sep 02 01:37:05 AM UTC 24 |
619904115 ps |
| T2493 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/73.xbar_access_same_device_slow_rsp.2725549662 |
|
|
Sep 02 01:30:12 AM UTC 24 |
Sep 02 01:37:10 AM UTC 24 |
24027177869 ps |
| T2494 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/78.xbar_smoke_large_delays.944234371 |
|
|
Sep 02 01:35:37 AM UTC 24 |
Sep 02 01:37:18 AM UTC 24 |
8382218045 ps |
| T2495 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/79.xbar_random_zero_delays.2523134352 |
|
|
Sep 02 01:37:07 AM UTC 24 |
Sep 02 01:37:24 AM UTC 24 |
100916956 ps |
| T2496 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/79.xbar_same_source.1159773474 |
|
|
Sep 02 01:37:20 AM UTC 24 |
Sep 02 01:37:32 AM UTC 24 |
160836920 ps |
| T2497 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/78.xbar_access_same_device.873826633 |
|
|
Sep 02 01:36:04 AM UTC 24 |
Sep 02 01:37:33 AM UTC 24 |
2145571348 ps |
| T2498 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/79.xbar_random.3156878485 |
|
|
Sep 02 01:37:07 AM UTC 24 |
Sep 02 01:37:33 AM UTC 24 |
428346793 ps |
| T2499 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/79.xbar_error_and_unmapped_addr.3975449211 |
|
|
Sep 02 01:37:25 AM UTC 24 |
Sep 02 01:37:43 AM UTC 24 |
82213863 ps |
| T2500 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/80.xbar_smoke.3413280149 |
|
|
Sep 02 01:37:46 AM UTC 24 |
Sep 02 01:37:55 AM UTC 24 |
37490351 ps |
| T2501 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/79.xbar_access_same_device.1234491379 |
|
|
Sep 02 01:37:11 AM UTC 24 |
Sep 02 01:38:02 AM UTC 24 |
823308527 ps |
| T2502 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/78.xbar_smoke_slow_rsp.4030155192 |
|
|
Sep 02 01:35:38 AM UTC 24 |
Sep 02 01:38:04 AM UTC 24 |
6264878700 ps |
| T2503 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/80.xbar_smoke_zero_delays.2761599287 |
|
|
Sep 02 01:37:55 AM UTC 24 |
Sep 02 01:38:06 AM UTC 24 |
44852216 ps |
| T2504 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/79.xbar_smoke_slow_rsp.111051309 |
|
|
Sep 02 01:37:02 AM UTC 24 |
Sep 02 01:38:10 AM UTC 24 |
4143852608 ps |
| T2505 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/79.xbar_error_random.1627001653 |
|
|
Sep 02 01:37:23 AM UTC 24 |
Sep 02 01:38:20 AM UTC 24 |
1201744070 ps |
| T2506 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/80.xbar_random_zero_delays.258246886 |
|
|
Sep 02 01:38:19 AM UTC 24 |
Sep 02 01:38:29 AM UTC 24 |
32992599 ps |
| T2507 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/79.xbar_unmapped_addr.838921351 |
|
|
Sep 02 01:37:25 AM UTC 24 |
Sep 02 01:38:41 AM UTC 24 |
1299376711 ps |
| T2508 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/76.xbar_stress_all.4037269376 |
|
|
Sep 02 01:33:54 AM UTC 24 |
Sep 02 01:38:44 AM UTC 24 |
3028904418 ps |
| T2509 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/79.xbar_stress_all.848188225 |
|
|
Sep 02 01:37:26 AM UTC 24 |
Sep 02 01:38:52 AM UTC 24 |
786629008 ps |
| T577 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/73.xbar_stress_all_with_reset_error.187035445 |
|
|
Sep 02 01:30:40 AM UTC 24 |
Sep 02 01:39:05 AM UTC 24 |
7546761817 ps |
| T2510 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/79.xbar_smoke_large_delays.1673601174 |
|
|
Sep 02 01:36:58 AM UTC 24 |
Sep 02 01:39:14 AM UTC 24 |
9154963892 ps |