| T1778 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/33.xbar_random_slow_rsp.871779494 |
|
|
Sep 02 12:37:44 AM UTC 24 |
Sep 02 12:44:37 AM UTC 24 |
28626879715 ps |
| T1779 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/38.xbar_stress_all_with_reset_error.2383193999 |
|
|
Sep 02 12:44:21 AM UTC 24 |
Sep 02 12:44:38 AM UTC 24 |
88779513 ps |
| T1780 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/38.xbar_error_and_unmapped_addr.2678602426 |
|
|
Sep 02 12:44:06 AM UTC 24 |
Sep 02 12:44:40 AM UTC 24 |
694836185 ps |
| T1781 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/38.xbar_same_source.2802887024 |
|
|
Sep 02 12:43:54 AM UTC 24 |
Sep 02 12:44:43 AM UTC 24 |
503332875 ps |
| T1782 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/36.xbar_stress_all.1649153865 |
|
|
Sep 02 12:41:32 AM UTC 24 |
Sep 02 12:44:44 AM UTC 24 |
3893861565 ps |
| T1783 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/38.xbar_unmapped_addr.781297197 |
|
|
Sep 02 12:44:06 AM UTC 24 |
Sep 02 12:44:49 AM UTC 24 |
888115274 ps |
| T1784 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/37.xbar_stress_all_with_error.1575903832 |
|
|
Sep 02 12:43:03 AM UTC 24 |
Sep 02 12:44:53 AM UTC 24 |
1017482265 ps |
| T1785 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/38.xbar_access_same_device.1622553057 |
|
|
Sep 02 12:43:52 AM UTC 24 |
Sep 02 12:44:54 AM UTC 24 |
676370465 ps |
| T1786 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/38.xbar_error_random.2105194970 |
|
|
Sep 02 12:44:03 AM UTC 24 |
Sep 02 12:44:56 AM UTC 24 |
1129997253 ps |
| T1787 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/38.xbar_smoke_large_delays.52022537 |
|
|
Sep 02 12:43:23 AM UTC 24 |
Sep 02 12:44:56 AM UTC 24 |
7024981680 ps |
| T1788 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/38.xbar_random_zero_delays.938537492 |
|
|
Sep 02 12:43:42 AM UTC 24 |
Sep 02 12:44:56 AM UTC 24 |
614343295 ps |
| T1789 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/38.xbar_smoke_slow_rsp.1541459089 |
|
|
Sep 02 12:43:28 AM UTC 24 |
Sep 02 12:45:03 AM UTC 24 |
5518062789 ps |
| T1790 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/36.xbar_stress_all_with_error.441690528 |
|
|
Sep 02 12:42:03 AM UTC 24 |
Sep 02 12:45:03 AM UTC 24 |
4783209388 ps |
| T1791 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/38.xbar_stress_all_with_rand_reset.1155281098 |
|
|
Sep 02 12:44:15 AM UTC 24 |
Sep 02 12:45:13 AM UTC 24 |
40627696 ps |
| T1792 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/37.xbar_stress_all.2701682707 |
|
|
Sep 02 12:43:01 AM UTC 24 |
Sep 02 12:45:17 AM UTC 24 |
4193099184 ps |
| T1793 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/35.xbar_stress_all_with_error.4131559815 |
|
|
Sep 02 12:40:33 AM UTC 24 |
Sep 02 12:45:33 AM UTC 24 |
2907928263 ps |
| T1794 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/39.xbar_random_zero_delays.1570817910 |
|
|
Sep 02 12:45:01 AM UTC 24 |
Sep 02 12:45:35 AM UTC 24 |
235580683 ps |
| T1795 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/38.xbar_stress_all.694533290 |
|
|
Sep 02 12:44:09 AM UTC 24 |
Sep 02 12:45:38 AM UTC 24 |
775097808 ps |
| T1796 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/39.xbar_random.1088764371 |
|
|
Sep 02 12:45:00 AM UTC 24 |
Sep 02 12:45:40 AM UTC 24 |
738164568 ps |
| T1797 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/37.xbar_random_slow_rsp.4067276427 |
|
|
Sep 02 12:42:34 AM UTC 24 |
Sep 02 12:45:44 AM UTC 24 |
12774667449 ps |
| T504 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/35.xbar_stress_all.3693307795 |
|
|
Sep 02 12:40:22 AM UTC 24 |
Sep 02 12:45:45 AM UTC 24 |
7405340967 ps |
| T1798 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/40.xbar_smoke.231638363 |
|
|
Sep 02 12:45:34 AM UTC 24 |
Sep 02 12:45:45 AM UTC 24 |
50807435 ps |
| T1799 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/39.xbar_same_source.729709160 |
|
|
Sep 02 12:45:11 AM UTC 24 |
Sep 02 12:45:47 AM UTC 24 |
1267798491 ps |
| T1800 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/39.xbar_unmapped_addr.3500608222 |
|
|
Sep 02 12:45:16 AM UTC 24 |
Sep 02 12:45:49 AM UTC 24 |
607589442 ps |
| T1801 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/40.xbar_smoke_zero_delays.3376940950 |
|
|
Sep 02 12:45:40 AM UTC 24 |
Sep 02 12:45:50 AM UTC 24 |
49704815 ps |
| T769 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/14.xbar_access_same_device_slow_rsp.186320282 |
|
|
Sep 02 12:00:28 AM UTC 24 |
Sep 02 12:46:08 AM UTC 24 |
158698452476 ps |
| T1802 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/39.xbar_error_and_unmapped_addr.752872762 |
|
|
Sep 02 12:45:17 AM UTC 24 |
Sep 02 12:46:08 AM UTC 24 |
328179861 ps |
| T1803 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/39.xbar_smoke_large_delays.2012824652 |
|
|
Sep 02 12:44:39 AM UTC 24 |
Sep 02 12:46:08 AM UTC 24 |
8425412806 ps |
| T1804 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/36.xbar_stress_all_with_rand_reset.2819140996 |
|
|
Sep 02 12:42:03 AM UTC 24 |
Sep 02 12:46:14 AM UTC 24 |
673010776 ps |
| T1805 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/39.xbar_error_random.3538573056 |
|
|
Sep 02 12:45:14 AM UTC 24 |
Sep 02 12:46:16 AM UTC 24 |
1433391768 ps |
| T1806 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/39.xbar_stress_all_with_rand_reset.262350934 |
|
|
Sep 02 12:45:16 AM UTC 24 |
Sep 02 12:46:19 AM UTC 24 |
43454578 ps |
| T1807 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/39.xbar_smoke_slow_rsp.2021276201 |
|
|
Sep 02 12:44:55 AM UTC 24 |
Sep 02 12:46:31 AM UTC 24 |
6092364773 ps |
| T1808 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/40.xbar_random_zero_delays.3530907802 |
|
|
Sep 02 12:46:02 AM UTC 24 |
Sep 02 12:46:37 AM UTC 24 |
348524680 ps |
| T1809 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/40.xbar_unmapped_addr.272742889 |
|
|
Sep 02 12:46:31 AM UTC 24 |
Sep 02 12:46:41 AM UTC 24 |
56853563 ps |
| T1810 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/40.xbar_error_and_unmapped_addr.465930968 |
|
|
Sep 02 12:46:31 AM UTC 24 |
Sep 02 12:46:43 AM UTC 24 |
209982473 ps |
| T1811 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/40.xbar_access_same_device.2115461984 |
|
|
Sep 02 12:46:09 AM UTC 24 |
Sep 02 12:46:46 AM UTC 24 |
303399386 ps |
| T1812 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/39.xbar_access_same_device.2900890311 |
|
|
Sep 02 12:45:06 AM UTC 24 |
Sep 02 12:46:47 AM UTC 24 |
2173077509 ps |
| T1813 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/40.xbar_stress_all_with_rand_reset.1337392504 |
|
|
Sep 02 12:46:37 AM UTC 24 |
Sep 02 12:46:51 AM UTC 24 |
46986423 ps |
| T435 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/17.chip_same_csr_outstanding.401295911 |
|
|
Sep 02 12:07:48 AM UTC 24 |
Sep 02 12:46:53 AM UTC 24 |
16757714496 ps |
| T1814 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/35.xbar_access_same_device_slow_rsp.2437976935 |
|
|
Sep 02 12:40:04 AM UTC 24 |
Sep 02 12:46:55 AM UTC 24 |
27177071893 ps |
| T1815 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/40.xbar_same_source.1314388594 |
|
|
Sep 02 12:46:13 AM UTC 24 |
Sep 02 12:46:57 AM UTC 24 |
1087810999 ps |
| T1816 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/41.xbar_smoke.1330124219 |
|
|
Sep 02 12:46:54 AM UTC 24 |
Sep 02 12:47:05 AM UTC 24 |
201392414 ps |
| T1817 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/41.xbar_smoke_zero_delays.1674798456 |
|
|
Sep 02 12:46:59 AM UTC 24 |
Sep 02 12:47:10 AM UTC 24 |
43617041 ps |
| T491 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/39.xbar_stress_all.2203562284 |
|
|
Sep 02 12:45:18 AM UTC 24 |
Sep 02 12:47:18 AM UTC 24 |
1314172242 ps |
| T1818 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/38.xbar_random_large_delays.2153472423 |
|
|
Sep 02 12:43:47 AM UTC 24 |
Sep 02 12:47:27 AM UTC 24 |
14428640591 ps |
| T1819 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/40.xbar_smoke_slow_rsp.1232774906 |
|
|
Sep 02 12:45:58 AM UTC 24 |
Sep 02 12:47:36 AM UTC 24 |
5378614639 ps |
| T1820 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/40.xbar_random.1593986172 |
|
|
Sep 02 12:46:00 AM UTC 24 |
Sep 02 12:47:36 AM UTC 24 |
1905942929 ps |
| T1821 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/41.xbar_random_zero_delays.1561563062 |
|
|
Sep 02 12:47:10 AM UTC 24 |
Sep 02 12:47:41 AM UTC 24 |
233753640 ps |
| T1822 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/40.xbar_error_random.4283337595 |
|
|
Sep 02 12:46:15 AM UTC 24 |
Sep 02 12:47:42 AM UTC 24 |
1853894376 ps |
| T1823 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/39.xbar_random_slow_rsp.766450019 |
|
|
Sep 02 12:45:03 AM UTC 24 |
Sep 02 12:47:52 AM UTC 24 |
9574630857 ps |
| T1824 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/39.xbar_stress_all_with_error.4017354634 |
|
|
Sep 02 12:45:22 AM UTC 24 |
Sep 02 12:48:02 AM UTC 24 |
3591221210 ps |
| T1825 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/40.xbar_smoke_large_delays.1517305424 |
|
|
Sep 02 12:45:55 AM UTC 24 |
Sep 02 12:48:05 AM UTC 24 |
8978150137 ps |
| T576 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/32.xbar_stress_all_with_reset_error.3055989582 |
|
|
Sep 02 12:37:21 AM UTC 24 |
Sep 02 12:48:07 AM UTC 24 |
5243388596 ps |
| T1826 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/41.xbar_same_source.2988684912 |
|
|
Sep 02 12:47:27 AM UTC 24 |
Sep 02 12:48:12 AM UTC 24 |
406630313 ps |
| T1827 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/41.xbar_random.782749504 |
|
|
Sep 02 12:47:09 AM UTC 24 |
Sep 02 12:48:22 AM UTC 24 |
1480911433 ps |
| T1828 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/42.xbar_smoke.440435870 |
|
|
Sep 02 12:48:16 AM UTC 24 |
Sep 02 12:48:27 AM UTC 24 |
44828549 ps |
| T1829 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/29.xbar_random_slow_rsp.4234429656 |
|
|
Sep 02 12:32:54 AM UTC 24 |
Sep 02 12:48:33 AM UTC 24 |
52514605802 ps |
| T1830 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/42.xbar_smoke_zero_delays.2395451072 |
|
|
Sep 02 12:48:25 AM UTC 24 |
Sep 02 12:48:34 AM UTC 24 |
38309893 ps |
| T1831 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/41.xbar_error_random.533947688 |
|
|
Sep 02 12:47:30 AM UTC 24 |
Sep 02 12:48:41 AM UTC 24 |
1514152334 ps |
| T1832 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/41.xbar_access_same_device.3550784987 |
|
|
Sep 02 12:47:16 AM UTC 24 |
Sep 02 12:48:43 AM UTC 24 |
1623061383 ps |
| T1833 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/41.xbar_error_and_unmapped_addr.3462230814 |
|
|
Sep 02 12:47:50 AM UTC 24 |
Sep 02 12:48:48 AM UTC 24 |
1353183686 ps |
| T1834 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/41.xbar_smoke_slow_rsp.3939169531 |
|
|
Sep 02 12:47:04 AM UTC 24 |
Sep 02 12:48:48 AM UTC 24 |
5530757371 ps |
| T1835 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/38.xbar_random_slow_rsp.1472913231 |
|
|
Sep 02 12:43:50 AM UTC 24 |
Sep 02 12:48:55 AM UTC 24 |
18978907840 ps |
| T1836 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/42.xbar_random.3723205400 |
|
|
Sep 02 12:48:36 AM UTC 24 |
Sep 02 12:48:56 AM UTC 24 |
145296557 ps |
| T1837 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/41.xbar_unmapped_addr.769428732 |
|
|
Sep 02 12:47:36 AM UTC 24 |
Sep 02 12:48:59 AM UTC 24 |
1374112704 ps |
| T1838 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/41.xbar_smoke_large_delays.282557148 |
|
|
Sep 02 12:47:03 AM UTC 24 |
Sep 02 12:49:11 AM UTC 24 |
9012718362 ps |
| T1839 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/42.xbar_same_source.522908825 |
|
|
Sep 02 12:49:06 AM UTC 24 |
Sep 02 12:49:17 AM UTC 24 |
53957311 ps |
| T1840 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/37.xbar_access_same_device_slow_rsp.2850448997 |
|
|
Sep 02 12:42:44 AM UTC 24 |
Sep 02 12:49:21 AM UTC 24 |
25155920457 ps |
| T1841 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/41.xbar_stress_all_with_rand_reset.1377705263 |
|
|
Sep 02 12:48:00 AM UTC 24 |
Sep 02 12:49:25 AM UTC 24 |
278956731 ps |
| T1842 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/42.xbar_error_random.78717777 |
|
|
Sep 02 12:49:10 AM UTC 24 |
Sep 02 12:49:34 AM UTC 24 |
374869645 ps |
| T1843 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/32.xbar_random_large_delays.1922633166 |
|
|
Sep 02 12:36:50 AM UTC 24 |
Sep 02 12:49:36 AM UTC 24 |
67950676476 ps |
| T1844 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/42.xbar_unmapped_addr.3770794303 |
|
|
Sep 02 12:49:10 AM UTC 24 |
Sep 02 12:49:38 AM UTC 24 |
142706259 ps |
| T1845 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/41.xbar_stress_all_with_error.2170810111 |
|
|
Sep 02 12:48:03 AM UTC 24 |
Sep 02 12:49:39 AM UTC 24 |
1346440147 ps |
| T1846 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/42.xbar_random_zero_delays.29206395 |
|
|
Sep 02 12:48:45 AM UTC 24 |
Sep 02 12:49:42 AM UTC 24 |
429587394 ps |
| T836 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/34.xbar_stress_all_with_reset_error.1755162231 |
|
|
Sep 02 12:39:29 AM UTC 24 |
Sep 02 12:49:49 AM UTC 24 |
7843003079 ps |
| T1847 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/32.xbar_access_same_device_slow_rsp.4132769131 |
|
|
Sep 02 12:36:59 AM UTC 24 |
Sep 02 12:49:49 AM UTC 24 |
47932657379 ps |
| T1848 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/43.xbar_smoke.2563413578 |
|
|
Sep 02 12:49:44 AM UTC 24 |
Sep 02 12:49:54 AM UTC 24 |
42004823 ps |
| T1849 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/42.xbar_smoke_slow_rsp.1764021492 |
|
|
Sep 02 12:48:30 AM UTC 24 |
Sep 02 12:49:56 AM UTC 24 |
4121933685 ps |
| T1850 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/19.chip_same_csr_outstanding.2977595102 |
|
|
Sep 02 12:13:13 AM UTC 24 |
Sep 02 12:49:59 AM UTC 24 |
15842905727 ps |
| T1851 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/43.xbar_smoke_zero_delays.1790831975 |
|
|
Sep 02 12:49:49 AM UTC 24 |
Sep 02 12:49:59 AM UTC 24 |
43467249 ps |
| T1852 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/42.xbar_access_same_device.3361238428 |
|
|
Sep 02 12:48:58 AM UTC 24 |
Sep 02 12:50:11 AM UTC 24 |
1057833320 ps |
| T1853 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/42.xbar_stress_all_with_reset_error.1608221508 |
|
|
Sep 02 12:49:40 AM UTC 24 |
Sep 02 12:50:14 AM UTC 24 |
119205422 ps |
| T1854 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/42.xbar_error_and_unmapped_addr.1023176289 |
|
|
Sep 02 12:49:18 AM UTC 24 |
Sep 02 12:50:20 AM UTC 24 |
1382360589 ps |
| T1855 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/43.xbar_random_zero_delays.1910524062 |
|
|
Sep 02 12:50:00 AM UTC 24 |
Sep 02 12:50:20 AM UTC 24 |
118869905 ps |
| T1856 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/38.xbar_stress_all_with_error.3414528136 |
|
|
Sep 02 12:44:18 AM UTC 24 |
Sep 02 12:50:35 AM UTC 24 |
4092247229 ps |
| T1857 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/42.xbar_smoke_large_delays.995440087 |
|
|
Sep 02 12:48:28 AM UTC 24 |
Sep 02 12:50:36 AM UTC 24 |
8751190410 ps |
| T1858 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/43.xbar_smoke_large_delays.320898302 |
|
|
Sep 02 12:49:57 AM UTC 24 |
Sep 02 12:50:42 AM UTC 24 |
5017300410 ps |
| T1859 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/43.xbar_unmapped_addr.3967653608 |
|
|
Sep 02 12:50:21 AM UTC 24 |
Sep 02 12:50:48 AM UTC 24 |
171611562 ps |
| T1860 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/7.chip_same_csr_outstanding.3613265702 |
|
|
Sep 01 11:42:05 PM UTC 24 |
Sep 02 12:50:58 AM UTC 24 |
31832455852 ps |
| T1861 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/41.xbar_stress_all.3722584283 |
|
|
Sep 02 12:48:00 AM UTC 24 |
Sep 02 12:51:00 AM UTC 24 |
5071095250 ps |
| T1862 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/31.xbar_random_slow_rsp.886677425 |
|
|
Sep 02 12:36:00 AM UTC 24 |
Sep 02 12:51:02 AM UTC 24 |
55978051977 ps |
| T1863 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/43.xbar_same_source.3213010181 |
|
|
Sep 02 12:50:19 AM UTC 24 |
Sep 02 12:51:14 AM UTC 24 |
1269868362 ps |
| T1864 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/44.xbar_smoke.710839824 |
|
|
Sep 02 12:50:59 AM UTC 24 |
Sep 02 12:51:15 AM UTC 24 |
231475291 ps |
| T1865 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/44.xbar_smoke_zero_delays.2063387729 |
|
|
Sep 02 12:51:06 AM UTC 24 |
Sep 02 12:51:15 AM UTC 24 |
37688495 ps |
| T1866 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/39.xbar_stress_all_with_reset_error.3311784988 |
|
|
Sep 02 12:45:23 AM UTC 24 |
Sep 02 12:51:20 AM UTC 24 |
3740870235 ps |
| T1867 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/43.xbar_error_and_unmapped_addr.3409267017 |
|
|
Sep 02 12:50:35 AM UTC 24 |
Sep 02 12:51:32 AM UTC 24 |
1278501961 ps |
| T1868 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/41.xbar_access_same_device_slow_rsp.1552721687 |
|
|
Sep 02 12:47:19 AM UTC 24 |
Sep 02 12:51:41 AM UTC 24 |
17909137723 ps |
| T1869 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/43.xbar_smoke_slow_rsp.3639435760 |
|
|
Sep 02 12:49:59 AM UTC 24 |
Sep 02 12:51:45 AM UTC 24 |
6475431283 ps |
| T1870 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/43.xbar_access_same_device.1392530496 |
|
|
Sep 02 12:50:09 AM UTC 24 |
Sep 02 12:51:47 AM UTC 24 |
1017534950 ps |
| T1871 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/43.xbar_random.903573682 |
|
|
Sep 02 12:50:01 AM UTC 24 |
Sep 02 12:51:49 AM UTC 24 |
2350520599 ps |
| T1872 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/40.xbar_random_large_delays.3631531975 |
|
|
Sep 02 12:46:07 AM UTC 24 |
Sep 02 12:51:54 AM UTC 24 |
22052933054 ps |
| T1873 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/43.xbar_error_random.3244998409 |
|
|
Sep 02 12:50:20 AM UTC 24 |
Sep 02 12:51:56 AM UTC 24 |
1840575091 ps |
| T1874 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/44.xbar_random_zero_delays.2323247588 |
|
|
Sep 02 12:51:24 AM UTC 24 |
Sep 02 12:52:11 AM UTC 24 |
467592222 ps |
| T1875 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/44.xbar_unmapped_addr.948277877 |
|
|
Sep 02 12:52:08 AM UTC 24 |
Sep 02 12:52:19 AM UTC 24 |
71334444 ps |
| T507 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/29.xbar_random_large_delays.4248855975 |
|
|
Sep 02 12:32:55 AM UTC 24 |
Sep 02 12:52:20 AM UTC 24 |
101636264054 ps |
| T1876 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/44.xbar_same_source.4174751148 |
|
|
Sep 02 12:51:54 AM UTC 24 |
Sep 02 12:52:22 AM UTC 24 |
210990228 ps |
| T1877 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/40.xbar_stress_all.3290270742 |
|
|
Sep 02 12:46:32 AM UTC 24 |
Sep 02 12:52:31 AM UTC 24 |
3714144527 ps |
| T1878 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/31.xbar_random_large_delays.137905493 |
|
|
Sep 02 12:35:50 AM UTC 24 |
Sep 02 12:52:35 AM UTC 24 |
101921496258 ps |
| T1879 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/44.xbar_random.1108762581 |
|
|
Sep 02 12:51:21 AM UTC 24 |
Sep 02 12:52:42 AM UTC 24 |
1997655222 ps |
| T1880 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/44.xbar_access_same_device.4043569193 |
|
|
Sep 02 12:51:38 AM UTC 24 |
Sep 02 12:52:45 AM UTC 24 |
530513816 ps |
| T1881 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/44.xbar_access_same_device_slow_rsp.979484751 |
|
|
Sep 02 12:51:43 AM UTC 24 |
Sep 02 12:52:52 AM UTC 24 |
2854391074 ps |
| T1882 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/45.xbar_smoke.498875769 |
|
|
Sep 02 12:52:42 AM UTC 24 |
Sep 02 12:52:53 AM UTC 24 |
50034428 ps |
| T1883 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/45.xbar_smoke_zero_delays.1410915122 |
|
|
Sep 02 12:52:43 AM UTC 24 |
Sep 02 12:52:53 AM UTC 24 |
43579996 ps |
| T1884 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/36.xbar_random_slow_rsp.3553654699 |
|
|
Sep 02 12:41:08 AM UTC 24 |
Sep 02 12:53:03 AM UTC 24 |
44642672790 ps |
| T1885 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/44.xbar_smoke_slow_rsp.3618216642 |
|
|
Sep 02 12:51:21 AM UTC 24 |
Sep 02 12:53:04 AM UTC 24 |
5300536844 ps |
| T1886 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/44.xbar_stress_all_with_error.1480660038 |
|
|
Sep 02 12:52:17 AM UTC 24 |
Sep 02 12:53:06 AM UTC 24 |
968754029 ps |
| T1887 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/44.xbar_error_and_unmapped_addr.4065907771 |
|
|
Sep 02 12:52:11 AM UTC 24 |
Sep 02 12:53:06 AM UTC 24 |
992143895 ps |
| T1888 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/29.xbar_access_same_device_slow_rsp.1492931659 |
|
|
Sep 02 12:33:08 AM UTC 24 |
Sep 02 12:53:08 AM UTC 24 |
67440391114 ps |
| T1889 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/40.xbar_random_slow_rsp.391339836 |
|
|
Sep 02 12:46:07 AM UTC 24 |
Sep 02 12:53:15 AM UTC 24 |
23855678740 ps |
| T1890 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/42.xbar_random_slow_rsp.1818659297 |
|
|
Sep 02 12:48:57 AM UTC 24 |
Sep 02 12:53:20 AM UTC 24 |
16041413163 ps |
| T1891 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/43.xbar_stress_all_with_error.2557154025 |
|
|
Sep 02 12:50:41 AM UTC 24 |
Sep 02 12:53:22 AM UTC 24 |
1604453720 ps |
| T1892 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/44.xbar_random_slow_rsp.2542085592 |
|
|
Sep 02 12:51:37 AM UTC 24 |
Sep 02 12:53:29 AM UTC 24 |
4916492036 ps |
| T1893 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/44.xbar_error_random.2155218113 |
|
|
Sep 02 12:52:04 AM UTC 24 |
Sep 02 12:53:30 AM UTC 24 |
2696097610 ps |
| T825 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/41.xbar_stress_all_with_reset_error.1209399579 |
|
|
Sep 02 12:48:04 AM UTC 24 |
Sep 02 12:53:32 AM UTC 24 |
751417665 ps |
| T1894 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/44.xbar_smoke_large_delays.1224148873 |
|
|
Sep 02 12:51:11 AM UTC 24 |
Sep 02 12:53:34 AM UTC 24 |
9524195345 ps |
| T1895 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/45.xbar_error_random.4106972303 |
|
|
Sep 02 12:53:26 AM UTC 24 |
Sep 02 12:53:48 AM UTC 24 |
349537779 ps |
| T1896 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/45.xbar_same_source.1852082485 |
|
|
Sep 02 12:53:26 AM UTC 24 |
Sep 02 12:53:55 AM UTC 24 |
309566875 ps |
| T1897 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/45.xbar_random_zero_delays.3686910318 |
|
|
Sep 02 12:53:04 AM UTC 24 |
Sep 02 12:54:00 AM UTC 24 |
442606955 ps |
| T1898 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/46.xbar_smoke.3424874193 |
|
|
Sep 02 12:53:51 AM UTC 24 |
Sep 02 12:54:00 AM UTC 24 |
51982062 ps |
| T1899 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/46.xbar_smoke_zero_delays.538875073 |
|
|
Sep 02 12:53:50 AM UTC 24 |
Sep 02 12:54:00 AM UTC 24 |
49039637 ps |
| T1900 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/34.xbar_stress_all_with_rand_reset.2858152094 |
|
|
Sep 02 12:39:22 AM UTC 24 |
Sep 02 12:54:01 AM UTC 24 |
11967248115 ps |
| T1901 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/44.xbar_stress_all_with_reset_error.820781489 |
|
|
Sep 02 12:52:34 AM UTC 24 |
Sep 02 12:54:04 AM UTC 24 |
209295816 ps |
| T1902 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/45.xbar_unmapped_addr.785892167 |
|
|
Sep 02 12:53:27 AM UTC 24 |
Sep 02 12:54:05 AM UTC 24 |
570484667 ps |
| T1903 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/42.xbar_stress_all_with_error.3452360169 |
|
|
Sep 02 12:49:33 AM UTC 24 |
Sep 02 12:54:06 AM UTC 24 |
8334152991 ps |
| T1904 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/45.xbar_error_and_unmapped_addr.2447684426 |
|
|
Sep 02 12:53:28 AM UTC 24 |
Sep 02 12:54:28 AM UTC 24 |
1162104235 ps |
| T1905 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/46.xbar_random.2706419037 |
|
|
Sep 02 12:54:11 AM UTC 24 |
Sep 02 12:54:28 AM UTC 24 |
100606615 ps |
| T1906 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/45.xbar_random.3931644324 |
|
|
Sep 02 12:52:57 AM UTC 24 |
Sep 02 12:54:32 AM UTC 24 |
1833638689 ps |
| T1907 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/45.xbar_smoke_slow_rsp.3132935606 |
|
|
Sep 02 12:52:54 AM UTC 24 |
Sep 02 12:54:33 AM UTC 24 |
5688101991 ps |
| T1908 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/40.xbar_stress_all_with_error.3078787547 |
|
|
Sep 02 12:46:40 AM UTC 24 |
Sep 02 12:54:38 AM UTC 24 |
11295628785 ps |
| T1909 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/45.xbar_random_large_delays.189653187 |
|
|
Sep 02 12:53:09 AM UTC 24 |
Sep 02 12:54:43 AM UTC 24 |
5552156166 ps |
| T1910 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/45.xbar_access_same_device.4217357623 |
|
|
Sep 02 12:53:16 AM UTC 24 |
Sep 02 12:54:46 AM UTC 24 |
902951101 ps |
| T844 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/43.xbar_stress_all_with_reset_error.536891079 |
|
|
Sep 02 12:50:59 AM UTC 24 |
Sep 02 12:54:47 AM UTC 24 |
4933314337 ps |
| T1911 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/45.xbar_smoke_large_delays.162073636 |
|
|
Sep 02 12:52:45 AM UTC 24 |
Sep 02 12:54:50 AM UTC 24 |
8054694063 ps |
| T1912 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/46.xbar_random_zero_delays.33309036 |
|
|
Sep 02 12:54:17 AM UTC 24 |
Sep 02 12:54:56 AM UTC 24 |
364884464 ps |
| T1913 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/46.xbar_error_random.2066877442 |
|
|
Sep 02 12:54:25 AM UTC 24 |
Sep 02 12:55:00 AM UTC 24 |
274829046 ps |
| T1914 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/6.chip_same_csr_outstanding.4054716901 |
|
|
Sep 01 11:39:19 PM UTC 24 |
Sep 02 12:55:05 AM UTC 24 |
26628703046 ps |
| T1915 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/45.xbar_stress_all.3088474933 |
|
|
Sep 02 12:53:30 AM UTC 24 |
Sep 02 12:55:06 AM UTC 24 |
994747670 ps |
| T1916 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/46.xbar_smoke_large_delays.630718415 |
|
|
Sep 02 12:53:55 AM UTC 24 |
Sep 02 12:55:08 AM UTC 24 |
7351331086 ps |
| T1917 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/46.xbar_same_source.1482479927 |
|
|
Sep 02 12:54:27 AM UTC 24 |
Sep 02 12:55:12 AM UTC 24 |
1193980199 ps |
| T1918 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/47.xbar_smoke.2281412299 |
|
|
Sep 02 12:55:05 AM UTC 24 |
Sep 02 12:55:17 AM UTC 24 |
54715392 ps |
| T1919 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/47.xbar_smoke_zero_delays.4186892215 |
|
|
Sep 02 12:55:06 AM UTC 24 |
Sep 02 12:55:17 AM UTC 24 |
54192858 ps |
| T1920 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/46.xbar_error_and_unmapped_addr.1684003707 |
|
|
Sep 02 12:54:50 AM UTC 24 |
Sep 02 12:55:18 AM UTC 24 |
371765191 ps |
| T1921 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/46.xbar_unmapped_addr.743100950 |
|
|
Sep 02 12:54:28 AM UTC 24 |
Sep 02 12:55:20 AM UTC 24 |
788109394 ps |
| T1922 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/42.xbar_stress_all.580174202 |
|
|
Sep 02 12:49:18 AM UTC 24 |
Sep 02 12:55:34 AM UTC 24 |
10725723517 ps |
| T1923 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/34.xbar_random_slow_rsp.1544521782 |
|
|
Sep 02 12:38:46 AM UTC 24 |
Sep 02 12:55:40 AM UTC 24 |
57529075900 ps |
| T1924 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/27.xbar_access_same_device_slow_rsp.4178966668 |
|
|
Sep 02 12:28:54 AM UTC 24 |
Sep 02 12:55:40 AM UTC 24 |
94794404987 ps |
| T1925 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/44.xbar_stress_all.646339469 |
|
|
Sep 02 12:52:12 AM UTC 24 |
Sep 02 12:55:43 AM UTC 24 |
2506325395 ps |
| T1926 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/47.xbar_access_same_device.3307958621 |
|
|
Sep 02 12:55:31 AM UTC 24 |
Sep 02 12:55:49 AM UTC 24 |
249049316 ps |
| T1927 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/47.xbar_unmapped_addr.3210685905 |
|
|
Sep 02 12:55:39 AM UTC 24 |
Sep 02 12:55:49 AM UTC 24 |
62310133 ps |
| T1928 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/46.xbar_access_same_device.979717567 |
|
|
Sep 02 12:54:23 AM UTC 24 |
Sep 02 12:55:53 AM UTC 24 |
1160109696 ps |
| T1929 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/47.xbar_random.1173145933 |
|
|
Sep 02 12:55:20 AM UTC 24 |
Sep 02 12:55:55 AM UTC 24 |
253242397 ps |
| T1930 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/32.xbar_random_slow_rsp.838701477 |
|
|
Sep 02 12:36:52 AM UTC 24 |
Sep 02 12:56:12 AM UTC 24 |
58989806154 ps |
| T1931 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/47.xbar_smoke_large_delays.3893618931 |
|
|
Sep 02 12:55:07 AM UTC 24 |
Sep 02 12:56:14 AM UTC 24 |
6407193115 ps |
| T1932 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/47.xbar_error_random.143548371 |
|
|
Sep 02 12:55:40 AM UTC 24 |
Sep 02 12:56:19 AM UTC 24 |
345410940 ps |
| T1933 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/47.xbar_random_zero_delays.1458482727 |
|
|
Sep 02 12:55:24 AM UTC 24 |
Sep 02 12:56:19 AM UTC 24 |
534570281 ps |
| T1934 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/41.xbar_random_large_delays.456565223 |
|
|
Sep 02 12:47:14 AM UTC 24 |
Sep 02 12:56:19 AM UTC 24 |
45081549571 ps |
| T1935 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/47.xbar_error_and_unmapped_addr.2015748733 |
|
|
Sep 02 12:55:42 AM UTC 24 |
Sep 02 12:56:22 AM UTC 24 |
614403035 ps |
| T1936 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/48.xbar_smoke_zero_delays.4071140993 |
|
|
Sep 02 12:56:12 AM UTC 24 |
Sep 02 12:56:22 AM UTC 24 |
39579480 ps |
| T1937 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/48.xbar_smoke.3868969833 |
|
|
Sep 02 12:56:12 AM UTC 24 |
Sep 02 12:56:25 AM UTC 24 |
157246405 ps |
| T1938 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/46.xbar_smoke_slow_rsp.4045098860 |
|
|
Sep 02 12:53:57 AM UTC 24 |
Sep 02 12:56:31 AM UTC 24 |
6546915814 ps |
| T1939 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/39.xbar_random_large_delays.3062551158 |
|
|
Sep 02 12:44:59 AM UTC 24 |
Sep 02 12:56:32 AM UTC 24 |
63577124723 ps |
| T1940 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/44.xbar_stress_all_with_rand_reset.2060820693 |
|
|
Sep 02 12:52:15 AM UTC 24 |
Sep 02 12:56:33 AM UTC 24 |
677149354 ps |
| T1941 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/47.xbar_same_source.1251604021 |
|
|
Sep 02 12:55:40 AM UTC 24 |
Sep 02 12:56:48 AM UTC 24 |
1523629956 ps |
| T1942 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/42.xbar_stress_all_with_rand_reset.3698655040 |
|
|
Sep 02 12:49:22 AM UTC 24 |
Sep 02 12:56:48 AM UTC 24 |
3073436109 ps |
| T1943 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/46.xbar_stress_all_with_reset_error.1848145841 |
|
|
Sep 02 12:55:01 AM UTC 24 |
Sep 02 12:56:56 AM UTC 24 |
421894043 ps |
| T1944 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/48.xbar_access_same_device.2427799170 |
|
|
Sep 02 12:56:43 AM UTC 24 |
Sep 02 12:57:00 AM UTC 24 |
215931619 ps |
| T1945 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/47.xbar_smoke_slow_rsp.4048261673 |
|
|
Sep 02 12:55:12 AM UTC 24 |
Sep 02 12:57:01 AM UTC 24 |
6428609986 ps |
| T1946 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/48.xbar_random.2353041789 |
|
|
Sep 02 12:56:35 AM UTC 24 |
Sep 02 12:57:08 AM UTC 24 |
230486091 ps |
| T1947 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/48.xbar_smoke_large_delays.1785999635 |
|
|
Sep 02 12:56:17 AM UTC 24 |
Sep 02 12:57:08 AM UTC 24 |
4773030434 ps |
| T1948 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/48.xbar_same_source.1330993349 |
|
|
Sep 02 12:56:45 AM UTC 24 |
Sep 02 12:57:09 AM UTC 24 |
587394476 ps |
| T1949 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/48.xbar_error_and_unmapped_addr.3343085318 |
|
|
Sep 02 12:56:56 AM UTC 24 |
Sep 02 12:57:29 AM UTC 24 |
837607250 ps |
| T1950 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/48.xbar_random_zero_delays.3287479297 |
|
|
Sep 02 12:56:36 AM UTC 24 |
Sep 02 12:57:31 AM UTC 24 |
548923309 ps |
| T1951 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/49.xbar_smoke.625449178 |
|
|
Sep 02 12:57:23 AM UTC 24 |
Sep 02 12:57:31 AM UTC 24 |
50416928 ps |
| T1952 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/49.xbar_smoke_zero_delays.823512286 |
|
|
Sep 02 12:57:23 AM UTC 24 |
Sep 02 12:57:32 AM UTC 24 |
38846909 ps |
| T1953 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/48.xbar_unmapped_addr.59450212 |
|
|
Sep 02 12:56:54 AM UTC 24 |
Sep 02 12:57:33 AM UTC 24 |
566299769 ps |
| T1954 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/47.xbar_stress_all.2222784790 |
|
|
Sep 02 12:55:57 AM UTC 24 |
Sep 02 12:57:33 AM UTC 24 |
1834189725 ps |
| T1955 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/37.xbar_stress_all_with_rand_reset.2707468254 |
|
|
Sep 02 12:43:01 AM UTC 24 |
Sep 02 12:57:42 AM UTC 24 |
6422357431 ps |
| T1956 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/44.xbar_random_large_delays.2992986764 |
|
|
Sep 02 12:51:35 AM UTC 24 |
Sep 02 12:57:52 AM UTC 24 |
36155486736 ps |
| T1957 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/48.xbar_error_random.73157778 |
|
|
Sep 02 12:56:47 AM UTC 24 |
Sep 02 12:57:58 AM UTC 24 |
606499434 ps |
| T1958 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/35.xbar_stress_all_with_rand_reset.1522964566 |
|
|
Sep 02 12:40:22 AM UTC 24 |
Sep 02 12:58:02 AM UTC 24 |
7160173099 ps |
| T1959 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/45.xbar_stress_all_with_rand_reset.1505580130 |
|
|
Sep 02 12:53:35 AM UTC 24 |
Sep 02 12:58:06 AM UTC 24 |
1743685414 ps |
| T1960 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/48.xbar_smoke_slow_rsp.2321302170 |
|
|
Sep 02 12:56:17 AM UTC 24 |
Sep 02 12:58:07 AM UTC 24 |
4484770971 ps |
| T1961 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/49.xbar_random_zero_delays.3980056688 |
|
|
Sep 02 12:57:51 AM UTC 24 |
Sep 02 12:58:07 AM UTC 24 |
103387741 ps |
| T1962 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/49.xbar_unmapped_addr.3417982159 |
|
|
Sep 02 12:58:15 AM UTC 24 |
Sep 02 12:58:30 AM UTC 24 |
155114132 ps |
| T1963 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/41.xbar_random_slow_rsp.2887075792 |
|
|
Sep 02 12:47:14 AM UTC 24 |
Sep 02 12:58:31 AM UTC 24 |
37156465596 ps |
| T1964 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/48.xbar_stress_all.605418825 |
|
|
Sep 02 12:56:57 AM UTC 24 |
Sep 02 12:58:35 AM UTC 24 |
2427649181 ps |
| T1965 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/49.xbar_random.3100798688 |
|
|
Sep 02 12:57:31 AM UTC 24 |
Sep 02 12:58:40 AM UTC 24 |
1824896021 ps |
| T1966 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/46.xbar_stress_all_with_error.704931300 |
|
|
Sep 02 12:54:56 AM UTC 24 |
Sep 02 12:58:45 AM UTC 24 |
2109263006 ps |
| T1967 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/47.xbar_stress_all_with_error.1556905343 |
|
|
Sep 02 12:56:03 AM UTC 24 |
Sep 02 12:58:48 AM UTC 24 |
3851559038 ps |
| T1968 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/49.xbar_smoke_slow_rsp.2313126857 |
|
|
Sep 02 12:57:29 AM UTC 24 |
Sep 02 12:58:51 AM UTC 24 |
4963153531 ps |
| T1969 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/50.xbar_smoke_zero_delays.1725536701 |
|
|
Sep 02 12:58:53 AM UTC 24 |
Sep 02 12:59:02 AM UTC 24 |
41527771 ps |
| T833 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/48.xbar_stress_all_with_rand_reset.2702046179 |
|
|
Sep 02 12:57:11 AM UTC 24 |
Sep 02 12:59:07 AM UTC 24 |
210973090 ps |
| T1970 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/42.xbar_random_large_delays.2953532338 |
|
|
Sep 02 12:48:50 AM UTC 24 |
Sep 02 12:59:08 AM UTC 24 |
55917990901 ps |
| T1971 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/49.xbar_error_and_unmapped_addr.680969531 |
|
|
Sep 02 12:58:21 AM UTC 24 |
Sep 02 12:59:10 AM UTC 24 |
840163958 ps |
| T1972 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/47.xbar_stress_all_with_reset_error.1069523510 |
|
|
Sep 02 12:56:06 AM UTC 24 |
Sep 02 12:59:13 AM UTC 24 |
1894150116 ps |
| T1973 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/47.xbar_stress_all_with_rand_reset.1239978765 |
|
|
Sep 02 12:56:03 AM UTC 24 |
Sep 02 12:59:15 AM UTC 24 |
1636080142 ps |
| T1974 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/49.xbar_error_random.532245422 |
|
|
Sep 02 12:58:06 AM UTC 24 |
Sep 02 12:59:21 AM UTC 24 |
1664968164 ps |
| T1975 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/49.xbar_access_same_device.1814505534 |
|
|
Sep 02 12:57:55 AM UTC 24 |
Sep 02 12:59:30 AM UTC 24 |
2498746761 ps |
| T1976 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/50.xbar_random_zero_delays.154972032 |
|
|
Sep 02 12:59:10 AM UTC 24 |
Sep 02 12:59:34 AM UTC 24 |
161444198 ps |
| T1977 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/49.xbar_smoke_large_delays.4228945849 |
|
|
Sep 02 12:57:31 AM UTC 24 |
Sep 02 12:59:38 AM UTC 24 |
8540474208 ps |
| T1978 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/50.xbar_access_same_device.1162510453 |
|
|
Sep 02 12:59:26 AM UTC 24 |
Sep 02 12:59:44 AM UTC 24 |
276783032 ps |
| T1979 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/49.xbar_same_source.1190426336 |
|
|
Sep 02 12:57:54 AM UTC 24 |
Sep 02 12:59:44 AM UTC 24 |
2497134168 ps |
| T1980 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/45.xbar_stress_all_with_error.3918854651 |
|
|
Sep 02 12:53:41 AM UTC 24 |
Sep 02 12:59:49 AM UTC 24 |
4027021106 ps |
| T1981 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/43.xbar_stress_all_with_rand_reset.613118493 |
|
|
Sep 02 12:50:43 AM UTC 24 |
Sep 02 12:59:59 AM UTC 24 |
891244761 ps |
| T1982 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/50.xbar_error_and_unmapped_addr.40090140 |
|
|
Sep 02 12:59:39 AM UTC 24 |
Sep 02 01:00:00 AM UTC 24 |
275038800 ps |
| T1983 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/45.xbar_access_same_device_slow_rsp.1350710327 |
|
|
Sep 02 12:53:17 AM UTC 24 |
Sep 02 01:00:01 AM UTC 24 |
26925647285 ps |
| T1984 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/49.xbar_stress_all.3243454681 |
|
|
Sep 02 12:58:26 AM UTC 24 |
Sep 02 01:00:06 AM UTC 24 |
1146403207 ps |
| T1985 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/50.xbar_random.318251664 |
|
|
Sep 02 12:59:07 AM UTC 24 |
Sep 02 01:00:10 AM UTC 24 |
561009671 ps |
| T1986 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/51.xbar_smoke.1598501857 |
|
|
Sep 02 01:00:05 AM UTC 24 |
Sep 02 01:00:16 AM UTC 24 |
41043700 ps |
| T1987 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/51.xbar_smoke_zero_delays.1319525099 |
|
|
Sep 02 01:00:04 AM UTC 24 |
Sep 02 01:00:16 AM UTC 24 |
47898136 ps |
| T1988 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/50.xbar_error_random.2735803951 |
|
|
Sep 02 12:59:34 AM UTC 24 |
Sep 02 01:00:27 AM UTC 24 |
1042990732 ps |
| T1989 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/50.xbar_same_source.2756090208 |
|
|
Sep 02 12:59:31 AM UTC 24 |
Sep 02 01:00:28 AM UTC 24 |
539255640 ps |
| T1990 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/51.xbar_random.1858972644 |
|
|
Sep 02 01:00:20 AM UTC 24 |
Sep 02 01:00:32 AM UTC 24 |
128162833 ps |
| T1991 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/50.xbar_unmapped_addr.1792535607 |
|
|
Sep 02 12:59:35 AM UTC 24 |
Sep 02 01:00:38 AM UTC 24 |
1276593000 ps |
| T1992 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/50.xbar_smoke_large_delays.758296210 |
|
|
Sep 02 12:58:58 AM UTC 24 |
Sep 02 01:00:41 AM UTC 24 |
8555917353 ps |
| T1993 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/50.xbar_smoke_slow_rsp.221403644 |
|
|
Sep 02 12:59:04 AM UTC 24 |
Sep 02 01:00:42 AM UTC 24 |
4720834199 ps |
| T1994 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/43.xbar_random_slow_rsp.85055734 |
|
|
Sep 02 12:50:13 AM UTC 24 |
Sep 02 01:00:49 AM UTC 24 |
31752790825 ps |
| T1995 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/43.xbar_stress_all.844786125 |
|
|
Sep 02 12:50:36 AM UTC 24 |
Sep 02 01:00:59 AM UTC 24 |
12144252919 ps |
| T1996 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/51.xbar_same_source.4057340168 |
|
|
Sep 02 01:00:49 AM UTC 24 |
Sep 02 01:01:08 AM UTC 24 |
169370446 ps |
| T1997 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/51.xbar_unmapped_addr.2818948018 |
|
|
Sep 02 01:00:54 AM UTC 24 |
Sep 02 01:01:09 AM UTC 24 |
136541130 ps |
| T1998 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/51.xbar_access_same_device.432533348 |
|
|
Sep 02 01:00:39 AM UTC 24 |
Sep 02 01:01:11 AM UTC 24 |
370833274 ps |
| T1999 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/51.xbar_random_zero_delays.4262006759 |
|
|
Sep 02 01:00:21 AM UTC 24 |
Sep 02 01:01:23 AM UTC 24 |
499586504 ps |
| T2000 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/49.xbar_random_large_delays.3089840250 |
|
|
Sep 02 12:57:54 AM UTC 24 |
Sep 02 01:01:30 AM UTC 24 |
16820049443 ps |
| T2001 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/51.xbar_error_and_unmapped_addr.588655389 |
|
|
Sep 02 01:01:01 AM UTC 24 |
Sep 02 01:01:33 AM UTC 24 |
186365379 ps |
| T2002 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/26.xbar_access_same_device_slow_rsp.3325829545 |
|
|
Sep 02 12:26:50 AM UTC 24 |
Sep 02 01:01:37 AM UTC 24 |
113350326305 ps |
| T2003 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/52.xbar_smoke.665777364 |
|
|
Sep 02 01:01:28 AM UTC 24 |
Sep 02 01:01:42 AM UTC 24 |
166261981 ps |
| T2004 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/52.xbar_smoke_zero_delays.1614597223 |
|
|
Sep 02 01:01:32 AM UTC 24 |
Sep 02 01:01:43 AM UTC 24 |
48780957 ps |
| T2005 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/51.xbar_smoke_slow_rsp.3815566370 |
|
|
Sep 02 01:00:23 AM UTC 24 |
Sep 02 01:01:52 AM UTC 24 |
5323514520 ps |
| T2006 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/47.xbar_access_same_device_slow_rsp.3538674946 |
|
|
Sep 02 12:55:35 AM UTC 24 |
Sep 02 01:01:58 AM UTC 24 |
23533697342 ps |
| T2007 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/51.xbar_error_random.2242007061 |
|
|
Sep 02 01:00:49 AM UTC 24 |
Sep 02 01:02:03 AM UTC 24 |
1748262006 ps |
| T2008 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/50.xbar_stress_all_with_error.3950437817 |
|
|
Sep 02 12:59:57 AM UTC 24 |
Sep 02 01:02:06 AM UTC 24 |
1829976072 ps |
| T2009 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/52.xbar_random.335358217 |
|
|
Sep 02 01:01:53 AM UTC 24 |
Sep 02 01:02:07 AM UTC 24 |
70549833 ps |
| T2010 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/48.xbar_stress_all_with_error.1833989893 |
|
|
Sep 02 12:57:12 AM UTC 24 |
Sep 02 01:02:12 AM UTC 24 |
7577979005 ps |
| T2011 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/49.xbar_stress_all_with_error.2051706307 |
|
|
Sep 02 12:58:30 AM UTC 24 |
Sep 02 01:02:25 AM UTC 24 |
2669461204 ps |
| T2012 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/46.xbar_random_large_delays.1495474858 |
|
|
Sep 02 12:54:22 AM UTC 24 |
Sep 02 01:02:27 AM UTC 24 |
38687914614 ps |
| T2013 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/12.chip_same_csr_outstanding.4180346021 |
|
|
Sep 01 11:53:38 PM UTC 24 |
Sep 02 01:02:29 AM UTC 24 |
28200054838 ps |
| T2014 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/52.xbar_random_zero_delays.2701817834 |
|
|
Sep 02 01:01:55 AM UTC 24 |
Sep 02 01:02:32 AM UTC 24 |
281832427 ps |
| T2015 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/48.xbar_stress_all_with_reset_error.1917011837 |
|
|
Sep 02 12:57:16 AM UTC 24 |
Sep 02 01:02:32 AM UTC 24 |
3034681361 ps |
| T2016 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/52.xbar_same_source.3021811868 |
|
|
Sep 02 01:02:20 AM UTC 24 |
Sep 02 01:02:33 AM UTC 24 |
100171669 ps |
| T2017 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/51.xbar_smoke_large_delays.3498207551 |
|
|
Sep 02 01:00:12 AM UTC 24 |
Sep 02 01:02:33 AM UTC 24 |
8876332095 ps |