| T2511 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/79.xbar_stress_all_with_error.1764778733 |
|
|
Sep 02 01:37:33 AM UTC 24 |
Sep 02 01:39:14 AM UTC 24 |
963269333 ps |
| T2512 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/80.xbar_random.271154784 |
|
|
Sep 02 01:38:06 AM UTC 24 |
Sep 02 01:39:15 AM UTC 24 |
1356180365 ps |
| T2513 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/75.xbar_stress_all.440120857 |
|
|
Sep 02 01:32:52 AM UTC 24 |
Sep 02 01:39:15 AM UTC 24 |
9649295350 ps |
| T2514 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/79.xbar_stress_all_with_rand_reset.3511982411 |
|
|
Sep 02 01:37:29 AM UTC 24 |
Sep 02 01:39:23 AM UTC 24 |
256535531 ps |
| T2515 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/80.xbar_smoke_slow_rsp.919964973 |
|
|
Sep 02 01:37:56 AM UTC 24 |
Sep 02 01:39:29 AM UTC 24 |
5935453357 ps |
| T2516 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/80.xbar_smoke_large_delays.2776707697 |
|
|
Sep 02 01:37:56 AM UTC 24 |
Sep 02 01:39:31 AM UTC 24 |
5755424447 ps |
| T2517 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/77.xbar_stress_all_with_rand_reset.2131657067 |
|
|
Sep 02 01:35:24 AM UTC 24 |
Sep 02 01:39:40 AM UTC 24 |
526668464 ps |
| T2518 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/81.xbar_smoke_zero_delays.1324287613 |
|
|
Sep 02 01:39:39 AM UTC 24 |
Sep 02 01:39:49 AM UTC 24 |
44690219 ps |
| T2519 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/80.xbar_same_source.600871235 |
|
|
Sep 02 01:38:43 AM UTC 24 |
Sep 02 01:39:49 AM UTC 24 |
1943642641 ps |
| T2520 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/81.xbar_smoke.3551238956 |
|
|
Sep 02 01:39:38 AM UTC 24 |
Sep 02 01:39:51 AM UTC 24 |
169083591 ps |
| T2521 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/73.xbar_stress_all.1139572790 |
|
|
Sep 02 01:30:34 AM UTC 24 |
Sep 02 01:39:51 AM UTC 24 |
5296279307 ps |
| T2522 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/80.xbar_error_and_unmapped_addr.4051675784 |
|
|
Sep 02 01:39:08 AM UTC 24 |
Sep 02 01:39:53 AM UTC 24 |
313811071 ps |
| T2523 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/78.xbar_random_slow_rsp.1922189927 |
|
|
Sep 02 01:36:01 AM UTC 24 |
Sep 02 01:39:59 AM UTC 24 |
11167323073 ps |
| T2524 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/80.xbar_access_same_device.3706336352 |
|
|
Sep 02 01:38:28 AM UTC 24 |
Sep 02 01:39:59 AM UTC 24 |
2102092067 ps |
| T2525 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/64.xbar_access_same_device_slow_rsp.2688982714 |
|
|
Sep 02 01:17:56 AM UTC 24 |
Sep 02 01:40:00 AM UTC 24 |
72001629374 ps |
| T2526 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/80.xbar_error_random.2024947997 |
|
|
Sep 02 01:38:50 AM UTC 24 |
Sep 02 01:40:03 AM UTC 24 |
1568659795 ps |
| T2527 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/72.xbar_random_large_delays.2737547751 |
|
|
Sep 02 01:28:34 AM UTC 24 |
Sep 02 01:40:15 AM UTC 24 |
65726158975 ps |
| T2528 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/80.xbar_unmapped_addr.4120817865 |
|
|
Sep 02 01:39:04 AM UTC 24 |
Sep 02 01:40:23 AM UTC 24 |
1361269761 ps |
| T2529 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/78.xbar_stress_all_with_error.483990483 |
|
|
Sep 02 01:36:46 AM UTC 24 |
Sep 02 01:40:27 AM UTC 24 |
2944208517 ps |
| T2530 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/73.xbar_random_slow_rsp.4145468056 |
|
|
Sep 02 01:30:08 AM UTC 24 |
Sep 02 01:40:30 AM UTC 24 |
33051378511 ps |
| T2531 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/60.xbar_access_same_device_slow_rsp.552746131 |
|
|
Sep 02 01:11:52 AM UTC 24 |
Sep 02 01:40:32 AM UTC 24 |
106101608381 ps |
| T2532 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/73.xbar_random_large_delays.2345126958 |
|
|
Sep 02 01:30:01 AM UTC 24 |
Sep 02 01:40:32 AM UTC 24 |
53373270507 ps |
| T2533 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/81.xbar_unmapped_addr.2026137482 |
|
|
Sep 02 01:40:21 AM UTC 24 |
Sep 02 01:40:41 AM UTC 24 |
363464304 ps |
| T2534 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/81.xbar_random_zero_delays.2559836681 |
|
|
Sep 02 01:40:04 AM UTC 24 |
Sep 02 01:40:44 AM UTC 24 |
302202844 ps |
| T2535 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/68.xbar_stress_all_with_reset_error.816219968 |
|
|
Sep 02 01:24:11 AM UTC 24 |
Sep 02 01:40:47 AM UTC 24 |
22190662026 ps |
| T2536 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/78.xbar_stress_all.3061919083 |
|
|
Sep 02 01:36:40 AM UTC 24 |
Sep 02 01:40:51 AM UTC 24 |
2949813782 ps |
| T2537 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/77.xbar_random_large_delays.1332227003 |
|
|
Sep 02 01:34:45 AM UTC 24 |
Sep 02 01:40:53 AM UTC 24 |
36897856163 ps |
| T2538 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/81.xbar_random.3069127331 |
|
|
Sep 02 01:39:54 AM UTC 24 |
Sep 02 01:40:53 AM UTC 24 |
1365198656 ps |
| T2539 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/81.xbar_same_source.2126927609 |
|
|
Sep 02 01:40:17 AM UTC 24 |
Sep 02 01:40:58 AM UTC 24 |
407626241 ps |
| T2540 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/82.xbar_smoke.4264592938 |
|
|
Sep 02 01:40:53 AM UTC 24 |
Sep 02 01:41:03 AM UTC 24 |
51016018 ps |
| T2541 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/82.xbar_smoke_zero_delays.4087862822 |
|
|
Sep 02 01:40:55 AM UTC 24 |
Sep 02 01:41:04 AM UTC 24 |
45100474 ps |
| T2542 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/80.xbar_stress_all_with_reset_error.2646098174 |
|
|
Sep 02 01:39:38 AM UTC 24 |
Sep 02 01:41:12 AM UTC 24 |
579394976 ps |
| T2543 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/78.xbar_stress_all_with_rand_reset.927649507 |
|
|
Sep 02 01:36:45 AM UTC 24 |
Sep 02 01:41:17 AM UTC 24 |
1199870418 ps |
| T2544 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/80.xbar_random_slow_rsp.2082332149 |
|
|
Sep 02 01:38:27 AM UTC 24 |
Sep 02 01:41:19 AM UTC 24 |
7648559477 ps |
| T2545 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/80.xbar_stress_all_with_rand_reset.186263185 |
|
|
Sep 02 01:39:29 AM UTC 24 |
Sep 02 01:41:27 AM UTC 24 |
228566672 ps |
| T2546 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/81.xbar_smoke_large_delays.66390423 |
|
|
Sep 02 01:39:46 AM UTC 24 |
Sep 02 01:41:30 AM UTC 24 |
8842763931 ps |
| T2547 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/81.xbar_error_and_unmapped_addr.554223023 |
|
|
Sep 02 01:40:22 AM UTC 24 |
Sep 02 01:41:30 AM UTC 24 |
1328334976 ps |
| T2548 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/81.xbar_stress_all_with_error.3468665643 |
|
|
Sep 02 01:40:46 AM UTC 24 |
Sep 02 01:41:31 AM UTC 24 |
890302270 ps |
| T2549 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/82.xbar_random.306387700 |
|
|
Sep 02 01:41:07 AM UTC 24 |
Sep 02 01:41:45 AM UTC 24 |
689559229 ps |
| T2550 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/81.xbar_error_random.2015996842 |
|
|
Sep 02 01:40:22 AM UTC 24 |
Sep 02 01:41:45 AM UTC 24 |
2484849173 ps |
| T2551 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/81.xbar_access_same_device.1357559918 |
|
|
Sep 02 01:40:14 AM UTC 24 |
Sep 02 01:41:52 AM UTC 24 |
2477570531 ps |
| T2552 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/82.xbar_error_random.2494284599 |
|
|
Sep 02 01:41:28 AM UTC 24 |
Sep 02 01:41:55 AM UTC 24 |
486616893 ps |
| T2553 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/82.xbar_same_source.1667469502 |
|
|
Sep 02 01:41:26 AM UTC 24 |
Sep 02 01:41:55 AM UTC 24 |
837619510 ps |
| T2554 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/81.xbar_smoke_slow_rsp.1150442827 |
|
|
Sep 02 01:39:52 AM UTC 24 |
Sep 02 01:41:55 AM UTC 24 |
6141451709 ps |
| T2555 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/83.xbar_smoke.287854482 |
|
|
Sep 02 01:41:54 AM UTC 24 |
Sep 02 01:42:03 AM UTC 24 |
42771762 ps |
| T2556 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/82.xbar_error_and_unmapped_addr.280533907 |
|
|
Sep 02 01:41:40 AM UTC 24 |
Sep 02 01:42:05 AM UTC 24 |
187832251 ps |
| T2557 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/82.xbar_random_zero_delays.2319543322 |
|
|
Sep 02 01:41:11 AM UTC 24 |
Sep 02 01:42:12 AM UTC 24 |
482282471 ps |
| T2558 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/82.xbar_unmapped_addr.225652797 |
|
|
Sep 02 01:41:35 AM UTC 24 |
Sep 02 01:42:17 AM UTC 24 |
669391942 ps |
| T2559 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/83.xbar_smoke_zero_delays.2267774222 |
|
|
Sep 02 01:42:07 AM UTC 24 |
Sep 02 01:42:18 AM UTC 24 |
55560861 ps |
| T2560 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/80.xbar_stress_all.1091987158 |
|
|
Sep 02 01:39:16 AM UTC 24 |
Sep 02 01:42:20 AM UTC 24 |
1723924642 ps |
| T2561 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/74.xbar_random_large_delays.1838583905 |
|
|
Sep 02 01:31:14 AM UTC 24 |
Sep 02 01:42:21 AM UTC 24 |
46452616517 ps |
| T2562 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/82.xbar_smoke_slow_rsp.3167477137 |
|
|
Sep 02 01:41:05 AM UTC 24 |
Sep 02 01:42:24 AM UTC 24 |
4812340500 ps |
| T2563 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/81.xbar_stress_all_with_reset_error.3255376732 |
|
|
Sep 02 01:40:50 AM UTC 24 |
Sep 02 01:42:26 AM UTC 24 |
226023750 ps |
| T2564 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/82.xbar_access_same_device.2671909212 |
|
|
Sep 02 01:41:16 AM UTC 24 |
Sep 02 01:42:35 AM UTC 24 |
1825009219 ps |
| T2565 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/80.xbar_stress_all_with_error.3567624553 |
|
|
Sep 02 01:39:37 AM UTC 24 |
Sep 02 01:42:38 AM UTC 24 |
1968802462 ps |
| T2566 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/83.xbar_random_zero_delays.696186003 |
|
|
Sep 02 01:42:19 AM UTC 24 |
Sep 02 01:42:53 AM UTC 24 |
387074500 ps |
| T2567 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/82.xbar_smoke_large_delays.1031445965 |
|
|
Sep 02 01:40:56 AM UTC 24 |
Sep 02 01:42:53 AM UTC 24 |
8594161657 ps |
| T2568 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/83.xbar_random.966708569 |
|
|
Sep 02 01:42:17 AM UTC 24 |
Sep 02 01:43:04 AM UTC 24 |
401334833 ps |
| T2569 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/83.xbar_error_random.2727239070 |
|
|
Sep 02 01:42:42 AM UTC 24 |
Sep 02 01:43:09 AM UTC 24 |
456831027 ps |
| T2570 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/77.xbar_stress_all_with_error.2960447971 |
|
|
Sep 02 01:35:27 AM UTC 24 |
Sep 02 01:43:13 AM UTC 24 |
12362422037 ps |
| T2571 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/81.xbar_random_slow_rsp.3547934061 |
|
|
Sep 02 01:40:13 AM UTC 24 |
Sep 02 01:43:23 AM UTC 24 |
13495245800 ps |
| T2572 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/84.xbar_smoke_zero_delays.2195745667 |
|
|
Sep 02 01:43:15 AM UTC 24 |
Sep 02 01:43:26 AM UTC 24 |
49515933 ps |
| T2573 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/84.xbar_smoke.2717267781 |
|
|
Sep 02 01:43:16 AM UTC 24 |
Sep 02 01:43:29 AM UTC 24 |
168943736 ps |
| T2574 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/83.xbar_access_same_device.1711394135 |
|
|
Sep 02 01:42:28 AM UTC 24 |
Sep 02 01:43:31 AM UTC 24 |
1489443892 ps |
| T2575 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/83.xbar_unmapped_addr.547064303 |
|
|
Sep 02 01:42:41 AM UTC 24 |
Sep 02 01:43:34 AM UTC 24 |
862852133 ps |
| T2576 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/83.xbar_smoke_slow_rsp.3748500279 |
|
|
Sep 02 01:42:16 AM UTC 24 |
Sep 02 01:43:39 AM UTC 24 |
3598054842 ps |
| T2577 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/82.xbar_stress_all_with_reset_error.4248343983 |
|
|
Sep 02 01:41:54 AM UTC 24 |
Sep 02 01:43:43 AM UTC 24 |
302581763 ps |
| T2578 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/75.xbar_access_same_device_slow_rsp.1053317415 |
|
|
Sep 02 01:32:38 AM UTC 24 |
Sep 02 01:43:47 AM UTC 24 |
32589663657 ps |
| T2579 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/83.xbar_error_and_unmapped_addr.3881346767 |
|
|
Sep 02 01:42:45 AM UTC 24 |
Sep 02 01:43:52 AM UTC 24 |
1226461901 ps |
| T2580 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/80.xbar_random_large_delays.4229054326 |
|
|
Sep 02 01:38:24 AM UTC 24 |
Sep 02 01:43:54 AM UTC 24 |
28513989605 ps |
| T2581 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/72.xbar_random_slow_rsp.3068192624 |
|
|
Sep 02 01:28:39 AM UTC 24 |
Sep 02 01:43:57 AM UTC 24 |
56194323906 ps |
| T2582 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/84.xbar_random_zero_delays.2381165442 |
|
|
Sep 02 01:43:46 AM UTC 24 |
Sep 02 01:44:02 AM UTC 24 |
90274459 ps |
| T2583 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/71.xbar_random_large_delays.4009871244 |
|
|
Sep 02 01:27:09 AM UTC 24 |
Sep 02 01:44:03 AM UTC 24 |
86628526635 ps |
| T2584 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/83.xbar_smoke_large_delays.2641256268 |
|
|
Sep 02 01:42:09 AM UTC 24 |
Sep 02 01:44:05 AM UTC 24 |
8100291769 ps |
| T2585 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/71.xbar_random_slow_rsp.731320330 |
|
|
Sep 02 01:27:13 AM UTC 24 |
Sep 02 01:44:14 AM UTC 24 |
58065182159 ps |
| T2586 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/69.xbar_random_large_delays.4069292400 |
|
|
Sep 02 01:24:32 AM UTC 24 |
Sep 02 01:44:14 AM UTC 24 |
98597023562 ps |
| T2587 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/79.xbar_random_large_delays.330483504 |
|
|
Sep 02 01:37:11 AM UTC 24 |
Sep 02 01:44:15 AM UTC 24 |
28835235798 ps |
| T2588 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/84.xbar_same_source.2983166658 |
|
|
Sep 02 01:44:03 AM UTC 24 |
Sep 02 01:44:16 AM UTC 24 |
71317618 ps |
| T2589 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/83.xbar_same_source.1660454054 |
|
|
Sep 02 01:42:41 AM UTC 24 |
Sep 02 01:44:21 AM UTC 24 |
2330948756 ps |
| T2590 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/74.xbar_random_slow_rsp.743008906 |
|
|
Sep 02 01:31:18 AM UTC 24 |
Sep 02 01:44:31 AM UTC 24 |
45781616904 ps |
| T2591 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/85.xbar_smoke.4042428959 |
|
|
Sep 02 01:44:27 AM UTC 24 |
Sep 02 01:44:36 AM UTC 24 |
161535826 ps |
| T2592 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/85.xbar_smoke_zero_delays.1699419385 |
|
|
Sep 02 01:44:28 AM UTC 24 |
Sep 02 01:44:38 AM UTC 24 |
42370678 ps |
| T2593 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/84.xbar_error_and_unmapped_addr.2143859674 |
|
|
Sep 02 01:44:10 AM UTC 24 |
Sep 02 01:44:54 AM UTC 24 |
1076860389 ps |
| T2594 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/79.xbar_random_slow_rsp.2127218864 |
|
|
Sep 02 01:37:13 AM UTC 24 |
Sep 02 01:44:55 AM UTC 24 |
31887385845 ps |
| T2595 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/85.xbar_random.1320111320 |
|
|
Sep 02 01:44:38 AM UTC 24 |
Sep 02 01:45:13 AM UTC 24 |
262368866 ps |
| T2596 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/84.xbar_unmapped_addr.3935804205 |
|
|
Sep 02 01:44:10 AM UTC 24 |
Sep 02 01:45:14 AM UTC 24 |
1240317855 ps |
| T2597 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/84.xbar_smoke_slow_rsp.595877276 |
|
|
Sep 02 01:43:32 AM UTC 24 |
Sep 02 01:45:14 AM UTC 24 |
4804775490 ps |
| T2598 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/84.xbar_random_large_delays.892581508 |
|
|
Sep 02 01:43:48 AM UTC 24 |
Sep 02 01:45:16 AM UTC 24 |
8087345329 ps |
| T2599 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/82.xbar_stress_all_with_error.3376050373 |
|
|
Sep 02 01:41:52 AM UTC 24 |
Sep 02 01:45:25 AM UTC 24 |
2228293550 ps |
| T2600 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/84.xbar_smoke_large_delays.848871417 |
|
|
Sep 02 01:43:26 AM UTC 24 |
Sep 02 01:45:28 AM UTC 24 |
10204332260 ps |
| T2601 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/85.xbar_access_same_device.3293679900 |
|
|
Sep 02 01:44:59 AM UTC 24 |
Sep 02 01:45:35 AM UTC 24 |
568480940 ps |
| T2602 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/85.xbar_error_random.320145616 |
|
|
Sep 02 01:45:17 AM UTC 24 |
Sep 02 01:45:37 AM UTC 24 |
339745203 ps |
| T2603 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/84.xbar_error_random.1000190836 |
|
|
Sep 02 01:44:07 AM UTC 24 |
Sep 02 01:45:42 AM UTC 24 |
1789326155 ps |
| T2604 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/74.xbar_stress_all.501082414 |
|
|
Sep 02 01:31:48 AM UTC 24 |
Sep 02 01:45:44 AM UTC 24 |
20023871891 ps |
| T2605 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/85.xbar_random_zero_delays.3105563889 |
|
|
Sep 02 01:44:38 AM UTC 24 |
Sep 02 01:45:51 AM UTC 24 |
585899258 ps |
| T2606 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/85.xbar_error_and_unmapped_addr.1228314061 |
|
|
Sep 02 01:45:37 AM UTC 24 |
Sep 02 01:46:05 AM UTC 24 |
161877723 ps |
| T2607 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/85.xbar_unmapped_addr.2206988636 |
|
|
Sep 02 01:45:38 AM UTC 24 |
Sep 02 01:46:09 AM UTC 24 |
172860297 ps |
| T2608 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/85.xbar_same_source.475454263 |
|
|
Sep 02 01:45:18 AM UTC 24 |
Sep 02 01:46:09 AM UTC 24 |
1519123824 ps |
| T2609 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/86.xbar_smoke_zero_delays.4086172968 |
|
|
Sep 02 01:46:00 AM UTC 24 |
Sep 02 01:46:10 AM UTC 24 |
40835151 ps |
| T2610 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/86.xbar_smoke.2274110547 |
|
|
Sep 02 01:45:58 AM UTC 24 |
Sep 02 01:46:12 AM UTC 24 |
182672867 ps |
| T2611 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/3.chip_csr_bit_bash.1300963945 |
|
|
Sep 01 11:30:34 PM UTC 24 |
Sep 02 01:46:19 AM UTC 24 |
81291980768 ps |
| T2612 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/86.xbar_random.1987236968 |
|
|
Sep 02 01:46:11 AM UTC 24 |
Sep 02 01:46:20 AM UTC 24 |
37325772 ps |
| T2613 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/85.xbar_stress_all.17729995 |
|
|
Sep 02 01:45:39 AM UTC 24 |
Sep 02 01:46:26 AM UTC 24 |
481323375 ps |
| T2614 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/84.xbar_access_same_device.3789140509 |
|
|
Sep 02 01:43:54 AM UTC 24 |
Sep 02 01:46:27 AM UTC 24 |
2685832487 ps |
| T2615 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/85.xbar_smoke_slow_rsp.1159525417 |
|
|
Sep 02 01:44:36 AM UTC 24 |
Sep 02 01:46:30 AM UTC 24 |
5148186055 ps |
| T2616 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/77.xbar_stress_all_with_reset_error.2600526598 |
|
|
Sep 02 01:35:31 AM UTC 24 |
Sep 02 01:46:37 AM UTC 24 |
14179455330 ps |
| T2617 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/83.xbar_stress_all_with_error.175336738 |
|
|
Sep 02 01:42:57 AM UTC 24 |
Sep 02 01:46:38 AM UTC 24 |
2849656447 ps |
| T2618 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/85.xbar_smoke_large_delays.2555115278 |
|
|
Sep 02 01:44:30 AM UTC 24 |
Sep 02 01:46:41 AM UTC 24 |
9849400430 ps |
| T2619 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/83.xbar_stress_all_with_rand_reset.3129306586 |
|
|
Sep 02 01:42:49 AM UTC 24 |
Sep 02 01:46:53 AM UTC 24 |
1391351465 ps |
| T2620 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/86.xbar_same_source.2832255846 |
|
|
Sep 02 01:46:40 AM UTC 24 |
Sep 02 01:47:02 AM UTC 24 |
421009227 ps |
| T2621 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/78.xbar_random_large_delays.3975626028 |
|
|
Sep 02 01:35:58 AM UTC 24 |
Sep 02 01:47:04 AM UTC 24 |
56564670876 ps |
| T2622 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/86.xbar_error_and_unmapped_addr.2966406925 |
|
|
Sep 02 01:46:50 AM UTC 24 |
Sep 02 01:47:05 AM UTC 24 |
88164082 ps |
| T2623 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/1.chip_csr_aliasing.579476788 |
|
|
Sep 01 11:27:17 PM UTC 24 |
Sep 02 01:47:12 AM UTC 24 |
41092253787 ps |
| T2624 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/62.xbar_access_same_device_slow_rsp.3208906852 |
|
|
Sep 02 01:14:50 AM UTC 24 |
Sep 02 01:47:13 AM UTC 24 |
126403488011 ps |
| T2625 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/86.xbar_random_zero_delays.3837403359 |
|
|
Sep 02 01:46:28 AM UTC 24 |
Sep 02 01:47:16 AM UTC 24 |
397635297 ps |
| T2626 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/84.xbar_stress_all_with_error.213672476 |
|
|
Sep 02 01:44:19 AM UTC 24 |
Sep 02 01:47:17 AM UTC 24 |
2552076537 ps |
| T2627 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/86.xbar_access_same_device.3310747125 |
|
|
Sep 02 01:46:33 AM UTC 24 |
Sep 02 01:47:20 AM UTC 24 |
853475526 ps |
| T2628 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/87.xbar_smoke.1980366679 |
|
|
Sep 02 01:47:17 AM UTC 24 |
Sep 02 01:47:26 AM UTC 24 |
45773078 ps |
| T2629 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/86.xbar_stress_all_with_reset_error.1798475809 |
|
|
Sep 02 01:47:05 AM UTC 24 |
Sep 02 01:47:26 AM UTC 24 |
23810792 ps |
| T2630 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/85.xbar_stress_all_with_reset_error.1699706505 |
|
|
Sep 02 01:45:52 AM UTC 24 |
Sep 02 01:47:27 AM UTC 24 |
299732329 ps |
| T2631 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/86.xbar_smoke_slow_rsp.4154119217 |
|
|
Sep 02 01:46:09 AM UTC 24 |
Sep 02 01:47:30 AM UTC 24 |
3902161364 ps |
| T2632 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/63.xbar_access_same_device_slow_rsp.4171020101 |
|
|
Sep 02 01:16:16 AM UTC 24 |
Sep 02 01:47:34 AM UTC 24 |
120830312077 ps |
| T2633 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/87.xbar_smoke_zero_delays.4106405516 |
|
|
Sep 02 01:47:27 AM UTC 24 |
Sep 02 01:47:37 AM UTC 24 |
48035160 ps |
| T2634 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/86.xbar_error_random.2941227545 |
|
|
Sep 02 01:46:44 AM UTC 24 |
Sep 02 01:47:40 AM UTC 24 |
633819373 ps |
| T2635 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/88.xbar_random_zero_delays.1604756309 |
|
|
Sep 02 01:48:24 AM UTC 24 |
Sep 02 01:48:36 AM UTC 24 |
94231281 ps |
| T2636 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/86.xbar_unmapped_addr.460536178 |
|
|
Sep 02 01:46:50 AM UTC 24 |
Sep 02 01:47:47 AM UTC 24 |
1101778241 ps |
| T2637 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/86.xbar_smoke_large_delays.4255763075 |
|
|
Sep 02 01:46:05 AM UTC 24 |
Sep 02 01:47:48 AM UTC 24 |
7380584086 ps |
| T2638 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/81.xbar_access_same_device_slow_rsp.3232936848 |
|
|
Sep 02 01:40:16 AM UTC 24 |
Sep 02 01:47:50 AM UTC 24 |
22343748251 ps |
| T2639 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/78.xbar_stress_all_with_reset_error.3984296881 |
|
|
Sep 02 01:36:48 AM UTC 24 |
Sep 02 01:47:50 AM UTC 24 |
12577222515 ps |
| T2640 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/81.xbar_stress_all_with_rand_reset.3030224756 |
|
|
Sep 02 01:40:38 AM UTC 24 |
Sep 02 01:47:55 AM UTC 24 |
927424570 ps |
| T2641 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/82.xbar_stress_all.2395847675 |
|
|
Sep 02 01:41:42 AM UTC 24 |
Sep 02 01:47:55 AM UTC 24 |
7965297435 ps |
| T2642 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/80.xbar_access_same_device_slow_rsp.1189776567 |
|
|
Sep 02 01:38:33 AM UTC 24 |
Sep 02 01:48:00 AM UTC 24 |
33006939280 ps |
| T2643 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/76.xbar_random_large_delays.1971841021 |
|
|
Sep 02 01:33:29 AM UTC 24 |
Sep 02 01:48:01 AM UTC 24 |
82201229220 ps |
| T2644 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/74.xbar_access_same_device_slow_rsp.402732821 |
|
|
Sep 02 01:31:19 AM UTC 24 |
Sep 02 01:48:03 AM UTC 24 |
48511412600 ps |
| T2645 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/87.xbar_error_and_unmapped_addr.2532317372 |
|
|
Sep 02 01:47:56 AM UTC 24 |
Sep 02 01:48:04 AM UTC 24 |
18579374 ps |
| T2646 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/87.xbar_unmapped_addr.358575006 |
|
|
Sep 02 01:47:53 AM UTC 24 |
Sep 02 01:48:16 AM UTC 24 |
286557261 ps |
| T2647 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/84.xbar_stress_all_with_rand_reset.146893613 |
|
|
Sep 02 01:44:17 AM UTC 24 |
Sep 02 01:48:18 AM UTC 24 |
1773747572 ps |
| T2648 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/76.xbar_random_slow_rsp.55086932 |
|
|
Sep 02 01:33:37 AM UTC 24 |
Sep 02 01:48:22 AM UTC 24 |
54514466234 ps |
| T2649 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/88.xbar_smoke_zero_delays.3494914088 |
|
|
Sep 02 01:48:14 AM UTC 24 |
Sep 02 01:48:25 AM UTC 24 |
48705939 ps |
| T2650 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/88.xbar_smoke.3001972489 |
|
|
Sep 02 01:48:12 AM UTC 24 |
Sep 02 01:48:26 AM UTC 24 |
151941932 ps |
| T2651 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/87.xbar_random_zero_delays.416427066 |
|
|
Sep 02 01:47:34 AM UTC 24 |
Sep 02 01:48:29 AM UTC 24 |
433141387 ps |
| T2652 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/84.xbar_stress_all_with_reset_error.1560203829 |
|
|
Sep 02 01:44:25 AM UTC 24 |
Sep 02 01:48:31 AM UTC 24 |
851439952 ps |
| T2653 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/87.xbar_smoke_large_delays.4240774695 |
|
|
Sep 02 01:47:27 AM UTC 24 |
Sep 02 01:48:40 AM UTC 24 |
7373243880 ps |
| T2654 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/88.xbar_random.80719865 |
|
|
Sep 02 01:48:22 AM UTC 24 |
Sep 02 01:48:45 AM UTC 24 |
158746960 ps |
| T2655 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/87.xbar_random.2529642618 |
|
|
Sep 02 01:47:35 AM UTC 24 |
Sep 02 01:48:46 AM UTC 24 |
568477599 ps |
| T2656 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/82.xbar_stress_all_with_rand_reset.540086288 |
|
|
Sep 02 01:41:50 AM UTC 24 |
Sep 02 01:48:48 AM UTC 24 |
3288004714 ps |
| T2657 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/81.xbar_stress_all.2156587021 |
|
|
Sep 02 01:40:27 AM UTC 24 |
Sep 02 01:48:52 AM UTC 24 |
12370091258 ps |
| T2658 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/87.xbar_error_random.195878309 |
|
|
Sep 02 01:47:51 AM UTC 24 |
Sep 02 01:48:52 AM UTC 24 |
590394343 ps |
| T2659 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/79.xbar_stress_all_with_reset_error.1094320422 |
|
|
Sep 02 01:37:42 AM UTC 24 |
Sep 02 01:48:59 AM UTC 24 |
9576499443 ps |
| T2660 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/87.xbar_smoke_slow_rsp.1987148221 |
|
|
Sep 02 01:47:28 AM UTC 24 |
Sep 02 01:48:59 AM UTC 24 |
4977866297 ps |
| T2661 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/86.xbar_stress_all_with_error.3735928798 |
|
|
Sep 02 01:47:01 AM UTC 24 |
Sep 02 01:49:03 AM UTC 24 |
3522891271 ps |
| T2662 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/87.xbar_access_same_device.3842733989 |
|
|
Sep 02 01:47:43 AM UTC 24 |
Sep 02 01:49:03 AM UTC 24 |
1681596194 ps |
| T2663 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/88.xbar_same_source.4156050712 |
|
|
Sep 02 01:48:42 AM UTC 24 |
Sep 02 01:49:07 AM UTC 24 |
190246491 ps |
| T2664 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/83.xbar_stress_all.3947931198 |
|
|
Sep 02 01:42:47 AM UTC 24 |
Sep 02 01:49:12 AM UTC 24 |
8112112582 ps |
| T2665 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/87.xbar_same_source.2346834422 |
|
|
Sep 02 01:47:51 AM UTC 24 |
Sep 02 01:49:12 AM UTC 24 |
2245336216 ps |
| T2666 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/83.xbar_random_slow_rsp.304418762 |
|
|
Sep 02 01:42:28 AM UTC 24 |
Sep 02 01:49:16 AM UTC 24 |
25978251675 ps |
| T2667 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/89.xbar_smoke_zero_delays.896973728 |
|
|
Sep 02 01:49:11 AM UTC 24 |
Sep 02 01:49:18 AM UTC 24 |
43421264 ps |
| T2668 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/89.xbar_smoke.3253219986 |
|
|
Sep 02 01:49:07 AM UTC 24 |
Sep 02 01:49:21 AM UTC 24 |
203502912 ps |
| T2669 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/87.xbar_stress_all_with_error.954182225 |
|
|
Sep 02 01:48:08 AM UTC 24 |
Sep 02 01:49:24 AM UTC 24 |
2138981273 ps |
| T2670 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/88.xbar_access_same_device.3659822625 |
|
|
Sep 02 01:48:38 AM UTC 24 |
Sep 02 01:49:32 AM UTC 24 |
940273042 ps |
| T2671 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/87.xbar_stress_all_with_reset_error.1406898324 |
|
|
Sep 02 01:48:12 AM UTC 24 |
Sep 02 01:49:35 AM UTC 24 |
243112380 ps |
| T2672 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/88.xbar_error_and_unmapped_addr.943329133 |
|
|
Sep 02 01:48:51 AM UTC 24 |
Sep 02 01:49:37 AM UTC 24 |
816045514 ps |
| T2673 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/88.xbar_unmapped_addr.596097295 |
|
|
Sep 02 01:48:47 AM UTC 24 |
Sep 02 01:49:40 AM UTC 24 |
1196592492 ps |
| T2674 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/88.xbar_error_random.604335674 |
|
|
Sep 02 01:48:48 AM UTC 24 |
Sep 02 01:49:49 AM UTC 24 |
631985767 ps |
| T2675 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/89.xbar_same_source.130553227 |
|
|
Sep 02 01:49:36 AM UTC 24 |
Sep 02 01:49:51 AM UTC 24 |
88992611 ps |
| T2676 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/84.xbar_stress_all.3179212082 |
|
|
Sep 02 01:44:15 AM UTC 24 |
Sep 02 01:49:55 AM UTC 24 |
8720215511 ps |
| T2677 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/89.xbar_error_and_unmapped_addr.49638864 |
|
|
Sep 02 01:49:45 AM UTC 24 |
Sep 02 01:49:58 AM UTC 24 |
63725123 ps |
| T2678 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/89.xbar_unmapped_addr.2067676077 |
|
|
Sep 02 01:49:42 AM UTC 24 |
Sep 02 01:50:10 AM UTC 24 |
522571461 ps |
| T2679 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/89.xbar_random_zero_delays.1975268989 |
|
|
Sep 02 01:49:23 AM UTC 24 |
Sep 02 01:50:13 AM UTC 24 |
501936122 ps |
| T2680 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/86.xbar_stress_all_with_rand_reset.438767279 |
|
|
Sep 02 01:47:01 AM UTC 24 |
Sep 02 01:50:14 AM UTC 24 |
252636951 ps |
| T2681 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/90.xbar_smoke.3024635709 |
|
|
Sep 02 01:50:05 AM UTC 24 |
Sep 02 01:50:14 AM UTC 24 |
174847658 ps |
| T2682 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/88.xbar_smoke_slow_rsp.1373066631 |
|
|
Sep 02 01:48:19 AM UTC 24 |
Sep 02 01:50:18 AM UTC 24 |
5837942157 ps |
| T2683 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/89.xbar_stress_all.966596670 |
|
|
Sep 02 01:49:47 AM UTC 24 |
Sep 02 01:50:18 AM UTC 24 |
710742526 ps |
| T2684 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/89.xbar_access_same_device.2611608582 |
|
|
Sep 02 01:49:30 AM UTC 24 |
Sep 02 01:50:21 AM UTC 24 |
1003840744 ps |
| T2685 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/90.xbar_smoke_zero_delays.3255292493 |
|
|
Sep 02 01:50:11 AM UTC 24 |
Sep 02 01:50:21 AM UTC 24 |
56599647 ps |
| T2686 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/86.xbar_stress_all.3959727334 |
|
|
Sep 02 01:46:55 AM UTC 24 |
Sep 02 01:50:21 AM UTC 24 |
5232842193 ps |
| T2687 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/88.xbar_smoke_large_delays.1799448504 |
|
|
Sep 02 01:48:19 AM UTC 24 |
Sep 02 01:50:25 AM UTC 24 |
7141920815 ps |
| T2688 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/76.xbar_access_same_device_slow_rsp.3282305929 |
|
|
Sep 02 01:33:42 AM UTC 24 |
Sep 02 01:50:27 AM UTC 24 |
55591877329 ps |
| T2689 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/75.xbar_stress_all_with_rand_reset.2753678806 |
|
|
Sep 02 01:32:51 AM UTC 24 |
Sep 02 01:50:36 AM UTC 24 |
17536899454 ps |
| T2690 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/87.xbar_stress_all_with_rand_reset.895505833 |
|
|
Sep 02 01:48:02 AM UTC 24 |
Sep 02 01:50:37 AM UTC 24 |
330782555 ps |
| T2691 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/89.xbar_random.3490793376 |
|
|
Sep 02 01:49:23 AM UTC 24 |
Sep 02 01:50:40 AM UTC 24 |
2399905230 ps |
| T2692 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/89.xbar_smoke_slow_rsp.4152394767 |
|
|
Sep 02 01:49:12 AM UTC 24 |
Sep 02 01:50:42 AM UTC 24 |
5723180410 ps |
| T2693 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/88.xbar_stress_all.2923294105 |
|
|
Sep 02 01:48:54 AM UTC 24 |
Sep 02 01:50:48 AM UTC 24 |
2272831262 ps |
| T2694 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/90.xbar_random.3865103651 |
|
|
Sep 02 01:50:21 AM UTC 24 |
Sep 02 01:50:58 AM UTC 24 |
625079079 ps |
| T2695 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/82.xbar_access_same_device_slow_rsp.1992293257 |
|
|
Sep 02 01:41:21 AM UTC 24 |
Sep 02 01:50:58 AM UTC 24 |
33782221749 ps |
| T2696 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/83.xbar_stress_all_with_reset_error.1359806235 |
|
|
Sep 02 01:43:02 AM UTC 24 |
Sep 02 01:51:04 AM UTC 24 |
7545302325 ps |
| T2697 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/90.xbar_unmapped_addr.173452293 |
|
|
Sep 02 01:50:44 AM UTC 24 |
Sep 02 01:51:04 AM UTC 24 |
341179490 ps |
| T2698 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/89.xbar_smoke_large_delays.2062998028 |
|
|
Sep 02 01:49:16 AM UTC 24 |
Sep 02 01:51:13 AM UTC 24 |
6967934582 ps |
| T2699 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/90.xbar_error_random.2400374886 |
|
|
Sep 02 01:50:44 AM UTC 24 |
Sep 02 01:51:13 AM UTC 24 |
695102619 ps |
| T2700 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/89.xbar_error_random.2106608724 |
|
|
Sep 02 01:49:39 AM UTC 24 |
Sep 02 01:51:15 AM UTC 24 |
2415654529 ps |
| T2701 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/91.xbar_smoke_zero_delays.3510074613 |
|
|
Sep 02 01:51:05 AM UTC 24 |
Sep 02 01:51:16 AM UTC 24 |
43639403 ps |
| T2702 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/91.xbar_smoke.608240110 |
|
|
Sep 02 01:51:06 AM UTC 24 |
Sep 02 01:51:17 AM UTC 24 |
47902240 ps |
| T2703 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/90.xbar_error_and_unmapped_addr.3510717739 |
|
|
Sep 02 01:50:45 AM UTC 24 |
Sep 02 01:51:23 AM UTC 24 |
241950474 ps |
| T2704 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/90.xbar_same_source.114306972 |
|
|
Sep 02 01:50:39 AM UTC 24 |
Sep 02 01:51:27 AM UTC 24 |
465339819 ps |
| T2705 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/90.xbar_random_zero_delays.1018499690 |
|
|
Sep 02 01:50:34 AM UTC 24 |
Sep 02 01:51:43 AM UTC 24 |
648692256 ps |
| T2706 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/91.xbar_random_zero_delays.1452490555 |
|
|
Sep 02 01:51:26 AM UTC 24 |
Sep 02 01:51:54 AM UTC 24 |
192793935 ps |
| T2707 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/90.xbar_smoke_slow_rsp.3136343818 |
|
|
Sep 02 01:50:18 AM UTC 24 |
Sep 02 01:51:54 AM UTC 24 |
4375600198 ps |
| T2708 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/91.xbar_error_random.1738687547 |
|
|
Sep 02 01:51:39 AM UTC 24 |
Sep 02 01:51:56 AM UTC 24 |
139520400 ps |
| T2709 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/91.xbar_access_same_device.1133569168 |
|
|
Sep 02 01:51:37 AM UTC 24 |
Sep 02 01:51:58 AM UTC 24 |
160060689 ps |
| T2710 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/91.xbar_random.2831355756 |
|
|
Sep 02 01:51:18 AM UTC 24 |
Sep 02 01:52:13 AM UTC 24 |
1087878903 ps |
| T2711 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/90.xbar_access_same_device.1573609245 |
|
|
Sep 02 01:50:35 AM UTC 24 |
Sep 02 01:52:18 AM UTC 24 |
1636640143 ps |
| T2712 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/90.xbar_stress_all_with_error.868983052 |
|
|
Sep 02 01:50:59 AM UTC 24 |
Sep 02 01:52:19 AM UTC 24 |
861333507 ps |
| T2713 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/90.xbar_smoke_large_delays.780082338 |
|
|
Sep 02 01:50:13 AM UTC 24 |
Sep 02 01:52:24 AM UTC 24 |
10169637032 ps |
| T2714 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/91.xbar_unmapped_addr.1745820964 |
|
|
Sep 02 01:51:47 AM UTC 24 |
Sep 02 01:52:31 AM UTC 24 |
253530532 ps |
| T2715 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/92.xbar_smoke.736992283 |
|
|
Sep 02 01:52:22 AM UTC 24 |
Sep 02 01:52:31 AM UTC 24 |
163608006 ps |
| T2716 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/84.xbar_random_slow_rsp.2487057548 |
|
|
Sep 02 01:43:53 AM UTC 24 |
Sep 02 01:52:33 AM UTC 24 |
34073155782 ps |
| T2717 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/91.xbar_same_source.2681655543 |
|
|
Sep 02 01:51:36 AM UTC 24 |
Sep 02 01:52:35 AM UTC 24 |
576602051 ps |
| T2718 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/90.xbar_stress_all_with_rand_reset.1830154779 |
|
|
Sep 02 01:50:51 AM UTC 24 |
Sep 02 01:52:40 AM UTC 24 |
191589543 ps |
| T2719 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/91.xbar_smoke_slow_rsp.3405613825 |
|
|
Sep 02 01:51:19 AM UTC 24 |
Sep 02 01:52:41 AM UTC 24 |
3565300136 ps |
| T2720 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/92.xbar_smoke_zero_delays.985252423 |
|
|
Sep 02 01:52:36 AM UTC 24 |
Sep 02 01:52:46 AM UTC 24 |
42274291 ps |
| T2721 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/91.xbar_error_and_unmapped_addr.1387399971 |
|
|
Sep 02 01:51:52 AM UTC 24 |
Sep 02 01:52:51 AM UTC 24 |
1025947653 ps |
| T2722 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/87.xbar_stress_all.1730604746 |
|
|
Sep 02 01:48:01 AM UTC 24 |
Sep 02 01:53:03 AM UTC 24 |
6456649349 ps |
| T2723 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/92.xbar_random.1443960303 |
|
|
Sep 02 01:52:48 AM UTC 24 |
Sep 02 01:53:16 AM UTC 24 |
468579807 ps |
| T2724 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/91.xbar_smoke_large_delays.1704544314 |
|
|
Sep 02 01:51:11 AM UTC 24 |
Sep 02 01:53:17 AM UTC 24 |
8555265073 ps |
| T2725 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/92.xbar_access_same_device.2133540706 |
|
|
Sep 02 01:52:58 AM UTC 24 |
Sep 02 01:53:20 AM UTC 24 |
296837156 ps |
| T2726 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/72.xbar_access_same_device_slow_rsp.1559180815 |
|
|
Sep 02 01:28:40 AM UTC 24 |
Sep 02 01:53:24 AM UTC 24 |
81512397919 ps |
| T2727 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/56.xbar_access_same_device_slow_rsp.528967754 |
|
|
Sep 02 01:06:58 AM UTC 24 |
Sep 02 01:53:26 AM UTC 24 |
143834767768 ps |
| T2728 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/85.xbar_stress_all_with_error.515466668 |
|
|
Sep 02 01:45:48 AM UTC 24 |
Sep 02 01:53:37 AM UTC 24 |
12442086866 ps |
| T2729 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/66.xbar_access_same_device_slow_rsp.2835136396 |
|
|
Sep 02 01:21:07 AM UTC 24 |
Sep 02 01:53:42 AM UTC 24 |
118337910723 ps |
| T2730 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/92.xbar_smoke_slow_rsp.1812000373 |
|
|
Sep 02 01:52:44 AM UTC 24 |
Sep 02 01:53:43 AM UTC 24 |
4261607490 ps |
| T2731 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/92.xbar_unmapped_addr.446228081 |
|
|
Sep 02 01:53:14 AM UTC 24 |
Sep 02 01:53:46 AM UTC 24 |
167857528 ps |
| T2732 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/93.xbar_smoke.2391409803 |
|
|
Sep 02 01:53:49 AM UTC 24 |
Sep 02 01:54:02 AM UTC 24 |
164170667 ps |
| T2733 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/92.xbar_random_zero_delays.1484041489 |
|
|
Sep 02 01:52:54 AM UTC 24 |
Sep 02 01:54:03 AM UTC 24 |
545447043 ps |
| T2734 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/91.xbar_stress_all_with_error.4103838485 |
|
|
Sep 02 01:52:18 AM UTC 24 |
Sep 02 01:54:04 AM UTC 24 |
2333360624 ps |
| T2735 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/92.xbar_error_random.1587021524 |
|
|
Sep 02 01:53:10 AM UTC 24 |
Sep 02 01:54:06 AM UTC 24 |
1763753248 ps |
| T2736 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/93.xbar_smoke_zero_delays.1054508702 |
|
|
Sep 02 01:54:01 AM UTC 24 |
Sep 02 01:54:11 AM UTC 24 |
43155468 ps |
| T2737 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/92.xbar_error_and_unmapped_addr.3859305030 |
|
|
Sep 02 01:53:26 AM UTC 24 |
Sep 02 01:54:12 AM UTC 24 |
984511128 ps |
| T2738 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/92.xbar_same_source.4000760340 |
|
|
Sep 02 01:53:02 AM UTC 24 |
Sep 02 01:54:15 AM UTC 24 |
2208257558 ps |
| T2739 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/77.xbar_random_slow_rsp.4146824757 |
|
|
Sep 02 01:34:47 AM UTC 24 |
Sep 02 01:54:30 AM UTC 24 |
72276066794 ps |
| T2740 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/92.xbar_smoke_large_delays.951084855 |
|
|
Sep 02 01:52:41 AM UTC 24 |
Sep 02 01:54:44 AM UTC 24 |
11166569895 ps |
| T2741 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/93.xbar_random_zero_delays.2131899173 |
|
|
Sep 02 01:54:25 AM UTC 24 |
Sep 02 01:54:47 AM UTC 24 |
126621213 ps |
| T2742 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/89.xbar_stress_all_with_rand_reset.351659084 |
|
|
Sep 02 01:49:56 AM UTC 24 |
Sep 02 01:54:52 AM UTC 24 |
2264483870 ps |
| T2743 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/92.xbar_stress_all.1028275808 |
|
|
Sep 02 01:53:39 AM UTC 24 |
Sep 02 01:54:59 AM UTC 24 |
748696417 ps |
| T2744 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/93.xbar_error_random.2315962450 |
|
|
Sep 02 01:54:39 AM UTC 24 |
Sep 02 01:55:20 AM UTC 24 |
1234445612 ps |
| T2745 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/93.xbar_random.3283385945 |
|
|
Sep 02 01:54:10 AM UTC 24 |
Sep 02 01:55:21 AM UTC 24 |
616357862 ps |
| T2746 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/93.xbar_error_and_unmapped_addr.736680709 |
|
|
Sep 02 01:55:08 AM UTC 24 |
Sep 02 01:55:22 AM UTC 24 |
159286270 ps |
| T2747 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/88.xbar_stress_all_with_error.1909626303 |
|
|
Sep 02 01:49:02 AM UTC 24 |
Sep 02 01:55:27 AM UTC 24 |
9507380923 ps |
| T2748 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/93.xbar_unmapped_addr.2307757785 |
|
|
Sep 02 01:54:54 AM UTC 24 |
Sep 02 01:55:28 AM UTC 24 |
196232988 ps |
| T2749 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/93.xbar_same_source.1537808720 |
|
|
Sep 02 01:54:35 AM UTC 24 |
Sep 02 01:55:31 AM UTC 24 |
532938644 ps |
| T2750 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/82.xbar_random_large_delays.3696599344 |
|
|
Sep 02 01:41:15 AM UTC 24 |
Sep 02 01:55:35 AM UTC 24 |
80360624150 ps |
| T2751 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/73.xbar_stress_all_with_rand_reset.3354077363 |
|
|
Sep 02 01:30:38 AM UTC 24 |
Sep 02 01:55:46 AM UTC 24 |
12443736597 ps |
| T2752 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/93.xbar_smoke_slow_rsp.2833539212 |
|
|
Sep 02 01:54:06 AM UTC 24 |
Sep 02 01:55:50 AM UTC 24 |
5069654796 ps |
| T2753 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/94.xbar_smoke_zero_delays.1835439357 |
|
|
Sep 02 01:55:43 AM UTC 24 |
Sep 02 01:55:54 AM UTC 24 |
54195828 ps |
| T2754 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/94.xbar_smoke.3521687892 |
|
|
Sep 02 01:55:46 AM UTC 24 |
Sep 02 01:55:56 AM UTC 24 |
185060480 ps |
| T2755 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/94.xbar_random.1497217015 |
|
|
Sep 02 01:55:54 AM UTC 24 |
Sep 02 01:56:04 AM UTC 24 |
37784563 ps |
| T2756 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/88.xbar_stress_all_with_reset_error.3335477321 |
|
|
Sep 02 01:49:07 AM UTC 24 |
Sep 02 01:56:15 AM UTC 24 |
4844784281 ps |
| T2757 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/93.xbar_smoke_large_delays.3217034780 |
|
|
Sep 02 01:54:05 AM UTC 24 |
Sep 02 01:56:20 AM UTC 24 |
8453748730 ps |
| T2758 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/85.xbar_stress_all_with_rand_reset.3888312069 |
|
|
Sep 02 01:45:40 AM UTC 24 |
Sep 02 01:56:24 AM UTC 24 |
9016623155 ps |
| T2759 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/90.xbar_stress_all.1900242340 |
|
|
Sep 02 01:50:47 AM UTC 24 |
Sep 02 01:56:26 AM UTC 24 |
9138395127 ps |
| T2760 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/94.xbar_random_zero_delays.295835893 |
|
|
Sep 02 01:55:59 AM UTC 24 |
Sep 02 01:56:26 AM UTC 24 |
179065839 ps |