| T1041 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_uart_tx_rx.1062487042 |
|
|
Sep 02 05:42:43 AM UTC 24 |
Sep 02 05:53:22 AM UTC 24 |
4570394152 ps |
| T1042 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_otbn_smoketest.3504218952 |
|
|
Sep 02 05:35:04 AM UTC 24 |
Sep 02 05:53:24 AM UTC 24 |
5754711322 ps |
| T44 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_spi_host_tx_rx.3181737763 |
|
|
Sep 02 05:47:10 AM UTC 24 |
Sep 02 05:53:46 AM UTC 24 |
3250652776 ps |
| T71 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_sleep_pin_wake.2134903136 |
|
|
Sep 02 05:42:43 AM UTC 24 |
Sep 02 05:54:24 AM UTC 24 |
6363758956 ps |
| T1043 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_uart_tx_rx_idx3.139474080 |
|
|
Sep 02 05:43:32 AM UTC 24 |
Sep 02 05:54:47 AM UTC 24 |
4637218938 ps |
| T1044 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_uart_tx_rx_alt_clk_freq_low_speed.721702354 |
|
|
Sep 02 05:46:35 AM UTC 24 |
Sep 02 05:55:07 AM UTC 24 |
4614066861 ps |
| T299 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_data_integrity_escalation.1177183379 |
|
|
Sep 02 05:40:56 AM UTC 24 |
Sep 02 05:55:07 AM UTC 24 |
6147199022 ps |
| T1045 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_uart_tx_rx_idx2.1628288476 |
|
|
Sep 02 05:43:27 AM UTC 24 |
Sep 02 05:55:18 AM UTC 24 |
4085900140 ps |
| T49 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_spi_device_tpm.3917495101 |
|
|
Sep 02 05:47:20 AM UTC 24 |
Sep 02 05:55:33 AM UTC 24 |
3969158193 ps |
| T190 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_otp_ctrl_vendor_test_csr_access.2462402287 |
|
|
Sep 02 05:55:21 AM UTC 24 |
Sep 02 05:57:10 AM UTC 24 |
1777440579 ps |
| T251 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_flash_ctrl_lc_rw_en.2150973208 |
|
|
Sep 02 05:49:29 AM UTC 24 |
Sep 02 05:57:30 AM UTC 24 |
4527864174 ps |
| T40 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_gpio.2400843242 |
|
|
Sep 02 05:48:08 AM UTC 24 |
Sep 02 05:57:50 AM UTC 24 |
4183321712 ps |
| T341 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_i2c_device_tx_rx.3686986571 |
|
|
Sep 02 05:47:09 AM UTC 24 |
Sep 02 05:58:06 AM UTC 24 |
3687428264 ps |
| T223 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_spi_device_pass_through_collision.1100513889 |
|
|
Sep 02 05:48:08 AM UTC 24 |
Sep 02 05:58:07 AM UTC 24 |
4771714816 ps |
| T1046 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_lc_ctrl_otp_hw_cfg0.2610690703 |
|
|
Sep 02 05:54:32 AM UTC 24 |
Sep 02 05:59:12 AM UTC 24 |
3044823624 ps |
| T1047 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_kmac_entropy.2078108567 |
|
|
Sep 02 05:54:32 AM UTC 24 |
Sep 02 05:59:44 AM UTC 24 |
2912793834 ps |
| T1048 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_flash_ctrl_idle_low_power.2567681877 |
|
|
Sep 02 05:51:49 AM UTC 24 |
Sep 02 06:00:13 AM UTC 24 |
3457715730 ps |
| T1049 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/0.rom_e2e_self_hash.4093595019 |
|
|
Sep 02 03:34:58 AM UTC 24 |
Sep 02 06:00:40 AM UTC 24 |
26800561592 ps |
| T224 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_spi_device_pass_through.3137221940 |
|
|
Sep 02 05:47:21 AM UTC 24 |
Sep 02 06:00:49 AM UTC 24 |
7250015067 ps |
| T600 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_lc_ctrl_rand_to_scrap.248659402 |
|
|
Sep 02 05:56:19 AM UTC 24 |
Sep 02 06:00:59 AM UTC 24 |
3470470887 ps |
| T1050 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz.465779380 |
|
|
Sep 02 05:58:51 AM UTC 24 |
Sep 02 06:01:01 AM UTC 24 |
2412309201 ps |
| T350 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_flash_ctrl_ops_jitter_en.1181714790 |
|
|
Sep 02 05:49:07 AM UTC 24 |
Sep 02 06:01:17 AM UTC 24 |
4468579273 ps |
| T1051 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_lc_ctrl_volatile_raw_unlock.3889515559 |
|
|
Sep 02 05:58:27 AM UTC 24 |
Sep 02 06:01:24 AM UTC 24 |
2334629215 ps |
| T354 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_i2c_host_tx_rx_idx2.595904185 |
|
|
Sep 02 05:47:16 AM UTC 24 |
Sep 02 06:01:54 AM UTC 24 |
4667228368 ps |
| T252 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_flash_init_reduced_freq.3149426379 |
|
|
Sep 02 05:25:02 AM UTC 24 |
Sep 02 06:02:28 AM UTC 24 |
18375278885 ps |
| T359 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_flash_ctrl_ops.186629283 |
|
|
Sep 02 05:48:39 AM UTC 24 |
Sep 02 06:02:29 AM UTC 24 |
4524748808 ps |
| T1052 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_otp_ctrl_ecc_error_vendor_test.2950219793 |
|
|
Sep 02 05:56:14 AM UTC 24 |
Sep 02 06:03:01 AM UTC 24 |
3389256960 ps |
| T1053 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_i2c_host_tx_rx.3847117616 |
|
|
Sep 02 05:46:57 AM UTC 24 |
Sep 02 06:03:41 AM UTC 24 |
5425258130 ps |
| T1054 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_keymgr_key_derivation_jitter_en_reduced_freq.3651293529 |
|
|
Sep 02 05:25:16 AM UTC 24 |
Sep 02 06:04:17 AM UTC 24 |
13023065928 ps |
| T1055 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_otbn_ecdsa_op_irq_jitter_en.3616597968 |
|
|
Sep 02 04:44:14 AM UTC 24 |
Sep 02 06:04:41 AM UTC 24 |
18881483860 ps |
| T1056 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_rstmgr_sw_rst.3781738370 |
|
|
Sep 02 06:00:49 AM UTC 24 |
Sep 02 06:05:09 AM UTC 24 |
2750011208 ps |
| T1057 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_i2c_host_tx_rx_idx1.3112872275 |
|
|
Sep 02 05:46:47 AM UTC 24 |
Sep 02 06:05:19 AM UTC 24 |
5094460752 ps |
| T1058 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_otp_ctrl_lc_signals_test_unlocked0.961055218 |
|
|
Sep 02 05:54:39 AM UTC 24 |
Sep 02 06:06:21 AM UTC 24 |
4197877178 ps |
| T1059 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_otbn_ecdsa_op_irq.39679641 |
|
|
Sep 02 04:44:14 AM UTC 24 |
Sep 02 06:06:26 AM UTC 24 |
16835087880 ps |
| T1060 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_rstmgr_sw_req.522680284 |
|
|
Sep 02 06:00:20 AM UTC 24 |
Sep 02 06:09:08 AM UTC 24 |
4136057708 ps |
| T1061 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_pwrmgr_main_power_glitch_reset.1660624910 |
|
|
Sep 02 06:02:11 AM UTC 24 |
Sep 02 06:09:21 AM UTC 24 |
4425993846 ps |
| T1062 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_flash_ctrl_access_jitter_en.1460115185 |
|
|
Sep 02 05:51:48 AM UTC 24 |
Sep 02 06:09:31 AM UTC 24 |
5653099212 ps |
| T1063 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_pwrmgr_sleep_disabled.734861399 |
|
|
Sep 02 06:05:58 AM UTC 24 |
Sep 02 06:09:47 AM UTC 24 |
2749030888 ps |
| T1064 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_flash_ctrl_access.942809811 |
|
|
Sep 02 05:50:04 AM UTC 24 |
Sep 02 06:09:55 AM UTC 24 |
6208580888 ps |
| T1065 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_sleep_pwm_pulses.959780323 |
|
|
Sep 02 05:43:21 AM UTC 24 |
Sep 02 06:10:57 AM UTC 24 |
9361816772 ps |
| T1066 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_rv_timer_irq.2590614152 |
|
|
Sep 02 06:07:07 AM UTC 24 |
Sep 02 06:11:12 AM UTC 24 |
3029887808 ps |
| T1067 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_pwrmgr_full_aon_reset.3290544060 |
|
|
Sep 02 06:02:30 AM UTC 24 |
Sep 02 06:13:03 AM UTC 24 |
9066822048 ps |
| T1068 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_flash_ctrl_clock_freqs.1783660244 |
|
|
Sep 02 05:54:20 AM UTC 24 |
Sep 02 06:13:42 AM UTC 24 |
6304023169 ps |
| T1069 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_lc_walkthrough_prodend.116421852 |
|
|
Sep 02 05:58:05 AM UTC 24 |
Sep 02 06:13:48 AM UTC 24 |
7164639998 ps |
| T1070 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_pwrmgr_usb_clk_disabled_when_active.273720461 |
|
|
Sep 02 06:07:06 AM UTC 24 |
Sep 02 06:14:03 AM UTC 24 |
3734984396 ps |
| T209 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_flash_rma_unlocked.350808023 |
|
|
Sep 02 04:27:23 AM UTC 24 |
Sep 02 06:14:24 AM UTC 24 |
44398534192 ps |
| T275 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_rstmgr_cpu_info.1400406023 |
|
|
Sep 02 06:02:09 AM UTC 24 |
Sep 02 06:14:42 AM UTC 24 |
5112347368 ps |
| T1071 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_otp_ctrl_lc_signals_dev.2146710125 |
|
|
Sep 02 05:54:37 AM UTC 24 |
Sep 02 06:15:20 AM UTC 24 |
7288887180 ps |
| T243 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_keymgr_sideload_otbn.3302066503 |
|
|
Sep 02 04:58:52 AM UTC 24 |
Sep 02 06:15:42 AM UTC 24 |
14834717000 ps |
| T1072 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_lc_ctrl_transition.3671287955 |
|
|
Sep 02 05:56:13 AM UTC 24 |
Sep 02 06:15:56 AM UTC 24 |
12071168051 ps |
| T1073 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_pwrmgr_deep_sleep_por_reset.4250342387 |
|
|
Sep 02 06:03:38 AM UTC 24 |
Sep 02 06:16:51 AM UTC 24 |
8268944122 ps |
| T1074 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_pwrmgr_deep_sleep_power_glitch_reset.2176434865 |
|
|
Sep 02 06:05:17 AM UTC 24 |
Sep 02 06:17:28 AM UTC 24 |
7774146648 ps |
| T1075 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_sysrst_ctrl_inputs.2697207383 |
|
|
Sep 02 06:10:48 AM UTC 24 |
Sep 02 06:17:40 AM UTC 24 |
2876660760 ps |
| T1076 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_sysrst_ctrl_outputs.4087480763 |
|
|
Sep 02 06:10:47 AM UTC 24 |
Sep 02 06:17:44 AM UTC 24 |
3703250324 ps |
| T1077 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_pwrmgr_normal_sleep_por_reset.2656524891 |
|
|
Sep 02 06:04:17 AM UTC 24 |
Sep 02 06:17:49 AM UTC 24 |
6509034612 ps |
| T1078 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_pwrmgr_sysrst_ctrl_reset.1742779564 |
|
|
Sep 02 06:02:30 AM UTC 24 |
Sep 02 06:18:48 AM UTC 24 |
6681567756 ps |
| T1079 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_otp_ctrl_lc_signals_prod.954721214 |
|
|
Sep 02 05:54:35 AM UTC 24 |
Sep 02 06:19:02 AM UTC 24 |
8022279920 ps |
| T46 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_sysrst_ctrl_ulp_z3_wakeup.1027277642 |
|
|
Sep 02 06:10:52 AM UTC 24 |
Sep 02 06:19:11 AM UTC 24 |
5659983068 ps |
| T1080 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_otp_ctrl_lc_signals_rma.3125261515 |
|
|
Sep 02 05:55:00 AM UTC 24 |
Sep 02 06:19:51 AM UTC 24 |
8866270854 ps |
| T1081 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_aon_timer_irq.3606294115 |
|
|
Sep 02 06:11:49 AM UTC 24 |
Sep 02 06:19:55 AM UTC 24 |
4213618384 ps |
| T1082 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_uart_rand_baudrate.2266617455 |
|
|
Sep 02 05:47:21 AM UTC 24 |
Sep 02 06:20:39 AM UTC 24 |
9087512056 ps |
| T1083 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_aon_timer_sleep_wdog_sleep_pause.4059873504 |
|
|
Sep 02 06:13:33 AM UTC 24 |
Sep 02 06:21:06 AM UTC 24 |
6154058264 ps |
| T1084 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_aes_idle.4078799711 |
|
|
Sep 02 06:18:41 AM UTC 24 |
Sep 02 06:22:28 AM UTC 24 |
2327392710 ps |
| T1085 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_pwrmgr_deep_sleep_all_reset_reqs.1748323381 |
|
|
Sep 02 06:03:15 AM UTC 24 |
Sep 02 06:22:42 AM UTC 24 |
16487292450 ps |
| T1086 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_aes_enc_jitter_en.3843591691 |
|
|
Sep 02 06:18:41 AM UTC 24 |
Sep 02 06:23:31 AM UTC 24 |
2377859689 ps |
| T1087 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_aes_enc.1225972870 |
|
|
Sep 02 06:18:39 AM UTC 24 |
Sep 02 06:24:11 AM UTC 24 |
2821033940 ps |
| T1088 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_sysrst_ctrl_in_irq.4153122329 |
|
|
Sep 02 06:10:40 AM UTC 24 |
Sep 02 06:24:54 AM UTC 24 |
5013588591 ps |
| T1089 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_otbn_mem_scramble.3536460334 |
|
|
Sep 02 06:16:33 AM UTC 24 |
Sep 02 06:25:29 AM UTC 24 |
2931536000 ps |
| T264 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_alert_test.3731819790 |
|
|
Sep 02 06:19:51 AM UTC 24 |
Sep 02 06:26:11 AM UTC 24 |
2920258388 ps |
| T1090 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_adc_ctrl_sleep_debug_cable_wakeup.3106679363 |
|
|
Sep 02 06:15:01 AM UTC 24 |
Sep 02 06:26:52 AM UTC 24 |
18471485380 ps |
| T1091 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_aes_masking_off.1274617438 |
|
|
Sep 02 06:19:44 AM UTC 24 |
Sep 02 06:27:24 AM UTC 24 |
3744356357 ps |
| T1092 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_aon_timer_wdog_lc_escalate.562063841 |
|
|
Sep 02 06:14:43 AM UTC 24 |
Sep 02 06:27:26 AM UTC 24 |
5033809760 ps |
| T1093 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_pwrmgr_wdog_reset.1851460512 |
|
|
Sep 02 06:14:39 AM UTC 24 |
Sep 02 06:28:38 AM UTC 24 |
4940334686 ps |
| T246 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_lc_walkthrough_prod.171397137 |
|
|
Sep 02 04:33:34 AM UTC 24 |
Sep 02 06:30:01 AM UTC 24 |
49195882152 ps |
| T1094 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_alert_handler_escalation.3867274662 |
|
|
Sep 02 06:19:52 AM UTC 24 |
Sep 02 06:30:02 AM UTC 24 |
5626107080 ps |
| T680 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_alert_handler_lpg_sleep_mode_alerts.1175857927 |
|
|
Sep 02 06:21:17 AM UTC 24 |
Sep 02 06:30:12 AM UTC 24 |
3697674336 ps |
| T1095 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_alert_handler_entropy.878055199 |
|
|
Sep 02 06:24:07 AM UTC 24 |
Sep 02 06:30:20 AM UTC 24 |
3724369962 ps |
| T1096 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_entropy_src_kat_test.743355340 |
|
|
Sep 02 06:25:31 AM UTC 24 |
Sep 02 06:30:41 AM UTC 24 |
3354124712 ps |
| T1097 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_aes_entropy.4120416961 |
|
|
Sep 02 06:24:47 AM UTC 24 |
Sep 02 06:30:45 AM UTC 24 |
2683799788 ps |
| T1098 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_alert_handler_ping_timeout.1510290664 |
|
|
Sep 02 06:20:52 AM UTC 24 |
Sep 02 06:32:05 AM UTC 24 |
5983074094 ps |
| T1099 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/1.rom_e2e_asm_init_test_unlocked0.1376567833 |
|
|
Sep 02 05:30:08 AM UTC 24 |
Sep 02 06:32:35 AM UTC 24 |
11641548632 ps |
| T1100 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_otbn_randomness.2505024102 |
|
|
Sep 02 06:15:17 AM UTC 24 |
Sep 02 06:32:38 AM UTC 24 |
5607505528 ps |
| T1101 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_lc_walkthrough_rma.3653177036 |
|
|
Sep 02 04:35:00 AM UTC 24 |
Sep 02 06:32:42 AM UTC 24 |
45886530740 ps |
| T1102 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_aon_timer_wdog_bite_reset.3799380098 |
|
|
Sep 02 06:14:40 AM UTC 24 |
Sep 02 06:33:27 AM UTC 24 |
10764744408 ps |
| T616 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_rv_core_ibex_nmi_irq.961524412 |
|
|
Sep 02 06:18:12 AM UTC 24 |
Sep 02 06:35:09 AM UTC 24 |
4908447100 ps |
| T1103 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_lc_walkthrough_testunlocks.2286308046 |
|
|
Sep 02 05:59:49 AM UTC 24 |
Sep 02 06:35:17 AM UTC 24 |
24563015800 ps |
| T1104 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_pwrmgr_all_reset_reqs.656729138 |
|
|
Sep 02 06:02:32 AM UTC 24 |
Sep 02 06:35:18 AM UTC 24 |
10467857198 ps |
| T1105 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_csrng_kat_test.2445388724 |
|
|
Sep 02 06:30:18 AM UTC 24 |
Sep 02 06:35:52 AM UTC 24 |
3051902824 ps |
| T1106 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_hmac_enc.1161841713 |
|
|
Sep 02 06:31:34 AM UTC 24 |
Sep 02 06:36:01 AM UTC 24 |
2067041998 ps |
| T1107 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_pwrmgr_normal_sleep_all_reset_reqs.360485269 |
|
|
Sep 02 06:03:16 AM UTC 24 |
Sep 02 06:36:24 AM UTC 24 |
13850912067 ps |
| T1108 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_flash_init.1153301915 |
|
|
Sep 02 05:52:01 AM UTC 24 |
Sep 02 06:36:40 AM UTC 24 |
20057328248 ps |
| T588 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_edn_boot_mode.551567482 |
|
|
Sep 02 06:26:50 AM UTC 24 |
Sep 02 06:37:06 AM UTC 24 |
2666659936 ps |
| T1109 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_rv_core_ibex_rnd.2164595491 |
|
|
Sep 02 06:17:27 AM UTC 24 |
Sep 02 06:37:28 AM UTC 24 |
5770543640 ps |
| T1110 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_hmac_enc_jitter_en.3169897197 |
|
|
Sep 02 06:32:42 AM UTC 24 |
Sep 02 06:37:36 AM UTC 24 |
3065014897 ps |
| T339 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_rstmgr_alert_info.3544591944 |
|
|
Sep 02 06:02:16 AM UTC 24 |
Sep 02 06:37:40 AM UTC 24 |
11706495324 ps |
| T1111 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_entropy_src_ast_rng_req.2559616152 |
|
|
Sep 02 06:31:42 AM UTC 24 |
Sep 02 06:37:59 AM UTC 24 |
2642952700 ps |
| T1112 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_hmac_oneshot.3206577697 |
|
|
Sep 02 06:33:36 AM UTC 24 |
Sep 02 06:39:14 AM UTC 24 |
2713401224 ps |
| T1113 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_csrng_fuse_en_sw_app_read_test.3343526185 |
|
|
Sep 02 06:31:36 AM UTC 24 |
Sep 02 06:39:24 AM UTC 24 |
3930499224 ps |
| T1114 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_hmac_enc_idle.3120010803 |
|
|
Sep 02 06:33:36 AM UTC 24 |
Sep 02 06:39:43 AM UTC 24 |
2626571960 ps |
| T1115 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_edn_kat.512481688 |
|
|
Sep 02 06:27:28 AM UTC 24 |
Sep 02 06:39:49 AM UTC 24 |
3717959816 ps |
| T1116 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_uart_tx_rx_alt_clk_freq.2882814708 |
|
|
Sep 02 05:46:00 AM UTC 24 |
Sep 02 06:40:23 AM UTC 24 |
13882305272 ps |
| T1117 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_kmac_mode_cshake.2065502896 |
|
|
Sep 02 06:36:57 AM UTC 24 |
Sep 02 06:41:09 AM UTC 24 |
3122311264 ps |
| T1118 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_kmac_app_rom.4223438672 |
|
|
Sep 02 06:37:49 AM UTC 24 |
Sep 02 06:41:38 AM UTC 24 |
2340839704 ps |
| T1119 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_kmac_mode_kmac.772733223 |
|
|
Sep 02 06:37:13 AM UTC 24 |
Sep 02 06:41:57 AM UTC 24 |
2553298780 ps |
| T1120 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_pwrmgr_random_sleep_all_reset_reqs.3117218594 |
|
|
Sep 02 06:02:36 AM UTC 24 |
Sep 02 06:42:23 AM UTC 24 |
21558056459 ps |
| T1121 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_csrng_lc_hw_debug_en_test.2446259207 |
|
|
Sep 02 06:28:13 AM UTC 24 |
Sep 02 06:42:32 AM UTC 24 |
5771674670 ps |
| T1122 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_kmac_idle.1904122043 |
|
|
Sep 02 06:38:40 AM UTC 24 |
Sep 02 06:43:57 AM UTC 24 |
2841815080 ps |
| T1123 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_kmac_mode_kmac_jitter_en.571091148 |
|
|
Sep 02 06:37:49 AM UTC 24 |
Sep 02 06:45:10 AM UTC 24 |
3257528637 ps |
| T1124 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_sysrst_ctrl_reset.3814771527 |
|
|
Sep 02 06:10:49 AM UTC 24 |
Sep 02 06:45:38 AM UTC 24 |
22652015050 ps |
| T1125 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_edn_auto_mode.529554125 |
|
|
Sep 02 06:26:05 AM UTC 24 |
Sep 02 06:46:06 AM UTC 24 |
4815455696 ps |
| T1126 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_sensor_ctrl_status.976433763 |
|
|
Sep 02 06:41:00 AM UTC 24 |
Sep 02 06:46:12 AM UTC 24 |
2968827550 ps |
| T638 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_alert_handler_lpg_sleep_mode_pings.3983945180 |
|
|
Sep 02 06:21:43 AM UTC 24 |
Sep 02 06:46:35 AM UTC 24 |
12019952326 ps |
| T1127 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/1.rom_e2e_shutdown_output.2811229667 |
|
|
Sep 02 05:32:20 AM UTC 24 |
Sep 02 06:47:38 AM UTC 24 |
24271947549 ps |
| T1128 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_sram_ctrl_scrambled_access.1708027062 |
|
|
Sep 02 06:38:41 AM UTC 24 |
Sep 02 06:47:50 AM UTC 24 |
4189295768 ps |
| T1129 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_alert_handler_ping_ok.2667809412 |
|
|
Sep 02 06:20:52 AM UTC 24 |
Sep 02 06:48:18 AM UTC 24 |
7663951640 ps |
| T1130 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/1.rom_e2e_shutdown_exception_c.3533470028 |
|
|
Sep 02 05:31:19 AM UTC 24 |
Sep 02 06:48:51 AM UTC 24 |
13986189215 ps |
| T1131 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_sram_ctrl_scrambled_access_jitter_en.1489721332 |
|
|
Sep 02 06:38:36 AM UTC 24 |
Sep 02 06:49:21 AM UTC 24 |
4584982777 ps |
| T428 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_plic_sw_irq.4137021181 |
|
|
Sep 02 06:44:34 AM UTC 24 |
Sep 02 06:49:27 AM UTC 24 |
2212419216 ps |
| T1132 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_edn_entropy_reqs.780476719 |
|
|
Sep 02 06:31:34 AM UTC 24 |
Sep 02 06:49:33 AM UTC 24 |
5569638188 ps |
| T167 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup.499135938 |
|
|
Sep 02 06:41:47 AM UTC 24 |
Sep 02 06:49:36 AM UTC 24 |
5715682488 ps |
| T1133 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_edn_entropy_reqs_jitter.1832944333 |
|
|
Sep 02 06:31:36 AM UTC 24 |
Sep 02 06:50:54 AM UTC 24 |
6759344064 ps |
| T408 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_rom_ctrl_integrity_check.1299352887 |
|
|
Sep 02 06:38:35 AM UTC 24 |
Sep 02 06:51:09 AM UTC 24 |
9263842620 ps |
| T674 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/6.chip_sw_all_escalation_resets.1319540331 |
|
|
Sep 02 07:31:10 AM UTC 24 |
Sep 02 07:40:25 AM UTC 24 |
5572181418 ps |
| T1134 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_alert_handler_lpg_reset_toggle.4109499533 |
|
|
Sep 02 06:23:20 AM UTC 24 |
Sep 02 06:51:40 AM UTC 24 |
7218200320 ps |
| T1135 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_csrng_edn_concurrency.2469102500 |
|
|
Sep 02 04:53:17 AM UTC 24 |
Sep 02 06:51:57 AM UTC 24 |
22656080908 ps |
| T1136 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_sleep_sram_ret_contents_no_scramble.2193644947 |
|
|
Sep 02 06:40:05 AM UTC 24 |
Sep 02 06:52:34 AM UTC 24 |
6891252800 ps |
| T1137 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/1.rom_e2e_asm_init_rma.1856297705 |
|
|
Sep 02 05:31:09 AM UTC 24 |
Sep 02 06:52:39 AM UTC 24 |
14625412696 ps |
| T1138 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/1.rom_e2e_asm_init_prod_end.1031863093 |
|
|
Sep 02 05:32:17 AM UTC 24 |
Sep 02 06:52:45 AM UTC 24 |
15486505279 ps |
| T593 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq.2179848989 |
|
|
Sep 02 05:25:35 AM UTC 24 |
Sep 02 06:52:56 AM UTC 24 |
24908971112 ps |
| T187 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_plic_all_irqs_10.3306274146 |
|
|
Sep 02 06:43:12 AM UTC 24 |
Sep 02 06:53:19 AM UTC 24 |
3755861288 ps |
| T1139 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/1.rom_e2e_asm_init_prod.3501045213 |
|
|
Sep 02 05:32:26 AM UTC 24 |
Sep 02 06:53:50 AM UTC 24 |
16329784167 ps |
| T1140 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_lc_walkthrough_dev.2619479281 |
|
|
Sep 02 04:32:52 AM UTC 24 |
Sep 02 06:53:52 AM UTC 24 |
49898471059 ps |
| T1141 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_keymgr_key_derivation_jitter_en.617460719 |
|
|
Sep 02 06:36:09 AM UTC 24 |
Sep 02 06:54:09 AM UTC 24 |
6578917026 ps |
| T340 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_entropy_src_csrng.3358605251 |
|
|
Sep 02 06:31:43 AM UTC 24 |
Sep 02 06:54:26 AM UTC 24 |
6031733800 ps |
| T1142 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/1.rom_e2e_keymgr_init_rom_ext_meas.2414354007 |
|
|
Sep 02 05:32:25 AM UTC 24 |
Sep 02 06:54:38 AM UTC 24 |
14978547484 ps |
| T1143 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_clkmgr_off_otbn_trans.1988466164 |
|
|
Sep 02 06:47:11 AM UTC 24 |
Sep 02 06:54:43 AM UTC 24 |
4914749480 ps |
| T1144 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_sleep_sram_ret_contents_scramble.3961611808 |
|
|
Sep 02 06:40:31 AM UTC 24 |
Sep 02 06:55:51 AM UTC 24 |
7714624020 ps |
| T1145 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_clkmgr_jitter.3254009392 |
|
|
Sep 02 06:51:46 AM UTC 24 |
Sep 02 06:56:01 AM UTC 24 |
2522417942 ps |
| T1146 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_clkmgr_off_aes_trans.3436644634 |
|
|
Sep 02 06:46:13 AM UTC 24 |
Sep 02 06:56:15 AM UTC 24 |
4928335600 ps |
| T1147 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/1.rom_e2e_keymgr_init_rom_ext_no_meas.1579945055 |
|
|
Sep 02 05:32:03 AM UTC 24 |
Sep 02 06:56:44 AM UTC 24 |
15063091938 ps |
| T1148 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_clkmgr_off_hmac_trans.2537469958 |
|
|
Sep 02 06:46:52 AM UTC 24 |
Sep 02 06:56:57 AM UTC 24 |
4422378392 ps |
| T1149 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/1.rom_e2e_keymgr_init_rom_ext_invalid_meas.2626635600 |
|
|
Sep 02 05:32:54 AM UTC 24 |
Sep 02 06:57:16 AM UTC 24 |
15065906020 ps |
| T326 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_plic_all_irqs_20.751043096 |
|
|
Sep 02 06:43:13 AM UTC 24 |
Sep 02 06:57:23 AM UTC 24 |
5019277480 ps |
| T1150 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/1.rom_e2e_smoke.1654754704 |
|
|
Sep 02 05:31:47 AM UTC 24 |
Sep 02 06:57:36 AM UTC 24 |
14628833954 ps |
| T1151 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_clkmgr_off_kmac_trans.925788329 |
|
|
Sep 02 06:46:53 AM UTC 24 |
Sep 02 06:57:39 AM UTC 24 |
4911358808 ps |
| T1152 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/1.rom_e2e_asm_init_dev.4014112946 |
|
|
Sep 02 05:32:24 AM UTC 24 |
Sep 02 06:57:40 AM UTC 24 |
15472482627 ps |
| T1153 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_clkmgr_reset_frequency.1151917099 |
|
|
Sep 02 06:50:29 AM UTC 24 |
Sep 02 06:57:51 AM UTC 24 |
3395488374 ps |
| T1154 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0.1007018348 |
|
|
Sep 02 06:48:56 AM UTC 24 |
Sep 02 06:58:42 AM UTC 24 |
4882785998 ps |
| T1155 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_clkmgr_external_clk_src_for_lc.1067901392 |
|
|
Sep 02 06:48:24 AM UTC 24 |
Sep 02 06:58:47 AM UTC 24 |
5605695219 ps |
| T1156 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_clkmgr_jitter_frequency.3851509825 |
|
|
Sep 02 06:51:41 AM UTC 24 |
Sep 02 06:58:47 AM UTC 24 |
3380721236 ps |
| T317 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_sram_ctrl_execution_main.3204212617 |
|
|
Sep 02 06:40:04 AM UTC 24 |
Sep 02 06:59:32 AM UTC 24 |
9711120047 ps |
| T1157 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_clkmgr_external_clk_src_for_sw_fast_rma.492860530 |
|
|
Sep 02 06:50:30 AM UTC 24 |
Sep 02 06:59:40 AM UTC 24 |
3835633750 ps |
| T1158 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_tap_straps_dev.2855763066 |
|
|
Sep 02 06:56:32 AM UTC 24 |
Sep 02 06:59:51 AM UTC 24 |
2409022472 ps |
| T172 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_sensor_ctrl_alert.3108758023 |
|
|
Sep 02 06:40:32 AM UTC 24 |
Sep 02 07:00:10 AM UTC 24 |
7900590054 ps |
| T1159 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0.1301644147 |
|
|
Sep 02 06:48:28 AM UTC 24 |
Sep 02 07:00:34 AM UTC 24 |
4052944084 ps |
| T1160 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_clkmgr_external_clk_src_for_sw_fast_dev.3586309458 |
|
|
Sep 02 06:49:28 AM UTC 24 |
Sep 02 07:00:59 AM UTC 24 |
3633897300 ps |
| T1161 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_tap_straps_prod.374054660 |
|
|
Sep 02 06:57:26 AM UTC 24 |
Sep 02 07:01:12 AM UTC 24 |
2532554588 ps |
| T343 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_pwrmgr_lowpower_cancel.3013329655 |
|
|
Sep 02 06:53:56 AM UTC 24 |
Sep 02 07:01:25 AM UTC 24 |
3545012800 ps |
| T1162 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_clkmgr_external_clk_src_for_sw_slow_rma.1672765100 |
|
|
Sep 02 06:50:34 AM UTC 24 |
Sep 02 07:01:28 AM UTC 24 |
5127141744 ps |
| T1163 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_pwrmgr_sleep_wake_5_bug.2966686833 |
|
|
Sep 02 06:55:14 AM UTC 24 |
Sep 02 07:01:36 AM UTC 24 |
5373183736 ps |
| T1164 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_clkmgr_external_clk_src_for_sw_slow_dev.1100402122 |
|
|
Sep 02 06:50:32 AM UTC 24 |
Sep 02 07:01:42 AM UTC 24 |
5042918024 ps |
| T369 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up.756189165 |
|
|
Sep 02 06:55:26 AM UTC 24 |
Sep 02 07:01:45 AM UTC 24 |
5060041416 ps |
| T416 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_pwrmgr_normal_sleep_all_wake_ups.3513238585 |
|
|
Sep 02 06:53:40 AM UTC 24 |
Sep 02 07:02:00 AM UTC 24 |
6581790808 ps |
| T329 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_plic_all_irqs_0.2411050310 |
|
|
Sep 02 06:42:35 AM UTC 24 |
Sep 02 07:02:20 AM UTC 24 |
5798216122 ps |
| T1165 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_alert_handler_lpg_clkoff.3407348822 |
|
|
Sep 02 06:23:15 AM UTC 24 |
Sep 02 07:02:36 AM UTC 24 |
9388469464 ps |
| T123 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_rv_dm_ndm_reset_req.4263812314 |
|
|
Sep 02 06:55:31 AM UTC 24 |
Sep 02 07:02:57 AM UTC 24 |
4725336106 ps |
| T312 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_rv_core_ibex_icache_invalidate.2222003702 |
|
|
Sep 02 06:58:52 AM UTC 24 |
Sep 02 07:03:12 AM UTC 24 |
2360016344 ps |
| T420 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_rv_core_ibex_lockstep_glitch.1770096382 |
|
|
Sep 02 06:58:49 AM UTC 24 |
Sep 02 07:03:19 AM UTC 24 |
2961464172 ps |
| T421 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_clkmgr_jitter_reduced_freq.2209331786 |
|
|
Sep 02 06:58:54 AM UTC 24 |
Sep 02 07:03:32 AM UTC 24 |
2929966376 ps |
| T422 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_clkmgr_sleep_frequency.2978522500 |
|
|
Sep 02 06:52:18 AM UTC 24 |
Sep 02 07:03:38 AM UTC 24 |
4506365768 ps |
| T197 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_lc_ctrl_program_error.3507094668 |
|
|
Sep 02 06:53:40 AM UTC 24 |
Sep 02 07:03:45 AM UTC 24 |
5407257664 ps |
| T423 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_rv_dm_ndm_reset_req_when_cpu_halted.1539949322 |
|
|
Sep 02 06:55:31 AM UTC 24 |
Sep 02 07:04:18 AM UTC 24 |
4239950992 ps |
| T260 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_rv_core_ibex_address_translation.1440519137 |
|
|
Sep 02 06:58:40 AM UTC 24 |
Sep 02 07:04:51 AM UTC 24 |
2667933580 ps |
| T424 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_flash_ctrl_write_clear.4136283195 |
|
|
Sep 02 06:58:52 AM UTC 24 |
Sep 02 07:04:53 AM UTC 24 |
2729477636 ps |
| T425 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_aes_enc_jitter_en_reduced_freq.2244778955 |
|
|
Sep 02 07:00:42 AM UTC 24 |
Sep 02 07:05:01 AM UTC 24 |
3090064612 ps |
| T1166 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_hmac_enc_jitter_en_reduced_freq.1532093301 |
|
|
Sep 02 07:00:31 AM UTC 24 |
Sep 02 07:05:02 AM UTC 24 |
3384380330 ps |
| T1167 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_tap_straps_testunlock0.1677306055 |
|
|
Sep 02 06:56:45 AM UTC 24 |
Sep 02 07:05:12 AM UTC 24 |
5895486687 ps |
| T1168 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_edn_sw_mode.898461388 |
|
|
Sep 02 06:28:12 AM UTC 24 |
Sep 02 07:05:22 AM UTC 24 |
9187418520 ps |
| T1169 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_rv_dm_access_after_wakeup.1611444653 |
|
|
Sep 02 06:56:09 AM UTC 24 |
Sep 02 07:05:28 AM UTC 24 |
7111384328 ps |
| T1170 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_kmac_mode_kmac_jitter_en_reduced_freq.671360301 |
|
|
Sep 02 07:00:48 AM UTC 24 |
Sep 02 07:06:30 AM UTC 24 |
3533567617 ps |
| T1171 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_hmac_multistream.2057580946 |
|
|
Sep 02 06:33:35 AM UTC 24 |
Sep 02 07:06:56 AM UTC 24 |
7640926334 ps |
| T1172 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/1.rom_e2e_static_critical.769188794 |
|
|
Sep 02 05:33:18 AM UTC 24 |
Sep 02 07:07:19 AM UTC 24 |
17766522816 ps |
| T596 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_rv_dm_access_after_escalation_reset.332928012 |
|
|
Sep 02 06:56:33 AM UTC 24 |
Sep 02 07:07:32 AM UTC 24 |
5338272755 ps |
| T1173 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_flash_scrambling_smoketest.3647175879 |
|
|
Sep 02 07:04:37 AM UTC 24 |
Sep 02 07:07:57 AM UTC 24 |
3064234062 ps |
| T226 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_jtag_csr_rw.2622728130 |
|
|
Sep 02 06:52:15 AM UTC 24 |
Sep 02 07:09:21 AM UTC 24 |
10565887778 ps |
| T1174 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq.4174213048 |
|
|
Sep 02 07:01:10 AM UTC 24 |
Sep 02 07:10:04 AM UTC 24 |
4989310252 ps |
| T1175 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/2.rom_volatile_raw_unlock.1661188627 |
|
|
Sep 02 07:07:54 AM UTC 24 |
Sep 02 07:10:28 AM UTC 24 |
2375956981 ps |
| T355 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_flash_crash_alert.3223541600 |
|
|
Sep 02 06:58:55 AM UTC 24 |
Sep 02 07:10:31 AM UTC 24 |
5573171320 ps |
| T1176 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_ast_clk_outputs.2414704287 |
|
|
Sep 02 06:53:41 AM UTC 24 |
Sep 02 07:11:16 AM UTC 24 |
7729703000 ps |
| T344 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_flash_ctrl_ops_jitter_en_reduced_freq.3975142099 |
|
|
Sep 02 06:59:39 AM UTC 24 |
Sep 02 07:11:18 AM UTC 24 |
4877211381 ps |
| T1177 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_clkmgr_smoketest.1779598442 |
|
|
Sep 02 07:08:33 AM UTC 24 |
Sep 02 07:12:05 AM UTC 24 |
2736898840 ps |
| T1178 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_keymgr_sideload_kmac.3093200007 |
|
|
Sep 02 06:36:10 AM UTC 24 |
Sep 02 07:13:00 AM UTC 24 |
10166510390 ps |
| T1179 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_csrng_smoketest.1408606223 |
|
|
Sep 02 07:09:15 AM UTC 24 |
Sep 02 07:13:18 AM UTC 24 |
3037991336 ps |
| T1180 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_power_idle_load.3574828054 |
|
|
Sep 02 07:03:26 AM UTC 24 |
Sep 02 07:13:28 AM UTC 24 |
5002831824 ps |
| T1181 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_aon_timer_smoketest.586487896 |
|
|
Sep 02 07:08:43 AM UTC 24 |
Sep 02 07:13:31 AM UTC 24 |
2644614494 ps |
| T1182 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_clkmgr_off_peri.863621172 |
|
|
Sep 02 06:45:47 AM UTC 24 |
Sep 02 07:13:34 AM UTC 24 |
13416461220 ps |
| T618 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/2.rom_raw_unlock.787019930 |
|
|
Sep 02 07:09:14 AM UTC 24 |
Sep 02 07:13:40 AM UTC 24 |
5684627948 ps |
| T1183 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_sysrst_ctrl_ec_rst_l.4278043908 |
|
|
Sep 02 06:11:34 AM UTC 24 |
Sep 02 07:14:14 AM UTC 24 |
20460577270 ps |
| T1184 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_pwrmgr_b2b_sleep_reset_req.346203333 |
|
|
Sep 02 06:42:14 AM UTC 24 |
Sep 02 07:14:30 AM UTC 24 |
28277927278 ps |
| T1185 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_tap_straps_rma.2089912983 |
|
|
Sep 02 06:57:14 AM UTC 24 |
Sep 02 07:14:51 AM UTC 24 |
9332103568 ps |
| T1186 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_aes_smoketest.1629596956 |
|
|
Sep 02 07:09:16 AM UTC 24 |
Sep 02 07:15:01 AM UTC 24 |
2570655270 ps |
| T1187 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_gpio_smoketest.368589214 |
|
|
Sep 02 07:09:15 AM UTC 24 |
Sep 02 07:15:04 AM UTC 24 |
2614328092 ps |
| T1188 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_otp_ctrl_smoketest.1678356103 |
|
|
Sep 02 07:11:13 AM UTC 24 |
Sep 02 07:15:19 AM UTC 24 |
2669233552 ps |
| T242 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_keymgr_sideload_aes.24223256 |
|
|
Sep 02 06:36:40 AM UTC 24 |
Sep 02 07:15:21 AM UTC 24 |
9968788072 ps |
| T1189 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_kmac_smoketest.345606252 |
|
|
Sep 02 07:10:41 AM UTC 24 |
Sep 02 07:15:52 AM UTC 24 |
2889590276 ps |
| T1190 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/2.rom_keymgr_functest.4070944138 |
|
|
Sep 02 07:07:34 AM UTC 24 |
Sep 02 07:16:25 AM UTC 24 |
4473545658 ps |
| T1191 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_keymgr_key_derivation.1572852712 |
|
|
Sep 02 06:34:04 AM UTC 24 |
Sep 02 07:16:32 AM UTC 24 |
11621057840 ps |
| T1192 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_hmac_smoketest.1824045094 |
|
|
Sep 02 07:09:58 AM UTC 24 |
Sep 02 07:16:33 AM UTC 24 |
3746786248 ps |
| T1193 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_rv_plic_smoketest.4008025358 |
|
|
Sep 02 07:12:41 AM UTC 24 |
Sep 02 07:16:59 AM UTC 24 |
3233701704 ps |
| T227 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_jtag_mem_access.3501614718 |
|
|
Sep 02 06:52:57 AM UTC 24 |
Sep 02 07:18:05 AM UTC 24 |
13919534006 ps |
| T1194 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_rv_timer_smoketest.3747508135 |
|
|
Sep 02 07:13:38 AM UTC 24 |
Sep 02 07:18:13 AM UTC 24 |
2731491240 ps |
| T1195 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_rstmgr_smoketest.3708328525 |
|
|
Sep 02 07:14:33 AM UTC 24 |
Sep 02 07:18:40 AM UTC 24 |
3303232486 ps |
| T1196 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_flash_ctrl_access_jitter_en_reduced_freq.3759859303 |
|
|
Sep 02 06:59:36 AM UTC 24 |
Sep 02 07:19:01 AM UTC 24 |
7642082791 ps |
| T1197 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_sram_ctrl_smoketest.4199559226 |
|
|
Sep 02 07:14:52 AM UTC 24 |
Sep 02 07:19:22 AM UTC 24 |
2883439944 ps |
| T125 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_pwrmgr_random_sleep_all_wake_ups.4258932502 |
|
|
Sep 02 06:54:50 AM UTC 24 |
Sep 02 07:19:40 AM UTC 24 |
21453597762 ps |
| T1198 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_power_sleep_load.3812218711 |
|
|
Sep 02 07:07:51 AM UTC 24 |
Sep 02 07:19:52 AM UTC 24 |
9832345480 ps |
| T1199 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_entropy_src_smoketest.2009562359 |
|
|
Sep 02 07:09:16 AM UTC 24 |
Sep 02 07:20:06 AM UTC 24 |
4231542182 ps |
| T1200 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_uart_smoketest.369001572 |
|
|
Sep 02 07:15:06 AM UTC 24 |
Sep 02 07:21:22 AM UTC 24 |
3171572500 ps |
| T1201 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_pwrmgr_usbdev_smoketest.1807312059 |
|
|
Sep 02 07:12:04 AM UTC 24 |
Sep 02 07:21:48 AM UTC 24 |
5727118872 ps |
| T1202 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_pwrmgr_smoketest.405006963 |
|
|
Sep 02 07:12:03 AM UTC 24 |
Sep 02 07:22:57 AM UTC 24 |
5588102584 ps |
| T1203 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/3.chip_sw_aon_timer_sleep_wdog_sleep_pause.1459309641 |
|
|
Sep 02 07:17:31 AM UTC 24 |
Sep 02 07:24:32 AM UTC 24 |
6307460896 ps |
| T1204 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_flash_ctrl_mem_protection.309573562 |
|
|
Sep 02 07:03:22 AM UTC 24 |
Sep 02 07:24:33 AM UTC 24 |
5735085008 ps |
| T1205 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/3.chip_sw_uart_tx_rx_alt_clk_freq_low_speed.45895931 |
|
|
Sep 02 07:16:33 AM UTC 24 |
Sep 02 07:25:12 AM UTC 24 |
3873371931 ps |
| T729 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/3.chip_sw_alert_handler_lpg_sleep_mode_alerts.1075070987 |
|
|
Sep 02 07:17:36 AM UTC 24 |
Sep 02 07:25:40 AM UTC 24 |
3345052824 ps |
| T84 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/3.chip_tap_straps_rma.3493623709 |
|
|
Sep 02 07:19:09 AM UTC 24 |
Sep 02 07:25:54 AM UTC 24 |
3721365754 ps |
| T1206 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/3.chip_sw_uart_tx_rx_idx2.3510158839 |
|
|
Sep 02 07:16:29 AM UTC 24 |
Sep 02 07:26:06 AM UTC 24 |
4019394228 ps |
| T1207 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/3.chip_sw_uart_rand_baudrate.1038627927 |
|
|
Sep 02 07:16:30 AM UTC 24 |
Sep 02 07:26:21 AM UTC 24 |
3516771000 ps |
| T1208 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_keymgr_key_derivation_jitter_en_reduced_freq.3393995764 |
|
|
Sep 02 07:00:44 AM UTC 24 |
Sep 02 07:26:25 AM UTC 24 |
9479923870 ps |
| T1209 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/3.chip_sw_lc_ctrl_transition.4195194561 |
|
|
Sep 02 07:16:34 AM UTC 24 |
Sep 02 07:26:45 AM UTC 24 |
6739890451 ps |
| T85 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/3.chip_tap_straps_testunlock0.989375768 |
|
|
Sep 02 07:18:43 AM UTC 24 |
Sep 02 07:27:09 AM UTC 24 |
5331807090 ps |
| T1210 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/3.chip_sw_uart_tx_rx.2116672764 |
|
|
Sep 02 07:15:11 AM UTC 24 |
Sep 02 07:27:13 AM UTC 24 |
4981583252 ps |
| T287 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/3.chip_sw_data_integrity_escalation.3231944951 |
|
|
Sep 02 07:15:09 AM UTC 24 |
Sep 02 07:27:39 AM UTC 24 |
5043993580 ps |
| T288 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/3.chip_sw_uart_tx_rx_idx1.2782149092 |
|
|
Sep 02 07:15:26 AM UTC 24 |
Sep 02 07:27:42 AM UTC 24 |
3619058136 ps |
| T174 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/3.chip_sw_sensor_ctrl_alert.1394295428 |
|
|
Sep 02 07:17:39 AM UTC 24 |
Sep 02 07:27:50 AM UTC 24 |
6402360856 ps |
| T289 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/3.chip_sw_all_escalation_resets.725895035 |
|
|
Sep 02 07:14:55 AM UTC 24 |
Sep 02 07:27:52 AM UTC 24 |
6049692820 ps |
| T290 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_keymgr_key_derivation_prod.2036714973 |
|
|
Sep 02 06:36:03 AM UTC 24 |
Sep 02 07:29:39 AM UTC 24 |
12797457756 ps |
| T291 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/3.chip_sw_uart_tx_rx_idx3.2977879410 |
|
|
Sep 02 07:16:27 AM UTC 24 |
Sep 02 07:30:18 AM UTC 24 |
4999345064 ps |
| T292 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/4.chip_tap_straps_prod.2705524421 |
|
|
Sep 02 07:27:45 AM UTC 24 |
Sep 02 07:30:25 AM UTC 24 |
2754962062 ps |
| T293 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_pwrmgr_deep_sleep_all_wake_ups.54565316 |
|
|
Sep 02 06:54:49 AM UTC 24 |
Sep 02 07:31:26 AM UTC 24 |
22302644116 ps |
| T294 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/4.chip_sw_uart_rand_baudrate.743275868 |
|
|
Sep 02 07:23:35 AM UTC 24 |
Sep 02 07:31:39 AM UTC 24 |
3879922160 ps |
| T295 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/4.chip_sw_all_escalation_resets.1347000818 |
|
|
Sep 02 07:20:01 AM UTC 24 |
Sep 02 07:31:42 AM UTC 24 |
6388129300 ps |
| T1211 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/4.chip_sw_uart_tx_rx_idx3.554588919 |
|
|
Sep 02 07:22:26 AM UTC 24 |
Sep 02 07:32:12 AM UTC 24 |
4256169364 ps |
| T1212 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/4.chip_tap_straps_dev.2172642305 |
|
|
Sep 02 07:27:00 AM UTC 24 |
Sep 02 07:32:17 AM UTC 24 |
3523097474 ps |
| T129 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_power_virus.1923716894 |
|
|
Sep 02 07:06:49 AM UTC 24 |
Sep 02 07:32:55 AM UTC 24 |
5680794140 ps |
| T692 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/4.chip_sw_alert_handler_lpg_sleep_mode_alerts.3155910228 |
|
|
Sep 02 07:26:44 AM UTC 24 |
Sep 02 07:33:05 AM UTC 24 |
3341828328 ps |
| T1213 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_otbn_ecdsa_op_irq.3879075819 |
|
|
Sep 02 06:15:59 AM UTC 24 |
Sep 02 07:33:20 AM UTC 24 |
16793936424 ps |
| T1214 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/4.chip_sw_uart_tx_rx.487041185 |
|
|
Sep 02 07:20:42 AM UTC 24 |
Sep 02 07:33:27 AM UTC 24 |
3986659752 ps |
| T1215 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/4.chip_sw_uart_tx_rx_idx2.4156196414 |
|
|
Sep 02 07:22:00 AM UTC 24 |
Sep 02 07:34:13 AM UTC 24 |
4741636308 ps |
| T1216 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/4.chip_sw_data_integrity_escalation.3191340654 |
|
|
Sep 02 07:20:28 AM UTC 24 |
Sep 02 07:34:40 AM UTC 24 |
5600952824 ps |
| T1217 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/4.chip_sw_lc_ctrl_transition.527496432 |
|
|
Sep 02 07:25:48 AM UTC 24 |
Sep 02 07:34:47 AM UTC 24 |
6020152834 ps |