| T591 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_csrng_edn_concurrency_reduced_freq.3234070361 |
|
|
Sep 02 05:25:53 AM UTC 24 |
Sep 02 11:23:19 AM UTC 24 |
142377405051 ps |
| T94 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/0.xbar_smoke.2430021509 |
|
|
Sep 01 11:27:08 PM UTC 24 |
Sep 01 11:27:15 PM UTC 24 |
34861309 ps |
| T95 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/0.xbar_smoke_zero_delays.208038378 |
|
|
Sep 01 11:27:09 PM UTC 24 |
Sep 01 11:27:17 PM UTC 24 |
43556942 ps |
| T96 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/1.xbar_smoke_zero_delays.3883024003 |
|
|
Sep 01 11:27:22 PM UTC 24 |
Sep 01 11:27:33 PM UTC 24 |
58987139 ps |
| T99 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/0.xbar_error_random.1288460791 |
|
|
Sep 01 11:27:14 PM UTC 24 |
Sep 01 11:27:34 PM UTC 24 |
155878311 ps |
| T161 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/1.xbar_smoke.2225354246 |
|
|
Sep 01 11:27:23 PM UTC 24 |
Sep 01 11:27:34 PM UTC 24 |
198976132 ps |
| T268 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/0.xbar_stress_all_with_rand_reset.1907065869 |
|
|
Sep 01 11:27:14 PM UTC 24 |
Sep 01 11:27:36 PM UTC 24 |
26111190 ps |
| T270 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/0.xbar_random_zero_delays.1369679641 |
|
|
Sep 01 11:27:10 PM UTC 24 |
Sep 01 11:27:38 PM UTC 24 |
275809880 ps |
| T440 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/0.xbar_error_and_unmapped_addr.2035835033 |
|
|
Sep 01 11:27:14 PM UTC 24 |
Sep 01 11:27:41 PM UTC 24 |
212865944 ps |
| T269 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/1.xbar_access_same_device.1791024546 |
|
|
Sep 01 11:27:34 PM UTC 24 |
Sep 01 11:27:46 PM UTC 24 |
67922870 ps |
| T168 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/3.chip_csr_hw_reset.1735208213 |
|
|
Sep 01 11:33:16 PM UTC 24 |
Sep 01 11:38:00 PM UTC 24 |
4738019175 ps |
| T426 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/0.xbar_access_same_device.1700536629 |
|
|
Sep 01 11:27:15 PM UTC 24 |
Sep 01 11:27:52 PM UTC 24 |
757077276 ps |
| T441 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/0.xbar_random.3104248982 |
|
|
Sep 01 11:27:09 PM UTC 24 |
Sep 01 11:27:52 PM UTC 24 |
486960484 ps |
| T539 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/1.xbar_unmapped_addr.1986355962 |
|
|
Sep 01 11:27:47 PM UTC 24 |
Sep 01 11:28:01 PM UTC 24 |
60257091 ps |
| T526 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/0.xbar_same_source.4044909478 |
|
|
Sep 01 11:27:14 PM UTC 24 |
Sep 01 11:28:06 PM UTC 24 |
509812247 ps |
| T519 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/1.xbar_random_zero_delays.4259655035 |
|
|
Sep 01 11:27:29 PM UTC 24 |
Sep 01 11:28:06 PM UTC 24 |
311957537 ps |
| T523 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/0.xbar_unmapped_addr.2119267985 |
|
|
Sep 01 11:27:13 PM UTC 24 |
Sep 01 11:28:12 PM UTC 24 |
1109692228 ps |
| T443 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/1.xbar_error_and_unmapped_addr.940231672 |
|
|
Sep 01 11:27:56 PM UTC 24 |
Sep 01 11:28:15 PM UTC 24 |
248500644 ps |
| T540 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/0.xbar_smoke_slow_rsp.4032294914 |
|
|
Sep 01 11:27:07 PM UTC 24 |
Sep 01 11:28:17 PM UTC 24 |
4288944068 ps |
| T533 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/1.xbar_error_random.1227730601 |
|
|
Sep 01 11:27:50 PM UTC 24 |
Sep 01 11:28:27 PM UTC 24 |
362213519 ps |
| T524 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/1.xbar_random.2345489746 |
|
|
Sep 01 11:27:23 PM UTC 24 |
Sep 01 11:28:37 PM UTC 24 |
1956695357 ps |
| T541 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/1.xbar_smoke_slow_rsp.4262746011 |
|
|
Sep 01 11:27:24 PM UTC 24 |
Sep 01 11:28:39 PM UTC 24 |
4679978591 ps |
| T535 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/2.xbar_smoke.3931857611 |
|
|
Sep 01 11:28:34 PM UTC 24 |
Sep 01 11:28:48 PM UTC 24 |
222765516 ps |
| T542 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/2.xbar_smoke_zero_delays.2222027142 |
|
|
Sep 01 11:28:37 PM UTC 24 |
Sep 01 11:28:49 PM UTC 24 |
59424930 ps |
| T531 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/0.xbar_smoke_large_delays.3968355487 |
|
|
Sep 01 11:27:09 PM UTC 24 |
Sep 01 11:28:50 PM UTC 24 |
9174025200 ps |
| T518 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/1.xbar_same_source.3851158579 |
|
|
Sep 01 11:27:38 PM UTC 24 |
Sep 01 11:28:53 PM UTC 24 |
1792073243 ps |
| T532 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/1.xbar_smoke_large_delays.2280473348 |
|
|
Sep 01 11:27:22 PM UTC 24 |
Sep 01 11:28:55 PM UTC 24 |
8170133630 ps |
| T639 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/1.xbar_access_same_device_slow_rsp.424605833 |
|
|
Sep 01 11:27:38 PM UTC 24 |
Sep 01 11:29:20 PM UTC 24 |
5528505920 ps |
| T419 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/2.xbar_random.543582898 |
|
|
Sep 01 11:28:59 PM UTC 24 |
Sep 01 11:29:40 PM UTC 24 |
889585247 ps |
| T415 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/2.xbar_random_zero_delays.437322953 |
|
|
Sep 01 11:29:01 PM UTC 24 |
Sep 01 11:29:40 PM UTC 24 |
341888613 ps |
| T529 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/2.xbar_error_random.626280834 |
|
|
Sep 01 11:29:12 PM UTC 24 |
Sep 01 11:29:42 PM UTC 24 |
247440625 ps |
| T510 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/2.xbar_same_source.2209279550 |
|
|
Sep 01 11:29:14 PM UTC 24 |
Sep 01 11:30:04 PM UTC 24 |
1812731654 ps |
| T525 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/2.xbar_error_and_unmapped_addr.3622324376 |
|
|
Sep 01 11:29:30 PM UTC 24 |
Sep 01 11:30:11 PM UTC 24 |
276293611 ps |
| T536 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/2.xbar_unmapped_addr.4290786662 |
|
|
Sep 01 11:29:16 PM UTC 24 |
Sep 01 11:30:20 PM UTC 24 |
1168762129 ps |
| T457 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/2.xbar_smoke_slow_rsp.4216637094 |
|
|
Sep 01 11:28:50 PM UTC 24 |
Sep 01 11:30:25 PM UTC 24 |
6125995054 ps |
| T520 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/2.xbar_access_same_device.262239585 |
|
|
Sep 01 11:29:10 PM UTC 24 |
Sep 01 11:30:28 PM UTC 24 |
1332522954 ps |
| T538 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/2.xbar_random_slow_rsp.2962571884 |
|
|
Sep 01 11:29:11 PM UTC 24 |
Sep 01 11:30:38 PM UTC 24 |
3784430403 ps |
| T473 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/2.xbar_smoke_large_delays.2709264593 |
|
|
Sep 01 11:28:39 PM UTC 24 |
Sep 01 11:30:43 PM UTC 24 |
8339200576 ps |
| T537 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/3.xbar_smoke.2354467660 |
|
|
Sep 01 11:30:52 PM UTC 24 |
Sep 01 11:31:05 PM UTC 24 |
169132947 ps |
| T580 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/3.xbar_smoke_zero_delays.63697798 |
|
|
Sep 01 11:31:01 PM UTC 24 |
Sep 01 11:31:10 PM UTC 24 |
48985816 ps |
| T521 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/2.xbar_stress_all_with_rand_reset.608841935 |
|
|
Sep 01 11:30:03 PM UTC 24 |
Sep 01 11:31:11 PM UTC 24 |
129811031 ps |
| T816 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/0.xbar_access_same_device_slow_rsp.483911513 |
|
|
Sep 01 11:27:14 PM UTC 24 |
Sep 01 11:31:30 PM UTC 24 |
11892516412 ps |
| T462 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/3.xbar_random_zero_delays.1734756343 |
|
|
Sep 01 11:31:32 PM UTC 24 |
Sep 01 11:32:19 PM UTC 24 |
362325422 ps |
| T563 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/3.xbar_smoke_large_delays.2336676883 |
|
|
Sep 01 11:31:04 PM UTC 24 |
Sep 01 11:32:20 PM UTC 24 |
7817003320 ps |
| T178 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/2.chip_csr_bit_bash.293246955 |
|
|
Sep 01 11:28:14 PM UTC 24 |
Sep 01 11:32:25 PM UTC 24 |
4486960000 ps |
| T522 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/1.xbar_stress_all_with_error.3455561861 |
|
|
Sep 01 11:27:56 PM UTC 24 |
Sep 01 11:32:26 PM UTC 24 |
2974524127 ps |
| T615 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/3.xbar_smoke_slow_rsp.1173072944 |
|
|
Sep 01 11:31:12 PM UTC 24 |
Sep 01 11:32:32 PM UTC 24 |
4678005463 ps |
| T451 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/3.xbar_random.50393859 |
|
|
Sep 01 11:31:25 PM UTC 24 |
Sep 01 11:32:39 PM UTC 24 |
1562121130 ps |
| T770 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/3.xbar_access_same_device.2779453557 |
|
|
Sep 01 11:32:05 PM UTC 24 |
Sep 01 11:32:40 PM UTC 24 |
541500422 ps |
| T846 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/1.chip_prim_tl_access.233321799 |
|
|
Sep 01 11:27:21 PM UTC 24 |
Sep 01 11:32:54 PM UTC 24 |
6731250256 ps |
| T1302 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/3.xbar_unmapped_addr.3855025167 |
|
|
Sep 01 11:32:48 PM UTC 24 |
Sep 01 11:32:59 PM UTC 24 |
140487475 ps |
| T534 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/3.xbar_error_and_unmapped_addr.3366020427 |
|
|
Sep 01 11:32:50 PM UTC 24 |
Sep 01 11:33:15 PM UTC 24 |
374403663 ps |
| T1303 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/1.chip_rv_dm_lc_disabled.3973273326 |
|
|
Sep 01 11:27:20 PM UTC 24 |
Sep 01 11:33:17 PM UTC 24 |
8768612637 ps |
| T530 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/3.xbar_error_random.3273206320 |
|
|
Sep 01 11:32:49 PM UTC 24 |
Sep 01 11:33:22 PM UTC 24 |
320404908 ps |
| T173 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/1.chip_csr_hw_reset.704307260 |
|
|
Sep 01 11:27:59 PM UTC 24 |
Sep 01 11:33:22 PM UTC 24 |
4281008490 ps |
| T179 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/0.chip_csr_rw.3244388868 |
|
|
Sep 01 11:27:15 PM UTC 24 |
Sep 01 11:33:50 PM UTC 24 |
3836270724 ps |
| T527 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/1.chip_tl_errors.304631665 |
|
|
Sep 01 11:27:19 PM UTC 24 |
Sep 01 11:34:10 PM UTC 24 |
3745727364 ps |
| T528 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/3.chip_tl_errors.872933886 |
|
|
Sep 01 11:30:51 PM UTC 24 |
Sep 01 11:34:15 PM UTC 24 |
3614890000 ps |
| T169 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/2.chip_csr_hw_reset.687038870 |
|
|
Sep 01 11:30:05 PM UTC 24 |
Sep 01 11:34:23 PM UTC 24 |
5248847596 ps |
| T1304 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/4.xbar_smoke.3743830823 |
|
|
Sep 01 11:34:13 PM UTC 24 |
Sep 01 11:34:23 PM UTC 24 |
48710451 ps |
| T573 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/1.xbar_random_large_delays.2262242895 |
|
|
Sep 01 11:27:29 PM UTC 24 |
Sep 01 11:34:27 PM UTC 24 |
38964317606 ps |
| T602 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/2.xbar_stress_all_with_error.2771883105 |
|
|
Sep 01 11:30:04 PM UTC 24 |
Sep 01 11:34:27 PM UTC 24 |
2255252589 ps |
| T559 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/3.xbar_same_source.2768362860 |
|
|
Sep 01 11:32:43 PM UTC 24 |
Sep 01 11:34:34 PM UTC 24 |
2691588466 ps |
| T603 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/0.xbar_stress_all_with_error.2198385625 |
|
|
Sep 01 11:27:15 PM UTC 24 |
Sep 01 11:34:36 PM UTC 24 |
12490739115 ps |
| T1305 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/4.xbar_smoke_zero_delays.2992487579 |
|
|
Sep 01 11:34:32 PM UTC 24 |
Sep 01 11:34:42 PM UTC 24 |
42100539 ps |
| T170 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/0.chip_csr_hw_reset.2407776092 |
|
|
Sep 01 11:27:16 PM UTC 24 |
Sep 01 11:34:53 PM UTC 24 |
7503146188 ps |
| T1306 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/4.xbar_random_zero_delays.907485925 |
|
|
Sep 01 11:34:44 PM UTC 24 |
Sep 01 11:35:04 PM UTC 24 |
138205539 ps |
| T582 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/1.xbar_random_slow_rsp.46607444 |
|
|
Sep 01 11:27:34 PM UTC 24 |
Sep 01 11:35:12 PM UTC 24 |
27794891344 ps |
| T815 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/4.xbar_access_same_device.4147334374 |
|
|
Sep 01 11:34:58 PM UTC 24 |
Sep 01 11:35:21 PM UTC 24 |
356816366 ps |
| T569 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/4.xbar_random.2913248112 |
|
|
Sep 01 11:34:46 PM UTC 24 |
Sep 01 11:35:26 PM UTC 24 |
748613532 ps |
| T1307 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/4.xbar_same_source.3048935807 |
|
|
Sep 01 11:35:03 PM UTC 24 |
Sep 01 11:35:27 PM UTC 24 |
580789609 ps |
| T1308 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/4.xbar_unmapped_addr.4088207181 |
|
|
Sep 01 11:35:27 PM UTC 24 |
Sep 01 11:35:41 PM UTC 24 |
139180866 ps |
| T574 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/3.xbar_random_large_delays.3330885513 |
|
|
Sep 01 11:31:34 PM UTC 24 |
Sep 01 11:36:06 PM UTC 24 |
19671240513 ps |
| T782 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/4.xbar_smoke_slow_rsp.2644070034 |
|
|
Sep 01 11:34:40 PM UTC 24 |
Sep 01 11:36:11 PM UTC 24 |
3904288706 ps |
| T1309 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/4.xbar_error_and_unmapped_addr.648566624 |
|
|
Sep 01 11:35:36 PM UTC 24 |
Sep 01 11:36:21 PM UTC 24 |
878220922 ps |
| T1310 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/4.xbar_smoke_large_delays.839092178 |
|
|
Sep 01 11:34:38 PM UTC 24 |
Sep 01 11:36:31 PM UTC 24 |
7145168381 ps |
| T543 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/0.chip_tl_errors.247659966 |
|
|
Sep 01 11:27:08 PM UTC 24 |
Sep 01 11:36:42 PM UTC 24 |
5151634576 ps |
| T459 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/3.xbar_stress_all.3174583237 |
|
|
Sep 01 11:32:51 PM UTC 24 |
Sep 01 11:36:49 PM UTC 24 |
2180581711 ps |
| T492 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/1.xbar_stress_all.3508624056 |
|
|
Sep 01 11:27:53 PM UTC 24 |
Sep 01 11:36:57 PM UTC 24 |
10614731728 ps |
| T385 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/0.chip_csr_mem_rw_with_rand_reset.4153465303 |
|
|
Sep 01 11:27:14 PM UTC 24 |
Sep 01 11:37:07 PM UTC 24 |
6252720104 ps |
| T1311 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/5.xbar_smoke.2989024056 |
|
|
Sep 01 11:37:03 PM UTC 24 |
Sep 01 11:37:14 PM UTC 24 |
51930402 ps |
| T605 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/4.xbar_error_random.270123860 |
|
|
Sep 01 11:35:16 PM UTC 24 |
Sep 01 11:37:17 PM UTC 24 |
2523418516 ps |
| T564 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/5.xbar_smoke_zero_delays.2987212401 |
|
|
Sep 01 11:37:10 PM UTC 24 |
Sep 01 11:37:21 PM UTC 24 |
46571943 ps |
| T759 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/2.xbar_access_same_device_slow_rsp.2953790150 |
|
|
Sep 01 11:29:12 PM UTC 24 |
Sep 01 11:37:45 PM UTC 24 |
29704163180 ps |
| T750 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/3.xbar_stress_all_with_reset_error.2822786932 |
|
|
Sep 01 11:33:01 PM UTC 24 |
Sep 01 11:38:01 PM UTC 24 |
2839319212 ps |
| T1312 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/4.xbar_random_large_delays.2422088486 |
|
|
Sep 01 11:34:49 PM UTC 24 |
Sep 01 11:38:06 PM UTC 24 |
11915648993 ps |
| T829 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/4.xbar_stress_all_with_reset_error.232641822 |
|
|
Sep 01 11:35:50 PM UTC 24 |
Sep 01 11:38:10 PM UTC 24 |
210275777 ps |
| T1313 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/0.chip_prim_tl_access.600029237 |
|
|
Sep 01 11:27:10 PM UTC 24 |
Sep 01 11:38:20 PM UTC 24 |
12538865369 ps |
| T1314 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/2.chip_rv_dm_lc_disabled.4248682994 |
|
|
Sep 01 11:28:28 PM UTC 24 |
Sep 01 11:38:28 PM UTC 24 |
9181558424 ps |
| T571 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/0.xbar_stress_all_with_reset_error.3358359838 |
|
|
Sep 01 11:27:16 PM UTC 24 |
Sep 01 11:38:40 PM UTC 24 |
12239544850 ps |
| T454 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/5.xbar_random_zero_delays.423221630 |
|
|
Sep 01 11:37:36 PM UTC 24 |
Sep 01 11:38:46 PM UTC 24 |
581233027 ps |
| T395 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/2.chip_tl_errors.2143948956 |
|
|
Sep 01 11:28:27 PM UTC 24 |
Sep 01 11:38:51 PM UTC 24 |
5526766622 ps |
| T410 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/2.chip_csr_rw.2847023273 |
|
|
Sep 01 11:30:12 PM UTC 24 |
Sep 01 11:38:53 PM UTC 24 |
4289256880 ps |
| T1315 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/5.xbar_unmapped_addr.4205105145 |
|
|
Sep 01 11:38:31 PM UTC 24 |
Sep 01 11:38:55 PM UTC 24 |
308557134 ps |
| T765 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/3.xbar_stress_all_with_error.528054304 |
|
|
Sep 01 11:33:01 PM UTC 24 |
Sep 01 11:38:56 PM UTC 24 |
9259129100 ps |
| T783 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/5.xbar_smoke_large_delays.2012536212 |
|
|
Sep 01 11:37:18 PM UTC 24 |
Sep 01 11:38:58 PM UTC 24 |
6120271020 ps |
| T566 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/5.xbar_random.4260241464 |
|
|
Sep 01 11:37:28 PM UTC 24 |
Sep 01 11:39:01 PM UTC 24 |
1929226601 ps |
| T1316 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/5.xbar_smoke_slow_rsp.2799242149 |
|
|
Sep 01 11:37:27 PM UTC 24 |
Sep 01 11:39:22 PM UTC 24 |
5056400000 ps |
| T1317 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/6.xbar_smoke.3178704797 |
|
|
Sep 01 11:39:23 PM UTC 24 |
Sep 01 11:39:40 PM UTC 24 |
233095544 ps |
| T565 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/5.xbar_same_source.4120780951 |
|
|
Sep 01 11:38:22 PM UTC 24 |
Sep 01 11:39:48 PM UTC 24 |
2625253627 ps |
| T1318 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/5.xbar_error_random.236281297 |
|
|
Sep 01 11:38:26 PM UTC 24 |
Sep 01 11:39:49 PM UTC 24 |
2305385916 ps |
| T1319 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/5.xbar_error_and_unmapped_addr.680852154 |
|
|
Sep 01 11:38:43 PM UTC 24 |
Sep 01 11:39:50 PM UTC 24 |
1185337977 ps |
| T1320 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/6.xbar_smoke_zero_delays.2164777833 |
|
|
Sep 01 11:39:44 PM UTC 24 |
Sep 01 11:39:54 PM UTC 24 |
40121092 ps |
| T396 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/1.chip_csr_rw.73673160 |
|
|
Sep 01 11:28:04 PM UTC 24 |
Sep 01 11:39:55 PM UTC 24 |
5393128875 ps |
| T552 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/4.xbar_stress_all_with_error.3814503736 |
|
|
Sep 01 11:35:48 PM UTC 24 |
Sep 01 11:40:05 PM UTC 24 |
2252424281 ps |
| T1321 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/6.xbar_random_zero_delays.236591947 |
|
|
Sep 01 11:40:11 PM UTC 24 |
Sep 01 11:40:22 PM UTC 24 |
29933725 ps |
| T751 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/1.xbar_stress_all_with_reset_error.812697125 |
|
|
Sep 01 11:27:58 PM UTC 24 |
Sep 01 11:40:28 PM UTC 24 |
14850132027 ps |
| T756 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/5.xbar_access_same_device.270083037 |
|
|
Sep 01 11:38:08 PM UTC 24 |
Sep 01 11:40:29 PM UTC 24 |
2274689759 ps |
| T475 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/4.xbar_stress_all_with_rand_reset.3220359835 |
|
|
Sep 01 11:35:49 PM UTC 24 |
Sep 01 11:40:59 PM UTC 24 |
3021064693 ps |
| T621 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/2.xbar_stress_all_with_reset_error.3445399662 |
|
|
Sep 01 11:30:02 PM UTC 24 |
Sep 01 11:41:01 PM UTC 24 |
5797629220 ps |
| T460 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/6.xbar_access_same_device.2021427008 |
|
|
Sep 01 11:40:26 PM UTC 24 |
Sep 01 11:41:06 PM UTC 24 |
662212635 ps |
| T1322 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/6.xbar_same_source.3293405841 |
|
|
Sep 01 11:40:50 PM UTC 24 |
Sep 01 11:41:13 PM UTC 24 |
410848197 ps |
| T411 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/2.chip_csr_mem_rw_with_rand_reset.4010039418 |
|
|
Sep 01 11:30:27 PM UTC 24 |
Sep 01 11:41:15 PM UTC 24 |
7142774536 ps |
| T1323 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/6.xbar_unmapped_addr.2194582854 |
|
|
Sep 01 11:41:04 PM UTC 24 |
Sep 01 11:41:17 PM UTC 24 |
123258188 ps |
| T1324 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/6.xbar_smoke_large_delays.607144751 |
|
|
Sep 01 11:40:03 PM UTC 24 |
Sep 01 11:41:23 PM UTC 24 |
8038099230 ps |
| T558 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/6.xbar_random.3535248015 |
|
|
Sep 01 11:40:10 PM UTC 24 |
Sep 01 11:41:42 PM UTC 24 |
1748113860 ps |
| T1325 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/6.xbar_error_random.2456078430 |
|
|
Sep 01 11:40:52 PM UTC 24 |
Sep 01 11:41:45 PM UTC 24 |
416427292 ps |
| T1326 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/6.xbar_smoke_slow_rsp.1297326429 |
|
|
Sep 01 11:40:11 PM UTC 24 |
Sep 01 11:41:54 PM UTC 24 |
4501805408 ps |
| T448 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/1.xbar_stress_all_with_rand_reset.3417224517 |
|
|
Sep 01 11:27:55 PM UTC 24 |
Sep 01 11:42:04 PM UTC 24 |
13558393762 ps |
| T544 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/5.chip_tl_errors.1513049382 |
|
|
Sep 01 11:36:53 PM UTC 24 |
Sep 01 11:42:07 PM UTC 24 |
2909866700 ps |
| T845 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/6.xbar_stress_all_with_rand_reset.1030783109 |
|
|
Sep 01 11:41:29 PM UTC 24 |
Sep 01 11:42:12 PM UTC 24 |
72562152 ps |
| T1327 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/2.chip_prim_tl_access.487179198 |
|
|
Sep 01 11:28:27 PM UTC 24 |
Sep 01 11:42:25 PM UTC 24 |
14782275925 ps |
| T1328 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/7.xbar_smoke.3900885484 |
|
|
Sep 01 11:42:16 PM UTC 24 |
Sep 01 11:42:26 PM UTC 24 |
51926749 ps |
| T803 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/6.xbar_error_and_unmapped_addr.687301158 |
|
|
Sep 01 11:41:22 PM UTC 24 |
Sep 01 11:42:26 PM UTC 24 |
1272664275 ps |
| T560 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/7.xbar_smoke_zero_delays.1856620958 |
|
|
Sep 01 11:42:27 PM UTC 24 |
Sep 01 11:42:37 PM UTC 24 |
46963957 ps |
| T461 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/0.xbar_stress_all.2553284475 |
|
|
Sep 01 11:27:12 PM UTC 24 |
Sep 01 11:42:43 PM UTC 24 |
23059616747 ps |
| T546 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/4.chip_tl_errors.83951078 |
|
|
Sep 01 11:33:45 PM UTC 24 |
Sep 01 11:42:49 PM UTC 24 |
4957157600 ps |
| T458 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/6.xbar_random_slow_rsp.1408706094 |
|
|
Sep 01 11:40:15 PM UTC 24 |
Sep 01 11:42:58 PM UTC 24 |
7452965265 ps |
| T1329 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/7.xbar_random.577092759 |
|
|
Sep 01 11:42:46 PM UTC 24 |
Sep 01 11:43:00 PM UTC 24 |
56561205 ps |
| T818 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/6.xbar_stress_all_with_reset_error.1566797224 |
|
|
Sep 01 11:41:37 PM UTC 24 |
Sep 01 11:43:04 PM UTC 24 |
593565700 ps |
| T488 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/3.xbar_stress_all_with_rand_reset.3577915132 |
|
|
Sep 01 11:32:53 PM UTC 24 |
Sep 01 11:43:11 PM UTC 24 |
7591738600 ps |
| T572 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/7.xbar_random_zero_delays.2575257142 |
|
|
Sep 01 11:42:48 PM UTC 24 |
Sep 01 11:43:17 PM UTC 24 |
200913345 ps |
| T819 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/5.xbar_stress_all_with_reset_error.327497438 |
|
|
Sep 01 11:39:10 PM UTC 24 |
Sep 01 11:43:20 PM UTC 24 |
1596081332 ps |
| T412 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/1.chip_csr_mem_rw_with_rand_reset.3577530839 |
|
|
Sep 01 11:28:05 PM UTC 24 |
Sep 01 11:43:29 PM UTC 24 |
8600559976 ps |
| T1330 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/7.xbar_error_random.3512418567 |
|
|
Sep 01 11:43:22 PM UTC 24 |
Sep 01 11:43:32 PM UTC 24 |
45784782 ps |
| T175 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/4.chip_csr_hw_reset.469449612 |
|
|
Sep 01 11:36:02 PM UTC 24 |
Sep 01 11:43:36 PM UTC 24 |
6906192250 ps |
| T392 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/3.chip_csr_mem_rw_with_rand_reset.1281043855 |
|
|
Sep 01 11:33:28 PM UTC 24 |
Sep 01 11:43:43 PM UTC 24 |
7296195650 ps |
| T1331 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/7.xbar_error_and_unmapped_addr.1288890055 |
|
|
Sep 01 11:43:34 PM UTC 24 |
Sep 01 11:43:52 PM UTC 24 |
91895492 ps |
| T1332 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/7.xbar_unmapped_addr.1369324633 |
|
|
Sep 01 11:43:27 PM UTC 24 |
Sep 01 11:44:04 PM UTC 24 |
567932066 ps |
| T553 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/7.xbar_same_source.3946434698 |
|
|
Sep 01 11:43:20 PM UTC 24 |
Sep 01 11:44:31 PM UTC 24 |
1676750091 ps |
| T1333 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/7.xbar_smoke_slow_rsp.2980734047 |
|
|
Sep 01 11:42:35 PM UTC 24 |
Sep 01 11:44:35 PM UTC 24 |
5188598925 ps |
| T397 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/4.chip_csr_rw.3353886869 |
|
|
Sep 01 11:36:28 PM UTC 24 |
Sep 01 11:44:43 PM UTC 24 |
4841215164 ps |
| T483 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/5.xbar_stress_all.1202120409 |
|
|
Sep 01 11:38:50 PM UTC 24 |
Sep 01 11:44:58 PM UTC 24 |
8355210525 ps |
| T1334 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/8.xbar_smoke.4145238842 |
|
|
Sep 01 11:44:54 PM UTC 24 |
Sep 01 11:45:07 PM UTC 24 |
175158065 ps |
| T1335 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/8.xbar_smoke_zero_delays.3356444278 |
|
|
Sep 01 11:44:57 PM UTC 24 |
Sep 01 11:45:08 PM UTC 24 |
46113500 ps |
| T760 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/7.xbar_access_same_device.4014610832 |
|
|
Sep 01 11:43:03 PM UTC 24 |
Sep 01 11:45:08 PM UTC 24 |
1075759052 ps |
| T1336 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/7.xbar_smoke_large_delays.2926349928 |
|
|
Sep 01 11:42:30 PM UTC 24 |
Sep 01 11:45:11 PM UTC 24 |
10121222426 ps |
| T554 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/6.xbar_stress_all.2276303789 |
|
|
Sep 01 11:41:24 PM UTC 24 |
Sep 01 11:45:15 PM UTC 24 |
5639409256 ps |
| T452 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/2.xbar_stress_all.3066798326 |
|
|
Sep 01 11:29:42 PM UTC 24 |
Sep 01 11:45:19 PM UTC 24 |
19380273270 ps |
| T470 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/2.xbar_random_large_delays.2885726976 |
|
|
Sep 01 11:29:08 PM UTC 24 |
Sep 01 11:45:21 PM UTC 24 |
87750522460 ps |
| T808 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/6.xbar_stress_all_with_error.1081755166 |
|
|
Sep 01 11:41:35 PM UTC 24 |
Sep 01 11:45:27 PM UTC 24 |
2532470492 ps |
| T1337 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/5.xbar_random_large_delays.151175857 |
|
|
Sep 01 11:37:39 PM UTC 24 |
Sep 01 11:45:30 PM UTC 24 |
50539417115 ps |
| T413 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/5.chip_csr_rw.3094675135 |
|
|
Sep 01 11:39:16 PM UTC 24 |
Sep 01 11:45:31 PM UTC 24 |
4193585832 ps |
| T1338 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/4.chip_csr_bit_bash.3875774712 |
|
|
Sep 01 11:33:37 PM UTC 24 |
Sep 01 11:45:38 PM UTC 24 |
6345782520 ps |
| T493 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/8.xbar_random_zero_delays.3584928248 |
|
|
Sep 01 11:45:30 PM UTC 24 |
Sep 01 11:45:47 PM UTC 24 |
115954887 ps |
| T578 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/4.xbar_random_slow_rsp.1855164405 |
|
|
Sep 01 11:34:49 PM UTC 24 |
Sep 01 11:45:53 PM UTC 24 |
39696909010 ps |
| T1339 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/8.xbar_error_and_unmapped_addr.3210314675 |
|
|
Sep 01 11:45:55 PM UTC 24 |
Sep 01 11:46:08 PM UTC 24 |
148649028 ps |
| T1340 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/7.xbar_random_slow_rsp.2412507159 |
|
|
Sep 01 11:42:59 PM UTC 24 |
Sep 01 11:46:15 PM UTC 24 |
12978413103 ps |
| T570 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/3.xbar_random_slow_rsp.2401388823 |
|
|
Sep 01 11:31:52 PM UTC 24 |
Sep 01 11:46:18 PM UTC 24 |
62204545614 ps |
| T1341 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/8.xbar_same_source.2238335707 |
|
|
Sep 01 11:45:44 PM UTC 24 |
Sep 01 11:46:22 PM UTC 24 |
808746391 ps |
| T548 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/8.xbar_random.642679248 |
|
|
Sep 01 11:45:29 PM UTC 24 |
Sep 01 11:46:28 PM UTC 24 |
452506925 ps |
| T1342 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/8.xbar_unmapped_addr.3428092430 |
|
|
Sep 01 11:45:52 PM UTC 24 |
Sep 01 11:46:29 PM UTC 24 |
743055773 ps |
| T549 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/0.xbar_random_slow_rsp.747763065 |
|
|
Sep 01 11:27:10 PM UTC 24 |
Sep 01 11:46:46 PM UTC 24 |
68366866376 ps |
| T1343 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/8.xbar_smoke_slow_rsp.1734628393 |
|
|
Sep 01 11:45:18 PM UTC 24 |
Sep 01 11:46:48 PM UTC 24 |
4787440862 ps |
| T1344 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/5.xbar_random_slow_rsp.4038146252 |
|
|
Sep 01 11:37:43 PM UTC 24 |
Sep 01 11:46:52 PM UTC 24 |
36998036113 ps |
| T790 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/5.xbar_access_same_device_slow_rsp.252745196 |
|
|
Sep 01 11:38:21 PM UTC 24 |
Sep 01 11:46:54 PM UTC 24 |
25475084772 ps |
| T842 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/8.xbar_stress_all_with_rand_reset.2313647256 |
|
|
Sep 01 11:46:08 PM UTC 24 |
Sep 01 11:47:04 PM UTC 24 |
78681825 ps |
| T1345 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/9.xbar_smoke.854675681 |
|
|
Sep 01 11:46:52 PM UTC 24 |
Sep 01 11:47:05 PM UTC 24 |
164677629 ps |
| T496 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/7.xbar_stress_all.1801031529 |
|
|
Sep 01 11:43:40 PM UTC 24 |
Sep 01 11:47:12 PM UTC 24 |
4855067787 ps |
| T1346 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/8.xbar_error_random.699442970 |
|
|
Sep 01 11:45:50 PM UTC 24 |
Sep 01 11:47:18 PM UTC 24 |
1873862896 ps |
| T1347 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/9.xbar_smoke_zero_delays.2586314708 |
|
|
Sep 01 11:47:08 PM UTC 24 |
Sep 01 11:47:18 PM UTC 24 |
56706744 ps |
| T1348 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/8.xbar_smoke_large_delays.3885943253 |
|
|
Sep 01 11:45:05 PM UTC 24 |
Sep 01 11:47:24 PM UTC 24 |
9000247425 ps |
| T1349 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/9.xbar_random_zero_delays.3812646459 |
|
|
Sep 01 11:47:26 PM UTC 24 |
Sep 01 11:47:48 PM UTC 24 |
123477082 ps |
| T414 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/4.chip_csr_mem_rw_with_rand_reset.1277218137 |
|
|
Sep 01 11:36:33 PM UTC 24 |
Sep 01 11:47:50 PM UTC 24 |
6573563078 ps |
| T784 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/8.xbar_access_same_device.1357135464 |
|
|
Sep 01 11:45:35 PM UTC 24 |
Sep 01 11:47:55 PM UTC 24 |
2507402895 ps |
| T1350 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/0.chip_rv_dm_lc_disabled.1753478783 |
|
|
Sep 01 11:27:09 PM UTC 24 |
Sep 01 11:48:01 PM UTC 24 |
25046053848 ps |
| T1351 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/9.xbar_same_source.2669371655 |
|
|
Sep 01 11:47:46 PM UTC 24 |
Sep 01 11:48:09 PM UTC 24 |
185804789 ps |
| T444 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/3.chip_csr_rw.1377326408 |
|
|
Sep 01 11:33:21 PM UTC 24 |
Sep 01 11:48:15 PM UTC 24 |
6014398960 ps |
| T617 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/9.xbar_random.1351697110 |
|
|
Sep 01 11:47:17 PM UTC 24 |
Sep 01 11:48:25 PM UTC 24 |
1740298652 ps |
| T545 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/6.chip_tl_errors.3553875633 |
|
|
Sep 01 11:39:20 PM UTC 24 |
Sep 01 11:48:34 PM UTC 24 |
4428647652 ps |
| T1352 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/9.xbar_unmapped_addr.3679727443 |
|
|
Sep 01 11:48:12 PM UTC 24 |
Sep 01 11:48:38 PM UTC 24 |
151553029 ps |
| T1353 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/9.xbar_error_random.2781568820 |
|
|
Sep 01 11:48:09 PM UTC 24 |
Sep 01 11:48:41 PM UTC 24 |
266768150 ps |
| T752 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/7.xbar_stress_all_with_reset_error.2865346488 |
|
|
Sep 01 11:43:56 PM UTC 24 |
Sep 01 11:48:48 PM UTC 24 |
1940775761 ps |
| T1354 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/9.xbar_error_and_unmapped_addr.3026064576 |
|
|
Sep 01 11:48:17 PM UTC 24 |
Sep 01 11:48:53 PM UTC 24 |
213325673 ps |
| T489 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/0.xbar_random_large_delays.2874485358 |
|
|
Sep 01 11:27:11 PM UTC 24 |
Sep 01 11:49:01 PM UTC 24 |
98851217113 ps |
| T787 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/7.xbar_access_same_device_slow_rsp.1831350817 |
|
|
Sep 01 11:43:11 PM UTC 24 |
Sep 01 11:49:01 PM UTC 24 |
22234641690 ps |
| T1355 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/9.xbar_smoke_large_delays.4027082895 |
|
|
Sep 01 11:47:09 PM UTC 24 |
Sep 01 11:49:01 PM UTC 24 |
8643930597 ps |
| T1356 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/8.xbar_stress_all_with_error.2769872678 |
|
|
Sep 01 11:46:15 PM UTC 24 |
Sep 01 11:49:04 PM UTC 24 |
1556801599 ps |
| T1357 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/9.xbar_smoke_slow_rsp.3740705632 |
|
|
Sep 01 11:47:14 PM UTC 24 |
Sep 01 11:49:15 PM UTC 24 |
5579201825 ps |
| T551 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/8.chip_tl_errors.3545361069 |
|
|
Sep 01 11:44:27 PM UTC 24 |
Sep 01 11:49:24 PM UTC 24 |
3779000285 ps |
| T557 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/7.xbar_stress_all_with_rand_reset.675667063 |
|
|
Sep 01 11:43:43 PM UTC 24 |
Sep 01 11:49:28 PM UTC 24 |
627953175 ps |
| T1358 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/1.chip_csr_bit_bash.1014320093 |
|
|
Sep 01 11:27:13 PM UTC 24 |
Sep 01 11:49:31 PM UTC 24 |
9170284327 ps |
| T1359 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/10.xbar_smoke.3888854111 |
|
|
Sep 01 11:49:13 PM UTC 24 |
Sep 01 11:49:32 PM UTC 24 |
248414446 ps |
| T1360 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/10.xbar_smoke_zero_delays.38760643 |
|
|
Sep 01 11:49:23 PM UTC 24 |
Sep 01 11:49:33 PM UTC 24 |
36735520 ps |
| T1361 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/10.xbar_random.1729526346 |
|
|
Sep 01 11:49:25 PM UTC 24 |
Sep 01 11:49:48 PM UTC 24 |
138448202 ps |
| T1362 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/10.xbar_random_zero_delays.2694237404 |
|
|
Sep 01 11:49:34 PM UTC 24 |
Sep 01 11:49:51 PM UTC 24 |
86760895 ps |
| T501 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/8.xbar_stress_all.2594714915 |
|
|
Sep 01 11:46:00 PM UTC 24 |
Sep 01 11:50:11 PM UTC 24 |
6172066260 ps |
| T1363 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/10.xbar_same_source.2474150372 |
|
|
Sep 01 11:49:55 PM UTC 24 |
Sep 01 11:50:22 PM UTC 24 |
218981365 ps |
| T776 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/8.xbar_stress_all_with_reset_error.1120719597 |
|
|
Sep 01 11:46:31 PM UTC 24 |
Sep 01 11:50:23 PM UTC 24 |
3770641498 ps |
| T777 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/9.xbar_access_same_device.262945844 |
|
|
Sep 01 11:47:39 PM UTC 24 |
Sep 01 11:50:29 PM UTC 24 |
3066916211 ps |
| T465 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/10.xbar_access_same_device.4023776327 |
|
|
Sep 01 11:49:53 PM UTC 24 |
Sep 01 11:50:43 PM UTC 24 |
469310988 ps |
| T766 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/5.xbar_stress_all_with_error.2513102554 |
|
|
Sep 01 11:39:09 PM UTC 24 |
Sep 01 11:50:44 PM UTC 24 |
16900184239 ps |
| T469 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/10.xbar_unmapped_addr.3793776410 |
|
|
Sep 01 11:50:13 PM UTC 24 |
Sep 01 11:50:47 PM UTC 24 |
508810691 ps |
| T1364 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/10.xbar_smoke_slow_rsp.1576630757 |
|
|
Sep 01 11:49:24 PM UTC 24 |
Sep 01 11:50:47 PM UTC 24 |
3555125955 ps |
| T511 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/7.chip_csr_rw.1351650231 |
|
|
Sep 01 11:43:57 PM UTC 24 |
Sep 01 11:50:48 PM UTC 24 |
3421830088 ps |
| T550 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/7.chip_tl_errors.4004360173 |
|
|
Sep 01 11:42:08 PM UTC 24 |
Sep 01 11:51:03 PM UTC 24 |
4866812635 ps |
| T453 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/5.xbar_stress_all_with_rand_reset.329222431 |
|
|
Sep 01 11:39:02 PM UTC 24 |
Sep 01 11:51:07 PM UTC 24 |
10554381371 ps |
| T1365 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/10.xbar_error_random.836110045 |
|
|
Sep 01 11:50:09 PM UTC 24 |
Sep 01 11:51:12 PM UTC 24 |
1639175974 ps |
| T1366 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/11.xbar_smoke.3010814960 |
|
|
Sep 01 11:51:11 PM UTC 24 |
Sep 01 11:51:21 PM UTC 24 |
37692585 ps |
| T1367 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/10.xbar_smoke_large_delays.1873952183 |
|
|
Sep 01 11:49:22 PM UTC 24 |
Sep 01 11:51:29 PM UTC 24 |
7855432557 ps |
| T1368 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/11.xbar_smoke_zero_delays.1664498668 |
|
|
Sep 01 11:51:25 PM UTC 24 |
Sep 01 11:51:35 PM UTC 24 |
46469659 ps |
| T1369 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/10.xbar_error_and_unmapped_addr.3073797263 |
|
|
Sep 01 11:50:33 PM UTC 24 |
Sep 01 11:51:44 PM UTC 24 |
1260928497 ps |
| T449 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/4.xbar_stress_all.3498628309 |
|
|
Sep 01 11:35:43 PM UTC 24 |
Sep 01 11:51:45 PM UTC 24 |
20157984346 ps |
| T455 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/9.xbar_stress_all.943069827 |
|
|
Sep 01 11:48:24 PM UTC 24 |
Sep 01 11:51:56 PM UTC 24 |
5340096698 ps |
| T1370 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/10.xbar_stress_all_with_error.3768112536 |
|
|
Sep 01 11:50:45 PM UTC 24 |
Sep 01 11:52:19 PM UTC 24 |
1832931993 ps |
| T1371 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/6.chip_csr_mem_rw_with_rand_reset.2500048432 |
|
|
Sep 01 11:41:45 PM UTC 24 |
Sep 01 11:52:25 PM UTC 24 |
7391548900 ps |
| T791 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/9.xbar_stress_all_with_error.366636738 |
|
|
Sep 01 11:48:38 PM UTC 24 |
Sep 01 11:52:27 PM UTC 24 |
2157128280 ps |
| T606 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/7.xbar_stress_all_with_error.971592339 |
|
|
Sep 01 11:43:51 PM UTC 24 |
Sep 01 11:52:32 PM UTC 24 |
12569398249 ps |
| T556 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/9.chip_tl_errors.3280390750 |
|
|
Sep 01 11:46:49 PM UTC 24 |
Sep 01 11:52:36 PM UTC 24 |
3527189670 ps |
| T581 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/6.xbar_random_large_delays.1766877081 |
|
|
Sep 01 11:40:15 PM UTC 24 |
Sep 01 11:52:47 PM UTC 24 |
61928368665 ps |
| T1372 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/11.xbar_random.3460084924 |
|
|
Sep 01 11:51:44 PM UTC 24 |
Sep 01 11:52:49 PM UTC 24 |
1296510288 ps |
| T786 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/11.xbar_access_same_device.571703521 |
|
|
Sep 01 11:52:06 PM UTC 24 |
Sep 01 11:52:49 PM UTC 24 |
827827120 ps |
| T445 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/11.xbar_random_zero_delays.3694731412 |
|
|
Sep 01 11:51:51 PM UTC 24 |
Sep 01 11:53:02 PM UTC 24 |
557262090 ps |
| T1373 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/11.xbar_error_and_unmapped_addr.1189030963 |
|
|
Sep 01 11:52:55 PM UTC 24 |
Sep 01 11:53:10 PM UTC 24 |
169721620 ps |
| T1374 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/11.xbar_smoke_slow_rsp.2517512582 |
|
|
Sep 01 11:51:34 PM UTC 24 |
Sep 01 11:53:16 PM UTC 24 |
4343008825 ps |
| T1375 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/11.xbar_same_source.499410193 |
|
|
Sep 01 11:52:39 PM UTC 24 |
Sep 01 11:53:22 PM UTC 24 |
430629857 ps |
| T1376 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/11.xbar_smoke_large_delays.4145574683 |
|
|
Sep 01 11:51:29 PM UTC 24 |
Sep 01 11:53:33 PM UTC 24 |
8635349326 ps |
| T575 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/11.xbar_unmapped_addr.1983635786 |
|
|
Sep 01 11:52:49 PM UTC 24 |
Sep 01 11:53:44 PM UTC 24 |
326236978 ps |
| T1377 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/10.xbar_random_slow_rsp.1576571190 |
|
|
Sep 01 11:49:50 PM UTC 24 |
Sep 01 11:53:59 PM UTC 24 |
15234503701 ps |
| T515 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/5.chip_csr_mem_rw_with_rand_reset.2620169880 |
|
|
Sep 01 11:39:17 PM UTC 24 |
Sep 01 11:54:00 PM UTC 24 |
11173907220 ps |
| T1378 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/12.xbar_smoke.3771002433 |
|
|
Sep 01 11:53:56 PM UTC 24 |
Sep 01 11:54:07 PM UTC 24 |
171213485 ps |
| T555 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/10.chip_tl_errors.2730419746 |
|
|
Sep 01 11:49:10 PM UTC 24 |
Sep 01 11:54:15 PM UTC 24 |
3848962710 ps |
| T1379 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/12.xbar_smoke_zero_delays.1452611622 |
|
|
Sep 01 11:54:06 PM UTC 24 |
Sep 01 11:54:16 PM UTC 24 |
42662678 ps |
| T1380 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/8.xbar_random_large_delays.1189984788 |
|
|
Sep 01 11:45:31 PM UTC 24 |
Sep 01 11:54:18 PM UTC 24 |
41312130840 ps |
| T1381 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/11.xbar_error_random.384317623 |
|
|
Sep 01 11:52:48 PM UTC 24 |
Sep 01 11:54:29 PM UTC 24 |
2097896440 ps |
| T1382 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/8.xbar_random_slow_rsp.1377086451 |
|
|
Sep 01 11:45:34 PM UTC 24 |
Sep 01 11:54:39 PM UTC 24 |
30908329956 ps |
| T1383 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/9.xbar_random_slow_rsp.1493239671 |
|
|
Sep 01 11:47:35 PM UTC 24 |
Sep 01 11:54:44 PM UTC 24 |
25388623724 ps |
| T1384 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/12.xbar_random_zero_delays.871668723 |
|
|
Sep 01 11:54:35 PM UTC 24 |
Sep 01 11:55:03 PM UTC 24 |
176169820 ps |
| T517 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/8.chip_csr_mem_rw_with_rand_reset.641631864 |
|
|
Sep 01 11:46:39 PM UTC 24 |
Sep 01 11:55:31 PM UTC 24 |
7054135127 ps |
| T1385 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/12.xbar_random.632867787 |
|
|
Sep 01 11:54:27 PM UTC 24 |
Sep 01 11:55:32 PM UTC 24 |
1527348454 ps |
| T512 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/6.chip_csr_rw.3770359170 |
|
|
Sep 01 11:41:39 PM UTC 24 |
Sep 01 11:55:39 PM UTC 24 |
5318615270 ps |
| T579 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/12.xbar_same_source.1021296761 |
|
|
Sep 01 11:55:07 PM UTC 24 |
Sep 01 11:55:43 PM UTC 24 |
759941532 ps |
| T773 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/4.xbar_access_same_device_slow_rsp.2931115548 |
|
|
Sep 01 11:34:58 PM UTC 24 |
Sep 01 11:55:54 PM UTC 24 |
62469450138 ps |
| T1386 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/12.xbar_smoke_slow_rsp.1586058205 |
|
|
Sep 01 11:54:23 PM UTC 24 |
Sep 01 11:56:01 PM UTC 24 |
5020613676 ps |
| T1387 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/7.xbar_random_large_delays.3840127651 |
|
|
Sep 01 11:42:48 PM UTC 24 |
Sep 01 11:56:01 PM UTC 24 |
78497944092 ps |
| T1388 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/12.xbar_smoke_large_delays.62813285 |
|
|
Sep 01 11:54:19 PM UTC 24 |
Sep 01 11:56:01 PM UTC 24 |
6502881357 ps |
| T794 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/12.xbar_access_same_device.3427536445 |
|
|
Sep 01 11:54:51 PM UTC 24 |
Sep 01 11:56:03 PM UTC 24 |
826235158 ps |
| T466 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/11.xbar_stress_all.801150330 |
|
|
Sep 01 11:52:59 PM UTC 24 |
Sep 01 11:56:05 PM UTC 24 |
1489320119 ps |
| T1389 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/12.xbar_unmapped_addr.1389007816 |
|
|
Sep 01 11:55:26 PM UTC 24 |
Sep 01 11:56:08 PM UTC 24 |
609825005 ps |
| T1390 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/11.xbar_random_large_delays.4282727591 |
|
|
Sep 01 11:51:58 PM UTC 24 |
Sep 01 11:56:15 PM UTC 24 |
22760137822 ps |