| T508 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/24.xbar_access_same_device.1000079823 |
|
|
Sep 02 12:23:03 AM UTC 24 |
Sep 02 12:25:05 AM UTC 24 |
1790242896 ps |
| T1566 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/23.xbar_stress_all.2755205898 |
|
|
Sep 02 12:21:59 AM UTC 24 |
Sep 02 12:25:07 AM UTC 24 |
4044032473 ps |
| T1567 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/25.xbar_random_zero_delays.2528055002 |
|
|
Sep 02 12:24:39 AM UTC 24 |
Sep 02 12:25:19 AM UTC 24 |
385033823 ps |
| T1568 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/20.xbar_stress_all_with_error.171134510 |
|
|
Sep 02 12:17:22 AM UTC 24 |
Sep 02 12:25:27 AM UTC 24 |
11814610420 ps |
| T394 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/11.chip_same_csr_outstanding.1475192013 |
|
|
Sep 01 11:51:09 PM UTC 24 |
Sep 02 12:25:35 AM UTC 24 |
16717302250 ps |
| T1569 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/25.xbar_random.1472403699 |
|
|
Sep 02 12:24:38 AM UTC 24 |
Sep 02 12:25:38 AM UTC 24 |
1376940716 ps |
| T1570 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/23.xbar_stress_all_with_reset_error.2523371757 |
|
|
Sep 02 12:22:16 AM UTC 24 |
Sep 02 12:25:40 AM UTC 24 |
804596555 ps |
| T1571 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/25.xbar_unmapped_addr.2511412511 |
|
|
Sep 02 12:25:30 AM UTC 24 |
Sep 02 12:25:42 AM UTC 24 |
40872029 ps |
| T1572 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/25.xbar_error_random.1639213933 |
|
|
Sep 02 12:25:28 AM UTC 24 |
Sep 02 12:25:50 AM UTC 24 |
148341460 ps |
| T1573 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/15.xbar_random_large_delays.2971186338 |
|
|
Sep 02 12:03:05 AM UTC 24 |
Sep 02 12:25:53 AM UTC 24 |
104446419481 ps |
| T481 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/21.xbar_stress_all_with_rand_reset.2234445536 |
|
|
Sep 02 12:18:49 AM UTC 24 |
Sep 02 12:25:56 AM UTC 24 |
6145707122 ps |
| T1574 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/16.xbar_random_large_delays.3641973782 |
|
|
Sep 02 12:06:01 AM UTC 24 |
Sep 02 12:25:57 AM UTC 24 |
109038872541 ps |
| T802 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/25.xbar_access_same_device.3597201247 |
|
|
Sep 02 12:24:56 AM UTC 24 |
Sep 02 12:26:03 AM UTC 24 |
668788790 ps |
| T1575 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/25.xbar_smoke_large_delays.2094400914 |
|
|
Sep 02 12:24:30 AM UTC 24 |
Sep 02 12:26:05 AM UTC 24 |
7634584990 ps |
| T1576 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/25.xbar_smoke_slow_rsp.3457030008 |
|
|
Sep 02 12:24:35 AM UTC 24 |
Sep 02 12:26:21 AM UTC 24 |
4759132555 ps |
| T509 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/18.xbar_random_slow_rsp.2205917189 |
|
|
Sep 02 12:11:29 AM UTC 24 |
Sep 02 12:26:22 AM UTC 24 |
51273260594 ps |
| T1577 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/26.xbar_smoke.47200125 |
|
|
Sep 02 12:26:12 AM UTC 24 |
Sep 02 12:26:24 AM UTC 24 |
158106050 ps |
| T1578 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/26.xbar_smoke_zero_delays.328220605 |
|
|
Sep 02 12:26:17 AM UTC 24 |
Sep 02 12:26:28 AM UTC 24 |
51386692 ps |
| T1579 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/25.xbar_error_and_unmapped_addr.2617721434 |
|
|
Sep 02 12:25:40 AM UTC 24 |
Sep 02 12:26:28 AM UTC 24 |
918114951 ps |
| T495 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/25.xbar_same_source.126691931 |
|
|
Sep 02 12:25:19 AM UTC 24 |
Sep 02 12:26:30 AM UTC 24 |
2074205360 ps |
| T1580 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/18.chip_csr_rw.1315788809 |
|
|
Sep 02 12:13:09 AM UTC 24 |
Sep 02 12:26:34 AM UTC 24 |
5086283200 ps |
| T1581 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/25.xbar_stress_all.3171233823 |
|
|
Sep 02 12:25:49 AM UTC 24 |
Sep 02 12:27:17 AM UTC 24 |
678671621 ps |
| T609 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/23.chip_tl_errors.1745289957 |
|
|
Sep 02 12:20:53 AM UTC 24 |
Sep 02 12:27:21 AM UTC 24 |
3466551675 ps |
| T1582 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/26.xbar_random_zero_delays.2494228809 |
|
|
Sep 02 12:26:27 AM UTC 24 |
Sep 02 12:27:24 AM UTC 24 |
545532672 ps |
| T823 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/20.xbar_stress_all_with_reset_error.2431658366 |
|
|
Sep 02 12:17:26 AM UTC 24 |
Sep 02 12:27:27 AM UTC 24 |
11651693131 ps |
| T767 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/9.xbar_access_same_device_slow_rsp.892323880 |
|
|
Sep 01 11:47:41 PM UTC 24 |
Sep 02 12:27:27 AM UTC 24 |
139864290268 ps |
| T1583 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/26.xbar_smoke_large_delays.2884270342 |
|
|
Sep 02 12:26:19 AM UTC 24 |
Sep 02 12:27:33 AM UTC 24 |
7150378669 ps |
| T1584 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/26.xbar_unmapped_addr.2250248999 |
|
|
Sep 02 12:26:56 AM UTC 24 |
Sep 02 12:27:35 AM UTC 24 |
215737714 ps |
| T1585 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/26.xbar_same_source.2311690584 |
|
|
Sep 02 12:26:50 AM UTC 24 |
Sep 02 12:27:49 AM UTC 24 |
507377067 ps |
| T775 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/26.xbar_access_same_device.3847766078 |
|
|
Sep 02 12:26:45 AM UTC 24 |
Sep 02 12:27:50 AM UTC 24 |
1421630397 ps |
| T1586 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/26.xbar_error_random.1969427554 |
|
|
Sep 02 12:26:52 AM UTC 24 |
Sep 02 12:27:51 AM UTC 24 |
1246937690 ps |
| T1587 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/26.xbar_random.1439994972 |
|
|
Sep 02 12:26:26 AM UTC 24 |
Sep 02 12:27:54 AM UTC 24 |
1749161756 ps |
| T1588 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/27.xbar_smoke.786988380 |
|
|
Sep 02 12:27:57 AM UTC 24 |
Sep 02 12:28:10 AM UTC 24 |
184891836 ps |
| T1589 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/27.xbar_smoke_zero_delays.289340810 |
|
|
Sep 02 12:28:12 AM UTC 24 |
Sep 02 12:28:21 AM UTC 24 |
39820107 ps |
| T1590 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/26.xbar_error_and_unmapped_addr.4277388744 |
|
|
Sep 02 12:27:39 AM UTC 24 |
Sep 02 12:28:24 AM UTC 24 |
845124853 ps |
| T1591 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/24.chip_tl_errors.176416731 |
|
|
Sep 02 12:22:20 AM UTC 24 |
Sep 02 12:28:30 AM UTC 24 |
3678411090 ps |
| T838 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/25.xbar_stress_all_with_reset_error.1500654530 |
|
|
Sep 02 12:26:03 AM UTC 24 |
Sep 02 12:28:32 AM UTC 24 |
495222312 ps |
| T1592 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/26.xbar_smoke_slow_rsp.1993674303 |
|
|
Sep 02 12:26:20 AM UTC 24 |
Sep 02 12:28:42 AM UTC 24 |
7380991723 ps |
| T1593 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/19.chip_csr_rw.97952297 |
|
|
Sep 02 12:15:35 AM UTC 24 |
Sep 02 12:28:53 AM UTC 24 |
6058185784 ps |
| T1594 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/27.xbar_random_zero_delays.64225190 |
|
|
Sep 02 12:28:32 AM UTC 24 |
Sep 02 12:28:56 AM UTC 24 |
170873587 ps |
| T1595 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/21.xbar_random_slow_rsp.2194207553 |
|
|
Sep 02 12:18:10 AM UTC 24 |
Sep 02 12:29:13 AM UTC 24 |
41167441811 ps |
| T1596 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/17.chip_csr_mem_rw_with_rand_reset.3664129855 |
|
|
Sep 02 12:10:27 AM UTC 24 |
Sep 02 12:29:17 AM UTC 24 |
12245023908 ps |
| T814 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/21.xbar_stress_all_with_error.2200997851 |
|
|
Sep 02 12:19:01 AM UTC 24 |
Sep 02 12:29:24 AM UTC 24 |
12068727586 ps |
| T1597 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/27.xbar_smoke_large_delays.1740342175 |
|
|
Sep 02 12:28:13 AM UTC 24 |
Sep 02 12:29:26 AM UTC 24 |
6393202471 ps |
| T1598 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/27.xbar_same_source.3613418043 |
|
|
Sep 02 12:29:06 AM UTC 24 |
Sep 02 12:29:29 AM UTC 24 |
456273037 ps |
| T482 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/27.xbar_random.3608330347 |
|
|
Sep 02 12:28:17 AM UTC 24 |
Sep 02 12:29:32 AM UTC 24 |
1442073677 ps |
| T1599 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/21.xbar_access_same_device_slow_rsp.1021844473 |
|
|
Sep 02 12:18:14 AM UTC 24 |
Sep 02 12:29:38 AM UTC 24 |
40769315665 ps |
| T1600 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/27.xbar_smoke_slow_rsp.1291441048 |
|
|
Sep 02 12:28:15 AM UTC 24 |
Sep 02 12:29:38 AM UTC 24 |
5192511693 ps |
| T1601 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/27.chip_tl_errors.464209055 |
|
|
Sep 02 12:27:54 AM UTC 24 |
Sep 02 12:29:39 AM UTC 24 |
2389270451 ps |
| T832 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/21.xbar_stress_all_with_reset_error.1337733518 |
|
|
Sep 02 12:19:01 AM UTC 24 |
Sep 02 12:29:44 AM UTC 24 |
3508223145 ps |
| T1602 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/23.xbar_stress_all_with_rand_reset.4176485635 |
|
|
Sep 02 12:22:00 AM UTC 24 |
Sep 02 12:29:52 AM UTC 24 |
8848340387 ps |
| T1603 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/27.xbar_unmapped_addr.3867977714 |
|
|
Sep 02 12:29:18 AM UTC 24 |
Sep 02 12:29:57 AM UTC 24 |
562661988 ps |
| T1604 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/28.xbar_smoke_zero_delays.999327050 |
|
|
Sep 02 12:30:01 AM UTC 24 |
Sep 02 12:30:09 AM UTC 24 |
32547777 ps |
| T1605 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/28.xbar_smoke.2616217040 |
|
|
Sep 02 12:30:01 AM UTC 24 |
Sep 02 12:30:14 AM UTC 24 |
174389725 ps |
| T1606 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/27.xbar_access_same_device.2645720841 |
|
|
Sep 02 12:28:54 AM UTC 24 |
Sep 02 12:30:23 AM UTC 24 |
1019442687 ps |
| T1607 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/27.xbar_error_random.703399171 |
|
|
Sep 02 12:29:16 AM UTC 24 |
Sep 02 12:30:29 AM UTC 24 |
2284976680 ps |
| T1608 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/28.xbar_random_zero_delays.1673846001 |
|
|
Sep 02 12:30:19 AM UTC 24 |
Sep 02 12:30:31 AM UTC 24 |
75830663 ps |
| T1609 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/27.xbar_error_and_unmapped_addr.271762694 |
|
|
Sep 02 12:29:36 AM UTC 24 |
Sep 02 12:30:52 AM UTC 24 |
1322463443 ps |
| T780 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/23.xbar_stress_all_with_error.322879124 |
|
|
Sep 02 12:21:59 AM UTC 24 |
Sep 02 12:31:09 AM UTC 24 |
11553166351 ps |
| T795 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/26.xbar_stress_all_with_error.868546492 |
|
|
Sep 02 12:27:47 AM UTC 24 |
Sep 02 12:31:10 AM UTC 24 |
4465981627 ps |
| T479 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/28.xbar_random.589830474 |
|
|
Sep 02 12:30:15 AM UTC 24 |
Sep 02 12:31:11 AM UTC 24 |
445021503 ps |
| T1610 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/24.xbar_stress_all_with_reset_error.1855162533 |
|
|
Sep 02 12:24:11 AM UTC 24 |
Sep 02 12:31:21 AM UTC 24 |
3619813449 ps |
| T1611 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/28.xbar_smoke_slow_rsp.572793205 |
|
|
Sep 02 12:30:08 AM UTC 24 |
Sep 02 12:31:30 AM UTC 24 |
4800549257 ps |
| T1612 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/27.xbar_stress_all.781909235 |
|
|
Sep 02 12:29:39 AM UTC 24 |
Sep 02 12:31:30 AM UTC 24 |
2245233058 ps |
| T1613 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/28.xbar_same_source.1460211120 |
|
|
Sep 02 12:30:55 AM UTC 24 |
Sep 02 12:31:40 AM UTC 24 |
1002032732 ps |
| T1614 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/28.xbar_smoke_large_delays.3979915707 |
|
|
Sep 02 12:30:02 AM UTC 24 |
Sep 02 12:32:00 AM UTC 24 |
7565639319 ps |
| T1615 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/28.xbar_error_random.2339235061 |
|
|
Sep 02 12:31:14 AM UTC 24 |
Sep 02 12:32:00 AM UTC 24 |
395383374 ps |
| T1616 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/28.xbar_error_and_unmapped_addr.208210289 |
|
|
Sep 02 12:31:33 AM UTC 24 |
Sep 02 12:32:06 AM UTC 24 |
197623786 ps |
| T1617 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/19.chip_csr_mem_rw_with_rand_reset.1379774151 |
|
|
Sep 02 12:15:32 AM UTC 24 |
Sep 02 12:32:08 AM UTC 24 |
10743621120 ps |
| T1618 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/26.xbar_random_large_delays.2680262841 |
|
|
Sep 02 12:26:44 AM UTC 24 |
Sep 02 12:32:14 AM UTC 24 |
26482753269 ps |
| T1619 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/28.xbar_unmapped_addr.3616866543 |
|
|
Sep 02 12:31:32 AM UTC 24 |
Sep 02 12:32:22 AM UTC 24 |
322206611 ps |
| T1620 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/29.xbar_smoke_zero_delays.1261234289 |
|
|
Sep 02 12:32:22 AM UTC 24 |
Sep 02 12:32:32 AM UTC 24 |
49790863 ps |
| T1621 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/29.xbar_smoke.75868196 |
|
|
Sep 02 12:32:23 AM UTC 24 |
Sep 02 12:32:33 AM UTC 24 |
48501975 ps |
| T1622 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/18.chip_csr_mem_rw_with_rand_reset.1417264883 |
|
|
Sep 02 12:13:12 AM UTC 24 |
Sep 02 12:32:49 AM UTC 24 |
12413850920 ps |
| T1623 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/25.chip_tl_errors.1588634662 |
|
|
Sep 02 12:24:15 AM UTC 24 |
Sep 02 12:32:49 AM UTC 24 |
5014081880 ps |
| T1624 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/29.xbar_random_zero_delays.2230074984 |
|
|
Sep 02 12:32:43 AM UTC 24 |
Sep 02 12:32:57 AM UTC 24 |
119465943 ps |
| T1625 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/25.xbar_stress_all_with_error.4044605588 |
|
|
Sep 02 12:26:01 AM UTC 24 |
Sep 02 12:32:57 AM UTC 24 |
4783601311 ps |
| T1626 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/29.xbar_random.1854112560 |
|
|
Sep 02 12:32:35 AM UTC 24 |
Sep 02 12:33:04 AM UTC 24 |
445346908 ps |
| T1627 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/24.xbar_random_slow_rsp.2110425321 |
|
|
Sep 02 12:23:01 AM UTC 24 |
Sep 02 12:33:06 AM UTC 24 |
30814765889 ps |
| T1628 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/19.xbar_random_large_delays.664197089 |
|
|
Sep 02 12:14:25 AM UTC 24 |
Sep 02 12:33:08 AM UTC 24 |
88302908515 ps |
| T1629 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/27.xbar_stress_all_with_reset_error.1119645234 |
|
|
Sep 02 12:29:52 AM UTC 24 |
Sep 02 12:33:11 AM UTC 24 |
574264044 ps |
| T1630 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/25.xbar_stress_all_with_rand_reset.799616024 |
|
|
Sep 02 12:25:58 AM UTC 24 |
Sep 02 12:33:25 AM UTC 24 |
3315006379 ps |
| T1631 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/27.xbar_stress_all_with_error.294000876 |
|
|
Sep 02 12:29:47 AM UTC 24 |
Sep 02 12:33:31 AM UTC 24 |
2711632315 ps |
| T1632 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/29.xbar_error_and_unmapped_addr.2900268072 |
|
|
Sep 02 12:33:29 AM UTC 24 |
Sep 02 12:33:40 AM UTC 24 |
83346566 ps |
| T497 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/28.xbar_access_same_device.2756282817 |
|
|
Sep 02 12:30:45 AM UTC 24 |
Sep 02 12:33:44 AM UTC 24 |
3000509379 ps |
| T472 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/26.xbar_stress_all.1352441648 |
|
|
Sep 02 12:27:43 AM UTC 24 |
Sep 02 12:33:45 AM UTC 24 |
3337029588 ps |
| T1633 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/29.xbar_error_random.852021824 |
|
|
Sep 02 12:33:18 AM UTC 24 |
Sep 02 12:33:46 AM UTC 24 |
222091646 ps |
| T1634 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/29.xbar_smoke_slow_rsp.1937101395 |
|
|
Sep 02 12:32:31 AM UTC 24 |
Sep 02 12:33:46 AM UTC 24 |
3908519799 ps |
| T1635 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/29.xbar_smoke_large_delays.3462842183 |
|
|
Sep 02 12:32:29 AM UTC 24 |
Sep 02 12:33:53 AM UTC 24 |
8193323480 ps |
| T1636 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/29.xbar_unmapped_addr.246926109 |
|
|
Sep 02 12:33:27 AM UTC 24 |
Sep 02 12:33:54 AM UTC 24 |
397237395 ps |
| T755 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/20.xbar_access_same_device_slow_rsp.2047827218 |
|
|
Sep 02 12:16:38 AM UTC 24 |
Sep 02 12:33:59 AM UTC 24 |
69959191615 ps |
| T1637 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/29.xbar_same_source.1392708373 |
|
|
Sep 02 12:33:19 AM UTC 24 |
Sep 02 12:34:01 AM UTC 24 |
352541382 ps |
| T1638 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/30.xbar_smoke.3868576556 |
|
|
Sep 02 12:34:03 AM UTC 24 |
Sep 02 12:34:13 AM UTC 24 |
56630531 ps |
| T1639 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/30.xbar_smoke_zero_delays.2203498769 |
|
|
Sep 02 12:34:06 AM UTC 24 |
Sep 02 12:34:16 AM UTC 24 |
47665918 ps |
| T499 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/26.xbar_stress_all_with_rand_reset.408276016 |
|
|
Sep 02 12:27:45 AM UTC 24 |
Sep 02 12:34:18 AM UTC 24 |
2158924051 ps |
| T1640 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/28.xbar_random_slow_rsp.3038695783 |
|
|
Sep 02 12:30:34 AM UTC 24 |
Sep 02 12:34:31 AM UTC 24 |
15309652884 ps |
| T1641 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/28.xbar_stress_all_with_rand_reset.3505088942 |
|
|
Sep 02 12:31:43 AM UTC 24 |
Sep 02 12:34:33 AM UTC 24 |
1485916411 ps |
| T781 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/24.xbar_access_same_device_slow_rsp.1717225655 |
|
|
Sep 02 12:23:03 AM UTC 24 |
Sep 02 12:34:39 AM UTC 24 |
34658636661 ps |
| T1642 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/28.xbar_stress_all.1938443115 |
|
|
Sep 02 12:31:32 AM UTC 24 |
Sep 02 12:34:43 AM UTC 24 |
1419379587 ps |
| T1643 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/28.chip_tl_errors.1245506745 |
|
|
Sep 02 12:29:55 AM UTC 24 |
Sep 02 12:35:01 AM UTC 24 |
3824657047 ps |
| T1644 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/28.xbar_random_large_delays.2667780273 |
|
|
Sep 02 12:30:30 AM UTC 24 |
Sep 02 12:35:03 AM UTC 24 |
21958572257 ps |
| T1645 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/30.xbar_unmapped_addr.608954699 |
|
|
Sep 02 12:34:54 AM UTC 24 |
Sep 02 12:35:03 AM UTC 24 |
22939322 ps |
| T1646 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/30.xbar_random_zero_delays.4245018970 |
|
|
Sep 02 12:34:16 AM UTC 24 |
Sep 02 12:35:05 AM UTC 24 |
368342222 ps |
| T1647 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/26.chip_tl_errors.23813629 |
|
|
Sep 02 12:26:04 AM UTC 24 |
Sep 02 12:35:07 AM UTC 24 |
4694122905 ps |
| T1648 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/30.xbar_random.3998153246 |
|
|
Sep 02 12:34:07 AM UTC 24 |
Sep 02 12:35:12 AM UTC 24 |
1231894111 ps |
| T1649 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/30.xbar_access_same_device.2036796318 |
|
|
Sep 02 12:34:24 AM UTC 24 |
Sep 02 12:35:14 AM UTC 24 |
1224517300 ps |
| T1650 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/29.xbar_stress_all_with_error.2113648313 |
|
|
Sep 02 12:33:49 AM UTC 24 |
Sep 02 12:35:24 AM UTC 24 |
2211165175 ps |
| T1651 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/29.xbar_access_same_device.3713952179 |
|
|
Sep 02 12:33:12 AM UTC 24 |
Sep 02 12:35:26 AM UTC 24 |
3308067089 ps |
| T1652 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/30.xbar_same_source.1676876463 |
|
|
Sep 02 12:34:38 AM UTC 24 |
Sep 02 12:35:36 AM UTC 24 |
1224877931 ps |
| T1653 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/31.xbar_smoke_zero_delays.4089060917 |
|
|
Sep 02 12:35:28 AM UTC 24 |
Sep 02 12:35:37 AM UTC 24 |
41961389 ps |
| T1654 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/31.xbar_smoke.1757911746 |
|
|
Sep 02 12:35:27 AM UTC 24 |
Sep 02 12:35:38 AM UTC 24 |
125585449 ps |
| T772 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/11.xbar_access_same_device_slow_rsp.1915761510 |
|
|
Sep 01 11:52:19 PM UTC 24 |
Sep 02 12:35:43 AM UTC 24 |
142720114895 ps |
| T1655 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/30.xbar_error_random.906270350 |
|
|
Sep 02 12:34:42 AM UTC 24 |
Sep 02 12:35:57 AM UTC 24 |
1378249302 ps |
| T1656 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/30.xbar_smoke_large_delays.2228834353 |
|
|
Sep 02 12:34:04 AM UTC 24 |
Sep 02 12:36:02 AM UTC 24 |
7701338283 ps |
| T1657 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/30.xbar_smoke_slow_rsp.2235708193 |
|
|
Sep 02 12:34:04 AM UTC 24 |
Sep 02 12:36:04 AM UTC 24 |
5203662714 ps |
| T393 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/16.chip_same_csr_outstanding.1775067817 |
|
|
Sep 02 12:04:40 AM UTC 24 |
Sep 02 12:36:04 AM UTC 24 |
15618625463 ps |
| T1658 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/30.xbar_error_and_unmapped_addr.2985675866 |
|
|
Sep 02 12:34:56 AM UTC 24 |
Sep 02 12:36:05 AM UTC 24 |
1326254527 ps |
| T1659 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/23.xbar_random_large_delays.3524472697 |
|
|
Sep 02 12:21:24 AM UTC 24 |
Sep 02 12:36:05 AM UTC 24 |
84486071011 ps |
| T1660 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/26.xbar_random_slow_rsp.671802417 |
|
|
Sep 02 12:26:42 AM UTC 24 |
Sep 02 12:36:05 AM UTC 24 |
30056202687 ps |
| T485 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/22.xbar_random_large_delays.566386374 |
|
|
Sep 02 12:19:49 AM UTC 24 |
Sep 02 12:36:12 AM UTC 24 |
99734653206 ps |
| T1661 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/24.xbar_random_large_delays.3236448268 |
|
|
Sep 02 12:23:01 AM UTC 24 |
Sep 02 12:36:16 AM UTC 24 |
67448256950 ps |
| T490 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/30.xbar_stress_all_with_rand_reset.3075383520 |
|
|
Sep 02 12:35:07 AM UTC 24 |
Sep 02 12:36:16 AM UTC 24 |
229002527 ps |
| T1662 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/23.xbar_access_same_device_slow_rsp.1481416985 |
|
|
Sep 02 12:21:36 AM UTC 24 |
Sep 02 12:36:19 AM UTC 24 |
62020481429 ps |
| T1663 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/31.xbar_random.4052339113 |
|
|
Sep 02 12:35:37 AM UTC 24 |
Sep 02 12:36:20 AM UTC 24 |
345885276 ps |
| T827 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/28.xbar_stress_all_with_reset_error.1093701357 |
|
|
Sep 02 12:31:52 AM UTC 24 |
Sep 02 12:36:21 AM UTC 24 |
3981497187 ps |
| T1664 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/28.xbar_stress_all_with_error.2483173803 |
|
|
Sep 02 12:31:52 AM UTC 24 |
Sep 02 12:36:28 AM UTC 24 |
2656466364 ps |
| T1665 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/31.xbar_random_zero_delays.250563996 |
|
|
Sep 02 12:35:46 AM UTC 24 |
Sep 02 12:36:29 AM UTC 24 |
322936713 ps |
| T1666 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/31.xbar_error_and_unmapped_addr.1222906678 |
|
|
Sep 02 12:36:25 AM UTC 24 |
Sep 02 12:36:36 AM UTC 24 |
73201976 ps |
| T1667 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/31.xbar_error_random.985012791 |
|
|
Sep 02 12:36:20 AM UTC 24 |
Sep 02 12:36:36 AM UTC 24 |
353576183 ps |
| T1668 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/29.xbar_stress_all_with_reset_error.4039115984 |
|
|
Sep 02 12:33:54 AM UTC 24 |
Sep 02 12:36:41 AM UTC 24 |
429107154 ps |
| T1669 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/31.xbar_access_same_device.3246888957 |
|
|
Sep 02 12:36:00 AM UTC 24 |
Sep 02 12:36:41 AM UTC 24 |
386773050 ps |
| T1670 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/22.xbar_random_slow_rsp.428222124 |
|
|
Sep 02 12:19:49 AM UTC 24 |
Sep 02 12:36:41 AM UTC 24 |
51827416846 ps |
| T1671 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/21.xbar_random_large_delays.2930141162 |
|
|
Sep 02 12:18:08 AM UTC 24 |
Sep 02 12:37:04 AM UTC 24 |
91607194719 ps |
| T1672 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/31.xbar_stress_all.3214265925 |
|
|
Sep 02 12:36:27 AM UTC 24 |
Sep 02 12:36:45 AM UTC 24 |
376139912 ps |
| T1673 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/23.xbar_random_slow_rsp.3600709408 |
|
|
Sep 02 12:21:26 AM UTC 24 |
Sep 02 12:36:45 AM UTC 24 |
51693552285 ps |
| T1674 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/32.xbar_smoke.3949005136 |
|
|
Sep 02 12:36:34 AM UTC 24 |
Sep 02 12:36:45 AM UTC 24 |
46665905 ps |
| T1675 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/32.xbar_smoke_zero_delays.3596945736 |
|
|
Sep 02 12:36:38 AM UTC 24 |
Sep 02 12:36:49 AM UTC 24 |
53425548 ps |
| T1676 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/30.xbar_stress_all_with_error.214085973 |
|
|
Sep 02 12:35:25 AM UTC 24 |
Sep 02 12:36:58 AM UTC 24 |
2454771519 ps |
| T1677 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/31.xbar_smoke_slow_rsp.3013158128 |
|
|
Sep 02 12:35:35 AM UTC 24 |
Sep 02 12:37:13 AM UTC 24 |
5439958997 ps |
| T1678 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/32.xbar_random_zero_delays.3747967474 |
|
|
Sep 02 12:36:45 AM UTC 24 |
Sep 02 12:37:14 AM UTC 24 |
239396252 ps |
| T1679 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/31.xbar_smoke_large_delays.1115774281 |
|
|
Sep 02 12:35:29 AM UTC 24 |
Sep 02 12:37:14 AM UTC 24 |
8635438821 ps |
| T1680 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/32.xbar_error_and_unmapped_addr.1519074989 |
|
|
Sep 02 12:37:07 AM UTC 24 |
Sep 02 12:37:20 AM UTC 24 |
121786969 ps |
| T1681 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/31.xbar_unmapped_addr.1788706825 |
|
|
Sep 02 12:36:24 AM UTC 24 |
Sep 02 12:37:21 AM UTC 24 |
323497999 ps |
| T1682 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/32.xbar_unmapped_addr.2956454740 |
|
|
Sep 02 12:37:04 AM UTC 24 |
Sep 02 12:37:21 AM UTC 24 |
67265407 ps |
| T1683 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/30.xbar_random_large_delays.4055003264 |
|
|
Sep 02 12:34:17 AM UTC 24 |
Sep 02 12:37:22 AM UTC 24 |
18117017215 ps |
| T1684 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/32.xbar_error_random.763345923 |
|
|
Sep 02 12:37:04 AM UTC 24 |
Sep 02 12:37:22 AM UTC 24 |
257215907 ps |
| T1685 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/32.xbar_same_source.2669505638 |
|
|
Sep 02 12:37:03 AM UTC 24 |
Sep 02 12:37:22 AM UTC 24 |
216953808 ps |
| T1686 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/31.xbar_same_source.742911052 |
|
|
Sep 02 12:36:06 AM UTC 24 |
Sep 02 12:37:32 AM UTC 24 |
2499663496 ps |
| T809 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/22.xbar_access_same_device_slow_rsp.2715787912 |
|
|
Sep 02 12:19:51 AM UTC 24 |
Sep 02 12:37:35 AM UTC 24 |
67895895338 ps |
| T1687 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/31.xbar_access_same_device_slow_rsp.1754926887 |
|
|
Sep 02 12:36:01 AM UTC 24 |
Sep 02 12:37:40 AM UTC 24 |
5753317040 ps |
| T1688 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/33.xbar_smoke.2135624681 |
|
|
Sep 02 12:37:28 AM UTC 24 |
Sep 02 12:37:42 AM UTC 24 |
189764050 ps |
| T1689 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/33.xbar_smoke_zero_delays.3330373929 |
|
|
Sep 02 12:37:36 AM UTC 24 |
Sep 02 12:37:44 AM UTC 24 |
39930518 ps |
| T1690 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/30.xbar_stress_all.2086795454 |
|
|
Sep 02 12:35:03 AM UTC 24 |
Sep 02 12:37:45 AM UTC 24 |
4006314594 ps |
| T1691 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/32.xbar_access_same_device.1976493319 |
|
|
Sep 02 12:36:56 AM UTC 24 |
Sep 02 12:37:47 AM UTC 24 |
463005522 ps |
| T1692 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/27.xbar_stress_all_with_rand_reset.1047760921 |
|
|
Sep 02 12:29:47 AM UTC 24 |
Sep 02 12:38:01 AM UTC 24 |
7148739082 ps |
| T1693 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/32.xbar_random.1438469437 |
|
|
Sep 02 12:36:43 AM UTC 24 |
Sep 02 12:38:01 AM UTC 24 |
1565717684 ps |
| T1694 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/30.xbar_random_slow_rsp.2147361582 |
|
|
Sep 02 12:34:23 AM UTC 24 |
Sep 02 12:38:11 AM UTC 24 |
12652761412 ps |
| T1695 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/33.xbar_same_source.2638390975 |
|
|
Sep 02 12:37:54 AM UTC 24 |
Sep 02 12:38:11 AM UTC 24 |
333500012 ps |
| T1696 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/32.xbar_smoke_slow_rsp.3332711891 |
|
|
Sep 02 12:36:43 AM UTC 24 |
Sep 02 12:38:12 AM UTC 24 |
5871085493 ps |
| T433 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/3.chip_same_csr_outstanding.1448157925 |
|
|
Sep 01 11:30:47 PM UTC 24 |
Sep 02 12:38:15 AM UTC 24 |
31367767454 ps |
| T1697 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/33.xbar_error_and_unmapped_addr.3571826643 |
|
|
Sep 02 12:38:01 AM UTC 24 |
Sep 02 12:38:15 AM UTC 24 |
148526005 ps |
| T1698 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/33.xbar_unmapped_addr.1388673770 |
|
|
Sep 02 12:37:57 AM UTC 24 |
Sep 02 12:38:23 AM UTC 24 |
124572280 ps |
| T1699 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/29.chip_tl_errors.2951658189 |
|
|
Sep 02 12:32:03 AM UTC 24 |
Sep 02 12:38:32 AM UTC 24 |
4541679146 ps |
| T1700 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/34.xbar_smoke_zero_delays.2213452350 |
|
|
Sep 02 12:38:23 AM UTC 24 |
Sep 02 12:38:34 AM UTC 24 |
48648136 ps |
| T1701 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/34.xbar_smoke.635829619 |
|
|
Sep 02 12:38:24 AM UTC 24 |
Sep 02 12:38:34 AM UTC 24 |
47578622 ps |
| T1702 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/30.xbar_stress_all_with_reset_error.3060498500 |
|
|
Sep 02 12:35:25 AM UTC 24 |
Sep 02 12:38:35 AM UTC 24 |
443262450 ps |
| T1703 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/25.xbar_random_slow_rsp.1688834273 |
|
|
Sep 02 12:24:48 AM UTC 24 |
Sep 02 12:38:41 AM UTC 24 |
40542735896 ps |
| T1704 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/32.xbar_smoke_large_delays.3174691965 |
|
|
Sep 02 12:36:40 AM UTC 24 |
Sep 02 12:38:45 AM UTC 24 |
11049175075 ps |
| T1705 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/33.xbar_random.1389815807 |
|
|
Sep 02 12:37:41 AM UTC 24 |
Sep 02 12:38:53 AM UTC 24 |
1573697744 ps |
| T1706 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/33.xbar_random_zero_delays.4077817947 |
|
|
Sep 02 12:37:45 AM UTC 24 |
Sep 02 12:38:59 AM UTC 24 |
639698608 ps |
| T1707 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/33.xbar_smoke_slow_rsp.4152354023 |
|
|
Sep 02 12:37:36 AM UTC 24 |
Sep 02 12:39:01 AM UTC 24 |
5386319420 ps |
| T1708 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/33.xbar_error_random.3557247501 |
|
|
Sep 02 12:37:54 AM UTC 24 |
Sep 02 12:39:06 AM UTC 24 |
1432615518 ps |
| T1709 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/33.xbar_stress_all_with_reset_error.2066855869 |
|
|
Sep 02 12:38:10 AM UTC 24 |
Sep 02 12:39:09 AM UTC 24 |
172677131 ps |
| T1710 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/27.xbar_random_slow_rsp.774333178 |
|
|
Sep 02 12:28:48 AM UTC 24 |
Sep 02 12:39:14 AM UTC 24 |
39258888099 ps |
| T1711 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/34.xbar_access_same_device.1782362186 |
|
|
Sep 02 12:38:52 AM UTC 24 |
Sep 02 12:39:15 AM UTC 24 |
218944510 ps |
| T1712 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/34.xbar_error_and_unmapped_addr.1599779499 |
|
|
Sep 02 12:39:07 AM UTC 24 |
Sep 02 12:39:17 AM UTC 24 |
76641789 ps |
| T1713 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/34.xbar_random_zero_delays.4077085742 |
|
|
Sep 02 12:38:39 AM UTC 24 |
Sep 02 12:39:24 AM UTC 24 |
352771754 ps |
| T1714 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/33.xbar_smoke_large_delays.2724071859 |
|
|
Sep 02 12:37:37 AM UTC 24 |
Sep 02 12:39:31 AM UTC 24 |
6598133100 ps |
| T824 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/31.xbar_stress_all_with_reset_error.2207732899 |
|
|
Sep 02 12:36:27 AM UTC 24 |
Sep 02 12:39:35 AM UTC 24 |
520315236 ps |
| T498 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/29.xbar_stress_all.3418106911 |
|
|
Sep 02 12:33:31 AM UTC 24 |
Sep 02 12:39:36 AM UTC 24 |
3603325736 ps |
| T1715 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/34.xbar_random.2227769341 |
|
|
Sep 02 12:38:35 AM UTC 24 |
Sep 02 12:39:37 AM UTC 24 |
512673112 ps |
| T1716 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/35.xbar_smoke_zero_delays.40704036 |
|
|
Sep 02 12:39:31 AM UTC 24 |
Sep 02 12:39:41 AM UTC 24 |
34988872 ps |
| T1717 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/35.xbar_smoke.115701805 |
|
|
Sep 02 12:39:32 AM UTC 24 |
Sep 02 12:39:43 AM UTC 24 |
43128735 ps |
| T1718 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/18.chip_same_csr_outstanding.3516450249 |
|
|
Sep 02 12:10:32 AM UTC 24 |
Sep 02 12:39:43 AM UTC 24 |
13697874886 ps |
| T1719 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/33.xbar_access_same_device.1158680098 |
|
|
Sep 02 12:37:45 AM UTC 24 |
Sep 02 12:39:57 AM UTC 24 |
3082197716 ps |
| T1720 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/34.xbar_smoke_large_delays.1053584962 |
|
|
Sep 02 12:38:34 AM UTC 24 |
Sep 02 12:39:57 AM UTC 24 |
5615526468 ps |
| T1721 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/34.xbar_unmapped_addr.3633064739 |
|
|
Sep 02 12:39:05 AM UTC 24 |
Sep 02 12:39:59 AM UTC 24 |
1095507845 ps |
| T1722 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/35.xbar_random.562799849 |
|
|
Sep 02 12:39:47 AM UTC 24 |
Sep 02 12:40:00 AM UTC 24 |
134402544 ps |
| T1723 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/34.xbar_same_source.3532382813 |
|
|
Sep 02 12:38:57 AM UTC 24 |
Sep 02 12:40:10 AM UTC 24 |
1638128636 ps |
| T1724 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/35.xbar_error_random.1346939152 |
|
|
Sep 02 12:40:06 AM UTC 24 |
Sep 02 12:40:29 AM UTC 24 |
164370749 ps |
| T1725 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/34.xbar_smoke_slow_rsp.1666334744 |
|
|
Sep 02 12:38:34 AM UTC 24 |
Sep 02 12:40:30 AM UTC 24 |
5956249545 ps |
| T1726 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/27.xbar_random_large_delays.1944411142 |
|
|
Sep 02 12:28:45 AM UTC 24 |
Sep 02 12:40:31 AM UTC 24 |
57569478851 ps |
| T1727 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/34.xbar_error_random.1602964032 |
|
|
Sep 02 12:38:56 AM UTC 24 |
Sep 02 12:40:31 AM UTC 24 |
2162056514 ps |
| T1728 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/35.xbar_random_zero_delays.2046754538 |
|
|
Sep 02 12:39:54 AM UTC 24 |
Sep 02 12:40:31 AM UTC 24 |
434360621 ps |
| T503 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/35.xbar_same_source.1599068506 |
|
|
Sep 02 12:40:05 AM UTC 24 |
Sep 02 12:40:42 AM UTC 24 |
784182809 ps |
| T1729 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/35.xbar_unmapped_addr.4105294625 |
|
|
Sep 02 12:40:20 AM UTC 24 |
Sep 02 12:40:45 AM UTC 24 |
443595221 ps |
| T1730 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/31.xbar_stress_all_with_error.517364330 |
|
|
Sep 02 12:36:28 AM UTC 24 |
Sep 02 12:40:45 AM UTC 24 |
3112752248 ps |
| T1731 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/29.xbar_stress_all_with_rand_reset.2146467502 |
|
|
Sep 02 12:33:34 AM UTC 24 |
Sep 02 12:40:45 AM UTC 24 |
3001914832 ps |
| T822 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/32.xbar_stress_all_with_rand_reset.2341264460 |
|
|
Sep 02 12:37:09 AM UTC 24 |
Sep 02 12:40:54 AM UTC 24 |
591415541 ps |
| T1732 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/35.xbar_smoke_slow_rsp.2202849544 |
|
|
Sep 02 12:39:41 AM UTC 24 |
Sep 02 12:40:59 AM UTC 24 |
3213510006 ps |
| T1733 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/36.xbar_smoke_zero_delays.2878966007 |
|
|
Sep 02 12:40:54 AM UTC 24 |
Sep 02 12:41:05 AM UTC 24 |
42587494 ps |
| T1734 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/32.xbar_stress_all.3343341472 |
|
|
Sep 02 12:37:09 AM UTC 24 |
Sep 02 12:41:06 AM UTC 24 |
2472172584 ps |
| T1735 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/31.xbar_stress_all_with_rand_reset.1376378564 |
|
|
Sep 02 12:36:26 AM UTC 24 |
Sep 02 12:41:09 AM UTC 24 |
609470090 ps |
| T1736 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/36.xbar_smoke.843642332 |
|
|
Sep 02 12:40:53 AM UTC 24 |
Sep 02 12:41:09 AM UTC 24 |
231639586 ps |
| T1737 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/35.xbar_smoke_large_delays.3421452883 |
|
|
Sep 02 12:39:37 AM UTC 24 |
Sep 02 12:41:09 AM UTC 24 |
9797206422 ps |
| T1738 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/35.xbar_error_and_unmapped_addr.1347502825 |
|
|
Sep 02 12:40:21 AM UTC 24 |
Sep 02 12:41:39 AM UTC 24 |
1405525316 ps |
| T477 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/33.xbar_random_large_delays.1876955053 |
|
|
Sep 02 12:37:44 AM UTC 24 |
Sep 02 12:41:40 AM UTC 24 |
21959475538 ps |
| T1739 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/36.xbar_unmapped_addr.3993436184 |
|
|
Sep 02 12:41:31 AM UTC 24 |
Sep 02 12:41:49 AM UTC 24 |
226077560 ps |
| T835 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/33.xbar_stress_all_with_rand_reset.1722833158 |
|
|
Sep 02 12:38:08 AM UTC 24 |
Sep 02 12:41:50 AM UTC 24 |
314379766 ps |
| T1740 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/35.xbar_random_slow_rsp.266474955 |
|
|
Sep 02 12:39:59 AM UTC 24 |
Sep 02 12:41:54 AM UTC 24 |
6255275194 ps |
| T1741 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/26.xbar_stress_all_with_reset_error.1893876285 |
|
|
Sep 02 12:27:49 AM UTC 24 |
Sep 02 12:41:56 AM UTC 24 |
14521529093 ps |
| T1742 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/35.xbar_stress_all_with_reset_error.1117010339 |
|
|
Sep 02 12:40:50 AM UTC 24 |
Sep 02 12:42:02 AM UTC 24 |
314423466 ps |
| T1743 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/36.xbar_error_random.2921828255 |
|
|
Sep 02 12:41:29 AM UTC 24 |
Sep 02 12:42:03 AM UTC 24 |
641567533 ps |
| T1744 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/36.xbar_random.3162478381 |
|
|
Sep 02 12:41:05 AM UTC 24 |
Sep 02 12:42:11 AM UTC 24 |
1615411337 ps |
| T812 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/35.xbar_access_same_device.2710749004 |
|
|
Sep 02 12:39:57 AM UTC 24 |
Sep 02 12:42:12 AM UTC 24 |
3241622404 ps |
| T1745 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/50.xbar_smoke.1043579195 |
|
|
Sep 02 12:58:49 AM UTC 24 |
Sep 02 12:59:01 AM UTC 24 |
172625550 ps |
| T1746 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/36.xbar_error_and_unmapped_addr.3647777356 |
|
|
Sep 02 12:41:33 AM UTC 24 |
Sep 02 12:42:13 AM UTC 24 |
327085259 ps |
| T1747 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/36.xbar_random_zero_delays.755915255 |
|
|
Sep 02 12:41:08 AM UTC 24 |
Sep 02 12:42:15 AM UTC 24 |
536130424 ps |
| T1748 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/37.xbar_smoke.1639004801 |
|
|
Sep 02 12:42:11 AM UTC 24 |
Sep 02 12:42:22 AM UTC 24 |
43945223 ps |
| T1749 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/37.xbar_smoke_zero_delays.2829600808 |
|
|
Sep 02 12:42:17 AM UTC 24 |
Sep 02 12:42:26 AM UTC 24 |
46273196 ps |
| T1750 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/32.xbar_stress_all_with_error.2169661898 |
|
|
Sep 02 12:37:12 AM UTC 24 |
Sep 02 12:42:28 AM UTC 24 |
8697962125 ps |
| T1751 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/34.xbar_random_large_delays.3667046445 |
|
|
Sep 02 12:38:39 AM UTC 24 |
Sep 02 12:42:33 AM UTC 24 |
19661980024 ps |
| T1752 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/36.xbar_same_source.2484374295 |
|
|
Sep 02 12:41:26 AM UTC 24 |
Sep 02 12:42:34 AM UTC 24 |
1923843204 ps |
| T768 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/34.xbar_stress_all.1496909868 |
|
|
Sep 02 12:39:17 AM UTC 24 |
Sep 02 12:42:40 AM UTC 24 |
5055059234 ps |
| T1753 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/36.xbar_stress_all_with_reset_error.831065389 |
|
|
Sep 02 12:42:09 AM UTC 24 |
Sep 02 12:42:41 AM UTC 24 |
59368542 ps |
| T1754 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/25.xbar_random_large_delays.2285599256 |
|
|
Sep 02 12:24:43 AM UTC 24 |
Sep 02 12:42:41 AM UTC 24 |
82012919734 ps |
| T1755 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/33.xbar_stress_all.3161054194 |
|
|
Sep 02 12:38:02 AM UTC 24 |
Sep 02 12:42:45 AM UTC 24 |
5836728318 ps |
| T1756 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/36.xbar_smoke_slow_rsp.4270446512 |
|
|
Sep 02 12:40:55 AM UTC 24 |
Sep 02 12:42:50 AM UTC 24 |
5807759673 ps |
| T1757 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/37.xbar_random.3239869791 |
|
|
Sep 02 12:42:25 AM UTC 24 |
Sep 02 12:42:58 AM UTC 24 |
278933112 ps |
| T1758 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/36.xbar_smoke_large_delays.3338976152 |
|
|
Sep 02 12:40:54 AM UTC 24 |
Sep 02 12:42:59 AM UTC 24 |
7968373149 ps |
| T1759 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/37.xbar_random_zero_delays.3251569823 |
|
|
Sep 02 12:42:34 AM UTC 24 |
Sep 02 12:43:05 AM UTC 24 |
221708148 ps |
| T1760 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/33.xbar_stress_all_with_error.805949971 |
|
|
Sep 02 12:38:05 AM UTC 24 |
Sep 02 12:43:06 AM UTC 24 |
7638656170 ps |
| T1761 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/37.xbar_error_and_unmapped_addr.1563731858 |
|
|
Sep 02 12:42:53 AM UTC 24 |
Sep 02 12:43:19 AM UTC 24 |
139813016 ps |
| T1762 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/38.xbar_smoke.4031956499 |
|
|
Sep 02 12:43:13 AM UTC 24 |
Sep 02 12:43:23 AM UTC 24 |
52177739 ps |
| T1763 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/37.xbar_same_source.2827551157 |
|
|
Sep 02 12:42:47 AM UTC 24 |
Sep 02 12:43:27 AM UTC 24 |
392204357 ps |
| T1764 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/38.xbar_smoke_zero_delays.1262695409 |
|
|
Sep 02 12:43:18 AM UTC 24 |
Sep 02 12:43:29 AM UTC 24 |
46651397 ps |
| T1765 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/37.xbar_error_random.3759271137 |
|
|
Sep 02 12:42:48 AM UTC 24 |
Sep 02 12:43:30 AM UTC 24 |
482951645 ps |
| T1766 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/36.xbar_access_same_device.3302774582 |
|
|
Sep 02 12:41:17 AM UTC 24 |
Sep 02 12:43:31 AM UTC 24 |
2610184394 ps |
| T1767 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/34.xbar_stress_all_with_error.3176936576 |
|
|
Sep 02 12:39:23 AM UTC 24 |
Sep 02 12:43:40 AM UTC 24 |
5627622592 ps |
| T1768 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/37.xbar_access_same_device.523687685 |
|
|
Sep 02 12:42:38 AM UTC 24 |
Sep 02 12:43:43 AM UTC 24 |
682454867 ps |
| T1769 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/37.xbar_unmapped_addr.778621497 |
|
|
Sep 02 12:42:54 AM UTC 24 |
Sep 02 12:43:44 AM UTC 24 |
945811557 ps |
| T434 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/0.chip_same_csr_outstanding.1070699748 |
|
|
Sep 01 11:27:10 PM UTC 24 |
Sep 02 12:43:45 AM UTC 24 |
30549629380 ps |
| T1770 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/37.xbar_smoke_large_delays.61871021 |
|
|
Sep 02 12:42:19 AM UTC 24 |
Sep 02 12:43:51 AM UTC 24 |
6676896510 ps |
| T1771 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/28.xbar_access_same_device_slow_rsp.2089789378 |
|
|
Sep 02 12:30:51 AM UTC 24 |
Sep 02 12:43:54 AM UTC 24 |
47413166953 ps |
| T1772 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/37.xbar_smoke_slow_rsp.1139665203 |
|
|
Sep 02 12:42:24 AM UTC 24 |
Sep 02 12:43:59 AM UTC 24 |
5553315357 ps |
| T1773 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/38.xbar_random.2298664954 |
|
|
Sep 02 12:43:28 AM UTC 24 |
Sep 02 12:44:04 AM UTC 24 |
262014091 ps |
| T1774 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/37.xbar_stress_all_with_reset_error.3807897799 |
|
|
Sep 02 12:43:06 AM UTC 24 |
Sep 02 12:44:08 AM UTC 24 |
116037848 ps |
| T1775 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/36.xbar_random_large_delays.2160274697 |
|
|
Sep 02 12:41:07 AM UTC 24 |
Sep 02 12:44:16 AM UTC 24 |
11887373026 ps |
| T1776 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/39.xbar_smoke.2407032816 |
|
|
Sep 02 12:44:25 AM UTC 24 |
Sep 02 12:44:33 AM UTC 24 |
41458788 ps |
| T1777 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/39.xbar_smoke_zero_delays.4154416030 |
|
|
Sep 02 12:44:27 AM UTC 24 |
Sep 02 12:44:37 AM UTC 24 |
39730966 ps |