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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
96.05 95.46 93.77 95.47 94.50 97.53 99.58


Total test records in report: 2919
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T476 /workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/11.xbar_stress_all_with_rand_reset.2211461923 Sep 01 11:53:10 PM UTC 24 Sep 01 11:56:24 PM UTC 24 3441681515 ps
T1391 /workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/12.xbar_error_random.2118475448 Sep 01 11:55:20 PM UTC 24 Sep 01 11:56:26 PM UTC 24 1554965464 ps
T1392 /workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/7.chip_csr_mem_rw_with_rand_reset.1346361884 Sep 01 11:44:06 PM UTC 24 Sep 01 11:56:27 PM UTC 24 7390187276 ps
T446 /workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/10.xbar_stress_all_with_rand_reset.3461902424 Sep 01 11:50:44 PM UTC 24 Sep 01 11:56:30 PM UTC 24 2645333421 ps
T1393 /workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/12.xbar_error_and_unmapped_addr.940199565 Sep 01 11:55:53 PM UTC 24 Sep 01 11:56:34 PM UTC 24 287642081 ps
T1394 /workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/13.xbar_smoke.4045821742 Sep 01 11:56:27 PM UTC 24 Sep 01 11:56:38 PM UTC 24 48908624 ps
T1395 /workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/13.xbar_smoke_zero_delays.353480669 Sep 01 11:56:30 PM UTC 24 Sep 01 11:56:40 PM UTC 24 36117991 ps
T1396 /workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/13.xbar_random_zero_delays.3800436605 Sep 01 11:56:50 PM UTC 24 Sep 01 11:57:03 PM UTC 24 59469220 ps
T789 /workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/11.xbar_stress_all_with_error.299481347 Sep 01 11:53:11 PM UTC 24 Sep 01 11:57:08 PM UTC 24 2292753419 ps
T1397 /workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/13.xbar_random.1580559289 Sep 01 11:56:48 PM UTC 24 Sep 01 11:57:26 PM UTC 24 796628710 ps
T502 /workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/10.xbar_stress_all.719053651 Sep 01 11:50:35 PM UTC 24 Sep 01 11:57:37 PM UTC 24 9921848447 ps
T1398 /workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/10.chip_csr_rw.1160857867 Sep 01 11:51:05 PM UTC 24 Sep 01 11:57:43 PM UTC 24 3977130112 ps
T1399 /workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/13.xbar_access_same_device.2332057463 Sep 01 11:57:02 PM UTC 24 Sep 01 11:57:43 PM UTC 24 761543740 ps
T1400 /workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/13.xbar_unmapped_addr.3211128133 Sep 01 11:57:30 PM UTC 24 Sep 01 11:57:48 PM UTC 24 220941559 ps
T1401 /workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/13.xbar_error_random.2560610039 Sep 01 11:57:24 PM UTC 24 Sep 01 11:57:52 PM UTC 24 498139843 ps
T1402 /workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/13.xbar_smoke_slow_rsp.3315320146 Sep 01 11:56:44 PM UTC 24 Sep 01 11:57:56 PM UTC 24 4260148031 ps
T1403 /workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/10.xbar_random_large_delays.3644388096 Sep 01 11:49:46 PM UTC 24 Sep 01 11:58:16 PM UTC 24 41407531520 ps
T1404 /workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/13.xbar_smoke_large_delays.1502513142 Sep 01 11:56:37 PM UTC 24 Sep 01 11:58:19 PM UTC 24 8401736618 ps
T568 /workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/12.chip_tl_errors.2153139685 Sep 01 11:53:44 PM UTC 24 Sep 01 11:58:32 PM UTC 24 4342686895 ps
T1405 /workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/13.xbar_error_and_unmapped_addr.2592390723 Sep 01 11:57:48 PM UTC 24 Sep 01 11:58:33 PM UTC 24 289365443 ps
T547 /workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/11.chip_tl_errors.576729693 Sep 01 11:51:10 PM UTC 24 Sep 01 11:58:36 PM UTC 24 4711582047 ps
T1406 /workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/13.xbar_same_source.3369957228 Sep 01 11:57:02 PM UTC 24 Sep 01 11:58:41 PM UTC 24 2363079909 ps
T761 /workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/6.xbar_access_same_device_slow_rsp.968838992 Sep 01 11:40:43 PM UTC 24 Sep 01 11:58:44 PM UTC 24 74397130693 ps
T1407 /workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/14.xbar_smoke.1917748420 Sep 01 11:58:54 PM UTC 24 Sep 01 11:59:03 PM UTC 24 37616253 ps
T513 /workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/8.chip_csr_rw.4219376466 Sep 01 11:46:37 PM UTC 24 Sep 01 11:59:04 PM UTC 24 4891596380 ps
T1408 /workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/14.xbar_smoke_zero_delays.1951930005 Sep 01 11:58:56 PM UTC 24 Sep 01 11:59:06 PM UTC 24 40845240 ps
T1409 /workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/14.xbar_random.811962002 Sep 01 11:59:06 PM UTC 24 Sep 01 11:59:43 PM UTC 24 262987655 ps
T450 /workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/9.xbar_stress_all_with_rand_reset.2372956032 Sep 01 11:48:32 PM UTC 24 Sep 02 12:00:03 AM UTC 24 4132515211 ps
T514 /workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/9.chip_csr_mem_rw_with_rand_reset.1902834685 Sep 01 11:49:00 PM UTC 24 Sep 02 12:00:12 AM UTC 24 7275072330 ps
T1410 /workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/14.xbar_smoke_slow_rsp.2290616830 Sep 01 11:59:03 PM UTC 24 Sep 02 12:00:27 AM UTC 24 3557919892 ps
T1411 /workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/14.xbar_random_zero_delays.3276506845 Sep 01 11:59:25 PM UTC 24 Sep 02 12:00:30 AM UTC 24 496449850 ps
T463 /workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/13.xbar_stress_all.445121368 Sep 01 11:58:00 PM UTC 24 Sep 02 12:00:49 AM UTC 24 1880313991 ps
T1412 /workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/14.xbar_same_source.1528695670 Sep 02 12:00:33 AM UTC 24 Sep 02 12:00:53 AM UTC 24 334411224 ps
T1413 /workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/14.xbar_unmapped_addr.64196069 Sep 02 12:00:51 AM UTC 24 Sep 02 12:01:04 AM UTC 24 155864668 ps
T1414 /workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/10.xbar_stress_all_with_reset_error.2141144318 Sep 01 11:50:52 PM UTC 24 Sep 02 12:01:08 AM UTC 24 4416579455 ps
T1415 /workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/13.xbar_stress_all_with_error.1332737943 Sep 01 11:58:06 PM UTC 24 Sep 02 12:01:15 AM UTC 24 1689639669 ps
T1416 /workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/14.xbar_smoke_large_delays.2483606021 Sep 01 11:58:58 PM UTC 24 Sep 02 12:01:34 AM UTC 24 10325316694 ps
T1417 /workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/14.xbar_error_and_unmapped_addr.2279224954 Sep 02 12:01:09 AM UTC 24 Sep 02 12:01:35 AM UTC 24 356959943 ps
T456 /workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/14.xbar_access_same_device.1093754690 Sep 02 12:00:06 AM UTC 24 Sep 02 12:01:37 AM UTC 24 939690735 ps
T1418 /workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/12.xbar_stress_all.2584458095 Sep 01 11:55:54 PM UTC 24 Sep 02 12:01:53 AM UTC 24 7397274796 ps
T1419 /workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/14.xbar_stress_all.2210788682 Sep 02 12:01:14 AM UTC 24 Sep 02 12:02:00 AM UTC 24 642661262 ps
T828 /workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/12.xbar_stress_all_with_reset_error.2150674845 Sep 01 11:56:15 PM UTC 24 Sep 02 12:02:03 AM UTC 24 879824414 ps
T1420 /workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/14.xbar_error_random.19843049 Sep 02 12:00:49 AM UTC 24 Sep 02 12:02:10 AM UTC 24 1615432953 ps
T1421 /workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/15.xbar_smoke_zero_delays.204716161 Sep 02 12:02:25 AM UTC 24 Sep 02 12:02:33 AM UTC 24 54516265 ps
T1422 /workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/15.xbar_smoke.2640833145 Sep 02 12:02:22 AM UTC 24 Sep 02 12:02:35 AM UTC 24 173470304 ps
T1423 /workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/11.xbar_random_slow_rsp.1744199659 Sep 01 11:52:07 PM UTC 24 Sep 02 12:02:44 AM UTC 24 31490152731 ps
T753 /workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/9.xbar_stress_all_with_reset_error.1005820002 Sep 01 11:48:48 PM UTC 24 Sep 02 12:02:53 AM UTC 24 6559199001 ps
T561 /workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/14.chip_tl_errors.1247659400 Sep 01 11:58:42 PM UTC 24 Sep 02 12:03:06 AM UTC 24 2965152479 ps
T1424 /workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/15.xbar_random_zero_delays.2849490756 Sep 02 12:02:55 AM UTC 24 Sep 02 12:03:09 AM UTC 24 63387102 ps
T516 /workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/9.chip_csr_rw.1421395704 Sep 01 11:48:57 PM UTC 24 Sep 02 12:03:13 AM UTC 24 5584109112 ps
T604 /workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/11.chip_csr_mem_rw_with_rand_reset.202866970 Sep 01 11:53:33 PM UTC 24 Sep 02 12:03:17 AM UTC 24 7633948368 ps
T464 /workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/13.xbar_stress_all_with_rand_reset.3747547860 Sep 01 11:58:04 PM UTC 24 Sep 02 12:03:18 AM UTC 24 4469353441 ps
T1425 /workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/15.xbar_random.1261466778 Sep 02 12:02:55 AM UTC 24 Sep 02 12:03:25 AM UTC 24 214320322 ps
T601 /workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/13.chip_tl_errors.3003492501 Sep 01 11:56:24 PM UTC 24 Sep 02 12:03:35 AM UTC 24 4117032408 ps
T1426 /workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/15.xbar_smoke_slow_rsp.1734491155 Sep 02 12:02:41 AM UTC 24 Sep 02 12:03:41 AM UTC 24 3332543484 ps
T1427 /workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/12.chip_csr_mem_rw_with_rand_reset.1319679415 Sep 01 11:56:24 PM UTC 24 Sep 02 12:03:49 AM UTC 24 7033672745 ps
T1428 /workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/13.chip_csr_rw.625216165 Sep 01 11:58:14 PM UTC 24 Sep 02 12:03:57 AM UTC 24 3912394152 ps
T1429 /workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/15.xbar_error_random.3687964694 Sep 02 12:03:40 AM UTC 24 Sep 02 12:04:00 AM UTC 24 325817820 ps
T487 /workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/15.xbar_unmapped_addr.53893705 Sep 02 12:03:41 AM UTC 24 Sep 02 12:04:12 AM UTC 24 182895553 ps
T1430 /workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/15.xbar_smoke_large_delays.2321416471 Sep 02 12:02:30 AM UTC 24 Sep 02 12:04:17 AM UTC 24 7819934454 ps
T1431 /workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/15.xbar_same_source.3581718678 Sep 02 12:03:34 AM UTC 24 Sep 02 12:04:31 AM UTC 24 1294086089 ps
T837 /workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/15.xbar_stress_all_with_rand_reset.3542800371 Sep 02 12:04:03 AM UTC 24 Sep 02 12:04:54 AM UTC 24 101931758 ps
T1432 /workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/15.xbar_error_and_unmapped_addr.3976610196 Sep 02 12:03:49 AM UTC 24 Sep 02 12:04:55 AM UTC 24 1115252574 ps
T796 /workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/12.xbar_stress_all_with_error.139182095 Sep 01 11:56:06 PM UTC 24 Sep 02 12:05:05 AM UTC 24 11930948700 ps
T584 /workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/9.xbar_random_large_delays.3013261072 Sep 01 11:47:28 PM UTC 24 Sep 02 12:05:26 AM UTC 24 87141497190 ps
T1433 /workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/16.xbar_smoke.531684017 Sep 02 12:05:16 AM UTC 24 Sep 02 12:05:28 AM UTC 24 121906208 ps
T1434 /workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/16.xbar_smoke_zero_delays.3510561288 Sep 02 12:05:19 AM UTC 24 Sep 02 12:05:29 AM UTC 24 50426302 ps
T1435 /workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/15.xbar_stress_all.1458065293 Sep 02 12:03:58 AM UTC 24 Sep 02 12:05:39 AM UTC 24 2115032189 ps
T1436 /workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/11.chip_csr_rw.2735703280 Sep 01 11:53:23 PM UTC 24 Sep 02 12:05:45 AM UTC 24 6180649110 ps
T1437 /workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/15.xbar_access_same_device.4188049036 Sep 02 12:03:29 AM UTC 24 Sep 02 12:05:46 AM UTC 24 1971996011 ps
T1438 /workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/15.xbar_random_slow_rsp.2414752438 Sep 02 12:03:14 AM UTC 24 Sep 02 12:05:48 AM UTC 24 8040252129 ps
T810 /workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/11.xbar_stress_all_with_reset_error.3847045165 Sep 01 11:53:10 PM UTC 24 Sep 02 12:05:56 AM UTC 24 6156259706 ps
T381 /workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/1.chip_same_csr_outstanding.1410338605 Sep 01 11:27:15 PM UTC 24 Sep 02 12:06:03 AM UTC 24 16973649097 ps
T774 /workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/3.xbar_access_same_device_slow_rsp.1417156120 Sep 01 11:32:42 PM UTC 24 Sep 02 12:06:10 AM UTC 24 108015598262 ps
T1439 /workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/16.xbar_random_zero_delays.2679746620 Sep 02 12:05:51 AM UTC 24 Sep 02 12:06:25 AM UTC 24 327199154 ps
T811 /workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/16.xbar_access_same_device.452253236 Sep 02 12:06:07 AM UTC 24 Sep 02 12:06:53 AM UTC 24 856955894 ps
T757 /workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/14.xbar_stress_all_with_error.62165683 Sep 02 12:01:30 AM UTC 24 Sep 02 12:07:03 AM UTC 24 8145648672 ps
T1440 /workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/16.xbar_error_and_unmapped_addr.1860036271 Sep 02 12:06:45 AM UTC 24 Sep 02 12:07:09 AM UTC 24 164199672 ps
T1441 /workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/16.xbar_random.3797569552 Sep 02 12:05:50 AM UTC 24 Sep 02 12:07:11 AM UTC 24 1992372585 ps
T1442 /workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/16.xbar_same_source.4186453325 Sep 02 12:06:19 AM UTC 24 Sep 02 12:07:14 AM UTC 24 486802787 ps
T480 /workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/16.xbar_unmapped_addr.2411069468 Sep 02 12:06:32 AM UTC 24 Sep 02 12:07:26 AM UTC 24 1267270615 ps
T1443 /workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/16.xbar_error_random.215619341 Sep 02 12:06:25 AM UTC 24 Sep 02 12:07:34 AM UTC 24 1350114919 ps
T1444 /workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/16.xbar_smoke_slow_rsp.2192034440 Sep 02 12:05:49 AM UTC 24 Sep 02 12:07:34 AM UTC 24 4788438641 ps
T1445 /workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/16.xbar_smoke_large_delays.3988459992 Sep 02 12:05:27 AM UTC 24 Sep 02 12:07:42 AM UTC 24 9068364616 ps
T1446 /workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/17.xbar_smoke.2063829993 Sep 02 12:07:56 AM UTC 24 Sep 02 12:08:09 AM UTC 24 171133574 ps
T1447 /workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/17.xbar_smoke_zero_delays.3760685264 Sep 02 12:08:03 AM UTC 24 Sep 02 12:08:13 AM UTC 24 45826132 ps
T1448 /workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/13.xbar_random_large_delays.1732307718 Sep 01 11:56:54 PM UTC 24 Sep 02 12:08:28 AM UTC 24 58747842491 ps
T608 /workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/16.chip_tl_errors.1637444554 Sep 02 12:04:53 AM UTC 24 Sep 02 12:08:35 AM UTC 24 3167099818 ps
T1449 /workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/12.chip_csr_rw.2824688027 Sep 01 11:56:24 PM UTC 24 Sep 02 12:08:38 AM UTC 24 4882118982 ps
T843 /workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/15.xbar_stress_all_with_reset_error.1998970485 Sep 02 12:04:19 AM UTC 24 Sep 02 12:08:47 AM UTC 24 709656387 ps
T467 /workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/12.xbar_stress_all_with_rand_reset.3683676957 Sep 01 11:56:01 PM UTC 24 Sep 02 12:08:48 AM UTC 24 5602704554 ps
T1450 /workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/17.xbar_random_zero_delays.3409887513 Sep 02 12:08:55 AM UTC 24 Sep 02 12:09:09 AM UTC 24 74260177 ps
T1451 /workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/13.chip_csr_mem_rw_with_rand_reset.2890570469 Sep 01 11:58:19 PM UTC 24 Sep 02 12:09:20 AM UTC 24 5862790284 ps
T1452 /workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/13.xbar_random_slow_rsp.3080397780 Sep 01 11:56:57 PM UTC 24 Sep 02 12:09:22 AM UTC 24 44047597972 ps
T1453 /workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/15.chip_csr_rw.2231235788 Sep 02 12:04:21 AM UTC 24 Sep 02 12:09:33 AM UTC 24 3520065405 ps
T468 /workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/16.xbar_stress_all.1396757494 Sep 02 12:06:48 AM UTC 24 Sep 02 12:09:37 AM UTC 24 1779249829 ps
T1454 /workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/17.xbar_error_random.1577396223 Sep 02 12:09:42 AM UTC 24 Sep 02 12:09:52 AM UTC 24 34941020 ps
T1455 /workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/12.xbar_random_slow_rsp.4212487899 Sep 01 11:54:41 PM UTC 24 Sep 02 12:09:56 AM UTC 24 54769421165 ps
T762 /workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/13.xbar_stress_all_with_reset_error.1065346924 Sep 01 11:58:12 PM UTC 24 Sep 02 12:10:00 AM UTC 24 4312926869 ps
T1456 /workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/17.xbar_random.3860526994 Sep 02 12:08:50 AM UTC 24 Sep 02 12:10:01 AM UTC 24 1459520736 ps
T1457 /workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/17.xbar_error_and_unmapped_addr.3695708268 Sep 02 12:09:56 AM UTC 24 Sep 02 12:10:06 AM UTC 24 22635910 ps
T1458 /workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/17.xbar_unmapped_addr.2524645740 Sep 02 12:09:44 AM UTC 24 Sep 02 12:10:10 AM UTC 24 359223221 ps
T382 /workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/2.chip_same_csr_outstanding.1617013116 Sep 01 11:28:23 PM UTC 24 Sep 02 12:10:28 AM UTC 24 17653141681 ps
T798 /workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/16.xbar_access_same_device_slow_rsp.2280726685 Sep 02 12:06:11 AM UTC 24 Sep 02 12:10:32 AM UTC 24 16169476865 ps
T797 /workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/15.xbar_stress_all_with_error.3241042569 Sep 02 12:04:12 AM UTC 24 Sep 02 12:10:37 AM UTC 24 8478918646 ps
T1459 /workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/17.xbar_smoke_slow_rsp.2350127746 Sep 02 12:08:36 AM UTC 24 Sep 02 12:10:52 AM UTC 24 5423247186 ps
T763 /workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/17.xbar_access_same_device.1158903372 Sep 02 12:09:10 AM UTC 24 Sep 02 12:10:55 AM UTC 24 974966507 ps
T1460 /workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/17.xbar_smoke_large_delays.1128087127 Sep 02 12:08:31 AM UTC 24 Sep 02 12:10:59 AM UTC 24 8968290818 ps
T778 /workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/15.xbar_access_same_device_slow_rsp.4169568247 Sep 02 12:03:31 AM UTC 24 Sep 02 12:11:00 AM UTC 24 23806641789 ps
T1461 /workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/18.xbar_smoke.2855631989 Sep 02 12:10:55 AM UTC 24 Sep 02 12:11:04 AM UTC 24 41868375 ps
T1462 /workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/10.chip_csr_mem_rw_with_rand_reset.3903675919 Sep 01 11:51:06 PM UTC 24 Sep 02 12:11:07 AM UTC 24 11097505596 ps
T1463 /workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/18.xbar_smoke_zero_delays.1611140776 Sep 02 12:10:58 AM UTC 24 Sep 02 12:11:07 AM UTC 24 42014428 ps
T567 /workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/15.chip_tl_errors.3808894598 Sep 02 12:02:15 AM UTC 24 Sep 02 12:11:09 AM UTC 24 4767800132 ps
T486 /workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/17.xbar_same_source.1726185472 Sep 02 12:09:31 AM UTC 24 Sep 02 12:11:17 AM UTC 24 2589354772 ps
T1464 /workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/18.xbar_random.1376742749 Sep 02 12:11:22 AM UTC 24 Sep 02 12:11:34 AM UTC 24 133944248 ps
T1465 /workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/14.chip_csr_mem_rw_with_rand_reset.3560162750 Sep 02 12:01:56 AM UTC 24 Sep 02 12:11:40 AM UTC 24 7126767200 ps
T1466 /workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/12.xbar_random_large_delays.1677327708 Sep 01 11:54:39 PM UTC 24 Sep 02 12:11:42 AM UTC 24 113787617729 ps
T1467 /workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/18.xbar_random_zero_delays.3250368652 Sep 02 12:11:23 AM UTC 24 Sep 02 12:11:44 AM UTC 24 126125368 ps
T817 /workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/18.xbar_access_same_device.528906734 Sep 02 12:11:30 AM UTC 24 Sep 02 12:12:18 AM UTC 24 448138498 ps
T1468 /workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/18.xbar_same_source.1940655528 Sep 02 12:11:39 AM UTC 24 Sep 02 12:12:22 AM UTC 24 421890114 ps
T820 /workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/14.xbar_stress_all_with_rand_reset.3777337521 Sep 02 12:01:25 AM UTC 24 Sep 02 12:12:47 AM UTC 24 8749893804 ps
T1469 /workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/18.xbar_error_random.539638974 Sep 02 12:11:57 AM UTC 24 Sep 02 12:12:48 AM UTC 24 553577390 ps
T1470 /workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/18.xbar_unmapped_addr.297597511 Sep 02 12:12:03 AM UTC 24 Sep 02 12:12:49 AM UTC 24 733280338 ps
T1471 /workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/18.xbar_error_and_unmapped_addr.3433037425 Sep 02 12:12:05 AM UTC 24 Sep 02 12:12:50 AM UTC 24 792959583 ps
T1472 /workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/18.xbar_smoke_large_delays.2758102877 Sep 02 12:11:14 AM UTC 24 Sep 02 12:13:12 AM UTC 24 8199734311 ps
T834 /workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/16.xbar_stress_all_with_rand_reset.3441383424 Sep 02 12:07:14 AM UTC 24 Sep 02 12:13:20 AM UTC 24 668057031 ps
T1473 /workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/18.xbar_smoke_slow_rsp.21834569 Sep 02 12:11:18 AM UTC 24 Sep 02 12:13:29 AM UTC 24 5382451735 ps
T813 /workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/16.xbar_stress_all_with_reset_error.2028698058 Sep 02 12:07:31 AM UTC 24 Sep 02 12:13:43 AM UTC 24 3644932475 ps
T807 /workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/14.xbar_stress_all_with_reset_error.811089079 Sep 02 12:01:37 AM UTC 24 Sep 02 12:13:45 AM UTC 24 11113412267 ps
T1474 /workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/19.xbar_smoke.2488934636 Sep 02 12:13:42 AM UTC 24 Sep 02 12:13:52 AM UTC 24 51195858 ps
T758 /workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/17.xbar_stress_all_with_error.1195681583 Sep 02 12:10:18 AM UTC 24 Sep 02 12:13:53 AM UTC 24 4288942115 ps
T1475 /workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/19.xbar_smoke_zero_delays.639428673 Sep 02 12:13:52 AM UTC 24 Sep 02 12:14:03 AM UTC 24 55875840 ps
T1476 /workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/14.chip_csr_rw.2905279920 Sep 02 12:01:57 AM UTC 24 Sep 02 12:14:10 AM UTC 24 6163631300 ps
T383 /workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/5.chip_same_csr_outstanding.3310691910 Sep 01 11:36:44 PM UTC 24 Sep 02 12:14:20 AM UTC 24 15550620312 ps
T1477 /workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/18.xbar_random_large_delays.3813298363 Sep 02 12:11:25 AM UTC 24 Sep 02 12:14:24 AM UTC 24 11634878669 ps
T1478 /workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/19.xbar_random_zero_delays.2155114424 Sep 02 12:14:15 AM UTC 24 Sep 02 12:14:29 AM UTC 24 69982917 ps
T447 /workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/17.xbar_stress_all.1820813385 Sep 02 12:10:00 AM UTC 24 Sep 02 12:14:32 AM UTC 24 6326860624 ps
T788 /workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/18.xbar_stress_all_with_error.1385193626 Sep 02 12:12:45 AM UTC 24 Sep 02 12:14:39 AM UTC 24 1365178188 ps
T1479 /workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/14.xbar_random_large_delays.4153071904 Sep 01 11:59:25 PM UTC 24 Sep 02 12:15:01 AM UTC 24 84968854143 ps
T500 /workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/8.xbar_access_same_device_slow_rsp.243295858 Sep 01 11:45:41 PM UTC 24 Sep 02 12:15:03 AM UTC 24 92942520939 ps
T1480 /workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/17.xbar_random_slow_rsp.1545697035 Sep 02 12:09:09 AM UTC 24 Sep 02 12:15:03 AM UTC 24 24881517521 ps
T1481 /workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/14.xbar_random_slow_rsp.1771599070 Sep 01 11:59:28 PM UTC 24 Sep 02 12:15:05 AM UTC 24 48491041963 ps
T792 /workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/16.xbar_stress_all_with_error.3209135921 Sep 02 12:07:24 AM UTC 24 Sep 02 12:15:13 AM UTC 24 13119635586 ps
T1482 /workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/19.xbar_random.2744165180 Sep 02 12:14:14 AM UTC 24 Sep 02 12:15:13 AM UTC 24 1504439139 ps
T1483 /workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/19.xbar_smoke_slow_rsp.988293170 Sep 02 12:14:06 AM UTC 24 Sep 02 12:15:28 AM UTC 24 4350360444 ps
T1484 /workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/19.xbar_unmapped_addr.4288654552 Sep 02 12:15:02 AM UTC 24 Sep 02 12:15:42 AM UTC 24 826267236 ps
T1485 /workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/19.xbar_smoke_large_delays.903751739 Sep 02 12:14:06 AM UTC 24 Sep 02 12:15:43 AM UTC 24 6268721342 ps
T1486 /workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/19.xbar_error_random.588408958 Sep 02 12:14:53 AM UTC 24 Sep 02 12:15:51 AM UTC 24 479130447 ps
T1487 /workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/4.chip_same_csr_outstanding.3497173995 Sep 01 11:33:44 PM UTC 24 Sep 02 12:15:59 AM UTC 24 14387682055 ps
T785 /workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/17.xbar_access_same_device_slow_rsp.2018220686 Sep 02 12:09:14 AM UTC 24 Sep 02 12:16:00 AM UTC 24 22258345748 ps
T799 /workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/17.xbar_stress_all_with_reset_error.1227345698 Sep 02 12:10:19 AM UTC 24 Sep 02 12:16:04 AM UTC 24 2796658947 ps
T1488 /workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/19.chip_tl_errors.2121186560 Sep 02 12:13:34 AM UTC 24 Sep 02 12:16:06 AM UTC 24 2477935013 ps
T1489 /workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/19.xbar_error_and_unmapped_addr.2255532352 Sep 02 12:15:24 AM UTC 24 Sep 02 12:16:12 AM UTC 24 304538076 ps
T1490 /workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/20.xbar_smoke.3274802753 Sep 02 12:16:05 AM UTC 24 Sep 02 12:16:15 AM UTC 24 44061152 ps
T1491 /workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/20.xbar_random.1124921372 Sep 02 12:16:22 AM UTC 24 Sep 02 12:17:22 AM UTC 24 1171210691 ps
T1492 /workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/20.xbar_smoke_zero_delays.4171502482 Sep 02 12:16:05 AM UTC 24 Sep 02 12:16:16 AM UTC 24 44442924 ps
T505 /workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/19.xbar_same_source.485862196 Sep 02 12:14:52 AM UTC 24 Sep 02 12:16:16 AM UTC 24 2542015436 ps
T764 /workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/19.xbar_access_same_device.2794450914 Sep 02 12:14:42 AM UTC 24 Sep 02 12:16:23 AM UTC 24 1821592291 ps
T1493 /workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/19.xbar_stress_all_with_error.2637373691 Sep 02 12:15:28 AM UTC 24 Sep 02 12:16:47 AM UTC 24 1533643305 ps
T771 /workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/10.xbar_access_same_device_slow_rsp.3770057822 Sep 01 11:49:55 PM UTC 24 Sep 02 12:16:53 AM UTC 24 86800588419 ps
T1494 /workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/20.xbar_access_same_device.3240326026 Sep 02 12:16:36 AM UTC 24 Sep 02 12:16:55 AM UTC 24 250555501 ps
T793 /workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/19.xbar_access_same_device_slow_rsp.1458394050 Sep 02 12:14:46 AM UTC 24 Sep 02 12:16:59 AM UTC 24 5455280670 ps
T478 /workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/18.xbar_stress_all.3282377329 Sep 02 12:12:08 AM UTC 24 Sep 02 12:17:00 AM UTC 24 2802494511 ps
T779 /workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/12.xbar_access_same_device_slow_rsp.3728963802 Sep 01 11:55:01 PM UTC 24 Sep 02 12:17:05 AM UTC 24 73629060311 ps
T1495 /workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/16.xbar_random_slow_rsp.2665338681 Sep 02 12:06:05 AM UTC 24 Sep 02 12:17:09 AM UTC 24 38842806882 ps
T1496 /workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/19.xbar_stress_all.2013765213 Sep 02 12:15:26 AM UTC 24 Sep 02 12:17:09 AM UTC 24 1848870369 ps
T1497 /workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/20.xbar_unmapped_addr.4270807012 Sep 02 12:17:09 AM UTC 24 Sep 02 12:17:29 AM UTC 24 90026780 ps
T1498 /workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/20.xbar_error_random.2660461338 Sep 02 12:16:45 AM UTC 24 Sep 02 12:17:40 AM UTC 24 1334083215 ps
T1499 /workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/21.xbar_smoke.3372252740 Sep 02 12:17:31 AM UTC 24 Sep 02 12:17:41 AM UTC 24 38929718 ps
T471 /workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/20.xbar_random_zero_delays.2389747779 Sep 02 12:16:26 AM UTC 24 Sep 02 12:17:43 AM UTC 24 615472589 ps
T1500 /workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/20.xbar_smoke_large_delays.1147519077 Sep 02 12:16:13 AM UTC 24 Sep 02 12:17:47 AM UTC 24 6884972972 ps
T1501 /workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/20.chip_tl_errors.842078833 Sep 02 12:15:50 AM UTC 24 Sep 02 12:17:48 AM UTC 24 3014261423 ps
T1502 /workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/20.xbar_same_source.3173992054 Sep 02 12:16:39 AM UTC 24 Sep 02 12:17:53 AM UTC 24 2182342350 ps
T1503 /workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/21.xbar_smoke_zero_delays.2026243696 Sep 02 12:17:45 AM UTC 24 Sep 02 12:17:53 AM UTC 24 50924797 ps
T1504 /workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/20.xbar_error_and_unmapped_addr.419226823 Sep 02 12:17:15 AM UTC 24 Sep 02 12:17:57 AM UTC 24 272212166 ps
T562 /workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/17.chip_tl_errors.1926146913 Sep 02 12:07:56 AM UTC 24 Sep 02 12:18:04 AM UTC 24 5174490216 ps
T1505 /workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/20.xbar_smoke_slow_rsp.4166110307 Sep 02 12:16:20 AM UTC 24 Sep 02 12:18:07 AM UTC 24 4551957294 ps
T805 /workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/18.xbar_stress_all_with_rand_reset.1657795010 Sep 02 12:12:41 AM UTC 24 Sep 02 12:18:12 AM UTC 24 903307213 ps
T1506 /workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/17.chip_csr_rw.391181245 Sep 02 12:10:24 AM UTC 24 Sep 02 12:18:13 AM UTC 24 4269329721 ps
T1507 /workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/21.xbar_random.690865980 Sep 02 12:18:04 AM UTC 24 Sep 02 12:18:27 AM UTC 24 138776422 ps
T1508 /workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/18.chip_tl_errors.3702839740 Sep 02 12:10:51 AM UTC 24 Sep 02 12:18:38 AM UTC 24 3921588045 ps
T494 /workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/21.xbar_random_zero_delays.1852093387 Sep 02 12:18:03 AM UTC 24 Sep 02 12:18:51 AM UTC 24 391281302 ps
T1509 /workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/21.xbar_error_and_unmapped_addr.3455019134 Sep 02 12:18:34 AM UTC 24 Sep 02 12:19:00 AM UTC 24 424366936 ps
T1510 /workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/19.xbar_stress_all_with_reset_error.3390825773 Sep 02 12:15:28 AM UTC 24 Sep 02 12:19:06 AM UTC 24 898861503 ps
T635 /workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/21.chip_tl_errors.116269161 Sep 02 12:17:31 AM UTC 24 Sep 02 12:19:08 AM UTC 24 3100968517 ps
T1511 /workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/21.xbar_same_source.2631735388 Sep 02 12:18:17 AM UTC 24 Sep 02 12:19:10 AM UTC 24 1285968601 ps
T806 /workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/18.xbar_access_same_device_slow_rsp.4191276180 Sep 02 12:11:31 AM UTC 24 Sep 02 12:19:17 AM UTC 24 24717582427 ps
T1512 /workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/21.xbar_error_random.3071839463 Sep 02 12:18:25 AM UTC 24 Sep 02 12:19:24 AM UTC 24 515776940 ps
T1513 /workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/21.xbar_unmapped_addr.2385877115 Sep 02 12:18:29 AM UTC 24 Sep 02 12:19:25 AM UTC 24 760322555 ps
T506 /workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/17.xbar_stress_all_with_rand_reset.1578572798 Sep 02 12:10:14 AM UTC 24 Sep 02 12:19:27 AM UTC 24 9297253459 ps
T384 /workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/10.chip_same_csr_outstanding.2692541648 Sep 01 11:49:03 PM UTC 24 Sep 02 12:19:29 AM UTC 24 15287314732 ps
T1514 /workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/21.xbar_smoke_slow_rsp.1421597059 Sep 02 12:18:03 AM UTC 24 Sep 02 12:19:29 AM UTC 24 4962094034 ps
T1515 /workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/22.xbar_smoke.2703911273 Sep 02 12:19:24 AM UTC 24 Sep 02 12:19:38 AM UTC 24 182550865 ps
T1516 /workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/22.xbar_smoke_zero_delays.3060556365 Sep 02 12:19:31 AM UTC 24 Sep 02 12:19:41 AM UTC 24 48282555 ps
T1517 /workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/18.xbar_stress_all_with_reset_error.2738748948 Sep 02 12:13:09 AM UTC 24 Sep 02 12:19:47 AM UTC 24 2830713011 ps
T1518 /workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/21.xbar_smoke_large_delays.3992643333 Sep 02 12:17:52 AM UTC 24 Sep 02 12:19:48 AM UTC 24 9618940951 ps
T1519 /workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/22.xbar_random_zero_delays.2553554041 Sep 02 12:19:48 AM UTC 24 Sep 02 12:19:57 AM UTC 24 39330052 ps
T801 /workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/21.xbar_access_same_device.662452508 Sep 02 12:18:14 AM UTC 24 Sep 02 12:19:58 AM UTC 24 861724052 ps
T1520 /workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/20.xbar_random_slow_rsp.2762759305 Sep 02 12:16:35 AM UTC 24 Sep 02 12:20:09 AM UTC 24 11270881834 ps
T1521 /workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/17.xbar_random_large_delays.2216829510 Sep 02 12:08:58 AM UTC 24 Sep 02 12:20:23 AM UTC 24 55769688452 ps
T1522 /workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/19.xbar_random_slow_rsp.78943287 Sep 02 12:14:33 AM UTC 24 Sep 02 12:20:31 AM UTC 24 21325302685 ps
T754 /workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/13.xbar_access_same_device_slow_rsp.3877497252 Sep 01 11:57:02 PM UTC 24 Sep 02 12:20:34 AM UTC 24 71682980271 ps
T1523 /workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/22.xbar_same_source.1804039377 Sep 02 12:19:58 AM UTC 24 Sep 02 12:20:43 AM UTC 24 963254319 ps
T1524 /workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/22.xbar_unmapped_addr.517076617 Sep 02 12:20:09 AM UTC 24 Sep 02 12:20:51 AM UTC 24 835868167 ps
T1525 /workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/22.xbar_smoke_slow_rsp.534173193 Sep 02 12:19:33 AM UTC 24 Sep 02 12:20:51 AM UTC 24 4669692104 ps
T1526 /workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/22.xbar_error_random.1462438715 Sep 02 12:20:02 AM UTC 24 Sep 02 12:20:52 AM UTC 24 510199076 ps
T1527 /workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/22.xbar_error_and_unmapped_addr.2648664593 Sep 02 12:20:10 AM UTC 24 Sep 02 12:20:57 AM UTC 24 815465197 ps
T1528 /workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/16.chip_csr_rw.3677293022 Sep 02 12:07:33 AM UTC 24 Sep 02 12:21:02 AM UTC 24 5640189716 ps
T1529 /workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/23.xbar_smoke.2149832840 Sep 02 12:20:55 AM UTC 24 Sep 02 12:21:04 AM UTC 24 34649611 ps
T1530 /workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/22.xbar_random.1928418677 Sep 02 12:19:40 AM UTC 24 Sep 02 12:21:06 AM UTC 24 2110699259 ps
T1531 /workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/23.xbar_smoke_zero_delays.509347877 Sep 02 12:21:03 AM UTC 24 Sep 02 12:21:13 AM UTC 24 48793767 ps
T1532 /workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/8.chip_same_csr_outstanding.2009237275 Sep 01 11:44:15 PM UTC 24 Sep 02 12:21:26 AM UTC 24 16498730135 ps
T1533 /workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/22.xbar_stress_all.637311229 Sep 02 12:20:19 AM UTC 24 Sep 02 12:21:26 AM UTC 24 1125363644 ps
T1534 /workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/23.xbar_random.1262190869 Sep 02 12:21:15 AM UTC 24 Sep 02 12:21:27 AM UTC 24 71539937 ps
T1535 /workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/20.xbar_random_large_delays.4069368865 Sep 02 12:16:28 AM UTC 24 Sep 02 12:21:33 AM UTC 24 21207962096 ps
T1536 /workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/22.xbar_smoke_large_delays.4105440605 Sep 02 12:19:31 AM UTC 24 Sep 02 12:21:36 AM UTC 24 8435677638 ps
T1537 /workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/22.xbar_stress_all_with_rand_reset.1267668663 Sep 02 12:20:20 AM UTC 24 Sep 02 12:21:38 AM UTC 24 218124302 ps
T1538 /workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/22.xbar_stress_all_with_reset_error.3275228992 Sep 02 12:20:44 AM UTC 24 Sep 02 12:21:42 AM UTC 24 363876000 ps
T1539 /workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/21.xbar_stress_all.1996935230 Sep 02 12:18:35 AM UTC 24 Sep 02 12:21:55 AM UTC 24 1813664400 ps
T484 /workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/20.xbar_stress_all_with_rand_reset.4012859536 Sep 02 12:17:21 AM UTC 24 Sep 02 12:21:57 AM UTC 24 2392347732 ps
T1540 /workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/23.xbar_unmapped_addr.2154796612 Sep 02 12:21:49 AM UTC 24 Sep 02 12:22:00 AM UTC 24 90637246 ps
T1541 /workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/23.xbar_same_source.3952735272 Sep 02 12:21:47 AM UTC 24 Sep 02 12:22:06 AM UTC 24 127153166 ps
T1542 /workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/23.xbar_random_zero_delays.3634684878 Sep 02 12:21:19 AM UTC 24 Sep 02 12:22:06 AM UTC 24 333606568 ps
T1543 /workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/20.xbar_stress_all.3989495962 Sep 02 12:17:19 AM UTC 24 Sep 02 12:22:21 AM UTC 24 8632299558 ps
T1544 /workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/16.chip_csr_mem_rw_with_rand_reset.3038010038 Sep 02 12:07:35 AM UTC 24 Sep 02 12:22:26 AM UTC 24 9958628128 ps
T1545 /workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/23.xbar_smoke_large_delays.999830493 Sep 02 12:21:13 AM UTC 24 Sep 02 12:22:26 AM UTC 24 5605468627 ps
T1546 /workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/23.xbar_error_and_unmapped_addr.3274681550 Sep 02 12:21:54 AM UTC 24 Sep 02 12:22:37 AM UTC 24 664681565 ps
T1547 /workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/24.xbar_smoke.962559124 Sep 02 12:22:24 AM UTC 24 Sep 02 12:22:38 AM UTC 24 218765822 ps
T1548 /workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/24.xbar_smoke_zero_delays.135769895 Sep 02 12:22:29 AM UTC 24 Sep 02 12:22:40 AM UTC 24 52920052 ps
T1549 /workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/23.xbar_smoke_slow_rsp.4146594629 Sep 02 12:21:14 AM UTC 24 Sep 02 12:22:40 AM UTC 24 5003757621 ps
T800 /workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/22.xbar_access_same_device.1388837033 Sep 02 12:19:52 AM UTC 24 Sep 02 12:22:47 AM UTC 24 2985375882 ps
T1550 /workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/22.xbar_stress_all_with_error.3957940995 Sep 02 12:20:31 AM UTC 24 Sep 02 12:22:51 AM UTC 24 1512756032 ps
T804 /workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/23.xbar_access_same_device.1800480194 Sep 02 12:21:28 AM UTC 24 Sep 02 12:23:13 AM UTC 24 2735274114 ps
T1551 /workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/24.xbar_random.3866915850 Sep 02 12:22:49 AM UTC 24 Sep 02 12:23:28 AM UTC 24 475750699 ps
T840 /workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/19.xbar_stress_all_with_rand_reset.1428870373 Sep 02 12:15:25 AM UTC 24 Sep 02 12:23:30 AM UTC 24 5478791574 ps
T1552 /workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/22.chip_tl_errors.3002962441 Sep 02 12:19:13 AM UTC 24 Sep 02 12:23:31 AM UTC 24 3341996250 ps
T1553 /workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/24.xbar_error_random.3026839303 Sep 02 12:23:14 AM UTC 24 Sep 02 12:23:36 AM UTC 24 159627851 ps
T1554 /workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/24.xbar_random_zero_delays.1049754414 Sep 02 12:22:48 AM UTC 24 Sep 02 12:23:49 AM UTC 24 482652474 ps
T1555 /workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/23.xbar_error_random.320503596 Sep 02 12:21:49 AM UTC 24 Sep 02 12:23:53 AM UTC 24 2659889094 ps
T1556 /workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/15.chip_csr_mem_rw_with_rand_reset.3522095774 Sep 02 12:04:31 AM UTC 24 Sep 02 12:23:53 AM UTC 24 11320676578 ps
T1557 /workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/24.xbar_smoke_large_delays.2811849003 Sep 02 12:22:29 AM UTC 24 Sep 02 12:24:04 AM UTC 24 7359661025 ps
T1558 /workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/24.xbar_same_source.3123119803 Sep 02 12:23:10 AM UTC 24 Sep 02 12:24:07 AM UTC 24 1843443615 ps
T1559 /workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/24.xbar_unmapped_addr.3064349775 Sep 02 12:23:35 AM UTC 24 Sep 02 12:24:14 AM UTC 24 262886455 ps
T1560 /workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/24.xbar_stress_all_with_error.1365222530 Sep 02 12:23:59 AM UTC 24 Sep 02 12:24:15 AM UTC 24 303964486 ps
T1561 /workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/24.xbar_smoke_slow_rsp.748358711 Sep 02 12:22:43 AM UTC 24 Sep 02 12:24:17 AM UTC 24 4018747808 ps
T1562 /workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/24.xbar_error_and_unmapped_addr.171125915 Sep 02 12:23:52 AM UTC 24 Sep 02 12:24:21 AM UTC 24 484072470 ps
T1563 /workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/25.xbar_smoke.1079539571 Sep 02 12:24:16 AM UTC 24 Sep 02 12:24:25 AM UTC 24 41955631 ps
T1564 /workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/25.xbar_smoke_zero_delays.98785426 Sep 02 12:24:26 AM UTC 24 Sep 02 12:24:36 AM UTC 24 36229939 ps
T1565 /workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/24.xbar_stress_all.754043364 Sep 02 12:23:53 AM UTC 24 Sep 02 12:24:49 AM UTC 24 572803337 ps
T841 /workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/24.xbar_stress_all_with_rand_reset.2282894554 Sep 02 12:23:54 AM UTC 24 Sep 02 12:24:57 AM UTC 24 77396640 ps
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