| T1218 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/4.chip_sw_uart_tx_rx_idx1.3975769028 |
|
|
Sep 02 07:20:45 AM UTC 24 |
Sep 02 07:35:03 AM UTC 24 |
4968984590 ps |
| T1219 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/4.chip_tap_straps_testunlock0.4063558292 |
|
|
Sep 02 07:27:12 AM UTC 24 |
Sep 02 07:35:30 AM UTC 24 |
5097281735 ps |
| T1220 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/4.chip_tap_straps_rma.4020764799 |
|
|
Sep 02 07:27:44 AM UTC 24 |
Sep 02 07:35:50 AM UTC 24 |
4329833354 ps |
| T1221 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/4.chip_sw_aon_timer_sleep_wdog_sleep_pause.1060902833 |
|
|
Sep 02 07:26:16 AM UTC 24 |
Sep 02 07:36:01 AM UTC 24 |
6175201000 ps |
| T1222 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_flash_init_reduced_freq.3031599788 |
|
|
Sep 02 07:01:28 AM UTC 24 |
Sep 02 07:36:45 AM UTC 24 |
18203193620 ps |
| T1223 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/5.chip_sw_all_escalation_resets.278552938 |
|
|
Sep 02 07:28:56 AM UTC 24 |
Sep 02 07:38:03 AM UTC 24 |
5437037300 ps |
| T747 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/5.chip_sw_alert_handler_lpg_sleep_mode_alerts.2152688382 |
|
|
Sep 02 07:30:17 AM UTC 24 |
Sep 02 07:38:11 AM UTC 24 |
3316475116 ps |
| T1224 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/3.chip_tap_straps_dev.3636045411 |
|
|
Sep 02 07:18:36 AM UTC 24 |
Sep 02 07:38:17 AM UTC 24 |
8428389623 ps |
| T1225 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/5.chip_sw_lc_ctrl_transition.4111423884 |
|
|
Sep 02 07:28:55 AM UTC 24 |
Sep 02 07:38:32 AM UTC 24 |
7375769779 ps |
| T685 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/6.chip_sw_alert_handler_lpg_sleep_mode_alerts.2291448630 |
|
|
Sep 02 07:32:28 AM UTC 24 |
Sep 02 07:39:25 AM UTC 24 |
3828254332 ps |
| T106 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/7.chip_sw_alert_handler_lpg_sleep_mode_alerts.2530722935 |
|
|
Sep 02 07:34:10 AM UTC 24 |
Sep 02 07:40:33 AM UTC 24 |
3360130444 ps |
| T1226 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_otbn_ecdsa_op_irq_jitter_en.3668248286 |
|
|
Sep 02 06:16:29 AM UTC 24 |
Sep 02 07:40:42 AM UTC 24 |
18690530957 ps |
| T1227 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/5.chip_sw_uart_rand_baudrate.1402203886 |
|
|
Sep 02 07:28:54 AM UTC 24 |
Sep 02 07:41:25 AM UTC 24 |
4485946140 ps |
| T1228 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/5.chip_sw_data_integrity_escalation.707118281 |
|
|
Sep 02 07:28:54 AM UTC 24 |
Sep 02 07:42:30 AM UTC 24 |
5648334434 ps |
| T276 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/7.chip_sw_all_escalation_resets.1300564271 |
|
|
Sep 02 07:32:59 AM UTC 24 |
Sep 02 07:42:35 AM UTC 24 |
4418382312 ps |
| T1229 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/3.chip_tap_straps_prod.3629459448 |
|
|
Sep 02 07:19:28 AM UTC 24 |
Sep 02 07:42:46 AM UTC 24 |
11338885196 ps |
| T1230 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/4.chip_sw_sensor_ctrl_alert.204635913 |
|
|
Sep 02 07:27:05 AM UTC 24 |
Sep 02 07:42:49 AM UTC 24 |
7915242982 ps |
| T1231 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/4.chip_sw_uart_tx_rx_alt_clk_freq_low_speed.1315477149 |
|
|
Sep 02 07:25:23 AM UTC 24 |
Sep 02 07:43:20 AM UTC 24 |
8258978328 ps |
| T704 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/8.chip_sw_alert_handler_lpg_sleep_mode_alerts.2935452937 |
|
|
Sep 02 07:35:38 AM UTC 24 |
Sep 02 07:43:35 AM UTC 24 |
3942299140 ps |
| T1232 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/8.chip_sw_uart_rand_baudrate.1821356665 |
|
|
Sep 02 07:35:22 AM UTC 24 |
Sep 02 07:44:34 AM UTC 24 |
3504351600 ps |
| T1233 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/6.chip_sw_lc_ctrl_transition.1530616197 |
|
|
Sep 02 07:32:29 AM UTC 24 |
Sep 02 07:44:37 AM UTC 24 |
7070120592 ps |
| T622 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/9.chip_sw_alert_handler_lpg_sleep_mode_alerts.399350777 |
|
|
Sep 02 07:39:18 AM UTC 24 |
Sep 02 07:46:42 AM UTC 24 |
3953180200 ps |
| T667 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/8.chip_sw_all_escalation_resets.1094305292 |
|
|
Sep 02 07:34:51 AM UTC 24 |
Sep 02 07:47:05 AM UTC 24 |
4981037380 ps |
| T631 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/10.chip_sw_alert_handler_lpg_sleep_mode_alerts.3936281493 |
|
|
Sep 02 07:41:31 AM UTC 24 |
Sep 02 07:48:16 AM UTC 24 |
3584724610 ps |
| T210 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_flash_rma_unlocked.4125180651 |
|
|
Sep 02 05:52:58 AM UTC 24 |
Sep 02 07:48:58 AM UTC 24 |
42983839281 ps |
| T1234 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/10.chip_sw_lc_ctrl_transition.3506061884 |
|
|
Sep 02 07:40:01 AM UTC 24 |
Sep 02 07:49:02 AM UTC 24 |
7348284317 ps |
| T1235 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/8.chip_sw_lc_ctrl_transition.2557289712 |
|
|
Sep 02 07:35:25 AM UTC 24 |
Sep 02 07:49:05 AM UTC 24 |
8209281617 ps |
| T713 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/11.chip_sw_alert_handler_lpg_sleep_mode_alerts.3734057332 |
|
|
Sep 02 07:42:03 AM UTC 24 |
Sep 02 07:49:28 AM UTC 24 |
4051727848 ps |
| T1236 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/12.chip_sw_alert_handler_lpg_sleep_mode_alerts.840548962 |
|
|
Sep 02 07:44:09 AM UTC 24 |
Sep 02 07:49:49 AM UTC 24 |
4123912664 ps |
| T1237 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/7.chip_sw_lc_ctrl_transition.3239824512 |
|
|
Sep 02 07:33:43 AM UTC 24 |
Sep 02 07:49:49 AM UTC 24 |
8989006239 ps |
| T660 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/9.chip_sw_all_escalation_resets.2466571642 |
|
|
Sep 02 07:36:40 AM UTC 24 |
Sep 02 07:49:57 AM UTC 24 |
4955042700 ps |
| T725 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/10.chip_sw_all_escalation_resets.214108548 |
|
|
Sep 02 07:39:18 AM UTC 24 |
Sep 02 07:49:59 AM UTC 24 |
5227431980 ps |
| T1238 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_otbn_smoketest.353887014 |
|
|
Sep 02 07:11:13 AM UTC 24 |
Sep 02 07:51:12 AM UTC 24 |
9093202296 ps |
| T1239 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/9.chip_sw_lc_ctrl_transition.1177205169 |
|
|
Sep 02 07:37:22 AM UTC 24 |
Sep 02 07:52:28 AM UTC 24 |
8428134317 ps |
| T714 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/11.chip_sw_all_escalation_resets.307623250 |
|
|
Sep 02 07:41:29 AM UTC 24 |
Sep 02 07:53:13 AM UTC 24 |
5574219586 ps |
| T1240 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/11.chip_sw_lc_ctrl_transition.1499371214 |
|
|
Sep 02 07:41:59 AM UTC 24 |
Sep 02 07:53:42 AM UTC 24 |
6588696900 ps |
| T643 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/13.chip_sw_alert_handler_lpg_sleep_mode_alerts.397277578 |
|
|
Sep 02 07:45:22 AM UTC 24 |
Sep 02 07:54:40 AM UTC 24 |
4243450108 ps |
| T649 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/12.chip_sw_all_escalation_resets.2057790186 |
|
|
Sep 02 07:43:44 AM UTC 24 |
Sep 02 07:55:24 AM UTC 24 |
6027182540 ps |
| T1241 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_lc_walkthrough_prod.1984578555 |
|
|
Sep 02 05:57:47 AM UTC 24 |
Sep 02 07:55:27 AM UTC 24 |
50550217321 ps |
| T1242 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/14.chip_sw_uart_rand_baudrate.28420847 |
|
|
Sep 02 07:47:42 AM UTC 24 |
Sep 02 07:56:08 AM UTC 24 |
3655542924 ps |
| T1243 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/14.chip_sw_lc_ctrl_transition.1652899925 |
|
|
Sep 02 07:48:53 AM UTC 24 |
Sep 02 07:56:27 AM UTC 24 |
6420273413 ps |
| T646 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/15.chip_sw_alert_handler_lpg_sleep_mode_alerts.1726657974 |
|
|
Sep 02 07:50:14 AM UTC 24 |
Sep 02 07:56:43 AM UTC 24 |
3109869780 ps |
| T1244 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/12.chip_sw_lc_ctrl_transition.1809451626 |
|
|
Sep 02 07:43:55 AM UTC 24 |
Sep 02 07:57:00 AM UTC 24 |
11573959516 ps |
| T1245 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/1.rom_e2e_self_hash.329332633 |
|
|
Sep 02 05:33:20 AM UTC 24 |
Sep 02 07:57:22 AM UTC 24 |
26164707112 ps |
| T736 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/14.chip_sw_alert_handler_lpg_sleep_mode_alerts.4131083194 |
|
|
Sep 02 07:50:57 AM UTC 24 |
Sep 02 07:57:43 AM UTC 24 |
3338943852 ps |
| T661 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/16.chip_sw_alert_handler_lpg_sleep_mode_alerts.3845431870 |
|
|
Sep 02 07:51:03 AM UTC 24 |
Sep 02 07:58:09 AM UTC 24 |
3786595902 ps |
| T741 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/13.chip_sw_all_escalation_resets.1326085912 |
|
|
Sep 02 07:44:10 AM UTC 24 |
Sep 02 07:58:41 AM UTC 24 |
6396944708 ps |
| T1246 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/4.chip_sw_uart_tx_rx_alt_clk_freq.3862785184 |
|
|
Sep 02 07:25:23 AM UTC 24 |
Sep 02 07:59:24 AM UTC 24 |
9224308027 ps |
| T1247 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_lc_walkthrough_rma.576268585 |
|
|
Sep 02 05:58:52 AM UTC 24 |
Sep 02 08:01:02 AM UTC 24 |
48401389766 ps |
| T720 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/14.chip_sw_all_escalation_resets.2867376136 |
|
|
Sep 02 07:47:19 AM UTC 24 |
Sep 02 08:01:04 AM UTC 24 |
6583098000 ps |
| T1248 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/6.chip_sw_uart_rand_baudrate.1054030787 |
|
|
Sep 02 07:32:23 AM UTC 24 |
Sep 02 08:01:11 AM UTC 24 |
7344584812 ps |
| T670 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/15.chip_sw_all_escalation_resets.2155765712 |
|
|
Sep 02 07:50:11 AM UTC 24 |
Sep 02 08:01:38 AM UTC 24 |
4916285066 ps |
| T1249 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/7.chip_sw_uart_rand_baudrate.1944442891 |
|
|
Sep 02 07:33:42 AM UTC 24 |
Sep 02 08:01:49 AM UTC 24 |
7621843534 ps |
| T695 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/16.chip_sw_all_escalation_resets.2834439318 |
|
|
Sep 02 07:51:09 AM UTC 24 |
Sep 02 08:02:24 AM UTC 24 |
4871584366 ps |
| T662 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/18.chip_sw_alert_handler_lpg_sleep_mode_alerts.1630719354 |
|
|
Sep 02 07:54:18 AM UTC 24 |
Sep 02 08:02:48 AM UTC 24 |
4549939326 ps |
| T362 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_uart_tx_rx_bootstrap.4056991330 |
|
|
Sep 02 02:08:08 AM UTC 24 |
Sep 02 08:03:01 AM UTC 24 |
80313688310 ps |
| T668 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/19.chip_sw_alert_handler_lpg_sleep_mode_alerts.3772447201 |
|
|
Sep 02 07:56:15 AM UTC 24 |
Sep 02 08:03:08 AM UTC 24 |
3780169274 ps |
| T711 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/20.chip_sw_alert_handler_lpg_sleep_mode_alerts.703858853 |
|
|
Sep 02 07:57:04 AM UTC 24 |
Sep 02 08:03:48 AM UTC 24 |
3223445940 ps |
| T696 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/17.chip_sw_all_escalation_resets.875574580 |
|
|
Sep 02 07:51:03 AM UTC 24 |
Sep 02 08:03:48 AM UTC 24 |
6169370806 ps |
| T744 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/18.chip_sw_all_escalation_resets.2172433971 |
|
|
Sep 02 07:53:40 AM UTC 24 |
Sep 02 08:04:10 AM UTC 24 |
5878222292 ps |
| T1250 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/19.chip_sw_uart_rand_baudrate.213863367 |
|
|
Sep 02 07:56:14 AM UTC 24 |
Sep 02 08:04:19 AM UTC 24 |
4218387026 ps |
| T1251 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/9.chip_sw_uart_rand_baudrate.4068076490 |
|
|
Sep 02 07:36:41 AM UTC 24 |
Sep 02 08:04:56 AM UTC 24 |
8036308910 ps |
| T734 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/21.chip_sw_alert_handler_lpg_sleep_mode_alerts.555019850 |
|
|
Sep 02 07:57:38 AM UTC 24 |
Sep 02 08:05:04 AM UTC 24 |
3475455960 ps |
| T632 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/22.chip_sw_alert_handler_lpg_sleep_mode_alerts.3642913331 |
|
|
Sep 02 07:58:21 AM UTC 24 |
Sep 02 08:05:16 AM UTC 24 |
3536972606 ps |
| T1252 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/13.chip_sw_lc_ctrl_transition.2940533810 |
|
|
Sep 02 07:45:21 AM UTC 24 |
Sep 02 08:06:16 AM UTC 24 |
12135629511 ps |
| T265 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/19.chip_sw_all_escalation_resets.2529244289 |
|
|
Sep 02 07:55:18 AM UTC 24 |
Sep 02 08:07:06 AM UTC 24 |
5617972318 ps |
| T302 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/2.rom_e2e_asm_init_test_unlocked0.3828770278 |
|
|
Sep 02 07:07:06 AM UTC 24 |
Sep 02 08:07:37 AM UTC 24 |
11658119663 ps |
| T303 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/3.chip_sw_uart_tx_rx_alt_clk_freq.900739658 |
|
|
Sep 02 07:16:37 AM UTC 24 |
Sep 02 08:07:44 AM UTC 24 |
13666812297 ps |
| T304 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/23.chip_sw_alert_handler_lpg_sleep_mode_alerts.709434927 |
|
|
Sep 02 07:59:19 AM UTC 24 |
Sep 02 08:07:46 AM UTC 24 |
4164563816 ps |
| T305 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/21.chip_sw_all_escalation_resets.3710278896 |
|
|
Sep 02 07:57:21 AM UTC 24 |
Sep 02 08:07:58 AM UTC 24 |
5651819172 ps |
| T306 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/20.chip_sw_all_escalation_resets.3665322659 |
|
|
Sep 02 07:56:45 AM UTC 24 |
Sep 02 08:08:12 AM UTC 24 |
5193531950 ps |
| T307 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/22.chip_sw_all_escalation_resets.2626033313 |
|
|
Sep 02 07:58:00 AM UTC 24 |
Sep 02 08:08:54 AM UTC 24 |
4801535828 ps |
| T308 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/11.chip_sw_uart_rand_baudrate.3278044157 |
|
|
Sep 02 07:41:31 AM UTC 24 |
Sep 02 08:08:59 AM UTC 24 |
7471108164 ps |
| T309 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/10.chip_sw_uart_rand_baudrate.4238756786 |
|
|
Sep 02 07:39:23 AM UTC 24 |
Sep 02 08:09:47 AM UTC 24 |
8450167076 ps |
| T310 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/24.chip_sw_alert_handler_lpg_sleep_mode_alerts.543358925 |
|
|
Sep 02 08:02:33 AM UTC 24 |
Sep 02 08:10:03 AM UTC 24 |
3477780484 ps |
| T432 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/27.chip_sw_alert_handler_lpg_sleep_mode_alerts.3874050874 |
|
|
Sep 02 08:03:04 AM UTC 24 |
Sep 02 08:10:19 AM UTC 24 |
3641399400 ps |
| T107 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/26.chip_sw_alert_handler_lpg_sleep_mode_alerts.876107635 |
|
|
Sep 02 08:02:46 AM UTC 24 |
Sep 02 08:10:34 AM UTC 24 |
4148641548 ps |
| T429 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/23.chip_sw_all_escalation_resets.294458478 |
|
|
Sep 02 07:58:47 AM UTC 24 |
Sep 02 08:11:19 AM UTC 24 |
6018197520 ps |
| T700 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/29.chip_sw_alert_handler_lpg_sleep_mode_alerts.2173439617 |
|
|
Sep 02 08:04:35 AM UTC 24 |
Sep 02 08:11:46 AM UTC 24 |
3364711942 ps |
| T721 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/28.chip_sw_alert_handler_lpg_sleep_mode_alerts.1471664194 |
|
|
Sep 02 08:03:53 AM UTC 24 |
Sep 02 08:11:51 AM UTC 24 |
3409824168 ps |
| T1253 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_lc_walkthrough_dev.1907554861 |
|
|
Sep 02 05:56:19 AM UTC 24 |
Sep 02 08:12:11 AM UTC 24 |
49432061991 ps |
| T244 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_keymgr_sideload_otbn.764873325 |
|
|
Sep 02 06:36:40 AM UTC 24 |
Sep 02 08:12:40 AM UTC 24 |
17746775908 ps |
| T698 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/24.chip_sw_all_escalation_resets.11018915 |
|
|
Sep 02 08:00:02 AM UTC 24 |
Sep 02 08:12:49 AM UTC 24 |
5639003300 ps |
| T726 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/31.chip_sw_alert_handler_lpg_sleep_mode_alerts.2116198212 |
|
|
Sep 02 08:06:00 AM UTC 24 |
Sep 02 08:13:22 AM UTC 24 |
3815142670 ps |
| T745 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/30.chip_sw_alert_handler_lpg_sleep_mode_alerts.3967045412 |
|
|
Sep 02 08:05:02 AM UTC 24 |
Sep 02 08:13:42 AM UTC 24 |
4123040262 ps |
| T740 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/27.chip_sw_all_escalation_resets.206350095 |
|
|
Sep 02 08:02:46 AM UTC 24 |
Sep 02 08:13:47 AM UTC 24 |
4457437796 ps |
| T1254 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/3.chip_sw_csrng_edn_concurrency.2438420293 |
|
|
Sep 02 07:17:35 AM UTC 24 |
Sep 02 08:13:56 AM UTC 24 |
11522279696 ps |
| T718 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/32.chip_sw_alert_handler_lpg_sleep_mode_alerts.1021315656 |
|
|
Sep 02 08:06:00 AM UTC 24 |
Sep 02 08:14:18 AM UTC 24 |
4236954350 ps |
| T709 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/33.chip_sw_alert_handler_lpg_sleep_mode_alerts.3711016522 |
|
|
Sep 02 08:07:45 AM UTC 24 |
Sep 02 08:15:12 AM UTC 24 |
3824431680 ps |
| T1255 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/13.chip_sw_uart_rand_baudrate.4017759001 |
|
|
Sep 02 07:44:14 AM UTC 24 |
Sep 02 08:15:21 AM UTC 24 |
9215088524 ps |
| T654 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/31.chip_sw_all_escalation_resets.3331597075 |
|
|
Sep 02 08:05:03 AM UTC 24 |
Sep 02 08:15:40 AM UTC 24 |
5133464692 ps |
| T266 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/29.chip_sw_all_escalation_resets.874526426 |
|
|
Sep 02 08:03:54 AM UTC 24 |
Sep 02 08:15:42 AM UTC 24 |
5692673640 ps |
| T715 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/30.chip_sw_all_escalation_resets.2093771373 |
|
|
Sep 02 08:04:44 AM UTC 24 |
Sep 02 08:15:58 AM UTC 24 |
4983092440 ps |
| T693 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/26.chip_sw_all_escalation_resets.1617689508 |
|
|
Sep 02 08:03:00 AM UTC 24 |
Sep 02 08:16:03 AM UTC 24 |
5129162442 ps |
| T626 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/36.chip_sw_alert_handler_lpg_sleep_mode_alerts.4192879451 |
|
|
Sep 02 08:10:07 AM UTC 24 |
Sep 02 08:16:19 AM UTC 24 |
3201698840 ps |
| T650 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/34.chip_sw_alert_handler_lpg_sleep_mode_alerts.3027847395 |
|
|
Sep 02 08:09:08 AM UTC 24 |
Sep 02 08:16:35 AM UTC 24 |
3106450052 ps |
| T669 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/28.chip_sw_all_escalation_resets.2980510306 |
|
|
Sep 02 08:03:47 AM UTC 24 |
Sep 02 08:16:37 AM UTC 24 |
5519031688 ps |
| T1256 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/25.chip_sw_all_escalation_resets.152396799 |
|
|
Sep 02 08:02:45 AM UTC 24 |
Sep 02 08:16:37 AM UTC 24 |
5970752228 ps |
| T705 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/37.chip_sw_alert_handler_lpg_sleep_mode_alerts.1345822358 |
|
|
Sep 02 08:10:09 AM UTC 24 |
Sep 02 08:17:34 AM UTC 24 |
4013943196 ps |
| T657 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/35.chip_sw_alert_handler_lpg_sleep_mode_alerts.1931255505 |
|
|
Sep 02 08:09:11 AM UTC 24 |
Sep 02 08:17:34 AM UTC 24 |
3446083986 ps |
| T742 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/38.chip_sw_alert_handler_lpg_sleep_mode_alerts.281969533 |
|
|
Sep 02 08:10:38 AM UTC 24 |
Sep 02 08:18:12 AM UTC 24 |
4278025202 ps |
| T663 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/32.chip_sw_all_escalation_resets.3233984984 |
|
|
Sep 02 08:06:01 AM UTC 24 |
Sep 02 08:18:23 AM UTC 24 |
5857928914 ps |
| T671 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/39.chip_sw_alert_handler_lpg_sleep_mode_alerts.3926611759 |
|
|
Sep 02 08:10:57 AM UTC 24 |
Sep 02 08:18:52 AM UTC 24 |
3927018798 ps |
| T683 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/40.chip_sw_alert_handler_lpg_sleep_mode_alerts.1639576143 |
|
|
Sep 02 08:11:55 AM UTC 24 |
Sep 02 08:19:06 AM UTC 24 |
4085383668 ps |
| T623 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/35.chip_sw_all_escalation_resets.3881733610 |
|
|
Sep 02 08:09:02 AM UTC 24 |
Sep 02 08:20:02 AM UTC 24 |
6220129306 ps |
| T701 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/41.chip_sw_alert_handler_lpg_sleep_mode_alerts.2028176319 |
|
|
Sep 02 08:12:37 AM UTC 24 |
Sep 02 08:20:02 AM UTC 24 |
3393928112 ps |
| T1257 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/2.rom_e2e_shutdown_exception_c.1654133922 |
|
|
Sep 02 07:04:47 AM UTC 24 |
Sep 02 08:20:02 AM UTC 24 |
14808887254 ps |
| T684 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/37.chip_sw_all_escalation_resets.1582951380 |
|
|
Sep 02 08:09:54 AM UTC 24 |
Sep 02 08:20:16 AM UTC 24 |
4583752586 ps |
| T1258 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/43.chip_sw_alert_handler_lpg_sleep_mode_alerts.2097977017 |
|
|
Sep 02 08:14:00 AM UTC 24 |
Sep 02 08:21:09 AM UTC 24 |
3742072300 ps |
| T430 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/33.chip_sw_all_escalation_resets.2033356815 |
|
|
Sep 02 08:06:55 AM UTC 24 |
Sep 02 08:21:09 AM UTC 24 |
4990168004 ps |
| T1259 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/36.chip_sw_all_escalation_resets.1131013532 |
|
|
Sep 02 08:09:10 AM UTC 24 |
Sep 02 08:21:10 AM UTC 24 |
6061704570 ps |
| T675 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/45.chip_sw_alert_handler_lpg_sleep_mode_alerts.307168690 |
|
|
Sep 02 08:15:02 AM UTC 24 |
Sep 02 08:21:11 AM UTC 24 |
3549343638 ps |
| T665 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/38.chip_sw_all_escalation_resets.494040048 |
|
|
Sep 02 08:10:23 AM UTC 24 |
Sep 02 08:21:19 AM UTC 24 |
5438075288 ps |
| T261 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/34.chip_sw_all_escalation_resets.73883537 |
|
|
Sep 02 08:09:01 AM UTC 24 |
Sep 02 08:21:23 AM UTC 24 |
6186455176 ps |
| T108 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/44.chip_sw_alert_handler_lpg_sleep_mode_alerts.963134353 |
|
|
Sep 02 08:14:59 AM UTC 24 |
Sep 02 08:21:32 AM UTC 24 |
3374875040 ps |
| T1260 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/42.chip_sw_alert_handler_lpg_sleep_mode_alerts.4092405523 |
|
|
Sep 02 08:13:29 AM UTC 24 |
Sep 02 08:21:33 AM UTC 24 |
3946332848 ps |
| T644 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/39.chip_sw_all_escalation_resets.4127001667 |
|
|
Sep 02 08:10:53 AM UTC 24 |
Sep 02 08:21:40 AM UTC 24 |
5150435138 ps |
| T140 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_ast_clk_rst_inputs.761930493 |
|
|
Sep 02 07:04:38 AM UTC 24 |
Sep 02 08:22:02 AM UTC 24 |
23450330819 ps |
| T192 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/40.chip_sw_all_escalation_resets.3961506127 |
|
|
Sep 02 08:11:13 AM UTC 24 |
Sep 02 08:22:24 AM UTC 24 |
5181181016 ps |
| T728 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/43.chip_sw_all_escalation_resets.1666980136 |
|
|
Sep 02 08:13:30 AM UTC 24 |
Sep 02 08:22:37 AM UTC 24 |
5043808030 ps |
| T1261 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_csrng_edn_concurrency.2656971686 |
|
|
Sep 02 06:29:16 AM UTC 24 |
Sep 02 08:23:17 AM UTC 24 |
20905477676 ps |
| T710 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/46.chip_sw_alert_handler_lpg_sleep_mode_alerts.3908323017 |
|
|
Sep 02 08:16:26 AM UTC 24 |
Sep 02 08:23:26 AM UTC 24 |
3939780016 ps |
| T652 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/42.chip_sw_all_escalation_resets.2852868991 |
|
|
Sep 02 08:12:52 AM UTC 24 |
Sep 02 08:23:28 AM UTC 24 |
5582716798 ps |
| T666 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/51.chip_sw_alert_handler_lpg_sleep_mode_alerts.3333396566 |
|
|
Sep 02 08:18:26 AM UTC 24 |
Sep 02 08:24:07 AM UTC 24 |
4356814812 ps |
| T699 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/41.chip_sw_all_escalation_resets.2364379579 |
|
|
Sep 02 08:12:36 AM UTC 24 |
Sep 02 08:24:34 AM UTC 24 |
5747937424 ps |
| T658 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/48.chip_sw_alert_handler_lpg_sleep_mode_alerts.2863453694 |
|
|
Sep 02 08:17:25 AM UTC 24 |
Sep 02 08:24:40 AM UTC 24 |
3529143460 ps |
| T746 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/49.chip_sw_alert_handler_lpg_sleep_mode_alerts.140463892 |
|
|
Sep 02 08:17:50 AM UTC 24 |
Sep 02 08:24:48 AM UTC 24 |
2907106400 ps |
| T1262 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/2.rom_e2e_smoke.3813505192 |
|
|
Sep 02 07:09:01 AM UTC 24 |
Sep 02 08:24:53 AM UTC 24 |
14329508232 ps |
| T645 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/44.chip_sw_all_escalation_resets.4026842249 |
|
|
Sep 02 08:14:57 AM UTC 24 |
Sep 02 08:24:57 AM UTC 24 |
4764405646 ps |
| T1263 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/2.rom_e2e_keymgr_init_rom_ext_invalid_meas.2004618757 |
|
|
Sep 02 07:08:59 AM UTC 24 |
Sep 02 08:25:00 AM UTC 24 |
15100148530 ps |
| T640 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/47.chip_sw_alert_handler_lpg_sleep_mode_alerts.1985921582 |
|
|
Sep 02 08:17:46 AM UTC 24 |
Sep 02 08:25:34 AM UTC 24 |
3721957780 ps |
| T1264 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/2.rom_e2e_asm_init_rma.1028982490 |
|
|
Sep 02 07:06:55 AM UTC 24 |
Sep 02 08:25:44 AM UTC 24 |
15215308940 ps |
| T737 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/50.chip_sw_alert_handler_lpg_sleep_mode_alerts.2375648014 |
|
|
Sep 02 08:17:44 AM UTC 24 |
Sep 02 08:25:50 AM UTC 24 |
3658309104 ps |
| T1265 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/2.rom_e2e_keymgr_init_rom_ext_meas.2030645586 |
|
|
Sep 02 07:08:33 AM UTC 24 |
Sep 02 08:25:50 AM UTC 24 |
15356292490 ps |
| T1266 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/46.chip_sw_all_escalation_resets.181640442 |
|
|
Sep 02 08:16:15 AM UTC 24 |
Sep 02 08:26:05 AM UTC 24 |
4149139768 ps |
| T722 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/45.chip_sw_all_escalation_resets.4132813313 |
|
|
Sep 02 08:14:57 AM UTC 24 |
Sep 02 08:26:12 AM UTC 24 |
5789609904 ps |
| T647 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/52.chip_sw_alert_handler_lpg_sleep_mode_alerts.1781474279 |
|
|
Sep 02 08:19:04 AM UTC 24 |
Sep 02 08:26:17 AM UTC 24 |
4041380256 ps |
| T1267 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/2.rom_e2e_keymgr_init_rom_ext_no_meas.683152237 |
|
|
Sep 02 07:08:18 AM UTC 24 |
Sep 02 08:26:20 AM UTC 24 |
15825949356 ps |
| T1268 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/53.chip_sw_alert_handler_lpg_sleep_mode_alerts.2180627147 |
|
|
Sep 02 08:19:42 AM UTC 24 |
Sep 02 08:26:22 AM UTC 24 |
3619303104 ps |
| T1269 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/47.chip_sw_all_escalation_resets.4234130189 |
|
|
Sep 02 08:17:50 AM UTC 24 |
Sep 02 08:26:34 AM UTC 24 |
4794484348 ps |
| T627 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/50.chip_sw_all_escalation_resets.1409192146 |
|
|
Sep 02 08:18:06 AM UTC 24 |
Sep 02 08:27:01 AM UTC 24 |
5563608108 ps |
| T1270 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/2.rom_e2e_shutdown_output.2743120205 |
|
|
Sep 02 07:07:46 AM UTC 24 |
Sep 02 08:27:08 AM UTC 24 |
24862903996 ps |
| T655 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/48.chip_sw_all_escalation_resets.2542359820 |
|
|
Sep 02 08:17:45 AM UTC 24 |
Sep 02 08:27:53 AM UTC 24 |
5435522242 ps |
| T633 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/54.chip_sw_alert_handler_lpg_sleep_mode_alerts.1744942716 |
|
|
Sep 02 08:21:21 AM UTC 24 |
Sep 02 08:28:13 AM UTC 24 |
4242808856 ps |
| T719 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/55.chip_sw_alert_handler_lpg_sleep_mode_alerts.3413163569 |
|
|
Sep 02 08:21:23 AM UTC 24 |
Sep 02 08:28:17 AM UTC 24 |
4236996656 ps |
| T653 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/53.chip_sw_all_escalation_resets.1257822739 |
|
|
Sep 02 08:19:25 AM UTC 24 |
Sep 02 08:28:26 AM UTC 24 |
4996623040 ps |
| T594 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq.3357474710 |
|
|
Sep 02 06:59:40 AM UTC 24 |
Sep 02 08:28:41 AM UTC 24 |
24719481066 ps |
| T1271 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/52.chip_sw_all_escalation_resets.4128370494 |
|
|
Sep 02 08:19:03 AM UTC 24 |
Sep 02 08:29:00 AM UTC 24 |
5472311048 ps |
| T672 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/51.chip_sw_all_escalation_resets.1895672828 |
|
|
Sep 02 08:18:24 AM UTC 24 |
Sep 02 08:29:15 AM UTC 24 |
5714578264 ps |
| T370 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/58.chip_sw_alert_handler_lpg_sleep_mode_alerts.930537250 |
|
|
Sep 02 08:23:39 AM UTC 24 |
Sep 02 08:29:28 AM UTC 24 |
3708305374 ps |
| T109 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/56.chip_sw_alert_handler_lpg_sleep_mode_alerts.4040692281 |
|
|
Sep 02 08:23:24 AM UTC 24 |
Sep 02 08:29:44 AM UTC 24 |
3273260070 ps |
| T371 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/2.rom_e2e_static_critical.4085851401 |
|
|
Sep 02 07:09:01 AM UTC 24 |
Sep 02 08:29:54 AM UTC 24 |
17029511432 ps |
| T372 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/49.chip_sw_all_escalation_resets.1525433520 |
|
|
Sep 02 08:18:22 AM UTC 24 |
Sep 02 08:30:02 AM UTC 24 |
6295657384 ps |
| T373 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/59.chip_sw_alert_handler_lpg_sleep_mode_alerts.2177782116 |
|
|
Sep 02 08:24:13 AM UTC 24 |
Sep 02 08:30:10 AM UTC 24 |
3748070216 ps |
| T374 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/2.rom_e2e_asm_init_prod.632906015 |
|
|
Sep 02 07:08:57 AM UTC 24 |
Sep 02 08:30:27 AM UTC 24 |
15440690720 ps |
| T375 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/2.rom_e2e_asm_init_dev.799458998 |
|
|
Sep 02 07:09:12 AM UTC 24 |
Sep 02 08:30:50 AM UTC 24 |
15882951751 ps |
| T376 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/55.chip_sw_all_escalation_resets.1808487687 |
|
|
Sep 02 08:21:21 AM UTC 24 |
Sep 02 08:31:24 AM UTC 24 |
4573568032 ps |
| T377 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/61.chip_sw_alert_handler_lpg_sleep_mode_alerts.3384839517 |
|
|
Sep 02 08:24:43 AM UTC 24 |
Sep 02 08:31:26 AM UTC 24 |
4218464684 ps |
| T378 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/62.chip_sw_alert_handler_lpg_sleep_mode_alerts.1994664774 |
|
|
Sep 02 08:24:25 AM UTC 24 |
Sep 02 08:31:29 AM UTC 24 |
3406998360 ps |
| T1272 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/2.rom_e2e_asm_init_prod_end.489258596 |
|
|
Sep 02 07:08:38 AM UTC 24 |
Sep 02 08:31:31 AM UTC 24 |
16229614204 ps |
| T687 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/60.chip_sw_alert_handler_lpg_sleep_mode_alerts.49702518 |
|
|
Sep 02 08:26:18 AM UTC 24 |
Sep 02 08:31:55 AM UTC 24 |
3413904032 ps |
| T110 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/58.chip_sw_all_escalation_resets.26255735 |
|
|
Sep 02 08:24:23 AM UTC 24 |
Sep 02 08:32:09 AM UTC 24 |
5543500738 ps |
| T673 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/54.chip_sw_all_escalation_resets.942319337 |
|
|
Sep 02 08:21:22 AM UTC 24 |
Sep 02 08:32:51 AM UTC 24 |
5770751656 ps |
| T743 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/60.chip_sw_all_escalation_resets.2030076588 |
|
|
Sep 02 08:24:42 AM UTC 24 |
Sep 02 08:32:54 AM UTC 24 |
4956250630 ps |
| T681 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/63.chip_sw_alert_handler_lpg_sleep_mode_alerts.3370758847 |
|
|
Sep 02 08:26:22 AM UTC 24 |
Sep 02 08:33:06 AM UTC 24 |
3686106500 ps |
| T1273 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/57.chip_sw_alert_handler_lpg_sleep_mode_alerts.31855515 |
|
|
Sep 02 08:25:56 AM UTC 24 |
Sep 02 08:33:18 AM UTC 24 |
3943487574 ps |
| T267 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/63.chip_sw_all_escalation_resets.3004324785 |
|
|
Sep 02 08:24:27 AM UTC 24 |
Sep 02 08:33:19 AM UTC 24 |
5142108084 ps |
| T1274 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/66.chip_sw_alert_handler_lpg_sleep_mode_alerts.704956436 |
|
|
Sep 02 08:26:38 AM UTC 24 |
Sep 02 08:33:28 AM UTC 24 |
4229190646 ps |
| T1275 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/12.chip_sw_uart_rand_baudrate.3150208934 |
|
|
Sep 02 07:43:56 AM UTC 24 |
Sep 02 08:33:43 AM UTC 24 |
13129486272 ps |
| T677 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/59.chip_sw_all_escalation_resets.2646915431 |
|
|
Sep 02 08:23:41 AM UTC 24 |
Sep 02 08:33:47 AM UTC 24 |
5692354418 ps |
| T688 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/56.chip_sw_all_escalation_resets.2500837762 |
|
|
Sep 02 08:24:55 AM UTC 24 |
Sep 02 08:34:09 AM UTC 24 |
4399173704 ps |
| T300 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/64.chip_sw_alert_handler_lpg_sleep_mode_alerts.3060696061 |
|
|
Sep 02 08:28:10 AM UTC 24 |
Sep 02 08:34:13 AM UTC 24 |
3632253016 ps |
| T624 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/67.chip_sw_alert_handler_lpg_sleep_mode_alerts.1446629672 |
|
|
Sep 02 08:28:09 AM UTC 24 |
Sep 02 08:34:24 AM UTC 24 |
3865197192 ps |
| T731 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/61.chip_sw_all_escalation_resets.3575675962 |
|
|
Sep 02 08:23:12 AM UTC 24 |
Sep 02 08:34:42 AM UTC 24 |
6209208450 ps |
| T651 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/62.chip_sw_all_escalation_resets.2451377711 |
|
|
Sep 02 08:25:57 AM UTC 24 |
Sep 02 08:35:32 AM UTC 24 |
5256811720 ps |
| T739 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/67.chip_sw_all_escalation_resets.4039283550 |
|
|
Sep 02 08:28:13 AM UTC 24 |
Sep 02 08:35:38 AM UTC 24 |
4388759654 ps |
| T1276 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/16.chip_sw_uart_rand_baudrate.1303916066 |
|
|
Sep 02 07:51:10 AM UTC 24 |
Sep 02 08:36:15 AM UTC 24 |
13037185056 ps |
| T748 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/76.chip_sw_alert_handler_lpg_sleep_mode_alerts.2510299091 |
|
|
Sep 02 08:30:32 AM UTC 24 |
Sep 02 08:36:16 AM UTC 24 |
3606890128 ps |
| T1277 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/75.chip_sw_alert_handler_lpg_sleep_mode_alerts.2625881903 |
|
|
Sep 02 08:30:49 AM UTC 24 |
Sep 02 08:37:10 AM UTC 24 |
4005495392 ps |
| T724 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/71.chip_sw_alert_handler_lpg_sleep_mode_alerts.1873240930 |
|
|
Sep 02 08:29:41 AM UTC 24 |
Sep 02 08:37:18 AM UTC 24 |
3713368352 ps |
| T682 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/72.chip_sw_alert_handler_lpg_sleep_mode_alerts.3040882066 |
|
|
Sep 02 08:30:13 AM UTC 24 |
Sep 02 08:37:22 AM UTC 24 |
3130269780 ps |
| T738 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/66.chip_sw_all_escalation_resets.4245246939 |
|
|
Sep 02 08:27:15 AM UTC 24 |
Sep 02 08:37:28 AM UTC 24 |
4227180348 ps |
| T431 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/65.chip_sw_alert_handler_lpg_sleep_mode_alerts.1414520283 |
|
|
Sep 02 08:29:52 AM UTC 24 |
Sep 02 08:37:30 AM UTC 24 |
4417350852 ps |
| T716 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/68.chip_sw_alert_handler_lpg_sleep_mode_alerts.280291835 |
|
|
Sep 02 08:30:51 AM UTC 24 |
Sep 02 08:37:32 AM UTC 24 |
4042587192 ps |
| T111 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/73.chip_sw_alert_handler_lpg_sleep_mode_alerts.3687183116 |
|
|
Sep 02 08:31:25 AM UTC 24 |
Sep 02 08:37:42 AM UTC 24 |
3143559632 ps |
| T1278 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/18.chip_sw_uart_rand_baudrate.568846733 |
|
|
Sep 02 07:53:45 AM UTC 24 |
Sep 02 08:38:03 AM UTC 24 |
13308854894 ps |
| T1279 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/15.chip_sw_uart_rand_baudrate.2929907164 |
|
|
Sep 02 07:50:14 AM UTC 24 |
Sep 02 08:38:11 AM UTC 24 |
12984447158 ps |
| T628 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/81.chip_sw_alert_handler_lpg_sleep_mode_alerts.2329219984 |
|
|
Sep 02 08:33:09 AM UTC 24 |
Sep 02 08:38:54 AM UTC 24 |
3892235114 ps |
| T702 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/69.chip_sw_all_escalation_resets.2748641725 |
|
|
Sep 02 08:28:51 AM UTC 24 |
Sep 02 08:38:55 AM UTC 24 |
5701455260 ps |
| T648 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/78.chip_sw_alert_handler_lpg_sleep_mode_alerts.3882701641 |
|
|
Sep 02 08:33:08 AM UTC 24 |
Sep 02 08:38:57 AM UTC 24 |
3451442028 ps |
| T112 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/64.chip_sw_all_escalation_resets.3035763347 |
|
|
Sep 02 08:28:26 AM UTC 24 |
Sep 02 08:39:44 AM UTC 24 |
5619481898 ps |
| T1280 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/74.chip_sw_all_escalation_resets.3783898695 |
|
|
Sep 02 08:30:35 AM UTC 24 |
Sep 02 08:40:00 AM UTC 24 |
4413551720 ps |
| T664 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/69.chip_sw_alert_handler_lpg_sleep_mode_alerts.2596303276 |
|
|
Sep 02 08:33:17 AM UTC 24 |
Sep 02 08:40:02 AM UTC 24 |
3315070816 ps |
| T678 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/74.chip_sw_alert_handler_lpg_sleep_mode_alerts.2470743227 |
|
|
Sep 02 08:31:50 AM UTC 24 |
Sep 02 08:40:10 AM UTC 24 |
3583721830 ps |
| T1281 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/72.chip_sw_all_escalation_resets.1325665864 |
|
|
Sep 02 08:28:53 AM UTC 24 |
Sep 02 08:40:13 AM UTC 24 |
5935280150 ps |
| T732 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/65.chip_sw_all_escalation_resets.970312546 |
|
|
Sep 02 08:29:19 AM UTC 24 |
Sep 02 08:40:39 AM UTC 24 |
5708372664 ps |
| T730 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/79.chip_sw_alert_handler_lpg_sleep_mode_alerts.3795701221 |
|
|
Sep 02 08:32:42 AM UTC 24 |
Sep 02 08:40:44 AM UTC 24 |
3614467808 ps |
| T1282 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/17.chip_sw_uart_rand_baudrate.2637851166 |
|
|
Sep 02 07:51:51 AM UTC 24 |
Sep 02 08:40:44 AM UTC 24 |
12856315440 ps |
| T706 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/82.chip_sw_alert_handler_lpg_sleep_mode_alerts.2469631330 |
|
|
Sep 02 08:33:41 AM UTC 24 |
Sep 02 08:40:51 AM UTC 24 |
4230152120 ps |
| T679 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/83.chip_sw_alert_handler_lpg_sleep_mode_alerts.413729677 |
|
|
Sep 02 08:34:28 AM UTC 24 |
Sep 02 08:41:04 AM UTC 24 |
3482077368 ps |
| T641 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/68.chip_sw_all_escalation_resets.2448864019 |
|
|
Sep 02 08:29:40 AM UTC 24 |
Sep 02 08:41:05 AM UTC 24 |
5900926760 ps |
| T1283 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/71.chip_sw_all_escalation_resets.4293765482 |
|
|
Sep 02 08:29:18 AM UTC 24 |
Sep 02 08:41:07 AM UTC 24 |
5532084800 ps |
| T625 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/80.chip_sw_alert_handler_lpg_sleep_mode_alerts.3051868820 |
|
|
Sep 02 08:33:40 AM UTC 24 |
Sep 02 08:41:46 AM UTC 24 |
4584534100 ps |
| T686 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/77.chip_sw_all_escalation_resets.585025540 |
|
|
Sep 02 08:32:58 AM UTC 24 |
Sep 02 08:41:50 AM UTC 24 |
5479506524 ps |
| T749 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/88.chip_sw_alert_handler_lpg_sleep_mode_alerts.2957188245 |
|
|
Sep 02 08:35:56 AM UTC 24 |
Sep 02 08:41:51 AM UTC 24 |
3476907280 ps |
| T1284 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/77.chip_sw_alert_handler_lpg_sleep_mode_alerts.613247 |
|
|
Sep 02 08:33:58 AM UTC 24 |
Sep 02 08:41:54 AM UTC 24 |
4072973916 ps |
| T689 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/76.chip_sw_all_escalation_resets.3521615677 |
|
|
Sep 02 08:32:15 AM UTC 24 |
Sep 02 08:41:55 AM UTC 24 |
5744646970 ps |
| T697 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/87.chip_sw_alert_handler_lpg_sleep_mode_alerts.3289069889 |
|
|
Sep 02 08:35:12 AM UTC 24 |
Sep 02 08:41:58 AM UTC 24 |
4328438538 ps |
| T707 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/79.chip_sw_all_escalation_resets.3775321239 |
|
|
Sep 02 08:32:45 AM UTC 24 |
Sep 02 08:42:00 AM UTC 24 |
5823989158 ps |
| T717 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/80.chip_sw_all_escalation_resets.3535009546 |
|
|
Sep 02 08:31:54 AM UTC 24 |
Sep 02 08:42:02 AM UTC 24 |
5229031670 ps |
| T690 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/75.chip_sw_all_escalation_resets.4130911163 |
|
|
Sep 02 08:32:43 AM UTC 24 |
Sep 02 08:42:20 AM UTC 24 |
4246524720 ps |
| T1285 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/82.chip_sw_all_escalation_resets.1967904349 |
|
|
Sep 02 08:33:56 AM UTC 24 |
Sep 02 08:42:20 AM UTC 24 |
4761749146 ps |
| T691 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/70.chip_sw_all_escalation_resets.3931916759 |
|
|
Sep 02 08:30:27 AM UTC 24 |
Sep 02 08:42:45 AM UTC 24 |
4913000500 ps |
| T712 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/86.chip_sw_alert_handler_lpg_sleep_mode_alerts.1593997037 |
|
|
Sep 02 08:36:09 AM UTC 24 |
Sep 02 08:42:49 AM UTC 24 |
4155461800 ps |
| T708 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/85.chip_sw_alert_handler_lpg_sleep_mode_alerts.2586331383 |
|
|
Sep 02 08:35:52 AM UTC 24 |
Sep 02 08:42:51 AM UTC 24 |
4118720738 ps |
| T703 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/83.chip_sw_all_escalation_resets.1188327032 |
|
|
Sep 02 08:33:53 AM UTC 24 |
Sep 02 08:43:10 AM UTC 24 |
5271705704 ps |
| T676 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/89.chip_sw_alert_handler_lpg_sleep_mode_alerts.2166657589 |
|
|
Sep 02 08:36:27 AM UTC 24 |
Sep 02 08:43:11 AM UTC 24 |
4492123190 ps |
| T694 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/84.chip_sw_alert_handler_lpg_sleep_mode_alerts.3621539039 |
|
|
Sep 02 08:35:47 AM UTC 24 |
Sep 02 08:43:25 AM UTC 24 |
4346624074 ps |
| T277 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/78.chip_sw_all_escalation_resets.706708407 |
|
|
Sep 02 08:32:30 AM UTC 24 |
Sep 02 08:43:47 AM UTC 24 |
5983716860 ps |
| T629 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/81.chip_sw_all_escalation_resets.2744741685 |
|
|
Sep 02 08:33:14 AM UTC 24 |
Sep 02 08:43:50 AM UTC 24 |
4470760588 ps |
| T659 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/86.chip_sw_all_escalation_resets.3227675536 |
|
|
Sep 02 08:34:58 AM UTC 24 |
Sep 02 08:43:55 AM UTC 24 |
5977059240 ps |
| T733 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/84.chip_sw_all_escalation_resets.2868763333 |
|
|
Sep 02 08:34:58 AM UTC 24 |
Sep 02 08:44:00 AM UTC 24 |
5208731928 ps |
| T1286 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/88.chip_sw_all_escalation_resets.234587077 |
|
|
Sep 02 08:35:57 AM UTC 24 |
Sep 02 08:45:06 AM UTC 24 |
4746694470 ps |
| T1287 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/4.chip_sw_csrng_edn_concurrency.589767483 |
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|
Sep 02 07:27:02 AM UTC 24 |
Sep 02 08:45:08 AM UTC 24 |
17752463516 ps |
| T727 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/73.chip_sw_all_escalation_resets.2042567435 |
|
|
Sep 02 08:33:10 AM UTC 24 |
Sep 02 08:45:16 AM UTC 24 |
4899574940 ps |
| T630 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/85.chip_sw_all_escalation_resets.2337222329 |
|
|
Sep 02 08:35:50 AM UTC 24 |
Sep 02 08:45:17 AM UTC 24 |
4799051504 ps |
| T723 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/87.chip_sw_all_escalation_resets.2879879815 |
|
|
Sep 02 08:35:57 AM UTC 24 |
Sep 02 08:45:31 AM UTC 24 |
6256914820 ps |
| T656 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/90.chip_sw_all_escalation_resets.3499186659 |
|
|
Sep 02 08:36:31 AM UTC 24 |
Sep 02 08:45:42 AM UTC 24 |
5246396332 ps |
| T301 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/91.chip_sw_all_escalation_resets.4015758275 |
|
|
Sep 02 08:37:06 AM UTC 24 |
Sep 02 08:46:11 AM UTC 24 |
5333509960 ps |
| T642 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/93.chip_sw_all_escalation_resets.863322003 |
|
|
Sep 02 08:39:11 AM UTC 24 |
Sep 02 08:46:14 AM UTC 24 |
5030267732 ps |
| T1288 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/89.chip_sw_all_escalation_resets.2019208890 |
|
|
Sep 02 08:36:30 AM UTC 24 |
Sep 02 08:46:25 AM UTC 24 |
6542700560 ps |
| T1289 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/99.chip_sw_all_escalation_resets.2635071627 |
|
|
Sep 02 08:39:07 AM UTC 24 |
Sep 02 08:47:11 AM UTC 24 |
6003610072 ps |
| T735 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/96.chip_sw_all_escalation_resets.3080975543 |
|
|
Sep 02 08:38:57 AM UTC 24 |
Sep 02 08:47:13 AM UTC 24 |
6199120940 ps |
| T1290 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/92.chip_sw_all_escalation_resets.2413355873 |
|
|
Sep 02 08:37:05 AM UTC 24 |
Sep 02 08:47:43 AM UTC 24 |
4671011130 ps |
| T1291 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/9.chip_sw_csrng_edn_concurrency.3867322183 |
|
|
Sep 02 07:39:21 AM UTC 24 |
Sep 02 08:48:08 AM UTC 24 |
16484490124 ps |
| T1292 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/98.chip_sw_all_escalation_resets.3291890851 |
|
|
Sep 02 08:39:11 AM UTC 24 |
Sep 02 08:48:21 AM UTC 24 |
6146087388 ps |
| T1293 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/94.chip_sw_all_escalation_resets.626529643 |
|
|
Sep 02 08:39:07 AM UTC 24 |
Sep 02 08:48:35 AM UTC 24 |
4828206334 ps |
| T634 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/95.chip_sw_all_escalation_resets.1825985018 |
|
|
Sep 02 08:38:58 AM UTC 24 |
Sep 02 08:48:51 AM UTC 24 |
6341893760 ps |
| T1294 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/97.chip_sw_all_escalation_resets.3969813401 |
|
|
Sep 02 08:39:09 AM UTC 24 |
Sep 02 08:49:08 AM UTC 24 |
4998730880 ps |
| T363 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_inject_scramble_seed.930375299 |
|
|
Sep 02 04:13:07 AM UTC 24 |
Sep 02 08:55:35 AM UTC 24 |
66596699204 ps |
| T1295 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/6.chip_sw_csrng_edn_concurrency.911822064 |
|
|
Sep 02 07:32:59 AM UTC 24 |
Sep 02 08:55:55 AM UTC 24 |
18439153528 ps |
| T1296 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/5.chip_sw_csrng_edn_concurrency.537993074 |
|
|
Sep 02 07:31:09 AM UTC 24 |
Sep 02 09:03:27 AM UTC 24 |
23753407416 ps |
| T1297 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/7.chip_sw_csrng_edn_concurrency.667640014 |
|
|
Sep 02 07:34:11 AM UTC 24 |
Sep 02 09:05:57 AM UTC 24 |
22692582336 ps |
| T1298 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/8.chip_sw_csrng_edn_concurrency.752854002 |
|
|
Sep 02 07:36:05 AM UTC 24 |
Sep 02 09:08:00 AM UTC 24 |
22722570552 ps |
| T1299 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/2.rom_e2e_self_hash.1567033285 |
|
|
Sep 02 07:09:13 AM UTC 24 |
Sep 02 09:08:16 AM UTC 24 |
27183808378 ps |
| T364 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_uart_tx_rx_bootstrap.2464863323 |
|
|
Sep 02 04:12:37 AM UTC 24 |
Sep 02 09:20:26 AM UTC 24 |
79125589240 ps |
| T1300 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_inject_scramble_seed.3606700500 |
|
|
Sep 02 05:44:06 AM UTC 24 |
Sep 02 09:31:25 AM UTC 24 |
67551041455 ps |
| T1301 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_uart_tx_rx_bootstrap.1486050605 |
|
|
Sep 02 05:44:06 AM UTC 24 |
Sep 02 10:10:30 AM UTC 24 |
80756384176 ps |
| T141 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_csrng_edn_concurrency_reduced_freq.1791870107 |
|
|
Sep 02 07:03:05 AM UTC 24 |
Sep 02 10:26:37 AM UTC 24 |
83397713786 ps |
| T590 |
/workspaces/repo/scratch/os_regression_2024_08_31/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_csrng_edn_concurrency_reduced_freq.1489298942 |
|
|
Sep 02 03:01:31 AM UTC 24 |
Sep 02 10:55:45 AM UTC 24 |
160716070090 ps |