| T372 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_good_dev.240760989 |
|
|
Sep 04 08:32:03 PM UTC 24 |
Sep 04 09:40:00 PM UTC 24 |
14884890424 ps |
| T924 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sival_flash_info_access.2076755302 |
|
|
Sep 04 09:34:48 PM UTC 24 |
Sep 04 09:40:00 PM UTC 24 |
3031144880 ps |
| T925 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/0.rom_e2e_smoke.2750809756 |
|
|
Sep 04 08:29:44 PM UTC 24 |
Sep 04 09:41:26 PM UTC 24 |
14822579760 ps |
| T926 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/0.rom_e2e_sigverify_always_a_nothing_b_bad_dev.2790480671 |
|
|
Sep 04 08:36:50 PM UTC 24 |
Sep 04 09:41:35 PM UTC 24 |
14280452598 ps |
| T927 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_nothing_prod_end.1750977171 |
|
|
Sep 04 08:36:08 PM UTC 24 |
Sep 04 09:41:43 PM UTC 24 |
14969690800 ps |
| T323 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_pattgen_ios.212003386 |
|
|
Sep 04 09:38:43 PM UTC 24 |
Sep 04 09:42:28 PM UTC 24 |
3439123588 ps |
| T928 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_nothing_dev.767182772 |
|
|
Sep 04 08:34:35 PM UTC 24 |
Sep 04 09:42:31 PM UTC 24 |
14668764508 ps |
| T929 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_nothing_rma.2365718713 |
|
|
Sep 04 08:36:33 PM UTC 24 |
Sep 04 09:43:05 PM UTC 24 |
14214953760 ps |
| T368 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/0.rom_e2e_shutdown_output.3833995203 |
|
|
Sep 04 08:31:15 PM UTC 24 |
Sep 04 09:43:05 PM UTC 24 |
33769504145 ps |
| T930 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/0.rom_e2e_sigverify_always_a_nothing_b_bad_prod.446816214 |
|
|
Sep 04 08:37:15 PM UTC 24 |
Sep 04 09:43:11 PM UTC 24 |
14975047631 ps |
| T23 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_sleep_pin_mio_dio_val.2168858450 |
|
|
Sep 04 09:38:22 PM UTC 24 |
Sep 04 09:43:29 PM UTC 24 |
3412808135 ps |
| T675 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_all_escalation_resets.2259015635 |
|
|
Sep 04 09:35:23 PM UTC 24 |
Sep 04 09:43:35 PM UTC 24 |
5484877272 ps |
| T28 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_sleep_pin_wake.4116731108 |
|
|
Sep 04 09:38:44 PM UTC 24 |
Sep 04 09:44:14 PM UTC 24 |
2720880444 ps |
| T68 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_sleep_pin_retention.2486340013 |
|
|
Sep 04 09:38:23 PM UTC 24 |
Sep 04 09:44:42 PM UTC 24 |
3881314640 ps |
| T417 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_nothing_prod.1374056509 |
|
|
Sep 04 08:36:15 PM UTC 24 |
Sep 04 09:45:11 PM UTC 24 |
15111161092 ps |
| T418 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/0.rom_e2e_asm_init_dev.3741603858 |
|
|
Sep 04 08:38:56 PM UTC 24 |
Sep 04 09:45:12 PM UTC 24 |
15368083450 ps |
| T419 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq.1522989354 |
|
|
Sep 04 08:24:04 PM UTC 24 |
Sep 04 09:45:51 PM UTC 24 |
24541941151 ps |
| T420 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/0.rom_e2e_sigverify_always_a_nothing_b_bad_prod_end.204893999 |
|
|
Sep 04 08:37:34 PM UTC 24 |
Sep 04 09:46:20 PM UTC 24 |
15040459890 ps |
| T421 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_good_prod.4036316010 |
|
|
Sep 04 08:32:55 PM UTC 24 |
Sep 04 09:46:29 PM UTC 24 |
15148222744 ps |
| T287 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_data_integrity_escalation.3575082653 |
|
|
Sep 04 09:38:27 PM UTC 24 |
Sep 04 09:47:14 PM UTC 24 |
4663749976 ps |
| T422 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_good_rma.1006049996 |
|
|
Sep 04 08:33:42 PM UTC 24 |
Sep 04 09:47:40 PM UTC 24 |
15487886450 ps |
| T346 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_uart_tx_rx_idx2.2709851300 |
|
|
Sep 04 09:39:32 PM UTC 24 |
Sep 04 09:47:50 PM UTC 24 |
3655778844 ps |
| T673 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_rstmgr_rst_cnsty_escalation.3452357506 |
|
|
Sep 04 09:36:56 PM UTC 24 |
Sep 04 09:47:53 PM UTC 24 |
6207799290 ps |
| T345 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_uart_tx_rx.221457686 |
|
|
Sep 04 09:38:42 PM UTC 24 |
Sep 04 09:48:03 PM UTC 24 |
3774614106 ps |
| T77 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_spi_device_pinmux_sleep_retention.3798956151 |
|
|
Sep 04 09:44:35 PM UTC 24 |
Sep 04 09:48:17 PM UTC 24 |
2590306373 ps |
| T931 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_bad_dev.4062739490 |
|
|
Sep 04 08:36:13 PM UTC 24 |
Sep 04 09:48:41 PM UTC 24 |
15575616040 ps |
| T932 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_uart_rand_baudrate.943669300 |
|
|
Sep 04 09:41:10 PM UTC 24 |
Sep 04 09:48:56 PM UTC 24 |
3877068230 ps |
| T933 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_good_prod_end.730927855 |
|
|
Sep 04 08:33:11 PM UTC 24 |
Sep 04 09:49:25 PM UTC 24 |
15749231824 ps |
| T51 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_spi_device_tpm.3522160713 |
|
|
Sep 04 09:43:27 PM UTC 24 |
Sep 04 09:49:46 PM UTC 24 |
3694589989 ps |
| T934 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_bad_prod.4056346163 |
|
|
Sep 04 08:34:43 PM UTC 24 |
Sep 04 09:49:48 PM UTC 24 |
15383635528 ps |
| T125 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_uart_tx_rx_idx1.788886846 |
|
|
Sep 04 09:39:03 PM UTC 24 |
Sep 04 09:50:02 PM UTC 24 |
4584102696 ps |
| T935 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/0.rom_e2e_jtag_inject_test_unlocked0.3881847917 |
|
|
Sep 04 08:51:56 PM UTC 24 |
Sep 04 09:50:24 PM UTC 24 |
31331764766 ps |
| T65 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_uart_tx_rx_idx3.1544700722 |
|
|
Sep 04 09:40:19 PM UTC 24 |
Sep 04 09:50:45 PM UTC 24 |
4242781840 ps |
| T47 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_spi_host_tx_rx.3497097127 |
|
|
Sep 04 09:44:40 PM UTC 24 |
Sep 04 09:51:29 PM UTC 24 |
3494306244 ps |
| T43 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_gpio.2953608565 |
|
|
Sep 04 09:44:40 PM UTC 24 |
Sep 04 09:51:53 PM UTC 24 |
4035607012 ps |
| T251 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_flash_ctrl_lc_rw_en.4253497878 |
|
|
Sep 04 09:46:06 PM UTC 24 |
Sep 04 09:52:14 PM UTC 24 |
4938120936 ps |
| T210 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_spi_device_pass_through_collision.1111368412 |
|
|
Sep 04 09:44:34 PM UTC 24 |
Sep 04 09:52:16 PM UTC 24 |
4710558906 ps |
| T660 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/0.rom_e2e_jtag_inject_dev.1434596331 |
|
|
Sep 04 08:52:51 PM UTC 24 |
Sep 04 09:53:16 PM UTC 24 |
31247107932 ps |
| T936 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_kmac_entropy.334569993 |
|
|
Sep 04 09:49:09 PM UTC 24 |
Sep 04 09:53:17 PM UTC 24 |
2274007240 ps |
| T186 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_otp_ctrl_vendor_test_csr_access.2054928068 |
|
|
Sep 04 09:49:43 PM UTC 24 |
Sep 04 09:53:30 PM UTC 24 |
3318484041 ps |
| T937 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_flash_ctrl_idle_low_power.3313991984 |
|
|
Sep 04 09:47:13 PM UTC 24 |
Sep 04 09:53:42 PM UTC 24 |
3845690500 ps |
| T938 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_lc_ctrl_otp_hw_cfg0.42188648 |
|
|
Sep 04 09:49:05 PM UTC 24 |
Sep 04 09:53:47 PM UTC 24 |
3096632408 ps |
| T939 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/0.rom_e2e_asm_init_prod.4082194329 |
|
|
Sep 04 08:39:54 PM UTC 24 |
Sep 04 09:53:52 PM UTC 24 |
15096452560 ps |
| T940 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_otp_ctrl_ecc_error_vendor_test.721351784 |
|
|
Sep 04 09:50:10 PM UTC 24 |
Sep 04 09:54:08 PM UTC 24 |
2794579556 ps |
| T629 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_lc_ctrl_rand_to_scrap.140352677 |
|
|
Sep 04 09:50:50 PM UTC 24 |
Sep 04 09:54:25 PM UTC 24 |
2931075235 ps |
| T61 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_i2c_device_tx_rx.3056717987 |
|
|
Sep 04 09:43:26 PM UTC 24 |
Sep 04 09:54:28 PM UTC 24 |
4469486388 ps |
| T348 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_flash_ctrl_ops.1887594143 |
|
|
Sep 04 09:45:00 PM UTC 24 |
Sep 04 09:54:31 PM UTC 24 |
3612159176 ps |
| T131 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_i2c_host_tx_rx_idx1.1914796095 |
|
|
Sep 04 09:42:29 PM UTC 24 |
Sep 04 09:54:31 PM UTC 24 |
5506090520 ps |
| T630 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_lc_ctrl_volatile_raw_unlock.1168651208 |
|
|
Sep 04 09:52:14 PM UTC 24 |
Sep 04 09:54:47 PM UTC 24 |
2980095402 ps |
| T631 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz.3913156432 |
|
|
Sep 04 09:52:38 PM UTC 24 |
Sep 04 09:54:47 PM UTC 24 |
2006863637 ps |
| T59 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_i2c_host_tx_rx.3280029490 |
|
|
Sep 04 09:42:16 PM UTC 24 |
Sep 04 09:55:07 PM UTC 24 |
4440901104 ps |
| T132 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_i2c_host_tx_rx_idx2.1027586124 |
|
|
Sep 04 09:42:32 PM UTC 24 |
Sep 04 09:55:42 PM UTC 24 |
4832399192 ps |
| T349 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_flash_ctrl_ops_jitter_en.1637207938 |
|
|
Sep 04 09:45:28 PM UTC 24 |
Sep 04 09:55:45 PM UTC 24 |
4557660262 ps |
| T217 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_spi_device_pass_through.106178246 |
|
|
Sep 04 09:44:29 PM UTC 24 |
Sep 04 09:56:03 PM UTC 24 |
7794099137 ps |
| T941 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_lc_ctrl_transition.2373862249 |
|
|
Sep 04 09:50:50 PM UTC 24 |
Sep 04 09:58:00 PM UTC 24 |
7084994240 ps |
| T439 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/0.rom_e2e_jtag_inject_rma.3968609748 |
|
|
Sep 04 08:56:48 PM UTC 24 |
Sep 04 09:58:51 PM UTC 24 |
31149073092 ps |
| T942 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/0.rom_e2e_asm_init_prod_end.2380738177 |
|
|
Sep 04 08:40:47 PM UTC 24 |
Sep 04 09:59:16 PM UTC 24 |
16076686716 ps |
| T943 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_rstmgr_sw_req.2181137610 |
|
|
Sep 04 09:54:39 PM UTC 24 |
Sep 04 09:59:23 PM UTC 24 |
3772361140 ps |
| T944 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_otbn_smoketest.4021121365 |
|
|
Sep 04 09:29:34 PM UTC 24 |
Sep 04 09:59:42 PM UTC 24 |
8309506160 ps |
| T945 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_otp_ctrl_lc_signals_test_unlocked0.2922175754 |
|
|
Sep 04 09:49:29 PM UTC 24 |
Sep 04 09:59:52 PM UTC 24 |
4007624200 ps |
| T946 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_rstmgr_sw_rst.3009632614 |
|
|
Sep 04 09:54:27 PM UTC 24 |
Sep 04 10:00:19 PM UTC 24 |
2949920096 ps |
| T947 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_sleep_pwm_pulses.633685764 |
|
|
Sep 04 09:39:00 PM UTC 24 |
Sep 04 10:00:39 PM UTC 24 |
8888845272 ps |
| T948 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_bad_test_unlocked0.2079486106 |
|
|
Sep 04 08:34:31 PM UTC 24 |
Sep 04 10:01:21 PM UTC 24 |
18332755160 ps |
| T949 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_flash_ctrl_access.4242304844 |
|
|
Sep 04 09:46:06 PM UTC 24 |
Sep 04 10:02:26 PM UTC 24 |
6020678780 ps |
| T640 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_pwrmgr_sleep_disabled.418122300 |
|
|
Sep 04 09:57:14 PM UTC 24 |
Sep 04 10:02:37 PM UTC 24 |
2855748192 ps |
| T950 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_lc_walkthrough_prodend.946281530 |
|
|
Sep 04 09:51:30 PM UTC 24 |
Sep 04 10:03:13 PM UTC 24 |
8151647568 ps |
| T951 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_flash_ctrl_access_jitter_en.1845194398 |
|
|
Sep 04 09:46:37 PM UTC 24 |
Sep 04 10:03:35 PM UTC 24 |
5942715326 ps |
| T952 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/0.rom_e2e_asm_init_rma.4082471712 |
|
|
Sep 04 08:40:59 PM UTC 24 |
Sep 04 10:03:43 PM UTC 24 |
15233995727 ps |
| T953 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_pwrmgr_main_power_glitch_reset.1833029084 |
|
|
Sep 04 09:55:39 PM UTC 24 |
Sep 04 10:03:44 PM UTC 24 |
4885338076 ps |
| T91 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_usbdev_pincfg.39324316 |
|
|
Sep 04 07:34:46 PM UTC 24 |
Sep 04 10:04:06 PM UTC 24 |
31490478804 ps |
| T954 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_pwrmgr_deep_sleep_power_glitch_reset.117684230 |
|
|
Sep 04 09:57:16 PM UTC 24 |
Sep 04 10:05:46 PM UTC 24 |
5862374100 ps |
| T223 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_sysrst_ctrl_inputs.2664794294 |
|
|
Sep 04 10:00:10 PM UTC 24 |
Sep 04 10:05:49 PM UTC 24 |
3549064811 ps |
| T955 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_rv_timer_irq.226088465 |
|
|
Sep 04 09:59:36 PM UTC 24 |
Sep 04 10:05:54 PM UTC 24 |
2739656680 ps |
| T956 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_flash_ctrl_clock_freqs.4037128752 |
|
|
Sep 04 09:47:59 PM UTC 24 |
Sep 04 10:06:30 PM UTC 24 |
5933270360 ps |
| T173 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_pwrmgr_full_aon_reset.2881871339 |
|
|
Sep 04 09:56:29 PM UTC 24 |
Sep 04 10:06:34 PM UTC 24 |
9220382610 ps |
| T258 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_rstmgr_cpu_info.4247274276 |
|
|
Sep 04 09:56:08 PM UTC 24 |
Sep 04 10:07:31 PM UTC 24 |
6415466100 ps |
| T351 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_uart_tx_rx_alt_clk_freq_low_speed.2920406299 |
|
|
Sep 04 09:41:18 PM UTC 24 |
Sep 04 10:07:52 PM UTC 24 |
12927619607 ps |
| T957 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/0.rom_e2e_keymgr_init_rom_ext_meas.2316079146 |
|
|
Sep 04 09:00:43 PM UTC 24 |
Sep 04 10:08:13 PM UTC 24 |
15145438070 ps |
| T958 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_aon_timer_irq.2269099394 |
|
|
Sep 04 10:02:06 PM UTC 24 |
Sep 04 10:08:28 PM UTC 24 |
3081588288 ps |
| T49 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_sysrst_ctrl_ulp_z3_wakeup.2887241605 |
|
|
Sep 04 10:00:40 PM UTC 24 |
Sep 04 10:09:07 PM UTC 24 |
6545741156 ps |
| T959 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_pwrmgr_usb_clk_disabled_when_active.2641819400 |
|
|
Sep 04 09:58:45 PM UTC 24 |
Sep 04 10:09:20 PM UTC 24 |
5048269338 ps |
| T224 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_sysrst_ctrl_outputs.873654263 |
|
|
Sep 04 10:01:38 PM UTC 24 |
Sep 04 10:09:26 PM UTC 24 |
3188561770 ps |
| T960 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_pwrmgr_normal_sleep_por_reset.182794107 |
|
|
Sep 04 09:57:16 PM UTC 24 |
Sep 04 10:09:41 PM UTC 24 |
7033435534 ps |
| T127 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_uart_tx_rx_alt_clk_freq.1968089115 |
|
|
Sep 04 09:41:17 PM UTC 24 |
Sep 04 10:09:49 PM UTC 24 |
8723133063 ps |
| T961 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_otp_ctrl_lc_signals_dev.3519190652 |
|
|
Sep 04 09:49:28 PM UTC 24 |
Sep 04 10:10:24 PM UTC 24 |
9521658750 ps |
| T225 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_sysrst_ctrl_in_irq.2326485010 |
|
|
Sep 04 10:00:39 PM UTC 24 |
Sep 04 10:10:27 PM UTC 24 |
4656464097 ps |
| T962 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_aes_enc_jitter_en.2619052433 |
|
|
Sep 04 10:08:15 PM UTC 24 |
Sep 04 10:11:38 PM UTC 24 |
2638299482 ps |
| T963 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_otp_ctrl_lc_signals_rma.3030307502 |
|
|
Sep 04 09:49:30 PM UTC 24 |
Sep 04 10:11:39 PM UTC 24 |
8928526260 ps |
| T964 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_pwrmgr_deep_sleep_por_reset.3403346429 |
|
|
Sep 04 09:56:36 PM UTC 24 |
Sep 04 10:11:51 PM UTC 24 |
8458751200 ps |
| T965 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_pwrmgr_wdog_reset.2606819148 |
|
|
Sep 04 10:03:57 PM UTC 24 |
Sep 04 10:12:19 PM UTC 24 |
4463330136 ps |
| T392 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/0.rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0.40898187 |
|
|
Sep 04 08:34:00 PM UTC 24 |
Sep 04 10:12:23 PM UTC 24 |
17913457728 ps |
| T966 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_otp_ctrl_lc_signals_prod.4128004136 |
|
|
Sep 04 09:49:25 PM UTC 24 |
Sep 04 10:12:32 PM UTC 24 |
7641074170 ps |
| T967 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_aes_idle.666753324 |
|
|
Sep 04 10:08:38 PM UTC 24 |
Sep 04 10:12:37 PM UTC 24 |
2696089664 ps |
| T968 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_aon_timer_sleep_wdog_sleep_pause.2688622073 |
|
|
Sep 04 10:03:21 PM UTC 24 |
Sep 04 10:13:12 PM UTC 24 |
7199762836 ps |
| T969 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/0.rom_e2e_keymgr_init_rom_ext_no_meas.2329951929 |
|
|
Sep 04 09:00:46 PM UTC 24 |
Sep 04 10:13:27 PM UTC 24 |
15005174960 ps |
| T970 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_aes_enc.658245062 |
|
|
Sep 04 10:07:27 PM UTC 24 |
Sep 04 10:13:41 PM UTC 24 |
3125077268 ps |
| T361 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_adc_ctrl_sleep_debug_cable_wakeup.522824684 |
|
|
Sep 04 10:05:00 PM UTC 24 |
Sep 04 10:13:51 PM UTC 24 |
18702886788 ps |
| T74 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_alert_test.3470723740 |
|
|
Sep 04 10:09:15 PM UTC 24 |
Sep 04 10:14:12 PM UTC 24 |
2736011208 ps |
| T971 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_aes_masking_off.3793645460 |
|
|
Sep 04 10:08:58 PM UTC 24 |
Sep 04 10:14:17 PM UTC 24 |
2342427060 ps |
| T972 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_aon_timer_wdog_lc_escalate.2974322977 |
|
|
Sep 04 10:04:54 PM UTC 24 |
Sep 04 10:14:49 PM UTC 24 |
6386280696 ps |
| T288 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_otbn_mem_scramble.1682194477 |
|
|
Sep 04 10:06:54 PM UTC 24 |
Sep 04 10:15:56 PM UTC 24 |
3520589502 ps |
| T973 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_aes_entropy.3645204605 |
|
|
Sep 04 10:12:49 PM UTC 24 |
Sep 04 10:16:04 PM UTC 24 |
2969924568 ps |
| T974 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_aon_timer_wdog_bite_reset.808206561 |
|
|
Sep 04 10:03:23 PM UTC 24 |
Sep 04 10:16:05 PM UTC 24 |
7499467550 ps |
| T975 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_pwrmgr_sysrst_ctrl_reset.1666921938 |
|
|
Sep 04 09:56:34 PM UTC 24 |
Sep 04 10:16:22 PM UTC 24 |
7105960538 ps |
| T976 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_entropy_src_kat_test.2336329210 |
|
|
Sep 04 10:13:32 PM UTC 24 |
Sep 04 10:17:33 PM UTC 24 |
2370707824 ps |
| T329 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_alert_handler_lpg_sleep_mode_alerts.695789468 |
|
|
Sep 04 10:10:46 PM UTC 24 |
Sep 04 10:17:37 PM UTC 24 |
3482304118 ps |
| T99 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_alert_handler_entropy.3613028201 |
|
|
Sep 04 10:12:48 PM UTC 24 |
Sep 04 10:18:16 PM UTC 24 |
3002893205 ps |
| T376 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_alert_handler_escalation.1297004863 |
|
|
Sep 04 10:09:44 PM UTC 24 |
Sep 04 10:18:17 PM UTC 24 |
4458708840 ps |
| T377 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/0.rom_e2e_static_critical.1661784858 |
|
|
Sep 04 08:57:13 PM UTC 24 |
Sep 04 10:18:50 PM UTC 24 |
17247198412 ps |
| T378 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_alert_handler_ping_timeout.1160159552 |
|
|
Sep 04 10:10:42 PM UTC 24 |
Sep 04 10:19:13 PM UTC 24 |
4695430088 ps |
| T379 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_csrng_kat_test.2748606513 |
|
|
Sep 04 10:14:39 PM UTC 24 |
Sep 04 10:19:30 PM UTC 24 |
3136142170 ps |
| T380 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_entropy_src_ast_rng_req.1879651054 |
|
|
Sep 04 10:15:08 PM UTC 24 |
Sep 04 10:20:41 PM UTC 24 |
2803866700 ps |
| T381 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_otbn_randomness.3839244996 |
|
|
Sep 04 10:04:58 PM UTC 24 |
Sep 04 10:20:52 PM UTC 24 |
6372119032 ps |
| T382 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_rv_core_ibex_nmi_irq.3532377504 |
|
|
Sep 04 10:07:27 PM UTC 24 |
Sep 04 10:20:57 PM UTC 24 |
4755733042 ps |
| T249 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_flash_init.707187642 |
|
|
Sep 04 09:47:08 PM UTC 24 |
Sep 04 10:21:22 PM UTC 24 |
18171798550 ps |
| T613 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_edn_boot_mode.4283346915 |
|
|
Sep 04 10:13:42 PM UTC 24 |
Sep 04 10:21:48 PM UTC 24 |
3021053380 ps |
| T977 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_hmac_enc_idle.579952941 |
|
|
Sep 04 10:18:31 PM UTC 24 |
Sep 04 10:22:30 PM UTC 24 |
3075977308 ps |
| T978 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_lc_walkthrough_testunlocks.613602103 |
|
|
Sep 04 09:53:12 PM UTC 24 |
Sep 04 10:22:37 PM UTC 24 |
26700880470 ps |
| T364 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_hmac_enc_jitter_en.2847264536 |
|
|
Sep 04 10:17:21 PM UTC 24 |
Sep 04 10:22:58 PM UTC 24 |
2636270140 ps |
| T979 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_rv_core_ibex_rnd.662117058 |
|
|
Sep 04 10:06:57 PM UTC 24 |
Sep 04 10:23:11 PM UTC 24 |
5958543864 ps |
| T980 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_hmac_enc.901881343 |
|
|
Sep 04 10:17:20 PM UTC 24 |
Sep 04 10:23:27 PM UTC 24 |
3280982996 ps |
| T981 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_pwrmgr_deep_sleep_all_reset_reqs.3936325177 |
|
|
Sep 04 09:57:17 PM UTC 24 |
Sep 04 10:23:32 PM UTC 24 |
16366279727 ps |
| T982 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_hmac_oneshot.3589390840 |
|
|
Sep 04 10:18:31 PM UTC 24 |
Sep 04 10:23:42 PM UTC 24 |
2691177560 ps |
| T983 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_csrng_lc_hw_debug_en_test.2553501243 |
|
|
Sep 04 10:14:33 PM UTC 24 |
Sep 04 10:24:04 PM UTC 24 |
5609402952 ps |
| T393 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/0.rom_e2e_boot_policy_valid_a_bad_b_good_prod.2189438756 |
|
|
Sep 04 08:33:08 PM UTC 24 |
Sep 04 10:24:24 PM UTC 24 |
24222038476 ps |
| T984 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_pwrmgr_all_reset_reqs.3548247084 |
|
|
Sep 04 09:56:52 PM UTC 24 |
Sep 04 10:24:34 PM UTC 24 |
10600500601 ps |
| T985 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_edn_kat.2047246408 |
|
|
Sep 04 10:13:39 PM UTC 24 |
Sep 04 10:24:38 PM UTC 24 |
3981170134 ps |
| T986 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_csrng_fuse_en_sw_app_read_test.355704676 |
|
|
Sep 04 10:15:08 PM UTC 24 |
Sep 04 10:24:42 PM UTC 24 |
5552768760 ps |
| T987 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_pwrmgr_normal_sleep_all_reset_reqs.2335070577 |
|
|
Sep 04 09:57:18 PM UTC 24 |
Sep 04 10:24:47 PM UTC 24 |
12763073269 ps |
| T988 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_sysrst_ctrl_reset.2793328160 |
|
|
Sep 04 10:01:00 PM UTC 24 |
Sep 04 10:25:07 PM UTC 24 |
23831156400 ps |
| T989 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_kmac_mode_cshake.305727369 |
|
|
Sep 04 10:21:53 PM UTC 24 |
Sep 04 10:25:35 PM UTC 24 |
2960845448 ps |
| T135 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_csrng_edn_concurrency_reduced_freq.2870875410 |
|
|
Sep 04 08:25:45 PM UTC 24 |
Sep 04 10:25:41 PM UTC 24 |
33133645759 ps |
| T990 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_kmac_idle.2682293872 |
|
|
Sep 04 10:23:27 PM UTC 24 |
Sep 04 10:26:36 PM UTC 24 |
2653226860 ps |
| T991 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_kmac_mode_kmac.1734556452 |
|
|
Sep 04 10:22:08 PM UTC 24 |
Sep 04 10:27:03 PM UTC 24 |
3033911680 ps |
| T342 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_rstmgr_alert_info.2369602708 |
|
|
Sep 04 09:56:32 PM UTC 24 |
Sep 04 10:27:49 PM UTC 24 |
12289901048 ps |
| T992 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_kmac_mode_kmac_jitter_en.1484683629 |
|
|
Sep 04 10:22:33 PM UTC 24 |
Sep 04 10:28:13 PM UTC 24 |
3457496297 ps |
| T406 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_kmac_app_rom.1525037777 |
|
|
Sep 04 10:23:26 PM UTC 24 |
Sep 04 10:28:32 PM UTC 24 |
2634308760 ps |
| T993 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_pwrmgr_random_sleep_all_reset_reqs.1316240730 |
|
|
Sep 04 09:56:36 PM UTC 24 |
Sep 04 10:29:37 PM UTC 24 |
24211412159 ps |
| T994 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/0.rom_e2e_keymgr_init_rom_ext_invalid_meas.3265540353 |
|
|
Sep 04 09:15:52 PM UTC 24 |
Sep 04 10:29:52 PM UTC 24 |
14630981208 ps |
| T394 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/0.rom_e2e_boot_policy_valid_a_bad_b_good_dev.3026284759 |
|
|
Sep 04 08:33:10 PM UTC 24 |
Sep 04 10:30:18 PM UTC 24 |
24027767928 ps |
| T270 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_plic_sw_irq.746948350 |
|
|
Sep 04 10:26:38 PM UTC 24 |
Sep 04 10:30:54 PM UTC 24 |
3083601944 ps |
| T326 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_sensor_ctrl_status.3907309425 |
|
|
Sep 04 10:26:34 PM UTC 24 |
Sep 04 10:31:33 PM UTC 24 |
3059252025 ps |
| T995 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_bad_prod.3848351824 |
|
|
Sep 04 08:35:21 PM UTC 24 |
Sep 04 10:32:02 PM UTC 24 |
23133822381 ps |
| T996 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_bad_prod_end.2274060912 |
|
|
Sep 04 08:36:07 PM UTC 24 |
Sep 04 10:32:38 PM UTC 24 |
23947593176 ps |
| T407 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_rom_ctrl_integrity_check.1216789756 |
|
|
Sep 04 10:23:54 PM UTC 24 |
Sep 04 10:33:04 PM UTC 24 |
8337709473 ps |
| T289 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_sram_ctrl_scrambled_access_jitter_en.748060244 |
|
|
Sep 04 10:24:36 PM UTC 24 |
Sep 04 10:33:23 PM UTC 24 |
3666269806 ps |
| T997 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_edn_entropy_reqs.619218118 |
|
|
Sep 04 10:17:22 PM UTC 24 |
Sep 04 10:33:32 PM UTC 24 |
6469725636 ps |
| T160 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup.3663241966 |
|
|
Sep 04 10:26:28 PM UTC 24 |
Sep 04 10:34:04 PM UTC 24 |
4987525800 ps |
| T998 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_alert_handler_ping_ok.3912888969 |
|
|
Sep 04 10:10:41 PM UTC 24 |
Sep 04 10:34:41 PM UTC 24 |
8060221448 ps |
| T999 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/0.rom_e2e_boot_policy_valid_a_bad_b_good_rma.4058611117 |
|
|
Sep 04 08:34:21 PM UTC 24 |
Sep 04 10:34:47 PM UTC 24 |
22811683640 ps |
| T1000 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_clkmgr_off_aes_trans.1176112090 |
|
|
Sep 04 10:27:47 PM UTC 24 |
Sep 04 10:34:56 PM UTC 24 |
4758695784 ps |
| T1001 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_keymgr_key_derivation_jitter_en.3224367449 |
|
|
Sep 04 10:19:58 PM UTC 24 |
Sep 04 10:35:18 PM UTC 24 |
6847376961 ps |
| T180 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_plic_all_irqs_10.1732673421 |
|
|
Sep 04 10:26:17 PM UTC 24 |
Sep 04 10:35:27 PM UTC 24 |
4273030272 ps |
| T1002 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_clkmgr_off_kmac_trans.131051456 |
|
|
Sep 04 10:28:56 PM UTC 24 |
Sep 04 10:35:28 PM UTC 24 |
4490187390 ps |
| T1003 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_bad_rma.2375938967 |
|
|
Sep 04 08:36:18 PM UTC 24 |
Sep 04 10:35:37 PM UTC 24 |
22164160986 ps |
| T290 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_sram_ctrl_scrambled_access.2120962081 |
|
|
Sep 04 10:23:58 PM UTC 24 |
Sep 04 10:36:06 PM UTC 24 |
5286938700 ps |
| T1004 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/0.rom_e2e_boot_policy_valid_a_bad_b_good_prod_end.1963376458 |
|
|
Sep 04 08:33:30 PM UTC 24 |
Sep 04 10:36:16 PM UTC 24 |
23680135440 ps |
| T1005 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_sleep_sram_ret_contents_scramble.1712808556 |
|
|
Sep 04 10:24:53 PM UTC 24 |
Sep 04 10:36:32 PM UTC 24 |
8658023800 ps |
| T1006 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_bad_dev.2623307274 |
|
|
Sep 04 08:36:17 PM UTC 24 |
Sep 04 10:36:35 PM UTC 24 |
23534856120 ps |
| T275 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_alert_handler_lpg_sleep_mode_pings.3858501802 |
|
|
Sep 04 10:11:23 PM UTC 24 |
Sep 04 10:36:36 PM UTC 24 |
13694669640 ps |
| T1007 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_edn_entropy_reqs_jitter.3548101059 |
|
|
Sep 04 10:17:22 PM UTC 24 |
Sep 04 10:36:59 PM UTC 24 |
8520195328 ps |
| T1008 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_clkmgr_off_hmac_trans.1527991618 |
|
|
Sep 04 10:28:32 PM UTC 24 |
Sep 04 10:37:54 PM UTC 24 |
5784656348 ps |
| T1009 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_clkmgr_external_clk_src_for_lc.1161852762 |
|
|
Sep 04 10:30:22 PM UTC 24 |
Sep 04 10:38:08 PM UTC 24 |
4857405326 ps |
| T1010 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_clkmgr_off_otbn_trans.3503226341 |
|
|
Sep 04 10:29:17 PM UTC 24 |
Sep 04 10:38:11 PM UTC 24 |
3956982824 ps |
| T1011 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_clkmgr_jitter.1671308945 |
|
|
Sep 04 10:34:21 PM UTC 24 |
Sep 04 10:38:26 PM UTC 24 |
2676493738 ps |
| T319 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_plic_all_irqs_20.1383459108 |
|
|
Sep 04 10:26:35 PM UTC 24 |
Sep 04 10:38:32 PM UTC 24 |
4654128600 ps |
| T1012 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_sleep_sram_ret_contents_no_scramble.3184862403 |
|
|
Sep 04 10:24:36 PM UTC 24 |
Sep 04 10:38:41 PM UTC 24 |
9432029250 ps |
| T1013 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_alert_handler_lpg_reset_toggle.1904032607 |
|
|
Sep 04 10:12:49 PM UTC 24 |
Sep 04 10:38:48 PM UTC 24 |
7863765032 ps |
| T1014 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_edn_auto_mode.1093767446 |
|
|
Sep 04 10:13:38 PM UTC 24 |
Sep 04 10:39:06 PM UTC 24 |
6074234104 ps |
| T164 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_sensor_ctrl_alert.915038103 |
|
|
Sep 04 10:26:29 PM UTC 24 |
Sep 04 10:39:18 PM UTC 24 |
7495573000 ps |
| T1015 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_keymgr_key_derivation.3455665831 |
|
|
Sep 04 10:19:11 PM UTC 24 |
Sep 04 10:40:12 PM UTC 24 |
6519242856 ps |
| T309 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_sram_ctrl_execution_main.3440957750 |
|
|
Sep 04 10:24:51 PM UTC 24 |
Sep 04 10:40:21 PM UTC 24 |
7940110945 ps |
| T1016 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_clkmgr_reset_frequency.2030934799 |
|
|
Sep 04 10:33:46 PM UTC 24 |
Sep 04 10:40:45 PM UTC 24 |
3959565240 ps |
| T1017 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0.823267121 |
|
|
Sep 04 10:31:02 PM UTC 24 |
Sep 04 10:40:48 PM UTC 24 |
4276803912 ps |
| T1018 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_clkmgr_external_clk_src_for_sw_fast_dev.2861536627 |
|
|
Sep 04 10:31:39 PM UTC 24 |
Sep 04 10:41:19 PM UTC 24 |
3900076912 ps |
| T1019 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_clkmgr_jitter_frequency.218009295 |
|
|
Sep 04 10:34:20 PM UTC 24 |
Sep 04 10:41:34 PM UTC 24 |
2925362400 ps |
| T1020 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_alert_handler_lpg_clkoff.3078613329 |
|
|
Sep 04 10:11:23 PM UTC 24 |
Sep 04 10:41:41 PM UTC 24 |
7795442472 ps |
| T1021 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0.1301261369 |
|
|
Sep 04 10:30:37 PM UTC 24 |
Sep 04 10:42:01 PM UTC 24 |
4197161134 ps |
| T1022 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_tap_straps_dev.4116863608 |
|
|
Sep 04 10:38:51 PM UTC 24 |
Sep 04 10:42:13 PM UTC 24 |
3034341674 ps |
| T347 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_pwrmgr_lowpower_cancel.2248532755 |
|
|
Sep 04 10:37:01 PM UTC 24 |
Sep 04 10:42:32 PM UTC 24 |
3672762170 ps |
| T1023 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_clkmgr_external_clk_src_for_sw_slow_dev.1291000174 |
|
|
Sep 04 10:32:18 PM UTC 24 |
Sep 04 10:42:58 PM UTC 24 |
5182237796 ps |
| T328 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_entropy_src_csrng.3307378959 |
|
|
Sep 04 10:15:33 PM UTC 24 |
Sep 04 10:44:05 PM UTC 24 |
7609893472 ps |
| T112 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_pwrmgr_normal_sleep_all_wake_ups.3672506122 |
|
|
Sep 04 10:36:33 PM UTC 24 |
Sep 04 10:44:06 PM UTC 24 |
7624713000 ps |
| T1024 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_clkmgr_external_clk_src_for_sw_slow_rma.4289520454 |
|
|
Sep 04 10:33:22 PM UTC 24 |
Sep 04 10:44:07 PM UTC 24 |
5293675050 ps |
| T395 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_rv_core_ibex_lockstep_glitch.463992406 |
|
|
Sep 04 10:39:34 PM UTC 24 |
Sep 04 10:44:08 PM UTC 24 |
2916473368 ps |
| T1025 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_pwrmgr_sleep_wake_5_bug.1750569229 |
|
|
Sep 04 10:37:34 PM UTC 24 |
Sep 04 10:44:13 PM UTC 24 |
6508639140 ps |
| T1026 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_clkmgr_external_clk_src_for_sw_fast_rma.708488239 |
|
|
Sep 04 10:32:47 PM UTC 24 |
Sep 04 10:44:23 PM UTC 24 |
4403400596 ps |
| T206 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_rv_core_ibex_address_translation.1250244431 |
|
|
Sep 04 10:39:34 PM UTC 24 |
Sep 04 10:44:29 PM UTC 24 |
3634917356 ps |
| T115 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_rv_dm_ndm_reset_req.1293937475 |
|
|
Sep 04 10:37:55 PM UTC 24 |
Sep 04 10:44:34 PM UTC 24 |
3542091744 ps |
| T321 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_plic_all_irqs_0.4190767595 |
|
|
Sep 04 10:26:38 PM UTC 24 |
Sep 04 10:44:45 PM UTC 24 |
6044237050 ps |
| T651 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_clkmgr_jitter_reduced_freq.1226818063 |
|
|
Sep 04 10:41:09 PM UTC 24 |
Sep 04 10:44:55 PM UTC 24 |
2569132109 ps |
| T652 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_clkmgr_sleep_frequency.2451541703 |
|
|
Sep 04 10:34:50 PM UTC 24 |
Sep 04 10:44:58 PM UTC 24 |
4731581630 ps |
| T304 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_rv_core_ibex_icache_invalidate.2506537195 |
|
|
Sep 04 10:40:03 PM UTC 24 |
Sep 04 10:45:20 PM UTC 24 |
3278925062 ps |
| T195 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_lc_ctrl_program_error.463379030 |
|
|
Sep 04 10:36:32 PM UTC 24 |
Sep 04 10:45:38 PM UTC 24 |
4790223368 ps |
| T653 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_rv_dm_access_after_wakeup.1371261551 |
|
|
Sep 04 10:37:59 PM UTC 24 |
Sep 04 10:45:48 PM UTC 24 |
5504866380 ps |
| T625 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_rv_dm_access_after_escalation_reset.234319255 |
|
|
Sep 04 10:38:49 PM UTC 24 |
Sep 04 10:46:25 PM UTC 24 |
5482821360 ps |
| T654 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_hmac_multistream.2241812002 |
|
|
Sep 04 10:19:10 PM UTC 24 |
Sep 04 10:46:33 PM UTC 24 |
8368215192 ps |
| T655 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_edn_sw_mode.3931087767 |
|
|
Sep 04 10:13:57 PM UTC 24 |
Sep 04 10:46:51 PM UTC 24 |
9877244802 ps |
| T1027 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_flash_ctrl_write_clear.3310538182 |
|
|
Sep 04 10:41:08 PM UTC 24 |
Sep 04 10:46:57 PM UTC 24 |
2980718744 ps |
| T1028 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_hmac_enc_jitter_en_reduced_freq.4255273132 |
|
|
Sep 04 10:42:29 PM UTC 24 |
Sep 04 10:46:58 PM UTC 24 |
3194945918 ps |
| T373 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up.1302632641 |
|
|
Sep 04 10:37:52 PM UTC 24 |
Sep 04 10:47:00 PM UTC 24 |
5028217864 ps |
| T365 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_rv_dm_ndm_reset_req_when_cpu_halted.1578741757 |
|
|
Sep 04 10:37:55 PM UTC 24 |
Sep 04 10:47:14 PM UTC 24 |
4038999176 ps |
| T83 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_tap_straps_testunlock0.69266486 |
|
|
Sep 04 10:38:51 PM UTC 24 |
Sep 04 10:47:18 PM UTC 24 |
6612066252 ps |
| T1029 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_aes_enc_jitter_en_reduced_freq.3177826388 |
|
|
Sep 04 10:42:26 PM UTC 24 |
Sep 04 10:47:21 PM UTC 24 |
3260323563 ps |
| T84 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_tap_straps_rma.1839046679 |
|
|
Sep 04 10:39:09 PM UTC 24 |
Sep 04 10:47:31 PM UTC 24 |
5460881715 ps |
| T1030 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_kmac_mode_kmac_jitter_en_reduced_freq.1198420473 |
|
|
Sep 04 10:43:00 PM UTC 24 |
Sep 04 10:47:42 PM UTC 24 |
3238608535 ps |
| T1031 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_csrng_edn_concurrency.3305197491 |
|
|
Sep 04 10:14:39 PM UTC 24 |
Sep 04 10:47:56 PM UTC 24 |
8919148400 ps |
| T1032 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_clkmgr_off_peri.758256039 |
|
|
Sep 04 10:27:22 PM UTC 24 |
Sep 04 10:48:13 PM UTC 24 |
9820607508 ps |
| T1033 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_flash_crash_alert.3834446503 |
|
|
Sep 04 10:40:07 PM UTC 24 |
Sep 04 10:48:46 PM UTC 24 |
4950665338 ps |
| T1034 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_ast_clk_outputs.1597265446 |
|
|
Sep 04 10:35:39 PM UTC 24 |
Sep 04 10:48:50 PM UTC 24 |
6594750536 ps |
| T1035 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_keymgr_sideload_kmac.764026080 |
|
|
Sep 04 10:20:16 PM UTC 24 |
Sep 04 10:49:48 PM UTC 24 |
10154138486 ps |
| T1036 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_flash_ctrl_ops_jitter_en_reduced_freq.2605774254 |
|
|
Sep 04 10:41:42 PM UTC 24 |
Sep 04 10:50:39 PM UTC 24 |
5260403654 ps |
| T1037 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_tap_straps_prod.1502382919 |
|
|
Sep 04 10:39:09 PM UTC 24 |
Sep 04 10:50:51 PM UTC 24 |
9128922462 ps |
| T291 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq.3483827335 |
|
|
Sep 04 10:43:17 PM UTC 24 |
Sep 04 10:50:52 PM UTC 24 |
4662145448 ps |
| T1038 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_sysrst_ctrl_ec_rst_l.1291252143 |
|
|
Sep 04 10:01:38 PM UTC 24 |
Sep 04 10:51:45 PM UTC 24 |
20555131891 ps |
| T96 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_jtag_csr_rw.3492371954 |
|
|
Sep 04 10:35:12 PM UTC 24 |
Sep 04 10:52:59 PM UTC 24 |
11020092618 ps |
| T1039 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_flash_scrambling_smoketest.2030520604 |
|
|
Sep 04 10:49:04 PM UTC 24 |
Sep 04 10:53:13 PM UTC 24 |
2591852248 ps |
| T1040 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/1.rom_volatile_raw_unlock.446182398 |
|
|
Sep 04 10:50:48 PM UTC 24 |
Sep 04 10:53:18 PM UTC 24 |
2685220138 ps |
| T1041 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_gpio_smoketest.274525014 |
|
|
Sep 04 10:50:40 PM UTC 24 |
Sep 04 10:53:31 PM UTC 24 |
3059678972 ps |
| T1042 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_aes_smoketest.1718322622 |
|
|
Sep 04 10:49:42 PM UTC 24 |
Sep 04 10:53:51 PM UTC 24 |
2987419720 ps |
| T1043 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_csrng_smoketest.3525156990 |
|
|
Sep 04 10:50:03 PM UTC 24 |
Sep 04 10:54:12 PM UTC 24 |
2882174280 ps |
| T241 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_keymgr_sideload_aes.3182121314 |
|
|
Sep 04 10:21:53 PM UTC 24 |
Sep 04 10:54:38 PM UTC 24 |
10323423228 ps |
| T1044 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_clkmgr_smoketest.1734625719 |
|
|
Sep 04 10:50:01 PM UTC 24 |
Sep 04 10:54:38 PM UTC 24 |
2416510362 ps |
| T177 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/1.rom_raw_unlock.3492706964 |
|
|
Sep 04 10:50:26 PM UTC 24 |
Sep 04 10:55:16 PM UTC 24 |
6137200017 ps |
| T1045 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_power_sleep_load.1725805784 |
|
|
Sep 04 10:46:18 PM UTC 24 |
Sep 04 10:55:36 PM UTC 24 |
10500442584 ps |
| T1046 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_aon_timer_smoketest.682305884 |
|
|
Sep 04 10:50:10 PM UTC 24 |
Sep 04 10:56:00 PM UTC 24 |
3312212562 ps |
| T1047 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_kmac_smoketest.1883212137 |
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|
Sep 04 10:51:21 PM UTC 24 |
Sep 04 10:57:08 PM UTC 24 |
2555658008 ps |
| T1048 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_otp_ctrl_smoketest.4283286993 |
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|
Sep 04 10:51:46 PM UTC 24 |
Sep 04 10:57:08 PM UTC 24 |
3077843720 ps |
| T1049 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_hmac_smoketest.3880334632 |
|
|
Sep 04 10:50:46 PM UTC 24 |
Sep 04 10:57:19 PM UTC 24 |
3128032880 ps |
| T220 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_jtag_mem_access.1898297815 |
|
|
Sep 04 10:35:17 PM UTC 24 |
Sep 04 10:57:26 PM UTC 24 |
13697553681 ps |
| T1050 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_rstmgr_smoketest.3335618448 |
|
|
Sep 04 10:54:32 PM UTC 24 |
Sep 04 10:57:57 PM UTC 24 |
2904414656 ps |
| T1051 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_entropy_src_smoketest.2544282072 |
|
|
Sep 04 10:50:40 PM UTC 24 |
Sep 04 10:58:03 PM UTC 24 |
3093737768 ps |
| T403 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_pwrmgr_deep_sleep_all_wake_ups.676497041 |
|
|
Sep 04 10:36:38 PM UTC 24 |
Sep 04 10:58:20 PM UTC 24 |
24116426710 ps |
| T1052 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_pwrmgr_random_sleep_power_glitch_reset.368574867 |
|
|
Sep 04 09:57:15 PM UTC 24 |
Sep 04 10:58:27 PM UTC 24 |
35659531650 ps |
| T117 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_pwrmgr_random_sleep_all_wake_ups.1202465091 |
|
|
Sep 04 10:37:48 PM UTC 24 |
Sep 04 10:58:28 PM UTC 24 |
21845330962 ps |
| T1053 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_example_rom.3753409786 |
|
|
Sep 04 10:55:19 PM UTC 24 |
Sep 04 10:58:31 PM UTC 24 |
2737798890 ps |
| T1054 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_flash_ctrl_access_jitter_en_reduced_freq.2917532181 |
|
|
Sep 04 10:41:42 PM UTC 24 |
Sep 04 10:58:37 PM UTC 24 |
8200675459 ps |
| T1055 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_rv_plic_smoketest.3099172875 |
|
|
Sep 04 10:54:21 PM UTC 24 |
Sep 04 10:58:41 PM UTC 24 |
2451496232 ps |
| T1056 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_sram_ctrl_smoketest.1823498283 |
|
|
Sep 04 10:54:37 PM UTC 24 |
Sep 04 10:58:46 PM UTC 24 |
3312251908 ps |
| T1057 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_rv_timer_smoketest.2084183089 |
|
|
Sep 04 10:54:19 PM UTC 24 |
Sep 04 10:58:56 PM UTC 24 |
2930383192 ps |
| T1058 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_pwrmgr_smoketest.2228320657 |
|
|
Sep 04 10:52:30 PM UTC 24 |
Sep 04 10:59:26 PM UTC 24 |
5755500496 ps |
| T1059 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_uart_smoketest.3381566904 |
|
|
Sep 04 10:54:53 PM UTC 24 |
Sep 04 10:59:34 PM UTC 24 |
3495486350 ps |
| T1060 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_example_flash.653042550 |
|
|
Sep 04 10:55:22 PM UTC 24 |
Sep 04 11:00:13 PM UTC 24 |
2881206308 ps |
| T1061 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_example_manufacturer.1369056027 |
|
|
Sep 04 10:56:00 PM UTC 24 |
Sep 04 11:00:27 PM UTC 24 |
3016941554 ps |
| T1062 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_example_concurrency.3513630379 |
|
|
Sep 04 10:56:21 PM UTC 24 |
Sep 04 11:00:38 PM UTC 24 |
2756891952 ps |
| T1063 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_pwrmgr_b2b_sleep_reset_req.3649387307 |
|
|
Sep 04 10:26:27 PM UTC 24 |
Sep 04 11:01:02 PM UTC 24 |
26263432820 ps |
| T1064 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sival_flash_info_access.3425514270 |
|
|
Sep 04 10:56:44 PM UTC 24 |
Sep 04 11:01:18 PM UTC 24 |
2341656644 ps |
| T1065 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/1.rom_keymgr_functest.1695447447 |
|
|
Sep 04 10:51:03 PM UTC 24 |
Sep 04 11:01:22 PM UTC 24 |
4744543570 ps |
| T1066 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_pwrmgr_usbdev_smoketest.3888430836 |
|
|
Sep 04 10:53:44 PM UTC 24 |
Sep 04 11:01:53 PM UTC 24 |
5148442196 ps |
| T1067 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_power_idle_load.1631323897 |
|
|
Sep 04 10:50:28 PM UTC 24 |
Sep 04 11:02:04 PM UTC 24 |
3870029944 ps |