| T1587 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/23.xbar_unmapped_addr.431965163 |
|
|
Sep 04 05:54:46 PM UTC 24 |
Sep 04 05:55:40 PM UTC 24 |
1289676791 ps |
| T1588 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/21.xbar_stress_all_with_error.1141082446 |
|
|
Sep 04 05:50:30 PM UTC 24 |
Sep 04 05:55:41 PM UTC 24 |
3505777966 ps |
| T1589 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/24.xbar_random_zero_delays.26228358 |
|
|
Sep 04 05:55:33 PM UTC 24 |
Sep 04 05:55:43 PM UTC 24 |
33462495 ps |
| T1590 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/19.chip_csr_mem_rw_with_rand_reset.1789776221 |
|
|
Sep 04 05:46:51 PM UTC 24 |
Sep 04 05:55:47 PM UTC 24 |
5585030324 ps |
| T1591 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/23.xbar_error_random.2107829531 |
|
|
Sep 04 05:54:47 PM UTC 24 |
Sep 04 05:55:52 PM UTC 24 |
2080969831 ps |
| T1592 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/19.chip_csr_rw.2397987211 |
|
|
Sep 04 05:46:35 PM UTC 24 |
Sep 04 05:55:53 PM UTC 24 |
6118778855 ps |
| T1593 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/24.xbar_access_same_device.4696366 |
|
|
Sep 04 05:55:57 PM UTC 24 |
Sep 04 05:56:13 PM UTC 24 |
112639785 ps |
| T1594 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/24.xbar_random.3772949325 |
|
|
Sep 04 05:55:29 PM UTC 24 |
Sep 04 05:56:25 PM UTC 24 |
1434170079 ps |
| T1595 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/23.xbar_random_large_delays.689691355 |
|
|
Sep 04 05:53:58 PM UTC 24 |
Sep 04 05:56:27 PM UTC 24 |
12479169819 ps |
| T1596 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/17.xbar_random_slow_rsp.2948040014 |
|
|
Sep 04 05:41:16 PM UTC 24 |
Sep 04 05:56:28 PM UTC 24 |
56747278289 ps |
| T859 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/22.xbar_stress_all_with_reset_error.980561530 |
|
|
Sep 04 05:53:10 PM UTC 24 |
Sep 04 05:56:37 PM UTC 24 |
562301042 ps |
| T1597 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/24.xbar_unmapped_addr.2778657223 |
|
|
Sep 04 05:56:11 PM UTC 24 |
Sep 04 05:56:38 PM UTC 24 |
153693324 ps |
| T1598 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/24.xbar_smoke_large_delays.2966534100 |
|
|
Sep 04 05:55:21 PM UTC 24 |
Sep 04 05:56:43 PM UTC 24 |
7322619094 ps |
| T1599 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/24.xbar_error_and_unmapped_addr.3971968349 |
|
|
Sep 04 05:56:12 PM UTC 24 |
Sep 04 05:56:50 PM UTC 24 |
266294965 ps |
| T1600 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/24.xbar_same_source.1216277417 |
|
|
Sep 04 05:56:01 PM UTC 24 |
Sep 04 05:56:52 PM UTC 24 |
1537838321 ps |
| T1601 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/24.xbar_error_random.2689213033 |
|
|
Sep 04 05:56:04 PM UTC 24 |
Sep 04 05:57:00 PM UTC 24 |
625624106 ps |
| T1602 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/23.xbar_stress_all_with_error.578023805 |
|
|
Sep 04 05:55:01 PM UTC 24 |
Sep 04 05:57:04 PM UTC 24 |
1450555691 ps |
| T1603 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/25.xbar_smoke.2031272382 |
|
|
Sep 04 05:56:54 PM UTC 24 |
Sep 04 05:57:04 PM UTC 24 |
49983611 ps |
| T619 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/23.chip_tl_errors.301951560 |
|
|
Sep 04 05:53:10 PM UTC 24 |
Sep 04 05:57:04 PM UTC 24 |
3302027492 ps |
| T1604 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/24.xbar_stress_all_with_reset_error.1409454460 |
|
|
Sep 04 05:56:23 PM UTC 24 |
Sep 04 05:57:04 PM UTC 24 |
118281027 ps |
| T1605 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/25.xbar_smoke_zero_delays.1896078316 |
|
|
Sep 04 05:56:59 PM UTC 24 |
Sep 04 05:57:08 PM UTC 24 |
40093889 ps |
| T1606 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/24.xbar_smoke_slow_rsp.1880801650 |
|
|
Sep 04 05:55:19 PM UTC 24 |
Sep 04 05:57:20 PM UTC 24 |
6545621816 ps |
| T1607 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/24.xbar_stress_all_with_error.2239895176 |
|
|
Sep 04 05:56:23 PM UTC 24 |
Sep 04 05:57:24 PM UTC 24 |
668908310 ps |
| T837 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/12.xbar_access_same_device_slow_rsp.2731013518 |
|
|
Sep 04 05:28:56 PM UTC 24 |
Sep 04 05:57:25 PM UTC 24 |
114168711924 ps |
| T1608 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/25.xbar_random_zero_delays.3694538502 |
|
|
Sep 04 05:57:14 PM UTC 24 |
Sep 04 05:57:32 PM UTC 24 |
120642202 ps |
| T850 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/22.xbar_access_same_device_slow_rsp.2224888324 |
|
|
Sep 04 05:51:39 PM UTC 24 |
Sep 04 05:57:49 PM UTC 24 |
22123382541 ps |
| T1609 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/25.xbar_error_and_unmapped_addr.1423700042 |
|
|
Sep 04 05:57:33 PM UTC 24 |
Sep 04 05:57:50 PM UTC 24 |
191726762 ps |
| T466 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/25.xbar_random.1569781917 |
|
|
Sep 04 05:57:08 PM UTC 24 |
Sep 04 05:57:51 PM UTC 24 |
381248112 ps |
| T1610 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/25.xbar_unmapped_addr.710824299 |
|
|
Sep 04 05:57:34 PM UTC 24 |
Sep 04 05:57:53 PM UTC 24 |
83661550 ps |
| T1611 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/20.xbar_random_slow_rsp.4063174091 |
|
|
Sep 04 05:47:38 PM UTC 24 |
Sep 04 05:57:56 PM UTC 24 |
30855914814 ps |
| T494 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/20.xbar_access_same_device_slow_rsp.4253134135 |
|
|
Sep 04 05:47:44 PM UTC 24 |
Sep 04 05:58:06 PM UTC 24 |
42136958649 ps |
| T1612 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/25.xbar_smoke_large_delays.595271132 |
|
|
Sep 04 05:57:00 PM UTC 24 |
Sep 04 05:58:06 PM UTC 24 |
6159717309 ps |
| T500 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/23.xbar_stress_all.178616722 |
|
|
Sep 04 05:54:56 PM UTC 24 |
Sep 04 05:58:11 PM UTC 24 |
5613106273 ps |
| T1613 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/25.xbar_smoke_slow_rsp.3914093100 |
|
|
Sep 04 05:57:08 PM UTC 24 |
Sep 04 05:58:18 PM UTC 24 |
4307841918 ps |
| T1614 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/26.xbar_smoke.1039832533 |
|
|
Sep 04 05:58:19 PM UTC 24 |
Sep 04 05:58:26 PM UTC 24 |
36275847 ps |
| T1615 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/18.xbar_random_slow_rsp.3324176732 |
|
|
Sep 04 05:43:21 PM UTC 24 |
Sep 04 05:58:26 PM UTC 24 |
61863495340 ps |
| T1616 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/26.xbar_smoke_zero_delays.3019745297 |
|
|
Sep 04 05:58:22 PM UTC 24 |
Sep 04 05:58:32 PM UTC 24 |
53305261 ps |
| T1617 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/25.xbar_same_source.451703130 |
|
|
Sep 04 05:57:31 PM UTC 24 |
Sep 04 05:58:32 PM UTC 24 |
1573635835 ps |
| T1618 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/17.chip_csr_mem_rw_with_rand_reset.780020228 |
|
|
Sep 04 05:42:40 PM UTC 24 |
Sep 04 05:58:51 PM UTC 24 |
11587815120 ps |
| T1619 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/26.xbar_random.52929521 |
|
|
Sep 04 05:58:36 PM UTC 24 |
Sep 04 05:59:07 PM UTC 24 |
227376903 ps |
| T1620 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/25.xbar_error_random.2869307342 |
|
|
Sep 04 05:57:36 PM UTC 24 |
Sep 04 05:59:10 PM UTC 24 |
1884966199 ps |
| T1621 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/26.xbar_random_zero_delays.28555747 |
|
|
Sep 04 05:58:37 PM UTC 24 |
Sep 04 05:59:13 PM UTC 24 |
341603954 ps |
| T1622 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/25.xbar_stress_all.1424302098 |
|
|
Sep 04 05:57:49 PM UTC 24 |
Sep 04 05:59:16 PM UTC 24 |
2390798892 ps |
| T1623 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/25.xbar_access_same_device.703235225 |
|
|
Sep 04 05:57:28 PM UTC 24 |
Sep 04 05:59:25 PM UTC 24 |
2308449506 ps |
| T1624 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/26.xbar_error_random.2260033319 |
|
|
Sep 04 05:59:04 PM UTC 24 |
Sep 04 05:59:26 PM UTC 24 |
372225950 ps |
| T1625 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/23.xbar_stress_all_with_rand_reset.481483777 |
|
|
Sep 04 05:54:56 PM UTC 24 |
Sep 04 05:59:28 PM UTC 24 |
415433181 ps |
| T1626 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/26.xbar_unmapped_addr.4075466759 |
|
|
Sep 04 05:59:21 PM UTC 24 |
Sep 04 05:59:33 PM UTC 24 |
36641591 ps |
| T517 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/26.xbar_smoke_slow_rsp.4259376122 |
|
|
Sep 04 05:58:26 PM UTC 24 |
Sep 04 05:59:41 PM UTC 24 |
5511710245 ps |
| T1627 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/22.xbar_stress_all.3421573941 |
|
|
Sep 04 05:52:35 PM UTC 24 |
Sep 04 05:59:47 PM UTC 24 |
4872052479 ps |
| T845 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/26.xbar_access_same_device.231232524 |
|
|
Sep 04 05:58:56 PM UTC 24 |
Sep 04 05:59:50 PM UTC 24 |
457964372 ps |
| T1628 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/24.xbar_random_slow_rsp.1535745921 |
|
|
Sep 04 05:55:34 PM UTC 24 |
Sep 04 05:59:55 PM UTC 24 |
18133632860 ps |
| T1629 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/27.xbar_smoke_zero_delays.3125801545 |
|
|
Sep 04 05:59:57 PM UTC 24 |
Sep 04 06:00:05 PM UTC 24 |
44247578 ps |
| T507 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/24.xbar_stress_all_with_rand_reset.2491732371 |
|
|
Sep 04 05:56:18 PM UTC 24 |
Sep 04 06:00:09 PM UTC 24 |
565713366 ps |
| T1630 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/27.xbar_smoke.852433920 |
|
|
Sep 04 05:59:59 PM UTC 24 |
Sep 04 06:00:09 PM UTC 24 |
47823504 ps |
| T1631 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/26.xbar_error_and_unmapped_addr.924111011 |
|
|
Sep 04 05:59:38 PM UTC 24 |
Sep 04 06:00:09 PM UTC 24 |
483692812 ps |
| T886 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/26.xbar_stress_all_with_rand_reset.2714225261 |
|
|
Sep 04 05:59:45 PM UTC 24 |
Sep 04 06:00:14 PM UTC 24 |
80856948 ps |
| T511 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/26.xbar_same_source.4271058272 |
|
|
Sep 04 05:59:02 PM UTC 24 |
Sep 04 06:00:22 PM UTC 24 |
2492247853 ps |
| T1632 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/26.xbar_smoke_large_delays.1234708195 |
|
|
Sep 04 05:58:25 PM UTC 24 |
Sep 04 06:00:24 PM UTC 24 |
10015747982 ps |
| T645 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/24.chip_tl_errors.2995351880 |
|
|
Sep 04 05:55:03 PM UTC 24 |
Sep 04 06:00:30 PM UTC 24 |
3186319714 ps |
| T806 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/10.xbar_access_same_device_slow_rsp.3347176087 |
|
|
Sep 04 05:24:01 PM UTC 24 |
Sep 04 06:00:31 PM UTC 24 |
146240570495 ps |
| T1633 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/13.chip_same_csr_outstanding.520342460 |
|
|
Sep 04 05:30:17 PM UTC 24 |
Sep 04 06:00:38 PM UTC 24 |
16323305668 ps |
| T1634 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/27.xbar_unmapped_addr.2846111039 |
|
|
Sep 04 06:00:53 PM UTC 24 |
Sep 04 06:01:02 PM UTC 24 |
17789793 ps |
| T1635 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/27.xbar_random.1682767206 |
|
|
Sep 04 06:00:21 PM UTC 24 |
Sep 04 06:01:02 PM UTC 24 |
858011415 ps |
| T1636 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/27.xbar_random_zero_delays.529856373 |
|
|
Sep 04 06:00:26 PM UTC 24 |
Sep 04 06:01:09 PM UTC 24 |
447741067 ps |
| T1637 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/27.xbar_same_source.963600972 |
|
|
Sep 04 06:00:44 PM UTC 24 |
Sep 04 06:01:10 PM UTC 24 |
250421834 ps |
| T1638 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/27.xbar_error_random.1553903808 |
|
|
Sep 04 06:00:51 PM UTC 24 |
Sep 04 06:01:15 PM UTC 24 |
222779398 ps |
| T1639 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/25.xbar_stress_all_with_error.2906583088 |
|
|
Sep 04 05:57:55 PM UTC 24 |
Sep 04 06:01:21 PM UTC 24 |
6033819267 ps |
| T1640 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/25.xbar_random_large_delays.1744226608 |
|
|
Sep 04 05:57:19 PM UTC 24 |
Sep 04 06:01:28 PM UTC 24 |
22786210905 ps |
| T644 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/25.chip_tl_errors.18484410 |
|
|
Sep 04 05:56:43 PM UTC 24 |
Sep 04 06:01:33 PM UTC 24 |
3558568154 ps |
| T1641 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/27.xbar_smoke_slow_rsp.2712810588 |
|
|
Sep 04 06:00:16 PM UTC 24 |
Sep 04 06:01:48 PM UTC 24 |
5031615608 ps |
| T1642 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/28.xbar_smoke.3601151828 |
|
|
Sep 04 06:01:40 PM UTC 24 |
Sep 04 06:01:51 PM UTC 24 |
143223549 ps |
| T1643 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/27.xbar_access_same_device.1852613249 |
|
|
Sep 04 06:00:38 PM UTC 24 |
Sep 04 06:01:52 PM UTC 24 |
502214911 ps |
| T1644 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/28.xbar_smoke_zero_delays.1666595306 |
|
|
Sep 04 06:01:44 PM UTC 24 |
Sep 04 06:01:54 PM UTC 24 |
43775748 ps |
| T1645 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/21.xbar_random_slow_rsp.2041401748 |
|
|
Sep 04 05:49:32 PM UTC 24 |
Sep 04 06:02:03 PM UTC 24 |
52581906736 ps |
| T1646 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/27.xbar_error_and_unmapped_addr.176189845 |
|
|
Sep 04 06:01:00 PM UTC 24 |
Sep 04 06:02:09 PM UTC 24 |
1256876461 ps |
| T529 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/24.xbar_stress_all.4156096976 |
|
|
Sep 04 05:56:15 PM UTC 24 |
Sep 04 06:02:16 PM UTC 24 |
7629534077 ps |
| T1647 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/18.chip_csr_mem_rw_with_rand_reset.998743571 |
|
|
Sep 04 05:44:21 PM UTC 24 |
Sep 04 06:02:27 PM UTC 24 |
10151470635 ps |
| T1648 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/25.xbar_stress_all_with_reset_error.3229795939 |
|
|
Sep 04 05:58:01 PM UTC 24 |
Sep 04 06:02:33 PM UTC 24 |
681157860 ps |
| T1649 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/27.xbar_smoke_large_delays.1683430041 |
|
|
Sep 04 06:00:12 PM UTC 24 |
Sep 04 06:02:36 PM UTC 24 |
10684332305 ps |
| T1650 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/22.xbar_random_slow_rsp.3915429565 |
|
|
Sep 04 05:51:32 PM UTC 24 |
Sep 04 06:02:38 PM UTC 24 |
36407762051 ps |
| T1651 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/28.xbar_random_zero_delays.2922124929 |
|
|
Sep 04 06:02:16 PM UTC 24 |
Sep 04 06:02:42 PM UTC 24 |
249688314 ps |
| T818 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/26.xbar_access_same_device_slow_rsp.3553280555 |
|
|
Sep 04 05:58:56 PM UTC 24 |
Sep 04 06:02:48 PM UTC 24 |
13660038211 ps |
| T1652 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/26.xbar_stress_all.1564590310 |
|
|
Sep 04 05:59:41 PM UTC 24 |
Sep 04 06:02:53 PM UTC 24 |
1899358719 ps |
| T1653 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/28.xbar_error_random.2550828395 |
|
|
Sep 04 06:02:40 PM UTC 24 |
Sep 04 06:03:05 PM UTC 24 |
509012127 ps |
| T1654 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/28.xbar_same_source.898577046 |
|
|
Sep 04 06:02:31 PM UTC 24 |
Sep 04 06:03:08 PM UTC 24 |
381676212 ps |
| T1655 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/28.xbar_unmapped_addr.793695403 |
|
|
Sep 04 06:02:43 PM UTC 24 |
Sep 04 06:03:16 PM UTC 24 |
235454041 ps |
| T1656 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/28.xbar_error_and_unmapped_addr.3132420730 |
|
|
Sep 04 06:02:57 PM UTC 24 |
Sep 04 06:03:20 PM UTC 24 |
383080114 ps |
| T1657 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/28.xbar_smoke_large_delays.1748178885 |
|
|
Sep 04 06:01:51 PM UTC 24 |
Sep 04 06:03:20 PM UTC 24 |
7358662325 ps |
| T868 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/26.xbar_stress_all_with_reset_error.3315879591 |
|
|
Sep 04 05:59:54 PM UTC 24 |
Sep 04 06:03:21 PM UTC 24 |
645195116 ps |
| T1658 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/0.chip_same_csr_outstanding.1081628666 |
|
|
Sep 04 05:00:55 PM UTC 24 |
Sep 04 06:03:26 PM UTC 24 |
29445491958 ps |
| T1659 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/28.xbar_smoke_slow_rsp.1482498071 |
|
|
Sep 04 06:02:00 PM UTC 24 |
Sep 04 06:03:28 PM UTC 24 |
4442973865 ps |
| T1660 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/29.xbar_smoke.2416172239 |
|
|
Sep 04 06:03:22 PM UTC 24 |
Sep 04 06:03:33 PM UTC 24 |
106649653 ps |
| T1661 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/17.chip_same_csr_outstanding.3829836665 |
|
|
Sep 04 05:40:11 PM UTC 24 |
Sep 04 06:03:44 PM UTC 24 |
16324346077 ps |
| T1662 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/28.xbar_stress_all.1548343358 |
|
|
Sep 04 06:03:01 PM UTC 24 |
Sep 04 06:08:47 PM UTC 24 |
9042169350 ps |
| T1663 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/29.xbar_smoke_zero_delays.2450192582 |
|
|
Sep 04 06:03:36 PM UTC 24 |
Sep 04 06:03:45 PM UTC 24 |
47518001 ps |
| T1664 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/28.xbar_random.3794588786 |
|
|
Sep 04 06:02:04 PM UTC 24 |
Sep 04 06:03:54 PM UTC 24 |
2175837510 ps |
| T1665 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/16.chip_same_csr_outstanding.2513282844 |
|
|
Sep 04 05:37:49 PM UTC 24 |
Sep 04 06:04:18 PM UTC 24 |
14416520371 ps |
| T1666 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/27.xbar_stress_all_with_reset_error.2055586750 |
|
|
Sep 04 06:01:34 PM UTC 24 |
Sep 04 06:04:19 PM UTC 24 |
616239836 ps |
| T1667 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/29.xbar_random.31506296 |
|
|
Sep 04 06:03:49 PM UTC 24 |
Sep 04 06:04:20 PM UTC 24 |
500997259 ps |
| T477 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/29.xbar_random_zero_delays.207504163 |
|
|
Sep 04 06:03:53 PM UTC 24 |
Sep 04 06:04:25 PM UTC 24 |
211299501 ps |
| T882 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/28.xbar_stress_all_with_reset_error.3472219171 |
|
|
Sep 04 06:03:14 PM UTC 24 |
Sep 04 06:04:32 PM UTC 24 |
298580294 ps |
| T852 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/29.xbar_access_same_device.2143040869 |
|
|
Sep 04 06:03:56 PM UTC 24 |
Sep 04 06:04:40 PM UTC 24 |
856985156 ps |
| T1668 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/29.xbar_same_source.1377253236 |
|
|
Sep 04 06:04:15 PM UTC 24 |
Sep 04 06:04:52 PM UTC 24 |
373596631 ps |
| T1669 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/22.xbar_random_large_delays.2882562506 |
|
|
Sep 04 05:51:30 PM UTC 24 |
Sep 04 06:04:52 PM UTC 24 |
87123523806 ps |
| T1670 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/27.xbar_stress_all_with_rand_reset.3992389220 |
|
|
Sep 04 06:01:07 PM UTC 24 |
Sep 04 06:04:53 PM UTC 24 |
581001178 ps |
| T1671 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/29.xbar_error_random.1267640580 |
|
|
Sep 04 06:04:16 PM UTC 24 |
Sep 04 06:05:00 PM UTC 24 |
336542268 ps |
| T621 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/26.chip_tl_errors.1439965248 |
|
|
Sep 04 05:58:19 PM UTC 24 |
Sep 04 06:05:03 PM UTC 24 |
5036702839 ps |
| T1672 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/29.xbar_error_and_unmapped_addr.1634339576 |
|
|
Sep 04 06:04:50 PM UTC 24 |
Sep 04 06:05:09 PM UTC 24 |
142029307 ps |
| T804 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/28.xbar_access_same_device.3203894670 |
|
|
Sep 04 06:02:23 PM UTC 24 |
Sep 04 06:05:10 PM UTC 24 |
3398931053 ps |
| T1673 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/21.xbar_random_large_delays.1235529349 |
|
|
Sep 04 05:49:20 PM UTC 24 |
Sep 04 06:05:14 PM UTC 24 |
92784561638 ps |
| T1674 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/29.xbar_smoke_slow_rsp.110881730 |
|
|
Sep 04 06:03:40 PM UTC 24 |
Sep 04 06:05:14 PM UTC 24 |
5587273835 ps |
| T1675 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/30.xbar_smoke.1708087839 |
|
|
Sep 04 06:05:11 PM UTC 24 |
Sep 04 06:05:22 PM UTC 24 |
51717770 ps |
| T1676 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/29.xbar_unmapped_addr.790011511 |
|
|
Sep 04 06:04:25 PM UTC 24 |
Sep 04 06:05:25 PM UTC 24 |
1080297313 ps |
| T1677 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/30.xbar_smoke_zero_delays.2538092995 |
|
|
Sep 04 06:05:21 PM UTC 24 |
Sep 04 06:05:32 PM UTC 24 |
43844828 ps |
| T1678 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/29.xbar_smoke_large_delays.3017995805 |
|
|
Sep 04 06:03:39 PM UTC 24 |
Sep 04 06:05:34 PM UTC 24 |
8835294662 ps |
| T1679 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/28.chip_tl_errors.1924096521 |
|
|
Sep 04 06:01:40 PM UTC 24 |
Sep 04 06:05:42 PM UTC 24 |
3073717625 ps |
| T1680 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/26.xbar_stress_all_with_error.645633560 |
|
|
Sep 04 05:59:47 PM UTC 24 |
Sep 04 06:05:58 PM UTC 24 |
9290476359 ps |
| T1681 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/28.xbar_stress_all_with_rand_reset.2485673166 |
|
|
Sep 04 06:03:08 PM UTC 24 |
Sep 04 06:06:05 PM UTC 24 |
401626601 ps |
| T1682 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/30.xbar_random_zero_delays.4064320122 |
|
|
Sep 04 06:05:34 PM UTC 24 |
Sep 04 06:06:23 PM UTC 24 |
346679628 ps |
| T1683 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/30.xbar_unmapped_addr.3789596198 |
|
|
Sep 04 06:06:03 PM UTC 24 |
Sep 04 06:06:23 PM UTC 24 |
308895341 ps |
| T1684 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/30.xbar_access_same_device.2131649353 |
|
|
Sep 04 06:05:45 PM UTC 24 |
Sep 04 06:06:36 PM UTC 24 |
433848170 ps |
| T1685 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/30.xbar_error_random.2918890262 |
|
|
Sep 04 06:05:56 PM UTC 24 |
Sep 04 06:06:43 PM UTC 24 |
1226497161 ps |
| T1686 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/30.xbar_stress_all.1985392440 |
|
|
Sep 04 06:06:13 PM UTC 24 |
Sep 04 06:06:44 PM UTC 24 |
652085974 ps |
| T1687 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/29.xbar_stress_all.2487484659 |
|
|
Sep 04 06:04:51 PM UTC 24 |
Sep 04 06:06:44 PM UTC 24 |
3280513652 ps |
| T1688 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/30.xbar_smoke_slow_rsp.3663001708 |
|
|
Sep 04 06:05:20 PM UTC 24 |
Sep 04 06:06:45 PM UTC 24 |
5627611170 ps |
| T1689 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/30.xbar_error_and_unmapped_addr.2825754133 |
|
|
Sep 04 06:06:05 PM UTC 24 |
Sep 04 06:06:52 PM UTC 24 |
923171615 ps |
| T1690 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/30.xbar_random.803343026 |
|
|
Sep 04 06:05:31 PM UTC 24 |
Sep 04 06:06:53 PM UTC 24 |
1738214654 ps |
| T844 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/23.xbar_access_same_device_slow_rsp.2055607127 |
|
|
Sep 04 05:54:35 PM UTC 24 |
Sep 04 06:06:55 PM UTC 24 |
46178856094 ps |
| T482 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/23.xbar_random_slow_rsp.3239503109 |
|
|
Sep 04 05:54:02 PM UTC 24 |
Sep 04 06:06:59 PM UTC 24 |
54040999188 ps |
| T1691 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/31.xbar_smoke.4106143141 |
|
|
Sep 04 06:06:53 PM UTC 24 |
Sep 04 06:07:05 PM UTC 24 |
128217961 ps |
| T1692 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/30.xbar_same_source.825646318 |
|
|
Sep 04 06:05:53 PM UTC 24 |
Sep 04 06:07:08 PM UTC 24 |
1674863456 ps |
| T1693 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/31.xbar_smoke_zero_delays.123418786 |
|
|
Sep 04 06:07:07 PM UTC 24 |
Sep 04 06:07:15 PM UTC 24 |
36128528 ps |
| T807 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/15.xbar_access_same_device_slow_rsp.813921597 |
|
|
Sep 04 05:35:32 PM UTC 24 |
Sep 04 06:07:21 PM UTC 24 |
117092477166 ps |
| T1694 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/30.xbar_smoke_large_delays.2856986531 |
|
|
Sep 04 06:05:24 PM UTC 24 |
Sep 04 06:07:22 PM UTC 24 |
8891324833 ps |
| T1695 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/27.xbar_stress_all_with_error.3628617826 |
|
|
Sep 04 06:01:32 PM UTC 24 |
Sep 04 06:07:27 PM UTC 24 |
3759799116 ps |
| T1696 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/31.xbar_random_zero_delays.1890584385 |
|
|
Sep 04 06:07:13 PM UTC 24 |
Sep 04 06:07:30 PM UTC 24 |
90626372 ps |
| T620 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/29.chip_tl_errors.395856592 |
|
|
Sep 04 06:03:16 PM UTC 24 |
Sep 04 06:07:45 PM UTC 24 |
3970041288 ps |
| T1697 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/31.xbar_random_large_delays.1551284326 |
|
|
Sep 04 06:07:22 PM UTC 24 |
Sep 04 06:07:54 PM UTC 24 |
3034748095 ps |
| T1698 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/26.xbar_random_slow_rsp.2405684878 |
|
|
Sep 04 05:58:46 PM UTC 24 |
Sep 04 06:07:56 PM UTC 24 |
34057550891 ps |
| T1699 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/31.xbar_error_and_unmapped_addr.2112264136 |
|
|
Sep 04 06:07:51 PM UTC 24 |
Sep 04 06:08:04 PM UTC 24 |
144860055 ps |
| T1700 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/31.xbar_access_same_device.1050097962 |
|
|
Sep 04 06:07:18 PM UTC 24 |
Sep 04 06:08:08 PM UTC 24 |
1573894005 ps |
| T1701 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/25.xbar_random_slow_rsp.163862118 |
|
|
Sep 04 05:57:23 PM UTC 24 |
Sep 04 06:08:09 PM UTC 24 |
34978833265 ps |
| T1702 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/31.xbar_random.4122232503 |
|
|
Sep 04 06:07:11 PM UTC 24 |
Sep 04 06:08:15 PM UTC 24 |
1648005430 ps |
| T1703 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/31.xbar_unmapped_addr.404887208 |
|
|
Sep 04 06:07:45 PM UTC 24 |
Sep 04 06:08:26 PM UTC 24 |
249311330 ps |
| T1704 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/31.xbar_smoke_slow_rsp.87399005 |
|
|
Sep 04 06:07:10 PM UTC 24 |
Sep 04 06:08:28 PM UTC 24 |
5599730902 ps |
| T1705 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/31.xbar_access_same_device_slow_rsp.2619828598 |
|
|
Sep 04 06:07:26 PM UTC 24 |
Sep 04 06:08:30 PM UTC 24 |
2422337257 ps |
| T1706 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/32.xbar_smoke.4096162671 |
|
|
Sep 04 06:08:21 PM UTC 24 |
Sep 04 06:08:35 PM UTC 24 |
211313586 ps |
| T1707 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/28.xbar_random_large_delays.2662160077 |
|
|
Sep 04 06:02:20 PM UTC 24 |
Sep 04 06:08:36 PM UTC 24 |
31284084897 ps |
| T1708 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/32.xbar_smoke_zero_delays.3544302675 |
|
|
Sep 04 06:08:26 PM UTC 24 |
Sep 04 06:08:37 PM UTC 24 |
52484666 ps |
| T872 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/30.xbar_stress_all_with_rand_reset.1174094420 |
|
|
Sep 04 06:06:29 PM UTC 24 |
Sep 04 06:08:41 PM UTC 24 |
366585102 ps |
| T870 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/29.xbar_stress_all_with_rand_reset.3884922043 |
|
|
Sep 04 06:04:51 PM UTC 24 |
Sep 04 06:08:48 PM UTC 24 |
330704553 ps |
| T1709 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/31.xbar_smoke_large_delays.4082827936 |
|
|
Sep 04 06:07:12 PM UTC 24 |
Sep 04 06:08:48 PM UTC 24 |
7431151481 ps |
| T605 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/31.xbar_error_random.911259610 |
|
|
Sep 04 06:07:39 PM UTC 24 |
Sep 04 06:08:49 PM UTC 24 |
1954670335 ps |
| T1710 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/31.xbar_stress_all_with_reset_error.731516757 |
|
|
Sep 04 06:08:16 PM UTC 24 |
Sep 04 06:08:52 PM UTC 24 |
113268937 ps |
| T1711 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/29.xbar_stress_all_with_error.3825946496 |
|
|
Sep 04 06:04:53 PM UTC 24 |
Sep 04 06:08:55 PM UTC 24 |
5151830352 ps |
| T1712 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/24.xbar_random_large_delays.3179094097 |
|
|
Sep 04 05:55:36 PM UTC 24 |
Sep 04 06:09:04 PM UTC 24 |
80816028620 ps |
| T442 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/9.chip_same_csr_outstanding.2404027458 |
|
|
Sep 04 05:21:04 PM UTC 24 |
Sep 04 06:14:46 PM UTC 24 |
28627554470 ps |
| T1713 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/31.xbar_same_source.2213298922 |
|
|
Sep 04 06:07:31 PM UTC 24 |
Sep 04 06:09:12 PM UTC 24 |
2485866984 ps |
| T1714 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/32.xbar_random.1590986064 |
|
|
Sep 04 06:08:39 PM UTC 24 |
Sep 04 06:09:25 PM UTC 24 |
1303008477 ps |
| T1715 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/31.xbar_stress_all_with_rand_reset.839336770 |
|
|
Sep 04 06:07:59 PM UTC 24 |
Sep 04 06:09:32 PM UTC 24 |
175265630 ps |
| T1716 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/33.xbar_smoke.3963557937 |
|
|
Sep 04 06:09:26 PM UTC 24 |
Sep 04 06:09:36 PM UTC 24 |
41206147 ps |
| T1717 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/32.xbar_random_zero_delays.840067477 |
|
|
Sep 04 06:08:46 PM UTC 24 |
Sep 04 06:09:39 PM UTC 24 |
529584822 ps |
| T520 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/25.xbar_stress_all_with_rand_reset.1399439863 |
|
|
Sep 04 05:57:53 PM UTC 24 |
Sep 04 06:09:39 PM UTC 24 |
9480359171 ps |
| T1718 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/23.xbar_stress_all_with_reset_error.2374552410 |
|
|
Sep 04 05:55:04 PM UTC 24 |
Sep 04 06:09:44 PM UTC 24 |
9684362881 ps |
| T1719 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/33.xbar_smoke_zero_delays.3129663506 |
|
|
Sep 04 06:09:36 PM UTC 24 |
Sep 04 06:09:45 PM UTC 24 |
49186917 ps |
| T1720 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/32.xbar_error_random.3442236164 |
|
|
Sep 04 06:09:05 PM UTC 24 |
Sep 04 06:09:45 PM UTC 24 |
351465216 ps |
| T1721 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/32.xbar_error_and_unmapped_addr.2217891460 |
|
|
Sep 04 06:09:16 PM UTC 24 |
Sep 04 06:09:50 PM UTC 24 |
894321257 ps |
| T1722 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/32.xbar_unmapped_addr.1722915016 |
|
|
Sep 04 06:09:12 PM UTC 24 |
Sep 04 06:10:06 PM UTC 24 |
1366314916 ps |
| T1723 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/32.xbar_smoke_slow_rsp.942704416 |
|
|
Sep 04 06:08:39 PM UTC 24 |
Sep 04 06:10:09 PM UTC 24 |
5111994711 ps |
| T1724 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/28.xbar_stress_all_with_error.151976925 |
|
|
Sep 04 06:03:06 PM UTC 24 |
Sep 04 06:10:12 PM UTC 24 |
9938423051 ps |
| T1725 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/33.xbar_random.2079825676 |
|
|
Sep 04 06:10:03 PM UTC 24 |
Sep 04 06:10:16 PM UTC 24 |
123627398 ps |
| T1726 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/32.xbar_smoke_large_delays.431885026 |
|
|
Sep 04 06:08:33 PM UTC 24 |
Sep 04 06:10:16 PM UTC 24 |
10002809164 ps |
| T1727 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/31.xbar_stress_all_with_error.4040229935 |
|
|
Sep 04 06:08:00 PM UTC 24 |
Sep 04 06:10:22 PM UTC 24 |
5246555338 ps |
| T513 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/32.xbar_same_source.4048581407 |
|
|
Sep 04 06:09:06 PM UTC 24 |
Sep 04 06:10:29 PM UTC 24 |
2671493710 ps |
| T643 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/27.chip_tl_errors.348496655 |
|
|
Sep 04 05:59:56 PM UTC 24 |
Sep 04 06:10:29 PM UTC 24 |
6416448480 ps |
| T1728 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/28.xbar_random_slow_rsp.1704952451 |
|
|
Sep 04 06:02:22 PM UTC 24 |
Sep 04 06:10:30 PM UTC 24 |
28453153848 ps |
| T1729 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/32.xbar_access_same_device.2934405549 |
|
|
Sep 04 06:09:01 PM UTC 24 |
Sep 04 06:10:37 PM UTC 24 |
993394659 ps |
| T1730 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/33.xbar_smoke_slow_rsp.552024094 |
|
|
Sep 04 06:09:55 PM UTC 24 |
Sep 04 06:10:42 PM UTC 24 |
3398665542 ps |
| T1731 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/33.xbar_access_same_device.4254682990 |
|
|
Sep 04 06:10:14 PM UTC 24 |
Sep 04 06:10:50 PM UTC 24 |
801405914 ps |
| T1732 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/33.xbar_smoke_large_delays.3429205915 |
|
|
Sep 04 06:09:42 PM UTC 24 |
Sep 04 06:10:51 PM UTC 24 |
6936130353 ps |
| T1733 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/33.xbar_error_and_unmapped_addr.287059482 |
|
|
Sep 04 06:10:35 PM UTC 24 |
Sep 04 06:10:52 PM UTC 24 |
224273763 ps |
| T1734 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/33.xbar_same_source.2974916769 |
|
|
Sep 04 06:10:17 PM UTC 24 |
Sep 04 06:11:05 PM UTC 24 |
492238740 ps |
| T1735 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/27.xbar_random_large_delays.3032551672 |
|
|
Sep 04 06:00:35 PM UTC 24 |
Sep 04 06:11:05 PM UTC 24 |
61308523550 ps |
| T1736 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/33.xbar_random_zero_delays.1824904044 |
|
|
Sep 04 06:10:04 PM UTC 24 |
Sep 04 06:11:08 PM UTC 24 |
565505241 ps |
| T1737 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/30.xbar_random_slow_rsp.1520500490 |
|
|
Sep 04 06:05:42 PM UTC 24 |
Sep 04 06:11:11 PM UTC 24 |
24090482550 ps |
| T1738 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/34.xbar_smoke.1865859627 |
|
|
Sep 04 06:10:59 PM UTC 24 |
Sep 04 06:11:12 PM UTC 24 |
188029733 ps |
| T1739 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/34.xbar_smoke_zero_delays.1968616090 |
|
|
Sep 04 06:11:02 PM UTC 24 |
Sep 04 06:11:12 PM UTC 24 |
46363611 ps |
| T1740 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/33.xbar_error_random.3488732709 |
|
|
Sep 04 06:10:21 PM UTC 24 |
Sep 04 06:11:14 PM UTC 24 |
1094063772 ps |
| T1741 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/33.xbar_unmapped_addr.2595246059 |
|
|
Sep 04 06:10:35 PM UTC 24 |
Sep 04 06:11:15 PM UTC 24 |
206146631 ps |
| T1742 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/26.xbar_random_large_delays.1703579197 |
|
|
Sep 04 05:58:40 PM UTC 24 |
Sep 04 06:11:16 PM UTC 24 |
77332752154 ps |
| T496 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/27.xbar_stress_all.1394557356 |
|
|
Sep 04 06:01:01 PM UTC 24 |
Sep 04 06:11:35 PM UTC 24 |
13950269560 ps |
| T1743 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/34.xbar_random.3039297881 |
|
|
Sep 04 06:11:11 PM UTC 24 |
Sep 04 06:11:45 PM UTC 24 |
663140034 ps |
| T1744 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/34.xbar_unmapped_addr.3908699364 |
|
|
Sep 04 06:11:33 PM UTC 24 |
Sep 04 06:11:56 PM UTC 24 |
495401415 ps |
| T1745 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/31.xbar_stress_all.4113118512 |
|
|
Sep 04 06:07:52 PM UTC 24 |
Sep 04 06:11:59 PM UTC 24 |
2839245469 ps |
| T1746 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/34.xbar_error_random.687913096 |
|
|
Sep 04 06:11:36 PM UTC 24 |
Sep 04 06:12:00 PM UTC 24 |
591871993 ps |
| T1747 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/34.xbar_random_zero_delays.2757939510 |
|
|
Sep 04 06:11:19 PM UTC 24 |
Sep 04 06:12:06 PM UTC 24 |
471791058 ps |
| T1748 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/34.xbar_error_and_unmapped_addr.1636082248 |
|
|
Sep 04 06:11:41 PM UTC 24 |
Sep 04 06:12:13 PM UTC 24 |
571696741 ps |
| T1749 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/34.xbar_same_source.479670408 |
|
|
Sep 04 06:11:39 PM UTC 24 |
Sep 04 06:12:19 PM UTC 24 |
1155376552 ps |
| T1750 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/34.xbar_smoke_slow_rsp.1122476214 |
|
|
Sep 04 06:11:09 PM UTC 24 |
Sep 04 06:12:21 PM UTC 24 |
5119645264 ps |
| T1751 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/35.xbar_smoke.1451018992 |
|
|
Sep 04 06:12:16 PM UTC 24 |
Sep 04 06:12:26 PM UTC 24 |
52762791 ps |
| T1752 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/35.xbar_smoke_zero_delays.1645651720 |
|
|
Sep 04 06:12:24 PM UTC 24 |
Sep 04 06:12:31 PM UTC 24 |
52571613 ps |
| T1753 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/34.xbar_smoke_large_delays.3160702482 |
|
|
Sep 04 06:10:57 PM UTC 24 |
Sep 04 06:12:42 PM UTC 24 |
8453274564 ps |
| T789 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/19.xbar_access_same_device_slow_rsp.1288717716 |
|
|
Sep 04 05:45:50 PM UTC 24 |
Sep 04 06:12:57 PM UTC 24 |
108823630474 ps |
| T1754 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/34.xbar_random_slow_rsp.3980784588 |
|
|
Sep 04 06:11:23 PM UTC 24 |
Sep 04 06:13:03 PM UTC 24 |
4405546242 ps |
| T1755 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/30.xbar_stress_all_with_error.1357721350 |
|
|
Sep 04 06:06:36 PM UTC 24 |
Sep 04 06:13:06 PM UTC 24 |
11915380045 ps |
| T1756 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/35.xbar_random_zero_delays.3277102811 |
|
|
Sep 04 06:12:43 PM UTC 24 |
Sep 04 06:13:09 PM UTC 24 |
233856435 ps |
| T1757 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/35.xbar_random.3978844650 |
|
|
Sep 04 06:12:34 PM UTC 24 |
Sep 04 06:13:19 PM UTC 24 |
1286520486 ps |
| T1758 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/34.xbar_access_same_device.4158694257 |
|
|
Sep 04 06:11:31 PM UTC 24 |
Sep 04 06:13:21 PM UTC 24 |
1333147682 ps |
| T1759 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/34.xbar_stress_all_with_reset_error.819818064 |
|
|
Sep 04 06:12:06 PM UTC 24 |
Sep 04 06:13:25 PM UTC 24 |
189851237 ps |
| T1760 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/32.xbar_stress_all_with_error.3876551443 |
|
|
Sep 04 06:09:21 PM UTC 24 |
Sep 04 06:13:27 PM UTC 24 |
7197963846 ps |
| T1761 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/34.xbar_stress_all_with_error.4004050290 |
|
|
Sep 04 06:11:46 PM UTC 24 |
Sep 04 06:13:34 PM UTC 24 |
2998145143 ps |
| T1762 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/35.xbar_error_random.74980995 |
|
|
Sep 04 06:13:28 PM UTC 24 |
Sep 04 06:13:37 PM UTC 24 |
37190489 ps |
| T1763 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/35.xbar_smoke_slow_rsp.3440295708 |
|
|
Sep 04 06:12:31 PM UTC 24 |
Sep 04 06:13:39 PM UTC 24 |
2934905970 ps |
| T1764 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/35.xbar_same_source.2148376331 |
|
|
Sep 04 06:13:13 PM UTC 24 |
Sep 04 06:13:44 PM UTC 24 |
459596338 ps |
| T514 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/27.xbar_random_slow_rsp.2559152325 |
|
|
Sep 04 06:00:36 PM UTC 24 |
Sep 04 06:13:44 PM UTC 24 |
54158517940 ps |
| T1765 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/35.xbar_random_slow_rsp.1921175099 |
|
|
Sep 04 06:12:45 PM UTC 24 |
Sep 04 06:13:48 PM UTC 24 |
2983061068 ps |
| T848 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/35.xbar_access_same_device.1659901724 |
|
|
Sep 04 06:12:52 PM UTC 24 |
Sep 04 06:14:03 PM UTC 24 |
1234496060 ps |
| T1766 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/35.xbar_error_and_unmapped_addr.1565188506 |
|
|
Sep 04 06:13:37 PM UTC 24 |
Sep 04 06:14:05 PM UTC 24 |
272005552 ps |
| T1767 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/30.xbar_stress_all_with_reset_error.2714394091 |
|
|
Sep 04 06:06:52 PM UTC 24 |
Sep 04 06:14:06 PM UTC 24 |
3357278065 ps |
| T1768 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/36.xbar_smoke.2881545704 |
|
|
Sep 04 06:13:58 PM UTC 24 |
Sep 04 06:14:08 PM UTC 24 |
215744087 ps |
| T1769 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/36.xbar_smoke_zero_delays.67327972 |
|
|
Sep 04 06:14:02 PM UTC 24 |
Sep 04 06:14:10 PM UTC 24 |
40620632 ps |
| T846 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/21.xbar_access_same_device_slow_rsp.4003207921 |
|
|
Sep 04 05:49:42 PM UTC 24 |
Sep 04 06:14:25 PM UTC 24 |
107874225611 ps |
| T1770 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/35.xbar_smoke_large_delays.3714245843 |
|
|
Sep 04 06:12:30 PM UTC 24 |
Sep 04 06:14:27 PM UTC 24 |
7069575133 ps |
| T1771 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/33.xbar_stress_all_with_rand_reset.3626156517 |
|
|
Sep 04 06:10:45 PM UTC 24 |
Sep 04 06:14:32 PM UTC 24 |
645417551 ps |
| T1772 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/35.xbar_unmapped_addr.4060116163 |
|
|
Sep 04 06:13:33 PM UTC 24 |
Sep 04 06:14:33 PM UTC 24 |
1058131940 ps |
| T1773 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/36.xbar_random_zero_delays.1688912765 |
|
|
Sep 04 06:14:12 PM UTC 24 |
Sep 04 06:14:39 PM UTC 24 |
215443093 ps |
| T1774 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/33.xbar_stress_all.2629669827 |
|
|
Sep 04 06:10:43 PM UTC 24 |
Sep 04 06:14:46 PM UTC 24 |
6566505164 ps |
| T521 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/32.xbar_stress_all.667643007 |
|
|
Sep 04 06:09:20 PM UTC 24 |
Sep 04 06:14:50 PM UTC 24 |
3726985165 ps |
| T1775 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/28.xbar_access_same_device_slow_rsp.30616252 |
|
|
Sep 04 06:02:25 PM UTC 24 |
Sep 04 06:14:54 PM UTC 24 |
52143895855 ps |
| T1776 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/36.xbar_random.3650454874 |
|
|
Sep 04 06:14:07 PM UTC 24 |
Sep 04 06:15:01 PM UTC 24 |
1506033010 ps |
| T1777 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/36.xbar_error_and_unmapped_addr.3925371732 |
|
|
Sep 04 06:14:58 PM UTC 24 |
Sep 04 06:15:08 PM UTC 24 |
31994975 ps |
| T1778 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/34.xbar_access_same_device_slow_rsp.3801378431 |
|
|
Sep 04 06:11:34 PM UTC 24 |
Sep 04 06:15:14 PM UTC 24 |
14550516041 ps |
| T1779 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/35.xbar_stress_all.665759338 |
|
|
Sep 04 06:13:40 PM UTC 24 |
Sep 04 06:15:19 PM UTC 24 |
899483234 ps |
| T1780 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/37.xbar_smoke.395808509 |
|
|
Sep 04 06:15:12 PM UTC 24 |
Sep 04 06:15:23 PM UTC 24 |
212141255 ps |
| T1781 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/33.xbar_random_large_delays.2919380774 |
|
|
Sep 04 06:10:09 PM UTC 24 |
Sep 04 06:15:25 PM UTC 24 |
28450963531 ps |
| T608 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/29.xbar_stress_all_with_reset_error.3959483762 |
|
|
Sep 04 06:05:03 PM UTC 24 |
Sep 04 06:15:28 PM UTC 24 |
14955551038 ps |
| T1782 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/37.xbar_smoke_zero_delays.1453749256 |
|
|
Sep 04 06:15:20 PM UTC 24 |
Sep 04 06:15:28 PM UTC 24 |
40298561 ps |
| T1783 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/36.xbar_same_source.758450279 |
|
|
Sep 04 06:14:39 PM UTC 24 |
Sep 04 06:15:31 PM UTC 24 |
1200016851 ps |
| T1784 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/36.xbar_access_same_device.3885195463 |
|
|
Sep 04 06:14:32 PM UTC 24 |
Sep 04 06:15:36 PM UTC 24 |
675156917 ps |
| T1785 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/36.xbar_unmapped_addr.1189464561 |
|
|
Sep 04 06:14:57 PM UTC 24 |
Sep 04 06:15:50 PM UTC 24 |
313777700 ps |
| T1786 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/36.xbar_smoke_slow_rsp.2801097127 |
|
|
Sep 04 06:14:07 PM UTC 24 |
Sep 04 06:15:52 PM UTC 24 |
5401306226 ps |
| T1787 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/37.xbar_random.3172315422 |
|
|
Sep 04 06:15:36 PM UTC 24 |
Sep 04 06:15:56 PM UTC 24 |
120646655 ps |
| T1788 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/33.xbar_stress_all_with_reset_error.432774919 |
|
|
Sep 04 06:10:53 PM UTC 24 |
Sep 04 06:16:02 PM UTC 24 |
1376696220 ps |
| T1789 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/36.xbar_error_random.1155479377 |
|
|
Sep 04 06:14:41 PM UTC 24 |
Sep 04 06:16:03 PM UTC 24 |
2322977824 ps |
| T1790 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/37.xbar_random_zero_delays.2523897589 |
|
|
Sep 04 06:15:44 PM UTC 24 |
Sep 04 06:16:07 PM UTC 24 |
200885345 ps |
| T1791 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/36.xbar_smoke_large_delays.2948441328 |
|
|
Sep 04 06:14:07 PM UTC 24 |
Sep 04 06:16:10 PM UTC 24 |
7749009765 ps |
| T1792 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/37.xbar_error_random.2102095550 |
|
|
Sep 04 06:16:02 PM UTC 24 |
Sep 04 06:16:16 PM UTC 24 |
243537040 ps |
| T1793 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/33.xbar_random_slow_rsp.2938199737 |
|
|
Sep 04 06:10:10 PM UTC 24 |
Sep 04 06:16:16 PM UTC 24 |
28475741923 ps |
| T1794 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/2.chip_csr_aliasing.3874157396 |
|
|
Sep 04 05:03:22 PM UTC 24 |
Sep 04 06:16:19 PM UTC 24 |
26590172920 ps |
| T1795 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/34.xbar_random_large_delays.846721176 |
|
|
Sep 04 06:11:23 PM UTC 24 |
Sep 04 06:16:34 PM UTC 24 |
28568343535 ps |