| T636 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/9.xbar_stress_all_with_error.2356789457 |
|
|
Sep 04 05:23:14 PM UTC 24 |
Sep 04 05:28:48 PM UTC 24 |
8953030906 ps |
| T1429 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/12.xbar_random_zero_delays.2575400053 |
|
|
Sep 04 05:28:43 PM UTC 24 |
Sep 04 05:28:52 PM UTC 24 |
30364674 ps |
| T1430 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/12.xbar_random.2835037989 |
|
|
Sep 04 05:28:21 PM UTC 24 |
Sep 04 05:28:58 PM UTC 24 |
844594394 ps |
| T863 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/10.xbar_stress_all_with_rand_reset.1638340085 |
|
|
Sep 04 05:24:37 PM UTC 24 |
Sep 04 05:29:14 PM UTC 24 |
573882504 ps |
| T1431 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/12.xbar_stress_all.3876994004 |
|
|
Sep 04 05:29:28 PM UTC 24 |
Sep 04 05:29:35 PM UTC 24 |
6445281 ps |
| T534 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/11.xbar_stress_all.2174466554 |
|
|
Sep 04 05:27:10 PM UTC 24 |
Sep 04 05:29:39 PM UTC 24 |
2895869066 ps |
| T1432 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/12.xbar_unmapped_addr.3510275261 |
|
|
Sep 04 05:29:19 PM UTC 24 |
Sep 04 05:29:41 PM UTC 24 |
102625001 ps |
| T632 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/7.chip_csr_mem_rw_with_rand_reset.3618822739 |
|
|
Sep 04 05:18:10 PM UTC 24 |
Sep 04 05:29:43 PM UTC 24 |
10398808792 ps |
| T1433 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/12.xbar_smoke_slow_rsp.2218696413 |
|
|
Sep 04 05:28:25 PM UTC 24 |
Sep 04 05:29:47 PM UTC 24 |
4543597410 ps |
| T1434 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/12.xbar_error_and_unmapped_addr.428152832 |
|
|
Sep 04 05:29:24 PM UTC 24 |
Sep 04 05:29:55 PM UTC 24 |
216645911 ps |
| T1435 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/12.xbar_error_random.2475690944 |
|
|
Sep 04 05:29:16 PM UTC 24 |
Sep 04 05:29:55 PM UTC 24 |
1109565223 ps |
| T484 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/10.xbar_random_large_delays.2770508647 |
|
|
Sep 04 05:23:53 PM UTC 24 |
Sep 04 05:29:56 PM UTC 24 |
33238028864 ps |
| T530 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/12.xbar_same_source.2602331828 |
|
|
Sep 04 05:29:03 PM UTC 24 |
Sep 04 05:30:00 PM UTC 24 |
548505823 ps |
| T1436 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/8.chip_csr_rw.3779917320 |
|
|
Sep 04 05:20:57 PM UTC 24 |
Sep 04 05:30:05 PM UTC 24 |
6246409204 ps |
| T799 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/7.xbar_access_same_device_slow_rsp.3936632910 |
|
|
Sep 04 05:16:59 PM UTC 24 |
Sep 04 05:30:09 PM UTC 24 |
52734863559 ps |
| T570 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/10.chip_tl_errors.63078316 |
|
|
Sep 04 05:23:21 PM UTC 24 |
Sep 04 05:30:16 PM UTC 24 |
4345645130 ps |
| T827 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/9.xbar_stress_all_with_reset_error.1286888093 |
|
|
Sep 04 05:23:14 PM UTC 24 |
Sep 04 05:30:19 PM UTC 24 |
3063598909 ps |
| T1437 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/13.xbar_smoke.314428512 |
|
|
Sep 04 05:30:20 PM UTC 24 |
Sep 04 05:30:29 PM UTC 24 |
188002897 ps |
| T1438 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/12.xbar_smoke_large_delays.4023369832 |
|
|
Sep 04 05:28:26 PM UTC 24 |
Sep 04 05:30:30 PM UTC 24 |
9555021018 ps |
| T1439 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/13.xbar_smoke_zero_delays.1386476832 |
|
|
Sep 04 05:30:24 PM UTC 24 |
Sep 04 05:30:33 PM UTC 24 |
39117699 ps |
| T460 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/8.xbar_stress_all_with_rand_reset.1840039775 |
|
|
Sep 04 05:20:39 PM UTC 24 |
Sep 04 05:30:34 PM UTC 24 |
5876389016 ps |
| T821 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/11.xbar_stress_all_with_reset_error.1365369033 |
|
|
Sep 04 05:27:41 PM UTC 24 |
Sep 04 05:30:54 PM UTC 24 |
652375923 ps |
| T1440 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/13.xbar_random_zero_delays.3322897579 |
|
|
Sep 04 05:30:44 PM UTC 24 |
Sep 04 05:30:55 PM UTC 24 |
35784380 ps |
| T658 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/12.xbar_access_same_device.2079112593 |
|
|
Sep 04 05:28:52 PM UTC 24 |
Sep 04 05:30:56 PM UTC 24 |
2423112956 ps |
| T1441 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/11.xbar_stress_all_with_error.2721481362 |
|
|
Sep 04 05:27:37 PM UTC 24 |
Sep 04 05:31:07 PM UTC 24 |
6319047957 ps |
| T607 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/5.xbar_random_large_delays.2729535791 |
|
|
Sep 04 05:11:14 PM UTC 24 |
Sep 04 05:31:07 PM UTC 24 |
106789599549 ps |
| T1442 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/9.xbar_random_slow_rsp.3859118446 |
|
|
Sep 04 05:22:00 PM UTC 24 |
Sep 04 05:31:08 PM UTC 24 |
37223757975 ps |
| T828 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/8.xbar_stress_all_with_reset_error.646162969 |
|
|
Sep 04 05:20:58 PM UTC 24 |
Sep 04 05:31:25 PM UTC 24 |
6430087828 ps |
| T584 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/12.chip_tl_errors.3363106197 |
|
|
Sep 04 05:27:56 PM UTC 24 |
Sep 04 05:31:26 PM UTC 24 |
3475360960 ps |
| T1443 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/13.xbar_smoke_slow_rsp.2905755652 |
|
|
Sep 04 05:30:34 PM UTC 24 |
Sep 04 05:31:38 PM UTC 24 |
4281341824 ps |
| T633 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/9.chip_csr_rw.2804006546 |
|
|
Sep 04 05:23:20 PM UTC 24 |
Sep 04 05:31:44 PM UTC 24 |
5692631894 ps |
| T1444 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/13.xbar_random_large_delays.1352922999 |
|
|
Sep 04 05:30:49 PM UTC 24 |
Sep 04 05:31:46 PM UTC 24 |
6185096281 ps |
| T464 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/13.xbar_same_source.3359998992 |
|
|
Sep 04 05:31:03 PM UTC 24 |
Sep 04 05:31:48 PM UTC 24 |
1665262633 ps |
| T524 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/13.xbar_random.2608757016 |
|
|
Sep 04 05:30:39 PM UTC 24 |
Sep 04 05:31:50 PM UTC 24 |
1744712262 ps |
| T1445 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/11.chip_csr_rw.1984154712 |
|
|
Sep 04 05:27:46 PM UTC 24 |
Sep 04 05:31:53 PM UTC 24 |
3924247728 ps |
| T1446 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/13.xbar_unmapped_addr.2170127370 |
|
|
Sep 04 05:31:25 PM UTC 24 |
Sep 04 05:32:05 PM UTC 24 |
873578473 ps |
| T1447 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/13.xbar_smoke_large_delays.3437809511 |
|
|
Sep 04 05:30:30 PM UTC 24 |
Sep 04 05:32:08 PM UTC 24 |
6802075336 ps |
| T1448 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/13.xbar_error_and_unmapped_addr.2745907282 |
|
|
Sep 04 05:31:25 PM UTC 24 |
Sep 04 05:32:09 PM UTC 24 |
291920833 ps |
| T1449 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/13.xbar_error_random.2335043672 |
|
|
Sep 04 05:31:26 PM UTC 24 |
Sep 04 05:32:11 PM UTC 24 |
543773679 ps |
| T813 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/8.xbar_access_same_device_slow_rsp.945419143 |
|
|
Sep 04 05:19:26 PM UTC 24 |
Sep 04 05:32:15 PM UTC 24 |
38746086568 ps |
| T1450 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/14.xbar_smoke.913457016 |
|
|
Sep 04 05:32:16 PM UTC 24 |
Sep 04 05:32:26 PM UTC 24 |
38418877 ps |
| T1451 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/14.xbar_smoke_zero_delays.3131682396 |
|
|
Sep 04 05:32:22 PM UTC 24 |
Sep 04 05:32:31 PM UTC 24 |
45451701 ps |
| T1452 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/9.chip_csr_mem_rw_with_rand_reset.2428365220 |
|
|
Sep 04 05:23:19 PM UTC 24 |
Sep 04 05:32:39 PM UTC 24 |
7603730548 ps |
| T1453 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/13.xbar_stress_all_with_error.3490399763 |
|
|
Sep 04 05:31:38 PM UTC 24 |
Sep 04 05:32:54 PM UTC 24 |
649903018 ps |
| T1454 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/14.xbar_random.3431664284 |
|
|
Sep 04 05:32:40 PM UTC 24 |
Sep 04 05:33:09 PM UTC 24 |
195898739 ps |
| T610 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/13.xbar_stress_all.764781392 |
|
|
Sep 04 05:31:35 PM UTC 24 |
Sep 04 05:33:19 PM UTC 24 |
1007002537 ps |
| T826 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/13.xbar_access_same_device.3753745610 |
|
|
Sep 04 05:30:59 PM UTC 24 |
Sep 04 05:33:26 PM UTC 24 |
2949202883 ps |
| T531 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/14.xbar_random_zero_delays.3221009149 |
|
|
Sep 04 05:32:39 PM UTC 24 |
Sep 04 05:33:27 PM UTC 24 |
539125394 ps |
| T1455 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/14.xbar_smoke_large_delays.1325351762 |
|
|
Sep 04 05:32:24 PM UTC 24 |
Sep 04 05:33:30 PM UTC 24 |
5090036230 ps |
| T441 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/10.chip_csr_rw.3375357539 |
|
|
Sep 04 05:25:07 PM UTC 24 |
Sep 04 05:33:38 PM UTC 24 |
5533554640 ps |
| T505 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/14.xbar_same_source.1636151071 |
|
|
Sep 04 05:33:10 PM UTC 24 |
Sep 04 05:33:42 PM UTC 24 |
735969177 ps |
| T1456 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/8.xbar_random_large_delays.2080560037 |
|
|
Sep 04 05:19:11 PM UTC 24 |
Sep 04 05:33:54 PM UTC 24 |
84346745584 ps |
| T1457 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/14.xbar_unmapped_addr.131194516 |
|
|
Sep 04 05:33:39 PM UTC 24 |
Sep 04 05:33:57 PM UTC 24 |
106074460 ps |
| T1458 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/14.xbar_error_random.1858022160 |
|
|
Sep 04 05:33:22 PM UTC 24 |
Sep 04 05:33:59 PM UTC 24 |
307692278 ps |
| T1459 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/1.chip_same_csr_outstanding.669831048 |
|
|
Sep 04 05:01:26 PM UTC 24 |
Sep 04 05:34:04 PM UTC 24 |
15732686478 ps |
| T506 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/14.xbar_access_same_device.1592907335 |
|
|
Sep 04 05:32:55 PM UTC 24 |
Sep 04 05:34:07 PM UTC 24 |
1141779958 ps |
| T1460 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/14.xbar_random_slow_rsp.3241883345 |
|
|
Sep 04 05:32:47 PM UTC 24 |
Sep 04 05:34:19 PM UTC 24 |
3915959128 ps |
| T1461 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/14.xbar_error_and_unmapped_addr.3561967815 |
|
|
Sep 04 05:33:49 PM UTC 24 |
Sep 04 05:34:30 PM UTC 24 |
940349751 ps |
| T815 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/14.xbar_smoke_slow_rsp.3475627186 |
|
|
Sep 04 05:32:36 PM UTC 24 |
Sep 04 05:34:42 PM UTC 24 |
5479007799 ps |
| T591 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/15.xbar_smoke_zero_delays.270221684 |
|
|
Sep 04 05:34:37 PM UTC 24 |
Sep 04 05:34:47 PM UTC 24 |
50437345 ps |
| T840 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/13.xbar_access_same_device_slow_rsp.1551015156 |
|
|
Sep 04 05:30:59 PM UTC 24 |
Sep 04 05:34:47 PM UTC 24 |
15544945387 ps |
| T1462 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/15.xbar_smoke.907689093 |
|
|
Sep 04 05:34:35 PM UTC 24 |
Sep 04 05:34:48 PM UTC 24 |
186236192 ps |
| T1463 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/10.chip_csr_mem_rw_with_rand_reset.2265008926 |
|
|
Sep 04 05:25:19 PM UTC 24 |
Sep 04 05:34:59 PM UTC 24 |
6925410136 ps |
| T574 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/13.chip_tl_errors.2405194159 |
|
|
Sep 04 05:30:22 PM UTC 24 |
Sep 04 05:35:01 PM UTC 24 |
3912550920 ps |
| T572 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/14.xbar_stress_all.615768031 |
|
|
Sep 04 05:33:57 PM UTC 24 |
Sep 04 05:35:30 PM UTC 24 |
1010545023 ps |
| T866 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/14.xbar_stress_all_with_reset_error.3452399770 |
|
|
Sep 04 05:34:05 PM UTC 24 |
Sep 04 05:35:37 PM UTC 24 |
289902885 ps |
| T1464 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/15.xbar_random.793012985 |
|
|
Sep 04 05:35:11 PM UTC 24 |
Sep 04 05:35:47 PM UTC 24 |
329852078 ps |
| T471 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/15.xbar_access_same_device.2761918149 |
|
|
Sep 04 05:35:28 PM UTC 24 |
Sep 04 05:35:47 PM UTC 24 |
191199728 ps |
| T1465 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/15.xbar_random_zero_delays.2092192308 |
|
|
Sep 04 05:35:16 PM UTC 24 |
Sep 04 05:36:08 PM UTC 24 |
398364767 ps |
| T1466 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/15.xbar_smoke_slow_rsp.1082149155 |
|
|
Sep 04 05:35:01 PM UTC 24 |
Sep 04 05:36:09 PM UTC 24 |
4528330414 ps |
| T1467 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/15.xbar_same_source.2630581916 |
|
|
Sep 04 05:36:02 PM UTC 24 |
Sep 04 05:36:20 PM UTC 24 |
318850488 ps |
| T518 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/12.xbar_stress_all_with_rand_reset.2645757309 |
|
|
Sep 04 05:29:45 PM UTC 24 |
Sep 04 05:36:23 PM UTC 24 |
8198792854 ps |
| T1468 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/15.xbar_error_random.372672706 |
|
|
Sep 04 05:36:08 PM UTC 24 |
Sep 04 05:36:25 PM UTC 24 |
271661663 ps |
| T1469 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/15.xbar_unmapped_addr.2209273460 |
|
|
Sep 04 05:36:18 PM UTC 24 |
Sep 04 05:36:29 PM UTC 24 |
97811965 ps |
| T1470 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/13.chip_csr_rw.1071759866 |
|
|
Sep 04 05:31:57 PM UTC 24 |
Sep 04 05:37:26 PM UTC 24 |
3966715873 ps |
| T386 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/3.chip_same_csr_outstanding.2697912503 |
|
|
Sep 04 05:05:59 PM UTC 24 |
Sep 04 05:37:27 PM UTC 24 |
18004167967 ps |
| T1471 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/15.xbar_error_and_unmapped_addr.4095289178 |
|
|
Sep 04 05:36:17 PM UTC 24 |
Sep 04 05:37:28 PM UTC 24 |
1265685832 ps |
| T832 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/12.xbar_stress_all_with_error.3536251290 |
|
|
Sep 04 05:30:04 PM UTC 24 |
Sep 04 05:37:31 PM UTC 24 |
13025342084 ps |
| T1472 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/15.xbar_smoke_large_delays.1873324278 |
|
|
Sep 04 05:34:48 PM UTC 24 |
Sep 04 05:37:35 PM UTC 24 |
10133604761 ps |
| T580 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/10.xbar_random_slow_rsp.1313050922 |
|
|
Sep 04 05:23:53 PM UTC 24 |
Sep 04 05:37:47 PM UTC 24 |
57103644620 ps |
| T576 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/15.chip_tl_errors.1905904371 |
|
|
Sep 04 05:34:27 PM UTC 24 |
Sep 04 05:37:54 PM UTC 24 |
2921566885 ps |
| T387 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/4.chip_same_csr_outstanding.999085954 |
|
|
Sep 04 05:08:17 PM UTC 24 |
Sep 04 05:38:01 PM UTC 24 |
15500378527 ps |
| T1473 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/16.xbar_smoke.2417438082 |
|
|
Sep 04 05:37:54 PM UTC 24 |
Sep 04 05:38:02 PM UTC 24 |
42361038 ps |
| T1474 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/16.xbar_smoke_zero_delays.312941352 |
|
|
Sep 04 05:37:58 PM UTC 24 |
Sep 04 05:38:09 PM UTC 24 |
53519386 ps |
| T1475 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/14.chip_csr_rw.930830825 |
|
|
Sep 04 05:34:12 PM UTC 24 |
Sep 04 05:38:28 PM UTC 24 |
4172251906 ps |
| T1476 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/15.xbar_stress_all_with_rand_reset.2410487017 |
|
|
Sep 04 05:36:39 PM UTC 24 |
Sep 04 05:38:34 PM UTC 24 |
124981876 ps |
| T880 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/15.xbar_stress_all_with_reset_error.819290157 |
|
|
Sep 04 05:36:54 PM UTC 24 |
Sep 04 05:38:39 PM UTC 24 |
295007638 ps |
| T1477 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/13.xbar_random_slow_rsp.4264921252 |
|
|
Sep 04 05:30:58 PM UTC 24 |
Sep 04 05:39:10 PM UTC 24 |
24997325178 ps |
| T1478 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/16.xbar_same_source.2183778793 |
|
|
Sep 04 05:39:03 PM UTC 24 |
Sep 04 05:39:18 PM UTC 24 |
342676531 ps |
| T1479 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/16.xbar_random_zero_delays.1064608834 |
|
|
Sep 04 05:38:23 PM UTC 24 |
Sep 04 05:39:19 PM UTC 24 |
467043044 ps |
| T1480 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/11.xbar_random_slow_rsp.1562935139 |
|
|
Sep 04 05:26:15 PM UTC 24 |
Sep 04 05:39:26 PM UTC 24 |
56548787982 ps |
| T1481 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/16.xbar_smoke_large_delays.1889631758 |
|
|
Sep 04 05:37:59 PM UTC 24 |
Sep 04 05:39:29 PM UTC 24 |
8398140995 ps |
| T504 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/8.xbar_random_slow_rsp.665934715 |
|
|
Sep 04 05:19:13 PM UTC 24 |
Sep 04 05:39:30 PM UTC 24 |
62101565485 ps |
| T1482 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/16.xbar_error_random.923633868 |
|
|
Sep 04 05:39:11 PM UTC 24 |
Sep 04 05:39:32 PM UTC 24 |
168822116 ps |
| T1483 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/16.xbar_smoke_slow_rsp.2587909187 |
|
|
Sep 04 05:37:58 PM UTC 24 |
Sep 04 05:39:36 PM UTC 24 |
4694393900 ps |
| T1484 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/16.xbar_random.30465437 |
|
|
Sep 04 05:38:18 PM UTC 24 |
Sep 04 05:39:42 PM UTC 24 |
2365667475 ps |
| T1485 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/12.chip_csr_rw.536110278 |
|
|
Sep 04 05:30:10 PM UTC 24 |
Sep 04 05:39:59 PM UTC 24 |
5398217515 ps |
| T1486 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/16.xbar_error_and_unmapped_addr.106869118 |
|
|
Sep 04 05:39:50 PM UTC 24 |
Sep 04 05:40:03 PM UTC 24 |
115779679 ps |
| T810 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/16.xbar_access_same_device.2440999322 |
|
|
Sep 04 05:38:40 PM UTC 24 |
Sep 04 05:40:05 PM UTC 24 |
1797820318 ps |
| T533 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/14.xbar_stress_all_with_rand_reset.544011214 |
|
|
Sep 04 05:33:56 PM UTC 24 |
Sep 04 05:40:14 PM UTC 24 |
9341099677 ps |
| T1487 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/16.xbar_unmapped_addr.2543377898 |
|
|
Sep 04 05:39:40 PM UTC 24 |
Sep 04 05:40:14 PM UTC 24 |
541281687 ps |
| T1488 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/16.xbar_random_large_delays.3447876303 |
|
|
Sep 04 05:38:31 PM UTC 24 |
Sep 04 05:40:30 PM UTC 24 |
10078202673 ps |
| T816 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/11.xbar_access_same_device_slow_rsp.391156679 |
|
|
Sep 04 05:26:25 PM UTC 24 |
Sep 04 05:40:34 PM UTC 24 |
58654646312 ps |
| T1489 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/17.xbar_smoke_zero_delays.347351418 |
|
|
Sep 04 05:40:36 PM UTC 24 |
Sep 04 05:40:44 PM UTC 24 |
51185066 ps |
| T1490 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/17.xbar_smoke.3686608538 |
|
|
Sep 04 05:40:34 PM UTC 24 |
Sep 04 05:40:46 PM UTC 24 |
185531477 ps |
| T801 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/13.xbar_stress_all_with_reset_error.3810969422 |
|
|
Sep 04 05:31:56 PM UTC 24 |
Sep 04 05:40:57 PM UTC 24 |
5691337188 ps |
| T596 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/16.xbar_stress_all.2811565262 |
|
|
Sep 04 05:39:50 PM UTC 24 |
Sep 04 05:40:58 PM UTC 24 |
602611500 ps |
| T1491 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/16.xbar_stress_all_with_reset_error.468965175 |
|
|
Sep 04 05:40:01 PM UTC 24 |
Sep 04 05:41:00 PM UTC 24 |
296610989 ps |
| T822 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/15.xbar_stress_all_with_error.4008825312 |
|
|
Sep 04 05:36:51 PM UTC 24 |
Sep 04 05:41:04 PM UTC 24 |
6377241632 ps |
| T575 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/14.chip_tl_errors.3310049566 |
|
|
Sep 04 05:32:18 PM UTC 24 |
Sep 04 05:41:08 PM UTC 24 |
4453976088 ps |
| T876 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/16.xbar_stress_all_with_rand_reset.3461972911 |
|
|
Sep 04 05:39:57 PM UTC 24 |
Sep 04 05:41:14 PM UTC 24 |
470765952 ps |
| T592 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/16.chip_tl_errors.3002026635 |
|
|
Sep 04 05:37:56 PM UTC 24 |
Sep 04 05:41:36 PM UTC 24 |
3419935980 ps |
| T1492 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/11.chip_csr_mem_rw_with_rand_reset.3950362802 |
|
|
Sep 04 05:27:48 PM UTC 24 |
Sep 04 05:41:54 PM UTC 24 |
8657931205 ps |
| T1493 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/17.xbar_random_zero_delays.524462430 |
|
|
Sep 04 05:41:05 PM UTC 24 |
Sep 04 05:41:56 PM UTC 24 |
510005599 ps |
| T1494 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/17.xbar_smoke_large_delays.2470435015 |
|
|
Sep 04 05:40:45 PM UTC 24 |
Sep 04 05:42:00 PM UTC 24 |
7544966163 ps |
| T1495 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/17.xbar_unmapped_addr.940323384 |
|
|
Sep 04 05:41:39 PM UTC 24 |
Sep 04 05:42:08 PM UTC 24 |
174239744 ps |
| T1496 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/17.xbar_random.1731596227 |
|
|
Sep 04 05:41:01 PM UTC 24 |
Sep 04 05:42:11 PM UTC 24 |
1839254820 ps |
| T839 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/17.xbar_access_same_device_slow_rsp.1527194222 |
|
|
Sep 04 05:41:28 PM UTC 24 |
Sep 04 05:42:13 PM UTC 24 |
2657185884 ps |
| T1497 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/17.xbar_smoke_slow_rsp.1522015747 |
|
|
Sep 04 05:40:45 PM UTC 24 |
Sep 04 05:42:13 PM UTC 24 |
5649753182 ps |
| T1498 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/17.xbar_error_and_unmapped_addr.507444812 |
|
|
Sep 04 05:41:45 PM UTC 24 |
Sep 04 05:42:15 PM UTC 24 |
484960179 ps |
| T847 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/15.xbar_stress_all.2336298663 |
|
|
Sep 04 05:36:35 PM UTC 24 |
Sep 04 05:42:27 PM UTC 24 |
9422226278 ps |
| T834 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/17.xbar_access_same_device.3316810335 |
|
|
Sep 04 05:41:25 PM UTC 24 |
Sep 04 05:42:28 PM UTC 24 |
516621356 ps |
| T1499 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/17.xbar_stress_all.3921429794 |
|
|
Sep 04 05:42:07 PM UTC 24 |
Sep 04 05:42:31 PM UTC 24 |
314502127 ps |
| T1500 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/16.xbar_stress_all_with_error.315639390 |
|
|
Sep 04 05:40:00 PM UTC 24 |
Sep 04 05:42:40 PM UTC 24 |
4167054764 ps |
| T399 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/2.chip_same_csr_outstanding.195370817 |
|
|
Sep 04 05:03:21 PM UTC 24 |
Sep 04 05:42:43 PM UTC 24 |
15986309887 ps |
| T1501 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/17.xbar_same_source.2653054137 |
|
|
Sep 04 05:41:30 PM UTC 24 |
Sep 04 05:42:45 PM UTC 24 |
2373996737 ps |
| T823 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/14.xbar_stress_all_with_error.1062119156 |
|
|
Sep 04 05:33:59 PM UTC 24 |
Sep 04 05:42:49 PM UTC 24 |
13164159936 ps |
| T802 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/13.xbar_stress_all_with_rand_reset.3389411728 |
|
|
Sep 04 05:31:38 PM UTC 24 |
Sep 04 05:42:52 PM UTC 24 |
4475119242 ps |
| T1502 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/18.xbar_smoke.3601283855 |
|
|
Sep 04 05:42:43 PM UTC 24 |
Sep 04 05:42:53 PM UTC 24 |
42924111 ps |
| T642 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/17.chip_tl_errors.1552571213 |
|
|
Sep 04 05:40:30 PM UTC 24 |
Sep 04 05:42:57 PM UTC 24 |
3505170586 ps |
| T455 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/17.xbar_random_large_delays.774336923 |
|
|
Sep 04 05:41:13 PM UTC 24 |
Sep 04 05:43:02 PM UTC 24 |
11839976463 ps |
| T1503 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/18.xbar_smoke_zero_delays.4112856986 |
|
|
Sep 04 05:42:57 PM UTC 24 |
Sep 04 05:43:06 PM UTC 24 |
45840982 ps |
| T1504 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/17.xbar_error_random.3894780294 |
|
|
Sep 04 05:41:34 PM UTC 24 |
Sep 04 05:43:14 PM UTC 24 |
2441359904 ps |
| T1505 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/17.xbar_stress_all_with_error.719547032 |
|
|
Sep 04 05:42:27 PM UTC 24 |
Sep 04 05:43:17 PM UTC 24 |
1432497127 ps |
| T388 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/6.chip_same_csr_outstanding.2504879298 |
|
|
Sep 04 05:13:12 PM UTC 24 |
Sep 04 05:43:24 PM UTC 24 |
16908625747 ps |
| T1506 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/18.xbar_random_zero_delays.2237235242 |
|
|
Sep 04 05:43:13 PM UTC 24 |
Sep 04 05:43:25 PM UTC 24 |
95690178 ps |
| T856 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/18.xbar_access_same_device.1141541312 |
|
|
Sep 04 05:43:23 PM UTC 24 |
Sep 04 05:43:40 PM UTC 24 |
210186349 ps |
| T1507 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/18.xbar_unmapped_addr.1947999438 |
|
|
Sep 04 05:43:33 PM UTC 24 |
Sep 04 05:43:43 PM UTC 24 |
76376889 ps |
| T1508 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/12.chip_csr_mem_rw_with_rand_reset.3669990173 |
|
|
Sep 04 05:30:11 PM UTC 24 |
Sep 04 05:43:50 PM UTC 24 |
11511311882 ps |
| T1509 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/18.xbar_error_random.1372952545 |
|
|
Sep 04 05:43:29 PM UTC 24 |
Sep 04 05:44:00 PM UTC 24 |
335022656 ps |
| T1510 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/18.xbar_random.2680222330 |
|
|
Sep 04 05:43:10 PM UTC 24 |
Sep 04 05:44:15 PM UTC 24 |
1979371673 ps |
| T1511 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/18.xbar_same_source.441758279 |
|
|
Sep 04 05:43:28 PM UTC 24 |
Sep 04 05:44:23 PM UTC 24 |
1404437223 ps |
| T1512 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/18.xbar_error_and_unmapped_addr.824269695 |
|
|
Sep 04 05:43:39 PM UTC 24 |
Sep 04 05:44:23 PM UTC 24 |
957941033 ps |
| T1513 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/15.chip_csr_mem_rw_with_rand_reset.961085960 |
|
|
Sep 04 05:37:00 PM UTC 24 |
Sep 04 05:44:41 PM UTC 24 |
6977731989 ps |
| T1514 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/18.xbar_smoke_slow_rsp.3979775444 |
|
|
Sep 04 05:43:00 PM UTC 24 |
Sep 04 05:44:45 PM UTC 24 |
4584585528 ps |
| T1515 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/18.xbar_smoke_large_delays.2947137886 |
|
|
Sep 04 05:42:54 PM UTC 24 |
Sep 04 05:44:50 PM UTC 24 |
9590489792 ps |
| T1516 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/19.xbar_smoke_zero_delays.140329315 |
|
|
Sep 04 05:44:49 PM UTC 24 |
Sep 04 05:44:59 PM UTC 24 |
47525784 ps |
| T476 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/14.xbar_random_large_delays.632757059 |
|
|
Sep 04 05:32:42 PM UTC 24 |
Sep 04 05:45:00 PM UTC 24 |
54989592049 ps |
| T858 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/17.xbar_stress_all_with_rand_reset.872756920 |
|
|
Sep 04 05:42:24 PM UTC 24 |
Sep 04 05:45:05 PM UTC 24 |
328387137 ps |
| T1517 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/19.xbar_smoke.2868013749 |
|
|
Sep 04 05:44:54 PM UTC 24 |
Sep 04 05:45:07 PM UTC 24 |
202181488 ps |
| T1518 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/18.xbar_stress_all_with_reset_error.1068261140 |
|
|
Sep 04 05:44:11 PM UTC 24 |
Sep 04 05:45:19 PM UTC 24 |
310564664 ps |
| T1519 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/12.xbar_random_slow_rsp.3174863197 |
|
|
Sep 04 05:28:55 PM UTC 24 |
Sep 04 05:45:21 PM UTC 24 |
53932009307 ps |
| T788 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/14.xbar_access_same_device_slow_rsp.4163647009 |
|
|
Sep 04 05:33:02 PM UTC 24 |
Sep 04 05:45:22 PM UTC 24 |
42767978596 ps |
| T400 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/5.chip_same_csr_outstanding.1909102627 |
|
|
Sep 04 05:10:46 PM UTC 24 |
Sep 04 05:45:28 PM UTC 24 |
17638528713 ps |
| T864 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/17.xbar_stress_all_with_reset_error.4164733905 |
|
|
Sep 04 05:42:31 PM UTC 24 |
Sep 04 05:45:30 PM UTC 24 |
2976290828 ps |
| T791 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/6.xbar_access_same_device_slow_rsp.3399451232 |
|
|
Sep 04 05:14:09 PM UTC 24 |
Sep 04 05:45:44 PM UTC 24 |
118471417117 ps |
| T1520 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/15.xbar_random_large_delays.2502599328 |
|
|
Sep 04 05:35:18 PM UTC 24 |
Sep 04 05:45:47 PM UTC 24 |
59589109168 ps |
| T1521 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/19.xbar_random_zero_delays.1003479020 |
|
|
Sep 04 05:45:29 PM UTC 24 |
Sep 04 05:45:50 PM UTC 24 |
121961211 ps |
| T578 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/18.chip_tl_errors.201156925 |
|
|
Sep 04 05:42:43 PM UTC 24 |
Sep 04 05:45:51 PM UTC 24 |
3794040848 ps |
| T1522 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/19.xbar_same_source.1544365033 |
|
|
Sep 04 05:45:51 PM UTC 24 |
Sep 04 05:46:05 PM UTC 24 |
86241362 ps |
| T1523 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/19.xbar_error_and_unmapped_addr.4109179565 |
|
|
Sep 04 05:46:02 PM UTC 24 |
Sep 04 05:46:21 PM UTC 24 |
134490090 ps |
| T1524 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/19.xbar_unmapped_addr.1322317268 |
|
|
Sep 04 05:45:58 PM UTC 24 |
Sep 04 05:46:31 PM UTC 24 |
469191115 ps |
| T1525 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/19.xbar_error_random.4074043844 |
|
|
Sep 04 05:45:50 PM UTC 24 |
Sep 04 05:46:38 PM UTC 24 |
384101852 ps |
| T1526 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/19.xbar_access_same_device.3028926126 |
|
|
Sep 04 05:45:38 PM UTC 24 |
Sep 04 05:46:40 PM UTC 24 |
1087992459 ps |
| T1527 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/19.xbar_random.3364594819 |
|
|
Sep 04 05:45:19 PM UTC 24 |
Sep 04 05:46:47 PM UTC 24 |
2397321524 ps |
| T835 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/16.xbar_access_same_device_slow_rsp.1045882495 |
|
|
Sep 04 05:38:59 PM UTC 24 |
Sep 04 05:46:54 PM UTC 24 |
23335942707 ps |
| T1528 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/19.xbar_smoke_large_delays.4062667108 |
|
|
Sep 04 05:45:10 PM UTC 24 |
Sep 04 05:47:05 PM UTC 24 |
6825741079 ps |
| T1529 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/19.xbar_random_large_delays.3803356195 |
|
|
Sep 04 05:45:31 PM UTC 24 |
Sep 04 05:47:06 PM UTC 24 |
10362935117 ps |
| T1530 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/19.xbar_smoke_slow_rsp.1347819596 |
|
|
Sep 04 05:45:15 PM UTC 24 |
Sep 04 05:47:07 PM UTC 24 |
7250196265 ps |
| T480 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/15.xbar_random_slow_rsp.3825621843 |
|
|
Sep 04 05:35:19 PM UTC 24 |
Sep 04 05:47:07 PM UTC 24 |
46193626516 ps |
| T1531 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/18.xbar_stress_all.2942462397 |
|
|
Sep 04 05:43:48 PM UTC 24 |
Sep 04 05:47:11 PM UTC 24 |
5023302234 ps |
| T1532 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/20.xbar_smoke_zero_delays.3309768580 |
|
|
Sep 04 05:47:07 PM UTC 24 |
Sep 04 05:47:17 PM UTC 24 |
46000197 ps |
| T1533 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/20.xbar_smoke.1763206162 |
|
|
Sep 04 05:47:09 PM UTC 24 |
Sep 04 05:47:18 PM UTC 24 |
43333393 ps |
| T829 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/12.xbar_stress_all_with_reset_error.934192476 |
|
|
Sep 04 05:30:07 PM UTC 24 |
Sep 04 05:47:21 PM UTC 24 |
19770505781 ps |
| T1534 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/12.xbar_random_large_delays.2167179948 |
|
|
Sep 04 05:28:48 PM UTC 24 |
Sep 04 05:47:32 PM UTC 24 |
104401615890 ps |
| T1535 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/16.xbar_random_slow_rsp.2877283743 |
|
|
Sep 04 05:38:34 PM UTC 24 |
Sep 04 05:47:32 PM UTC 24 |
32217227815 ps |
| T1536 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/13.chip_csr_mem_rw_with_rand_reset.1304392031 |
|
|
Sep 04 05:32:08 PM UTC 24 |
Sep 04 05:47:41 PM UTC 24 |
10025763390 ps |
| T1537 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/17.chip_csr_rw.3508883264 |
|
|
Sep 04 05:42:37 PM UTC 24 |
Sep 04 05:48:06 PM UTC 24 |
4073208527 ps |
| T860 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/19.xbar_stress_all_with_reset_error.1642790285 |
|
|
Sep 04 05:46:22 PM UTC 24 |
Sep 04 05:48:20 PM UTC 24 |
473080922 ps |
| T519 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/20.xbar_random_zero_delays.245405583 |
|
|
Sep 04 05:47:34 PM UTC 24 |
Sep 04 05:48:20 PM UTC 24 |
518978682 ps |
| T1538 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/20.xbar_unmapped_addr.4154707637 |
|
|
Sep 04 05:47:57 PM UTC 24 |
Sep 04 05:48:29 PM UTC 24 |
306459435 ps |
| T1539 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/20.xbar_smoke_slow_rsp.2127989660 |
|
|
Sep 04 05:47:25 PM UTC 24 |
Sep 04 05:48:32 PM UTC 24 |
4339684153 ps |
| T473 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/20.xbar_same_source.1207670925 |
|
|
Sep 04 05:47:48 PM UTC 24 |
Sep 04 05:48:35 PM UTC 24 |
1164206681 ps |
| T1540 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/20.xbar_error_random.950527216 |
|
|
Sep 04 05:47:49 PM UTC 24 |
Sep 04 05:48:37 PM UTC 24 |
426381630 ps |
| T573 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/20.chip_tl_errors.1928856695 |
|
|
Sep 04 05:47:03 PM UTC 24 |
Sep 04 05:48:43 PM UTC 24 |
2396347395 ps |
| T1541 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/20.xbar_smoke_large_delays.841632953 |
|
|
Sep 04 05:47:16 PM UTC 24 |
Sep 04 05:48:48 PM UTC 24 |
8337722996 ps |
| T851 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/20.xbar_access_same_device.3449038951 |
|
|
Sep 04 05:47:41 PM UTC 24 |
Sep 04 05:48:52 PM UTC 24 |
973268674 ps |
| T1542 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/20.xbar_random.3089166788 |
|
|
Sep 04 05:47:32 PM UTC 24 |
Sep 04 05:48:52 PM UTC 24 |
1919534526 ps |
| T1543 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/20.xbar_error_and_unmapped_addr.398203336 |
|
|
Sep 04 05:48:00 PM UTC 24 |
Sep 04 05:49:03 PM UTC 24 |
1094251477 ps |
| T1544 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/21.xbar_smoke.2064331326 |
|
|
Sep 04 05:49:03 PM UTC 24 |
Sep 04 05:49:13 PM UTC 24 |
191609920 ps |
| T1545 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/21.xbar_smoke_zero_delays.2948978793 |
|
|
Sep 04 05:49:03 PM UTC 24 |
Sep 04 05:49:13 PM UTC 24 |
46489860 ps |
| T1546 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/19.xbar_stress_all_with_error.2043989631 |
|
|
Sep 04 05:46:19 PM UTC 24 |
Sep 04 05:49:21 PM UTC 24 |
5463041852 ps |
| T1547 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/16.chip_csr_rw.1446335148 |
|
|
Sep 04 05:40:03 PM UTC 24 |
Sep 04 05:49:30 PM UTC 24 |
6072989902 ps |
| T830 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/5.xbar_access_same_device_slow_rsp.669001299 |
|
|
Sep 04 05:11:39 PM UTC 24 |
Sep 04 05:49:31 PM UTC 24 |
139055649573 ps |
| T792 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/18.xbar_access_same_device_slow_rsp.113070855 |
|
|
Sep 04 05:43:24 PM UTC 24 |
Sep 04 05:49:32 PM UTC 24 |
24179910745 ps |
| T1548 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/15.chip_csr_rw.954776833 |
|
|
Sep 04 05:36:56 PM UTC 24 |
Sep 04 05:49:47 PM UTC 24 |
5663234158 ps |
| T1549 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/21.xbar_random_zero_delays.4162677647 |
|
|
Sep 04 05:49:21 PM UTC 24 |
Sep 04 05:49:52 PM UTC 24 |
273546587 ps |
| T1550 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/20.xbar_stress_all_with_error.3541077912 |
|
|
Sep 04 05:48:50 PM UTC 24 |
Sep 04 05:50:01 PM UTC 24 |
498756976 ps |
| T1551 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/21.xbar_same_source.1602117247 |
|
|
Sep 04 05:49:52 PM UTC 24 |
Sep 04 05:50:04 PM UTC 24 |
278915125 ps |
| T1552 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/14.chip_csr_mem_rw_with_rand_reset.1405668653 |
|
|
Sep 04 05:34:24 PM UTC 24 |
Sep 04 05:50:18 PM UTC 24 |
8718455700 ps |
| T817 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/21.xbar_access_same_device.1905303643 |
|
|
Sep 04 05:49:39 PM UTC 24 |
Sep 04 05:50:26 PM UTC 24 |
1312268758 ps |
| T1553 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/21.xbar_error_and_unmapped_addr.1646605166 |
|
|
Sep 04 05:50:01 PM UTC 24 |
Sep 04 05:50:26 PM UTC 24 |
256806222 ps |
| T1554 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/18.chip_csr_rw.1159836314 |
|
|
Sep 04 05:44:13 PM UTC 24 |
Sep 04 05:50:29 PM UTC 24 |
3466568836 ps |
| T1555 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/21.xbar_smoke_slow_rsp.1871428609 |
|
|
Sep 04 05:49:11 PM UTC 24 |
Sep 04 05:50:34 PM UTC 24 |
5927100388 ps |
| T1556 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/21.xbar_smoke_large_delays.1234783266 |
|
|
Sep 04 05:49:04 PM UTC 24 |
Sep 04 05:50:46 PM UTC 24 |
7571124295 ps |
| T1557 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/21.xbar_unmapped_addr.2173932636 |
|
|
Sep 04 05:50:01 PM UTC 24 |
Sep 04 05:50:53 PM UTC 24 |
1061058304 ps |
| T793 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/18.xbar_stress_all_with_error.1922891857 |
|
|
Sep 04 05:43:56 PM UTC 24 |
Sep 04 05:51:00 PM UTC 24 |
13673540195 ps |
| T1558 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/22.xbar_smoke_zero_delays.404739556 |
|
|
Sep 04 05:50:55 PM UTC 24 |
Sep 04 05:51:03 PM UTC 24 |
51373474 ps |
| T1559 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/21.xbar_error_random.1307746868 |
|
|
Sep 04 05:49:58 PM UTC 24 |
Sep 04 05:51:06 PM UTC 24 |
2064432618 ps |
| T1560 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/22.xbar_smoke.475626087 |
|
|
Sep 04 05:50:56 PM UTC 24 |
Sep 04 05:51:10 PM UTC 24 |
212661991 ps |
| T1561 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/21.xbar_random.2343639677 |
|
|
Sep 04 05:49:14 PM UTC 24 |
Sep 04 05:51:17 PM UTC 24 |
2544836176 ps |
| T1562 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/21.xbar_stress_all_with_reset_error.2278898922 |
|
|
Sep 04 05:50:34 PM UTC 24 |
Sep 04 05:51:30 PM UTC 24 |
105218147 ps |
| T1563 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/22.xbar_random_zero_delays.1230073858 |
|
|
Sep 04 05:51:19 PM UTC 24 |
Sep 04 05:51:51 PM UTC 24 |
263806820 ps |
| T1564 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/22.xbar_random.602558235 |
|
|
Sep 04 05:51:12 PM UTC 24 |
Sep 04 05:51:51 PM UTC 24 |
1028163014 ps |
| T461 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/20.xbar_stress_all.373252762 |
|
|
Sep 04 05:48:12 PM UTC 24 |
Sep 04 05:52:05 PM UTC 24 |
3001676703 ps |
| T1565 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/22.xbar_smoke_large_delays.2183627817 |
|
|
Sep 04 05:51:00 PM UTC 24 |
Sep 04 05:52:18 PM UTC 24 |
8410943241 ps |
| T1566 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/22.xbar_unmapped_addr.1735371127 |
|
|
Sep 04 05:52:21 PM UTC 24 |
Sep 04 05:52:29 PM UTC 24 |
91696235 ps |
| T1567 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/22.xbar_same_source.1724308997 |
|
|
Sep 04 05:51:49 PM UTC 24 |
Sep 04 05:52:41 PM UTC 24 |
1197550723 ps |
| T865 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/18.xbar_stress_all_with_rand_reset.1907335644 |
|
|
Sep 04 05:43:56 PM UTC 24 |
Sep 04 05:52:44 PM UTC 24 |
3103851296 ps |
| T493 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/19.xbar_stress_all_with_rand_reset.1236764316 |
|
|
Sep 04 05:46:16 PM UTC 24 |
Sep 04 05:52:47 PM UTC 24 |
2815262823 ps |
| T1568 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/22.xbar_error_and_unmapped_addr.3161183300 |
|
|
Sep 04 05:52:22 PM UTC 24 |
Sep 04 05:53:02 PM UTC 24 |
279774402 ps |
| T1569 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/22.xbar_error_random.660841370 |
|
|
Sep 04 05:52:02 PM UTC 24 |
Sep 04 05:53:04 PM UTC 24 |
590374158 ps |
| T794 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/22.xbar_access_same_device.4104910343 |
|
|
Sep 04 05:51:36 PM UTC 24 |
Sep 04 05:53:08 PM UTC 24 |
1531550042 ps |
| T1570 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/22.xbar_stress_all_with_error.1281004135 |
|
|
Sep 04 05:52:59 PM UTC 24 |
Sep 04 05:53:12 PM UTC 24 |
82732112 ps |
| T1571 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/22.xbar_smoke_slow_rsp.2597660267 |
|
|
Sep 04 05:51:06 PM UTC 24 |
Sep 04 05:53:26 PM UTC 24 |
5931037418 ps |
| T1572 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/20.xbar_stress_all_with_reset_error.3784190258 |
|
|
Sep 04 05:48:50 PM UTC 24 |
Sep 04 05:53:27 PM UTC 24 |
350360428 ps |
| T1573 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/23.xbar_smoke.2938414593 |
|
|
Sep 04 05:53:16 PM UTC 24 |
Sep 04 05:53:31 PM UTC 24 |
241596957 ps |
| T1574 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/23.xbar_smoke_zero_delays.10163491 |
|
|
Sep 04 05:53:26 PM UTC 24 |
Sep 04 05:53:37 PM UTC 24 |
55626149 ps |
| T456 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/19.xbar_stress_all.2769163112 |
|
|
Sep 04 05:46:13 PM UTC 24 |
Sep 04 05:54:06 PM UTC 24 |
5263373266 ps |
| T618 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/19.chip_tl_errors.1752627630 |
|
|
Sep 04 05:44:46 PM UTC 24 |
Sep 04 05:54:09 PM UTC 24 |
5448718188 ps |
| T811 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/21.xbar_stress_all.2988187297 |
|
|
Sep 04 05:50:18 PM UTC 24 |
Sep 04 05:54:17 PM UTC 24 |
2002468570 ps |
| T1575 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/16.chip_csr_mem_rw_with_rand_reset.1602573625 |
|
|
Sep 04 05:40:07 PM UTC 24 |
Sep 04 05:54:17 PM UTC 24 |
11458452575 ps |
| T1576 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/20.xbar_random_large_delays.840414614 |
|
|
Sep 04 05:47:36 PM UTC 24 |
Sep 04 05:54:18 PM UTC 24 |
38815741730 ps |
| T1577 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/23.xbar_random.3788533114 |
|
|
Sep 04 05:53:41 PM UTC 24 |
Sep 04 05:54:25 PM UTC 24 |
1015046423 ps |
| T646 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/21.chip_tl_errors.2070273358 |
|
|
Sep 04 05:49:00 PM UTC 24 |
Sep 04 05:54:26 PM UTC 24 |
4690421792 ps |
| T1578 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/23.xbar_random_zero_delays.222502608 |
|
|
Sep 04 05:53:56 PM UTC 24 |
Sep 04 05:54:32 PM UTC 24 |
277197721 ps |
| T1579 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/19.xbar_random_slow_rsp.599556994 |
|
|
Sep 04 05:45:34 PM UTC 24 |
Sep 04 05:54:33 PM UTC 24 |
36858121258 ps |
| T803 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/20.xbar_stress_all_with_rand_reset.1951387795 |
|
|
Sep 04 05:48:37 PM UTC 24 |
Sep 04 05:54:34 PM UTC 24 |
5131390151 ps |
| T857 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/23.xbar_access_same_device.395580725 |
|
|
Sep 04 05:54:08 PM UTC 24 |
Sep 04 05:54:48 PM UTC 24 |
742333975 ps |
| T800 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/9.xbar_access_same_device_slow_rsp.2488620543 |
|
|
Sep 04 05:22:18 PM UTC 24 |
Sep 04 05:54:49 PM UTC 24 |
116571473266 ps |
| T1580 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/22.xbar_stress_all_with_rand_reset.161550236 |
|
|
Sep 04 05:52:47 PM UTC 24 |
Sep 04 05:54:52 PM UTC 24 |
172948442 ps |
| T1581 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/23.xbar_smoke_slow_rsp.4037499613 |
|
|
Sep 04 05:53:39 PM UTC 24 |
Sep 04 05:54:54 PM UTC 24 |
3884607014 ps |
| T499 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/18.xbar_random_large_delays.520397038 |
|
|
Sep 04 05:43:15 PM UTC 24 |
Sep 04 05:55:00 PM UTC 24 |
63592411492 ps |
| T1582 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/23.xbar_error_and_unmapped_addr.2772335515 |
|
|
Sep 04 05:54:48 PM UTC 24 |
Sep 04 05:55:03 PM UTC 24 |
182471291 ps |
| T1583 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/23.xbar_same_source.2434358276 |
|
|
Sep 04 05:54:39 PM UTC 24 |
Sep 04 05:55:04 PM UTC 24 |
636960140 ps |
| T579 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/22.chip_tl_errors.1799804202 |
|
|
Sep 04 05:50:48 PM UTC 24 |
Sep 04 05:55:06 PM UTC 24 |
3918012445 ps |
| T885 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/21.xbar_stress_all_with_rand_reset.3420009717 |
|
|
Sep 04 05:50:21 PM UTC 24 |
Sep 04 05:55:26 PM UTC 24 |
6887023855 ps |
| T1584 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/24.xbar_smoke_zero_delays.3717828713 |
|
|
Sep 04 05:55:17 PM UTC 24 |
Sep 04 05:55:27 PM UTC 24 |
46937006 ps |
| T1585 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/23.xbar_smoke_large_delays.413559695 |
|
|
Sep 04 05:53:33 PM UTC 24 |
Sep 04 05:55:30 PM UTC 24 |
8969697517 ps |
| T1586 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/24.xbar_smoke.2589215614 |
|
|
Sep 04 05:55:18 PM UTC 24 |
Sep 04 05:55:33 PM UTC 24 |
241669210 ps |