| T1253 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/4.chip_tap_straps_rma.3362443279 |
|
|
Sep 05 12:45:54 AM UTC 24 |
Sep 05 12:48:56 AM UTC 24 |
2659569832 ps |
| T1254 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/4.chip_tap_straps_prod.2197759895 |
|
|
Sep 05 12:46:14 AM UTC 24 |
Sep 05 12:49:26 AM UTC 24 |
2964194048 ps |
| T779 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/4.chip_sw_alert_handler_lpg_sleep_mode_alerts.2020437009 |
|
|
Sep 05 12:44:38 AM UTC 24 |
Sep 05 12:49:45 AM UTC 24 |
3921229640 ps |
| T1255 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/4.chip_sw_uart_tx_rx_idx1.3759295030 |
|
|
Sep 05 12:42:32 AM UTC 24 |
Sep 05 12:50:42 AM UTC 24 |
3844894926 ps |
| T1256 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/3.chip_tap_straps_testunlock0.3861249356 |
|
|
Sep 05 12:37:34 AM UTC 24 |
Sep 05 12:50:45 AM UTC 24 |
6564059210 ps |
| T1257 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/4.chip_tap_straps_testunlock0.441864537 |
|
|
Sep 05 12:45:19 AM UTC 24 |
Sep 05 12:50:50 AM UTC 24 |
3754562349 ps |
| T1258 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/4.chip_sw_uart_tx_rx_idx3.4026600422 |
|
|
Sep 05 12:43:06 AM UTC 24 |
Sep 05 12:51:24 AM UTC 24 |
3914789100 ps |
| T1259 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/4.chip_sw_uart_tx_rx_idx2.2340470267 |
|
|
Sep 05 12:42:23 AM UTC 24 |
Sep 05 12:51:31 AM UTC 24 |
3454972346 ps |
| T665 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/36.chip_sw_all_escalation_resets.2727382050 |
|
|
Sep 05 01:26:48 AM UTC 24 |
Sep 05 01:38:20 AM UTC 24 |
6140129768 ps |
| T1260 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/3.chip_sw_uart_tx_rx_alt_clk_freq_low_speed.3872308082 |
|
|
Sep 05 12:33:18 AM UTC 24 |
Sep 05 12:52:05 AM UTC 24 |
9435590455 ps |
| T1261 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/4.chip_sw_aon_timer_sleep_wdog_sleep_pause.548001058 |
|
|
Sep 05 12:44:30 AM UTC 24 |
Sep 05 12:52:10 AM UTC 24 |
8083045848 ps |
| T1262 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_lc_walkthrough_rma.3348077564 |
|
|
Sep 04 11:17:38 PM UTC 24 |
Sep 05 12:52:53 AM UTC 24 |
48162302380 ps |
| T1263 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/4.chip_sw_uart_rand_baudrate.2410430770 |
|
|
Sep 05 12:43:06 AM UTC 24 |
Sep 05 12:52:59 AM UTC 24 |
4563794390 ps |
| T101 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/4.chip_sw_all_escalation_resets.1082096381 |
|
|
Sep 05 12:42:33 AM UTC 24 |
Sep 05 12:53:01 AM UTC 24 |
4544748292 ps |
| T103 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/4.chip_sw_data_integrity_escalation.341230492 |
|
|
Sep 05 12:42:36 AM UTC 24 |
Sep 05 12:53:46 AM UTC 24 |
5598292782 ps |
| T104 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_flash_init_reduced_freq.2385369020 |
|
|
Sep 05 12:17:00 AM UTC 24 |
Sep 05 12:54:01 AM UTC 24 |
20776292937 ps |
| T105 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/4.chip_sw_uart_tx_rx.1681447380 |
|
|
Sep 05 12:42:18 AM UTC 24 |
Sep 05 12:54:34 AM UTC 24 |
4269623558 ps |
| T106 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/3.chip_sw_sensor_ctrl_alert.3725592478 |
|
|
Sep 05 12:37:15 AM UTC 24 |
Sep 05 12:54:37 AM UTC 24 |
8114184870 ps |
| T107 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/5.chip_sw_alert_handler_lpg_sleep_mode_alerts.573646685 |
|
|
Sep 05 12:48:19 AM UTC 24 |
Sep 05 12:55:04 AM UTC 24 |
3540613078 ps |
| T108 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/5.chip_sw_all_escalation_resets.1993407175 |
|
|
Sep 05 12:46:41 AM UTC 24 |
Sep 05 12:56:11 AM UTC 24 |
4218783268 ps |
| T109 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/4.chip_sw_uart_tx_rx_alt_clk_freq.2473747160 |
|
|
Sep 05 12:44:36 AM UTC 24 |
Sep 05 01:01:22 AM UTC 24 |
4545242737 ps |
| T110 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/5.chip_sw_uart_rand_baudrate.1603579094 |
|
|
Sep 05 12:46:46 AM UTC 24 |
Sep 05 01:01:22 AM UTC 24 |
4129093040 ps |
| T111 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_csrng_edn_concurrency.2089682949 |
|
|
Sep 04 11:44:02 PM UTC 24 |
Sep 05 01:01:22 AM UTC 24 |
17406466424 ps |
| T375 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/6.chip_sw_all_escalation_resets.935493856 |
|
|
Sep 05 12:49:46 AM UTC 24 |
Sep 05 01:01:22 AM UTC 24 |
4362189142 ps |
| T762 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/6.chip_sw_alert_handler_lpg_sleep_mode_alerts.2352657862 |
|
|
Sep 05 12:51:55 AM UTC 24 |
Sep 05 01:01:22 AM UTC 24 |
3682625920 ps |
| T1264 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/5.chip_sw_data_integrity_escalation.700222231 |
|
|
Sep 05 12:46:46 AM UTC 24 |
Sep 05 01:01:22 AM UTC 24 |
5600295434 ps |
| T369 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_uart_tx_rx_bootstrap.312998374 |
|
|
Sep 04 07:36:06 PM UTC 24 |
Sep 05 01:01:22 AM UTC 24 |
79797420818 ps |
| T1265 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/3.chip_sw_uart_tx_rx_alt_clk_freq.432332718 |
|
|
Sep 05 12:33:11 AM UTC 24 |
Sep 05 01:01:22 AM UTC 24 |
8823256973 ps |
| T1266 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/5.chip_sw_lc_ctrl_transition.3645694782 |
|
|
Sep 05 12:47:16 AM UTC 24 |
Sep 05 01:01:22 AM UTC 24 |
9283639546 ps |
| T1267 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/3.chip_sw_uart_rand_baudrate.3609519864 |
|
|
Sep 05 12:33:19 AM UTC 24 |
Sep 05 01:01:22 AM UTC 24 |
8601913068 ps |
| T1268 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/4.chip_sw_sensor_ctrl_alert.1227362926 |
|
|
Sep 05 12:45:00 AM UTC 24 |
Sep 05 01:01:22 AM UTC 24 |
8222232648 ps |
| T1269 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/7.chip_sw_uart_rand_baudrate.2533761509 |
|
|
Sep 05 12:52:23 AM UTC 24 |
Sep 05 01:01:22 AM UTC 24 |
3367758472 ps |
| T1270 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/6.chip_sw_uart_rand_baudrate.1480902474 |
|
|
Sep 05 12:50:13 AM UTC 24 |
Sep 05 01:01:22 AM UTC 24 |
4073519618 ps |
| T1271 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/4.chip_sw_lc_ctrl_transition.4265050770 |
|
|
Sep 05 12:44:38 AM UTC 24 |
Sep 05 01:01:25 AM UTC 24 |
11415676274 ps |
| T670 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/7.chip_sw_all_escalation_resets.270619178 |
|
|
Sep 05 12:52:10 AM UTC 24 |
Sep 05 01:01:49 AM UTC 24 |
5370824100 ps |
| T708 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/8.chip_sw_alert_handler_lpg_sleep_mode_alerts.2764498965 |
|
|
Sep 05 12:54:44 AM UTC 24 |
Sep 05 01:01:50 AM UTC 24 |
3790897642 ps |
| T1272 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/8.chip_sw_lc_ctrl_transition.3040142503 |
|
|
Sep 05 12:54:03 AM UTC 24 |
Sep 05 01:02:02 AM UTC 24 |
7805294674 ps |
| T694 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/7.chip_sw_alert_handler_lpg_sleep_mode_alerts.119514376 |
|
|
Sep 05 12:53:05 AM UTC 24 |
Sep 05 01:02:08 AM UTC 24 |
4339153276 ps |
| T1273 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_lc_walkthrough_dev.521435317 |
|
|
Sep 04 11:14:26 PM UTC 24 |
Sep 05 01:03:00 AM UTC 24 |
47666116520 ps |
| T1274 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_lc_walkthrough_prod.134413913 |
|
|
Sep 04 11:14:30 PM UTC 24 |
Sep 05 01:03:33 AM UTC 24 |
47966865242 ps |
| T1275 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/4.chip_sw_uart_tx_rx_alt_clk_freq_low_speed.3397660082 |
|
|
Sep 05 12:44:26 AM UTC 24 |
Sep 05 01:04:31 AM UTC 24 |
9344758670 ps |
| T1276 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/1.rom_e2e_self_hash.2008679324 |
|
|
Sep 04 10:51:01 PM UTC 24 |
Sep 05 01:04:37 AM UTC 24 |
27253114292 ps |
| T1277 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/8.chip_sw_all_escalation_resets.3254695094 |
|
|
Sep 05 12:54:07 AM UTC 24 |
Sep 05 01:04:58 AM UTC 24 |
5795850234 ps |
| T1278 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/7.chip_sw_lc_ctrl_transition.753757306 |
|
|
Sep 05 12:52:26 AM UTC 24 |
Sep 05 01:06:40 AM UTC 24 |
12132426822 ps |
| T1279 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/6.chip_sw_lc_ctrl_transition.1974501697 |
|
|
Sep 05 12:50:30 AM UTC 24 |
Sep 05 01:08:27 AM UTC 24 |
11842452512 ps |
| T627 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/3.chip_tap_straps_dev.2670999556 |
|
|
Sep 05 12:37:13 AM UTC 24 |
Sep 05 01:09:19 AM UTC 24 |
19521639822 ps |
| T709 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/9.chip_sw_all_escalation_resets.2308303498 |
|
|
Sep 05 12:55:32 AM UTC 24 |
Sep 05 01:11:00 AM UTC 24 |
4915975608 ps |
| T1280 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/2.rom_e2e_asm_init_test_unlocked0.3566834597 |
|
|
Sep 05 12:19:54 AM UTC 24 |
Sep 05 01:11:07 AM UTC 24 |
11576582392 ps |
| T1281 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/12.chip_sw_lc_ctrl_transition.1778311890 |
|
|
Sep 05 01:05:01 AM UTC 24 |
Sep 05 01:11:17 AM UTC 24 |
6834365708 ps |
| T689 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/13.chip_sw_alert_handler_lpg_sleep_mode_alerts.2998032396 |
|
|
Sep 05 01:04:44 AM UTC 24 |
Sep 05 01:11:48 AM UTC 24 |
3812523320 ps |
| T699 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/11.chip_sw_alert_handler_lpg_sleep_mode_alerts.79810038 |
|
|
Sep 05 01:04:16 AM UTC 24 |
Sep 05 01:12:00 AM UTC 24 |
3816501624 ps |
| T774 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/10.chip_sw_all_escalation_resets.802020065 |
|
|
Sep 05 01:03:52 AM UTC 24 |
Sep 05 01:12:09 AM UTC 24 |
5291091760 ps |
| T759 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/12.chip_sw_alert_handler_lpg_sleep_mode_alerts.3476135483 |
|
|
Sep 05 01:05:58 AM UTC 24 |
Sep 05 01:12:29 AM UTC 24 |
3983627824 ps |
| T748 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/10.chip_sw_alert_handler_lpg_sleep_mode_alerts.2240304015 |
|
|
Sep 05 01:06:04 AM UTC 24 |
Sep 05 01:13:07 AM UTC 24 |
4255203096 ps |
| T1282 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/11.chip_sw_lc_ctrl_transition.742101789 |
|
|
Sep 05 01:05:45 AM UTC 24 |
Sep 05 01:13:15 AM UTC 24 |
6317994045 ps |
| T1283 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/9.chip_sw_lc_ctrl_transition.2135812773 |
|
|
Sep 05 12:55:50 AM UTC 24 |
Sep 05 01:13:18 AM UTC 24 |
9268439237 ps |
| T700 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/14.chip_sw_all_escalation_resets.3587136502 |
|
|
Sep 05 01:05:04 AM UTC 24 |
Sep 05 01:14:14 AM UTC 24 |
5365305256 ps |
| T727 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/14.chip_sw_alert_handler_lpg_sleep_mode_alerts.3349401210 |
|
|
Sep 05 01:05:48 AM UTC 24 |
Sep 05 01:14:31 AM UTC 24 |
4252737640 ps |
| T1284 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/10.chip_sw_uart_rand_baudrate.663101745 |
|
|
Sep 05 01:04:00 AM UTC 24 |
Sep 05 01:14:40 AM UTC 24 |
4982916734 ps |
| T1285 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/14.chip_sw_uart_rand_baudrate.2516619465 |
|
|
Sep 05 01:05:41 AM UTC 24 |
Sep 05 01:14:43 AM UTC 24 |
3404730996 ps |
| T696 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/15.chip_sw_alert_handler_lpg_sleep_mode_alerts.3509218160 |
|
|
Sep 05 01:07:07 AM UTC 24 |
Sep 05 01:15:45 AM UTC 24 |
3851332904 ps |
| T360 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/12.chip_sw_all_escalation_resets.739513040 |
|
|
Sep 05 01:06:07 AM UTC 24 |
Sep 05 01:15:58 AM UTC 24 |
6073420200 ps |
| T780 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/16.chip_sw_all_escalation_resets.569155997 |
|
|
Sep 05 01:07:27 AM UTC 24 |
Sep 05 01:16:01 AM UTC 24 |
5452260744 ps |
| T1286 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/14.chip_sw_lc_ctrl_transition.1120582220 |
|
|
Sep 05 01:05:52 AM UTC 24 |
Sep 05 01:16:10 AM UTC 24 |
4728487139 ps |
| T702 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/16.chip_sw_alert_handler_lpg_sleep_mode_alerts.2900821717 |
|
|
Sep 05 01:10:17 AM UTC 24 |
Sep 05 01:17:34 AM UTC 24 |
4688375576 ps |
| T170 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_ast_clk_rst_inputs.4243320542 |
|
|
Sep 05 12:20:29 AM UTC 24 |
Sep 05 01:18:25 AM UTC 24 |
21333671932 ps |
| T357 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/11.chip_sw_all_escalation_resets.639359244 |
|
|
Sep 05 01:05:43 AM UTC 24 |
Sep 05 01:18:51 AM UTC 24 |
5143561500 ps |
| T1287 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/4.chip_sw_csrng_edn_concurrency.3011497651 |
|
|
Sep 05 12:44:49 AM UTC 24 |
Sep 05 01:19:22 AM UTC 24 |
8921307450 ps |
| T690 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/17.chip_sw_alert_handler_lpg_sleep_mode_alerts.3238463461 |
|
|
Sep 05 01:12:13 AM UTC 24 |
Sep 05 01:19:29 AM UTC 24 |
3989169600 ps |
| T710 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/13.chip_sw_all_escalation_resets.3369138155 |
|
|
Sep 05 01:05:59 AM UTC 24 |
Sep 05 01:19:39 AM UTC 24 |
5444964490 ps |
| T744 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/18.chip_sw_alert_handler_lpg_sleep_mode_alerts.2572034087 |
|
|
Sep 05 01:13:09 AM UTC 24 |
Sep 05 01:20:35 AM UTC 24 |
3544623860 ps |
| T697 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/17.chip_sw_all_escalation_resets.2170889501 |
|
|
Sep 05 01:10:20 AM UTC 24 |
Sep 05 01:20:46 AM UTC 24 |
5334482888 ps |
| T1288 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/17.chip_sw_uart_rand_baudrate.2645743835 |
|
|
Sep 05 01:12:15 AM UTC 24 |
Sep 05 01:20:48 AM UTC 24 |
4158889572 ps |
| T781 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/20.chip_sw_alert_handler_lpg_sleep_mode_alerts.2171151054 |
|
|
Sep 05 01:14:30 AM UTC 24 |
Sep 05 01:21:17 AM UTC 24 |
3940911800 ps |
| T265 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/22.chip_sw_alert_handler_lpg_sleep_mode_alerts.2589803662 |
|
|
Sep 05 01:15:46 AM UTC 24 |
Sep 05 01:22:31 AM UTC 24 |
4348806444 ps |
| T296 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/13.chip_sw_lc_ctrl_transition.4280199610 |
|
|
Sep 05 01:06:03 AM UTC 24 |
Sep 05 01:22:36 AM UTC 24 |
11124228734 ps |
| T297 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/21.chip_sw_alert_handler_lpg_sleep_mode_alerts.837963268 |
|
|
Sep 05 01:14:56 AM UTC 24 |
Sep 05 01:22:45 AM UTC 24 |
4363434700 ps |
| T298 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/19.chip_sw_all_escalation_resets.263509484 |
|
|
Sep 05 01:12:59 AM UTC 24 |
Sep 05 01:22:50 AM UTC 24 |
4827373752 ps |
| T299 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/19.chip_sw_alert_handler_lpg_sleep_mode_alerts.1688838205 |
|
|
Sep 05 01:14:27 AM UTC 24 |
Sep 05 01:22:55 AM UTC 24 |
3607655064 ps |
| T276 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/21.chip_sw_all_escalation_resets.1710621770 |
|
|
Sep 05 01:14:27 AM UTC 24 |
Sep 05 01:22:58 AM UTC 24 |
4924979348 ps |
| T300 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/18.chip_sw_all_escalation_resets.3344196941 |
|
|
Sep 05 01:12:15 AM UTC 24 |
Sep 05 01:23:39 AM UTC 24 |
5789252310 ps |
| T301 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/2.rom_e2e_shutdown_exception_c.4036846156 |
|
|
Sep 05 12:20:25 AM UTC 24 |
Sep 05 01:23:51 AM UTC 24 |
14253702393 ps |
| T302 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/24.chip_sw_alert_handler_lpg_sleep_mode_alerts.3238197065 |
|
|
Sep 05 01:17:17 AM UTC 24 |
Sep 05 01:24:21 AM UTC 24 |
4249879690 ps |
| T303 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/22.chip_sw_all_escalation_resets.2597054871 |
|
|
Sep 05 01:15:43 AM UTC 24 |
Sep 05 01:24:47 AM UTC 24 |
4996433920 ps |
| T330 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/25.chip_sw_alert_handler_lpg_sleep_mode_alerts.340563839 |
|
|
Sep 05 01:18:21 AM UTC 24 |
Sep 05 01:24:54 AM UTC 24 |
3909671920 ps |
| T1289 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq.2280316199 |
|
|
Sep 05 12:12:44 AM UTC 24 |
Sep 05 01:25:02 AM UTC 24 |
25320477070 ps |
| T731 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/23.chip_sw_all_escalation_resets.1858982010 |
|
|
Sep 05 01:15:43 AM UTC 24 |
Sep 05 01:25:07 AM UTC 24 |
5674007900 ps |
| T666 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/23.chip_sw_alert_handler_lpg_sleep_mode_alerts.3679650508 |
|
|
Sep 05 01:17:11 AM UTC 24 |
Sep 05 01:25:10 AM UTC 24 |
3901688302 ps |
| T1290 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/10.chip_sw_lc_ctrl_transition.3595386436 |
|
|
Sep 05 01:06:08 AM UTC 24 |
Sep 05 01:25:15 AM UTC 24 |
10772413106 ps |
| T663 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/20.chip_sw_all_escalation_resets.393056169 |
|
|
Sep 05 01:14:31 AM UTC 24 |
Sep 05 01:25:15 AM UTC 24 |
4796950246 ps |
| T1291 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/2.rom_e2e_keymgr_init_rom_ext_meas.1124180338 |
|
|
Sep 05 12:20:16 AM UTC 24 |
Sep 05 01:26:34 AM UTC 24 |
15087800452 ps |
| T664 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/24.chip_sw_all_escalation_resets.151829111 |
|
|
Sep 05 01:17:15 AM UTC 24 |
Sep 05 01:26:49 AM UTC 24 |
6026977036 ps |
| T1292 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/2.rom_e2e_smoke.511528722 |
|
|
Sep 05 12:19:04 AM UTC 24 |
Sep 05 01:26:51 AM UTC 24 |
15248463404 ps |
| T1293 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/2.rom_e2e_asm_init_rma.923384717 |
|
|
Sep 05 12:20:38 AM UTC 24 |
Sep 05 01:27:00 AM UTC 24 |
15151522413 ps |
| T1294 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/2.rom_e2e_keymgr_init_rom_ext_invalid_meas.1458347526 |
|
|
Sep 05 12:20:28 AM UTC 24 |
Sep 05 01:27:08 AM UTC 24 |
14936789396 ps |
| T331 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/26.chip_sw_alert_handler_lpg_sleep_mode_alerts.607966380 |
|
|
Sep 05 01:19:38 AM UTC 24 |
Sep 05 01:27:14 AM UTC 24 |
3733808948 ps |
| T667 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/28.chip_sw_alert_handler_lpg_sleep_mode_alerts.1984761430 |
|
|
Sep 05 01:20:48 AM UTC 24 |
Sep 05 01:27:32 AM UTC 24 |
3686599380 ps |
| T1295 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/2.rom_e2e_shutdown_output.2474786618 |
|
|
Sep 05 12:19:49 AM UTC 24 |
Sep 05 01:27:44 AM UTC 24 |
31038384626 ps |
| T711 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/27.chip_sw_alert_handler_lpg_sleep_mode_alerts.3664842709 |
|
|
Sep 05 01:20:43 AM UTC 24 |
Sep 05 01:27:46 AM UTC 24 |
4279999740 ps |
| T662 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/30.chip_sw_alert_handler_lpg_sleep_mode_alerts.2071140855 |
|
|
Sep 05 01:22:06 AM UTC 24 |
Sep 05 01:28:07 AM UTC 24 |
3359249920 ps |
| T678 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/25.chip_sw_all_escalation_resets.1156239944 |
|
|
Sep 05 01:17:16 AM UTC 24 |
Sep 05 01:28:19 AM UTC 24 |
6158160192 ps |
| T766 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/29.chip_sw_alert_handler_lpg_sleep_mode_alerts.3310795151 |
|
|
Sep 05 01:21:49 AM UTC 24 |
Sep 05 01:28:37 AM UTC 24 |
3711650858 ps |
| T698 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/26.chip_sw_all_escalation_resets.1720559967 |
|
|
Sep 05 01:19:12 AM UTC 24 |
Sep 05 01:28:49 AM UTC 24 |
6465161392 ps |
| T737 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/28.chip_sw_all_escalation_resets.3263652991 |
|
|
Sep 05 01:20:44 AM UTC 24 |
Sep 05 01:29:32 AM UTC 24 |
4623843514 ps |
| T680 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/32.chip_sw_alert_handler_lpg_sleep_mode_alerts.3878317771 |
|
|
Sep 05 01:24:40 AM UTC 24 |
Sep 05 01:29:48 AM UTC 24 |
3814411640 ps |
| T1296 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/2.rom_e2e_asm_init_prod_end.431955851 |
|
|
Sep 05 12:20:31 AM UTC 24 |
Sep 05 01:29:55 AM UTC 24 |
14924453883 ps |
| T682 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/29.chip_sw_all_escalation_resets.3322070682 |
|
|
Sep 05 01:22:03 AM UTC 24 |
Sep 05 01:30:11 AM UTC 24 |
4656823152 ps |
| T1297 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/13.chip_sw_uart_rand_baudrate.2618354303 |
|
|
Sep 05 01:03:51 AM UTC 24 |
Sep 05 01:30:21 AM UTC 24 |
7723925452 ps |
| T732 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/31.chip_sw_alert_handler_lpg_sleep_mode_alerts.3912847789 |
|
|
Sep 05 01:24:49 AM UTC 24 |
Sep 05 01:30:32 AM UTC 24 |
3475924092 ps |
| T717 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/33.chip_sw_alert_handler_lpg_sleep_mode_alerts.2849081881 |
|
|
Sep 05 01:24:50 AM UTC 24 |
Sep 05 01:30:48 AM UTC 24 |
3782238222 ps |
| T1298 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/2.rom_e2e_asm_init_prod.3553464462 |
|
|
Sep 05 12:20:10 AM UTC 24 |
Sep 05 01:30:53 AM UTC 24 |
16293175280 ps |
| T718 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/34.chip_sw_alert_handler_lpg_sleep_mode_alerts.1917529800 |
|
|
Sep 05 01:24:48 AM UTC 24 |
Sep 05 01:31:07 AM UTC 24 |
3844584450 ps |
| T1299 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/2.rom_e2e_keymgr_init_rom_ext_no_meas.841769295 |
|
|
Sep 05 12:20:42 AM UTC 24 |
Sep 05 01:31:13 AM UTC 24 |
15051266144 ps |
| T705 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/30.chip_sw_all_escalation_resets.3673237563 |
|
|
Sep 05 01:21:48 AM UTC 24 |
Sep 05 01:32:00 AM UTC 24 |
4676527020 ps |
| T1300 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/34.chip_sw_all_escalation_resets.17090160 |
|
|
Sep 05 01:24:52 AM UTC 24 |
Sep 05 01:32:11 AM UTC 24 |
5384814988 ps |
| T782 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/35.chip_sw_alert_handler_lpg_sleep_mode_alerts.1001048728 |
|
|
Sep 05 01:26:53 AM UTC 24 |
Sep 05 01:32:11 AM UTC 24 |
3737360712 ps |
| T777 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/38.chip_sw_alert_handler_lpg_sleep_mode_alerts.3927467221 |
|
|
Sep 05 01:26:48 AM UTC 24 |
Sep 05 01:32:12 AM UTC 24 |
3425313532 ps |
| T1301 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/2.rom_e2e_asm_init_dev.2314713152 |
|
|
Sep 05 12:20:49 AM UTC 24 |
Sep 05 01:32:16 AM UTC 24 |
15812053164 ps |
| T1302 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/11.chip_sw_uart_rand_baudrate.1468668971 |
|
|
Sep 05 01:05:49 AM UTC 24 |
Sep 05 01:32:19 AM UTC 24 |
8374610168 ps |
| T763 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/27.chip_sw_all_escalation_resets.3088613974 |
|
|
Sep 05 01:20:42 AM UTC 24 |
Sep 05 01:32:26 AM UTC 24 |
6428215420 ps |
| T734 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/31.chip_sw_all_escalation_resets.3600219617 |
|
|
Sep 05 01:24:00 AM UTC 24 |
Sep 05 01:32:43 AM UTC 24 |
4803750296 ps |
| T745 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/36.chip_sw_alert_handler_lpg_sleep_mode_alerts.2377469661 |
|
|
Sep 05 01:26:54 AM UTC 24 |
Sep 05 01:32:57 AM UTC 24 |
3680132712 ps |
| T721 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/37.chip_sw_alert_handler_lpg_sleep_mode_alerts.2019089695 |
|
|
Sep 05 01:26:51 AM UTC 24 |
Sep 05 01:33:43 AM UTC 24 |
4156330212 ps |
| T1303 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/12.chip_sw_uart_rand_baudrate.893134664 |
|
|
Sep 05 01:06:05 AM UTC 24 |
Sep 05 01:33:43 AM UTC 24 |
8944383340 ps |
| T1304 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/2.rom_e2e_static_critical.3853586605 |
|
|
Sep 05 12:18:55 AM UTC 24 |
Sep 05 01:34:20 AM UTC 24 |
17376465012 ps |
| T746 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/38.chip_sw_all_escalation_resets.3241440931 |
|
|
Sep 05 01:26:41 AM UTC 24 |
Sep 05 01:34:28 AM UTC 24 |
5699768944 ps |
| T1305 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/15.chip_sw_uart_rand_baudrate.1308183980 |
|
|
Sep 05 01:06:04 AM UTC 24 |
Sep 05 01:34:40 AM UTC 24 |
8844190700 ps |
| T756 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/39.chip_sw_alert_handler_lpg_sleep_mode_alerts.1588337604 |
|
|
Sep 05 01:29:06 AM UTC 24 |
Sep 05 01:35:12 AM UTC 24 |
3883034632 ps |
| T1306 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/16.chip_sw_uart_rand_baudrate.4252995858 |
|
|
Sep 05 01:09:13 AM UTC 24 |
Sep 05 01:35:24 AM UTC 24 |
8969782136 ps |
| T749 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/37.chip_sw_all_escalation_resets.1710016299 |
|
|
Sep 05 01:26:43 AM UTC 24 |
Sep 05 01:35:31 AM UTC 24 |
4146093460 ps |
| T1307 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/39.chip_sw_all_escalation_resets.2286045072 |
|
|
Sep 05 01:27:32 AM UTC 24 |
Sep 05 01:35:40 AM UTC 24 |
5356922984 ps |
| T712 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/33.chip_sw_all_escalation_resets.4232772541 |
|
|
Sep 05 01:25:05 AM UTC 24 |
Sep 05 01:35:55 AM UTC 24 |
5592559794 ps |
| T722 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/32.chip_sw_all_escalation_resets.329808474 |
|
|
Sep 05 01:24:49 AM UTC 24 |
Sep 05 01:36:13 AM UTC 24 |
4562659418 ps |
| T707 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/40.chip_sw_alert_handler_lpg_sleep_mode_alerts.1402426781 |
|
|
Sep 05 01:30:12 AM UTC 24 |
Sep 05 01:36:14 AM UTC 24 |
3692056640 ps |
| T1308 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/42.chip_sw_alert_handler_lpg_sleep_mode_alerts.853257819 |
|
|
Sep 05 01:29:57 AM UTC 24 |
Sep 05 01:36:20 AM UTC 24 |
4292976584 ps |
| T778 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/44.chip_sw_alert_handler_lpg_sleep_mode_alerts.3404233333 |
|
|
Sep 05 01:29:55 AM UTC 24 |
Sep 05 01:36:26 AM UTC 24 |
4055706576 ps |
| T714 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/35.chip_sw_all_escalation_resets.2028307906 |
|
|
Sep 05 01:25:09 AM UTC 24 |
Sep 05 01:36:40 AM UTC 24 |
5738541688 ps |
| T332 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/45.chip_sw_alert_handler_lpg_sleep_mode_alerts.1080892255 |
|
|
Sep 05 01:30:50 AM UTC 24 |
Sep 05 01:37:09 AM UTC 24 |
4070550512 ps |
| T1309 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/18.chip_sw_uart_rand_baudrate.1193743242 |
|
|
Sep 05 01:12:54 AM UTC 24 |
Sep 05 01:37:11 AM UTC 24 |
8095179788 ps |
| T1310 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/5.chip_sw_csrng_edn_concurrency.3603116453 |
|
|
Sep 05 12:49:42 AM UTC 24 |
Sep 05 01:37:25 AM UTC 24 |
12171000600 ps |
| T684 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/41.chip_sw_alert_handler_lpg_sleep_mode_alerts.295771429 |
|
|
Sep 05 01:29:36 AM UTC 24 |
Sep 05 01:37:26 AM UTC 24 |
3770018582 ps |
| T1311 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/19.chip_sw_uart_rand_baudrate.412858625 |
|
|
Sep 05 01:13:13 AM UTC 24 |
Sep 05 01:38:26 AM UTC 24 |
8793369464 ps |
| T719 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/40.chip_sw_all_escalation_resets.3894760042 |
|
|
Sep 05 01:29:55 AM UTC 24 |
Sep 05 01:38:38 AM UTC 24 |
5291166210 ps |
| T333 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/43.chip_sw_alert_handler_lpg_sleep_mode_alerts.581745962 |
|
|
Sep 05 01:32:16 AM UTC 24 |
Sep 05 01:38:40 AM UTC 24 |
3580093244 ps |
| T750 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/50.chip_sw_alert_handler_lpg_sleep_mode_alerts.3410272788 |
|
|
Sep 05 01:32:29 AM UTC 24 |
Sep 05 01:38:44 AM UTC 24 |
3957029640 ps |
| T753 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/46.chip_sw_alert_handler_lpg_sleep_mode_alerts.2951646949 |
|
|
Sep 05 01:34:00 AM UTC 24 |
Sep 05 01:38:49 AM UTC 24 |
3622157250 ps |
| T740 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/48.chip_sw_alert_handler_lpg_sleep_mode_alerts.1490267236 |
|
|
Sep 05 01:32:25 AM UTC 24 |
Sep 05 01:38:59 AM UTC 24 |
4004947432 ps |
| T1312 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/8.chip_sw_uart_rand_baudrate.1356011962 |
|
|
Sep 05 12:54:04 AM UTC 24 |
Sep 05 01:39:08 AM UTC 24 |
13037927944 ps |
| T1313 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/9.chip_sw_uart_rand_baudrate.1839679060 |
|
|
Sep 05 12:55:33 AM UTC 24 |
Sep 05 01:39:38 AM UTC 24 |
13454641628 ps |
| T770 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/47.chip_sw_alert_handler_lpg_sleep_mode_alerts.3442185986 |
|
|
Sep 05 01:33:04 AM UTC 24 |
Sep 05 01:39:43 AM UTC 24 |
4390200408 ps |
| T1314 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/49.chip_sw_all_escalation_resets.3849492014 |
|
|
Sep 05 01:32:21 AM UTC 24 |
Sep 05 01:40:12 AM UTC 24 |
4330272864 ps |
| T668 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/44.chip_sw_all_escalation_resets.2090142256 |
|
|
Sep 05 01:29:56 AM UTC 24 |
Sep 05 01:40:21 AM UTC 24 |
6417505586 ps |
| T783 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/43.chip_sw_all_escalation_resets.307215806 |
|
|
Sep 05 01:31:11 AM UTC 24 |
Sep 05 01:40:26 AM UTC 24 |
4348513708 ps |
| T775 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/56.chip_sw_alert_handler_lpg_sleep_mode_alerts.903678641 |
|
|
Sep 05 01:35:38 AM UTC 24 |
Sep 05 01:40:26 AM UTC 24 |
3357494964 ps |
| T720 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/42.chip_sw_all_escalation_resets.1023717595 |
|
|
Sep 05 01:30:15 AM UTC 24 |
Sep 05 01:40:29 AM UTC 24 |
6301435720 ps |
| T701 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/47.chip_sw_all_escalation_resets.3064957102 |
|
|
Sep 05 01:32:29 AM UTC 24 |
Sep 05 01:40:31 AM UTC 24 |
4771116440 ps |
| T671 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/52.chip_sw_alert_handler_lpg_sleep_mode_alerts.3933513903 |
|
|
Sep 05 01:33:45 AM UTC 24 |
Sep 05 01:40:38 AM UTC 24 |
3362972588 ps |
| T1315 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/49.chip_sw_alert_handler_lpg_sleep_mode_alerts.4010791424 |
|
|
Sep 05 01:33:41 AM UTC 24 |
Sep 05 01:40:40 AM UTC 24 |
3640190428 ps |
| T1316 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/3.chip_sw_csrng_edn_concurrency.649602410 |
|
|
Sep 05 12:36:33 AM UTC 24 |
Sep 05 01:40:58 AM UTC 24 |
14482664792 ps |
| T776 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/45.chip_sw_all_escalation_resets.3006494602 |
|
|
Sep 05 01:30:58 AM UTC 24 |
Sep 05 01:41:02 AM UTC 24 |
6105060756 ps |
| T686 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/48.chip_sw_all_escalation_resets.1911952445 |
|
|
Sep 05 01:32:01 AM UTC 24 |
Sep 05 01:41:11 AM UTC 24 |
5868794788 ps |
| T754 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/57.chip_sw_alert_handler_lpg_sleep_mode_alerts.858243029 |
|
|
Sep 05 01:35:41 AM UTC 24 |
Sep 05 01:41:16 AM UTC 24 |
4221528724 ps |
| T784 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/54.chip_sw_alert_handler_lpg_sleep_mode_alerts.2388927384 |
|
|
Sep 05 01:35:31 AM UTC 24 |
Sep 05 01:41:26 AM UTC 24 |
3193578984 ps |
| T772 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/51.chip_sw_alert_handler_lpg_sleep_mode_alerts.3899271256 |
|
|
Sep 05 01:35:28 AM UTC 24 |
Sep 05 01:41:29 AM UTC 24 |
3795775560 ps |
| T695 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/53.chip_sw_alert_handler_lpg_sleep_mode_alerts.3682266848 |
|
|
Sep 05 01:34:51 AM UTC 24 |
Sep 05 01:41:36 AM UTC 24 |
3585247814 ps |
| T751 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/55.chip_sw_alert_handler_lpg_sleep_mode_alerts.1118519700 |
|
|
Sep 05 01:35:37 AM UTC 24 |
Sep 05 01:41:44 AM UTC 24 |
3513497922 ps |
| T1317 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/50.chip_sw_all_escalation_resets.3673630105 |
|
|
Sep 05 01:32:20 AM UTC 24 |
Sep 05 01:41:53 AM UTC 24 |
4840853298 ps |
| T277 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/46.chip_sw_all_escalation_resets.2980768880 |
|
|
Sep 05 01:32:21 AM UTC 24 |
Sep 05 01:42:36 AM UTC 24 |
6559034294 ps |
| T687 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/52.chip_sw_all_escalation_resets.581648866 |
|
|
Sep 05 01:34:44 AM UTC 24 |
Sep 05 01:42:37 AM UTC 24 |
5809577664 ps |
| T769 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/58.chip_sw_alert_handler_lpg_sleep_mode_alerts.1710954873 |
|
|
Sep 05 01:37:28 AM UTC 24 |
Sep 05 01:42:38 AM UTC 24 |
4243488056 ps |
| T730 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/56.chip_sw_all_escalation_resets.1935044186 |
|
|
Sep 05 01:35:35 AM UTC 24 |
Sep 05 01:43:15 AM UTC 24 |
4378360060 ps |
| T764 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/60.chip_sw_alert_handler_lpg_sleep_mode_alerts.2558126254 |
|
|
Sep 05 01:38:06 AM UTC 24 |
Sep 05 01:43:20 AM UTC 24 |
3913616212 ps |
| T691 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/62.chip_sw_alert_handler_lpg_sleep_mode_alerts.1548377098 |
|
|
Sep 05 01:38:38 AM UTC 24 |
Sep 05 01:43:38 AM UTC 24 |
3385396850 ps |
| T723 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/59.chip_sw_alert_handler_lpg_sleep_mode_alerts.3428517328 |
|
|
Sep 05 01:38:41 AM UTC 24 |
Sep 05 01:43:46 AM UTC 24 |
3306558644 ps |
| T735 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/63.chip_sw_alert_handler_lpg_sleep_mode_alerts.1567026427 |
|
|
Sep 05 01:38:40 AM UTC 24 |
Sep 05 01:43:56 AM UTC 24 |
3551873088 ps |
| T785 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/54.chip_sw_all_escalation_resets.2552115061 |
|
|
Sep 05 01:34:49 AM UTC 24 |
Sep 05 01:44:06 AM UTC 24 |
5080774860 ps |
| T760 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/55.chip_sw_all_escalation_resets.1579578971 |
|
|
Sep 05 01:35:32 AM UTC 24 |
Sep 05 01:44:21 AM UTC 24 |
4203432696 ps |
| T765 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/53.chip_sw_all_escalation_resets.4133658800 |
|
|
Sep 05 01:34:50 AM UTC 24 |
Sep 05 01:44:22 AM UTC 24 |
5831000592 ps |
| T738 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/41.chip_sw_all_escalation_resets.1935030599 |
|
|
Sep 05 01:34:01 AM UTC 24 |
Sep 05 01:44:44 AM UTC 24 |
6253513960 ps |
| T757 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/57.chip_sw_all_escalation_resets.1149454772 |
|
|
Sep 05 01:35:40 AM UTC 24 |
Sep 05 01:45:13 AM UTC 24 |
6551602824 ps |
| T713 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/58.chip_sw_all_escalation_resets.394039205 |
|
|
Sep 05 01:37:37 AM UTC 24 |
Sep 05 01:45:16 AM UTC 24 |
4710595640 ps |
| T733 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/61.chip_sw_alert_handler_lpg_sleep_mode_alerts.2151073451 |
|
|
Sep 05 01:38:44 AM UTC 24 |
Sep 05 01:45:17 AM UTC 24 |
4006089720 ps |
| T261 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/51.chip_sw_all_escalation_resets.347595985 |
|
|
Sep 05 01:34:41 AM UTC 24 |
Sep 05 01:45:18 AM UTC 24 |
5161686270 ps |
| T1318 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/62.chip_sw_all_escalation_resets.2966900472 |
|
|
Sep 05 01:38:07 AM UTC 24 |
Sep 05 01:45:57 AM UTC 24 |
4310780512 ps |
| T334 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/65.chip_sw_alert_handler_lpg_sleep_mode_alerts.3612655268 |
|
|
Sep 05 01:40:29 AM UTC 24 |
Sep 05 01:46:00 AM UTC 24 |
3769089212 ps |
| T739 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/67.chip_sw_alert_handler_lpg_sleep_mode_alerts.3279004284 |
|
|
Sep 05 01:41:02 AM UTC 24 |
Sep 05 01:46:42 AM UTC 24 |
4056339670 ps |
| T755 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/68.chip_sw_alert_handler_lpg_sleep_mode_alerts.168004217 |
|
|
Sep 05 01:40:51 AM UTC 24 |
Sep 05 01:46:51 AM UTC 24 |
3320578824 ps |
| T669 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/64.chip_sw_alert_handler_lpg_sleep_mode_alerts.95363540 |
|
|
Sep 05 01:40:48 AM UTC 24 |
Sep 05 01:47:10 AM UTC 24 |
4441920320 ps |
| T741 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/60.chip_sw_all_escalation_resets.1073986243 |
|
|
Sep 05 01:37:38 AM UTC 24 |
Sep 05 01:47:16 AM UTC 24 |
4935997532 ps |
| T1319 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/61.chip_sw_all_escalation_resets.2329697150 |
|
|
Sep 05 01:39:33 AM UTC 24 |
Sep 05 01:47:29 AM UTC 24 |
4781901718 ps |
| T683 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/69.chip_sw_alert_handler_lpg_sleep_mode_alerts.4171559072 |
|
|
Sep 05 01:42:18 AM UTC 24 |
Sep 05 01:47:38 AM UTC 24 |
3951463714 ps |
| T1320 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/79.chip_sw_alert_handler_lpg_sleep_mode_alerts.3492930271 |
|
|
Sep 05 01:43:35 AM UTC 24 |
Sep 05 01:48:03 AM UTC 24 |
3386631980 ps |
| T688 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/59.chip_sw_all_escalation_resets.2837687454 |
|
|
Sep 05 01:37:26 AM UTC 24 |
Sep 05 01:48:08 AM UTC 24 |
5169833124 ps |
| T1321 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/64.chip_sw_all_escalation_resets.2617823317 |
|
|
Sep 05 01:39:20 AM UTC 24 |
Sep 05 01:48:35 AM UTC 24 |
5474400158 ps |
| T190 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/68.chip_sw_all_escalation_resets.3712864039 |
|
|
Sep 05 01:40:47 AM UTC 24 |
Sep 05 01:48:47 AM UTC 24 |
4560632258 ps |
| T706 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/73.chip_sw_alert_handler_lpg_sleep_mode_alerts.3297325930 |
|
|
Sep 05 01:43:23 AM UTC 24 |
Sep 05 01:49:03 AM UTC 24 |
4311611776 ps |
| T715 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/63.chip_sw_all_escalation_resets.3099437169 |
|
|
Sep 05 01:39:07 AM UTC 24 |
Sep 05 01:49:22 AM UTC 24 |
6134301276 ps |
| T692 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/66.chip_sw_alert_handler_lpg_sleep_mode_alerts.3217809503 |
|
|
Sep 05 01:43:29 AM UTC 24 |
Sep 05 01:49:33 AM UTC 24 |
3982822240 ps |
| T1322 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/74.chip_sw_alert_handler_lpg_sleep_mode_alerts.1739073164 |
|
|
Sep 05 01:43:35 AM UTC 24 |
Sep 05 01:49:52 AM UTC 24 |
4096260152 ps |
| T370 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_inject_scramble_seed.843800743 |
|
|
Sep 04 09:41:12 PM UTC 24 |
Sep 05 01:50:08 AM UTC 24 |
64375846819 ps |
| T716 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/66.chip_sw_all_escalation_resets.2541465034 |
|
|
Sep 05 01:40:48 AM UTC 24 |
Sep 05 01:50:30 AM UTC 24 |
5284734040 ps |
| T728 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/80.chip_sw_alert_handler_lpg_sleep_mode_alerts.1958420676 |
|
|
Sep 05 01:45:02 AM UTC 24 |
Sep 05 01:50:37 AM UTC 24 |
3822171346 ps |
| T742 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/72.chip_sw_alert_handler_lpg_sleep_mode_alerts.268005790 |
|
|
Sep 05 01:45:06 AM UTC 24 |
Sep 05 01:50:48 AM UTC 24 |
3633048040 ps |
| T729 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/77.chip_sw_alert_handler_lpg_sleep_mode_alerts.4012685623 |
|
|
Sep 05 01:45:06 AM UTC 24 |
Sep 05 01:50:50 AM UTC 24 |
3668997064 ps |
| T679 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/71.chip_sw_alert_handler_lpg_sleep_mode_alerts.1032689716 |
|
|
Sep 05 01:44:18 AM UTC 24 |
Sep 05 01:51:30 AM UTC 24 |
3536852616 ps |
| T1323 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_csrng_edn_concurrency_reduced_freq.3492443819 |
|
|
Sep 05 12:15:37 AM UTC 24 |
Sep 05 01:51:51 AM UTC 24 |
28825994395 ps |
| T743 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/75.chip_sw_alert_handler_lpg_sleep_mode_alerts.2475822475 |
|
|
Sep 05 01:45:14 AM UTC 24 |
Sep 05 01:52:00 AM UTC 24 |
4527859602 ps |
| T335 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/70.chip_sw_alert_handler_lpg_sleep_mode_alerts.2448439386 |
|
|
Sep 05 01:46:16 AM UTC 24 |
Sep 05 01:52:11 AM UTC 24 |
3321705386 ps |
| T262 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/70.chip_sw_all_escalation_resets.3869456636 |
|
|
Sep 05 01:43:32 AM UTC 24 |
Sep 05 01:52:15 AM UTC 24 |
5809375240 ps |
| T703 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/84.chip_sw_alert_handler_lpg_sleep_mode_alerts.4202552497 |
|
|
Sep 05 01:46:49 AM UTC 24 |
Sep 05 01:52:16 AM UTC 24 |
3200058160 ps |
| T1324 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/65.chip_sw_all_escalation_resets.1348027816 |
|
|
Sep 05 01:42:50 AM UTC 24 |
Sep 05 01:52:23 AM UTC 24 |
4428550780 ps |
| T1325 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/82.chip_sw_alert_handler_lpg_sleep_mode_alerts.509643798 |
|
|
Sep 05 01:45:36 AM UTC 24 |
Sep 05 01:52:25 AM UTC 24 |
3927205340 ps |
| T767 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/74.chip_sw_all_escalation_resets.3095965246 |
|
|
Sep 05 01:44:39 AM UTC 24 |
Sep 05 01:52:32 AM UTC 24 |
5353839516 ps |
| T278 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/80.chip_sw_all_escalation_resets.1176184077 |
|
|
Sep 05 01:46:02 AM UTC 24 |
Sep 05 01:53:05 AM UTC 24 |
4432949330 ps |
| T758 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/85.chip_sw_alert_handler_lpg_sleep_mode_alerts.144353756 |
|
|
Sep 05 01:47:53 AM UTC 24 |
Sep 05 01:53:31 AM UTC 24 |
3630473372 ps |
| T1326 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/67.chip_sw_all_escalation_resets.1405620399 |
|
|
Sep 05 01:45:36 AM UTC 24 |
Sep 05 01:53:41 AM UTC 24 |
5045294596 ps |
| T768 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/78.chip_sw_all_escalation_resets.27042575 |
|
|
Sep 05 01:43:57 AM UTC 24 |
Sep 05 01:53:43 AM UTC 24 |
4846277240 ps |
| T266 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/83.chip_sw_alert_handler_lpg_sleep_mode_alerts.76932192 |
|
|
Sep 05 01:46:51 AM UTC 24 |
Sep 05 01:53:43 AM UTC 24 |
4494662440 ps |
| T681 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/73.chip_sw_all_escalation_resets.3214218276 |
|
|
Sep 05 01:44:36 AM UTC 24 |
Sep 05 01:53:46 AM UTC 24 |
5873801032 ps |
| T1327 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/86.chip_sw_alert_handler_lpg_sleep_mode_alerts.3461625018 |
|
|
Sep 05 01:48:19 AM UTC 24 |
Sep 05 01:53:50 AM UTC 24 |
3707300464 ps |
| T725 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/88.chip_sw_alert_handler_lpg_sleep_mode_alerts.3084201809 |
|
|
Sep 05 01:48:36 AM UTC 24 |
Sep 05 01:54:01 AM UTC 24 |
3569632840 ps |
| T1328 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/79.chip_sw_all_escalation_resets.562042394 |
|
|
Sep 05 01:46:48 AM UTC 24 |
Sep 05 01:54:37 AM UTC 24 |
5486197800 ps |
| T1329 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/76.chip_sw_all_escalation_resets.643321152 |
|
|
Sep 05 01:45:35 AM UTC 24 |
Sep 05 01:54:40 AM UTC 24 |
5160259400 ps |
| T704 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/69.chip_sw_all_escalation_resets.3902654671 |
|
|
Sep 05 01:46:02 AM UTC 24 |
Sep 05 01:54:46 AM UTC 24 |
5313461400 ps |
| T773 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/83.chip_sw_all_escalation_resets.1964052388 |
|
|
Sep 05 01:45:45 AM UTC 24 |
Sep 05 01:54:47 AM UTC 24 |
5484855944 ps |
| T685 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/78.chip_sw_alert_handler_lpg_sleep_mode_alerts.3038205096 |
|
|
Sep 05 01:48:17 AM UTC 24 |
Sep 05 01:54:49 AM UTC 24 |
3774062664 ps |
| T693 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/89.chip_sw_alert_handler_lpg_sleep_mode_alerts.1706718020 |
|
|
Sep 05 01:48:59 AM UTC 24 |
Sep 05 01:55:07 AM UTC 24 |
3613322760 ps |
| T724 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/81.chip_sw_alert_handler_lpg_sleep_mode_alerts.3251519075 |
|
|
Sep 05 01:47:30 AM UTC 24 |
Sep 05 01:55:14 AM UTC 24 |
3981921908 ps |
| T279 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/71.chip_sw_all_escalation_resets.872135000 |
|
|
Sep 05 01:44:00 AM UTC 24 |
Sep 05 01:55:22 AM UTC 24 |
6463656020 ps |
| T726 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/87.chip_sw_alert_handler_lpg_sleep_mode_alerts.1220135003 |
|
|
Sep 05 01:47:57 AM UTC 24 |
Sep 05 01:55:23 AM UTC 24 |
4421961926 ps |
| T747 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/81.chip_sw_all_escalation_resets.1075379264 |
|
|
Sep 05 01:46:44 AM UTC 24 |
Sep 05 01:55:35 AM UTC 24 |
5808840482 ps |
| T102 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/72.chip_sw_all_escalation_resets.4109456999 |
|
|
Sep 05 01:45:37 AM UTC 24 |
Sep 05 01:55:44 AM UTC 24 |
5499777064 ps |
| T1330 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/77.chip_sw_all_escalation_resets.3538605734 |
|
|
Sep 05 01:47:29 AM UTC 24 |
Sep 05 01:55:56 AM UTC 24 |
5149131260 ps |
| T191 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/75.chip_sw_all_escalation_resets.612964308 |
|
|
Sep 05 01:45:46 AM UTC 24 |
Sep 05 01:56:41 AM UTC 24 |
6023054780 ps |
| T1331 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/84.chip_sw_all_escalation_resets.3930952708 |
|
|
Sep 05 01:46:45 AM UTC 24 |
Sep 05 01:56:59 AM UTC 24 |
6556532232 ps |
| T280 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/90.chip_sw_all_escalation_resets.1875132841 |
|
|
Sep 05 01:49:56 AM UTC 24 |
Sep 05 01:57:17 AM UTC 24 |
5120936344 ps |
| T771 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/85.chip_sw_all_escalation_resets.4103703881 |
|
|
Sep 05 01:49:01 AM UTC 24 |
Sep 05 01:57:37 AM UTC 24 |
5621259768 ps |
| T1332 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/87.chip_sw_all_escalation_resets.891332127 |
|
|
Sep 05 01:48:33 AM UTC 24 |
Sep 05 01:57:39 AM UTC 24 |
4847620680 ps |
| T1333 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/86.chip_sw_all_escalation_resets.2828435732 |
|
|
Sep 05 01:48:43 AM UTC 24 |
Sep 05 01:58:05 AM UTC 24 |
5626510050 ps |
| T1334 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/93.chip_sw_all_escalation_resets.2868614899 |
|
|
Sep 05 01:50:03 AM UTC 24 |
Sep 05 01:58:28 AM UTC 24 |
4328525912 ps |
| T1335 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/96.chip_sw_all_escalation_resets.2756223007 |
|
|
Sep 05 01:51:01 AM UTC 24 |
Sep 05 01:58:32 AM UTC 24 |
4769289526 ps |
| T336 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/98.chip_sw_all_escalation_resets.670774984 |
|
|
Sep 05 01:51:01 AM UTC 24 |
Sep 05 01:58:40 AM UTC 24 |
4135094476 ps |
| T752 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/95.chip_sw_all_escalation_resets.1164156062 |
|
|
Sep 05 01:50:42 AM UTC 24 |
Sep 05 01:58:49 AM UTC 24 |
4860183266 ps |
| T1336 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/82.chip_sw_all_escalation_resets.536890182 |
|
|
Sep 05 01:48:59 AM UTC 24 |
Sep 05 01:59:04 AM UTC 24 |
5494302100 ps |
| T1337 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/99.chip_sw_all_escalation_resets.944562525 |
|
|
Sep 05 01:51:07 AM UTC 24 |
Sep 05 01:59:13 AM UTC 24 |
5312023400 ps |
| T1338 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/92.chip_sw_all_escalation_resets.608423794 |
|
|
Sep 05 01:50:02 AM UTC 24 |
Sep 05 01:59:27 AM UTC 24 |
5525665862 ps |
| T1339 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/91.chip_sw_all_escalation_resets.1181733671 |
|
|
Sep 05 01:50:03 AM UTC 24 |
Sep 05 01:59:34 AM UTC 24 |
5790045448 ps |
| T1340 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/89.chip_sw_all_escalation_resets.3956101139 |
|
|
Sep 05 01:50:03 AM UTC 24 |
Sep 05 01:59:36 AM UTC 24 |
5601166008 ps |
| T267 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/88.chip_sw_all_escalation_resets.3580217065 |
|
|
Sep 05 01:48:43 AM UTC 24 |
Sep 05 01:59:54 AM UTC 24 |
5997199852 ps |
| T736 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/94.chip_sw_all_escalation_resets.2783016662 |
|
|
Sep 05 01:50:55 AM UTC 24 |
Sep 05 02:00:33 AM UTC 24 |
5613407160 ps |