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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
96.02 95.45 93.66 95.48 94.43 97.53 99.54


Total test records in report: 2931
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T1796 /workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/37.xbar_unmapped_addr.3908097353 Sep 04 06:16:07 PM UTC 24 Sep 04 06:16:39 PM UTC 24 192412730 ps
T1797 /workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/37.xbar_access_same_device.3687359838 Sep 04 06:15:56 PM UTC 24 Sep 04 06:16:40 PM UTC 24 559083118 ps
T1798 /workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/37.xbar_smoke_slow_rsp.128813217 Sep 04 06:15:26 PM UTC 24 Sep 04 06:16:42 PM UTC 24 4159303276 ps
T1799 /workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/36.xbar_random_slow_rsp.157491390 Sep 04 06:14:33 PM UTC 24 Sep 04 06:16:46 PM UTC 24 8410877481 ps
T1800 /workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/32.xbar_stress_all_with_reset_error.2681385419 Sep 04 06:09:23 PM UTC 24 Sep 04 06:16:46 PM UTC 24 3980703536 ps
T1801 /workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/38.xbar_smoke_zero_delays.1636201934 Sep 04 06:16:41 PM UTC 24 Sep 04 06:16:50 PM UTC 24 45134209 ps
T1802 /workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/34.xbar_stress_all.629712338 Sep 04 06:11:42 PM UTC 24 Sep 04 06:16:52 PM UTC 24 7151665248 ps
T1803 /workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/38.xbar_smoke.1451780662 Sep 04 06:16:39 PM UTC 24 Sep 04 06:16:53 PM UTC 24 217805900 ps
T1804 /workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/37.xbar_error_and_unmapped_addr.2042912944 Sep 04 06:16:20 PM UTC 24 Sep 04 06:16:58 PM UTC 24 966258290 ps
T1805 /workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/37.xbar_same_source.215528337 Sep 04 06:15:59 PM UTC 24 Sep 04 06:16:59 PM UTC 24 1574729778 ps
T1806 /workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/37.xbar_smoke_large_delays.1927922596 Sep 04 06:15:25 PM UTC 24 Sep 04 06:17:07 PM UTC 24 9445959924 ps
T1807 /workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/37.xbar_random_slow_rsp.1109612016 Sep 04 06:15:53 PM UTC 24 Sep 04 06:17:07 PM UTC 24 4902669094 ps
T483 /workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/31.xbar_random_slow_rsp.1534525182 Sep 04 06:07:22 PM UTC 24 Sep 04 06:17:08 PM UTC 24 39300953133 ps
T1808 /workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/36.xbar_stress_all_with_reset_error.2182831897 Sep 04 06:15:17 PM UTC 24 Sep 04 06:17:08 PM UTC 24 361119084 ps
T1809 /workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/38.xbar_random_zero_delays.98620082 Sep 04 06:17:05 PM UTC 24 Sep 04 06:17:16 PM UTC 24 41861272 ps
T1810 /workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/35.xbar_stress_all_with_reset_error.3814333956 Sep 04 06:13:55 PM UTC 24 Sep 04 06:17:25 PM UTC 24 575214965 ps
T1811 /workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/38.xbar_smoke_slow_rsp.158528184 Sep 04 06:16:48 PM UTC 24 Sep 04 06:17:26 PM UTC 24 2183945402 ps
T1812 /workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/38.xbar_access_same_device.152722111 Sep 04 06:17:12 PM UTC 24 Sep 04 06:17:29 PM UTC 24 107012022 ps
T1813 /workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/38.xbar_error_random.1811758766 Sep 04 06:17:17 PM UTC 24 Sep 04 06:17:29 PM UTC 24 75845988 ps
T1814 /workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/35.xbar_stress_all_with_rand_reset.2460880 Sep 04 06:13:49 PM UTC 24 Sep 04 06:17:30 PM UTC 24 354530271 ps
T1815 /workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/39.xbar_smoke_zero_delays.1075742345 Sep 04 06:17:31 PM UTC 24 Sep 04 06:17:41 PM UTC 24 43319717 ps
T1816 /workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/39.xbar_smoke.237150045 Sep 04 06:17:33 PM UTC 24 Sep 04 06:17:47 PM UTC 24 243214075 ps
T1817 /workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/38.xbar_stress_all_with_rand_reset.3113071074 Sep 04 06:17:29 PM UTC 24 Sep 04 06:17:57 PM UTC 24 70592809 ps
T1818 /workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/38.xbar_error_and_unmapped_addr.2922307113 Sep 04 06:17:21 PM UTC 24 Sep 04 06:17:57 PM UTC 24 274418136 ps
T1819 /workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/2.chip_csr_bit_bash.1448049977 Sep 04 05:03:22 PM UTC 24 Sep 04 06:17:58 PM UTC 24 43479803094 ps
T1820 /workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/38.xbar_random.290892534 Sep 04 06:16:49 PM UTC 24 Sep 04 06:18:01 PM UTC 24 1899066984 ps
T1821 /workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/38.xbar_unmapped_addr.3130318560 Sep 04 06:17:19 PM UTC 24 Sep 04 06:18:01 PM UTC 24 951064310 ps
T1822 /workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/38.xbar_smoke_large_delays.1918620070 Sep 04 06:16:45 PM UTC 24 Sep 04 06:18:12 PM UTC 24 7486300233 ps
T1823 /workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/38.xbar_same_source.629550012 Sep 04 06:17:17 PM UTC 24 Sep 04 06:18:16 PM UTC 24 2239293780 ps
T1824 /workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/33.xbar_stress_all_with_error.1385182023 Sep 04 06:10:48 PM UTC 24 Sep 04 06:18:28 PM UTC 24 12690564121 ps
T1825 /workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/39.xbar_random.1158039493 Sep 04 06:17:56 PM UTC 24 Sep 04 06:18:30 PM UTC 24 635478285 ps
T1826 /workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/39.xbar_same_source.3116981945 Sep 04 06:18:28 PM UTC 24 Sep 04 06:18:37 PM UTC 24 45142534 ps
T1827 /workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/32.xbar_random_slow_rsp.3825774455 Sep 04 06:08:59 PM UTC 24 Sep 04 06:18:42 PM UTC 24 36278246207 ps
T1828 /workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/39.xbar_unmapped_addr.1632440349 Sep 04 06:18:28 PM UTC 24 Sep 04 06:18:45 PM UTC 24 203924376 ps
T1829 /workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/36.xbar_stress_all_with_error.1332879425 Sep 04 06:15:09 PM UTC 24 Sep 04 06:18:45 PM UTC 24 5720075899 ps
T842 /workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/29.xbar_access_same_device_slow_rsp.673889134 Sep 04 06:04:03 PM UTC 24 Sep 04 06:18:47 PM UTC 24 57403158558 ps
T1830 /workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/39.xbar_stress_all_with_error.3440646996 Sep 04 06:18:48 PM UTC 24 Sep 04 06:19:01 PM UTC 24 153209966 ps
T1831 /workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/39.xbar_random_zero_delays.2994724752 Sep 04 06:17:59 PM UTC 24 Sep 04 06:19:02 PM UTC 24 603727625 ps
T1832 /workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/37.xbar_stress_all_with_reset_error.1720973735 Sep 04 06:16:31 PM UTC 24 Sep 04 06:19:04 PM UTC 24 353752351 ps
T1833 /workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/36.xbar_stress_all.2319236842 Sep 04 06:15:02 PM UTC 24 Sep 04 06:19:13 PM UTC 24 2740778044 ps
T1834 /workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/39.xbar_error_and_unmapped_addr.3568148703 Sep 04 06:18:30 PM UTC 24 Sep 04 06:19:14 PM UTC 24 897775367 ps
T1835 /workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/39.xbar_error_random.1986878134 Sep 04 06:18:24 PM UTC 24 Sep 04 06:19:16 PM UTC 24 1104530172 ps
T1836 /workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/40.xbar_smoke.1980895288 Sep 04 06:19:01 PM UTC 24 Sep 04 06:19:17 PM UTC 24 230482092 ps
T1837 /workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/38.xbar_stress_all_with_error.1769762717 Sep 04 06:17:33 PM UTC 24 Sep 04 06:19:18 PM UTC 24 1383756440 ps
T1838 /workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/40.xbar_smoke_zero_delays.177904647 Sep 04 06:19:09 PM UTC 24 Sep 04 06:19:18 PM UTC 24 46062137 ps
T1839 /workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/39.xbar_smoke_slow_rsp.2286771379 Sep 04 06:17:54 PM UTC 24 Sep 04 06:19:18 PM UTC 24 4682392072 ps
T1840 /workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/39.xbar_access_same_device.1536696095 Sep 04 06:18:13 PM UTC 24 Sep 04 06:19:23 PM UTC 24 624575725 ps
T486 /workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/24.xbar_access_same_device_slow_rsp.3071942292 Sep 04 05:55:59 PM UTC 24 Sep 04 06:19:27 PM UTC 24 81847853394 ps
T1841 /workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/39.xbar_stress_all.644994930 Sep 04 06:18:29 PM UTC 24 Sep 04 06:19:32 PM UTC 24 532373771 ps
T1842 /workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/39.xbar_smoke_large_delays.3524030936 Sep 04 06:17:44 PM UTC 24 Sep 04 06:19:37 PM UTC 24 8671685780 ps
T1843 /workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/40.xbar_random_zero_delays.3265442077 Sep 04 06:19:16 PM UTC 24 Sep 04 06:19:39 PM UTC 24 181780717 ps
T1844 /workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/11.chip_same_csr_outstanding.3456520108 Sep 04 05:25:36 PM UTC 24 Sep 04 06:19:42 PM UTC 24 28163980454 ps
T1845 /workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/39.xbar_stress_all_with_rand_reset.3181603471 Sep 04 06:18:44 PM UTC 24 Sep 04 06:19:42 PM UTC 24 184733645 ps
T1846 /workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/38.xbar_stress_all.2144396574 Sep 04 06:17:24 PM UTC 24 Sep 04 06:19:50 PM UTC 24 1220168232 ps
T1847 /workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/40.xbar_access_same_device.637972642 Sep 04 06:19:32 PM UTC 24 Sep 04 06:19:57 PM UTC 24 474942774 ps
T1848 /workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/35.xbar_stress_all_with_error.3231833238 Sep 04 06:13:54 PM UTC 24 Sep 04 06:20:02 PM UTC 24 11545773007 ps
T1849 /workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/40.xbar_unmapped_addr.37723357 Sep 04 06:19:46 PM UTC 24 Sep 04 06:20:04 PM UTC 24 211334779 ps
T1850 /workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/40.xbar_same_source.1164350655 Sep 04 06:19:42 PM UTC 24 Sep 04 06:20:06 PM UTC 24 216304028 ps
T1851 /workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/41.xbar_smoke.2081805463 Sep 04 06:20:03 PM UTC 24 Sep 04 06:20:12 PM UTC 24 46103122 ps
T1852 /workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/40.xbar_error_random.1539818085 Sep 04 06:19:47 PM UTC 24 Sep 04 06:20:17 PM UTC 24 397501581 ps
T508 /workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/41.xbar_smoke_zero_delays.2349265671 Sep 04 06:20:08 PM UTC 24 Sep 04 06:20:19 PM UTC 24 56768935 ps
T1853 /workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/40.xbar_error_and_unmapped_addr.772129637 Sep 04 06:19:48 PM UTC 24 Sep 04 06:20:19 PM UTC 24 233961121 ps
T879 /workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/36.xbar_stress_all_with_rand_reset.3297242993 Sep 04 06:15:05 PM UTC 24 Sep 04 06:20:28 PM UTC 24 1223844378 ps
T1854 /workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/40.xbar_stress_all_with_reset_error.4093183000 Sep 04 06:19:56 PM UTC 24 Sep 04 06:20:29 PM UTC 24 91624732 ps
T1855 /workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/37.xbar_stress_all.3439993808 Sep 04 06:16:24 PM UTC 24 Sep 04 06:20:32 PM UTC 24 2625658970 ps
T1856 /workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/29.xbar_random_slow_rsp.3259829158 Sep 04 06:03:57 PM UTC 24 Sep 04 06:20:35 PM UTC 24 64879003844 ps
T1857 /workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/7.chip_same_csr_outstanding.3454491003 Sep 04 05:15:42 PM UTC 24 Sep 04 06:20:38 PM UTC 24 30562113955 ps
T1858 /workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/29.xbar_random_large_delays.3206419568 Sep 04 06:03:49 PM UTC 24 Sep 04 06:20:39 PM UTC 24 106080522491 ps
T1859 /workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/40.xbar_smoke_large_delays.1979844872 Sep 04 06:19:14 PM UTC 24 Sep 04 06:20:44 PM UTC 24 8804420837 ps
T1860 /workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/40.xbar_smoke_slow_rsp.2418840832 Sep 04 06:19:16 PM UTC 24 Sep 04 06:20:47 PM UTC 24 4842199650 ps
T1861 /workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/40.xbar_stress_all_with_rand_reset.2312311668 Sep 04 06:19:46 PM UTC 24 Sep 04 06:20:53 PM UTC 24 186421898 ps
T1862 /workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/41.xbar_random_zero_delays.3820060991 Sep 04 06:20:21 PM UTC 24 Sep 04 06:20:57 PM UTC 24 394710744 ps
T1863 /workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/41.xbar_random.3934620547 Sep 04 06:20:16 PM UTC 24 Sep 04 06:21:00 PM UTC 24 1019468546 ps
T861 /workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/37.xbar_stress_all_with_rand_reset.359207798 Sep 04 06:16:26 PM UTC 24 Sep 04 06:21:01 PM UTC 24 1968292751 ps
T440 /workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/8.chip_same_csr_outstanding.523424356 Sep 04 05:18:20 PM UTC 24 Sep 04 06:21:05 PM UTC 24 30446867472 ps
T1864 /workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/40.xbar_stress_all_with_error.3814780733 Sep 04 06:19:50 PM UTC 24 Sep 04 06:21:11 PM UTC 24 921428904 ps
T1865 /workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/42.xbar_smoke_zero_delays.3543683797 Sep 04 06:21:04 PM UTC 24 Sep 04 06:21:14 PM UTC 24 38303121 ps
T1866 /workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/41.xbar_error_random.3971954435 Sep 04 06:20:39 PM UTC 24 Sep 04 06:21:17 PM UTC 24 410596774 ps
T1867 /workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/42.xbar_smoke.2487916538 Sep 04 06:21:05 PM UTC 24 Sep 04 06:21:17 PM UTC 24 158834319 ps
T1868 /workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/41.xbar_smoke_slow_rsp.3483019781 Sep 04 06:20:08 PM UTC 24 Sep 04 06:21:20 PM UTC 24 3786240608 ps
T1869 /workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/41.xbar_same_source.2601070384 Sep 04 06:20:30 PM UTC 24 Sep 04 06:21:20 PM UTC 24 483230369 ps
T1870 /workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/40.xbar_random.577744468 Sep 04 06:19:15 PM UTC 24 Sep 04 06:21:21 PM UTC 24 2648013931 ps
T1871 /workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/41.xbar_stress_all_with_error.1118177129 Sep 04 06:21:00 PM UTC 24 Sep 04 06:21:24 PM UTC 24 198582906 ps
T1872 /workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/41.xbar_smoke_large_delays.637150853 Sep 04 06:20:01 PM UTC 24 Sep 04 06:21:27 PM UTC 24 7905931232 ps
T1873 /workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/40.xbar_stress_all.2666109977 Sep 04 06:19:50 PM UTC 24 Sep 04 06:21:27 PM UTC 24 2081851058 ps
T1874 /workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/41.xbar_unmapped_addr.1872402900 Sep 04 06:20:48 PM UTC 24 Sep 04 06:21:36 PM UTC 24 1111950387 ps
T1875 /workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/34.xbar_stress_all_with_rand_reset.403392694 Sep 04 06:11:44 PM UTC 24 Sep 04 06:21:38 PM UTC 24 8758788502 ps
T877 /workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/39.xbar_stress_all_with_reset_error.1403269721 Sep 04 06:18:57 PM UTC 24 Sep 04 06:21:40 PM UTC 24 693782357 ps
T1876 /workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/39.xbar_random_slow_rsp.2176756424 Sep 04 06:18:02 PM UTC 24 Sep 04 06:21:40 PM UTC 24 13811840308 ps
T1877 /workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/41.xbar_error_and_unmapped_addr.2340547814 Sep 04 06:20:51 PM UTC 24 Sep 04 06:21:43 PM UTC 24 1307074893 ps
T1878 /workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/42.xbar_random.1981563920 Sep 04 06:21:14 PM UTC 24 Sep 04 06:21:43 PM UTC 24 307061182 ps
T1879 /workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/42.xbar_access_same_device.1251039875 Sep 04 06:21:32 PM UTC 24 Sep 04 06:21:50 PM UTC 24 97705170 ps
T1880 /workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/43.xbar_smoke.245641916 Sep 04 06:21:49 PM UTC 24 Sep 04 06:22:04 PM UTC 24 232145316 ps
T1881 /workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/43.xbar_smoke_zero_delays.3953394440 Sep 04 06:21:58 PM UTC 24 Sep 04 06:22:05 PM UTC 24 47364244 ps
T849 /workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/41.xbar_stress_all.2722028272 Sep 04 06:20:48 PM UTC 24 Sep 04 06:22:10 PM UTC 24 2261006923 ps
T1882 /workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/42.xbar_same_source.518292693 Sep 04 06:21:40 PM UTC 24 Sep 04 06:22:11 PM UTC 24 609157148 ps
T1883 /workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/41.xbar_access_same_device.726165989 Sep 04 06:20:30 PM UTC 24 Sep 04 06:22:12 PM UTC 24 2740123806 ps
T1884 /workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/42.xbar_stress_all.1211952179 Sep 04 06:21:49 PM UTC 24 Sep 04 06:22:13 PM UTC 24 376184418 ps
T1885 /workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/42.xbar_random_zero_delays.4239429743 Sep 04 06:21:23 PM UTC 24 Sep 04 06:22:15 PM UTC 24 600895554 ps
T1886 /workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/42.xbar_stress_all_with_reset_error.864201788 Sep 04 06:21:55 PM UTC 24 Sep 04 06:22:18 PM UTC 24 72876351 ps
T1887 /workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/42.xbar_error_random.2998489814 Sep 04 06:21:44 PM UTC 24 Sep 04 06:22:33 PM UTC 24 534266356 ps
T1888 /workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/42.xbar_error_and_unmapped_addr.1669700127 Sep 04 06:21:47 PM UTC 24 Sep 04 06:22:37 PM UTC 24 327923354 ps
T1889 /workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/42.xbar_smoke_slow_rsp.1771265708 Sep 04 06:21:15 PM UTC 24 Sep 04 06:22:44 PM UTC 24 5863522549 ps
T1890 /workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/43.xbar_random_zero_delays.1516988960 Sep 04 06:22:06 PM UTC 24 Sep 04 06:22:51 PM UTC 24 468980372 ps
T1891 /workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/42.xbar_unmapped_addr.3198073086 Sep 04 06:21:45 PM UTC 24 Sep 04 06:22:51 PM UTC 24 1332835499 ps
T1892 /workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/42.xbar_smoke_large_delays.2252481555 Sep 04 06:21:07 PM UTC 24 Sep 04 06:22:57 PM UTC 24 7624181546 ps
T1893 /workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/30.xbar_random_large_delays.2176282286 Sep 04 06:05:40 PM UTC 24 Sep 04 06:22:58 PM UTC 24 101908869241 ps
T1894 /workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/43.xbar_error_and_unmapped_addr.3066548711 Sep 04 06:22:42 PM UTC 24 Sep 04 06:23:07 PM UTC 24 155347985 ps
T1895 /workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/43.xbar_smoke_slow_rsp.1715089585 Sep 04 06:22:06 PM UTC 24 Sep 04 06:23:08 PM UTC 24 4291746521 ps
T1896 /workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/43.xbar_unmapped_addr.3238825058 Sep 04 06:22:42 PM UTC 24 Sep 04 06:23:09 PM UTC 24 147250202 ps
T1897 /workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/41.xbar_random_large_delays.1742482847 Sep 04 06:20:18 PM UTC 24 Sep 04 06:23:13 PM UTC 24 15905998327 ps
T1898 /workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/44.xbar_smoke.2529413456 Sep 04 06:23:07 PM UTC 24 Sep 04 06:23:15 PM UTC 24 39355531 ps
T1899 /workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/43.xbar_error_random.1439997966 Sep 04 06:22:42 PM UTC 24 Sep 04 06:23:16 PM UTC 24 816040841 ps
T1900 /workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/44.xbar_smoke_zero_delays.1498992678 Sep 04 06:23:12 PM UTC 24 Sep 04 06:23:19 PM UTC 24 47725744 ps
T1901 /workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/43.xbar_smoke_large_delays.1268598598 Sep 04 06:22:04 PM UTC 24 Sep 04 06:23:22 PM UTC 24 9074954830 ps
T1902 /workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/43.xbar_access_same_device.4246167540 Sep 04 06:22:17 PM UTC 24 Sep 04 06:23:28 PM UTC 24 638756868 ps
T1903 /workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/36.xbar_access_same_device_slow_rsp.1593562739 Sep 04 06:14:38 PM UTC 24 Sep 04 06:23:29 PM UTC 24 35286277968 ps
T1904 /workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/43.xbar_random.1992221936 Sep 04 06:22:04 PM UTC 24 Sep 04 06:23:29 PM UTC 24 2339007618 ps
T1905 /workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/43.xbar_same_source.1815843522 Sep 04 06:22:37 PM UTC 24 Sep 04 06:23:38 PM UTC 24 1471548464 ps
T1906 /workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/38.xbar_stress_all_with_reset_error.2863495497 Sep 04 06:17:35 PM UTC 24 Sep 04 06:23:38 PM UTC 24 2634623583 ps
T1907 /workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/44.xbar_random.1746624845 Sep 04 06:23:22 PM UTC 24 Sep 04 06:23:45 PM UTC 24 172957897 ps
T1908 /workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/10.chip_same_csr_outstanding.850282846 Sep 04 05:23:18 PM UTC 24 Sep 04 06:23:46 PM UTC 24 31015532696 ps
T1909 /workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/44.xbar_access_same_device.2445190087 Sep 04 06:23:36 PM UTC 24 Sep 04 06:23:51 PM UTC 24 134554564 ps
T1910 /workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/44.xbar_unmapped_addr.956480424 Sep 04 06:23:46 PM UTC 24 Sep 04 06:23:59 PM UTC 24 136072081 ps
T1911 /workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/43.xbar_stress_all.3752492704 Sep 04 06:22:42 PM UTC 24 Sep 04 06:24:03 PM UTC 24 844897289 ps
T1912 /workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/44.xbar_error_and_unmapped_addr.60474599 Sep 04 06:23:54 PM UTC 24 Sep 04 06:24:09 PM UTC 24 345132464 ps
T1913 /workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/44.xbar_error_random.2973827594 Sep 04 06:23:43 PM UTC 24 Sep 04 06:24:09 PM UTC 24 207748770 ps
T1914 /workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/44.xbar_same_source.2208893675 Sep 04 06:23:44 PM UTC 24 Sep 04 06:24:15 PM UTC 24 299007366 ps
T1915 /workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/43.xbar_stress_all_with_reset_error.1556052421 Sep 04 06:23:05 PM UTC 24 Sep 04 06:24:15 PM UTC 24 236008453 ps
T1916 /workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/45.xbar_smoke_zero_delays.1589819870 Sep 04 06:24:10 PM UTC 24 Sep 04 06:24:18 PM UTC 24 51913498 ps
T1917 /workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/44.xbar_random_zero_delays.1655744391 Sep 04 06:23:28 PM UTC 24 Sep 04 06:24:19 PM UTC 24 423437109 ps
T1918 /workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/45.xbar_smoke.620831492 Sep 04 06:24:07 PM UTC 24 Sep 04 06:24:19 PM UTC 24 221503949 ps
T1919 /workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/44.xbar_smoke_large_delays.3338797278 Sep 04 06:23:18 PM UTC 24 Sep 04 06:24:30 PM UTC 24 6566334462 ps
T1920 /workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/40.xbar_random_slow_rsp.2705979967 Sep 04 06:19:34 PM UTC 24 Sep 04 06:24:32 PM UTC 24 22427569060 ps
T1921 /workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/44.xbar_stress_all_with_rand_reset.2817463143 Sep 04 06:24:00 PM UTC 24 Sep 04 06:24:32 PM UTC 24 88015611 ps
T1922 /workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/44.xbar_random_large_delays.3970187252 Sep 04 06:23:36 PM UTC 24 Sep 04 06:24:39 PM UTC 24 4986682132 ps
T1923 /workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/44.xbar_stress_all.3806963774 Sep 04 06:23:56 PM UTC 24 Sep 04 06:24:43 PM UTC 24 1167906151 ps
T1924 /workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/41.xbar_stress_all_with_rand_reset.1309693417 Sep 04 06:20:56 PM UTC 24 Sep 04 06:24:44 PM UTC 24 649667922 ps
T1925 /workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/32.xbar_random_large_delays.3810883601 Sep 04 06:08:57 PM UTC 24 Sep 04 06:24:54 PM UTC 24 101668551137 ps
T1926 /workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/44.xbar_smoke_slow_rsp.296154949 Sep 04 06:23:22 PM UTC 24 Sep 04 06:24:58 PM UTC 24 6280349474 ps
T1927 /workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/45.xbar_error_random.969054134 Sep 04 06:24:50 PM UTC 24 Sep 04 06:25:01 PM UTC 24 33352425 ps
T1928 /workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/45.xbar_same_source.3834175766 Sep 04 06:24:50 PM UTC 24 Sep 04 06:25:18 PM UTC 24 219296949 ps
T1929 /workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/45.xbar_random.4242033256 Sep 04 06:24:27 PM UTC 24 Sep 04 06:25:22 PM UTC 24 463951973 ps
T1930 /workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/45.xbar_random_zero_delays.43754064 Sep 04 06:24:34 PM UTC 24 Sep 04 06:25:23 PM UTC 24 358715928 ps
T1931 /workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/45.xbar_unmapped_addr.2170370986 Sep 04 06:24:49 PM UTC 24 Sep 04 06:25:24 PM UTC 24 492827924 ps
T1932 /workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/45.xbar_error_and_unmapped_addr.3397729274 Sep 04 06:25:00 PM UTC 24 Sep 04 06:25:24 PM UTC 24 242290397 ps
T1933 /workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/46.xbar_smoke.1379096944 Sep 04 06:25:15 PM UTC 24 Sep 04 06:25:30 PM UTC 24 243719679 ps
T1934 /workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/46.xbar_smoke_zero_delays.1173605490 Sep 04 06:25:23 PM UTC 24 Sep 04 06:25:32 PM UTC 24 43201996 ps
T1935 /workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/36.xbar_random_large_delays.3536930014 Sep 04 06:14:13 PM UTC 24 Sep 04 06:25:33 PM UTC 24 68662218201 ps
T1936 /workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/45.xbar_smoke_large_delays.727110655 Sep 04 06:24:10 PM UTC 24 Sep 04 06:25:35 PM UTC 24 9335191829 ps
T1937 /workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/45.xbar_access_same_device.2427275896 Sep 04 06:24:48 PM UTC 24 Sep 04 06:25:41 PM UTC 24 1500146303 ps
T1938 /workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/44.xbar_stress_all_with_error.1278038977 Sep 04 06:23:59 PM UTC 24 Sep 04 06:25:42 PM UTC 24 3043556711 ps
T1939 /workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/45.xbar_smoke_slow_rsp.2409471611 Sep 04 06:24:20 PM UTC 24 Sep 04 06:25:44 PM UTC 24 6011059441 ps
T1940 /workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/41.xbar_stress_all_with_reset_error.1447935759 Sep 04 06:21:03 PM UTC 24 Sep 04 06:26:03 PM UTC 24 1597576042 ps
T1941 /workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/46.xbar_random_zero_delays.538383868 Sep 04 06:25:50 PM UTC 24 Sep 04 06:26:14 PM UTC 24 262333487 ps
T795 /workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/42.xbar_stress_all_with_error.2896765550 Sep 04 06:21:48 PM UTC 24 Sep 04 06:26:20 PM UTC 24 8470621476 ps
T1942 /workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/46.xbar_error_and_unmapped_addr.169759758 Sep 04 06:26:10 PM UTC 24 Sep 04 06:26:28 PM UTC 24 155893844 ps
T1943 /workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/46.xbar_error_random.488453607 Sep 04 06:26:05 PM UTC 24 Sep 04 06:26:29 PM UTC 24 198912922 ps
T1944 /workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/45.xbar_stress_all_with_error.3125833586 Sep 04 06:25:09 PM UTC 24 Sep 04 06:26:30 PM UTC 24 833442599 ps
T1945 /workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/35.xbar_random_large_delays.3328793404 Sep 04 06:12:48 PM UTC 24 Sep 04 06:26:33 PM UTC 24 81793908259 ps
T1946 /workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/46.xbar_same_source.2197436372 Sep 04 06:26:03 PM UTC 24 Sep 04 06:26:37 PM UTC 24 314753794 ps
T1947 /workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/38.xbar_random_slow_rsp.1620809525 Sep 04 06:17:08 PM UTC 24 Sep 04 06:26:37 PM UTC 24 42520429982 ps
T1948 /workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/42.xbar_stress_all_with_rand_reset.622988526 Sep 04 06:21:47 PM UTC 24 Sep 04 06:26:39 PM UTC 24 4520699125 ps
T1949 /workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/37.xbar_random_large_delays.1124665593 Sep 04 06:15:51 PM UTC 24 Sep 04 06:26:46 PM UTC 24 63524386796 ps
T853 /workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/43.xbar_stress_all_with_error.1535309700 Sep 04 06:22:49 PM UTC 24 Sep 04 06:26:50 PM UTC 24 7346881722 ps
T1950 /workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/45.xbar_stress_all.3234024387 Sep 04 06:25:03 PM UTC 24 Sep 04 06:26:57 PM UTC 24 1304529188 ps
T1951 /workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/46.xbar_unmapped_addr.3209352458 Sep 04 06:26:07 PM UTC 24 Sep 04 06:26:57 PM UTC 24 1173744098 ps
T1952 /workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/46.xbar_smoke_large_delays.3271221667 Sep 04 06:25:22 PM UTC 24 Sep 04 06:26:59 PM UTC 24 6033344779 ps
T1953 /workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/47.xbar_smoke.3445555676 Sep 04 06:26:48 PM UTC 24 Sep 04 06:27:00 PM UTC 24 144465845 ps
T1954 /workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/47.xbar_smoke_zero_delays.4107280839 Sep 04 06:26:55 PM UTC 24 Sep 04 06:27:02 PM UTC 24 38796443 ps
T1955 /workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/54.xbar_smoke_zero_delays.3769982648 Sep 04 06:36:50 PM UTC 24 Sep 04 06:36:59 PM UTC 24 37664492 ps
T1956 /workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/46.xbar_smoke_slow_rsp.2820781952 Sep 04 06:25:32 PM UTC 24 Sep 04 06:27:11 PM UTC 24 5293468697 ps
T1957 /workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/46.xbar_access_same_device.2768329429 Sep 04 06:25:53 PM UTC 24 Sep 04 06:27:13 PM UTC 24 1725469351 ps
T491 /workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/42.xbar_random_slow_rsp.440913032 Sep 04 06:21:29 PM UTC 24 Sep 04 06:27:15 PM UTC 24 24821308827 ps
T1958 /workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/47.xbar_random_zero_delays.1937319065 Sep 04 06:27:01 PM UTC 24 Sep 04 06:27:17 PM UTC 24 99160668 ps
T1959 /workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/47.xbar_random.4211774527 Sep 04 06:27:00 PM UTC 24 Sep 04 06:27:22 PM UTC 24 136386270 ps
T1960 /workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/14.chip_same_csr_outstanding.2870929359 Sep 04 05:32:14 PM UTC 24 Sep 04 06:27:47 PM UTC 24 29675567924 ps
T1961 /workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/46.xbar_random.3176961459 Sep 04 06:25:49 PM UTC 24 Sep 04 06:27:54 PM UTC 24 2337075171 ps
T1962 /workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/47.xbar_unmapped_addr.3991685745 Sep 04 06:27:28 PM UTC 24 Sep 04 06:27:56 PM UTC 24 422272510 ps
T1963 /workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/47.xbar_error_and_unmapped_addr.501987411 Sep 04 06:27:26 PM UTC 24 Sep 04 06:27:56 PM UTC 24 625090599 ps
T1964 /workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/37.xbar_stress_all_with_error.3270148552 Sep 04 06:16:32 PM UTC 24 Sep 04 06:28:02 PM UTC 24 18111804088 ps
T1965 /workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/48.xbar_smoke_zero_delays.364384593 Sep 04 06:27:52 PM UTC 24 Sep 04 06:28:02 PM UTC 24 46450965 ps
T526 /workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/32.xbar_stress_all_with_rand_reset.164222390 Sep 04 06:09:18 PM UTC 24 Sep 04 06:28:02 PM UTC 24 18594493070 ps
T1966 /workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/47.xbar_stress_all_with_reset_error.3978035746 Sep 04 06:27:46 PM UTC 24 Sep 04 06:28:03 PM UTC 24 8042157 ps
T1967 /workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/48.xbar_smoke.447916227 Sep 04 06:27:49 PM UTC 24 Sep 04 06:28:03 PM UTC 24 207170264 ps
T1968 /workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/47.xbar_smoke_slow_rsp.1700619173 Sep 04 06:27:01 PM UTC 24 Sep 04 06:28:04 PM UTC 24 4389873278 ps
T869 /workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/45.xbar_stress_all_with_rand_reset.503181097 Sep 04 06:25:03 PM UTC 24 Sep 04 06:28:21 PM UTC 24 500968275 ps
T1969 /workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/47.xbar_stress_all_with_error.3043604553 Sep 04 06:27:45 PM UTC 24 Sep 04 06:28:35 PM UTC 24 603716200 ps
T1970 /workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/48.xbar_random_zero_delays.2365260030 Sep 04 06:28:27 PM UTC 24 Sep 04 06:28:38 PM UTC 24 40623578 ps
T1971 /workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/47.xbar_access_same_device.532973818 Sep 04 06:27:12 PM UTC 24 Sep 04 06:28:39 PM UTC 24 862167160 ps
T871 /workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/44.xbar_stress_all_with_reset_error.4095054471 Sep 04 06:24:05 PM UTC 24 Sep 04 06:28:41 PM UTC 24 3134470998 ps
T1972 /workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/47.xbar_same_source.4005490926 Sep 04 06:27:24 PM UTC 24 Sep 04 06:28:56 PM UTC 24 2715545928 ps
T1973 /workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/48.xbar_access_same_device.2850377311 Sep 04 06:28:33 PM UTC 24 Sep 04 06:28:57 PM UTC 24 214836596 ps
T1974 /workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/47.xbar_smoke_large_delays.1521511391 Sep 04 06:27:00 PM UTC 24 Sep 04 06:29:00 PM UTC 24 11352348152 ps
T1975 /workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/47.xbar_error_random.721786173 Sep 04 06:27:26 PM UTC 24 Sep 04 06:29:05 PM UTC 24 2306222865 ps
T1976 /workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/48.xbar_random.2044876070 Sep 04 06:28:26 PM UTC 24 Sep 04 06:29:15 PM UTC 24 384823978 ps
T1977 /workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/48.xbar_same_source.3375737351 Sep 04 06:28:35 PM UTC 24 Sep 04 06:29:15 PM UTC 24 370796689 ps
T1978 /workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/48.xbar_unmapped_addr.2785845174 Sep 04 06:28:50 PM UTC 24 Sep 04 06:29:19 PM UTC 24 207105374 ps
T1979 /workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/48.xbar_smoke_large_delays.2795983338 Sep 04 06:28:18 PM UTC 24 Sep 04 06:29:36 PM UTC 24 8130992845 ps
T1980 /workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/49.xbar_smoke.75545286 Sep 04 06:29:27 PM UTC 24 Sep 04 06:29:37 PM UTC 24 55550153 ps
T1981 /workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/49.xbar_smoke_zero_delays.2067983563 Sep 04 06:29:32 PM UTC 24 Sep 04 06:29:41 PM UTC 24 42984962 ps
T1982 /workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/48.xbar_stress_all_with_rand_reset.530977495 Sep 04 06:29:09 PM UTC 24 Sep 04 06:29:42 PM UTC 24 26571746 ps
T1983 /workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/48.xbar_error_and_unmapped_addr.3309345245 Sep 04 06:29:04 PM UTC 24 Sep 04 06:29:51 PM UTC 24 310374156 ps
T1984 /workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/48.xbar_error_random.1767631507 Sep 04 06:28:35 PM UTC 24 Sep 04 06:29:54 PM UTC 24 2380053317 ps
T1985 /workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/43.xbar_stress_all_with_rand_reset.3250654970 Sep 04 06:22:47 PM UTC 24 Sep 04 06:30:13 PM UTC 24 812182603 ps
T1986 /workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/49.xbar_random_zero_delays.1179288891 Sep 04 06:29:49 PM UTC 24 Sep 04 06:30:15 PM UTC 24 197306997 ps
T1987 /workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/47.xbar_stress_all.1873579748 Sep 04 06:27:32 PM UTC 24 Sep 04 06:30:19 PM UTC 24 2069433990 ps
T1988 /workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/46.xbar_stress_all_with_rand_reset.366173548 Sep 04 06:26:14 PM UTC 24 Sep 04 06:30:22 PM UTC 24 2553130750 ps
T1989 /workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/40.xbar_random_large_delays.4251828221 Sep 04 06:19:32 PM UTC 24 Sep 04 06:30:26 PM UTC 24 58632420926 ps
T1990 /workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/48.xbar_smoke_slow_rsp.4016398169 Sep 04 06:28:25 PM UTC 24 Sep 04 06:30:42 PM UTC 24 6995098572 ps
T1991 /workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/46.xbar_stress_all_with_error.3811575882 Sep 04 06:26:33 PM UTC 24 Sep 04 06:30:44 PM UTC 24 3417783441 ps
T1992 /workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/70.xbar_error_random.2210940942 Sep 04 06:57:10 PM UTC 24 Sep 04 06:57:44 PM UTC 24 323388346 ps
T1993 /workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/49.xbar_smoke_large_delays.1858421014 Sep 04 06:29:30 PM UTC 24 Sep 04 06:30:47 PM UTC 24 6796601126 ps
T1994 /workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/49.xbar_access_same_device_slow_rsp.2580375735 Sep 04 06:30:13 PM UTC 24 Sep 04 06:30:59 PM UTC 24 2734072509 ps
T1995 /workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/47.xbar_stress_all_with_rand_reset.2722879047 Sep 04 06:27:43 PM UTC 24 Sep 04 06:31:00 PM UTC 24 4977260021 ps
T1996 /workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/49.xbar_same_source.3329773903 Sep 04 06:30:23 PM UTC 24 Sep 04 06:31:03 PM UTC 24 1315902238 ps
T1997 /workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/49.xbar_error_random.1715876810 Sep 04 06:30:26 PM UTC 24 Sep 04 06:31:17 PM UTC 24 594952600 ps
T854 /workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/46.xbar_stress_all.3406541190 Sep 04 06:26:10 PM UTC 24 Sep 04 06:31:19 PM UTC 24 9600565504 ps
T1998 /workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/50.xbar_smoke.230748060 Sep 04 06:31:16 PM UTC 24 Sep 04 06:31:24 PM UTC 24 122090453 ps
T1999 /workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/49.xbar_error_and_unmapped_addr.3742321715 Sep 04 06:30:47 PM UTC 24 Sep 04 06:31:27 PM UTC 24 260963465 ps
T2000 /workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/50.xbar_smoke_zero_delays.2486837323 Sep 04 06:31:18 PM UTC 24 Sep 04 06:31:27 PM UTC 24 38438173 ps
T2001 /workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/49.xbar_random.1754611500 Sep 04 06:29:47 PM UTC 24 Sep 04 06:31:39 PM UTC 24 2207147347 ps
T2002 /workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/49.xbar_unmapped_addr.2973477640 Sep 04 06:30:44 PM UTC 24 Sep 04 06:31:42 PM UTC 24 1084308687 ps
T2003 /workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/49.xbar_smoke_slow_rsp.3950017020 Sep 04 06:29:45 PM UTC 24 Sep 04 06:31:49 PM UTC 24 6259594322 ps
T2004 /workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/48.xbar_stress_all.581504150 Sep 04 06:29:08 PM UTC 24 Sep 04 06:31:53 PM UTC 24 1280812586 ps
T2005 /workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/45.xbar_random_slow_rsp.2018084638 Sep 04 06:24:37 PM UTC 24 Sep 04 06:31:58 PM UTC 24 28576873199 ps
T2006 /workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/46.xbar_random_large_delays.151639169 Sep 04 06:25:54 PM UTC 24 Sep 04 06:32:02 PM UTC 24 37730447484 ps
T2007 /workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/50.xbar_random.2235386301 Sep 04 06:31:35 PM UTC 24 Sep 04 06:32:03 PM UTC 24 219180248 ps
T2008 /workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/49.xbar_access_same_device.3317340920 Sep 04 06:30:13 PM UTC 24 Sep 04 06:32:09 PM UTC 24 2281066800 ps
T2009 /workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/50.xbar_random_zero_delays.1435173823 Sep 04 06:31:48 PM UTC 24 Sep 04 06:32:11 PM UTC 24 175486658 ps
T2010 /workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/38.xbar_random_large_delays.3919927011 Sep 04 06:17:08 PM UTC 24 Sep 04 06:32:16 PM UTC 24 75844909617 ps
T2011 /workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/48.xbar_stress_all_with_error.590098546 Sep 04 06:29:13 PM UTC 24 Sep 04 06:32:20 PM UTC 24 3012286221 ps
T796 /workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/30.xbar_access_same_device_slow_rsp.462675782 Sep 04 06:05:46 PM UTC 24 Sep 04 06:32:21 PM UTC 24 96575411498 ps
T2012 /workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/50.xbar_same_source.614792741 Sep 04 06:32:06 PM UTC 24 Sep 04 06:32:26 PM UTC 24 175455316 ps
T2013 /workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/50.xbar_access_same_device.2311233358 Sep 04 06:31:58 PM UTC 24 Sep 04 06:32:32 PM UTC 24 434172172 ps
T2014 /workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/50.xbar_error_random.1278529052 Sep 04 06:32:14 PM UTC 24 Sep 04 06:32:35 PM UTC 24 223385677 ps
T2015 /workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/0.chip_csr_aliasing.1659281967 Sep 04 05:00:51 PM UTC 24 Sep 04 06:32:35 PM UTC 24 31313170980 ps
T2016 /workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/50.xbar_unmapped_addr.4022402458 Sep 04 06:32:20 PM UTC 24 Sep 04 06:32:47 PM UTC 24 391270040 ps
T2017 /workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/51.xbar_smoke_zero_delays.3693921731 Sep 04 06:32:40 PM UTC 24 Sep 04 06:32:50 PM UTC 24 39134884 ps
T2018 /workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/50.xbar_error_and_unmapped_addr.901275825 Sep 04 06:32:24 PM UTC 24 Sep 04 06:32:54 PM UTC 24 485448813 ps
T2019 /workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/51.xbar_smoke.4148873969 Sep 04 06:32:41 PM UTC 24 Sep 04 06:32:54 PM UTC 24 186457558 ps
T2020 /workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/50.xbar_smoke_large_delays.1882328386 Sep 04 06:31:31 PM UTC 24 Sep 04 06:32:59 PM UTC 24 8227151183 ps
T2021 /workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/50.xbar_smoke_slow_rsp.1332548366 Sep 04 06:31:20 PM UTC 24 Sep 04 06:33:02 PM UTC 24 4358668507 ps
T2022 /workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/32.xbar_access_same_device_slow_rsp.3796569407 Sep 04 06:09:07 PM UTC 24 Sep 04 06:33:14 PM UTC 24 91285090037 ps
T2023 /workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/51.xbar_random_zero_delays.2920870594 Sep 04 06:33:02 PM UTC 24 Sep 04 06:33:21 PM UTC 24 133568439 ps
T2024 /workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/50.xbar_stress_all_with_error.2648390230 Sep 04 06:32:35 PM UTC 24 Sep 04 06:33:40 PM UTC 24 915862821 ps
T2025 /workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/51.xbar_error_random.1727105869 Sep 04 06:33:26 PM UTC 24 Sep 04 06:33:50 PM UTC 24 774791122 ps
T2026 /workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/51.xbar_random.1195973616 Sep 04 06:32:58 PM UTC 24 Sep 04 06:33:51 PM UTC 24 992085550 ps
T2027 /workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/51.xbar_smoke_slow_rsp.1285900641 Sep 04 06:32:50 PM UTC 24 Sep 04 06:33:54 PM UTC 24 4275446220 ps
T2028 /workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/51.xbar_same_source.1794187984 Sep 04 06:33:25 PM UTC 24 Sep 04 06:33:58 PM UTC 24 302032908 ps
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