| T1068 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_keymgr_key_derivation_prod.3690963719 |
|
|
Sep 04 10:19:33 PM UTC 24 |
Sep 04 11:02:18 PM UTC 24 |
12998208472 ps |
| T29 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_sleep_pin_mio_dio_val.1153690186 |
|
|
Sep 04 10:58:42 PM UTC 24 |
Sep 04 11:03:05 PM UTC 24 |
2786459518 ps |
| T72 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_sleep_pin_wake.1919596689 |
|
|
Sep 04 10:59:54 PM UTC 24 |
Sep 04 11:04:06 PM UTC 24 |
2884733260 ps |
| T355 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_pattgen_ios.880434456 |
|
|
Sep 04 11:01:00 PM UTC 24 |
Sep 04 11:04:51 PM UTC 24 |
2987605288 ps |
| T429 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_flash_ctrl_mem_protection.3278269215 |
|
|
Sep 04 10:49:23 PM UTC 24 |
Sep 04 11:06:13 PM UTC 24 |
4978977724 ps |
| T76 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_sleep_pin_retention.2695699980 |
|
|
Sep 04 11:00:18 PM UTC 24 |
Sep 04 11:06:25 PM UTC 24 |
4018065550 ps |
| T48 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_spi_host_tx_rx.2305160475 |
|
|
Sep 04 11:03:06 PM UTC 24 |
Sep 04 11:07:24 PM UTC 24 |
2789631696 ps |
| T292 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_data_integrity_escalation.2218100097 |
|
|
Sep 04 10:58:41 PM UTC 24 |
Sep 04 11:08:01 PM UTC 24 |
4624282658 ps |
| T430 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_uart_tx_rx_idx3.1659327437 |
|
|
Sep 04 11:00:27 PM UTC 24 |
Sep 04 11:08:40 PM UTC 24 |
3963132374 ps |
| T431 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_otbn_ecdsa_op_irq.368154857 |
|
|
Sep 04 10:05:00 PM UTC 24 |
Sep 04 11:09:12 PM UTC 24 |
16995202916 ps |
| T78 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_spi_device_pinmux_sleep_retention.1053008274 |
|
|
Sep 04 11:03:09 PM UTC 24 |
Sep 04 11:09:35 PM UTC 24 |
3863092358 ps |
| T432 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_uart_tx_rx.187077409 |
|
|
Sep 04 11:01:03 PM UTC 24 |
Sep 04 11:10:04 PM UTC 24 |
3953537384 ps |
| T1069 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_rstmgr_rst_cnsty_escalation.2286749634 |
|
|
Sep 04 10:58:41 PM UTC 24 |
Sep 04 11:10:06 PM UTC 24 |
6406451964 ps |
| T356 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_all_escalation_resets.3726965592 |
|
|
Sep 04 10:58:40 PM UTC 24 |
Sep 04 11:10:48 PM UTC 24 |
5839419710 ps |
| T1070 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_uart_tx_rx_idx2.1898738237 |
|
|
Sep 04 11:01:25 PM UTC 24 |
Sep 04 11:10:50 PM UTC 24 |
3987728722 ps |
| T1071 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_uart_tx_rx_alt_clk_freq.2033371607 |
|
|
Sep 04 11:01:42 PM UTC 24 |
Sep 04 11:11:10 PM UTC 24 |
3759277231 ps |
| T1072 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_keymgr_key_derivation_jitter_en_reduced_freq.2112935609 |
|
|
Sep 04 10:42:56 PM UTC 24 |
Sep 04 11:11:16 PM UTC 24 |
10394496017 ps |
| T67 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_power_virus.1110717364 |
|
|
Sep 04 10:49:31 PM UTC 24 |
Sep 04 11:11:21 PM UTC 24 |
5726237978 ps |
| T126 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_uart_tx_rx_idx1.3804742663 |
|
|
Sep 04 11:01:38 PM UTC 24 |
Sep 04 11:11:28 PM UTC 24 |
4701902282 ps |
| T1073 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_uart_tx_rx_alt_clk_freq_low_speed.396256972 |
|
|
Sep 04 11:02:17 PM UTC 24 |
Sep 04 11:11:39 PM UTC 24 |
4386645670 ps |
| T1074 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_i2c_device_tx_rx.1963928626 |
|
|
Sep 04 11:02:49 PM UTC 24 |
Sep 04 11:11:51 PM UTC 24 |
4230681668 ps |
| T52 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_spi_device_tpm.4093791352 |
|
|
Sep 04 11:03:04 PM UTC 24 |
Sep 04 11:12:01 PM UTC 24 |
4115158240 ps |
| T218 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_spi_device_pass_through.2900643885 |
|
|
Sep 04 11:03:51 PM UTC 24 |
Sep 04 11:13:30 PM UTC 24 |
5788980838 ps |
| T44 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_gpio.2799507348 |
|
|
Sep 04 11:05:36 PM UTC 24 |
Sep 04 11:13:46 PM UTC 24 |
4245105738 ps |
| T219 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_spi_device_pass_through_collision.3552213744 |
|
|
Sep 04 11:04:52 PM UTC 24 |
Sep 04 11:14:41 PM UTC 24 |
4514865591 ps |
| T250 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_flash_init_reduced_freq.1366943623 |
|
|
Sep 04 10:43:36 PM UTC 24 |
Sep 04 11:15:20 PM UTC 24 |
19575987660 ps |
| T1075 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_otbn_smoketest.3360001364 |
|
|
Sep 04 10:51:46 PM UTC 24 |
Sep 04 11:16:04 PM UTC 24 |
7600446844 ps |
| T352 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_i2c_host_tx_rx_idx2.2189988656 |
|
|
Sep 04 11:02:52 PM UTC 24 |
Sep 04 11:16:10 PM UTC 24 |
5530743446 ps |
| T1076 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_lc_ctrl_otp_hw_cfg0.1393040468 |
|
|
Sep 04 11:11:41 PM UTC 24 |
Sep 04 11:16:24 PM UTC 24 |
2963637634 ps |
| T1077 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_flash_ctrl_ops_jitter_en.358338501 |
|
|
Sep 04 11:07:12 PM UTC 24 |
Sep 04 11:16:25 PM UTC 24 |
4352048447 ps |
| T253 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_flash_ctrl_lc_rw_en.3292529050 |
|
|
Sep 04 11:08:09 PM UTC 24 |
Sep 04 11:16:43 PM UTC 24 |
4437235125 ps |
| T1078 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_flash_ctrl_idle_low_power.2530316785 |
|
|
Sep 04 11:09:56 PM UTC 24 |
Sep 04 11:16:43 PM UTC 24 |
3904226336 ps |
| T1079 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_kmac_entropy.3065777956 |
|
|
Sep 04 11:11:40 PM UTC 24 |
Sep 04 11:17:07 PM UTC 24 |
2742329088 ps |
| T1080 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_i2c_host_tx_rx_idx1.1949620367 |
|
|
Sep 04 11:02:22 PM UTC 24 |
Sep 04 11:17:12 PM UTC 24 |
4147268980 ps |
| T185 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_otp_ctrl_vendor_test_csr_access.3778125158 |
|
|
Sep 04 11:12:58 PM UTC 24 |
Sep 04 11:17:12 PM UTC 24 |
2897211157 ps |
| T1081 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_lc_ctrl_rand_to_scrap.1809760324 |
|
|
Sep 04 11:13:17 PM UTC 24 |
Sep 04 11:17:42 PM UTC 24 |
2908486239 ps |
| T1082 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_lc_ctrl_volatile_raw_unlock.1434026852 |
|
|
Sep 04 11:16:01 PM UTC 24 |
Sep 04 11:18:15 PM UTC 24 |
2543014927 ps |
| T354 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_i2c_host_tx_rx.4031913942 |
|
|
Sep 04 11:02:48 PM UTC 24 |
Sep 04 11:18:17 PM UTC 24 |
5890931736 ps |
| T1083 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_otp_ctrl_ecc_error_vendor_test.282290111 |
|
|
Sep 04 11:13:14 PM UTC 24 |
Sep 04 11:18:29 PM UTC 24 |
2869337969 ps |
| T362 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_flash_ctrl_ops.645391526 |
|
|
Sep 04 11:07:08 PM UTC 24 |
Sep 04 11:19:05 PM UTC 24 |
3966851320 ps |
| T136 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_ast_clk_rst_inputs.2273593453 |
|
|
Sep 04 10:47:30 PM UTC 24 |
Sep 04 11:20:23 PM UTC 24 |
15151717704 ps |
| T1084 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz.660786686 |
|
|
Sep 04 11:18:08 PM UTC 24 |
Sep 04 11:20:28 PM UTC 24 |
2276563164 ps |
| T1085 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_sleep_pwm_pulses.215856264 |
|
|
Sep 04 11:00:59 PM UTC 24 |
Sep 04 11:20:33 PM UTC 24 |
9233880440 ps |
| T1086 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_rstmgr_sw_rst.1843246162 |
|
|
Sep 04 11:18:34 PM UTC 24 |
Sep 04 11:21:59 PM UTC 24 |
2221579184 ps |
| T1087 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_flash_ctrl_access_jitter_en.4045800209 |
|
|
Sep 04 11:09:25 PM UTC 24 |
Sep 04 11:23:57 PM UTC 24 |
5336307608 ps |
| T1088 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_otp_ctrl_lc_signals_test_unlocked0.3072087627 |
|
|
Sep 04 11:13:22 PM UTC 24 |
Sep 04 11:24:13 PM UTC 24 |
4998074768 ps |
| T1089 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_pwrmgr_full_aon_reset.3288805928 |
|
|
Sep 04 11:18:37 PM UTC 24 |
Sep 04 11:26:30 PM UTC 24 |
6729098908 ps |
| T1090 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_lc_walkthrough_rma.3711617433 |
|
|
Sep 04 09:53:11 PM UTC 24 |
Sep 04 11:26:40 PM UTC 24 |
46441546052 ps |
| T1091 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_pwrmgr_main_power_glitch_reset.567529603 |
|
|
Sep 04 11:18:27 PM UTC 24 |
Sep 04 11:26:50 PM UTC 24 |
5459846124 ps |
| T1092 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_kmac_mode_kmac_jitter_en.1932709368 |
|
|
Sep 04 11:52:17 PM UTC 24 |
Sep 04 11:57:05 PM UTC 24 |
3125253058 ps |
| T1093 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_flash_ctrl_access.1570442109 |
|
|
Sep 04 11:08:46 PM UTC 24 |
Sep 04 11:27:04 PM UTC 24 |
5659930006 ps |
| T1094 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_flash_rma_unlocked.914495771 |
|
|
Sep 04 09:47:08 PM UTC 24 |
Sep 04 11:27:22 PM UTC 24 |
43960416338 ps |
| T1095 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_rstmgr_sw_req.2378803794 |
|
|
Sep 04 11:18:09 PM UTC 24 |
Sep 04 11:27:45 PM UTC 24 |
5223863870 ps |
| T1096 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_flash_ctrl_clock_freqs.3812081097 |
|
|
Sep 04 11:10:56 PM UTC 24 |
Sep 04 11:27:58 PM UTC 24 |
5810436477 ps |
| T1097 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_lc_ctrl_transition.4225858544 |
|
|
Sep 04 11:13:25 PM UTC 24 |
Sep 04 11:28:05 PM UTC 24 |
12209614043 ps |
| T1098 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/0.rom_e2e_self_hash.554116704 |
|
|
Sep 04 09:23:26 PM UTC 24 |
Sep 04 11:28:11 PM UTC 24 |
26594673152 ps |
| T1099 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_otbn_ecdsa_op_irq_jitter_en.1968153330 |
|
|
Sep 04 10:06:53 PM UTC 24 |
Sep 04 11:28:15 PM UTC 24 |
18908618612 ps |
| T641 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_pwrmgr_sleep_disabled.1762489224 |
|
|
Sep 04 11:24:57 PM UTC 24 |
Sep 04 11:29:17 PM UTC 24 |
2661516464 ps |
| T259 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_rstmgr_cpu_info.2925285380 |
|
|
Sep 04 11:18:30 PM UTC 24 |
Sep 04 11:30:36 PM UTC 24 |
5543106110 ps |
| T1100 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_pwrmgr_deep_sleep_power_glitch_reset.1958050134 |
|
|
Sep 04 11:22:43 PM UTC 24 |
Sep 04 11:30:47 PM UTC 24 |
6492693870 ps |
| T1101 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_pwrmgr_deep_sleep_por_reset.787248831 |
|
|
Sep 04 11:21:31 PM UTC 24 |
Sep 04 11:31:19 PM UTC 24 |
7644638930 ps |
| T244 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_keymgr_sideload_otbn.2049292166 |
|
|
Sep 04 10:21:54 PM UTC 24 |
Sep 04 11:31:31 PM UTC 24 |
14085419780 ps |
| T1102 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_pwrmgr_normal_sleep_por_reset.4027610015 |
|
|
Sep 04 11:21:32 PM UTC 24 |
Sep 04 11:32:04 PM UTC 24 |
6668316129 ps |
| T1103 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_pwrmgr_sysrst_ctrl_reset.2514891698 |
|
|
Sep 04 11:18:37 PM UTC 24 |
Sep 04 11:32:12 PM UTC 24 |
6085264643 ps |
| T1104 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_rv_timer_irq.2005369181 |
|
|
Sep 04 11:27:48 PM UTC 24 |
Sep 04 11:33:20 PM UTC 24 |
3073683808 ps |
| T1105 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_otp_ctrl_lc_signals_rma.1724626719 |
|
|
Sep 04 11:13:22 PM UTC 24 |
Sep 04 11:33:41 PM UTC 24 |
8751764640 ps |
| T1106 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_otp_ctrl_lc_signals_dev.2700261315 |
|
|
Sep 04 11:13:26 PM UTC 24 |
Sep 04 11:34:16 PM UTC 24 |
7544198080 ps |
| T1107 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_sysrst_ctrl_inputs.3145289416 |
|
|
Sep 04 11:28:30 PM UTC 24 |
Sep 04 11:34:33 PM UTC 24 |
3361062338 ps |
| T1108 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_aon_timer_irq.147780590 |
|
|
Sep 04 11:29:20 PM UTC 24 |
Sep 04 11:34:56 PM UTC 24 |
3580756220 ps |
| T1109 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_lc_walkthrough_prodend.692153468 |
|
|
Sep 04 11:15:27 PM UTC 24 |
Sep 04 11:35:29 PM UTC 24 |
9795809513 ps |
| T1110 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_sysrst_ctrl_outputs.925373023 |
|
|
Sep 04 11:29:25 PM UTC 24 |
Sep 04 11:35:47 PM UTC 24 |
3833855868 ps |
| T1111 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_lc_walkthrough_dev.3429642444 |
|
|
Sep 04 09:50:53 PM UTC 24 |
Sep 04 11:36:18 PM UTC 24 |
49327810406 ps |
| T1112 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_pwrmgr_usb_clk_disabled_when_active.1405839642 |
|
|
Sep 04 11:27:33 PM UTC 24 |
Sep 04 11:36:35 PM UTC 24 |
4776765380 ps |
| T1113 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_aon_timer_sleep_wdog_sleep_pause.894997308 |
|
|
Sep 04 11:29:26 PM UTC 24 |
Sep 04 11:37:33 PM UTC 24 |
7151256240 ps |
| T1114 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_otp_ctrl_lc_signals_prod.2764798340 |
|
|
Sep 04 11:13:25 PM UTC 24 |
Sep 04 11:38:59 PM UTC 24 |
8043206580 ps |
| T50 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_sysrst_ctrl_ulp_z3_wakeup.1567654577 |
|
|
Sep 04 11:28:51 PM UTC 24 |
Sep 04 11:39:45 PM UTC 24 |
7200089688 ps |
| T1115 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_sysrst_ctrl_in_irq.678812549 |
|
|
Sep 04 11:28:29 PM UTC 24 |
Sep 04 11:39:59 PM UTC 24 |
5027810762 ps |
| T1116 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_aes_enc.1675929356 |
|
|
Sep 04 11:35:16 PM UTC 24 |
Sep 04 11:40:02 PM UTC 24 |
3138222866 ps |
| T1117 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_aes_idle.1522633254 |
|
|
Sep 04 11:36:12 PM UTC 24 |
Sep 04 11:40:06 PM UTC 24 |
2547564410 ps |
| T1118 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_aes_enc_jitter_en.13803153 |
|
|
Sep 04 11:35:38 PM UTC 24 |
Sep 04 11:40:20 PM UTC 24 |
2795077053 ps |
| T1119 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_otbn_mem_scramble.2961832960 |
|
|
Sep 04 11:34:06 PM UTC 24 |
Sep 04 11:40:53 PM UTC 24 |
4035921768 ps |
| T1120 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_aon_timer_wdog_bite_reset.3209368165 |
|
|
Sep 04 11:29:55 PM UTC 24 |
Sep 04 11:40:56 PM UTC 24 |
8652046048 ps |
| T343 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_rstmgr_alert_info.1087410318 |
|
|
Sep 04 11:18:32 PM UTC 24 |
Sep 04 11:41:17 PM UTC 24 |
11724561712 ps |
| T1121 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_lc_walkthrough_prod.895179726 |
|
|
Sep 04 09:51:09 PM UTC 24 |
Sep 04 11:41:27 PM UTC 24 |
51262480416 ps |
| T1122 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_pwrmgr_normal_sleep_all_reset_reqs.3190402468 |
|
|
Sep 04 11:19:52 PM UTC 24 |
Sep 04 11:41:45 PM UTC 24 |
8774999341 ps |
| T1123 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_aes_masking_off.1649298785 |
|
|
Sep 04 11:36:33 PM UTC 24 |
Sep 04 11:42:13 PM UTC 24 |
3580560864 ps |
| T75 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_alert_test.3308232464 |
|
|
Sep 04 11:37:04 PM UTC 24 |
Sep 04 11:42:36 PM UTC 24 |
3620251688 ps |
| T1124 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_pwrmgr_wdog_reset.1822188701 |
|
|
Sep 04 11:31:35 PM UTC 24 |
Sep 04 11:42:48 PM UTC 24 |
3769152498 ps |
| T1125 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_pwrmgr_all_reset_reqs.1969481689 |
|
|
Sep 04 11:19:23 PM UTC 24 |
Sep 04 11:43:13 PM UTC 24 |
12372268403 ps |
| T1126 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_aon_timer_wdog_lc_escalate.125275420 |
|
|
Sep 04 11:31:36 PM UTC 24 |
Sep 04 11:43:41 PM UTC 24 |
5589687300 ps |
| T358 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_alert_handler_ping_timeout.3038440902 |
|
|
Sep 04 11:38:19 PM UTC 24 |
Sep 04 11:43:52 PM UTC 24 |
3312425870 ps |
| T1127 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_pwrmgr_deep_sleep_all_reset_reqs.4085250192 |
|
|
Sep 04 11:19:26 PM UTC 24 |
Sep 04 11:43:53 PM UTC 24 |
16449324850 ps |
| T1128 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/1.rom_e2e_asm_init_test_unlocked0.3045533093 |
|
|
Sep 04 10:50:31 PM UTC 24 |
Sep 04 11:44:46 PM UTC 24 |
11141557752 ps |
| T1129 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_adc_ctrl_sleep_debug_cable_wakeup.1290866074 |
|
|
Sep 04 11:32:15 PM UTC 24 |
Sep 04 11:44:53 PM UTC 24 |
20053745460 ps |
| T1130 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_alert_handler_escalation.2345641371 |
|
|
Sep 04 11:37:19 PM UTC 24 |
Sep 04 11:45:09 PM UTC 24 |
5393719480 ps |
| T1131 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_entropy_src_kat_test.2245175831 |
|
|
Sep 04 11:42:12 PM UTC 24 |
Sep 04 11:45:52 PM UTC 24 |
2809504364 ps |
| T1132 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_alert_handler_entropy.2957499515 |
|
|
Sep 04 11:41:48 PM UTC 24 |
Sep 04 11:46:11 PM UTC 24 |
2852863552 ps |
| T1133 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_aes_entropy.3072647580 |
|
|
Sep 04 11:42:08 PM UTC 24 |
Sep 04 11:46:38 PM UTC 24 |
2495219500 ps |
| T1134 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_entropy_src_ast_rng_req.2980961624 |
|
|
Sep 04 11:44:50 PM UTC 24 |
Sep 04 11:47:47 PM UTC 24 |
2617305696 ps |
| T1135 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_csrng_kat_test.1196907882 |
|
|
Sep 04 11:44:03 PM UTC 24 |
Sep 04 11:48:05 PM UTC 24 |
2663120800 ps |
| T1136 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_alert_handler_lpg_sleep_mode_alerts.1984642836 |
|
|
Sep 04 11:41:21 PM UTC 24 |
Sep 04 11:48:39 PM UTC 24 |
4378019132 ps |
| T1137 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_uart_rand_baudrate.831727327 |
|
|
Sep 04 11:01:43 PM UTC 24 |
Sep 04 11:49:13 PM UTC 24 |
12852248024 ps |
| T1138 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_otbn_randomness.3110121293 |
|
|
Sep 04 11:32:18 PM UTC 24 |
Sep 04 11:49:20 PM UTC 24 |
6455512032 ps |
| T227 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_inject_scramble_seed.4161951809 |
|
|
Sep 04 07:35:31 PM UTC 24 |
Sep 04 11:49:48 PM UTC 24 |
63961820024 ps |
| T1139 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/1.rom_e2e_shutdown_output.3319807568 |
|
|
Sep 04 10:49:05 PM UTC 24 |
Sep 04 11:49:57 PM UTC 24 |
25949658200 ps |
| T656 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_rv_core_ibex_nmi_irq.2372787809 |
|
|
Sep 04 11:35:01 PM UTC 24 |
Sep 04 11:50:04 PM UTC 24 |
4613326894 ps |
| T252 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_flash_init.494012482 |
|
|
Sep 04 11:10:13 PM UTC 24 |
Sep 04 11:50:32 PM UTC 24 |
21097521416 ps |
| T1140 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_hmac_enc.3031809834 |
|
|
Sep 04 11:45:57 PM UTC 24 |
Sep 04 11:51:07 PM UTC 24 |
2240574658 ps |
| T1141 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_rv_core_ibex_rnd.4077715596 |
|
|
Sep 04 11:34:23 PM UTC 24 |
Sep 04 11:51:17 PM UTC 24 |
4999985696 ps |
| T1142 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_hmac_enc_jitter_en.310684586 |
|
|
Sep 04 11:46:39 PM UTC 24 |
Sep 04 11:51:27 PM UTC 24 |
3072856142 ps |
| T614 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_edn_boot_mode.2041818492 |
|
|
Sep 04 11:42:28 PM UTC 24 |
Sep 04 11:52:43 PM UTC 24 |
3087990786 ps |
| T1143 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_hmac_enc_idle.4011216531 |
|
|
Sep 04 11:46:57 PM UTC 24 |
Sep 04 11:53:19 PM UTC 24 |
3102843496 ps |
| T1144 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_edn_kat.1383344229 |
|
|
Sep 04 11:42:59 PM UTC 24 |
Sep 04 11:53:44 PM UTC 24 |
3272917352 ps |
| T1145 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_hmac_oneshot.4253823481 |
|
|
Sep 04 11:47:21 PM UTC 24 |
Sep 04 11:53:44 PM UTC 24 |
3216812746 ps |
| T1146 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_sysrst_ctrl_reset.3661319001 |
|
|
Sep 04 11:29:07 PM UTC 24 |
Sep 04 11:54:23 PM UTC 24 |
22719807168 ps |
| T1147 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_csrng_fuse_en_sw_app_read_test.647779454 |
|
|
Sep 04 11:44:46 PM UTC 24 |
Sep 04 11:54:57 PM UTC 24 |
5817374402 ps |
| T1148 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_csrng_lc_hw_debug_en_test.1628654087 |
|
|
Sep 04 11:44:02 PM UTC 24 |
Sep 04 11:55:28 PM UTC 24 |
7309796138 ps |
| T1149 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/1.rom_e2e_keymgr_init_rom_ext_meas.1042080361 |
|
|
Sep 04 10:50:59 PM UTC 24 |
Sep 04 11:55:34 PM UTC 24 |
14837838778 ps |
| T1150 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_kmac_mode_cshake.2641342241 |
|
|
Sep 04 11:51:00 PM UTC 24 |
Sep 04 11:56:24 PM UTC 24 |
2807732328 ps |
| T1151 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_kmac_app_rom.1844002052 |
|
|
Sep 04 11:52:17 PM UTC 24 |
Sep 04 11:56:33 PM UTC 24 |
2697120416 ps |
| T1152 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_kmac_mode_kmac.1530071567 |
|
|
Sep 04 11:51:18 PM UTC 24 |
Sep 04 11:57:03 PM UTC 24 |
2934468080 ps |
| T1153 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_kmac_idle.2613605207 |
|
|
Sep 04 11:52:16 PM UTC 24 |
Sep 04 11:57:42 PM UTC 24 |
3008377256 ps |
| T1154 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_edn_auto_mode.757572000 |
|
|
Sep 04 11:42:13 PM UTC 24 |
Sep 04 11:57:53 PM UTC 24 |
4569903120 ps |
| T1155 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_edn_entropy_reqs_jitter.2316411730 |
|
|
Sep 04 11:45:54 PM UTC 24 |
Sep 04 11:59:03 PM UTC 24 |
5956184905 ps |
| T1156 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_pwrmgr_random_sleep_all_reset_reqs.4222339193 |
|
|
Sep 04 11:19:22 PM UTC 24 |
Sep 04 11:59:26 PM UTC 24 |
23102243313 ps |
| T1157 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/1.rom_e2e_asm_init_rma.4157068834 |
|
|
Sep 04 10:50:53 PM UTC 24 |
Sep 04 11:59:44 PM UTC 24 |
14798618122 ps |
| T1158 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_sensor_ctrl_status.2361783000 |
|
|
Sep 04 11:56:14 PM UTC 24 |
Sep 05 12:00:05 AM UTC 24 |
2905473499 ps |
| T1159 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/1.rom_e2e_shutdown_exception_c.387560102 |
|
|
Sep 04 10:49:53 PM UTC 24 |
Sep 05 12:00:52 AM UTC 24 |
14458367198 ps |
| T1160 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/1.rom_e2e_asm_init_prod.124375400 |
|
|
Sep 04 10:50:40 PM UTC 24 |
Sep 05 12:01:40 AM UTC 24 |
15174505145 ps |
| T1161 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_alert_handler_ping_ok.983802011 |
|
|
Sep 04 11:39:45 PM UTC 24 |
Sep 05 12:01:47 AM UTC 24 |
8693408186 ps |
| T1162 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_alert_handler_lpg_clkoff.889514194 |
|
|
Sep 04 11:41:22 PM UTC 24 |
Sep 05 12:01:48 AM UTC 24 |
6114724812 ps |
| T1163 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/1.rom_e2e_keymgr_init_rom_ext_invalid_meas.2012361644 |
|
|
Sep 04 10:50:43 PM UTC 24 |
Sep 05 12:01:52 AM UTC 24 |
15175620162 ps |
| T1164 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/1.rom_e2e_asm_init_prod_end.406047211 |
|
|
Sep 04 10:48:13 PM UTC 24 |
Sep 05 12:01:54 AM UTC 24 |
15455197196 ps |
| T1165 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_sram_ctrl_scrambled_access.200083225 |
|
|
Sep 04 11:54:03 PM UTC 24 |
Sep 05 12:03:06 AM UTC 24 |
4380579108 ps |
| T1166 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/1.rom_e2e_smoke.4241431507 |
|
|
Sep 04 10:50:25 PM UTC 24 |
Sep 05 12:03:11 AM UTC 24 |
15017671468 ps |
| T161 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup.999617737 |
|
|
Sep 04 11:56:18 PM UTC 24 |
Sep 05 12:03:20 AM UTC 24 |
5062350176 ps |
| T1167 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/1.rom_e2e_asm_init_dev.4018134174 |
|
|
Sep 04 10:51:04 PM UTC 24 |
Sep 05 12:03:35 AM UTC 24 |
15378066300 ps |
| T1168 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_lc_walkthrough_testunlocks.1627896257 |
|
|
Sep 04 11:18:31 PM UTC 24 |
Sep 05 12:03:39 AM UTC 24 |
36581879248 ps |
| T271 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_plic_sw_irq.3056488675 |
|
|
Sep 04 11:58:38 PM UTC 24 |
Sep 05 12:03:58 AM UTC 24 |
3326961396 ps |
| T408 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_rom_ctrl_integrity_check.4161390062 |
|
|
Sep 04 11:53:28 PM UTC 24 |
Sep 05 12:04:12 AM UTC 24 |
9394785172 ps |
| T616 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq.2487655665 |
|
|
Sep 04 10:42:13 PM UTC 24 |
Sep 05 12:04:34 AM UTC 24 |
25387521474 ps |
| T1169 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_sram_ctrl_scrambled_access_jitter_en.3618601279 |
|
|
Sep 04 11:54:41 PM UTC 24 |
Sep 05 12:04:40 AM UTC 24 |
4867427668 ps |
| T1170 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_edn_entropy_reqs.1502701357 |
|
|
Sep 04 11:45:54 PM UTC 24 |
Sep 05 12:05:04 AM UTC 24 |
6552272420 ps |
| T181 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_plic_all_irqs_10.3561752100 |
|
|
Sep 04 11:58:02 PM UTC 24 |
Sep 05 12:06:08 AM UTC 24 |
3611695168 ps |
| T344 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_entropy_src_csrng.3772150529 |
|
|
Sep 04 11:44:51 PM UTC 24 |
Sep 05 12:06:14 AM UTC 24 |
6738575086 ps |
| T1171 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/1.rom_e2e_keymgr_init_rom_ext_no_meas.205366300 |
|
|
Sep 04 10:50:44 PM UTC 24 |
Sep 05 12:06:43 AM UTC 24 |
15410971424 ps |
| T1172 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_clkmgr_off_hmac_trans.4122842911 |
|
|
Sep 05 12:00:14 AM UTC 24 |
Sep 05 12:06:53 AM UTC 24 |
5315148200 ps |
| T1173 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_alert_handler_lpg_reset_toggle.4000816469 |
|
|
Sep 04 11:41:23 PM UTC 24 |
Sep 05 12:07:14 AM UTC 24 |
7582767996 ps |
| T1174 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_clkmgr_off_aes_trans.3731362186 |
|
|
Sep 04 11:59:47 PM UTC 24 |
Sep 05 12:07:26 AM UTC 24 |
4084667222 ps |
| T1175 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_sleep_sram_ret_contents_no_scramble.82950123 |
|
|
Sep 04 11:55:14 PM UTC 24 |
Sep 05 12:07:55 AM UTC 24 |
7272722240 ps |
| T1176 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_clkmgr_jitter.655844647 |
|
|
Sep 05 12:04:27 AM UTC 24 |
Sep 05 12:07:58 AM UTC 24 |
3182454232 ps |
| T310 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_sram_ctrl_execution_main.605631827 |
|
|
Sep 04 11:54:41 PM UTC 24 |
Sep 05 12:08:26 AM UTC 24 |
8819040744 ps |
| T1177 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_clkmgr_off_otbn_trans.2158151735 |
|
|
Sep 05 12:00:27 AM UTC 24 |
Sep 05 12:08:48 AM UTC 24 |
4540948956 ps |
| T1178 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_clkmgr_external_clk_src_for_lc.129728283 |
|
|
Sep 05 12:00:49 AM UTC 24 |
Sep 05 12:08:51 AM UTC 24 |
6046780438 ps |
| T221 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_jtag_csr_rw.2518925368 |
|
|
Sep 05 12:04:09 AM UTC 24 |
Sep 05 12:09:03 AM UTC 24 |
4573990115 ps |
| T1179 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_sleep_sram_ret_contents_scramble.2432590015 |
|
|
Sep 04 11:55:15 PM UTC 24 |
Sep 05 12:09:30 AM UTC 24 |
8317997374 ps |
| T1180 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_clkmgr_off_kmac_trans.505576981 |
|
|
Sep 05 12:00:14 AM UTC 24 |
Sep 05 12:09:35 AM UTC 24 |
5751230376 ps |
| T676 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_alert_handler_lpg_sleep_mode_pings.3420759873 |
|
|
Sep 04 11:41:45 PM UTC 24 |
Sep 05 12:09:37 AM UTC 24 |
14069237340 ps |
| T1181 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_keymgr_sideload_kmac.701560268 |
|
|
Sep 04 11:50:12 PM UTC 24 |
Sep 05 12:10:39 AM UTC 24 |
8585342130 ps |
| T320 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_plic_all_irqs_20.683199041 |
|
|
Sep 04 11:58:01 PM UTC 24 |
Sep 05 12:10:54 AM UTC 24 |
5387655660 ps |
| T1182 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_clkmgr_reset_frequency.760460837 |
|
|
Sep 05 12:04:23 AM UTC 24 |
Sep 05 12:11:12 AM UTC 24 |
3378349794 ps |
| T1183 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/1.rom_e2e_static_critical.1227426432 |
|
|
Sep 04 10:51:00 PM UTC 24 |
Sep 05 12:11:15 AM UTC 24 |
17376274884 ps |
| T1184 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_clkmgr_jitter_frequency.860100719 |
|
|
Sep 05 12:04:23 AM UTC 24 |
Sep 05 12:11:31 AM UTC 24 |
3272900904 ps |
| T1185 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0.2127737498 |
|
|
Sep 05 12:01:25 AM UTC 24 |
Sep 05 12:11:35 AM UTC 24 |
3666120040 ps |
| T165 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_sensor_ctrl_alert.240723652 |
|
|
Sep 04 11:55:41 PM UTC 24 |
Sep 05 12:12:44 AM UTC 24 |
8954416880 ps |
| T1186 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_clkmgr_external_clk_src_for_sw_slow_dev.2111115345 |
|
|
Sep 05 12:03:13 AM UTC 24 |
Sep 05 12:12:48 AM UTC 24 |
5328331480 ps |
| T1187 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_clkmgr_sleep_frequency.1670107941 |
|
|
Sep 05 12:04:27 AM UTC 24 |
Sep 05 12:13:22 AM UTC 24 |
4706260200 ps |
| T1188 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_clkmgr_external_clk_src_for_sw_fast_dev.3393027842 |
|
|
Sep 05 12:02:53 AM UTC 24 |
Sep 05 12:14:02 AM UTC 24 |
4557531386 ps |
| T374 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up.1959499161 |
|
|
Sep 05 12:07:40 AM UTC 24 |
Sep 05 12:14:07 AM UTC 24 |
5553027896 ps |
| T1189 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0.1166107261 |
|
|
Sep 05 12:03:09 AM UTC 24 |
Sep 05 12:14:08 AM UTC 24 |
4445313604 ps |
| T1190 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_clkmgr_external_clk_src_for_sw_fast_rma.2412251983 |
|
|
Sep 05 12:03:09 AM UTC 24 |
Sep 05 12:14:17 AM UTC 24 |
4358132162 ps |
| T423 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_pwrmgr_normal_sleep_all_wake_ups.2631617685 |
|
|
Sep 05 12:05:29 AM UTC 24 |
Sep 05 12:14:25 AM UTC 24 |
7963154792 ps |
| T1191 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_clkmgr_external_clk_src_for_sw_slow_rma.494095614 |
|
|
Sep 05 12:03:11 AM UTC 24 |
Sep 05 12:14:27 AM UTC 24 |
4829006700 ps |
| T116 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_rv_dm_ndm_reset_req.1905971458 |
|
|
Sep 05 12:08:08 AM UTC 24 |
Sep 05 12:14:39 AM UTC 24 |
4139452216 ps |
| T196 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_lc_ctrl_program_error.1673816512 |
|
|
Sep 05 12:05:26 AM UTC 24 |
Sep 05 12:14:48 AM UTC 24 |
3847638078 ps |
| T260 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_rv_core_ibex_address_translation.3983040057 |
|
|
Sep 05 12:10:37 AM UTC 24 |
Sep 05 12:14:50 AM UTC 24 |
2931674460 ps |
| T1192 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_rv_dm_ndm_reset_req_when_cpu_halted.1393381720 |
|
|
Sep 05 12:08:11 AM UTC 24 |
Sep 05 12:14:58 AM UTC 24 |
4338592320 ps |
| T1193 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_rv_dm_access_after_wakeup.1479129077 |
|
|
Sep 05 12:08:50 AM UTC 24 |
Sep 05 12:14:59 AM UTC 24 |
5451712264 ps |
| T1194 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_clkmgr_jitter_reduced_freq.3972550714 |
|
|
Sep 05 12:12:36 AM UTC 24 |
Sep 05 12:15:14 AM UTC 24 |
2642369374 ps |
| T305 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_rv_core_ibex_icache_invalidate.994173564 |
|
|
Sep 05 12:10:38 AM UTC 24 |
Sep 05 12:15:32 AM UTC 24 |
2727753845 ps |
| T1195 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_pwrmgr_sleep_wake_5_bug.2131196811 |
|
|
Sep 05 12:07:40 AM UTC 24 |
Sep 05 12:15:32 AM UTC 24 |
5999801902 ps |
| T322 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_plic_all_irqs_0.2048706571 |
|
|
Sep 04 11:57:23 PM UTC 24 |
Sep 05 12:15:54 AM UTC 24 |
6479274856 ps |
| T1196 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_edn_sw_mode.2262517640 |
|
|
Sep 04 11:43:17 PM UTC 24 |
Sep 05 12:16:42 AM UTC 24 |
10601663664 ps |
| T1197 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_hmac_multistream.3567016106 |
|
|
Sep 04 11:48:30 PM UTC 24 |
Sep 05 12:16:49 AM UTC 24 |
8403631248 ps |
| T1198 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_hmac_enc_jitter_en_reduced_freq.266731175 |
|
|
Sep 05 12:13:36 AM UTC 24 |
Sep 05 12:16:58 AM UTC 24 |
2699062750 ps |
| T1199 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_tap_straps_testunlock0.2708826585 |
|
|
Sep 05 12:09:30 AM UTC 24 |
Sep 05 12:17:06 AM UTC 24 |
5214967229 ps |
| T1200 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_aes_enc_jitter_en_reduced_freq.2345997794 |
|
|
Sep 05 12:12:39 AM UTC 24 |
Sep 05 12:17:27 AM UTC 24 |
3180798446 ps |
| T626 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_rv_dm_access_after_escalation_reset.1203198996 |
|
|
Sep 05 12:08:50 AM UTC 24 |
Sep 05 12:17:57 AM UTC 24 |
5595097071 ps |
| T1201 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_flash_ctrl_write_clear.1338349976 |
|
|
Sep 05 12:12:39 AM UTC 24 |
Sep 05 12:18:19 AM UTC 24 |
3465869736 ps |
| T1202 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_kmac_mode_kmac_jitter_en_reduced_freq.2829485772 |
|
|
Sep 05 12:14:06 AM UTC 24 |
Sep 05 12:18:26 AM UTC 24 |
2691660242 ps |
| T1203 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_tap_straps_rma.4090886311 |
|
|
Sep 05 12:09:31 AM UTC 24 |
Sep 05 12:19:15 AM UTC 24 |
6621114974 ps |
| T1204 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_clkmgr_off_peri.1247284615 |
|
|
Sep 04 11:58:39 PM UTC 24 |
Sep 05 12:19:51 AM UTC 24 |
9095248932 ps |
| T1205 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_ast_clk_outputs.1337356345 |
|
|
Sep 05 12:04:55 AM UTC 24 |
Sep 05 12:20:11 AM UTC 24 |
7477730136 ps |
| T1206 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_flash_crash_alert.1354504189 |
|
|
Sep 05 12:11:55 AM UTC 24 |
Sep 05 12:21:43 AM UTC 24 |
4708591916 ps |
| T1207 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_keymgr_key_derivation_jitter_en.821488211 |
|
|
Sep 04 11:50:11 PM UTC 24 |
Sep 05 12:21:59 AM UTC 24 |
10764342465 ps |
| T1208 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/2.rom_volatile_raw_unlock.2946612218 |
|
|
Sep 05 12:20:09 AM UTC 24 |
Sep 05 12:22:07 AM UTC 24 |
2390311851 ps |
| T363 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_flash_ctrl_ops_jitter_en_reduced_freq.697204682 |
|
|
Sep 05 12:12:31 AM UTC 24 |
Sep 05 12:24:02 AM UTC 24 |
4925148175 ps |
| T1209 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/2.rom_raw_unlock.2313561854 |
|
|
Sep 05 12:19:44 AM UTC 24 |
Sep 05 12:24:06 AM UTC 24 |
6031728286 ps |
| T1210 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_flash_scrambling_smoketest.376657211 |
|
|
Sep 05 12:19:48 AM UTC 24 |
Sep 05 12:24:15 AM UTC 24 |
3458495852 ps |
| T1211 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq.4166494120 |
|
|
Sep 05 12:15:55 AM UTC 24 |
Sep 05 12:24:35 AM UTC 24 |
4074885424 ps |
| T1212 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_clkmgr_smoketest.3816656404 |
|
|
Sep 05 12:22:25 AM UTC 24 |
Sep 05 12:25:16 AM UTC 24 |
2923146612 ps |
| T242 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_keymgr_sideload_aes.858087463 |
|
|
Sep 04 11:50:55 PM UTC 24 |
Sep 05 12:25:46 AM UTC 24 |
10618662476 ps |
| T1213 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_aon_timer_smoketest.4284129018 |
|
|
Sep 05 12:21:07 AM UTC 24 |
Sep 05 12:25:47 AM UTC 24 |
2993858232 ps |
| T1214 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_tap_straps_dev.854153255 |
|
|
Sep 05 12:09:04 AM UTC 24 |
Sep 05 12:25:50 AM UTC 24 |
10356745659 ps |
| T1215 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_aes_smoketest.1810228174 |
|
|
Sep 05 12:21:00 AM UTC 24 |
Sep 05 12:29:38 AM UTC 24 |
3214727712 ps |
| T647 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_power_sleep_load.1771978135 |
|
|
Sep 05 12:19:50 AM UTC 24 |
Sep 05 12:29:38 AM UTC 24 |
4078588312 ps |
| T424 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_pwrmgr_deep_sleep_all_wake_ups.3572844292 |
|
|
Sep 05 12:07:08 AM UTC 24 |
Sep 05 12:29:38 AM UTC 24 |
23981622332 ps |
| T222 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_jtag_mem_access.2899759785 |
|
|
Sep 05 12:04:26 AM UTC 24 |
Sep 05 12:29:38 AM UTC 24 |
13300594796 ps |
| T1216 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_flash_ctrl_access_jitter_en_reduced_freq.438258209 |
|
|
Sep 05 12:12:44 AM UTC 24 |
Sep 05 12:29:38 AM UTC 24 |
7375110644 ps |
| T1217 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/2.rom_keymgr_functest.239361145 |
|
|
Sep 05 12:20:42 AM UTC 24 |
Sep 05 12:29:38 AM UTC 24 |
3901499214 ps |
| T1218 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_csrng_smoketest.2654255284 |
|
|
Sep 05 12:22:55 AM UTC 24 |
Sep 05 12:29:38 AM UTC 24 |
2621619234 ps |
| T1219 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_keymgr_key_derivation.4287700017 |
|
|
Sep 04 11:48:50 PM UTC 24 |
Sep 05 12:29:38 AM UTC 24 |
12433323680 ps |
| T1220 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_power_idle_load.1744808809 |
|
|
Sep 05 12:19:53 AM UTC 24 |
Sep 05 12:29:41 AM UTC 24 |
4073783084 ps |
| T1221 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_entropy_src_smoketest.2522559065 |
|
|
Sep 05 12:22:55 AM UTC 24 |
Sep 05 12:29:50 AM UTC 24 |
3070645434 ps |
| T1222 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_sysrst_ctrl_ec_rst_l.1052571404 |
|
|
Sep 04 11:29:23 PM UTC 24 |
Sep 05 12:30:52 AM UTC 24 |
20179829927 ps |
| T1223 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_keymgr_key_derivation_prod.2155429202 |
|
|
Sep 04 11:49:24 PM UTC 24 |
Sep 05 12:31:15 AM UTC 24 |
12511222920 ps |
| T118 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_pwrmgr_random_sleep_all_wake_ups.1793623872 |
|
|
Sep 05 12:07:09 AM UTC 24 |
Sep 05 12:31:48 AM UTC 24 |
24693810760 ps |
| T1224 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_flash_ctrl_mem_protection.170999673 |
|
|
Sep 05 12:18:32 AM UTC 24 |
Sep 05 12:33:33 AM UTC 24 |
5362181736 ps |
| T1225 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_gpio_smoketest.53715918 |
|
|
Sep 05 12:29:43 AM UTC 24 |
Sep 05 12:34:40 AM UTC 24 |
3013216302 ps |
| T1226 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_kmac_smoketest.1171112241 |
|
|
Sep 05 12:25:15 AM UTC 24 |
Sep 05 12:34:43 AM UTC 24 |
3194959328 ps |
| T1227 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_hmac_smoketest.2520806078 |
|
|
Sep 05 12:25:15 AM UTC 24 |
Sep 05 12:35:47 AM UTC 24 |
3361099752 ps |
| T1228 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_sram_ctrl_smoketest.3252820770 |
|
|
Sep 05 12:33:09 AM UTC 24 |
Sep 05 12:36:24 AM UTC 24 |
2547853096 ps |
| T1229 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_rstmgr_smoketest.3143285745 |
|
|
Sep 05 12:32:54 AM UTC 24 |
Sep 05 12:36:24 AM UTC 24 |
2608949096 ps |
| T1230 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_otp_ctrl_smoketest.1140975946 |
|
|
Sep 05 12:33:06 AM UTC 24 |
Sep 05 12:36:57 AM UTC 24 |
2443181924 ps |
| T1231 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_rv_timer_smoketest.1001297145 |
|
|
Sep 05 12:32:29 AM UTC 24 |
Sep 05 12:37:13 AM UTC 24 |
3524682794 ps |
| T1232 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_rv_plic_smoketest.3068538187 |
|
|
Sep 05 12:32:27 AM UTC 24 |
Sep 05 12:40:53 AM UTC 24 |
2512289384 ps |
| T1233 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_uart_smoketest.386156467 |
|
|
Sep 05 12:33:06 AM UTC 24 |
Sep 05 12:40:53 AM UTC 24 |
3169647800 ps |
| T1234 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_keymgr_key_derivation_jitter_en_reduced_freq.2065460876 |
|
|
Sep 05 12:13:37 AM UTC 24 |
Sep 05 12:40:53 AM UTC 24 |
11041460803 ps |
| T1235 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_pwrmgr_usbdev_smoketest.926087716 |
|
|
Sep 05 12:33:18 AM UTC 24 |
Sep 05 12:40:53 AM UTC 24 |
4865327416 ps |
| T1236 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_pwrmgr_b2b_sleep_reset_req.1839849904 |
|
|
Sep 04 11:57:22 PM UTC 24 |
Sep 05 12:40:53 AM UTC 24 |
25650305261 ps |
| T1237 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/3.chip_sw_lc_ctrl_transition.226090700 |
|
|
Sep 05 12:34:18 AM UTC 24 |
Sep 05 12:41:31 AM UTC 24 |
7185221280 ps |
| T359 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/3.chip_sw_data_integrity_escalation.4129554710 |
|
|
Sep 05 12:33:02 AM UTC 24 |
Sep 05 12:42:07 AM UTC 24 |
5688583540 ps |
| T1238 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/3.chip_sw_aon_timer_sleep_wdog_sleep_pause.1363060546 |
|
|
Sep 05 12:35:37 AM UTC 24 |
Sep 05 12:42:10 AM UTC 24 |
7215555700 ps |
| T1239 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/3.chip_sw_uart_tx_rx_idx1.330259459 |
|
|
Sep 05 12:33:16 AM UTC 24 |
Sep 05 12:42:50 AM UTC 24 |
3948134300 ps |
| T1240 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/3.chip_sw_uart_tx_rx.1297865028 |
|
|
Sep 05 12:32:42 AM UTC 24 |
Sep 05 12:43:02 AM UTC 24 |
4547894032 ps |
| T1241 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_pwrmgr_smoketest.4257596092 |
|
|
Sep 05 12:33:04 AM UTC 24 |
Sep 05 12:43:07 AM UTC 24 |
5642925960 ps |
| T1242 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_flash_rma_unlocked.90993059 |
|
|
Sep 04 11:10:54 PM UTC 24 |
Sep 05 12:43:10 AM UTC 24 |
44649366766 ps |
| T123 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_power_virus.3340406741 |
|
|
Sep 05 12:20:49 AM UTC 24 |
Sep 05 12:43:23 AM UTC 24 |
5767577078 ps |
| T761 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/3.chip_sw_alert_handler_lpg_sleep_mode_alerts.2539876159 |
|
|
Sep 05 12:35:37 AM UTC 24 |
Sep 05 12:43:38 AM UTC 24 |
4113739200 ps |
| T1243 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_otbn_ecdsa_op_irq.2217787696 |
|
|
Sep 04 11:33:01 PM UTC 24 |
Sep 05 12:44:08 AM UTC 24 |
17656378500 ps |
| T1244 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/3.chip_sw_uart_tx_rx_idx2.1522679847 |
|
|
Sep 05 12:33:14 AM UTC 24 |
Sep 05 12:44:09 AM UTC 24 |
4157003160 ps |
| T1245 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/3.chip_tap_straps_prod.1160969198 |
|
|
Sep 05 12:42:02 AM UTC 24 |
Sep 05 12:44:42 AM UTC 24 |
2873852704 ps |
| T1246 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/3.chip_sw_uart_tx_rx_idx3.3992506713 |
|
|
Sep 05 12:32:57 AM UTC 24 |
Sep 05 12:45:16 AM UTC 24 |
4342395228 ps |
| T1247 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_otbn_ecdsa_op_irq_jitter_en.49096487 |
|
|
Sep 04 11:33:02 PM UTC 24 |
Sep 05 12:45:26 AM UTC 24 |
19015860682 ps |
| T245 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_keymgr_sideload_otbn.2543390648 |
|
|
Sep 04 11:51:00 PM UTC 24 |
Sep 05 12:45:29 AM UTC 24 |
12976997860 ps |
| T1248 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_tap_straps_prod.2794372226 |
|
|
Sep 05 12:09:40 AM UTC 24 |
Sep 05 12:45:36 AM UTC 24 |
20173125849 ps |
| T1249 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_otbn_smoketest.918614733 |
|
|
Sep 05 12:29:44 AM UTC 24 |
Sep 05 12:45:47 AM UTC 24 |
5930385986 ps |
| T1250 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/3.chip_sw_all_escalation_resets.761732269 |
|
|
Sep 05 12:33:07 AM UTC 24 |
Sep 05 12:46:32 AM UTC 24 |
6912737336 ps |
| T1251 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/3.chip_tap_straps_rma.1239290075 |
|
|
Sep 05 12:40:55 AM UTC 24 |
Sep 05 12:47:33 AM UTC 24 |
4797341794 ps |
| T1252 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/4.chip_tap_straps_dev.1101025954 |
|
|
Sep 05 12:44:59 AM UTC 24 |
Sep 05 12:48:44 AM UTC 24 |
3038609598 ps |