| T2268 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/62.xbar_stress_all.254260371 |
|
|
Sep 04 06:48:24 PM UTC 24 |
Sep 04 06:51:54 PM UTC 24 |
2412002963 ps |
| T2269 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/63.xbar_stress_all_with_reset_error.2201507761 |
|
|
Sep 04 06:49:57 PM UTC 24 |
Sep 04 06:51:56 PM UTC 24 |
506906812 ps |
| T2270 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/64.xbar_unmapped_addr.2695651323 |
|
|
Sep 04 06:50:49 PM UTC 24 |
Sep 04 06:51:56 PM UTC 24 |
1272952064 ps |
| T2271 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/63.xbar_stress_all.43863117 |
|
|
Sep 04 06:49:53 PM UTC 24 |
Sep 04 06:52:11 PM UTC 24 |
4363585998 ps |
| T2272 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/65.xbar_error_random.1722336296 |
|
|
Sep 04 06:51:54 PM UTC 24 |
Sep 04 06:52:16 PM UTC 24 |
164966293 ps |
| T2273 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/65.xbar_error_and_unmapped_addr.820137957 |
|
|
Sep 04 06:51:49 PM UTC 24 |
Sep 04 06:52:22 PM UTC 24 |
636968568 ps |
| T2274 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/19.chip_same_csr_outstanding.796083582 |
|
|
Sep 04 05:44:30 PM UTC 24 |
Sep 04 06:52:22 PM UTC 24 |
32294678270 ps |
| T2275 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/65.xbar_random_zero_delays.994837606 |
|
|
Sep 04 06:51:40 PM UTC 24 |
Sep 04 06:52:28 PM UTC 24 |
345171236 ps |
| T2276 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/66.xbar_smoke.1390490614 |
|
|
Sep 04 06:52:23 PM UTC 24 |
Sep 04 06:52:31 PM UTC 24 |
47286100 ps |
| T2277 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/66.xbar_smoke_zero_delays.3972397117 |
|
|
Sep 04 06:52:24 PM UTC 24 |
Sep 04 06:52:33 PM UTC 24 |
41456476 ps |
| T2278 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/60.xbar_random_large_delays.439990059 |
|
|
Sep 04 06:45:02 PM UTC 24 |
Sep 04 06:52:37 PM UTC 24 |
44121265190 ps |
| T2279 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/65.xbar_unmapped_addr.2937876089 |
|
|
Sep 04 06:51:55 PM UTC 24 |
Sep 04 06:52:38 PM UTC 24 |
334125734 ps |
| T2280 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/66.xbar_random.3031959432 |
|
|
Sep 04 06:52:22 PM UTC 24 |
Sep 04 06:52:40 PM UTC 24 |
117292243 ps |
| T2281 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/65.xbar_access_same_device.3801804253 |
|
|
Sep 04 06:51:49 PM UTC 24 |
Sep 04 06:52:46 PM UTC 24 |
1330326645 ps |
| T2282 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/65.xbar_smoke_large_delays.1121105296 |
|
|
Sep 04 06:51:31 PM UTC 24 |
Sep 04 06:52:46 PM UTC 24 |
7970889788 ps |
| T2283 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/65.xbar_same_source.3779201428 |
|
|
Sep 04 06:51:51 PM UTC 24 |
Sep 04 06:52:52 PM UTC 24 |
2044627577 ps |
| T2284 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/41.xbar_access_same_device_slow_rsp.356921763 |
|
|
Sep 04 06:20:35 PM UTC 24 |
Sep 04 06:52:55 PM UTC 24 |
121664965596 ps |
| T2285 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/64.xbar_stress_all.386494238 |
|
|
Sep 04 06:50:56 PM UTC 24 |
Sep 04 06:52:58 PM UTC 24 |
1409652407 ps |
| T2286 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/63.xbar_access_same_device_slow_rsp.2764969995 |
|
|
Sep 04 06:49:31 PM UTC 24 |
Sep 04 06:53:00 PM UTC 24 |
11600239430 ps |
| T2287 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/66.xbar_random_zero_delays.2958023885 |
|
|
Sep 04 06:52:40 PM UTC 24 |
Sep 04 06:53:04 PM UTC 24 |
211379249 ps |
| T2288 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/63.xbar_random_slow_rsp.1491672652 |
|
|
Sep 04 06:49:19 PM UTC 24 |
Sep 04 06:53:04 PM UTC 24 |
15947537896 ps |
| T2289 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/64.xbar_stress_all_with_error.1622417103 |
|
|
Sep 04 06:51:05 PM UTC 24 |
Sep 04 06:53:05 PM UTC 24 |
4131237550 ps |
| T487 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/67.xbar_stress_all.808971065 |
|
|
Sep 04 06:54:08 PM UTC 24 |
Sep 04 07:02:34 PM UTC 24 |
13469851264 ps |
| T2290 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/57.xbar_stress_all_with_rand_reset.1997319564 |
|
|
Sep 04 06:42:11 PM UTC 24 |
Sep 04 06:53:06 PM UTC 24 |
6233366361 ps |
| T2291 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/65.xbar_smoke_slow_rsp.885161510 |
|
|
Sep 04 06:51:38 PM UTC 24 |
Sep 04 06:53:09 PM UTC 24 |
3954226670 ps |
| T2292 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/59.xbar_random_large_delays.670665888 |
|
|
Sep 04 06:43:56 PM UTC 24 |
Sep 04 06:53:12 PM UTC 24 |
56553838024 ps |
| T2293 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/61.xbar_stress_all.1950098998 |
|
|
Sep 04 06:47:02 PM UTC 24 |
Sep 04 06:53:20 PM UTC 24 |
10106001467 ps |
| T2294 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/66.xbar_error_and_unmapped_addr.2077102032 |
|
|
Sep 04 06:53:10 PM UTC 24 |
Sep 04 06:53:20 PM UTC 24 |
74314063 ps |
| T2295 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/66.xbar_access_same_device.133761048 |
|
|
Sep 04 06:52:54 PM UTC 24 |
Sep 04 06:53:24 PM UTC 24 |
253645887 ps |
| T510 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/52.xbar_access_same_device_slow_rsp.3656424412 |
|
|
Sep 04 06:35:02 PM UTC 24 |
Sep 04 06:53:27 PM UTC 24 |
75172829556 ps |
| T2296 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/67.xbar_smoke_zero_delays.3436833499 |
|
|
Sep 04 06:53:23 PM UTC 24 |
Sep 04 06:53:33 PM UTC 24 |
41152943 ps |
| T2297 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/67.xbar_smoke.2139227323 |
|
|
Sep 04 06:53:24 PM UTC 24 |
Sep 04 06:53:38 PM UTC 24 |
234342510 ps |
| T2298 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/66.xbar_unmapped_addr.1473274267 |
|
|
Sep 04 06:53:07 PM UTC 24 |
Sep 04 06:53:39 PM UTC 24 |
437427967 ps |
| T2299 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/66.xbar_smoke_slow_rsp.1907753824 |
|
|
Sep 04 06:52:28 PM UTC 24 |
Sep 04 06:53:45 PM UTC 24 |
4396317849 ps |
| T2300 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/57.xbar_random_slow_rsp.4261201377 |
|
|
Sep 04 06:41:41 PM UTC 24 |
Sep 04 06:53:49 PM UTC 24 |
52121156813 ps |
| T2301 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/59.xbar_stress_all_with_rand_reset.2683842267 |
|
|
Sep 04 06:44:43 PM UTC 24 |
Sep 04 06:53:53 PM UTC 24 |
5072640802 ps |
| T2302 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/67.xbar_random_zero_delays.610544280 |
|
|
Sep 04 06:53:32 PM UTC 24 |
Sep 04 06:53:55 PM UTC 24 |
164892331 ps |
| T2303 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/65.xbar_stress_all_with_error.1806130639 |
|
|
Sep 04 06:52:06 PM UTC 24 |
Sep 04 06:53:59 PM UTC 24 |
3563769493 ps |
| T2304 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/64.xbar_random_large_delays.64236101 |
|
|
Sep 04 06:50:31 PM UTC 24 |
Sep 04 06:54:01 PM UTC 24 |
21280191685 ps |
| T2305 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/67.xbar_same_source.417960467 |
|
|
Sep 04 06:53:45 PM UTC 24 |
Sep 04 06:54:02 PM UTC 24 |
245606026 ps |
| T2306 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/59.xbar_random_slow_rsp.380422251 |
|
|
Sep 04 06:44:00 PM UTC 24 |
Sep 04 06:54:03 PM UTC 24 |
40790352030 ps |
| T2307 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/66.xbar_error_random.4129480685 |
|
|
Sep 04 06:53:06 PM UTC 24 |
Sep 04 06:54:06 PM UTC 24 |
566499011 ps |
| T2308 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/67.xbar_error_random.2930725649 |
|
|
Sep 04 06:53:54 PM UTC 24 |
Sep 04 06:54:06 PM UTC 24 |
251918915 ps |
| T2309 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/65.xbar_random_slow_rsp.2773636052 |
|
|
Sep 04 06:51:43 PM UTC 24 |
Sep 04 06:54:19 PM UTC 24 |
11117506083 ps |
| T2310 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/67.xbar_random.1150658274 |
|
|
Sep 04 06:53:34 PM UTC 24 |
Sep 04 06:54:20 PM UTC 24 |
1506423343 ps |
| T2311 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/42.xbar_access_same_device_slow_rsp.2735950847 |
|
|
Sep 04 06:21:33 PM UTC 24 |
Sep 04 06:54:21 PM UTC 24 |
132440862275 ps |
| T2312 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/67.xbar_unmapped_addr.3530335245 |
|
|
Sep 04 06:53:58 PM UTC 24 |
Sep 04 06:54:23 PM UTC 24 |
189705063 ps |
| T2313 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/66.xbar_smoke_large_delays.360083409 |
|
|
Sep 04 06:52:25 PM UTC 24 |
Sep 04 06:54:25 PM UTC 24 |
8754746927 ps |
| T2314 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/66.xbar_same_source.3446155057 |
|
|
Sep 04 06:52:59 PM UTC 24 |
Sep 04 06:54:26 PM UTC 24 |
2505599211 ps |
| T2315 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/67.xbar_smoke_slow_rsp.664794323 |
|
|
Sep 04 06:53:33 PM UTC 24 |
Sep 04 06:54:28 PM UTC 24 |
3470622675 ps |
| T2316 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/67.xbar_error_and_unmapped_addr.3491955145 |
|
|
Sep 04 06:54:03 PM UTC 24 |
Sep 04 06:54:30 PM UTC 24 |
534460720 ps |
| T2317 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/59.xbar_stress_all_with_reset_error.2930668373 |
|
|
Sep 04 06:44:49 PM UTC 24 |
Sep 04 06:54:32 PM UTC 24 |
13409968689 ps |
| T2318 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/68.xbar_smoke_zero_delays.710780698 |
|
|
Sep 04 06:54:26 PM UTC 24 |
Sep 04 06:54:34 PM UTC 24 |
46236963 ps |
| T2319 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/68.xbar_smoke.993961464 |
|
|
Sep 04 06:54:24 PM UTC 24 |
Sep 04 06:54:36 PM UTC 24 |
182465891 ps |
| T2320 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/68.xbar_random.2455993110 |
|
|
Sep 04 06:54:34 PM UTC 24 |
Sep 04 06:54:42 PM UTC 24 |
94536004 ps |
| T2321 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/68.xbar_random_zero_delays.3491909297 |
|
|
Sep 04 06:54:32 PM UTC 24 |
Sep 04 06:54:44 PM UTC 24 |
80855008 ps |
| T2322 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/67.xbar_smoke_large_delays.3452259621 |
|
|
Sep 04 06:53:27 PM UTC 24 |
Sep 04 06:54:55 PM UTC 24 |
7142275007 ps |
| T2323 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/66.xbar_stress_all_with_rand_reset.380335163 |
|
|
Sep 04 06:53:18 PM UTC 24 |
Sep 04 06:55:11 PM UTC 24 |
251017194 ps |
| T2324 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/69.xbar_smoke.3254069096 |
|
|
Sep 04 06:55:04 PM UTC 24 |
Sep 04 06:55:11 PM UTC 24 |
48290048 ps |
| T2325 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/68.xbar_unmapped_addr.532914070 |
|
|
Sep 04 06:54:51 PM UTC 24 |
Sep 04 06:55:12 PM UTC 24 |
155949081 ps |
| T2326 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/69.xbar_smoke_zero_delays.1980626849 |
|
|
Sep 04 06:55:06 PM UTC 24 |
Sep 04 06:55:16 PM UTC 24 |
44957794 ps |
| T2327 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/50.xbar_access_same_device_slow_rsp.2463831113 |
|
|
Sep 04 06:31:59 PM UTC 24 |
Sep 04 06:55:21 PM UTC 24 |
86858971049 ps |
| T2328 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/67.xbar_access_same_device.1929014569 |
|
|
Sep 04 06:53:40 PM UTC 24 |
Sep 04 06:55:24 PM UTC 24 |
2645682194 ps |
| T2329 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/68.xbar_stress_all_with_rand_reset.1048028175 |
|
|
Sep 04 06:55:00 PM UTC 24 |
Sep 04 06:55:34 PM UTC 24 |
49634192 ps |
| T2330 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/68.xbar_error_and_unmapped_addr.567161658 |
|
|
Sep 04 06:54:54 PM UTC 24 |
Sep 04 06:55:34 PM UTC 24 |
1119808807 ps |
| T2331 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/67.xbar_stress_all_with_reset_error.2482650521 |
|
|
Sep 04 06:54:20 PM UTC 24 |
Sep 04 06:55:37 PM UTC 24 |
415449660 ps |
| T2332 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/45.xbar_access_same_device_slow_rsp.440967089 |
|
|
Sep 04 06:24:46 PM UTC 24 |
Sep 04 06:55:43 PM UTC 24 |
114234699720 ps |
| T2333 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/68.xbar_access_same_device.57255955 |
|
|
Sep 04 06:54:48 PM UTC 24 |
Sep 04 06:55:45 PM UTC 24 |
998302781 ps |
| T2334 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/69.xbar_random_zero_delays.2088159019 |
|
|
Sep 04 06:55:40 PM UTC 24 |
Sep 04 06:55:48 PM UTC 24 |
40733458 ps |
| T2335 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/68.xbar_stress_all.4145384076 |
|
|
Sep 04 06:54:54 PM UTC 24 |
Sep 04 06:55:51 PM UTC 24 |
584456920 ps |
| T2336 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/68.xbar_error_random.3931833177 |
|
|
Sep 04 06:54:49 PM UTC 24 |
Sep 04 06:55:56 PM UTC 24 |
1604863339 ps |
| T2337 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/68.xbar_same_source.2147820461 |
|
|
Sep 04 06:54:49 PM UTC 24 |
Sep 04 06:56:05 PM UTC 24 |
2647219853 ps |
| T2338 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/58.xbar_stress_all_with_reset_error.2766317371 |
|
|
Sep 04 06:43:14 PM UTC 24 |
Sep 04 06:56:08 PM UTC 24 |
7561453188 ps |
| T2339 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/68.xbar_smoke_slow_rsp.4061015687 |
|
|
Sep 04 06:54:24 PM UTC 24 |
Sep 04 06:56:11 PM UTC 24 |
4154323479 ps |
| T884 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/65.xbar_stress_all_with_rand_reset.1771393483 |
|
|
Sep 04 06:52:00 PM UTC 24 |
Sep 04 06:56:15 PM UTC 24 |
433800945 ps |
| T2340 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/68.xbar_smoke_large_delays.1764532534 |
|
|
Sep 04 06:54:29 PM UTC 24 |
Sep 04 06:56:20 PM UTC 24 |
7067945465 ps |
| T2341 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/69.xbar_same_source.2045232385 |
|
|
Sep 04 06:56:02 PM UTC 24 |
Sep 04 06:56:28 PM UTC 24 |
254504094 ps |
| T2342 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/65.xbar_stress_all.871376866 |
|
|
Sep 04 06:51:54 PM UTC 24 |
Sep 04 06:56:28 PM UTC 24 |
7479534864 ps |
| T2343 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/66.xbar_random_large_delays.3224048137 |
|
|
Sep 04 06:52:46 PM UTC 24 |
Sep 04 06:56:29 PM UTC 24 |
19372217539 ps |
| T2344 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/69.xbar_error_and_unmapped_addr.2892164379 |
|
|
Sep 04 06:56:14 PM UTC 24 |
Sep 04 06:56:32 PM UTC 24 |
141745612 ps |
| T2345 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/66.xbar_stress_all.3291517226 |
|
|
Sep 04 06:53:12 PM UTC 24 |
Sep 04 06:56:40 PM UTC 24 |
2338060023 ps |
| T2346 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/69.xbar_unmapped_addr.2615922516 |
|
|
Sep 04 06:56:07 PM UTC 24 |
Sep 04 06:56:41 PM UTC 24 |
235874420 ps |
| T2347 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/70.xbar_smoke_zero_delays.133716720 |
|
|
Sep 04 06:56:36 PM UTC 24 |
Sep 04 06:56:43 PM UTC 24 |
47953323 ps |
| T2348 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/68.xbar_stress_all_with_error.822421587 |
|
|
Sep 04 06:55:00 PM UTC 24 |
Sep 04 06:56:45 PM UTC 24 |
1296593521 ps |
| T2349 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/69.xbar_random.3177781745 |
|
|
Sep 04 06:55:40 PM UTC 24 |
Sep 04 06:56:51 PM UTC 24 |
1531992273 ps |
| T2350 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/70.xbar_smoke.367068569 |
|
|
Sep 04 06:56:37 PM UTC 24 |
Sep 04 06:56:52 PM UTC 24 |
254122013 ps |
| T2351 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/69.xbar_smoke_large_delays.2173750735 |
|
|
Sep 04 06:55:12 PM UTC 24 |
Sep 04 06:56:58 PM UTC 24 |
7899313011 ps |
| T2352 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/67.xbar_stress_all_with_error.2078655540 |
|
|
Sep 04 06:54:16 PM UTC 24 |
Sep 04 06:57:09 PM UTC 24 |
6578787560 ps |
| T2353 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/69.xbar_smoke_slow_rsp.2506427568 |
|
|
Sep 04 06:55:22 PM UTC 24 |
Sep 04 06:57:10 PM UTC 24 |
6046959211 ps |
| T2354 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/68.xbar_stress_all_with_reset_error.846242464 |
|
|
Sep 04 06:55:01 PM UTC 24 |
Sep 04 06:57:14 PM UTC 24 |
420238669 ps |
| T2355 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/70.xbar_random.1933590019 |
|
|
Sep 04 06:56:49 PM UTC 24 |
Sep 04 06:57:15 PM UTC 24 |
192731697 ps |
| T2356 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/69.xbar_error_random.4232902835 |
|
|
Sep 04 06:56:03 PM UTC 24 |
Sep 04 06:57:22 PM UTC 24 |
2173325291 ps |
| T2357 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/66.xbar_stress_all_with_error.193025256 |
|
|
Sep 04 06:53:17 PM UTC 24 |
Sep 04 06:57:25 PM UTC 24 |
6788944476 ps |
| T2358 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/70.xbar_unmapped_addr.2697389755 |
|
|
Sep 04 06:57:12 PM UTC 24 |
Sep 04 06:57:26 PM UTC 24 |
145211307 ps |
| T2359 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/63.xbar_stress_all_with_error.376866655 |
|
|
Sep 04 06:49:58 PM UTC 24 |
Sep 04 06:57:28 PM UTC 24 |
12356329269 ps |
| T2360 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/69.xbar_stress_all_with_rand_reset.3630201919 |
|
|
Sep 04 06:56:16 PM UTC 24 |
Sep 04 06:57:32 PM UTC 24 |
210122382 ps |
| T2361 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/70.xbar_same_source.1432188504 |
|
|
Sep 04 06:57:09 PM UTC 24 |
Sep 04 06:57:34 PM UTC 24 |
267967173 ps |
| T2362 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/70.xbar_error_and_unmapped_addr.1708115829 |
|
|
Sep 04 06:57:20 PM UTC 24 |
Sep 04 06:57:40 PM UTC 24 |
366210925 ps |
| T2363 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/70.xbar_access_same_device.1261585122 |
|
|
Sep 04 06:57:01 PM UTC 24 |
Sep 04 06:57:41 PM UTC 24 |
767465530 ps |
| T2364 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/67.xbar_access_same_device_slow_rsp.2883568336 |
|
|
Sep 04 06:53:45 PM UTC 24 |
Sep 04 06:57:42 PM UTC 24 |
15403557967 ps |
| T2365 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/70.xbar_random_zero_delays.1864583073 |
|
|
Sep 04 06:56:58 PM UTC 24 |
Sep 04 06:57:45 PM UTC 24 |
413864364 ps |
| T2366 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/71.xbar_smoke_zero_delays.395898149 |
|
|
Sep 04 06:57:44 PM UTC 24 |
Sep 04 06:57:55 PM UTC 24 |
55168048 ps |
| T2367 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/69.xbar_stress_all_with_reset_error.3857777305 |
|
|
Sep 04 06:56:24 PM UTC 24 |
Sep 04 06:57:55 PM UTC 24 |
221345715 ps |
| T2368 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/71.xbar_smoke.1308920120 |
|
|
Sep 04 06:57:42 PM UTC 24 |
Sep 04 06:57:56 PM UTC 24 |
226041726 ps |
| T2369 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/56.xbar_access_same_device_slow_rsp.151424620 |
|
|
Sep 04 06:40:35 PM UTC 24 |
Sep 04 06:58:00 PM UTC 24 |
74423587255 ps |
| T2370 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/69.xbar_access_same_device.2905404052 |
|
|
Sep 04 06:55:51 PM UTC 24 |
Sep 04 06:58:03 PM UTC 24 |
3457567844 ps |
| T2371 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/67.xbar_stress_all_with_rand_reset.1156152720 |
|
|
Sep 04 06:54:06 PM UTC 24 |
Sep 04 06:58:06 PM UTC 24 |
4246913682 ps |
| T2372 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/70.xbar_smoke_large_delays.3732497411 |
|
|
Sep 04 06:56:38 PM UTC 24 |
Sep 04 06:58:07 PM UTC 24 |
5795683737 ps |
| T2373 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/65.xbar_stress_all_with_reset_error.3250291406 |
|
|
Sep 04 06:52:14 PM UTC 24 |
Sep 04 06:58:10 PM UTC 24 |
2702852137 ps |
| T2374 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/47.xbar_access_same_device_slow_rsp.2599730898 |
|
|
Sep 04 06:27:15 PM UTC 24 |
Sep 04 06:58:13 PM UTC 24 |
145028851523 ps |
| T2375 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/69.xbar_stress_all.2433377814 |
|
|
Sep 04 06:56:13 PM UTC 24 |
Sep 04 06:58:14 PM UTC 24 |
1377040283 ps |
| T2376 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/71.xbar_random_zero_delays.1559141977 |
|
|
Sep 04 06:58:00 PM UTC 24 |
Sep 04 06:58:19 PM UTC 24 |
164903990 ps |
| T2377 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/70.xbar_smoke_slow_rsp.1406394809 |
|
|
Sep 04 06:56:47 PM UTC 24 |
Sep 04 06:58:19 PM UTC 24 |
6609545094 ps |
| T2378 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/64.xbar_stress_all_with_rand_reset.1902817389 |
|
|
Sep 04 06:51:01 PM UTC 24 |
Sep 04 06:58:20 PM UTC 24 |
6705002367 ps |
| T2379 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/71.xbar_random.3836564617 |
|
|
Sep 04 06:57:54 PM UTC 24 |
Sep 04 06:58:31 PM UTC 24 |
280873361 ps |
| T2380 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/71.xbar_same_source.2525727939 |
|
|
Sep 04 06:58:11 PM UTC 24 |
Sep 04 06:58:36 PM UTC 24 |
872071902 ps |
| T2381 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/71.xbar_access_same_device.2915021312 |
|
|
Sep 04 06:58:08 PM UTC 24 |
Sep 04 06:58:40 PM UTC 24 |
503404907 ps |
| T2382 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/71.xbar_error_and_unmapped_addr.2421108511 |
|
|
Sep 04 06:58:25 PM UTC 24 |
Sep 04 06:58:41 PM UTC 24 |
173283255 ps |
| T2383 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/71.xbar_unmapped_addr.1060210375 |
|
|
Sep 04 06:58:12 PM UTC 24 |
Sep 04 06:58:44 PM UTC 24 |
552406253 ps |
| T2384 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/66.xbar_stress_all_with_reset_error.1442876442 |
|
|
Sep 04 06:53:20 PM UTC 24 |
Sep 04 06:58:45 PM UTC 24 |
2456314839 ps |
| T2385 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/72.xbar_smoke.2942378687 |
|
|
Sep 04 06:58:37 PM UTC 24 |
Sep 04 06:58:46 PM UTC 24 |
237628769 ps |
| T2386 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/72.xbar_smoke_zero_delays.1947921778 |
|
|
Sep 04 06:58:37 PM UTC 24 |
Sep 04 06:58:47 PM UTC 24 |
40361721 ps |
| T2387 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/61.xbar_random_slow_rsp.3832061962 |
|
|
Sep 04 06:46:24 PM UTC 24 |
Sep 04 06:58:49 PM UTC 24 |
50613194829 ps |
| T2388 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/72.xbar_random_zero_delays.365272755 |
|
|
Sep 04 06:58:43 PM UTC 24 |
Sep 04 06:58:55 PM UTC 24 |
100665812 ps |
| T2389 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/71.xbar_error_random.2378054447 |
|
|
Sep 04 06:58:12 PM UTC 24 |
Sep 04 06:59:01 PM UTC 24 |
499661711 ps |
| T2390 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/71.xbar_stress_all.2319642167 |
|
|
Sep 04 06:58:23 PM UTC 24 |
Sep 04 06:59:03 PM UTC 24 |
725149800 ps |
| T2391 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/62.xbar_random_slow_rsp.4272001404 |
|
|
Sep 04 06:48:02 PM UTC 24 |
Sep 04 06:59:06 PM UTC 24 |
44673289565 ps |
| T2392 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/71.xbar_smoke_slow_rsp.2674756081 |
|
|
Sep 04 06:57:57 PM UTC 24 |
Sep 04 06:59:11 PM UTC 24 |
4968148843 ps |
| T2393 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/72.xbar_random.4062112329 |
|
|
Sep 04 06:58:40 PM UTC 24 |
Sep 04 06:59:17 PM UTC 24 |
1017351955 ps |
| T2394 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/72.xbar_same_source.554883962 |
|
|
Sep 04 06:59:10 PM UTC 24 |
Sep 04 06:59:35 PM UTC 24 |
196318594 ps |
| T2395 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/73.xbar_smoke.2750152643 |
|
|
Sep 04 06:59:29 PM UTC 24 |
Sep 04 06:59:42 PM UTC 24 |
201428680 ps |
| T2396 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/73.xbar_smoke_zero_delays.1849705152 |
|
|
Sep 04 06:59:32 PM UTC 24 |
Sep 04 06:59:43 PM UTC 24 |
49407768 ps |
| T2397 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/72.xbar_stress_all_with_rand_reset.454243867 |
|
|
Sep 04 06:59:14 PM UTC 24 |
Sep 04 06:59:43 PM UTC 24 |
82123624 ps |
| T2398 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/65.xbar_random_large_delays.1690782765 |
|
|
Sep 04 06:51:40 PM UTC 24 |
Sep 04 06:59:44 PM UTC 24 |
44419653413 ps |
| T2399 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/72.xbar_error_and_unmapped_addr.3342189994 |
|
|
Sep 04 06:59:15 PM UTC 24 |
Sep 04 06:59:47 PM UTC 24 |
738327039 ps |
| T2400 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/72.xbar_access_same_device.638218263 |
|
|
Sep 04 06:59:03 PM UTC 24 |
Sep 04 06:59:48 PM UTC 24 |
756267569 ps |
| T2401 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/72.xbar_smoke_slow_rsp.1328528028 |
|
|
Sep 04 06:58:44 PM UTC 24 |
Sep 04 06:59:48 PM UTC 24 |
4471593051 ps |
| T2402 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/3.chip_csr_aliasing.3101185366 |
|
|
Sep 04 05:05:51 PM UTC 24 |
Sep 04 06:59:54 PM UTC 24 |
41022747760 ps |
| T2403 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/58.xbar_random_large_delays.519143431 |
|
|
Sep 04 06:42:36 PM UTC 24 |
Sep 04 06:59:55 PM UTC 24 |
92130062388 ps |
| T2404 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/71.xbar_smoke_large_delays.2423698807 |
|
|
Sep 04 06:57:51 PM UTC 24 |
Sep 04 06:59:57 PM UTC 24 |
7888801907 ps |
| T2405 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/72.xbar_stress_all.2302031649 |
|
|
Sep 04 06:59:16 PM UTC 24 |
Sep 04 07:00:01 PM UTC 24 |
450280679 ps |
| T2406 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/72.xbar_error_random.1672997590 |
|
|
Sep 04 06:59:10 PM UTC 24 |
Sep 04 07:00:02 PM UTC 24 |
1142118959 ps |
| T2407 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/72.xbar_stress_all_with_error.401450179 |
|
|
Sep 04 06:59:17 PM UTC 24 |
Sep 04 07:00:02 PM UTC 24 |
1027312003 ps |
| T2408 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/51.xbar_access_same_device_slow_rsp.871093102 |
|
|
Sep 04 06:33:20 PM UTC 24 |
Sep 04 07:00:09 PM UTC 24 |
103242369485 ps |
| T2409 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/70.xbar_stress_all.2976296686 |
|
|
Sep 04 06:57:19 PM UTC 24 |
Sep 04 07:00:09 PM UTC 24 |
1720912535 ps |
| T2410 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/72.xbar_smoke_large_delays.1420163344 |
|
|
Sep 04 06:58:34 PM UTC 24 |
Sep 04 07:00:11 PM UTC 24 |
9936313551 ps |
| T2411 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/55.xbar_access_same_device_slow_rsp.3622841499 |
|
|
Sep 04 06:39:23 PM UTC 24 |
Sep 04 07:00:11 PM UTC 24 |
75454527439 ps |
| T2412 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/72.xbar_unmapped_addr.1189077112 |
|
|
Sep 04 06:59:12 PM UTC 24 |
Sep 04 07:00:13 PM UTC 24 |
1392131739 ps |
| T2413 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/73.xbar_same_source.2067358782 |
|
|
Sep 04 07:00:14 PM UTC 24 |
Sep 04 07:00:24 PM UTC 24 |
172449375 ps |
| T2414 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/61.xbar_stress_all_with_rand_reset.2288120796 |
|
|
Sep 04 06:47:06 PM UTC 24 |
Sep 04 07:00:26 PM UTC 24 |
17933708675 ps |
| T2415 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/73.xbar_random_zero_delays.2712799939 |
|
|
Sep 04 07:00:01 PM UTC 24 |
Sep 04 07:00:33 PM UTC 24 |
309682658 ps |
| T2416 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/73.xbar_stress_all_with_rand_reset.2164817188 |
|
|
Sep 04 07:00:25 PM UTC 24 |
Sep 04 07:00:43 PM UTC 24 |
43456100 ps |
| T2417 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/73.xbar_random.312241239 |
|
|
Sep 04 06:59:39 PM UTC 24 |
Sep 04 07:00:43 PM UTC 24 |
1522618333 ps |
| T2418 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/74.xbar_smoke_zero_delays.2303245045 |
|
|
Sep 04 07:00:35 PM UTC 24 |
Sep 04 07:00:44 PM UTC 24 |
44055222 ps |
| T2419 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/69.xbar_stress_all_with_error.2910246526 |
|
|
Sep 04 06:56:17 PM UTC 24 |
Sep 04 07:00:44 PM UTC 24 |
8426843063 ps |
| T2420 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/74.xbar_smoke.2628439059 |
|
|
Sep 04 07:00:35 PM UTC 24 |
Sep 04 07:00:45 PM UTC 24 |
40266239 ps |
| T2421 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/74.xbar_random.2001101170 |
|
|
Sep 04 07:00:33 PM UTC 24 |
Sep 04 07:00:54 PM UTC 24 |
609815767 ps |
| T2422 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/73.xbar_unmapped_addr.4281907218 |
|
|
Sep 04 07:00:19 PM UTC 24 |
Sep 04 07:01:00 PM UTC 24 |
1094303432 ps |
| T2423 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/73.xbar_error_random.2762627746 |
|
|
Sep 04 07:00:20 PM UTC 24 |
Sep 04 07:01:00 PM UTC 24 |
452945592 ps |
| T2424 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/60.xbar_random_slow_rsp.1013244963 |
|
|
Sep 04 06:45:08 PM UTC 24 |
Sep 04 07:01:08 PM UTC 24 |
60569436235 ps |
| T2425 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/73.xbar_error_and_unmapped_addr.1051053882 |
|
|
Sep 04 07:00:18 PM UTC 24 |
Sep 04 07:01:14 PM UTC 24 |
986435774 ps |
| T2426 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/73.xbar_smoke_slow_rsp.1581176128 |
|
|
Sep 04 06:59:43 PM UTC 24 |
Sep 04 07:01:19 PM UTC 24 |
5726980123 ps |
| T2427 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/71.xbar_stress_all_with_rand_reset.3882697908 |
|
|
Sep 04 06:58:25 PM UTC 24 |
Sep 04 07:01:26 PM UTC 24 |
1279962321 ps |
| T2428 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/73.xbar_access_same_device.4138170284 |
|
|
Sep 04 07:00:10 PM UTC 24 |
Sep 04 07:01:28 PM UTC 24 |
1554797946 ps |
| T2429 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/74.xbar_random_zero_delays.933309590 |
|
|
Sep 04 07:00:42 PM UTC 24 |
Sep 04 07:01:30 PM UTC 24 |
602642990 ps |
| T2430 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/73.xbar_smoke_large_delays.2358571242 |
|
|
Sep 04 06:59:37 PM UTC 24 |
Sep 04 07:01:44 PM UTC 24 |
9253075795 ps |
| T2431 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/74.xbar_same_source.1909403278 |
|
|
Sep 04 07:01:10 PM UTC 24 |
Sep 04 07:01:48 PM UTC 24 |
921945882 ps |
| T2432 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/75.xbar_smoke_zero_delays.1819878024 |
|
|
Sep 04 07:01:42 PM UTC 24 |
Sep 04 07:01:49 PM UTC 24 |
40700606 ps |
| T2433 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/63.xbar_random_large_delays.3576061759 |
|
|
Sep 04 06:49:18 PM UTC 24 |
Sep 04 07:01:52 PM UTC 24 |
79223381661 ps |
| T2434 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/75.xbar_smoke.3216775492 |
|
|
Sep 04 07:01:45 PM UTC 24 |
Sep 04 07:01:54 PM UTC 24 |
42721563 ps |
| T2435 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/74.xbar_unmapped_addr.1921316670 |
|
|
Sep 04 07:01:16 PM UTC 24 |
Sep 04 07:02:00 PM UTC 24 |
1045613406 ps |
| T2436 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/74.xbar_error_random.2154851601 |
|
|
Sep 04 07:01:08 PM UTC 24 |
Sep 04 07:02:05 PM UTC 24 |
2176748345 ps |
| T2437 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/74.xbar_error_and_unmapped_addr.747585778 |
|
|
Sep 04 07:01:18 PM UTC 24 |
Sep 04 07:02:06 PM UTC 24 |
1332195486 ps |
| T2438 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/75.xbar_random.14031032 |
|
|
Sep 04 07:01:56 PM UTC 24 |
Sep 04 07:02:11 PM UTC 24 |
407352376 ps |
| T2439 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/74.xbar_smoke_slow_rsp.1038932695 |
|
|
Sep 04 07:00:39 PM UTC 24 |
Sep 04 07:02:12 PM UTC 24 |
5762352492 ps |
| T2440 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/74.xbar_stress_all_with_error.481900324 |
|
|
Sep 04 07:01:23 PM UTC 24 |
Sep 04 07:02:14 PM UTC 24 |
497542594 ps |
| T2441 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/74.xbar_access_same_device.512713404 |
|
|
Sep 04 07:01:04 PM UTC 24 |
Sep 04 07:02:16 PM UTC 24 |
610116933 ps |
| T2442 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/71.xbar_stress_all_with_error.3168521755 |
|
|
Sep 04 06:58:28 PM UTC 24 |
Sep 04 07:02:29 PM UTC 24 |
7453823697 ps |
| T2443 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/58.xbar_access_same_device_slow_rsp.3520025186 |
|
|
Sep 04 06:42:50 PM UTC 24 |
Sep 04 07:02:48 PM UTC 24 |
82099651597 ps |
| T2444 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/75.xbar_random_zero_delays.3300274306 |
|
|
Sep 04 07:02:14 PM UTC 24 |
Sep 04 07:02:49 PM UTC 24 |
406583904 ps |
| T862 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/71.xbar_stress_all_with_reset_error.1367180109 |
|
|
Sep 04 06:58:31 PM UTC 24 |
Sep 04 07:02:49 PM UTC 24 |
5454669214 ps |
| T2445 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/54.xbar_access_same_device_slow_rsp.431054816 |
|
|
Sep 04 06:37:43 PM UTC 24 |
Sep 04 07:02:51 PM UTC 24 |
103980747088 ps |
| T2446 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/75.xbar_error_random.3640771354 |
|
|
Sep 04 07:02:31 PM UTC 24 |
Sep 04 07:03:00 PM UTC 24 |
736030755 ps |
| T2447 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/74.xbar_smoke_large_delays.3580363865 |
|
|
Sep 04 07:00:38 PM UTC 24 |
Sep 04 07:03:00 PM UTC 24 |
10463839655 ps |
| T2448 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/75.xbar_error_and_unmapped_addr.3224736643 |
|
|
Sep 04 07:02:38 PM UTC 24 |
Sep 04 07:03:00 PM UTC 24 |
576419838 ps |
| T2449 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/66.xbar_random_slow_rsp.3895655579 |
|
|
Sep 04 06:52:53 PM UTC 24 |
Sep 04 07:03:01 PM UTC 24 |
37849972205 ps |
| T2450 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/65.xbar_access_same_device_slow_rsp.1551536923 |
|
|
Sep 04 06:51:48 PM UTC 24 |
Sep 04 07:03:07 PM UTC 24 |
44988299265 ps |
| T2451 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/75.xbar_smoke_slow_rsp.791429853 |
|
|
Sep 04 07:01:58 PM UTC 24 |
Sep 04 07:03:14 PM UTC 24 |
4667314607 ps |
| T2452 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/75.xbar_smoke_large_delays.3083290035 |
|
|
Sep 04 07:01:53 PM UTC 24 |
Sep 04 07:03:14 PM UTC 24 |
7762582160 ps |
| T2453 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/76.xbar_smoke.2587897 |
|
|
Sep 04 07:03:05 PM UTC 24 |
Sep 04 07:03:15 PM UTC 24 |
48348762 ps |
| T2454 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/73.xbar_stress_all.3660473015 |
|
|
Sep 04 07:00:24 PM UTC 24 |
Sep 04 07:03:19 PM UTC 24 |
3464109705 ps |
| T2455 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/76.xbar_smoke_zero_delays.647770574 |
|
|
Sep 04 07:03:17 PM UTC 24 |
Sep 04 07:03:26 PM UTC 24 |
45325946 ps |
| T2456 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/75.xbar_unmapped_addr.3211726421 |
|
|
Sep 04 07:02:35 PM UTC 24 |
Sep 04 07:03:26 PM UTC 24 |
1187204987 ps |
| T2457 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/74.xbar_random_slow_rsp.2410708373 |
|
|
Sep 04 07:00:56 PM UTC 24 |
Sep 04 07:03:39 PM UTC 24 |
12050631492 ps |
| T2458 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/75.xbar_same_source.4245932499 |
|
|
Sep 04 07:02:28 PM UTC 24 |
Sep 04 07:03:40 PM UTC 24 |
2035540384 ps |
| T2459 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/70.xbar_stress_all_with_reset_error.2445636253 |
|
|
Sep 04 06:57:42 PM UTC 24 |
Sep 04 07:03:47 PM UTC 24 |
8814859793 ps |
| T2460 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/73.xbar_stress_all_with_reset_error.2590657226 |
|
|
Sep 04 07:00:33 PM UTC 24 |
Sep 04 07:03:52 PM UTC 24 |
3506185775 ps |
| T2461 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/68.xbar_access_same_device_slow_rsp.3876865423 |
|
|
Sep 04 06:54:46 PM UTC 24 |
Sep 04 07:03:52 PM UTC 24 |
37681724098 ps |
| T2462 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/66.xbar_access_same_device_slow_rsp.3260269730 |
|
|
Sep 04 06:52:57 PM UTC 24 |
Sep 04 07:03:57 PM UTC 24 |
50897004224 ps |
| T2463 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/76.xbar_error_and_unmapped_addr.3641504273 |
|
|
Sep 04 07:03:45 PM UTC 24 |
Sep 04 07:03:59 PM UTC 24 |
236679018 ps |
| T2464 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/72.xbar_stress_all_with_reset_error.1267723331 |
|
|
Sep 04 06:59:27 PM UTC 24 |
Sep 04 07:04:01 PM UTC 24 |
2407164997 ps |
| T2465 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/76.xbar_random_zero_delays.3800749749 |
|
|
Sep 04 07:03:29 PM UTC 24 |
Sep 04 07:04:04 PM UTC 24 |
267639893 ps |
| T2466 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/76.xbar_random.695238500 |
|
|
Sep 04 07:03:19 PM UTC 24 |
Sep 04 07:04:13 PM UTC 24 |
529065329 ps |
| T2467 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/76.xbar_error_random.2472578896 |
|
|
Sep 04 07:03:43 PM UTC 24 |
Sep 04 07:04:13 PM UTC 24 |
771913629 ps |
| T2468 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/64.xbar_random_slow_rsp.241759607 |
|
|
Sep 04 06:50:36 PM UTC 24 |
Sep 04 07:04:21 PM UTC 24 |
53587986857 ps |
| T2469 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/76.xbar_access_same_device.4095502689 |
|
|
Sep 04 07:03:33 PM UTC 24 |
Sep 04 07:04:21 PM UTC 24 |
927535879 ps |
| T2470 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/72.xbar_random_slow_rsp.1749227163 |
|
|
Sep 04 06:58:50 PM UTC 24 |
Sep 04 07:04:23 PM UTC 24 |
22825887426 ps |
| T2471 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/77.xbar_smoke.2159264776 |
|
|
Sep 04 07:04:17 PM UTC 24 |
Sep 04 07:04:27 PM UTC 24 |
164855884 ps |
| T2472 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/77.xbar_smoke_zero_delays.3038499337 |
|
|
Sep 04 07:04:18 PM UTC 24 |
Sep 04 07:04:29 PM UTC 24 |
43516490 ps |
| T2473 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/71.xbar_random_slow_rsp.4159884671 |
|
|
Sep 04 06:58:01 PM UTC 24 |
Sep 04 07:04:33 PM UTC 24 |
24298768738 ps |
| T2474 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/76.xbar_same_source.4145481540 |
|
|
Sep 04 07:03:45 PM UTC 24 |
Sep 04 07:04:34 PM UTC 24 |
1727319624 ps |
| T2475 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/76.xbar_unmapped_addr.3215157270 |
|
|
Sep 04 07:03:45 PM UTC 24 |
Sep 04 07:04:36 PM UTC 24 |
1266358576 ps |
| T2476 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/62.xbar_stress_all_with_reset_error.161622328 |
|
|
Sep 04 06:48:43 PM UTC 24 |
Sep 04 07:04:41 PM UTC 24 |
24005461159 ps |
| T2477 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/75.xbar_access_same_device.2818839719 |
|
|
Sep 04 07:02:21 PM UTC 24 |
Sep 04 07:04:43 PM UTC 24 |
2691707764 ps |
| T2478 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/70.xbar_random_slow_rsp.4058564404 |
|
|
Sep 04 06:56:59 PM UTC 24 |
Sep 04 07:04:47 PM UTC 24 |
32154476427 ps |
| T2479 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/75.xbar_stress_all_with_error.2823885594 |
|
|
Sep 04 07:02:47 PM UTC 24 |
Sep 04 07:04:52 PM UTC 24 |
1690474724 ps |
| T2480 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/76.xbar_stress_all_with_reset_error.4083196789 |
|
|
Sep 04 07:04:08 PM UTC 24 |
Sep 04 07:04:52 PM UTC 24 |
45672799 ps |
| T2481 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/76.xbar_smoke_slow_rsp.2384469363 |
|
|
Sep 04 07:03:19 PM UTC 24 |
Sep 04 07:04:52 PM UTC 24 |
4787269667 ps |
| T2482 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/77.xbar_error_random.3092016240 |
|
|
Sep 04 07:04:48 PM UTC 24 |
Sep 04 07:04:55 PM UTC 24 |
44365168 ps |
| T2483 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/76.xbar_smoke_large_delays.2046048020 |
|
|
Sep 04 07:03:16 PM UTC 24 |
Sep 04 07:04:57 PM UTC 24 |
8614815137 ps |
| T2484 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/77.xbar_same_source.1709161277 |
|
|
Sep 04 07:04:49 PM UTC 24 |
Sep 04 07:05:16 PM UTC 24 |
591042418 ps |
| T2485 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/77.xbar_random.2117543048 |
|
|
Sep 04 07:04:28 PM UTC 24 |
Sep 04 07:05:16 PM UTC 24 |
1395382565 ps |
| T2486 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/77.xbar_random_zero_delays.2911545513 |
|
|
Sep 04 07:04:30 PM UTC 24 |
Sep 04 07:05:16 PM UTC 24 |
351302289 ps |
| T2487 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/78.xbar_smoke.2410037809 |
|
|
Sep 04 07:05:09 PM UTC 24 |
Sep 04 07:05:21 PM UTC 24 |
213143203 ps |
| T2488 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/78.xbar_smoke_zero_delays.1483750903 |
|
|
Sep 04 07:05:15 PM UTC 24 |
Sep 04 07:05:23 PM UTC 24 |
45619474 ps |
| T2489 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/77.xbar_error_and_unmapped_addr.943458976 |
|
|
Sep 04 07:04:54 PM UTC 24 |
Sep 04 07:05:23 PM UTC 24 |
908128908 ps |
| T2490 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/77.xbar_unmapped_addr.108251935 |
|
|
Sep 04 07:04:52 PM UTC 24 |
Sep 04 07:05:31 PM UTC 24 |
833387097 ps |
| T2491 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/77.xbar_smoke_slow_rsp.1558909213 |
|
|
Sep 04 07:04:25 PM UTC 24 |
Sep 04 07:05:40 PM UTC 24 |
5669962612 ps |
| T2492 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/75.xbar_stress_all.3946925678 |
|
|
Sep 04 07:02:41 PM UTC 24 |
Sep 04 07:05:49 PM UTC 24 |
4339283834 ps |
| T2493 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/67.xbar_random_slow_rsp.3968757426 |
|
|
Sep 04 06:53:36 PM UTC 24 |
Sep 04 07:05:55 PM UTC 24 |
45274193067 ps |
| T2494 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/78.xbar_random_zero_delays.3891740689 |
|
|
Sep 04 07:05:23 PM UTC 24 |
Sep 04 07:05:59 PM UTC 24 |
310668861 ps |
| T2495 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/78.xbar_random.1597071232 |
|
|
Sep 04 07:05:15 PM UTC 24 |
Sep 04 07:06:00 PM UTC 24 |
937409793 ps |
| T2496 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/69.xbar_random_slow_rsp.542554231 |
|
|
Sep 04 06:55:47 PM UTC 24 |
Sep 04 07:06:00 PM UTC 24 |
40096278453 ps |
| T2497 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/77.xbar_smoke_large_delays.474859276 |
|
|
Sep 04 07:04:23 PM UTC 24 |
Sep 04 07:06:02 PM UTC 24 |
8690647894 ps |
| T2498 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/61.xbar_access_same_device_slow_rsp.1256406494 |
|
|
Sep 04 06:46:31 PM UTC 24 |
Sep 04 07:06:10 PM UTC 24 |
76560920751 ps |
| T2499 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/78.xbar_same_source.2577464028 |
|
|
Sep 04 07:05:52 PM UTC 24 |
Sep 04 07:06:13 PM UTC 24 |
320873763 ps |
| T2500 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/78.xbar_random_slow_rsp.4135558411 |
|
|
Sep 04 07:05:47 PM UTC 24 |
Sep 04 07:06:22 PM UTC 24 |
1975046496 ps |
| T2501 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/77.xbar_access_same_device.110374065 |
|
|
Sep 04 07:04:44 PM UTC 24 |
Sep 04 07:06:23 PM UTC 24 |
1278685755 ps |
| T2502 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/73.xbar_stress_all_with_error.3352879510 |
|
|
Sep 04 07:00:33 PM UTC 24 |
Sep 04 07:06:24 PM UTC 24 |
10570333724 ps |
| T2503 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/74.xbar_stress_all.3837509702 |
|
|
Sep 04 07:01:25 PM UTC 24 |
Sep 04 07:06:26 PM UTC 24 |
8894063644 ps |
| T2504 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/78.xbar_error_random.3126444613 |
|
|
Sep 04 07:05:56 PM UTC 24 |
Sep 04 07:06:26 PM UTC 24 |
376263597 ps |
| T2505 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/78.xbar_smoke_slow_rsp.753259466 |
|
|
Sep 04 07:05:16 PM UTC 24 |
Sep 04 07:06:35 PM UTC 24 |
5678641397 ps |
| T2506 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/68.xbar_random_large_delays.2443865316 |
|
|
Sep 04 06:54:33 PM UTC 24 |
Sep 04 07:06:36 PM UTC 24 |
62928706474 ps |
| T2507 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/79.xbar_smoke_zero_delays.3657090591 |
|
|
Sep 04 07:06:32 PM UTC 24 |
Sep 04 07:06:39 PM UTC 24 |
41348891 ps |
| T2508 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/79.xbar_smoke.3970493501 |
|
|
Sep 04 07:06:32 PM UTC 24 |
Sep 04 07:06:40 PM UTC 24 |
44157910 ps |
| T2509 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/78.xbar_unmapped_addr.784069012 |
|
|
Sep 04 07:05:55 PM UTC 24 |
Sep 04 07:06:42 PM UTC 24 |
1252595191 ps |
| T2510 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/78.xbar_error_and_unmapped_addr.824328353 |
|
|
Sep 04 07:06:04 PM UTC 24 |
Sep 04 07:06:42 PM UTC 24 |
326678116 ps |
| T2511 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/78.xbar_access_same_device.2808859094 |
|
|
Sep 04 07:05:48 PM UTC 24 |
Sep 04 07:06:44 PM UTC 24 |
1316302522 ps |
| T2512 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/72.xbar_random_large_delays.2811652369 |
|
|
Sep 04 06:58:46 PM UTC 24 |
Sep 04 07:06:48 PM UTC 24 |
46265112085 ps |
| T2513 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/79.xbar_random_zero_delays.1319001642 |
|
|
Sep 04 07:06:50 PM UTC 24 |
Sep 04 07:06:59 PM UTC 24 |
34657761 ps |