| T2029 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/41.xbar_random_slow_rsp.1475611084 |
|
|
Sep 04 06:20:25 PM UTC 24 |
Sep 04 06:33:58 PM UTC 24 |
56725028745 ps |
| T2030 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/51.xbar_unmapped_addr.687506772 |
|
|
Sep 04 06:33:31 PM UTC 24 |
Sep 04 06:34:12 PM UTC 24 |
296445726 ps |
| T2031 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/51.xbar_error_and_unmapped_addr.926938826 |
|
|
Sep 04 06:33:32 PM UTC 24 |
Sep 04 06:34:12 PM UTC 24 |
853676555 ps |
| T2032 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/27.xbar_access_same_device_slow_rsp.3181414855 |
|
|
Sep 04 06:00:40 PM UTC 24 |
Sep 04 06:34:24 PM UTC 24 |
131672348569 ps |
| T2033 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/52.xbar_smoke.141416869 |
|
|
Sep 04 06:34:21 PM UTC 24 |
Sep 04 06:34:28 PM UTC 24 |
45576086 ps |
| T873 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/49.xbar_stress_all_with_reset_error.202886103 |
|
|
Sep 04 06:31:12 PM UTC 24 |
Sep 04 06:34:31 PM UTC 24 |
913105211 ps |
| T2034 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/51.xbar_stress_all.1704201708 |
|
|
Sep 04 06:33:42 PM UTC 24 |
Sep 04 06:34:32 PM UTC 24 |
1741955663 ps |
| T2035 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/50.xbar_stress_all_with_reset_error.3327949671 |
|
|
Sep 04 06:32:39 PM UTC 24 |
Sep 04 06:34:33 PM UTC 24 |
534134273 ps |
| T2036 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/52.xbar_smoke_zero_delays.985743060 |
|
|
Sep 04 06:34:24 PM UTC 24 |
Sep 04 06:34:35 PM UTC 24 |
53676567 ps |
| T2037 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/51.xbar_smoke_large_delays.2445715587 |
|
|
Sep 04 06:32:52 PM UTC 24 |
Sep 04 06:34:38 PM UTC 24 |
8799420073 ps |
| T525 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/45.xbar_random_large_delays.3353889461 |
|
|
Sep 04 06:24:40 PM UTC 24 |
Sep 04 06:34:43 PM UTC 24 |
48186848939 ps |
| T2038 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/43.xbar_random_large_delays.140225763 |
|
|
Sep 04 06:22:11 PM UTC 24 |
Sep 04 06:34:45 PM UTC 24 |
71810491302 ps |
| T2039 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/25.xbar_access_same_device_slow_rsp.833624805 |
|
|
Sep 04 05:57:29 PM UTC 24 |
Sep 04 06:34:50 PM UTC 24 |
139375515969 ps |
| T2040 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/51.xbar_access_same_device.4189251392 |
|
|
Sep 04 06:33:17 PM UTC 24 |
Sep 04 06:35:01 PM UTC 24 |
1906277047 ps |
| T2041 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/47.xbar_random_slow_rsp.4036672039 |
|
|
Sep 04 06:27:06 PM UTC 24 |
Sep 04 06:35:03 PM UTC 24 |
33598687869 ps |
| T2042 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/52.xbar_random.1395940331 |
|
|
Sep 04 06:34:44 PM UTC 24 |
Sep 04 06:35:09 PM UTC 24 |
164736011 ps |
| T2043 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/52.xbar_error_random.372586714 |
|
|
Sep 04 06:35:03 PM UTC 24 |
Sep 04 06:35:16 PM UTC 24 |
66088083 ps |
| T2044 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/46.xbar_random_slow_rsp.1349375411 |
|
|
Sep 04 06:25:50 PM UTC 24 |
Sep 04 06:35:26 PM UTC 24 |
38593659550 ps |
| T2045 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/52.xbar_access_same_device.3403088235 |
|
|
Sep 04 06:35:04 PM UTC 24 |
Sep 04 06:35:29 PM UTC 24 |
318167217 ps |
| T2046 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/49.xbar_stress_all.707890228 |
|
|
Sep 04 06:30:52 PM UTC 24 |
Sep 04 06:35:33 PM UTC 24 |
7191940746 ps |
| T2047 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/52.xbar_error_and_unmapped_addr.1082153298 |
|
|
Sep 04 06:35:14 PM UTC 24 |
Sep 04 06:35:33 PM UTC 24 |
142346094 ps |
| T878 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/48.xbar_stress_all_with_reset_error.1757461057 |
|
|
Sep 04 06:29:27 PM UTC 24 |
Sep 04 06:35:35 PM UTC 24 |
5762830322 ps |
| T2048 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/52.xbar_random_zero_delays.893303756 |
|
|
Sep 04 06:34:40 PM UTC 24 |
Sep 04 06:35:40 PM UTC 24 |
518319820 ps |
| T478 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/52.xbar_unmapped_addr.1813938830 |
|
|
Sep 04 06:35:10 PM UTC 24 |
Sep 04 06:35:47 PM UTC 24 |
281671496 ps |
| T2049 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/53.xbar_smoke.1743399780 |
|
|
Sep 04 06:35:40 PM UTC 24 |
Sep 04 06:35:55 PM UTC 24 |
236607765 ps |
| T2050 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/53.xbar_smoke_zero_delays.440528816 |
|
|
Sep 04 06:35:48 PM UTC 24 |
Sep 04 06:35:58 PM UTC 24 |
52845683 ps |
| T2051 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/49.xbar_stress_all_with_error.509563171 |
|
|
Sep 04 06:30:58 PM UTC 24 |
Sep 04 06:36:00 PM UTC 24 |
4197217027 ps |
| T2052 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/39.xbar_access_same_device_slow_rsp.2489982484 |
|
|
Sep 04 06:18:19 PM UTC 24 |
Sep 04 06:36:00 PM UTC 24 |
67645857544 ps |
| T2053 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/52.xbar_stress_all.621219019 |
|
|
Sep 04 06:35:15 PM UTC 24 |
Sep 04 06:36:02 PM UTC 24 |
1195239073 ps |
| T2054 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/52.xbar_smoke_slow_rsp.3115872217 |
|
|
Sep 04 06:34:28 PM UTC 24 |
Sep 04 06:36:03 PM UTC 24 |
6711056195 ps |
| T2055 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/50.xbar_random_large_delays.3686334401 |
|
|
Sep 04 06:31:51 PM UTC 24 |
Sep 04 06:36:04 PM UTC 24 |
28236717666 ps |
| T2056 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/52.xbar_stress_all_with_error.4051504770 |
|
|
Sep 04 06:35:30 PM UTC 24 |
Sep 04 06:36:09 PM UTC 24 |
411635397 ps |
| T2057 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/42.xbar_random_large_delays.1769355747 |
|
|
Sep 04 06:21:26 PM UTC 24 |
Sep 04 06:36:10 PM UTC 24 |
87244514092 ps |
| T2058 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/53.xbar_random_zero_delays.2575545969 |
|
|
Sep 04 06:36:03 PM UTC 24 |
Sep 04 06:36:17 PM UTC 24 |
66312539 ps |
| T2059 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/52.xbar_same_source.354805787 |
|
|
Sep 04 06:35:04 PM UTC 24 |
Sep 04 06:36:17 PM UTC 24 |
1980964752 ps |
| T2060 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/52.xbar_smoke_large_delays.671676078 |
|
|
Sep 04 06:34:30 PM UTC 24 |
Sep 04 06:36:23 PM UTC 24 |
7054141703 ps |
| T2061 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/53.xbar_random.1312455992 |
|
|
Sep 04 06:36:03 PM UTC 24 |
Sep 04 06:36:32 PM UTC 24 |
578297806 ps |
| T2062 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/53.xbar_error_and_unmapped_addr.1389275573 |
|
|
Sep 04 06:36:33 PM UTC 24 |
Sep 04 06:36:41 PM UTC 24 |
79611192 ps |
| T2063 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/50.xbar_random_slow_rsp.1753143872 |
|
|
Sep 04 06:31:57 PM UTC 24 |
Sep 04 06:36:49 PM UTC 24 |
19252192229 ps |
| T2064 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/54.xbar_smoke.4097182993 |
|
|
Sep 04 06:36:49 PM UTC 24 |
Sep 04 06:36:58 PM UTC 24 |
41415678 ps |
| T2065 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/53.xbar_smoke_large_delays.2265739337 |
|
|
Sep 04 06:35:57 PM UTC 24 |
Sep 04 06:36:59 PM UTC 24 |
7258272518 ps |
| T2066 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/51.xbar_random_slow_rsp.1519229484 |
|
|
Sep 04 06:33:06 PM UTC 24 |
Sep 04 06:37:14 PM UTC 24 |
14021511575 ps |
| T2067 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/51.xbar_stress_all_with_error.2394379204 |
|
|
Sep 04 06:34:06 PM UTC 24 |
Sep 04 06:37:24 PM UTC 24 |
5525319289 ps |
| T2068 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/53.xbar_same_source.4176411824 |
|
|
Sep 04 06:36:26 PM UTC 24 |
Sep 04 06:37:27 PM UTC 24 |
1796575248 ps |
| T2069 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/53.xbar_unmapped_addr.1737321977 |
|
|
Sep 04 06:36:31 PM UTC 24 |
Sep 04 06:37:32 PM UTC 24 |
981754236 ps |
| T2070 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/53.xbar_smoke_slow_rsp.1176640347 |
|
|
Sep 04 06:36:00 PM UTC 24 |
Sep 04 06:37:44 PM UTC 24 |
6616930127 ps |
| T2071 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/53.xbar_error_random.835678762 |
|
|
Sep 04 06:36:31 PM UTC 24 |
Sep 04 06:37:45 PM UTC 24 |
2508967098 ps |
| T2072 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/12.chip_same_csr_outstanding.1997936947 |
|
|
Sep 04 05:27:54 PM UTC 24 |
Sep 04 06:37:53 PM UTC 24 |
30693888648 ps |
| T2073 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/50.xbar_stress_all.888955833 |
|
|
Sep 04 06:32:28 PM UTC 24 |
Sep 04 06:38:01 PM UTC 24 |
3350430951 ps |
| T2074 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/54.xbar_smoke_slow_rsp.1412014109 |
|
|
Sep 04 06:37:01 PM UTC 24 |
Sep 04 06:38:10 PM UTC 24 |
3123982773 ps |
| T2075 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/54.xbar_same_source.2742552801 |
|
|
Sep 04 06:37:56 PM UTC 24 |
Sep 04 06:38:11 PM UTC 24 |
101882890 ps |
| T2076 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/54.xbar_random_zero_delays.944820317 |
|
|
Sep 04 06:37:20 PM UTC 24 |
Sep 04 06:38:15 PM UTC 24 |
546366529 ps |
| T2077 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/54.xbar_random.1697730022 |
|
|
Sep 04 06:37:10 PM UTC 24 |
Sep 04 06:38:20 PM UTC 24 |
2198902359 ps |
| T2078 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/53.xbar_access_same_device.177860058 |
|
|
Sep 04 06:36:18 PM UTC 24 |
Sep 04 06:38:21 PM UTC 24 |
2618880760 ps |
| T2079 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/44.xbar_random_slow_rsp.858793016 |
|
|
Sep 04 06:23:36 PM UTC 24 |
Sep 04 06:38:30 PM UTC 24 |
54826973138 ps |
| T638 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/46.xbar_stress_all_with_reset_error.475208147 |
|
|
Sep 04 06:26:45 PM UTC 24 |
Sep 04 06:38:32 PM UTC 24 |
8903117742 ps |
| T2080 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/54.xbar_error_random.1811422974 |
|
|
Sep 04 06:37:57 PM UTC 24 |
Sep 04 06:38:32 PM UTC 24 |
310524808 ps |
| T2081 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/55.xbar_smoke.3128247752 |
|
|
Sep 04 06:38:42 PM UTC 24 |
Sep 04 06:38:53 PM UTC 24 |
219293728 ps |
| T2082 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/54.xbar_error_and_unmapped_addr.2774126158 |
|
|
Sep 04 06:38:15 PM UTC 24 |
Sep 04 06:38:53 PM UTC 24 |
241157654 ps |
| T2083 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/55.xbar_smoke_zero_delays.4260776567 |
|
|
Sep 04 06:38:43 PM UTC 24 |
Sep 04 06:38:53 PM UTC 24 |
53825109 ps |
| T2084 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/54.xbar_smoke_large_delays.3406350090 |
|
|
Sep 04 06:36:55 PM UTC 24 |
Sep 04 06:38:55 PM UTC 24 |
10511020814 ps |
| T2085 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/54.xbar_unmapped_addr.382095002 |
|
|
Sep 04 06:38:01 PM UTC 24 |
Sep 04 06:39:01 PM UTC 24 |
999621804 ps |
| T604 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/45.xbar_stress_all_with_reset_error.4104862306 |
|
|
Sep 04 06:25:15 PM UTC 24 |
Sep 04 06:39:07 PM UTC 24 |
20143985117 ps |
| T2086 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/54.xbar_stress_all_with_rand_reset.2305809412 |
|
|
Sep 04 06:38:25 PM UTC 24 |
Sep 04 06:39:14 PM UTC 24 |
67689322 ps |
| T2087 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/53.xbar_stress_all_with_error.1837165548 |
|
|
Sep 04 06:36:36 PM UTC 24 |
Sep 04 06:39:32 PM UTC 24 |
2030994531 ps |
| T2088 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/54.xbar_access_same_device.892045925 |
|
|
Sep 04 06:37:24 PM UTC 24 |
Sep 04 06:39:37 PM UTC 24 |
3063003264 ps |
| T2089 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/55.xbar_same_source.3391890027 |
|
|
Sep 04 06:39:25 PM UTC 24 |
Sep 04 06:39:37 PM UTC 24 |
63679367 ps |
| T2090 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/53.xbar_stress_all.3168206215 |
|
|
Sep 04 06:36:35 PM UTC 24 |
Sep 04 06:39:37 PM UTC 24 |
1774012183 ps |
| T2091 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/48.xbar_random_slow_rsp.1188139666 |
|
|
Sep 04 06:28:32 PM UTC 24 |
Sep 04 06:39:40 PM UTC 24 |
47389385765 ps |
| T2092 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/55.xbar_access_same_device.4231995818 |
|
|
Sep 04 06:39:22 PM UTC 24 |
Sep 04 06:39:43 PM UTC 24 |
567821962 ps |
| T2093 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/55.xbar_random_zero_delays.562093585 |
|
|
Sep 04 06:39:03 PM UTC 24 |
Sep 04 06:39:51 PM UTC 24 |
452887631 ps |
| T2094 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/55.xbar_random.2949676874 |
|
|
Sep 04 06:39:00 PM UTC 24 |
Sep 04 06:39:53 PM UTC 24 |
515189504 ps |
| T2095 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/48.xbar_random_large_delays.358344305 |
|
|
Sep 04 06:28:34 PM UTC 24 |
Sep 04 06:39:54 PM UTC 24 |
64280816019 ps |
| T501 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/43.xbar_random_slow_rsp.2038980553 |
|
|
Sep 04 06:22:08 PM UTC 24 |
Sep 04 06:39:55 PM UTC 24 |
62756450662 ps |
| T2096 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/38.xbar_access_same_device_slow_rsp.766844930 |
|
|
Sep 04 06:17:15 PM UTC 24 |
Sep 04 06:39:55 PM UTC 24 |
83738538909 ps |
| T2097 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/51.xbar_stress_all_with_reset_error.3787561062 |
|
|
Sep 04 06:34:21 PM UTC 24 |
Sep 04 06:39:57 PM UTC 24 |
4086486073 ps |
| T2098 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/55.xbar_smoke_large_delays.1388665189 |
|
|
Sep 04 06:38:50 PM UTC 24 |
Sep 04 06:40:06 PM UTC 24 |
8076480892 ps |
| T2099 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/55.xbar_error_random.1547151092 |
|
|
Sep 04 06:39:31 PM UTC 24 |
Sep 04 06:40:07 PM UTC 24 |
319049198 ps |
| T2100 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/54.xbar_stress_all_with_reset_error.3106784522 |
|
|
Sep 04 06:38:40 PM UTC 24 |
Sep 04 06:40:15 PM UTC 24 |
236020910 ps |
| T2101 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/55.xbar_smoke_slow_rsp.2854980791 |
|
|
Sep 04 06:38:46 PM UTC 24 |
Sep 04 06:40:15 PM UTC 24 |
4412350238 ps |
| T2102 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/55.xbar_unmapped_addr.3452322438 |
|
|
Sep 04 06:39:39 PM UTC 24 |
Sep 04 06:40:16 PM UTC 24 |
859715201 ps |
| T527 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/35.xbar_access_same_device_slow_rsp.1800019937 |
|
|
Sep 04 06:13:00 PM UTC 24 |
Sep 04 06:40:18 PM UTC 24 |
111426203685 ps |
| T2103 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/52.xbar_random_slow_rsp.2827927418 |
|
|
Sep 04 06:34:56 PM UTC 24 |
Sep 04 06:40:18 PM UTC 24 |
16416409293 ps |
| T2104 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/56.xbar_smoke.2660037358 |
|
|
Sep 04 06:40:10 PM UTC 24 |
Sep 04 06:40:18 PM UTC 24 |
40139470 ps |
| T2105 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/56.xbar_smoke_zero_delays.909187075 |
|
|
Sep 04 06:40:13 PM UTC 24 |
Sep 04 06:40:23 PM UTC 24 |
53661841 ps |
| T2106 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/53.xbar_stress_all_with_rand_reset.3837109816 |
|
|
Sep 04 06:36:31 PM UTC 24 |
Sep 04 06:40:27 PM UTC 24 |
3087743082 ps |
| T2107 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/55.xbar_random_slow_rsp.3284365507 |
|
|
Sep 04 06:39:20 PM UTC 24 |
Sep 04 06:40:34 PM UTC 24 |
3560443650 ps |
| T2108 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/55.xbar_stress_all_with_rand_reset.761326932 |
|
|
Sep 04 06:40:07 PM UTC 24 |
Sep 04 06:40:35 PM UTC 24 |
73748139 ps |
| T2109 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/55.xbar_error_and_unmapped_addr.371514779 |
|
|
Sep 04 06:39:46 PM UTC 24 |
Sep 04 06:40:44 PM UTC 24 |
1400768746 ps |
| T2110 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/54.xbar_stress_all_with_error.747939775 |
|
|
Sep 04 06:38:32 PM UTC 24 |
Sep 04 06:40:44 PM UTC 24 |
2140891048 ps |
| T2111 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/54.xbar_random_slow_rsp.3806934098 |
|
|
Sep 04 06:37:26 PM UTC 24 |
Sep 04 06:40:46 PM UTC 24 |
12196540250 ps |
| T2112 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/56.xbar_error_random.3172131979 |
|
|
Sep 04 06:40:38 PM UTC 24 |
Sep 04 06:40:58 PM UTC 24 |
377416413 ps |
| T2113 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/56.xbar_error_and_unmapped_addr.3244408787 |
|
|
Sep 04 06:40:49 PM UTC 24 |
Sep 04 06:41:05 PM UTC 24 |
240964025 ps |
| T2114 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/56.xbar_same_source.4023375750 |
|
|
Sep 04 06:40:42 PM UTC 24 |
Sep 04 06:41:09 PM UTC 24 |
245194938 ps |
| T2115 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/57.xbar_smoke.3217128065 |
|
|
Sep 04 06:40:58 PM UTC 24 |
Sep 04 06:41:09 PM UTC 24 |
51582854 ps |
| T2116 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/57.xbar_smoke_zero_delays.3251238323 |
|
|
Sep 04 06:41:00 PM UTC 24 |
Sep 04 06:41:10 PM UTC 24 |
40423136 ps |
| T2117 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/56.xbar_stress_all_with_rand_reset.2753903499 |
|
|
Sep 04 06:40:47 PM UTC 24 |
Sep 04 06:41:14 PM UTC 24 |
9814148 ps |
| T2118 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/39.xbar_random_large_delays.2373114552 |
|
|
Sep 04 06:18:00 PM UTC 24 |
Sep 04 06:41:15 PM UTC 24 |
113738122676 ps |
| T2119 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/56.xbar_random_zero_delays.3309777985 |
|
|
Sep 04 06:40:26 PM UTC 24 |
Sep 04 06:41:18 PM UTC 24 |
412042566 ps |
| T2120 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/56.xbar_smoke_large_delays.1182626025 |
|
|
Sep 04 06:40:22 PM UTC 24 |
Sep 04 06:41:30 PM UTC 24 |
7249639878 ps |
| T2121 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/49.xbar_stress_all_with_rand_reset.270214844 |
|
|
Sep 04 06:30:54 PM UTC 24 |
Sep 04 06:41:41 PM UTC 24 |
11795099486 ps |
| T2122 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/56.xbar_unmapped_addr.3474037054 |
|
|
Sep 04 06:40:39 PM UTC 24 |
Sep 04 06:41:42 PM UTC 24 |
1337445691 ps |
| T2123 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/57.xbar_random.19969302 |
|
|
Sep 04 06:41:13 PM UTC 24 |
Sep 04 06:41:42 PM UTC 24 |
339007893 ps |
| T2124 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/56.xbar_random.3797865505 |
|
|
Sep 04 06:40:26 PM UTC 24 |
Sep 04 06:41:42 PM UTC 24 |
2421641411 ps |
| T2125 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/53.xbar_random_large_delays.3934879638 |
|
|
Sep 04 06:36:05 PM UTC 24 |
Sep 04 06:41:43 PM UTC 24 |
27716443954 ps |
| T2126 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/56.xbar_smoke_slow_rsp.2962501229 |
|
|
Sep 04 06:40:21 PM UTC 24 |
Sep 04 06:41:49 PM UTC 24 |
5180282806 ps |
| T2127 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/55.xbar_stress_all.2187471396 |
|
|
Sep 04 06:40:01 PM UTC 24 |
Sep 04 06:41:49 PM UTC 24 |
1264716312 ps |
| T2128 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/57.xbar_random_zero_delays.1276593432 |
|
|
Sep 04 06:41:26 PM UTC 24 |
Sep 04 06:41:52 PM UTC 24 |
189325529 ps |
| T2129 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/57.xbar_unmapped_addr.3207097155 |
|
|
Sep 04 06:41:46 PM UTC 24 |
Sep 04 06:41:57 PM UTC 24 |
70692091 ps |
| T2130 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/57.xbar_same_source.224578650 |
|
|
Sep 04 06:41:46 PM UTC 24 |
Sep 04 06:42:00 PM UTC 24 |
315636454 ps |
| T2131 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/47.xbar_random_large_delays.1494390488 |
|
|
Sep 04 06:27:05 PM UTC 24 |
Sep 04 06:42:05 PM UTC 24 |
90438992789 ps |
| T2132 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/57.xbar_error_random.2281806983 |
|
|
Sep 04 06:41:47 PM UTC 24 |
Sep 04 06:42:06 PM UTC 24 |
277416999 ps |
| T2133 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/58.xbar_smoke.1635679132 |
|
|
Sep 04 06:42:07 PM UTC 24 |
Sep 04 06:42:16 PM UTC 24 |
35643844 ps |
| T2134 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/52.xbar_stress_all_with_rand_reset.2477416810 |
|
|
Sep 04 06:35:18 PM UTC 24 |
Sep 04 06:42:19 PM UTC 24 |
2445731602 ps |
| T2135 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/56.xbar_access_same_device.4207280957 |
|
|
Sep 04 06:40:33 PM UTC 24 |
Sep 04 06:42:24 PM UTC 24 |
1981867143 ps |
| T2136 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/57.xbar_smoke_slow_rsp.4240104688 |
|
|
Sep 04 06:41:11 PM UTC 24 |
Sep 04 06:42:24 PM UTC 24 |
4066170219 ps |
| T2137 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/57.xbar_access_same_device.1619751832 |
|
|
Sep 04 06:41:40 PM UTC 24 |
Sep 04 06:42:26 PM UTC 24 |
854545443 ps |
| T2138 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/58.xbar_smoke_zero_delays.3226188108 |
|
|
Sep 04 06:42:19 PM UTC 24 |
Sep 04 06:42:29 PM UTC 24 |
54160385 ps |
| T2139 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/40.xbar_access_same_device_slow_rsp.649230571 |
|
|
Sep 04 06:19:41 PM UTC 24 |
Sep 04 06:42:31 PM UTC 24 |
96122908667 ps |
| T2140 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/56.xbar_random_large_delays.3949261759 |
|
|
Sep 04 06:40:26 PM UTC 24 |
Sep 04 06:42:35 PM UTC 24 |
12849699976 ps |
| T2141 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/58.xbar_random.3273040168 |
|
|
Sep 04 06:42:28 PM UTC 24 |
Sep 04 06:42:36 PM UTC 24 |
71554923 ps |
| T867 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/53.xbar_stress_all_with_reset_error.2765181423 |
|
|
Sep 04 06:36:39 PM UTC 24 |
Sep 04 06:42:46 PM UTC 24 |
6640893603 ps |
| T2142 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/56.xbar_stress_all.3077040285 |
|
|
Sep 04 06:40:48 PM UTC 24 |
Sep 04 06:42:49 PM UTC 24 |
4112350391 ps |
| T2143 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/57.xbar_error_and_unmapped_addr.964935453 |
|
|
Sep 04 06:41:59 PM UTC 24 |
Sep 04 06:42:57 PM UTC 24 |
1160196742 ps |
| T2144 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/52.xbar_stress_all_with_reset_error.1105412521 |
|
|
Sep 04 06:35:30 PM UTC 24 |
Sep 04 06:43:01 PM UTC 24 |
8076204500 ps |
| T2145 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/58.xbar_error_and_unmapped_addr.2277440363 |
|
|
Sep 04 06:42:54 PM UTC 24 |
Sep 04 06:43:05 PM UTC 24 |
53074210 ps |
| T2146 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/58.xbar_random_zero_delays.3672736473 |
|
|
Sep 04 06:42:30 PM UTC 24 |
Sep 04 06:43:05 PM UTC 24 |
441101429 ps |
| T2147 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/18.chip_same_csr_outstanding.1781114305 |
|
|
Sep 04 05:42:43 PM UTC 24 |
Sep 04 06:43:13 PM UTC 24 |
31074995792 ps |
| T2148 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/58.xbar_unmapped_addr.3596634589 |
|
|
Sep 04 06:42:55 PM UTC 24 |
Sep 04 06:43:25 PM UTC 24 |
458538695 ps |
| T2149 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/58.xbar_smoke_large_delays.2327507772 |
|
|
Sep 04 06:42:13 PM UTC 24 |
Sep 04 06:43:29 PM UTC 24 |
8098758897 ps |
| T2150 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/59.xbar_smoke.1711377917 |
|
|
Sep 04 06:43:18 PM UTC 24 |
Sep 04 06:43:29 PM UTC 24 |
124977914 ps |
| T2151 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/56.xbar_stress_all_with_reset_error.3754642875 |
|
|
Sep 04 06:40:56 PM UTC 24 |
Sep 04 06:43:34 PM UTC 24 |
891557129 ps |
| T2152 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/59.xbar_smoke_zero_delays.1734101791 |
|
|
Sep 04 06:43:26 PM UTC 24 |
Sep 04 06:43:37 PM UTC 24 |
55381110 ps |
| T2153 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/55.xbar_stress_all_with_error.3380478316 |
|
|
Sep 04 06:40:07 PM UTC 24 |
Sep 04 06:43:43 PM UTC 24 |
2730235765 ps |
| T2154 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/57.xbar_smoke_large_delays.4264876290 |
|
|
Sep 04 06:41:13 PM UTC 24 |
Sep 04 06:43:45 PM UTC 24 |
9863236154 ps |
| T2155 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/50.xbar_stress_all_with_rand_reset.197285216 |
|
|
Sep 04 06:32:33 PM UTC 24 |
Sep 04 06:43:46 PM UTC 24 |
6985993377 ps |
| T2156 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/58.xbar_stress_all.249164343 |
|
|
Sep 04 06:42:58 PM UTC 24 |
Sep 04 06:43:54 PM UTC 24 |
2054344614 ps |
| T2157 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/58.xbar_stress_all_with_rand_reset.2897972004 |
|
|
Sep 04 06:43:02 PM UTC 24 |
Sep 04 06:44:13 PM UTC 24 |
41849360 ps |
| T2158 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/58.xbar_error_random.1498653126 |
|
|
Sep 04 06:42:49 PM UTC 24 |
Sep 04 06:44:16 PM UTC 24 |
2184457300 ps |
| T2159 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/59.xbar_same_source.1485837877 |
|
|
Sep 04 06:44:04 PM UTC 24 |
Sep 04 06:44:18 PM UTC 24 |
216279016 ps |
| T2160 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/59.xbar_error_and_unmapped_addr.2174434885 |
|
|
Sep 04 06:44:14 PM UTC 24 |
Sep 04 06:44:22 PM UTC 24 |
18113206 ps |
| T2161 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/58.xbar_same_source.700130286 |
|
|
Sep 04 06:42:55 PM UTC 24 |
Sep 04 06:44:23 PM UTC 24 |
2415373344 ps |
| T2162 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/15.chip_same_csr_outstanding.996199924 |
|
|
Sep 04 05:34:27 PM UTC 24 |
Sep 04 06:44:23 PM UTC 24 |
29972673706 ps |
| T2163 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/59.xbar_random.1141480477 |
|
|
Sep 04 06:43:25 PM UTC 24 |
Sep 04 06:44:33 PM UTC 24 |
1730893359 ps |
| T2164 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/43.xbar_access_same_device_slow_rsp.4016076647 |
|
|
Sep 04 06:22:33 PM UTC 24 |
Sep 04 06:44:34 PM UTC 24 |
83263935963 ps |
| T509 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/59.xbar_access_same_device.2243882823 |
|
|
Sep 04 06:43:58 PM UTC 24 |
Sep 04 06:44:36 PM UTC 24 |
628271272 ps |
| T2165 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/59.xbar_random_zero_delays.377048655 |
|
|
Sep 04 06:43:45 PM UTC 24 |
Sep 04 06:44:38 PM UTC 24 |
449397995 ps |
| T2166 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/58.xbar_smoke_slow_rsp.2691969925 |
|
|
Sep 04 06:42:19 PM UTC 24 |
Sep 04 06:44:40 PM UTC 24 |
5896907838 ps |
| T2167 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/59.xbar_smoke_slow_rsp.524271207 |
|
|
Sep 04 06:43:30 PM UTC 24 |
Sep 04 06:44:40 PM UTC 24 |
5236866132 ps |
| T2168 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/59.xbar_smoke_large_delays.951782472 |
|
|
Sep 04 06:43:30 PM UTC 24 |
Sep 04 06:44:45 PM UTC 24 |
6692980046 ps |
| T2169 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/55.xbar_stress_all_with_reset_error.592577826 |
|
|
Sep 04 06:40:05 PM UTC 24 |
Sep 04 06:44:46 PM UTC 24 |
944319595 ps |
| T2170 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/58.xbar_access_same_device.3260827234 |
|
|
Sep 04 06:42:43 PM UTC 24 |
Sep 04 06:44:46 PM UTC 24 |
3372205881 ps |
| T2171 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/59.xbar_error_random.2534038881 |
|
|
Sep 04 06:44:12 PM UTC 24 |
Sep 04 06:44:52 PM UTC 24 |
1532790847 ps |
| T2172 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/60.xbar_smoke.2842307944 |
|
|
Sep 04 06:44:47 PM UTC 24 |
Sep 04 06:44:58 PM UTC 24 |
48380695 ps |
| T2173 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/60.xbar_smoke_zero_delays.3632799448 |
|
|
Sep 04 06:44:53 PM UTC 24 |
Sep 04 06:45:01 PM UTC 24 |
35730218 ps |
| T2174 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/49.xbar_random_slow_rsp.1320859464 |
|
|
Sep 04 06:30:08 PM UTC 24 |
Sep 04 06:45:05 PM UTC 24 |
53462243929 ps |
| T2175 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/59.xbar_unmapped_addr.3904176152 |
|
|
Sep 04 06:44:09 PM UTC 24 |
Sep 04 06:45:15 PM UTC 24 |
1338358731 ps |
| T2176 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/60.xbar_error_random.986966755 |
|
|
Sep 04 06:45:14 PM UTC 24 |
Sep 04 06:45:26 PM UTC 24 |
96770085 ps |
| T2177 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/56.xbar_stress_all_with_error.3891846030 |
|
|
Sep 04 06:40:53 PM UTC 24 |
Sep 04 06:45:27 PM UTC 24 |
3072908031 ps |
| T2178 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/60.xbar_unmapped_addr.2904461680 |
|
|
Sep 04 06:45:22 PM UTC 24 |
Sep 04 06:45:33 PM UTC 24 |
171417949 ps |
| T2179 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/49.xbar_random_large_delays.3317988557 |
|
|
Sep 04 06:30:07 PM UTC 24 |
Sep 04 06:45:35 PM UTC 24 |
92438608669 ps |
| T2180 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/60.xbar_same_source.3685412530 |
|
|
Sep 04 06:45:13 PM UTC 24 |
Sep 04 06:45:37 PM UTC 24 |
329965684 ps |
| T2181 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/51.xbar_stress_all_with_rand_reset.811988394 |
|
|
Sep 04 06:33:51 PM UTC 24 |
Sep 04 06:45:51 PM UTC 24 |
14204595949 ps |
| T2182 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/60.xbar_random.4063213840 |
|
|
Sep 04 06:45:04 PM UTC 24 |
Sep 04 06:45:54 PM UTC 24 |
1214825652 ps |
| T2183 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/57.xbar_access_same_device_slow_rsp.782009887 |
|
|
Sep 04 06:41:42 PM UTC 24 |
Sep 04 06:45:55 PM UTC 24 |
12695786455 ps |
| T2184 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/46.xbar_access_same_device_slow_rsp.3958471871 |
|
|
Sep 04 06:26:01 PM UTC 24 |
Sep 04 06:45:56 PM UTC 24 |
73413801055 ps |
| T2185 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/60.xbar_random_zero_delays.3337061548 |
|
|
Sep 04 06:45:05 PM UTC 24 |
Sep 04 06:45:57 PM UTC 24 |
634673283 ps |
| T2186 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/57.xbar_random_large_delays.1211967849 |
|
|
Sep 04 06:41:37 PM UTC 24 |
Sep 04 06:46:01 PM UTC 24 |
24016121891 ps |
| T2187 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/61.xbar_smoke.2255407487 |
|
|
Sep 04 06:45:59 PM UTC 24 |
Sep 04 06:46:11 PM UTC 24 |
236145528 ps |
| T2188 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/61.xbar_smoke_zero_delays.444880927 |
|
|
Sep 04 06:46:03 PM UTC 24 |
Sep 04 06:46:14 PM UTC 24 |
46016773 ps |
| T2189 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/60.xbar_error_and_unmapped_addr.979661059 |
|
|
Sep 04 06:45:27 PM UTC 24 |
Sep 04 06:46:23 PM UTC 24 |
1255332982 ps |
| T2190 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/60.xbar_smoke_large_delays.1182841489 |
|
|
Sep 04 06:44:54 PM UTC 24 |
Sep 04 06:46:29 PM UTC 24 |
8197703599 ps |
| T2191 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/60.xbar_smoke_slow_rsp.2633202157 |
|
|
Sep 04 06:45:02 PM UTC 24 |
Sep 04 06:46:33 PM UTC 24 |
5293312957 ps |
| T2192 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/54.xbar_stress_all.1116607254 |
|
|
Sep 04 06:38:18 PM UTC 24 |
Sep 04 06:46:34 PM UTC 24 |
14076931785 ps |
| T2193 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/60.xbar_access_same_device.1982103855 |
|
|
Sep 04 06:45:10 PM UTC 24 |
Sep 04 06:46:37 PM UTC 24 |
1889084968 ps |
| T2194 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/61.xbar_random.1049741457 |
|
|
Sep 04 06:46:23 PM UTC 24 |
Sep 04 06:46:56 PM UTC 24 |
670332264 ps |
| T2195 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/61.xbar_random_zero_delays.1423632299 |
|
|
Sep 04 06:46:24 PM UTC 24 |
Sep 04 06:46:58 PM UTC 24 |
257456622 ps |
| T2196 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/61.xbar_error_random.1946674557 |
|
|
Sep 04 06:46:42 PM UTC 24 |
Sep 04 06:47:08 PM UTC 24 |
682286757 ps |
| T2197 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/37.xbar_access_same_device_slow_rsp.1814326440 |
|
|
Sep 04 06:15:59 PM UTC 24 |
Sep 04 06:47:09 PM UTC 24 |
131788535121 ps |
| T2198 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/61.xbar_smoke_slow_rsp.1672811545 |
|
|
Sep 04 06:46:07 PM UTC 24 |
Sep 04 06:47:13 PM UTC 24 |
4242334194 ps |
| T2199 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/58.xbar_stress_all_with_error.54701400 |
|
|
Sep 04 06:43:03 PM UTC 24 |
Sep 04 06:47:23 PM UTC 24 |
3113402730 ps |
| T2200 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/61.xbar_error_and_unmapped_addr.1043751491 |
|
|
Sep 04 06:46:59 PM UTC 24 |
Sep 04 06:47:26 PM UTC 24 |
176549154 ps |
| T2201 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/33.xbar_access_same_device_slow_rsp.1942839913 |
|
|
Sep 04 06:10:16 PM UTC 24 |
Sep 04 06:47:26 PM UTC 24 |
158442617490 ps |
| T2202 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/54.xbar_random_large_delays.3541882829 |
|
|
Sep 04 06:37:28 PM UTC 24 |
Sep 04 06:47:31 PM UTC 24 |
55580158317 ps |
| T2203 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/53.xbar_access_same_device_slow_rsp.786297234 |
|
|
Sep 04 06:36:25 PM UTC 24 |
Sep 04 06:47:32 PM UTC 24 |
47011694176 ps |
| T2204 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/61.xbar_same_source.1309018840 |
|
|
Sep 04 06:46:42 PM UTC 24 |
Sep 04 06:47:32 PM UTC 24 |
521815664 ps |
| T2205 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/62.xbar_smoke.328094791 |
|
|
Sep 04 06:47:27 PM UTC 24 |
Sep 04 06:47:37 PM UTC 24 |
43633238 ps |
| T2206 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/44.xbar_access_same_device_slow_rsp.1057614729 |
|
|
Sep 04 06:23:43 PM UTC 24 |
Sep 04 06:47:38 PM UTC 24 |
99973264554 ps |
| T2207 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/61.xbar_smoke_large_delays.4142377218 |
|
|
Sep 04 06:46:07 PM UTC 24 |
Sep 04 06:47:42 PM UTC 24 |
8831830994 ps |
| T2208 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/62.xbar_smoke_zero_delays.311855369 |
|
|
Sep 04 06:47:38 PM UTC 24 |
Sep 04 06:47:47 PM UTC 24 |
44978990 ps |
| T2209 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/61.xbar_unmapped_addr.1722843727 |
|
|
Sep 04 06:46:51 PM UTC 24 |
Sep 04 06:47:54 PM UTC 24 |
1191899760 ps |
| T2210 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/60.xbar_stress_all_with_reset_error.4100950630 |
|
|
Sep 04 06:45:58 PM UTC 24 |
Sep 04 06:47:57 PM UTC 24 |
1628888228 ps |
| T883 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/60.xbar_stress_all_with_rand_reset.3191335203 |
|
|
Sep 04 06:45:35 PM UTC 24 |
Sep 04 06:48:00 PM UTC 24 |
288065346 ps |
| T2211 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/57.xbar_stress_all_with_error.4216253373 |
|
|
Sep 04 06:42:11 PM UTC 24 |
Sep 04 06:48:11 PM UTC 24 |
9417216397 ps |
| T2212 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/61.xbar_access_same_device.3981511810 |
|
|
Sep 04 06:46:28 PM UTC 24 |
Sep 04 06:48:12 PM UTC 24 |
2961730298 ps |
| T2213 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/62.xbar_access_same_device.271719950 |
|
|
Sep 04 06:48:02 PM UTC 24 |
Sep 04 06:48:21 PM UTC 24 |
262869895 ps |
| T2214 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/56.xbar_random_slow_rsp.97022739 |
|
|
Sep 04 06:40:26 PM UTC 24 |
Sep 04 06:48:23 PM UTC 24 |
31653869421 ps |
| T2215 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/62.xbar_error_random.2587811599 |
|
|
Sep 04 06:48:05 PM UTC 24 |
Sep 04 06:48:42 PM UTC 24 |
1099517090 ps |
| T2216 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/62.xbar_random_zero_delays.1267620969 |
|
|
Sep 04 06:47:56 PM UTC 24 |
Sep 04 06:48:44 PM UTC 24 |
570479426 ps |
| T2217 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/57.xbar_stress_all_with_reset_error.3613411935 |
|
|
Sep 04 06:42:12 PM UTC 24 |
Sep 04 06:48:45 PM UTC 24 |
2564788117 ps |
| T2218 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/62.xbar_unmapped_addr.2513468103 |
|
|
Sep 04 06:48:12 PM UTC 24 |
Sep 04 06:48:46 PM UTC 24 |
309838831 ps |
| T2219 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/62.xbar_random.529872776 |
|
|
Sep 04 06:47:54 PM UTC 24 |
Sep 04 06:48:49 PM UTC 24 |
1194403482 ps |
| T2220 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/63.xbar_smoke.1400392455 |
|
|
Sep 04 06:48:44 PM UTC 24 |
Sep 04 06:48:53 PM UTC 24 |
53919774 ps |
| T2221 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/63.xbar_smoke_zero_delays.3976271961 |
|
|
Sep 04 06:48:52 PM UTC 24 |
Sep 04 06:49:01 PM UTC 24 |
37458402 ps |
| T2222 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/59.xbar_stress_all_with_error.3650115647 |
|
|
Sep 04 06:44:45 PM UTC 24 |
Sep 04 06:49:10 PM UTC 24 |
3435361594 ps |
| T2223 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/62.xbar_smoke_slow_rsp.3681303415 |
|
|
Sep 04 06:47:42 PM UTC 24 |
Sep 04 06:49:15 PM UTC 24 |
6065950906 ps |
| T2224 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/62.xbar_stress_all_with_error.1223099454 |
|
|
Sep 04 06:48:32 PM UTC 24 |
Sep 04 06:49:17 PM UTC 24 |
595704498 ps |
| T2225 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/52.xbar_random_large_delays.912839730 |
|
|
Sep 04 06:34:54 PM UTC 24 |
Sep 04 06:49:17 PM UTC 24 |
87423110972 ps |
| T2226 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/60.xbar_stress_all_with_error.1507860802 |
|
|
Sep 04 06:45:46 PM UTC 24 |
Sep 04 06:49:21 PM UTC 24 |
6704780329 ps |
| T2227 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/48.xbar_access_same_device_slow_rsp.581168972 |
|
|
Sep 04 06:28:32 PM UTC 24 |
Sep 04 06:49:25 PM UTC 24 |
85086787164 ps |
| T2228 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/62.xbar_same_source.2512691629 |
|
|
Sep 04 06:48:04 PM UTC 24 |
Sep 04 06:49:26 PM UTC 24 |
1964043733 ps |
| T2229 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/62.xbar_error_and_unmapped_addr.3624166843 |
|
|
Sep 04 06:48:15 PM UTC 24 |
Sep 04 06:49:28 PM UTC 24 |
1365551037 ps |
| T2230 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/53.xbar_random_slow_rsp.937116879 |
|
|
Sep 04 06:36:07 PM UTC 24 |
Sep 04 06:49:31 PM UTC 24 |
60887414465 ps |
| T2231 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/51.xbar_random_large_delays.3367417621 |
|
|
Sep 04 06:33:08 PM UTC 24 |
Sep 04 06:49:35 PM UTC 24 |
72022816663 ps |
| T2232 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/63.xbar_random_zero_delays.894226172 |
|
|
Sep 04 06:49:16 PM UTC 24 |
Sep 04 06:49:35 PM UTC 24 |
121970947 ps |
| T2233 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/58.xbar_random_slow_rsp.912822706 |
|
|
Sep 04 06:42:33 PM UTC 24 |
Sep 04 06:49:45 PM UTC 24 |
26782883123 ps |
| T2234 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/62.xbar_random_large_delays.706196011 |
|
|
Sep 04 06:47:56 PM UTC 24 |
Sep 04 06:49:46 PM UTC 24 |
11782421912 ps |
| T2235 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/62.xbar_smoke_large_delays.2515100495 |
|
|
Sep 04 06:47:35 PM UTC 24 |
Sep 04 06:49:47 PM UTC 24 |
8267723012 ps |
| T2236 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/61.xbar_stress_all_with_reset_error.1483401501 |
|
|
Sep 04 06:47:22 PM UTC 24 |
Sep 04 06:49:59 PM UTC 24 |
330726513 ps |
| T2237 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/63.xbar_access_same_device.191336323 |
|
|
Sep 04 06:49:25 PM UTC 24 |
Sep 04 06:50:04 PM UTC 24 |
329064009 ps |
| T2238 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/59.xbar_stress_all.184730917 |
|
|
Sep 04 06:44:23 PM UTC 24 |
Sep 04 06:50:08 PM UTC 24 |
10167881244 ps |
| T2239 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/64.xbar_smoke.3710683385 |
|
|
Sep 04 06:50:01 PM UTC 24 |
Sep 04 06:50:11 PM UTC 24 |
48368894 ps |
| T2240 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/63.xbar_same_source.3497923060 |
|
|
Sep 04 06:49:41 PM UTC 24 |
Sep 04 06:50:12 PM UTC 24 |
884057173 ps |
| T2241 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/64.xbar_smoke_zero_delays.1887255507 |
|
|
Sep 04 06:50:05 PM UTC 24 |
Sep 04 06:50:15 PM UTC 24 |
51088293 ps |
| T2242 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/63.xbar_random.2475361333 |
|
|
Sep 04 06:49:14 PM UTC 24 |
Sep 04 06:50:19 PM UTC 24 |
2163611834 ps |
| T2243 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/63.xbar_error_and_unmapped_addr.772306771 |
|
|
Sep 04 06:49:48 PM UTC 24 |
Sep 04 06:50:22 PM UTC 24 |
196830565 ps |
| T2244 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/63.xbar_smoke_large_delays.993421112 |
|
|
Sep 04 06:48:54 PM UTC 24 |
Sep 04 06:50:24 PM UTC 24 |
8603924935 ps |
| T2245 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/63.xbar_unmapped_addr.1882308380 |
|
|
Sep 04 06:49:47 PM UTC 24 |
Sep 04 06:50:30 PM UTC 24 |
295160585 ps |
| T2246 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/63.xbar_error_random.2716237152 |
|
|
Sep 04 06:49:44 PM UTC 24 |
Sep 04 06:50:33 PM UTC 24 |
1527883769 ps |
| T2247 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/63.xbar_stress_all_with_rand_reset.3721610113 |
|
|
Sep 04 06:49:56 PM UTC 24 |
Sep 04 06:50:35 PM UTC 24 |
79153397 ps |
| T2248 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/60.xbar_stress_all.926584914 |
|
|
Sep 04 06:45:25 PM UTC 24 |
Sep 04 06:50:37 PM UTC 24 |
6921803735 ps |
| T2249 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/63.xbar_smoke_slow_rsp.3205050317 |
|
|
Sep 04 06:49:11 PM UTC 24 |
Sep 04 06:50:44 PM UTC 24 |
5964973162 ps |
| T2250 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/64.xbar_random.563901573 |
|
|
Sep 04 06:50:17 PM UTC 24 |
Sep 04 06:50:58 PM UTC 24 |
367408134 ps |
| T2251 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/64.xbar_random_zero_delays.1165751839 |
|
|
Sep 04 06:50:19 PM UTC 24 |
Sep 04 06:51:07 PM UTC 24 |
468388480 ps |
| T2252 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/64.xbar_access_same_device.4038924928 |
|
|
Sep 04 06:50:40 PM UTC 24 |
Sep 04 06:51:09 PM UTC 24 |
560732532 ps |
| T2253 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/64.xbar_error_random.710591165 |
|
|
Sep 04 06:50:44 PM UTC 24 |
Sep 04 06:51:11 PM UTC 24 |
356260712 ps |
| T2254 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/61.xbar_random_large_delays.565472983 |
|
|
Sep 04 06:46:26 PM UTC 24 |
Sep 04 06:51:12 PM UTC 24 |
25593105963 ps |
| T2255 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/62.xbar_stress_all_with_rand_reset.4149922818 |
|
|
Sep 04 06:48:28 PM UTC 24 |
Sep 04 06:51:12 PM UTC 24 |
222693602 ps |
| T2256 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/64.xbar_error_and_unmapped_addr.538814377 |
|
|
Sep 04 06:50:54 PM UTC 24 |
Sep 04 06:51:18 PM UTC 24 |
197602292 ps |
| T2257 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/64.xbar_stress_all_with_reset_error.1885454481 |
|
|
Sep 04 06:51:03 PM UTC 24 |
Sep 04 06:51:21 PM UTC 24 |
7829573 ps |
| T2258 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/65.xbar_smoke.2368725151 |
|
|
Sep 04 06:51:07 PM UTC 24 |
Sep 04 06:51:22 PM UTC 24 |
285481499 ps |
| T2259 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/65.xbar_smoke_zero_delays.3138515078 |
|
|
Sep 04 06:51:12 PM UTC 24 |
Sep 04 06:51:22 PM UTC 24 |
49527614 ps |
| T2260 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/61.xbar_stress_all_with_error.1319394684 |
|
|
Sep 04 06:47:08 PM UTC 24 |
Sep 04 06:51:24 PM UTC 24 |
8054322821 ps |
| T2261 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/64.xbar_smoke_large_delays.2886559440 |
|
|
Sep 04 06:50:05 PM UTC 24 |
Sep 04 06:51:27 PM UTC 24 |
8564011001 ps |
| T2262 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/64.xbar_same_source.3451451423 |
|
|
Sep 04 06:50:44 PM UTC 24 |
Sep 04 06:51:30 PM UTC 24 |
1253901508 ps |
| T2263 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/59.xbar_access_same_device_slow_rsp.675354107 |
|
|
Sep 04 06:44:02 PM UTC 24 |
Sep 04 06:51:34 PM UTC 24 |
28704421382 ps |
| T2264 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/64.xbar_smoke_slow_rsp.3274801742 |
|
|
Sep 04 06:50:13 PM UTC 24 |
Sep 04 06:51:37 PM UTC 24 |
5506358304 ps |
| T2265 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/65.xbar_random.133062968 |
|
|
Sep 04 06:51:38 PM UTC 24 |
Sep 04 06:51:47 PM UTC 24 |
39443833 ps |
| T2266 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/55.xbar_random_large_delays.1114171880 |
|
|
Sep 04 06:38:59 PM UTC 24 |
Sep 04 06:51:51 PM UTC 24 |
72526937209 ps |
| T2267 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/57.xbar_stress_all.3275948142 |
|
|
Sep 04 06:42:08 PM UTC 24 |
Sep 04 06:51:54 PM UTC 24 |
17475470097 ps |