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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
96.02 95.45 93.66 95.48 94.43 97.53 99.54


Total test records in report: 2931
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T2514 /workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/78.xbar_stress_all.1927810541 Sep 04 07:06:11 PM UTC 24 Sep 04 07:07:02 PM UTC 24 602658515 ps
T2515 /workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/77.xbar_stress_all_with_reset_error.182820880 Sep 04 07:05:06 PM UTC 24 Sep 04 07:07:04 PM UTC 24 524030334 ps
T2516 /workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/78.xbar_smoke_large_delays.2955403420 Sep 04 07:05:16 PM UTC 24 Sep 04 07:07:06 PM UTC 24 6560992031 ps
T2517 /workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/79.xbar_access_same_device.1928698722 Sep 04 07:06:52 PM UTC 24 Sep 04 07:07:09 PM UTC 24 110727001 ps
T2518 /workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/79.xbar_unmapped_addr.1074472786 Sep 04 07:07:08 PM UTC 24 Sep 04 07:07:19 PM UTC 24 42237478 ps
T2519 /workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/79.xbar_error_and_unmapped_addr.2445477946 Sep 04 07:07:09 PM UTC 24 Sep 04 07:07:24 PM UTC 24 99703855 ps
T2520 /workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/75.xbar_stress_all_with_rand_reset.2191950633 Sep 04 07:02:46 PM UTC 24 Sep 04 07:07:25 PM UTC 24 2185960264 ps
T2521 /workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/79.xbar_smoke_large_delays.857268900 Sep 04 07:06:31 PM UTC 24 Sep 04 07:07:29 PM UTC 24 6333833608 ps
T2522 /workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/76.xbar_stress_all.696643825 Sep 04 07:03:55 PM UTC 24 Sep 04 07:07:30 PM UTC 24 2938599006 ps
T2523 /workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/76.xbar_random_slow_rsp.4264659859 Sep 04 07:03:32 PM UTC 24 Sep 04 07:07:32 PM UTC 24 17598304836 ps
T2524 /workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/77.xbar_stress_all.1016141900 Sep 04 07:04:57 PM UTC 24 Sep 04 07:07:37 PM UTC 24 5464804834 ps
T2525 /workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/80.xbar_smoke.3410959588 Sep 04 07:07:28 PM UTC 24 Sep 04 07:07:39 PM UTC 24 51922194 ps
T2526 /workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/80.xbar_smoke_zero_delays.2068858230 Sep 04 07:07:33 PM UTC 24 Sep 04 07:07:41 PM UTC 24 53590851 ps
T2527 /workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/79.xbar_same_source.960298285 Sep 04 07:07:02 PM UTC 24 Sep 04 07:07:48 PM UTC 24 544415035 ps
T2528 /workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/80.xbar_random.1878150637 Sep 04 07:07:38 PM UTC 24 Sep 04 07:07:50 PM UTC 24 57712696 ps
T2529 /workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/74.xbar_stress_all_with_reset_error.2689007219 Sep 04 07:01:35 PM UTC 24 Sep 04 07:07:50 PM UTC 24 3834509614 ps
T2530 /workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/79.xbar_smoke_slow_rsp.4033209966 Sep 04 07:06:38 PM UTC 24 Sep 04 07:07:51 PM UTC 24 4651955211 ps
T2531 /workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/70.xbar_stress_all_with_error.547961898 Sep 04 06:57:41 PM UTC 24 Sep 04 07:07:59 PM UTC 24 18286140381 ps
T2532 /workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/78.xbar_stress_all_with_rand_reset.406989303 Sep 04 07:06:20 PM UTC 24 Sep 04 07:08:00 PM UTC 24 204993120 ps
T2533 /workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/78.xbar_access_same_device_slow_rsp.2592260882 Sep 04 07:05:45 PM UTC 24 Sep 04 07:08:02 PM UTC 24 7173398291 ps
T2534 /workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/69.xbar_random_large_delays.128440866 Sep 04 06:55:41 PM UTC 24 Sep 04 07:08:09 PM UTC 24 68754222780 ps
T2535 /workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/79.xbar_random.2278689998 Sep 04 07:06:44 PM UTC 24 Sep 04 07:08:15 PM UTC 24 1937871997 ps
T2536 /workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/76.xbar_stress_all_with_rand_reset.842246019 Sep 04 07:03:56 PM UTC 24 Sep 04 07:08:19 PM UTC 24 775425452 ps
T2537 /workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/80.xbar_random_zero_delays.3048215214 Sep 04 07:07:43 PM UTC 24 Sep 04 07:08:28 PM UTC 24 355647040 ps
T2538 /workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/79.xbar_error_random.4218407337 Sep 04 07:07:05 PM UTC 24 Sep 04 07:08:31 PM UTC 24 2198942660 ps
T2539 /workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/81.xbar_smoke.290768754 Sep 04 07:08:28 PM UTC 24 Sep 04 07:08:40 PM UTC 24 189275190 ps
T2540 /workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/81.xbar_smoke_zero_delays.3297826594 Sep 04 07:08:31 PM UTC 24 Sep 04 07:08:40 PM UTC 24 47026347 ps
T2541 /workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/80.xbar_error_and_unmapped_addr.2394272452 Sep 04 07:08:08 PM UTC 24 Sep 04 07:08:40 PM UTC 24 637761673 ps
T2542 /workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/80.xbar_unmapped_addr.3473968733 Sep 04 07:08:07 PM UTC 24 Sep 04 07:09:02 PM UTC 24 942869940 ps
T2543 /workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/80.xbar_same_source.2792111700 Sep 04 07:08:02 PM UTC 24 Sep 04 07:09:05 PM UTC 24 2611824588 ps
T2544 /workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/73.xbar_random_slow_rsp.2539990570 Sep 04 07:00:10 PM UTC 24 Sep 04 07:09:05 PM UTC 24 37476364355 ps
T2545 /workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/80.xbar_smoke_large_delays.2907767034 Sep 04 07:07:27 PM UTC 24 Sep 04 07:09:08 PM UTC 24 9219393773 ps
T2546 /workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/80.xbar_error_random.2299814203 Sep 04 07:08:05 PM UTC 24 Sep 04 07:09:16 PM UTC 24 1828554195 ps
T2547 /workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/80.xbar_smoke_slow_rsp.3904890221 Sep 04 07:07:37 PM UTC 24 Sep 04 07:09:19 PM UTC 24 5632267350 ps
T2548 /workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/62.xbar_access_same_device_slow_rsp.1550533258 Sep 04 06:48:02 PM UTC 24 Sep 04 07:09:21 PM UTC 24 81565728862 ps
T2549 /workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/81.xbar_random_zero_delays.1005405735 Sep 04 07:08:47 PM UTC 24 Sep 04 07:09:29 PM UTC 24 353528262 ps
T2550 /workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/70.xbar_stress_all_with_rand_reset.2437889859 Sep 04 06:57:27 PM UTC 24 Sep 04 07:09:31 PM UTC 24 15693574362 ps
T2551 /workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/79.xbar_stress_all_with_error.1015479669 Sep 04 07:07:10 PM UTC 24 Sep 04 07:09:35 PM UTC 24 2550731212 ps
T2552 /workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/81.xbar_random.360831475 Sep 04 07:08:47 PM UTC 24 Sep 04 07:09:37 PM UTC 24 480011399 ps
T2553 /workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/77.xbar_stress_all_with_error.484539458 Sep 04 07:05:01 PM UTC 24 Sep 04 07:09:42 PM UTC 24 4292657440 ps
T2554 /workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/68.xbar_random_slow_rsp.3398879481 Sep 04 06:54:36 PM UTC 24 Sep 04 07:09:45 PM UTC 24 57632013022 ps
T2555 /workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/80.xbar_access_same_device.2347415086 Sep 04 07:07:56 PM UTC 24 Sep 04 07:09:52 PM UTC 24 3388877319 ps
T2556 /workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/81.xbar_smoke_large_delays.3372334738 Sep 04 07:08:33 PM UTC 24 Sep 04 07:09:55 PM UTC 24 7280300023 ps
T2557 /workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/70.xbar_access_same_device_slow_rsp.2727889361 Sep 04 06:57:07 PM UTC 24 Sep 04 07:09:58 PM UTC 24 49369304619 ps
T2558 /workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/82.xbar_smoke.1626337336 Sep 04 07:09:57 PM UTC 24 Sep 04 07:10:07 PM UTC 24 48822159 ps
T2559 /workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/82.xbar_smoke_zero_delays.1490701086 Sep 04 07:09:59 PM UTC 24 Sep 04 07:10:10 PM UTC 24 55052268 ps
T2560 /workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/81.xbar_unmapped_addr.1518125901 Sep 04 07:09:35 PM UTC 24 Sep 04 07:10:10 PM UTC 24 622691869 ps
T2561 /workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/81.xbar_error_and_unmapped_addr.1134511235 Sep 04 07:09:37 PM UTC 24 Sep 04 07:10:13 PM UTC 24 926989036 ps
T2562 /workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/67.xbar_random_large_delays.1392570583 Sep 04 06:53:31 PM UTC 24 Sep 04 07:10:14 PM UTC 24 107923708177 ps
T2563 /workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/81.xbar_smoke_slow_rsp.574253463 Sep 04 07:08:36 PM UTC 24 Sep 04 07:10:30 PM UTC 24 5096473543 ps
T2564 /workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/82.xbar_random_zero_delays.788770579 Sep 04 07:10:11 PM UTC 24 Sep 04 07:10:36 PM UTC 24 208625437 ps
T2565 /workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/81.xbar_same_source.373739593 Sep 04 07:09:12 PM UTC 24 Sep 04 07:10:36 PM UTC 24 2763238714 ps
T2566 /workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/81.xbar_error_random.2881286649 Sep 04 07:09:33 PM UTC 24 Sep 04 07:10:43 PM UTC 24 2311661922 ps
T2567 /workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/82.xbar_access_same_device.3574916291 Sep 04 07:10:28 PM UTC 24 Sep 04 07:10:43 PM UTC 24 261251508 ps
T2568 /workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/76.xbar_stress_all_with_error.1416840308 Sep 04 07:04:07 PM UTC 24 Sep 04 07:10:46 PM UTC 24 11589904495 ps
T2569 /workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/82.xbar_same_source.4058078503 Sep 04 07:10:36 PM UTC 24 Sep 04 07:11:00 PM UTC 24 282678878 ps
T2570 /workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/82.xbar_error_and_unmapped_addr.16994329 Sep 04 07:10:38 PM UTC 24 Sep 04 07:11:04 PM UTC 24 164230511 ps
T2571 /workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/82.xbar_stress_all.2800200261 Sep 04 07:10:59 PM UTC 24 Sep 04 07:11:12 PM UTC 24 137609052 ps
T2572 /workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/80.xbar_stress_all.1922022357 Sep 04 07:08:19 PM UTC 24 Sep 04 07:11:20 PM UTC 24 6062953039 ps
T637 /workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/75.xbar_stress_all_with_reset_error.1598665814 Sep 04 07:03:00 PM UTC 24 Sep 04 07:11:22 PM UTC 24 10747073804 ps
T2573 /workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/79.xbar_stress_all_with_reset_error.2442739423 Sep 04 07:07:18 PM UTC 24 Sep 04 07:11:23 PM UTC 24 4512371852 ps
T2574 /workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/77.xbar_stress_all_with_rand_reset.1792772716 Sep 04 07:05:01 PM UTC 24 Sep 04 07:11:23 PM UTC 24 3236461817 ps
T2575 /workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/82.xbar_unmapped_addr.1223433410 Sep 04 07:10:41 PM UTC 24 Sep 04 07:11:24 PM UTC 24 830485352 ps
T2576 /workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/75.xbar_random_slow_rsp.1548678050 Sep 04 07:02:16 PM UTC 24 Sep 04 07:11:24 PM UTC 24 42499528952 ps
T2577 /workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/82.xbar_smoke_slow_rsp.1644486048 Sep 04 07:10:03 PM UTC 24 Sep 04 07:11:26 PM UTC 24 5111159960 ps
T2578 /workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/83.xbar_smoke_zero_delays.987911398 Sep 04 07:11:18 PM UTC 24 Sep 04 07:11:26 PM UTC 24 39803915 ps
T2579 /workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/83.xbar_smoke.129915856 Sep 04 07:11:16 PM UTC 24 Sep 04 07:11:27 PM UTC 24 166846954 ps
T2580 /workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/79.xbar_stress_all.4112767987 Sep 04 07:07:09 PM UTC 24 Sep 04 07:11:27 PM UTC 24 3702974545 ps
T2581 /workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/81.xbar_access_same_device.3398553758 Sep 04 07:09:10 PM UTC 24 Sep 04 07:11:29 PM UTC 24 3704260481 ps
T2582 /workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/82.xbar_random.3545969568 Sep 04 07:10:11 PM UTC 24 Sep 04 07:11:32 PM UTC 24 2511659872 ps
T2583 /workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/80.xbar_stress_all_with_rand_reset.1153616669 Sep 04 07:08:20 PM UTC 24 Sep 04 07:11:38 PM UTC 24 1037901323 ps
T2584 /workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/82.xbar_error_random.1956903702 Sep 04 07:10:38 PM UTC 24 Sep 04 07:11:40 PM UTC 24 2193128246 ps
T2585 /workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/81.xbar_random_large_delays.2429124426 Sep 04 07:09:01 PM UTC 24 Sep 04 07:11:52 PM UTC 24 14421286107 ps
T2586 /workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/81.xbar_stress_all_with_reset_error.915669410 Sep 04 07:09:51 PM UTC 24 Sep 04 07:11:52 PM UTC 24 206388237 ps
T2587 /workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/78.xbar_stress_all_with_reset_error.4102943565 Sep 04 07:06:31 PM UTC 24 Sep 04 07:11:54 PM UTC 24 2388094492 ps
T2588 /workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/82.xbar_smoke_large_delays.3131400290 Sep 04 07:10:05 PM UTC 24 Sep 04 07:11:55 PM UTC 24 8865403303 ps
T2589 /workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/83.xbar_random.259618036 Sep 04 07:11:40 PM UTC 24 Sep 04 07:11:57 PM UTC 24 232969333 ps
T2590 /workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/83.xbar_error_and_unmapped_addr.700096753 Sep 04 07:11:52 PM UTC 24 Sep 04 07:12:01 PM UTC 24 112647326 ps
T2591 /workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/83.xbar_same_source.2042872435 Sep 04 07:11:53 PM UTC 24 Sep 04 07:12:09 PM UTC 24 195274611 ps
T2592 /workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/83.xbar_access_same_device.647174217 Sep 04 07:11:52 PM UTC 24 Sep 04 07:12:11 PM UTC 24 252322575 ps
T2593 /workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/64.xbar_access_same_device_slow_rsp.3152691175 Sep 04 06:50:43 PM UTC 24 Sep 04 07:12:20 PM UTC 24 78997683739 ps
T2594 /workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/84.xbar_smoke.3002100702 Sep 04 07:12:10 PM UTC 24 Sep 04 07:12:21 PM UTC 24 134861739 ps
T2595 /workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/77.xbar_random_slow_rsp.3693043601 Sep 04 07:04:40 PM UTC 24 Sep 04 07:12:21 PM UTC 24 30551220980 ps
T2596 /workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/84.xbar_smoke_zero_delays.671973894 Sep 04 07:12:20 PM UTC 24 Sep 04 07:12:31 PM UTC 24 55724181 ps
T2597 /workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/83.xbar_random_zero_delays.1337366737 Sep 04 07:11:48 PM UTC 24 Sep 04 07:12:33 PM UTC 24 549078023 ps
T2598 /workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/83.xbar_unmapped_addr.713401339 Sep 04 07:11:55 PM UTC 24 Sep 04 07:12:35 PM UTC 24 735088374 ps
T2599 /workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/80.xbar_stress_all_with_error.3372017312 Sep 04 07:08:18 PM UTC 24 Sep 04 07:12:43 PM UTC 24 9467464363 ps
T2600 /workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/80.xbar_stress_all_with_reset_error.1016755987 Sep 04 07:08:17 PM UTC 24 Sep 04 07:12:49 PM UTC 24 3085383026 ps
T2601 /workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/83.xbar_smoke_large_delays.1299852164 Sep 04 07:11:29 PM UTC 24 Sep 04 07:12:54 PM UTC 24 8746742430 ps
T2602 /workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/84.xbar_random.2457234541 Sep 04 07:12:21 PM UTC 24 Sep 04 07:12:55 PM UTC 24 1074697657 ps
T2603 /workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/70.xbar_random_large_delays.694916976 Sep 04 06:56:53 PM UTC 24 Sep 04 07:12:56 PM UTC 24 89098302573 ps
T2604 /workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/83.xbar_error_random.2221611237 Sep 04 07:11:54 PM UTC 24 Sep 04 07:12:57 PM UTC 24 1770995078 ps
T2605 /workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/83.xbar_smoke_slow_rsp.2565913192 Sep 04 07:11:31 PM UTC 24 Sep 04 07:13:02 PM UTC 24 6281927015 ps
T2606 /workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/84.xbar_error_random.2163969451 Sep 04 07:12:50 PM UTC 24 Sep 04 07:13:04 PM UTC 24 107170106 ps
T2607 /workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/84.xbar_random_zero_delays.2434953998 Sep 04 07:12:29 PM UTC 24 Sep 04 07:13:07 PM UTC 24 527243279 ps
T2608 /workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/83.xbar_stress_all.2879851699 Sep 04 07:11:53 PM UTC 24 Sep 04 07:13:08 PM UTC 24 713612309 ps
T2609 /workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/74.xbar_random_large_delays.143611771 Sep 04 07:00:51 PM UTC 24 Sep 04 07:13:10 PM UTC 24 75675771780 ps
T2610 /workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/82.xbar_stress_all_with_reset_error.3047992187 Sep 04 07:11:13 PM UTC 24 Sep 04 07:13:15 PM UTC 24 1022879270 ps
T2611 /workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/74.xbar_stress_all_with_rand_reset.2503793826 Sep 04 07:01:31 PM UTC 24 Sep 04 07:13:20 PM UTC 24 5638894502 ps
T2612 /workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/84.xbar_error_and_unmapped_addr.4268687422 Sep 04 07:13:03 PM UTC 24 Sep 04 07:13:21 PM UTC 24 123469342 ps
T2613 /workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/81.xbar_stress_all_with_rand_reset.3680439699 Sep 04 07:09:47 PM UTC 24 Sep 04 07:13:28 PM UTC 24 455066334 ps
T2614 /workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/84.xbar_smoke_large_delays.2923822750 Sep 04 07:12:19 PM UTC 24 Sep 04 07:13:31 PM UTC 24 8343236111 ps
T2615 /workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/75.xbar_random_large_delays.4073981464 Sep 04 07:02:19 PM UTC 24 Sep 04 07:13:35 PM UTC 24 71164043991 ps
T2616 /workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/85.xbar_smoke_zero_delays.855900290 Sep 04 07:13:25 PM UTC 24 Sep 04 07:13:36 PM UTC 24 49947818 ps
T2617 /workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/85.xbar_smoke.1795213183 Sep 04 07:13:23 PM UTC 24 Sep 04 07:13:36 PM UTC 24 228169051 ps
T2618 /workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/84.xbar_access_same_device.3494213625 Sep 04 07:12:38 PM UTC 24 Sep 04 07:13:41 PM UTC 24 1821510753 ps
T2619 /workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/79.xbar_stress_all_with_rand_reset.2275817346 Sep 04 07:07:09 PM UTC 24 Sep 04 07:13:43 PM UTC 24 3022310228 ps
T2620 /workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/84.xbar_unmapped_addr.679940327 Sep 04 07:13:02 PM UTC 24 Sep 04 07:13:44 PM UTC 24 1047229472 ps
T2621 /workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/83.xbar_stress_all_with_reset_error.2510380947 Sep 04 07:12:07 PM UTC 24 Sep 04 07:13:55 PM UTC 24 2688407103 ps
T2622 /workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/83.xbar_stress_all_with_error.2385764894 Sep 04 07:12:00 PM UTC 24 Sep 04 07:13:58 PM UTC 24 2638838839 ps
T2623 /workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/84.xbar_smoke_slow_rsp.620842334 Sep 04 07:12:23 PM UTC 24 Sep 04 07:14:01 PM UTC 24 5440849556 ps
T2624 /workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/84.xbar_same_source.1766963872 Sep 04 07:12:52 PM UTC 24 Sep 04 07:14:04 PM UTC 24 2268800576 ps
T2625 /workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/85.xbar_error_random.1820368766 Sep 04 07:13:59 PM UTC 24 Sep 04 07:14:17 PM UTC 24 521170547 ps
T2626 /workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/86.xbar_smoke.552296221 Sep 04 07:14:14 PM UTC 24 Sep 04 07:14:24 PM UTC 24 47274814 ps
T2627 /workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/85.xbar_error_and_unmapped_addr.1896864380 Sep 04 07:14:04 PM UTC 24 Sep 04 07:14:25 PM UTC 24 167144002 ps
T2628 /workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/85.xbar_smoke_slow_rsp.1733440276 Sep 04 07:13:31 PM UTC 24 Sep 04 07:14:25 PM UTC 24 3646670863 ps
T2629 /workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/85.xbar_same_source.1520104196 Sep 04 07:13:54 PM UTC 24 Sep 04 07:14:28 PM UTC 24 1389182833 ps
T2630 /workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/78.xbar_stress_all_with_error.3677953143 Sep 04 07:06:27 PM UTC 24 Sep 04 07:14:30 PM UTC 24 16383276151 ps
T2631 /workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/85.xbar_unmapped_addr.2838019827 Sep 04 07:14:01 PM UTC 24 Sep 04 07:14:30 PM UTC 24 502040123 ps
T2632 /workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/84.xbar_stress_all.2563453114 Sep 04 07:13:05 PM UTC 24 Sep 04 07:14:34 PM UTC 24 842755215 ps
T2633 /workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/86.xbar_smoke_zero_delays.1933409434 Sep 04 07:14:25 PM UTC 24 Sep 04 07:14:35 PM UTC 24 47107574 ps
T2634 /workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/85.xbar_random_zero_delays.1124796215 Sep 04 07:13:36 PM UTC 24 Sep 04 07:14:37 PM UTC 24 595562742 ps
T2635 /workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/85.xbar_random.2349691613 Sep 04 07:13:34 PM UTC 24 Sep 04 07:14:37 PM UTC 24 1775947004 ps
T2636 /workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/85.xbar_stress_all_with_rand_reset.1982102420 Sep 04 07:14:05 PM UTC 24 Sep 04 07:14:41 PM UTC 24 65211758 ps
T2637 /workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/73.xbar_random_large_delays.3888471087 Sep 04 07:00:12 PM UTC 24 Sep 04 07:14:51 PM UTC 24 84329015810 ps
T2638 /workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/85.xbar_stress_all_with_reset_error.745551281 Sep 04 07:14:13 PM UTC 24 Sep 04 07:14:57 PM UTC 24 105963028 ps
T2639 /workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/86.xbar_random_zero_delays.3146510570 Sep 04 07:14:45 PM UTC 24 Sep 04 07:15:07 PM UTC 24 200312371 ps
T2640 /workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/85.xbar_smoke_large_delays.1168875641 Sep 04 07:13:26 PM UTC 24 Sep 04 07:15:08 PM UTC 24 7363604287 ps
T2641 /workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/86.xbar_error_random.39390355 Sep 04 07:14:57 PM UTC 24 Sep 04 07:15:21 PM UTC 24 175301315 ps
T2642 /workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/83.xbar_stress_all_with_rand_reset.350325717 Sep 04 07:11:58 PM UTC 24 Sep 04 07:15:22 PM UTC 24 1222233738 ps
T2643 /workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/81.xbar_stress_all_with_error.3723069283 Sep 04 07:09:51 PM UTC 24 Sep 04 07:15:36 PM UTC 24 9796386437 ps
T2644 /workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/87.xbar_smoke.3740098416 Sep 04 07:15:25 PM UTC 24 Sep 04 07:15:38 PM UTC 24 201380884 ps
T2645 /workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/87.xbar_smoke_zero_delays.1988977458 Sep 04 07:15:36 PM UTC 24 Sep 04 07:15:43 PM UTC 24 37237440 ps
T2646 /workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/86.xbar_smoke_large_delays.3800624164 Sep 04 07:14:28 PM UTC 24 Sep 04 07:15:50 PM UTC 24 7112106890 ps
T2647 /workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/86.xbar_unmapped_addr.901329661 Sep 04 07:14:58 PM UTC 24 Sep 04 07:15:52 PM UTC 24 1383434951 ps
T2648 /workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/86.xbar_access_same_device.44151106 Sep 04 07:14:56 PM UTC 24 Sep 04 07:15:54 PM UTC 24 794511859 ps
T2649 /workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/86.xbar_random.3259530828 Sep 04 07:14:34 PM UTC 24 Sep 04 07:15:55 PM UTC 24 2212375768 ps
T2650 /workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/86.xbar_stress_all.2127677186 Sep 04 07:15:05 PM UTC 24 Sep 04 07:16:04 PM UTC 24 909020257 ps
T2651 /workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/87.xbar_random.4071298388 Sep 04 07:15:54 PM UTC 24 Sep 04 07:16:06 PM UTC 24 92254152 ps
T2652 /workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/85.xbar_access_same_device.1022402459 Sep 04 07:13:48 PM UTC 24 Sep 04 07:16:08 PM UTC 24 3047896808 ps
T2653 /workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/86.xbar_error_and_unmapped_addr.3512813374 Sep 04 07:15:02 PM UTC 24 Sep 04 07:16:08 PM UTC 24 1185360237 ps
T2654 /workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/86.xbar_same_source.3342910587 Sep 04 07:15:00 PM UTC 24 Sep 04 07:16:14 PM UTC 24 2408195585 ps
T2655 /workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/82.xbar_stress_all_with_error.3561009995 Sep 04 07:11:05 PM UTC 24 Sep 04 07:16:20 PM UTC 24 9007359524 ps
T2656 /workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/81.xbar_random_slow_rsp.3486474169 Sep 04 07:09:03 PM UTC 24 Sep 04 07:16:26 PM UTC 24 23480324951 ps
T2657 /workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/86.xbar_smoke_slow_rsp.4278533276 Sep 04 07:14:33 PM UTC 24 Sep 04 07:16:31 PM UTC 24 5525247459 ps
T2658 /workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/87.xbar_random_zero_delays.1997148716 Sep 04 07:16:08 PM UTC 24 Sep 04 07:16:32 PM UTC 24 179294146 ps
T2659 /workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/85.xbar_stress_all_with_error.1261484346 Sep 04 07:14:12 PM UTC 24 Sep 04 07:16:34 PM UTC 24 3572714312 ps
T2660 /workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/86.xbar_access_same_device_slow_rsp.2619954143 Sep 04 07:14:58 PM UTC 24 Sep 04 07:16:35 PM UTC 24 5621758448 ps
T2661 /workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/71.xbar_random_large_delays.3676032755 Sep 04 06:58:01 PM UTC 24 Sep 04 07:16:39 PM UTC 24 97630369351 ps
T2662 /workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/84.xbar_stress_all_with_error.4016435232 Sep 04 07:13:15 PM UTC 24 Sep 04 07:16:41 PM UTC 24 6843831438 ps
T2663 /workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/88.xbar_smoke_zero_delays.3931479688 Sep 04 07:17:00 PM UTC 24 Sep 04 07:17:10 PM UTC 24 54773015 ps
T2664 /workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/60.xbar_access_same_device_slow_rsp.2196881933 Sep 04 06:45:13 PM UTC 24 Sep 04 07:16:46 PM UTC 24 128187376887 ps
T2665 /workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/87.xbar_error_and_unmapped_addr.2841705778 Sep 04 07:16:37 PM UTC 24 Sep 04 07:16:50 PM UTC 24 138867552 ps
T2666 /workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/87.xbar_smoke_slow_rsp.2368007292 Sep 04 07:15:53 PM UTC 24 Sep 04 07:16:50 PM UTC 24 3615365908 ps
T2667 /workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/87.xbar_error_random.1534179977 Sep 04 07:16:27 PM UTC 24 Sep 04 07:16:54 PM UTC 24 334721464 ps
T2668 /workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/87.xbar_smoke_large_delays.234300087 Sep 04 07:15:39 PM UTC 24 Sep 04 07:16:57 PM UTC 24 5335391777 ps
T2669 /workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/87.xbar_same_source.1696085531 Sep 04 07:16:26 PM UTC 24 Sep 04 07:17:04 PM UTC 24 1295263353 ps
T2670 /workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/88.xbar_smoke.1126602286 Sep 04 07:16:57 PM UTC 24 Sep 04 07:17:09 PM UTC 24 201191885 ps
T2671 /workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/82.xbar_random_large_delays.2304722450 Sep 04 07:10:21 PM UTC 24 Sep 04 07:17:10 PM UTC 24 45223821539 ps
T2672 /workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/87.xbar_unmapped_addr.3808055457 Sep 04 07:16:36 PM UTC 24 Sep 04 07:17:13 PM UTC 24 612519961 ps
T2673 /workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/87.xbar_access_same_device.2029441493 Sep 04 07:16:19 PM UTC 24 Sep 04 07:17:15 PM UTC 24 1523682175 ps
T2674 /workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/88.xbar_random.3414565377 Sep 04 07:17:04 PM UTC 24 Sep 04 07:17:22 PM UTC 24 175621126 ps
T2675 /workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/87.xbar_random_large_delays.222960525 Sep 04 07:16:11 PM UTC 24 Sep 04 07:17:26 PM UTC 24 5640870105 ps
T2676 /workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/77.xbar_random_large_delays.2659280963 Sep 04 07:04:31 PM UTC 24 Sep 04 07:17:30 PM UTC 24 73143331233 ps
T2677 /workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/88.xbar_random_zero_delays.1186710541 Sep 04 07:17:12 PM UTC 24 Sep 04 07:17:40 PM UTC 24 235373401 ps
T2678 /workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/87.xbar_stress_all_with_error.739085915 Sep 04 07:16:42 PM UTC 24 Sep 04 07:17:56 PM UTC 24 1218875010 ps
T2679 /workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/80.xbar_random_slow_rsp.2561393331 Sep 04 07:07:53 PM UTC 24 Sep 04 07:18:00 PM UTC 24 35150938824 ps
T2680 /workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/88.xbar_error_and_unmapped_addr.357873909 Sep 04 07:17:40 PM UTC 24 Sep 04 07:18:00 PM UTC 24 332681890 ps
T2681 /workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/89.xbar_smoke_zero_delays.77502194 Sep 04 07:17:52 PM UTC 24 Sep 04 07:18:02 PM UTC 24 43472430 ps
T2682 /workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/89.xbar_smoke.715842921 Sep 04 07:17:53 PM UTC 24 Sep 04 07:18:02 PM UTC 24 182703913 ps
T2683 /workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/88.xbar_same_source.3739085331 Sep 04 07:17:25 PM UTC 24 Sep 04 07:18:02 PM UTC 24 554796695 ps
T2684 /workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/88.xbar_error_random.1636105971 Sep 04 07:17:27 PM UTC 24 Sep 04 07:18:04 PM UTC 24 1127758700 ps
T2685 /workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/88.xbar_unmapped_addr.2601309592 Sep 04 07:17:35 PM UTC 24 Sep 04 07:18:06 PM UTC 24 507189117 ps
T2686 /workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/88.xbar_random_slow_rsp.1767088925 Sep 04 07:17:16 PM UTC 24 Sep 04 07:18:07 PM UTC 24 2895240570 ps
T2687 /workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/82.xbar_stress_all_with_rand_reset.2367521635 Sep 04 07:11:08 PM UTC 24 Sep 04 07:18:08 PM UTC 24 4506329461 ps
T2688 /workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/86.xbar_stress_all_with_rand_reset.401904497 Sep 04 07:15:06 PM UTC 24 Sep 04 07:18:16 PM UTC 24 2834561168 ps
T2689 /workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/88.xbar_access_same_device.472975617 Sep 04 07:17:23 PM UTC 24 Sep 04 07:18:33 PM UTC 24 807380227 ps
T2690 /workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/88.xbar_smoke_large_delays.2691352013 Sep 04 07:17:02 PM UTC 24 Sep 04 07:18:36 PM UTC 24 6796432995 ps
T2691 /workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/87.xbar_stress_all_with_reset_error.3050827559 Sep 04 07:16:49 PM UTC 24 Sep 04 07:18:36 PM UTC 24 368401270 ps
T2692 /workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/88.xbar_smoke_slow_rsp.1402866235 Sep 04 07:17:06 PM UTC 24 Sep 04 07:18:40 PM UTC 24 5851528827 ps
T2693 /workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/83.xbar_random_large_delays.3984383563 Sep 04 07:11:53 PM UTC 24 Sep 04 07:18:42 PM UTC 24 42366916478 ps
T2694 /workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/76.xbar_random_large_delays.2527279023 Sep 04 07:03:27 PM UTC 24 Sep 04 07:18:47 PM UTC 24 94325120869 ps
T2695 /workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/87.xbar_random_slow_rsp.3058492580 Sep 04 07:16:11 PM UTC 24 Sep 04 07:18:48 PM UTC 24 11169036420 ps
T2696 /workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/86.xbar_stress_all_with_reset_error.1636176650 Sep 04 07:15:17 PM UTC 24 Sep 04 07:18:50 PM UTC 24 1256566965 ps
T2697 /workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/89.xbar_smoke_large_delays.899733527 Sep 04 07:17:59 PM UTC 24 Sep 04 07:18:51 PM UTC 24 4983995989 ps
T2698 /workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/85.xbar_random_slow_rsp.143518274 Sep 04 07:13:41 PM UTC 24 Sep 04 07:18:55 PM UTC 24 19939926027 ps
T2699 /workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/89.xbar_error_and_unmapped_addr.2758205789 Sep 04 07:18:41 PM UTC 24 Sep 04 07:19:02 PM UTC 24 152980044 ps
T2700 /workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/89.xbar_unmapped_addr.1368343507 Sep 04 07:18:37 PM UTC 24 Sep 04 07:19:15 PM UTC 24 267524588 ps
T2701 /workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/89.xbar_random_zero_delays.930076730 Sep 04 07:18:30 PM UTC 24 Sep 04 07:19:17 PM UTC 24 485832225 ps
T2702 /workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/89.xbar_error_random.387534604 Sep 04 07:18:34 PM UTC 24 Sep 04 07:19:19 PM UTC 24 463503841 ps
T2703 /workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/89.xbar_same_source.777583616 Sep 04 07:18:34 PM UTC 24 Sep 04 07:19:20 PM UTC 24 1630691071 ps
T2704 /workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/90.xbar_smoke.3485151783 Sep 04 07:19:10 PM UTC 24 Sep 04 07:19:21 PM UTC 24 219456381 ps
T2705 /workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/90.xbar_smoke_zero_delays.3743592719 Sep 04 07:19:13 PM UTC 24 Sep 04 07:19:22 PM UTC 24 46875931 ps
T2706 /workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/88.xbar_stress_all.1785822612 Sep 04 07:17:36 PM UTC 24 Sep 04 07:19:32 PM UTC 24 1809470871 ps
T2707 /workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/90.xbar_random.4292713140 Sep 04 07:19:23 PM UTC 24 Sep 04 07:19:35 PM UTC 24 151084454 ps
T2708 /workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/89.xbar_random.146077816 Sep 04 07:18:28 PM UTC 24 Sep 04 07:19:38 PM UTC 24 1789192234 ps
T2709 /workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/89.xbar_stress_all_with_reset_error.1572541956 Sep 04 07:19:06 PM UTC 24 Sep 04 07:19:40 PM UTC 24 146593510 ps
T2710 /workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/85.xbar_stress_all.563250527 Sep 04 07:14:07 PM UTC 24 Sep 04 07:19:40 PM UTC 24 8406609862 ps
T2711 /workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/89.xbar_smoke_slow_rsp.1931294346 Sep 04 07:18:12 PM UTC 24 Sep 04 07:19:45 PM UTC 24 6109025041 ps
T2712 /workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/89.xbar_access_same_device.812352866 Sep 04 07:18:30 PM UTC 24 Sep 04 07:19:58 PM UTC 24 2199603146 ps
T2713 /workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/90.xbar_random_zero_delays.70801947 Sep 04 07:19:22 PM UTC 24 Sep 04 07:20:01 PM UTC 24 459645482 ps
T2714 /workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/90.xbar_access_same_device.144721090 Sep 04 07:19:48 PM UTC 24 Sep 04 07:20:05 PM UTC 24 81018178 ps
T2715 /workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/90.xbar_error_random.65985158 Sep 04 07:19:52 PM UTC 24 Sep 04 07:20:12 PM UTC 24 615927014 ps
T2716 /workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/69.xbar_access_same_device_slow_rsp.903266253 Sep 04 06:55:56 PM UTC 24 Sep 04 07:20:18 PM UTC 24 104813191076 ps
T2717 /workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/90.xbar_error_and_unmapped_addr.3085840364 Sep 04 07:19:52 PM UTC 24 Sep 04 07:20:20 PM UTC 24 483994528 ps
T2718 /workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/91.xbar_smoke.2023504210 Sep 04 07:20:10 PM UTC 24 Sep 04 07:20:21 PM UTC 24 54932606 ps
T2719 /workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/90.xbar_unmapped_addr.1293948037 Sep 04 07:19:51 PM UTC 24 Sep 04 07:20:26 PM UTC 24 243413199 ps
T2720 /workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/91.xbar_smoke_zero_delays.1807609825 Sep 04 07:20:17 PM UTC 24 Sep 04 07:20:27 PM UTC 24 46498783 ps
T2721 /workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/89.xbar_stress_all_with_rand_reset.1625590180 Sep 04 07:19:06 PM UTC 24 Sep 04 07:20:30 PM UTC 24 190307867 ps
T2722 /workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/90.xbar_smoke_large_delays.3901805597 Sep 04 07:19:19 PM UTC 24 Sep 04 07:20:36 PM UTC 24 8315686419 ps
T2723 /workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/90.xbar_random_slow_rsp.3049207805 Sep 04 07:19:34 PM UTC 24 Sep 04 07:20:43 PM UTC 24 2905502244 ps
T2724 /workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/90.xbar_same_source.3089432279 Sep 04 07:19:50 PM UTC 24 Sep 04 07:20:44 PM UTC 24 1455193513 ps
T2725 /workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/88.xbar_random_large_delays.3788292124 Sep 04 07:17:11 PM UTC 24 Sep 04 07:20:49 PM UTC 24 21385995393 ps
T2726 /workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/81.xbar_stress_all.2569246745 Sep 04 07:09:38 PM UTC 24 Sep 04 07:20:51 PM UTC 24 19463833472 ps
T2727 /workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/91.xbar_random_zero_delays.518239931 Sep 04 07:20:40 PM UTC 24 Sep 04 07:20:57 PM UTC 24 102292546 ps
T2728 /workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/74.xbar_access_same_device_slow_rsp.1772986582 Sep 04 07:01:12 PM UTC 24 Sep 04 07:20:59 PM UTC 24 87183811592 ps
T2729 /workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/86.xbar_stress_all_with_error.925309469 Sep 04 07:15:10 PM UTC 24 Sep 04 07:21:02 PM UTC 24 11411791611 ps
T2730 /workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/88.xbar_stress_all_with_error.174375225 Sep 04 07:17:46 PM UTC 24 Sep 04 07:21:14 PM UTC 24 7101817076 ps
T2731 /workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/89.xbar_stress_all_with_error.2238555213 Sep 04 07:19:07 PM UTC 24 Sep 04 07:21:15 PM UTC 24 1903503951 ps
T2732 /workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/90.xbar_access_same_device_slow_rsp.2945719341 Sep 04 07:19:48 PM UTC 24 Sep 04 07:21:20 PM UTC 24 3774435774 ps
T2733 /workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/72.xbar_access_same_device_slow_rsp.3872540086 Sep 04 06:59:01 PM UTC 24 Sep 04 07:21:21 PM UTC 24 86880887301 ps
T2734 /workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/84.xbar_random_large_delays.201114727 Sep 04 07:12:34 PM UTC 24 Sep 04 07:21:21 PM UTC 24 40659571145 ps
T2735 /workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/91.xbar_unmapped_addr.2154613953 Sep 04 07:21:03 PM UTC 24 Sep 04 07:21:24 PM UTC 24 382275696 ps
T2736 /workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/91.xbar_error_random.2668487659 Sep 04 07:20:58 PM UTC 24 Sep 04 07:21:27 PM UTC 24 576848407 ps
T2737 /workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/91.xbar_same_source.749022010 Sep 04 07:20:56 PM UTC 24 Sep 04 07:21:30 PM UTC 24 1141363803 ps
T2738 /workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/84.xbar_random_slow_rsp.416978379 Sep 04 07:12:35 PM UTC 24 Sep 04 07:21:36 PM UTC 24 41021810797 ps
T2739 /workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/92.xbar_smoke_zero_delays.628601463 Sep 04 07:21:27 PM UTC 24 Sep 04 07:21:37 PM UTC 24 43630566 ps
T2740 /workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/92.xbar_smoke.1899081708 Sep 04 07:21:28 PM UTC 24 Sep 04 07:21:37 PM UTC 24 176761531 ps
T2741 /workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/91.xbar_random.1192197802 Sep 04 07:20:37 PM UTC 24 Sep 04 07:21:37 PM UTC 24 1588218188 ps
T2742 /workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/91.xbar_access_same_device.2722305792 Sep 04 07:20:50 PM UTC 24 Sep 04 07:21:37 PM UTC 24 1031594061 ps
T2743 /workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/91.xbar_error_and_unmapped_addr.2446882176 Sep 04 07:21:11 PM UTC 24 Sep 04 07:21:43 PM UTC 24 575177236 ps
T2744 /workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/78.xbar_random_large_delays.608625760 Sep 04 07:05:21 PM UTC 24 Sep 04 07:21:43 PM UTC 24 92321791776 ps
T2745 /workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/87.xbar_stress_all_with_rand_reset.3969503457 Sep 04 07:16:35 PM UTC 24 Sep 04 07:21:50 PM UTC 24 2030461955 ps
T2746 /workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/89.xbar_access_same_device_slow_rsp.3912161685 Sep 04 07:18:35 PM UTC 24 Sep 04 07:21:51 PM UTC 24 11627357924 ps
T2747 /workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/75.xbar_access_same_device_slow_rsp.1122791716 Sep 04 07:02:24 PM UTC 24 Sep 04 07:21:52 PM UTC 24 77649638750 ps
T2748 /workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/90.xbar_smoke_slow_rsp.2461861606 Sep 04 07:19:21 PM UTC 24 Sep 04 07:21:55 PM UTC 24 6458686957 ps
T2749 /workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/97.xbar_smoke_zero_delays.3703498135 Sep 04 07:26:05 PM UTC 24 Sep 04 07:26:14 PM UTC 24 39587460 ps
T881 /workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/84.xbar_stress_all_with_reset_error.3761528414 Sep 04 07:13:23 PM UTC 24 Sep 04 07:21:59 PM UTC 24 5170998991 ps
T2750 /workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/91.xbar_smoke_large_delays.808171930 Sep 04 07:20:30 PM UTC 24 Sep 04 07:22:00 PM UTC 24 7687029105 ps
T2751 /workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/91.xbar_stress_all_with_rand_reset.1262736132 Sep 04 07:21:20 PM UTC 24 Sep 04 07:22:00 PM UTC 24 84153396 ps
T2752 /workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/92.xbar_error_random.648907262 Sep 04 07:21:58 PM UTC 24 Sep 04 07:22:09 PM UTC 24 130187740 ps
T2753 /workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/91.xbar_smoke_slow_rsp.3315466412 Sep 04 07:20:29 PM UTC 24 Sep 04 07:22:09 PM UTC 24 6429567879 ps
T2754 /workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/90.xbar_stress_all_with_error.4094728486 Sep 04 07:20:08 PM UTC 24 Sep 04 07:22:10 PM UTC 24 4018459009 ps
T2755 /workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/92.xbar_error_and_unmapped_addr.1862671934 Sep 04 07:22:00 PM UTC 24 Sep 04 07:22:10 PM UTC 24 37388497 ps
T2756 /workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/91.xbar_stress_all_with_error.4032838785 Sep 04 07:21:17 PM UTC 24 Sep 04 07:22:11 PM UTC 24 1044143876 ps
T2757 /workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/93.xbar_smoke_zero_delays.3767858781 Sep 04 07:22:16 PM UTC 24 Sep 04 07:22:25 PM UTC 24 44226872 ps
T2758 /workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/79.xbar_random_slow_rsp.1566574038 Sep 04 07:06:53 PM UTC 24 Sep 04 07:22:26 PM UTC 24 63540913524 ps
T2759 /workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/88.xbar_stress_all_with_rand_reset.2073637971 Sep 04 07:17:41 PM UTC 24 Sep 04 07:22:27 PM UTC 24 3344474110 ps
T2760 /workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/84.xbar_stress_all_with_rand_reset.3491098760 Sep 04 07:13:11 PM UTC 24 Sep 04 07:22:29 PM UTC 24 8548597391 ps
T2761 /workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/93.xbar_smoke.2210291213 Sep 04 07:22:19 PM UTC 24 Sep 04 07:22:32 PM UTC 24 210755166 ps
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